diff --git a/ci b/ci
index f0fba61d..528dc02b 160000
--- a/ci
+++ b/ci
@@ -1 +1 @@
-Subproject commit f0fba61d699a73f5f658bde40cbc8b7f6803d2c2
+Subproject commit 528dc02b27b9728a5049248539afeff7ffe0a5e7
diff --git a/src/arch/armv8/aarch32/inc/arch/subarch/sysregs.h b/src/arch/armv8/aarch32/inc/arch/subarch/sysregs.h
index 93cb8988..44c8eeff 100644
--- a/src/arch/armv8/aarch32/inc/arch/subarch/sysregs.h
+++ b/src/arch/armv8/aarch32/inc/arch/subarch/sysregs.h
@@ -40,7 +40,7 @@
     {                                                                                             \
         unsigned long long _temp, _tempH;                                                         \
         __asm__ volatile("mrrc p15, " #op1 ", %0, %1, " #crm "\n\r" : "=r"(_temp), "=r"(_tempH)); \
-        return ((_tempH << 32) | _temp);                                                          \
+        return ((_tempH << 32) | ((unsigned long)_temp));                                         \
     }                                                                                             \
     static inline void sysreg_##reg##_write(unsigned long long val)                               \
     {                                                                                             \
diff --git a/src/arch/riscv/inc/arch/csrs.h b/src/arch/riscv/inc/arch/csrs.h
index 9539028c..36072bfe 100644
--- a/src/arch/riscv/inc/arch/csrs.h
+++ b/src/arch/riscv/inc/arch/csrs.h
@@ -104,7 +104,7 @@
 #define SSTATUS_XS_DIRTY            (3ULL << SSTATUS_XS_OFF)
 #define SSTATUS_SUM                 (1ULL << 18)
 #define SSTATUS_MXR                 (1ULL << 19)
-#define SSTATUS_SD                  (1ULL << 63)
+#define SSTATUS_SD                  (1ULL << ((REGLEN * 8) - 1))
 
 #define SIE_USIE                    (1ULL << 0)
 #define SIE_SSIE                    (1ULL << 1)
diff --git a/src/arch/riscv/irqc/aia/imsic.c b/src/arch/riscv/irqc/aia/imsic.c
index bf27845b..06a9fa53 100644
--- a/src/arch/riscv/irqc/aia/imsic.c
+++ b/src/arch/riscv/irqc/aia/imsic.c
@@ -53,7 +53,7 @@ void imsic_init(void)
 void imsic_set_enbl(irqid_t intp_id)
 {
     csrs_siselect_write(IMSIC_EIE + imsic_eie_index(intp_id));
-    csrs_sireg_set(1ULL << imsic_eie_bit(intp_id));
+    csrs_sireg_set(1UL << imsic_eie_bit(intp_id));
 }
 
 bool imsic_get_pend(irqid_t intp_id)
@@ -65,7 +65,7 @@ bool imsic_get_pend(irqid_t intp_id)
 void imsic_clr_pend(irqid_t intp_id)
 {
     csrs_siselect_write(IMSIC_EIP + imsic_eie_index(intp_id));
-    csrs_sireg_clear(1ULL << imsic_eie_bit(intp_id));
+    csrs_sireg_clear(1UL << imsic_eie_bit(intp_id));
 }
 
 /**
@@ -77,7 +77,7 @@ void imsic_inject_pend(size_t guest_file, irqid_t intp_id)
     UNUSED_ARG(guest_file);
 
     csrs_vsiselect_write(IMSIC_EIP + imsic_eie_index(intp_id));
-    csrs_vsireg_clear(1ULL << imsic_eie_bit(intp_id));
+    csrs_vsireg_clear(1UL << imsic_eie_bit(intp_id));
 }
 
 void imsic_send_msi(cpuid_t target_cpu, irqid_t ipi_id)
diff --git a/src/arch/riscv/sbi.c b/src/arch/riscv/sbi.c
index a6699a2c..668717c8 100644
--- a/src/arch/riscv/sbi.c
+++ b/src/arch/riscv/sbi.c
@@ -404,7 +404,10 @@ static struct sbiret sbi_bao_handler(unsigned long fid)
 {
     struct sbiret ret;
 
-    ret.error = hypercall(fid);
+    // Any hypercall will always be successful from a purely SBI standpoint. A
+    // bao-specific hypercall code is returned as the value.
+    ret.error = SBI_SUCCESS;
+    ret.value = hypercall(fid);
 
     return ret;
 }
@@ -436,7 +439,7 @@ size_t sbi_vs_handler()
             break;
         default:
             WARNING("guest issued unsupport sbi extension call (%d)", extid);
-            ret.value = SBI_ERR_NOT_SUPPORTED;
+            ret.error = SBI_ERR_NOT_SUPPORTED;
     }
 
     vcpu_writereg(cpu()->vcpu, REG_A0, (unsigned long)ret.error);