From fb42590d5b23c1d22b793380298d85ac9eb440a0 Mon Sep 17 00:00:00 2001
From: Hussein Hazem <alhussein.abdelhamid@gmail.com>
Date: Mon, 14 Oct 2024 13:43:20 +0200
Subject: [PATCH] #29 optimize tx/rx fifo check

---
 src/can.rs | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/can.rs b/src/can.rs
index 41a9fec..7548006 100644
--- a/src/can.rs
+++ b/src/can.rs
@@ -124,10 +124,10 @@ impl<B: Transfer<u8>, CS: OutputPin, CLK: Clock> CanController for MCP2517<B, CS
         let fifo_status_reg = Self::fifo_status_register(FIFO_TX_INDEX);
 
         // Check if TX fifo is full
-        if blocking {
-            while !self.fifo_not_full(fifo_status_reg)? {}
-        } else if !self.fifo_not_full(fifo_status_reg)? {
-            return Err(Error::TxFifoFullErr);
+        while !self.fifo_not_full(fifo_status_reg)? {
+            if !blocking {
+                return Err(Error::TxFifoFullErr);
+            }
         }
 
         // make sure length of payload is consistent with CAN operation mode
@@ -165,10 +165,10 @@ impl<B: Transfer<u8>, CS: OutputPin, CLK: Clock> CanController for MCP2517<B, CS
         let fifo_status_reg = Self::fifo_status_register(FIFO_RX_INDEX);
 
         // Make sure RX fifo is not empty
-        if blocking {
-            while !self.fifo_not_empty(fifo_status_reg)? {}
-        } else if !self.fifo_not_empty(fifo_status_reg)? {
-            return Err(Error::RxFifoEmptyErr);
+        while !self.fifo_not_empty(fifo_status_reg)? {
+            if !blocking {
+                return Err(Error::RxFifoEmptyErr);
+            }
         }
 
         let user_address = self.read32(Self::fifo_user_address_register(FIFO_RX_INDEX))?;