From c801c74692c83db89c4baabef6211965c18ed44c Mon Sep 17 00:00:00 2001 From: "Travis F. Collins" Date: Fri, 27 Sep 2024 16:26:43 -0600 Subject: [PATCH] Fix example for new FPGA API Signed-off-by: Travis F. Collins --- examples/ad9081_rxtx_hmc7044.py | 1 + 1 file changed, 1 insertion(+) diff --git a/examples/ad9081_rxtx_hmc7044.py b/examples/ad9081_rxtx_hmc7044.py index 8e4edf0..0711c54 100644 --- a/examples/ad9081_rxtx_hmc7044.py +++ b/examples/ad9081_rxtx_hmc7044.py @@ -7,6 +7,7 @@ sys = adijif.system("ad9081", "hmc7044", "xilinx", vcxo, solver="CPLEX") sys.fpga.setup_by_dev_kit_name("zcu102") +sys.fpga.ref_clock_constraint = "Unconstrained" sys.fpga.sys_clk_select = "GTH34_SYSCLK_QPLL0" # Use faster QPLL sys.converter.clocking_option = "integrated_pll" sys.fpga.out_clk_select = "XCVR_PROGDIV_CLK" # force reference to be core clock rate