From 53ce9d0ffe23aa4112c597ce03c22b3c00bf0739 Mon Sep 17 00:00:00 2001 From: Anush Shetty Date: Thu, 21 Nov 2024 19:00:54 +0530 Subject: [PATCH] projects:ad405x_iio: Update ad405x project according to the latest driver changes 1. Sync up the code with latest DMA and PWM drivers 2. Add virtual COM support 3. Club the firmwares of AD4052 and AD4050 Signed-off-by: Anush Shetty --- projects/ad405x_iio/STM32/.extSettings | 4 +- projects/ad405x_iio/STM32/ad405x_iio.ioc | 330 +++++++++++++++++-- projects/ad405x_iio/app/ad405x_iio.c | 228 +++++++------ projects/ad405x_iio/app/ad405x_user_config.c | 1 - projects/ad405x_iio/app/app_config.h | 61 +--- projects/ad405x_iio/app/app_config_stm32.c | 60 ++-- projects/ad405x_iio/app/app_config_stm32.h | 7 +- 7 files changed, 468 insertions(+), 223 deletions(-) diff --git a/projects/ad405x_iio/STM32/.extSettings b/projects/ad405x_iio/STM32/.extSettings index e634feb5..90a7b9e6 100644 --- a/projects/ad405x_iio/STM32/.extSettings +++ b/projects/ad405x_iio/STM32/.extSettings @@ -16,11 +16,11 @@ app/libraries/no-OS/drivers/eeprom/24xx32a/=../../../libraries/no-OS/drivers/eep app/libraries/no-OS/drivers/adc/ad405x/=../../../libraries/no-OS/drivers/adc/ad405x/ad405x.c;../../../libraries/no-OS/drivers/adc/ad405x/ad405x.h; -app/libraries/no-OS/drivers/platform/stm32/=../../../libraries/no-OS/drivers/platform/stm32/stm32_delay.c;../../../libraries/no-OS/drivers/platform/stm32/stm32_gpio.c;../../../libraries/no-OS/drivers/platform/stm32/stm32_gpio.h;../../../libraries/no-OS/drivers/platform/stm32/stm32_gpio_irq.c;../../../libraries/no-OS/drivers/platform/stm32/stm32_gpio_irq.h;../../../libraries/no-OS/drivers/platform/stm32/stm32_spi.c;../../../libraries/no-OS/drivers/platform/stm32/stm32_spi.h;../../../libraries/no-OS/drivers/platform/stm32/stm32_i2c.c;../../../libraries/no-OS/drivers/platform/stm32/stm32_i2c.h;../../../libraries/no-OS/drivers/platform/stm32/stm32_uart.c;../../../libraries/no-OS/drivers/platform/stm32/stm32_uart.h;../../../libraries/no-OS/drivers/platform/stm32/stm32_irq.h;../../../libraries/no-OS/drivers/platform/stm32/stm32_irq.c;../../../libraries/no-OS/drivers/platform/stm32/stm32_pwm.h;../../../libraries/no-OS/drivers/platform/stm32/stm32_pwm.c;../../../libraries/no-OS/drivers/platform/stm32/stm32_dma.c;../../../libraries/no-OS/drivers/platform/stm32/stm32_dma.h; +app/libraries/no-OS/drivers/platform/stm32/=../../../libraries/no-OS/drivers/platform/stm32/stm32_delay.c;../../../libraries/no-OS/drivers/platform/stm32/stm32_gpio.c;../../../libraries/no-OS/drivers/platform/stm32/stm32_gpio.h;../../../libraries/no-OS/drivers/platform/stm32/stm32_gpio_irq.c;../../../libraries/no-OS/drivers/platform/stm32/stm32_gpio_irq.h;../../../libraries/no-OS/drivers/platform/stm32/stm32_spi.c;../../../libraries/no-OS/drivers/platform/stm32/stm32_spi.h;../../../libraries/no-OS/drivers/platform/stm32/stm32_i2c.c;../../../libraries/no-OS/drivers/platform/stm32/stm32_i2c.h;../../../libraries/no-OS/drivers/platform/stm32/stm32_uart.c;../../../libraries/no-OS/drivers/platform/stm32/stm32_uart.h;../../../libraries/no-OS/drivers/platform/stm32/stm32_irq.h;../../../libraries/no-OS/drivers/platform/stm32/stm32_irq.c;../../../libraries/no-OS/drivers/platform/stm32/stm32_pwm.h;../../../libraries/no-OS/drivers/platform/stm32/stm32_pwm.c;../../../libraries/no-OS/drivers/platform/stm32/stm32_dma.c;../../../libraries/no-OS/drivers/platform/stm32/stm32_dma.h;../../../libraries/no-OS/drivers/platform/stm32/stm32_usb_uart.c;../../../libraries/no-OS/drivers/platform/stm32/stm32_usb_uart.h; app/libraries/no-OS/iio/=../../../libraries/no-OS/iio/iio.c;../../../libraries/no-OS/iio/iio.h;../../../libraries/no-OS/iio/iiod.h;../../../libraries/no-OS/iio/iiod.c;../../../libraries/no-OS/iio/iio_trigger.c;../../../libraries/no-OS/iio/iio_types.h;../../../libraries/no-OS/iio/iio_trigger.h; app/libraries/no-OS/drivers/api/=../../../libraries/no-OS/drivers/api/no_os_gpio.c;../../../libraries/no-OS/drivers/api/no_os_spi.c;../../../libraries/no-OS/drivers/api/no_os_irq.c;../../../libraries/no-OS/drivers/api/no_os_i2c.c;../../../libraries/no-OS/drivers/api/no_os_eeprom.c;../../../libraries/no-OS/drivers/api/no_os_uart.c;../../../libraries/no-OS/drivers/api/no_os_pwm.c;../../../libraries/no-OS/drivers/api/no_os_dma.c; [Others] -Define=_USE_STD_INT_TYPES;TINYIIOD_VERSION_MAJOR;TINYIIOD_VERSION_MINOR;TINYIIOD_VERSION_GIT;IIOD_BUFFER_SIZE;IIO_IGNORE_BUFF_OVERRUN_ERR;USE_PHY_COM_PORT;NO_OS_VERSION; \ No newline at end of file +Define=_USE_STD_INT_TYPES;TINYIIOD_VERSION_MAJOR;TINYIIOD_VERSION_MINOR;TINYIIOD_VERSION_GIT;IIOD_BUFFER_SIZE;IIO_IGNORE_BUFF_OVERRUN_ERR;NO_OS_VERSION;ACTIVE_PLATFORM:2;TARGET_SDP_K1 \ No newline at end of file diff --git a/projects/ad405x_iio/STM32/ad405x_iio.ioc b/projects/ad405x_iio/STM32/ad405x_iio.ioc index 873b7423..51b7dec5 100644 --- a/projects/ad405x_iio/STM32/ad405x_iio.ioc +++ b/projects/ad405x_iio/STM32/ad405x_iio.ioc @@ -36,6 +36,11 @@ Dma.TIM8_CH1.2.PeriphDataAlignment=DMA_PDATAALIGN_BYTE Dma.TIM8_CH1.2.PeriphInc=DMA_PINC_DISABLE Dma.TIM8_CH1.2.Priority=DMA_PRIORITY_LOW Dma.TIM8_CH1.2.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode +FMC.CASLatency1=FMC_SDRAM_CAS_LATENCY_3 +FMC.IPParameters=ReadBurst1,CASLatency1,ReadBurst2,SDClockPeriod1 +FMC.ReadBurst1=FMC_SDRAM_RBURST_ENABLE +FMC.ReadBurst2=FMC_SDRAM_RBURST_ENABLE +FMC.SDClockPeriod1=FMC_SDRAM_CLOCK_DISABLE File.Version=6 GPIO.groupedBy=Group By Peripherals KeepUserPlacement=false @@ -44,6 +49,8 @@ Mcu.Family=STM32F4 Mcu.IP0=DMA Mcu.IP1=FMC Mcu.IP10=UART5 +Mcu.IP11=USB_DEVICE +Mcu.IP12=USB_OTG_HS Mcu.IP2=I2C1 Mcu.IP3=NVIC Mcu.IP4=RCC @@ -52,31 +59,94 @@ Mcu.IP6=SYS Mcu.IP7=TIM1 Mcu.IP8=TIM2 Mcu.IP9=TIM8 -Mcu.IPNb=11 +Mcu.IPNb=13 Mcu.Name=STM32F469NIHx Mcu.Package=TFBGA216 Mcu.Pin0=PB8 -Mcu.Pin1=PB4 -Mcu.Pin10=PH0/OSC_IN -Mcu.Pin11=PH1/OSC_OUT -Mcu.Pin12=PH3 -Mcu.Pin13=PH2 -Mcu.Pin14=PA7 -Mcu.Pin15=VP_SYS_VS_Systick -Mcu.Pin16=VP_TIM1_VS_ClockSourceINT -Mcu.Pin17=VP_TIM2_VS_ClockSourceINT -Mcu.Pin18=VP_TIM8_VS_ClockSourceINT -Mcu.Pin19=VP_TIM8_VS_ClockSourceITR -Mcu.Pin2=PB3 -Mcu.Pin20=VP_TIM8_VS_no_output1 -Mcu.Pin3=PC12 -Mcu.Pin4=PA15 -Mcu.Pin5=PB7 -Mcu.Pin6=PG11 -Mcu.Pin7=PG9 -Mcu.Pin8=PD2 -Mcu.Pin9=PA10 -Mcu.PinsNb=21 +Mcu.Pin1=PB5 +Mcu.Pin10=PD1 +Mcu.Pin11=PI3 +Mcu.Pin12=PI2 +Mcu.Pin13=PF0 +Mcu.Pin14=PI7 +Mcu.Pin15=PI10 +Mcu.Pin16=PI6 +Mcu.Pin17=PG9 +Mcu.Pin18=PD2 +Mcu.Pin19=PH15 +Mcu.Pin2=PB4 +Mcu.Pin20=PI1 +Mcu.Pin21=PA10 +Mcu.Pin22=PF1 +Mcu.Pin23=PI9 +Mcu.Pin24=PH13 +Mcu.Pin25=PH14 +Mcu.Pin26=PI0 +Mcu.Pin27=PH0/OSC_IN +Mcu.Pin28=PF2 +Mcu.Pin29=PH1/OSC_OUT +Mcu.Pin3=PB3 +Mcu.Pin30=PF3 +Mcu.Pin31=PG8 +Mcu.Pin32=PF4 +Mcu.Pin33=PH5 +Mcu.Pin34=PH3 +Mcu.Pin35=PF5 +Mcu.Pin36=PH2 +Mcu.Pin37=PD15 +Mcu.Pin38=PB13 +Mcu.Pin39=PD10 +Mcu.Pin4=PC12 +Mcu.Pin40=PC3 +Mcu.Pin41=PD14 +Mcu.Pin42=PB12 +Mcu.Pin43=PD9 +Mcu.Pin44=PD8 +Mcu.Pin45=PC0 +Mcu.Pin46=PC2 +Mcu.Pin47=PF12 +Mcu.Pin48=PG1 +Mcu.Pin49=PF15 +Mcu.Pin5=PA15 +Mcu.Pin50=PH12 +Mcu.Pin51=PF13 +Mcu.Pin52=PG0 +Mcu.Pin53=PE8 +Mcu.Pin54=PG5 +Mcu.Pin55=PG4 +Mcu.Pin56=PH9 +Mcu.Pin57=PH11 +Mcu.Pin58=PA5 +Mcu.Pin59=PF14 +Mcu.Pin6=PB7 +Mcu.Pin60=PF11 +Mcu.Pin61=PE9 +Mcu.Pin62=PE11 +Mcu.Pin63=PE14 +Mcu.Pin64=PB10 +Mcu.Pin65=PH8 +Mcu.Pin66=PH10 +Mcu.Pin67=PA3 +Mcu.Pin68=PA7 +Mcu.Pin69=PB1 +Mcu.Pin7=PG15 +Mcu.Pin70=PB0 +Mcu.Pin71=PE7 +Mcu.Pin72=PE10 +Mcu.Pin73=PE12 +Mcu.Pin74=PE15 +Mcu.Pin75=PE13 +Mcu.Pin76=PB11 +Mcu.Pin77=VP_SYS_VS_Systick +Mcu.Pin78=VP_TIM1_VS_ClockSourceINT +Mcu.Pin79=VP_TIM2_VS_ClockSourceINT +Mcu.Pin8=PG11 +Mcu.Pin80=VP_TIM8_VS_ClockSourceINT +Mcu.Pin81=VP_TIM8_VS_ClockSourceITR +Mcu.Pin82=VP_TIM8_VS_no_output1 +Mcu.Pin83=VP_USB_DEVICE_VS_USB_DEVICE_CDC_HS +Mcu.Pin9=PD0 +Mcu.PinsNb=84 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32F469NIHx @@ -92,6 +162,7 @@ NVIC.I2C1_ER_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true NVIC.I2C1_EV_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false +NVIC.OTG_HS_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false @@ -108,9 +179,41 @@ PA15.GPIO_Label=CS_PIN PA15.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH PA15.Locked=true PA15.Signal=S_TIM2_CH1_ETR +PA3.GPIOParameters=GPIO_PuPd +PA3.GPIO_PuPd=GPIO_PULLUP +PA3.Mode=Device_HS +PA3.Signal=USB_OTG_HS_ULPI_D0 +PA5.GPIOParameters=GPIO_PuPd +PA5.GPIO_PuPd=GPIO_PULLUP +PA5.Mode=Device_HS +PA5.Signal=USB_OTG_HS_ULPI_CK PA7.Locked=true PA7.Mode=Full_Duplex_Master PA7.Signal=SPI1_MOSI +PB0.GPIOParameters=GPIO_PuPd +PB0.GPIO_PuPd=GPIO_PULLUP +PB0.Mode=Device_HS +PB0.Signal=USB_OTG_HS_ULPI_D1 +PB1.GPIOParameters=GPIO_PuPd +PB1.GPIO_PuPd=GPIO_PULLUP +PB1.Mode=Device_HS +PB1.Signal=USB_OTG_HS_ULPI_D2 +PB10.GPIOParameters=GPIO_PuPd +PB10.GPIO_PuPd=GPIO_PULLUP +PB10.Mode=Device_HS +PB10.Signal=USB_OTG_HS_ULPI_D3 +PB11.GPIOParameters=GPIO_PuPd +PB11.GPIO_PuPd=GPIO_PULLUP +PB11.Mode=Device_HS +PB11.Signal=USB_OTG_HS_ULPI_D4 +PB12.GPIOParameters=GPIO_PuPd +PB12.GPIO_PuPd=GPIO_PULLUP +PB12.Mode=Device_HS +PB12.Signal=USB_OTG_HS_ULPI_D5 +PB13.GPIOParameters=GPIO_PuPd +PB13.GPIO_PuPd=GPIO_PULLUP +PB13.Mode=Device_HS +PB13.Signal=USB_OTG_HS_ULPI_D6 PB3.GPIOParameters=GPIO_PuPd PB3.GPIO_PuPd=GPIO_NOPULL PB3.Locked=true @@ -119,19 +222,70 @@ PB3.Signal=SPI1_SCK PB4.Locked=true PB4.Mode=Full_Duplex_Master PB4.Signal=SPI1_MISO +PB5.GPIOParameters=GPIO_PuPd +PB5.GPIO_PuPd=GPIO_PULLUP +PB5.Mode=Device_HS +PB5.Signal=USB_OTG_HS_ULPI_D7 PB7.Locked=true PB7.Mode=I2C PB7.Signal=I2C1_SDA PB8.Mode=I2C PB8.Signal=I2C1_SCL +PC0.GPIOParameters=GPIO_PuPd +PC0.GPIO_PuPd=GPIO_PULLUP +PC0.Mode=Device_HS +PC0.Signal=USB_OTG_HS_ULPI_STP PC12.Mode=Asynchronous PC12.Signal=UART5_TX +PC2.GPIOParameters=GPIO_PuPd +PC2.GPIO_PuPd=GPIO_PULLUP +PC2.Locked=true +PC2.Mode=Device_HS +PC2.Signal=USB_OTG_HS_ULPI_DIR +PC3.GPIOParameters=GPIO_PuPd +PC3.GPIO_PuPd=GPIO_PULLUP +PC3.Locked=true +PC3.Mode=Device_HS +PC3.Signal=USB_OTG_HS_ULPI_NXT +PD0.Signal=FMC_D2_DA2 +PD1.Signal=FMC_D3_DA3 +PD10.Signal=FMC_D15_DA15 +PD14.Signal=FMC_D0_DA0 +PD15.Signal=FMC_D1_DA1 PD2.Mode=Asynchronous PD2.Signal=UART5_RX +PD8.Signal=FMC_D13_DA13 +PD9.Signal=FMC_D14_DA14 +PE10.Signal=FMC_D7_DA7 +PE11.Signal=FMC_D8_DA8 +PE12.Signal=FMC_D9_DA9 +PE13.Signal=FMC_D10_DA10 +PE14.Signal=FMC_D11_DA11 +PE15.Signal=FMC_D12_DA12 +PE7.Signal=FMC_D4_DA4 +PE8.Signal=FMC_D5_DA5 +PE9.Signal=FMC_D6_DA6 +PF0.Signal=FMC_A0 +PF1.Signal=FMC_A1 +PF11.Signal=FMC_SDNRAS +PF12.Signal=FMC_A6 +PF13.Signal=FMC_A7 +PF14.Signal=FMC_A8 +PF15.Signal=FMC_A9 +PF2.Signal=FMC_A2 +PF3.Signal=FMC_A3 +PF4.Signal=FMC_A4 +PF5.Signal=FMC_A5 +PG0.Signal=FMC_A10 +PG1.Signal=FMC_A11 PG11.GPIOParameters=GPIO_ModeDefaultEXTI PG11.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING PG11.Locked=true PG11.Signal=GPXTI11 +PG15.Signal=FMC_SDNCAS +PG4.Signal=FMC_A14_BA0 +PG5.Signal=FMC_A15_BA1 +PG8.Signal=FMC_SDCLK PG9.GPIOParameters=GPIO_Speed,PinState,GPIO_PuPd PG9.GPIO_PuPd=GPIO_PULLUP PG9.GPIO_Speed=GPIO_SPEED_FREQ_VERY_HIGH @@ -142,11 +296,28 @@ PH0/OSC_IN.Mode=HSE-External-Oscillator PH0/OSC_IN.Signal=RCC_OSC_IN PH1/OSC_OUT.Mode=HSE-External-Oscillator PH1/OSC_OUT.Signal=RCC_OSC_OUT +PH10.Signal=FMC_D18 +PH11.Signal=FMC_D19 +PH12.Signal=FMC_D20 +PH13.Signal=FMC_D21 +PH14.Signal=FMC_D22 +PH15.Signal=FMC_D23 PH2.Mode=SdramChipSelect1_1 PH2.Signal=FMC_SDCKE0 PH3.Locked=true PH3.Mode=SdramChipSelect1_1 PH3.Signal=FMC_SDNE0 +PH5.Signal=FMC_SDNWE +PH8.Signal=FMC_D16 +PH9.Signal=FMC_D17 +PI0.Signal=FMC_D24 +PI1.Signal=FMC_D25 +PI10.Signal=FMC_D31 +PI2.Signal=FMC_D26 +PI3.Signal=FMC_D27 +PI6.Signal=FMC_D28 +PI7.Signal=FMC_D29 +PI9.Signal=FMC_D30 PinOutPanel.CurrentBGAView=Top PinOutPanel.RotationAngle=0 ProjectManager.AskForMigrate=true @@ -158,12 +329,12 @@ ProjectManager.CustomerFirmwarePackage= ProjectManager.DefaultFWLocation=true ProjectManager.DeletePrevious=true ProjectManager.DeviceId=STM32F469NIHx -ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.28.1 +ProjectManager.FirmwarePackage=STM32Cube FW_F4 V1.28.0 ProjectManager.FreePins=false ProjectManager.HalAssertFull=false ProjectManager.HeapSize=0x200 ProjectManager.KeepUserCode=false -ProjectManager.LastFirmware=true +ProjectManager.LastFirmware=false ProjectManager.LibraryCopy=1 ProjectManager.MainLocation=Core/Src ProjectManager.NoMain=true @@ -179,7 +350,7 @@ ProjectManager.ToolChainLocation= ProjectManager.UAScriptAfterPath= ProjectManager.UAScriptBeforePath= ProjectManager.UnderRoot=true -ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-false,2-SystemClock_Config-RCC-false-HAL-false,3-MX_DMA_Init-DMA-false-HAL-false,4-MX_UART5_Init-UART5-false-HAL-false,5-MX_SPI1_Init-SPI1-false-HAL-false,6-MX_I2C1_Init-I2C1-false-HAL-false,7-MX_TIM1_Init-TIM1-false-HAL-false,8-MX_TIM2_Init-TIM2-false-HAL-false,false-9-MX_FMC_Init-FMC-false-HAL-false,10-MX_TIM8_Init-TIM8-false-HAL-false +ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-false,2-SystemClock_Config-RCC-false-HAL-false,3-MX_DMA_Init-DMA-false-HAL-false,4-MX_UART5_Init-UART5-false-HAL-false,5-MX_SPI1_Init-SPI1-false-HAL-false,6-MX_I2C1_Init-I2C1-false-HAL-false,7-MX_TIM1_Init-TIM1-false-HAL-false,8-MX_TIM2_Init-TIM2-false-HAL-false,false-9-MX_FMC_Init-FMC-false-HAL-false,10-MX_TIM8_Init-TIM8-false-HAL-false,11-MX_USB_DEVICE_Init-USB_DEVICE-false-HAL-false RCC.AHBFreq_Value=180000000 RCC.APB1CLKDivider=RCC_HCLK_DIV4 RCC.APB1Freq_Value=45000000 @@ -226,6 +397,106 @@ RCC.VCOI2SOutputFreq_Value=384000000 RCC.VCOInputFreq_Value=2000000 RCC.VCOOutputFreq_Value=360000000 RCC.VCOSAIOutputFreq_Value=384000000 +SH.FMC_A0.0=FMC_A0,12b-sda1 +SH.FMC_A0.ConfNb=1 +SH.FMC_A1.0=FMC_A1,12b-sda1 +SH.FMC_A1.ConfNb=1 +SH.FMC_A10.0=FMC_A10,12b-sda1 +SH.FMC_A10.ConfNb=1 +SH.FMC_A11.0=FMC_A11,12b-sda1 +SH.FMC_A11.ConfNb=1 +SH.FMC_A14_BA0.0=FMC_BA0,FourSdramBanks1 +SH.FMC_A14_BA0.ConfNb=1 +SH.FMC_A15_BA1.0=FMC_BA1,FourSdramBanks1 +SH.FMC_A15_BA1.ConfNb=1 +SH.FMC_A2.0=FMC_A2,12b-sda1 +SH.FMC_A2.ConfNb=1 +SH.FMC_A3.0=FMC_A3,12b-sda1 +SH.FMC_A3.ConfNb=1 +SH.FMC_A4.0=FMC_A4,12b-sda1 +SH.FMC_A4.ConfNb=1 +SH.FMC_A5.0=FMC_A5,12b-sda1 +SH.FMC_A5.ConfNb=1 +SH.FMC_A6.0=FMC_A6,12b-sda1 +SH.FMC_A6.ConfNb=1 +SH.FMC_A7.0=FMC_A7,12b-sda1 +SH.FMC_A7.ConfNb=1 +SH.FMC_A8.0=FMC_A8,12b-sda1 +SH.FMC_A8.ConfNb=1 +SH.FMC_A9.0=FMC_A9,12b-sda1 +SH.FMC_A9.ConfNb=1 +SH.FMC_D0_DA0.0=FMC_D0,sd-32b-d1 +SH.FMC_D0_DA0.ConfNb=1 +SH.FMC_D10_DA10.0=FMC_D10,sd-32b-d1 +SH.FMC_D10_DA10.ConfNb=1 +SH.FMC_D11_DA11.0=FMC_D11,sd-32b-d1 +SH.FMC_D11_DA11.ConfNb=1 +SH.FMC_D12_DA12.0=FMC_D12,sd-32b-d1 +SH.FMC_D12_DA12.ConfNb=1 +SH.FMC_D13_DA13.0=FMC_D13,sd-32b-d1 +SH.FMC_D13_DA13.ConfNb=1 +SH.FMC_D14_DA14.0=FMC_D14,sd-32b-d1 +SH.FMC_D14_DA14.ConfNb=1 +SH.FMC_D15_DA15.0=FMC_D15,sd-32b-d1 +SH.FMC_D15_DA15.ConfNb=1 +SH.FMC_D16.0=FMC_D16,sd-32b-d1 +SH.FMC_D16.ConfNb=1 +SH.FMC_D17.0=FMC_D17,sd-32b-d1 +SH.FMC_D17.ConfNb=1 +SH.FMC_D18.0=FMC_D18,sd-32b-d1 +SH.FMC_D18.ConfNb=1 +SH.FMC_D19.0=FMC_D19,sd-32b-d1 +SH.FMC_D19.ConfNb=1 +SH.FMC_D1_DA1.0=FMC_D1,sd-32b-d1 +SH.FMC_D1_DA1.ConfNb=1 +SH.FMC_D20.0=FMC_D20,sd-32b-d1 +SH.FMC_D20.ConfNb=1 +SH.FMC_D21.0=FMC_D21,sd-32b-d1 +SH.FMC_D21.ConfNb=1 +SH.FMC_D22.0=FMC_D22,sd-32b-d1 +SH.FMC_D22.ConfNb=1 +SH.FMC_D23.0=FMC_D23,sd-32b-d1 +SH.FMC_D23.ConfNb=1 +SH.FMC_D24.0=FMC_D24,sd-32b-d1 +SH.FMC_D24.ConfNb=1 +SH.FMC_D25.0=FMC_D25,sd-32b-d1 +SH.FMC_D25.ConfNb=1 +SH.FMC_D26.0=FMC_D26,sd-32b-d1 +SH.FMC_D26.ConfNb=1 +SH.FMC_D27.0=FMC_D27,sd-32b-d1 +SH.FMC_D27.ConfNb=1 +SH.FMC_D28.0=FMC_D28,sd-32b-d1 +SH.FMC_D28.ConfNb=1 +SH.FMC_D29.0=FMC_D29,sd-32b-d1 +SH.FMC_D29.ConfNb=1 +SH.FMC_D2_DA2.0=FMC_D2,sd-32b-d1 +SH.FMC_D2_DA2.ConfNb=1 +SH.FMC_D30.0=FMC_D30,sd-32b-d1 +SH.FMC_D30.ConfNb=1 +SH.FMC_D31.0=FMC_D31,sd-32b-d1 +SH.FMC_D31.ConfNb=1 +SH.FMC_D3_DA3.0=FMC_D3,sd-32b-d1 +SH.FMC_D3_DA3.ConfNb=1 +SH.FMC_D4_DA4.0=FMC_D4,sd-32b-d1 +SH.FMC_D4_DA4.ConfNb=1 +SH.FMC_D5_DA5.0=FMC_D5,sd-32b-d1 +SH.FMC_D5_DA5.ConfNb=1 +SH.FMC_D6_DA6.0=FMC_D6,sd-32b-d1 +SH.FMC_D6_DA6.ConfNb=1 +SH.FMC_D7_DA7.0=FMC_D7,sd-32b-d1 +SH.FMC_D7_DA7.ConfNb=1 +SH.FMC_D8_DA8.0=FMC_D8,sd-32b-d1 +SH.FMC_D8_DA8.ConfNb=1 +SH.FMC_D9_DA9.0=FMC_D9,sd-32b-d1 +SH.FMC_D9_DA9.ConfNb=1 +SH.FMC_SDCLK.0=FMC_SDCLK,12b-sda1 +SH.FMC_SDCLK.ConfNb=1 +SH.FMC_SDNCAS.0=FMC_SDNCAS,12b-sda1 +SH.FMC_SDNCAS.ConfNb=1 +SH.FMC_SDNRAS.0=FMC_SDNRAS,12b-sda1 +SH.FMC_SDNRAS.ConfNb=1 +SH.FMC_SDNWE.0=FMC_SDNWE,12b-sda1 +SH.FMC_SDNWE.ConfNb=1 SH.GPXTI11.0=GPIO_EXTI11 SH.GPXTI11.ConfNb=1 SH.S_TIM1_CH3.0=TIM1_CH3,PWM Generation3 CH3 @@ -262,6 +533,13 @@ TIM8.TIM_MasterSlaveMode=TIM_MASTERSLAVEMODE_ENABLE UART5.BaudRate=230400 UART5.IPParameters=VirtualMode,BaudRate UART5.VirtualMode=Asynchronous +USB_DEVICE.CLASS_NAME_HS=CDC +USB_DEVICE.IPParameters=VirtualMode-CDC_HS,VirtualModeHS,CLASS_NAME_HS +USB_DEVICE.VirtualMode-CDC_HS=Cdc +USB_DEVICE.VirtualModeHS=Cdc_HS +USB_OTG_HS.DeviceSpeed-Device_HS=PCD_SPEED_HIGH +USB_OTG_HS.IPParameters=VirtualMode-Device_HS,DeviceSpeed-Device_HS +USB_OTG_HS.VirtualMode-Device_HS=Device_HS VP_SYS_VS_Systick.Mode=SysTick VP_SYS_VS_Systick.Signal=SYS_VS_Systick VP_TIM1_VS_ClockSourceINT.Mode=Internal @@ -274,4 +552,6 @@ VP_TIM8_VS_ClockSourceITR.Mode=TriggerSource_ITR0 VP_TIM8_VS_ClockSourceITR.Signal=TIM8_VS_ClockSourceITR VP_TIM8_VS_no_output1.Mode=PWM Generation1 No Output VP_TIM8_VS_no_output1.Signal=TIM8_VS_no_output1 +VP_USB_DEVICE_VS_USB_DEVICE_CDC_HS.Mode=CDC_HS +VP_USB_DEVICE_VS_USB_DEVICE_CDC_HS.Signal=USB_DEVICE_VS_USB_DEVICE_CDC_HS board=custom diff --git a/projects/ad405x_iio/app/ad405x_iio.c b/projects/ad405x_iio/app/ad405x_iio.c index 51823dba..aa981173 100644 --- a/projects/ad405x_iio/app/ad405x_iio.c +++ b/projects/ad405x_iio/app/ad405x_iio.c @@ -85,37 +85,29 @@ static int8_t adc_data_buffer[DATA_BUFFER_SIZE]; /* IIO trigger name */ #define AD405X_IIO_TRIGGER_NAME ACTIVE_DEVICE_NAME"_iio_trigger" +/* Device names */ +#define DEV_AD4050 "ad4050" +#define DEV_AD4052 "ad4052" + #if (ADC_CAPTURE_MODE == SAMPLE_MODE) -#define REAL_BITS ADC_SAMPLE_MODE_RESOLUTION #define STORAGE_BITS 16 -#elif (ADC_CAPTURE_MODE == BURST_AVERAGING_MODE) -#define REAL_BITS ADC_BURST_AVG_MODE_RESOLUTION -#define STORAGE_BITS 32 -#elif (ADC_CAPTURE_MODE == AVERAGING_MODE) -#define REAL_BITS ADC_BURST_AVG_MODE_RESOLUTION +#define AD4050_SAMPLE_RES 12 +#define AD4052_SAMPLE_RES 16 +#else #define STORAGE_BITS 32 +#define AD4050_AVG_RES 14 +#define AD4052_AVG_RES 20 #endif /* Number of storage bytes for each sample */ #define BYTES_PER_SAMPLE (STORAGE_BITS/8) -static float scale = (((ADC_REF_VOLTAGE) / ADC_MAX_COUNT) * 1000); - /* Internal sampling frequency/period (2msps->500nsec) */ #define INTERNAL_SAMPLING_CLK_NS 500 /* Internal conversion time in nsec */ #define CONVERSION_TIME_NS 250 -/* The SPI SCLK is fixed to 44.4ns per 22.5MHz frequency, - * So in burst mode the time taken for 24 bits transfer is - * 24 * 44.4ns = ~1.1us. For 16 bits it is 16 * 44.4ns = 0.72us */ -#if defined(DEV_AD4050) -#define SPI_BURST_DATA_READ_TIME_NS 720 -#else -#define SPI_BURST_DATA_READ_TIME_NS 1100 -#endif - #define MAX_SAMPLING_TIME_NS (((float)(1.0/SAMPLING_RATE) * 1000000000) / 2) #define MAX_SAMPLING_PERIOD_NSEC 1000000 @@ -211,7 +203,6 @@ static struct scan_type ad405x_iio_scan_type = { #else .sign = 's', #endif - .realbits = REAL_BITS, .storagebits = STORAGE_BITS, .shift = 0, #if (INTERFACE_MODE == SPI_DMA) @@ -232,10 +223,7 @@ static char *ad405x_op_mode_str[] = { /* Averaging filter length values string representation */ static char *ad405x_avg_filter_str[] = { "2","4","8","16","32","64","128", - "256", -#if !defined(DEV_AD4050) - "512","1024","2048","4096" -#endif + "256", "512","1024","2048","4096" }; /* String representation of burst mode sample rates */ @@ -336,6 +324,12 @@ uint32_t nb_of_samples_g; /* Global variable for data read from CB functions */ int32_t data_read; +/* Variable to store ADC resolution based on device and mode */ +static uint8_t resolution; + +/* Variable to store maximum count of the ADC based on device and mode*/ +static uint32_t adc_max_count; + /* SPI Message */ struct no_os_spi_msg ad405x_spi_msg; @@ -466,11 +460,11 @@ static int calc_closest_burst_attr_val(enum ad405x_attribute_ids attr_id, switch (attr_id) { case ADC_FILTER_LENGTH: lower_bound = AD405X_LENGTH_2; -#if defined(DEV_AD4052) - upper_bound = AD405X_LENGTH_4096; -#else - upper_bound = AD405X_LENGTH_256; -#endif + if (p_ad405x_dev->active_device == ID_AD4050) { + upper_bound = AD405X_LENGTH_256; + } else { + upper_bound = AD405X_LENGTH_4096; + } break; case ADC_BURST_SAMPLE_RATE: @@ -520,6 +514,7 @@ static int iio_ad405x_attr_get(void *device, int ret; int32_t adc_raw_data; static int32_t offset = 0; + float scale; uint8_t reg_data; uint32_t value; @@ -562,12 +557,8 @@ static int iio_ad405x_attr_get(void *device, } #if (ADC_DATA_FORMAT == TWOS_COMPLEMENT) - if (adc_raw_data >= ADC_MAX_COUNT) { -#if (ADC_CAPTURE_MODE == SAMPLE_MODE) - offset = -(NO_OS_BIT(ADC_SAMPLE_MODE_RESOLUTION) - 1); -#else - offset = -(NO_OS_BIT(ADC_BURST_AVG_MODE_RESOLUTION) - 1); -#endif + if (adc_raw_data >= adc_max_count) { + offset = -(NO_OS_BIT(resolution) - 1); } else { offset = 0; } @@ -575,6 +566,7 @@ static int iio_ad405x_attr_get(void *device, return sprintf(buf, "%ld", adc_raw_data); case ADC_SCALE: + scale = (((ADC_REF_VOLTAGE) / adc_max_count) * 1000); return sprintf(buf, "%g", scale); case ADC_OFFSET: @@ -677,7 +669,7 @@ static int iio_ad405x_attr_set(void *device, return len; #if (ADC_CAPTURE_MODE != SAMPLE_MODE) -#if (ADC_CAPTURE_MODE == BURST_AVERAGING_MODE_MODE) +#if (ADC_CAPTURE_MODE == BURST_AVERAGING_MODE) case ADC_BURST_SAMPLE_RATE: for (burst_rate = AD405X_2_MSPS; burst_rate <= AD405X_111_SPS; burst_rate++) { if (!strncmp(buf, ad405x_burst_sample_rates_str[burst_rate], strlen(buf))) { @@ -826,28 +818,33 @@ static int iio_ad405x_attr_available_get(void *device, #endif case ADC_FILTER_LENGTH: - return sprintf(buf, - "%s %s %s %s %s %s %s %s" -#if !defined(DEV_AD4050) - " %s %s %s %s", -#else - , -#endif - ad405x_avg_filter_str[0], - ad405x_avg_filter_str[1], - ad405x_avg_filter_str[2], - ad405x_avg_filter_str[3], - ad405x_avg_filter_str[4], - ad405x_avg_filter_str[5], - ad405x_avg_filter_str[6], - ad405x_avg_filter_str[7] -#if !defined(DEV_AD4050) - ,ad405x_avg_filter_str[8], - ad405x_avg_filter_str[9], - ad405x_avg_filter_str[10], - ad405x_avg_filter_str[11] -#endif - ); + if (p_ad405x_dev->active_device == ID_AD4050) { + return sprintf(buf, + "%s %s %s %s %s %s %s %s", + ad405x_avg_filter_str[0], + ad405x_avg_filter_str[1], + ad405x_avg_filter_str[2], + ad405x_avg_filter_str[3], + ad405x_avg_filter_str[4], + ad405x_avg_filter_str[5], + ad405x_avg_filter_str[6], + ad405x_avg_filter_str[7]); + } else { + return sprintf(buf, + "%s %s %s %s %s %s %s %s %s %s %s %s", + ad405x_avg_filter_str[0], + ad405x_avg_filter_str[1], + ad405x_avg_filter_str[2], + ad405x_avg_filter_str[3], + ad405x_avg_filter_str[4], + ad405x_avg_filter_str[5], + ad405x_avg_filter_str[6], + ad405x_avg_filter_str[7], + ad405x_avg_filter_str[8], + ad405x_avg_filter_str[9], + ad405x_avg_filter_str[10], + ad405x_avg_filter_str[11]); + } #endif default: @@ -993,32 +990,15 @@ static int32_t iio_ad405x_prepare_transfer(void *dev, uint32_t mask) return ret; } - struct no_os_dma_ch* rxch; - struct no_os_dma_ch* txch; - /* Switch to faster SPI SCLK and * initialize Chip Select PWMs and DMA descriptors */ ad405x_init_params.spi_init->max_speed_hz = MAX_SPI_SCLK_45MHz; spi_init_param = ad405x_init_params.spi_init->extra; - spi_init_param->pwm_init = (const struct no_os_pwm_init *)&cs_init_params; + spi_init_param->pwm_init = (const struct no_os_pwm_init_param *)&cs_init_params; spi_init_param->dma_init = &ad405x_dma_init_param; - - rxch = (struct no_os_dma_ch*)no_os_calloc(1, sizeof(*rxch)); - if (!rxch) { - return -ENOMEM; - } - - txch = (struct no_os_dma_ch*)no_os_calloc(1, sizeof(*txch)); - if (!txch) { - return -ENOMEM; - } - - rxch->irq_num = Rx_DMA_IRQ_ID; - rxch->extra = &rxdma_channel; - txch->extra = &txdma_channel; - - spi_init_param->rxdma_ch = rxch; - spi_init_param->txdma_ch = txch; + spi_init_param->irq_num = Rx_DMA_IRQ_ID; + spi_init_param->rxdma_ch = &rxdma_channel; + spi_init_param->txdma_ch = &txdma_channel; ret = no_os_spi_init(&p_ad405x_dev->spi_desc, ad405x_init_params.spi_init); if (ret) { @@ -1038,9 +1018,6 @@ static int32_t iio_ad405x_prepare_transfer(void *dev, uint32_t mask) if (ret) { return ret; } - - /* Configure Timer 1 parameters */ - tim1_config(); #endif return 0; @@ -1157,7 +1134,7 @@ static int32_t iio_ad405x_submit_samples(struct iio_device_data *iio_dev_data) ret = no_os_spi_transfer_dma_async(p_ad405x_dev->spi_desc, &ad405x_spi_msg, 1, - (void *)receivecomplete_callback, + NULL, NULL); if (ret) { return ret; @@ -1169,14 +1146,8 @@ static int32_t iio_ad405x_submit_samples(struct iio_device_data *iio_dev_data) htim1.Instance->CNT = 0; TIM8->CNT = 0; - sdesc->hspi.hdmarx->Instance->CR &= ~DMA_SxCR_EN; - sdesc->hspi.hdmarx->Instance->M0AR = (uint16_t *)local_buf; - sdesc->hspi.hdmarx->Instance->NDTR = spirxdma_ndtr; - sdesc->hspi.hdmarx->Instance->CR |= DMA_SxCR_EN; - dma_config_updated = true; ad405x_conversion_flag = false; - tim8_config(); } dma_cycle_count = ((nb_of_samples) / spirxdma_ndtr) + 1; @@ -1351,6 +1322,49 @@ static int32_t iio_ad405x_debug_reg_write(void *dev, return 0; } +/** + * @brief Assign device name and resolution + * @param dev_type[in] - The device type + * @param dev_name[out] - The device name + * @return 0 in case of success, negative error code otherwise. + */ +static int32_t ad405x_assign_device(enum ad405x_device_type dev_type, + char** dev_name) +{ + switch (dev_type) { + case ID_AD4050: + ad405x_init_params.active_device = ID_AD4050; + *dev_name = DEV_AD4050; +#if (ADC_CAPTURE_MODE == SAMPLE_MODE) + resolution = AD4050_SAMPLE_RES; +#else + resolution = AD4050_AVG_RES; +#endif + break; + + case ID_AD4052: + ad405x_init_params.active_device = ID_AD4052; + *dev_name = DEV_AD4052; +#if (ADC_CAPTURE_MODE == SAMPLE_MODE) + resolution = AD4052_SAMPLE_RES; +#else + resolution = AD4052_AVG_RES; +#endif + break; + + default: + return -EINVAL; + } + +#if (ADC_DATA_FORMAT == STRAIGHT_BINARY) + adc_max_count = (uint32_t)(1 << (resolution)); +#else + adc_max_count = (uint32_t)(1 << (resolution - 1)); +#endif + + return 0; +} + /** * @brief Init for reading/writing and parameterization of a * ad405x IIO device @@ -1366,6 +1380,9 @@ static int32_t iio_ad405x_init(struct iio_device **desc) return -EINVAL; } + /* Resolution is assigned to the IIO channel */ + iio_ad405x_channels[0].scan_type->realbits = resolution; + iio_ad405x_inst->num_ch = NO_OS_ARRAY_SIZE(iio_ad405x_channels); iio_ad405x_inst->channels = iio_ad405x_channels; iio_ad405x_inst->attributes = iio_ad405x_global_attributes; @@ -1434,6 +1451,8 @@ static int32_t ad405x_iio_trigger_param_init(struct iio_hw_trig **desc) int32_t iio_ad405x_initialize(void) { int32_t init_status; + enum ad405x_device_type dev_type; + uint8_t indx; #if (APP_CAPTURE_MODE == CONTINUOUS_DATA_CAPTURE) static struct iio_trigger ad405x_iio_trig_desc = { @@ -1471,19 +1490,37 @@ int32_t iio_ad405x_initialize(void) } /* Read context attributes */ - init_status = get_iio_context_attributes(&iio_init_params.ctx_attrs, - &iio_init_params.nb_ctx_attr, - eeprom_desc, - HW_MEZZANINE_NAME, - STR(HW_CARRIER_NAME), - &hw_mezzanine_is_valid); - if (init_status) { - return init_status; + static const char *mezzanine_names[] = { + "EVAL-AD4050-ARDZ", + "EVAL-AD4052-ARDZ" + }; + + /* Iterate twice to detect the correct attached board */ + for (indx = 0; indx < NO_OS_ARRAY_SIZE(mezzanine_names); indx++) { + init_status = get_iio_context_attributes(&iio_init_params.ctx_attrs, + &iio_init_params.nb_ctx_attr, + eeprom_desc, + mezzanine_names[indx], + STR(HW_CARRIER_NAME), + &hw_mezzanine_is_valid); + if (init_status) { + return init_status; + } + + if (hw_mezzanine_is_valid) { + dev_type = indx; + break; + } } if (hw_mezzanine_is_valid) { /* Initialize AD405X device and peripheral interface */ + init_status = ad405x_assign_device(dev_type, &iio_device_init_params[0].name); + if (init_status) { + return init_status; + } + init_status = ad405x_init(&p_ad405x_dev, ad405x_init_params); if (init_status) { return init_status; @@ -1509,7 +1546,6 @@ int32_t iio_ad405x_initialize(void) } /* Initialize the IIO interface */ - iio_device_init_params[0].name = ACTIVE_DEVICE_NAME; iio_device_init_params[0].raw_buf = adc_data_buffer; iio_device_init_params[0].raw_buf_len = DATA_BUFFER_SIZE; diff --git a/projects/ad405x_iio/app/ad405x_user_config.c b/projects/ad405x_iio/app/ad405x_user_config.c index 425ae9d6..62b402f0 100644 --- a/projects/ad405x_iio/app/ad405x_user_config.c +++ b/projects/ad405x_iio/app/ad405x_user_config.c @@ -64,7 +64,6 @@ struct no_os_gpio_init_param gpio_gpio1_param = { /* Initialize the AD405X device structure */ struct ad405x_init_param ad405x_init_params = { .spi_init = &spi_init_params, - .active_device = ACTIVE_DEVICE_ID, .gpio_cnv = &gpio_cnv_param, .gpio_gpio0 = &gpio_gpio0_param, .gpio_gpio1 = &gpio_gpio1_param, diff --git a/projects/ad405x_iio/app/app_config.h b/projects/ad405x_iio/app/app_config.h index 7edd3a94..f57064af 100644 --- a/projects/ad405x_iio/app/app_config.h +++ b/projects/ad405x_iio/app/app_config.h @@ -91,43 +91,13 @@ #endif #endif -// **** Note for User on selection of Active Device ****// -/* Define the device type here from the list of below device type defines - * (one at a time. Defining more than one device can result into compile error). - * e.g. #define DEV_AD4050 -> This will make AD4050 as an active device. - * The active device is default set to AD4052 if device type is not defined. - * */ -// #define DEV_AD4050 - -#if defined(DEV_AD4052) -#define ACTIVE_DEVICE_NAME "ad4052" -#define DEVICE_NAME "DEV_AD4052" -#define ACTIVE_DEVICE_ID ID_AD4052 -#define HW_MEZZANINE_NAME "EVAL-AD4052-ARDZ" -#define ADC_SAMPLE_MODE_RESOLUTION 16 -#define ADC_AVERAGING_MODE_RESOLUTION 20 -#define ADC_BURST_AVG_MODE_RESOLUTION 20 -#elif defined(DEV_AD4050) -#define ACTIVE_DEVICE_NAME "ad4050" -#define DEVICE_NAME "DEV_AD4050" -#define ACTIVE_DEVICE_ID ID_AD4050 -#define HW_MEZZANINE_NAME "EVAL-AD4050-ARDZ" -#define ADC_SAMPLE_MODE_RESOLUTION 12 -#define ADC_AVERAGING_MODE_RESOLUTION 14 -#define ADC_BURST_AVG_MODE_RESOLUTION 14 -#else -#define ACTIVE_DEVICE_NAME "ad4052" -#define DEVICE_NAME "DEV_AD4052" -#define ACTIVE_DEVICE_ID ID_AD4052 -#define HW_MEZZANINE_NAME "EVAL-AD4052-ARDZ" -#define ADC_SAMPLE_MODE_RESOLUTION 16 -#define ADC_AVERAGING_MODE_RESOLUTION 20 -#define ADC_BURST_AVG_MODE_RESOLUTION 20 -#endif +#define ACTIVE_DEVICE_NAME "ad405x" +#define DEVICE_NAME "DEV_AD405x" #if (ACTIVE_PLATFORM == MBED_PLATFORM) #include "app_config_mbed.h" #define HW_CARRIER_NAME TARGET_NAME +#define CONSOLE_STDIO_PORT_AVAILABLE #elif (ACTIVE_PLATFORM == STM32_PLATFORM) #include "app_config_stm32.h" #define HW_CARRIER_NAME TARGET_NAME @@ -150,20 +120,6 @@ /* ADC reference voltage (Range: 2.5 to 3.3v) */ #define ADC_REF_VOLTAGE 2.5 -#if (ADC_CAPTURE_MODE == SAMPLE_MODE) -#if (ADC_DATA_FORMAT == STRAIGHT_BINARY) -#define ADC_MAX_COUNT (uint32_t)(1 << (ADC_SAMPLE_MODE_RESOLUTION)) -#else -#define ADC_MAX_COUNT (uint32_t)(1 << (ADC_SAMPLE_MODE_RESOLUTION - 1)) -#endif -#else -#if (ADC_DATA_FORMAT == STRAIGHT_BINARY) -#define ADC_MAX_COUNT (uint32_t)(1 << (ADC_BURST_AVG_MODE_RESOLUTION)) -#else -#define ADC_MAX_COUNT (uint32_t)(1 << (ADC_BURST_AVG_MODE_RESOLUTION - 1)) -#endif -#endif - /* Time taken for the application to process the interrupt and * push data into iio buffer. */ #define MIN_DATA_CAPTURE_TIME_NS 8000 @@ -195,17 +151,6 @@ /* Serial number string is formed as: application name + device (target) name + platform (host) name */ #define VIRTUAL_COM_SERIAL_NUM (FIRMWARE_NAME "_" DEVICE_NAME "_" STR(PLATFORM_NAME)) -/* Check if any serial port available for use as console stdio port */ -#if defined(USE_PHY_COM_PORT) -/* If PHY com is selected, VCOM or alternate PHY com port can act as a console stdio port */ -#if (ACTIVE_PLATFORM == MBED_PLATFORM) -#define CONSOLE_STDIO_PORT_AVAILABLE -#endif -#else -/* If VCOM is selected, PHY com port will/should act as a console stdio port */ -#define CONSOLE_STDIO_PORT_AVAILABLE -#endif - /* Enable/Disable the use of SDRAM for ADC data capture buffer */ //#define USE_SDRAM // Uncomment to use SDRAM as data buffer diff --git a/projects/ad405x_iio/app/app_config_stm32.c b/projects/ad405x_iio/app/app_config_stm32.c index 6041109d..1f0c6d26 100644 --- a/projects/ad405x_iio/app/app_config_stm32.c +++ b/projects/ad405x_iio/app/app_config_stm32.c @@ -50,10 +50,16 @@ struct stm32_uart_init_param stm32_uart_extra_init_params = { .huart = &huart5, }; +/* STM32 VCOM init parameters */ +struct stm32_usb_uart_init_param stm32_vcom_extra_init_params = { + .husbdevice = &hUsbDeviceHS, +}; + /* STM32 SPI specific parameters */ struct stm32_spi_init_param stm32_spi_extra_init_params = { .chip_select_port = STM32_SPI_CS_PORT_NUM, .get_input_clock = HAL_RCC_GetPCLK2Freq, + .alternate = GPIO_AF1_TIM2 }; /* STM32 GPIO specific parameters */ @@ -115,7 +121,9 @@ struct stm32_pwm_init_param stm32_pwm_cnv_extra_init_params = { .mode = TIM_OC_PWM1, .timer_chn = TIMER_CHANNEL_3, .get_timer_clock = HAL_RCC_GetPCLK2Freq, - .clock_divider = TIMER_1_CLK_DIVIDER + .clock_divider = TIMER_1_CLK_DIVIDER, + .trigger_enable = false, + .trigger_output = PWM_TRGO_UPDATE }; #if (INTERFACE_MODE == SPI_DMA) @@ -139,7 +147,12 @@ struct stm32_pwm_init_param stm32_tx_trigger_extra_init_params = { .timer_chn = TIMER_CHANNEL_1, .complementary_channel = false, .get_timer_clock = HAL_RCC_GetPCLK1Freq, - .clock_divider = TIMER_8_CLK_DIVIDER + .clock_divider = TIMER_8_CLK_DIVIDER, + .trigger_enable = true, + .trigger_source = PWM_TS_ITR0, + .repetitions = 0, + .onepulse_enable = true, + .dma_enable = true, }; #endif @@ -176,7 +189,6 @@ uint8_t *dma_buf_current_idx; /************************** Functions Declaration *****************************/ /******************************************************************************/ void receivecomplete_callback(DMA_HandleTypeDef * hdma); -void tim1_config(void); /******************************************************************************/ /************************** Functions Definition ******************************/ /******************************************************************************/ @@ -202,6 +214,9 @@ void stm32_system_init(void) MX_TIM1_Init(); MX_TIM8_Init(); MX_SPI1_Init(); +#ifdef USE_VIRTUAL_COM_PORT + MX_USB_DEVICE_Init(); +#endif HAL_NVIC_DisableIRQ(STM32_DMA_CONT_TRIGGER); #if (INTERFACE_MODE == SPI_INTERRUPT) HAL_NVIC_DisableIRQ(STM32_DMA_SPI_RX_TRIGGER); @@ -266,6 +281,9 @@ void update_buff(uint32_t* local_buf, uint32_t* buf_start_addr) */ void stm32_timer_enable(void) { + /* Enable TIM DMA request */ + no_os_pwm_enable(tx_trigger_desc); + /* Enable timers 1 and 2 */ TIM1->CCER |= TIM_CCER_CC3E; TIM2->CCER |= TIM_CCER_CC1E; @@ -394,40 +412,4 @@ int stm32_abort_dma_transfer(void) } } - -/** - * @brief Configure CNV timer - * @return None - */ -void tim1_config(void) -{ - TIM1->EGR = TIM_EGR_UG;// Generate update event - - TIM1->CR2 &= ~TIM_CR2_MMS; - TIM1->CR2 |= TIM_TRGO_UPDATE; // Select Update as trigger event -} - -/* Configure TIM8 for slave mode operation, one-pulse mode - * and to generate DMA requests. */ -void tim8_config(void) -{ - TIM8->RCR = 0; - - TIM8->CCMR1 &= ~TIM_CCMR1_CC1S_Msk; - - TIM8->EGR = TIM_EGR_UG;// Generate update event - - TIM8->CCMR1 &= ~TIM_CCMR1_CC1S_Msk; // Output compare - - TIM8->SMCR &= ~TIM_SMCR_TS_Msk; // Select TIM1 as TRGI source - - TIM8->SMCR &= ~TIM_SMCR_SMS_Msk; - TIM8->SMCR |= TIM_SMCR_SMS_1 | - TIM_SMCR_SMS_2; // Set trigger mode for slave controller - - TIM8->CR1 &= ~TIM_CR1_OPM_Msk; - TIM8->CR1 |= TIM_CR1_OPM; // Enable one pulse mode - - TIM8->DIER |= TIM_DIER_CC1DE; // Generate DMA request after overflow -} #endif \ No newline at end of file diff --git a/projects/ad405x_iio/app/app_config_stm32.h b/projects/ad405x_iio/app/app_config_stm32.h index e3bd9978..83efcd64 100644 --- a/projects/ad405x_iio/app/app_config_stm32.h +++ b/projects/ad405x_iio/app/app_config_stm32.h @@ -27,6 +27,7 @@ #include "stm32_uart.h" #include "stm32_dma.h" #include "stm32_pwm.h" +#include "stm32_usb_uart.h" /******************************************************************************/ /********************** Macros and Constants Definition ***********************/ @@ -95,6 +96,7 @@ #define dma_extra_init_params stm32_dma_extra_init_params #define cs_extra_init_params stm32_cs_extra_init_params #define tx_trigger_extra_init_params stm32_tx_trigger_extra_init_params +#define vcom_extra_init_params stm32_vcom_extra_init_params /* Platform ops */ #define gpio_ops stm32_gpio_ops @@ -104,6 +106,7 @@ #define pwm_ops stm32_pwm_ops #define trigger_gpio_irq_ops stm32_gpio_irq_ops #define dma_ops stm32_dma_ops +#define vcom_ops stm32_usb_uart_ops #define MAX_SPI_SCLK 22500000 #define MAX_SPI_SCLK_45MHz 45000000 @@ -143,9 +146,11 @@ extern DMA_HandleTypeDef hdma_tim1_ch3; extern DMA_HandleTypeDef hdma_tim1_ch2; extern DMA_HandleTypeDef hdma_tim8_ch1; extern UART_HandleTypeDef huart5; +extern USBD_HandleTypeDef hUsbDeviceHS; extern volatile bool data_ready; extern struct stm32_uart_init_param stm32_uart_extra_init_params; +extern struct stm32_usb_uart_init_param stm32_vcom_extra_init_params; extern struct stm32_spi_init_param stm32_spi_extra_init_params; extern struct stm32_gpio_init_param stm32_pwm_gpio_extra_init_params; extern struct stm32_gpio_init_param stm32_gpio_cnv_extra_init_params; @@ -179,7 +184,5 @@ void stm32_configure_spi_dma(struct no_os_spi_init_param* spi_init_par, struct no_os_spi_desc* spi_desc, bool is_dma_mode); int stm32_abort_dma_transfer(void); void receivecomplete_callback(DMA_HandleTypeDef * hdma); -void tim8_config(void); -void tim1_config(void); #endif /* APP_CONFIG_STM32_H_ */