From c691d2bf56a0449e93a1fec92345adda0e0dacd7 Mon Sep 17 00:00:00 2001 From: Jake Carter Date: Thu, 18 Apr 2024 16:03:51 -0600 Subject: [PATCH 01/93] Allow configuration of -mcpu for different archs --- Libraries/CMSIS/Device/Maxim/GCC/gcc.mk | 42 +++++++++++++++---------- USERGUIDE.md | 4 ++- 2 files changed, 28 insertions(+), 18 deletions(-) diff --git a/Libraries/CMSIS/Device/Maxim/GCC/gcc.mk b/Libraries/CMSIS/Device/Maxim/GCC/gcc.mk index 494adabccca..d16eae97c2c 100644 --- a/Libraries/CMSIS/Device/Maxim/GCC/gcc.mk +++ b/Libraries/CMSIS/Device/Maxim/GCC/gcc.mk @@ -242,26 +242,19 @@ GCCVERSIONGTEQ4 := 1 # endif -# The flags passed to the assembler. -AFLAGS=-mthumb \ - -mcpu=cortex-m4 \ - -MD -ifneq "$(HEAP_SIZE)" "" -AFLAGS+=-D__HEAP_SIZE=$(HEAP_SIZE) -endif -ifneq "$(STACK_SIZE)" "" -AFLAGS+=-D__STACK_SIZE=$(STACK_SIZE) -endif -ifneq "$(SRAM_SIZE)" "" -AFLAGS+=-D__SRAM_SIZE=$(SRAM_SIZE) -endif -AFLAGS+=$(PROJ_AFLAGS) - ifeq "$(MXC_OPTIMIZE_CFLAGS)" "" # Default is optimize for size MXC_OPTIMIZE_CFLAGS = -Os endif +# Select the target ARM processor. +# Permissible options can be found under the "-mtune" documentation in the GCC manual +# https://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html +# Our hardware currently supports +# - cortex-m4 (default) +# - cortex-m33 +MCPU ?= cortex-m4 + # Float ABI options: # See https://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html (-mfloat-abi) # Specifies which floating-point ABI to use. Permissible values are: ‘soft’, ‘softfp’ and ‘hard’. @@ -302,8 +295,23 @@ endif DEFAULT_OPTIMIZE_FLAGS ?= -ffunction-sections -fdata-sections -fsingle-precision-constant DEFAULT_WARNING_FLAGS ?= -Wall -Wno-format -Wdouble-promotion +# The flags passed to the assembler. +AFLAGS=-mthumb \ + -mcpu=$(MCPU) \ + -MD +ifneq "$(HEAP_SIZE)" "" +AFLAGS+=-D__HEAP_SIZE=$(HEAP_SIZE) +endif +ifneq "$(STACK_SIZE)" "" +AFLAGS+=-D__STACK_SIZE=$(STACK_SIZE) +endif +ifneq "$(SRAM_SIZE)" "" +AFLAGS+=-D__SRAM_SIZE=$(SRAM_SIZE) +endif +AFLAGS+=$(PROJ_AFLAGS) + CFLAGS=-mthumb \ - -mcpu=cortex-m4 \ + -mcpu=$(MCPU) \ -mfloat-abi=$(MFLOAT_ABI) \ -mfpu=$(MFPU) \ -Wa,-mimplicit-it=thumb \ @@ -363,7 +371,7 @@ LD=${PREFIX}-gcc # The flags passed to the linker. LDFLAGS=-mthumb \ - -mcpu=cortex-m4 \ + -mcpu=$(MCPU) \ -mfloat-abi=$(MFLOAT_ABI) \ -mfpu=$(MFPU) \ -Xlinker --gc-sections \ diff --git a/USERGUIDE.md b/USERGUIDE.md index 3a79b576b3c..7b7e40902e5 100644 --- a/USERGUIDE.md +++ b/USERGUIDE.md @@ -1752,7 +1752,7 @@ The following variables can be used to interface with the compiler to perform co | `LINKERFILE` | Set the linkerfile to use | A linkerfile is responsible for specifying the available memory banks, their layout, and the organization of program binaries memory. The file should exist in `Libraries/CMSIS/Device/Maxim/TARGET/Source/GCC` in the MSDK, or it should be placed inside the root directory of the project. | | `PROJ_LDFLAGS` | Add a linker flag to the build | **Use the `+=` operator with this variable**. Flags can be passed to the linker with this option. See [GCC Options for Linking](https://gcc.gnu.org/onlinedocs/gcc/Link-Options.html#Link-Options) | -#### Build Variables for Arm Cortex-M4 Cores +#### Build Variables for Arm Cores The following build variables are used to control options specific to the Arm Cortex-M4 core available. They are available on all microcontrollers, and for all projects unless that project is built for a RISC-V core. @@ -1761,6 +1761,8 @@ The following build variables are used to control options specific to the Arm Co | `MFLOAT_ABI` | Set the floating point acceleration level | Sets the floating-point acceleration level. Permitted values are `hard`, `soft`, and `softfp` (default). To enable full hardware acceleration instructions, use `hard`, but keep in mind that _all_ libraries your source code uses must also be compiled with `hard`. If there is any conflict, you'll get a linker error. For more details, see `-mfloat-abi` under [ARM Options](https://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html). | | `DEFAULT_OPTIMIZE_FLAGS` | Override the default extra optimization flags | Extra compiler optimization flags are added to the build. They are defined in `Libraries/CMSIS/Device/Maxim/GCC/gcc.mk`. These can be disabled entirely by setting this variable to empty (`DEFAULT_OPTIMIZE_FLAGS=`). | | `DEFAULT_WARNING_FLAGS` | Override the default warning flags | Default flags controlling warning output are added in `Libraries/CMSIS/Device/Maxim/GCC/gcc.mk`. These can be disabled entirely by setting this variable to empty (`DEFAULT_OPTIMIZE_FLAGS=`). | +| `MCPU` | Set the processor type | Set the target ARM processor. Directly maps to `-mcpu` under [ARM Options](https://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html). This flag is handled by the MSDK and not typically changed manually. | +| `MFPU` | Set the FPU architecture | Set the floating point unit (FPU) architecture. Directly maps to `-mfpu` under [ARM Options](https://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html). This flag is handled by the MSDK and not typically changed manually. | #### Build Variables for RISC-V Cores From 5061c3baedfd2830a4208f9a09f60d5277efba7d Mon Sep 17 00:00:00 2001 From: Jake Carter Date: Thu, 18 Apr 2024 16:41:59 -0600 Subject: [PATCH 02/93] Add starter/placeholder ME30 files --- .../Boards/MAX32657/EvKit_V1/Include/board.h | 90 ++++ .../Boards/MAX32657/EvKit_V1/Source/board.c | 117 +++++ .../Boards/MAX32657/EvKit_V1/adapters.txt | 2 + Libraries/Boards/MAX32657/EvKit_V1/board.mk | 43 ++ .../Boards/MAX32657/EvKit_V1/examples.txt | 1 + Libraries/Boards/MAX32657/EvKit_V1/target.txt | 1 + .../Device/Maxim/MAX32657/Include/max32657.h | 32 ++ .../Maxim/MAX32657/Source/GCC/max32657.ld | 197 +++++++++ .../Maxim/MAX32657/Source/GCC/max32657.mk | 127 ++++++ .../MAX32657/Source/GCC/startup_max32657.S | 195 +++++++++ .../CMSIS/Device/Maxim/MAX32657/Source/heap.c | 50 +++ .../Maxim/MAX32657/Source/system_max32657.c | 19 + .../PeriphDrivers/Include/MAX32657/mxc.h | 72 ++++ .../Include/MAX32657/mxc_assert.h | 94 ++++ .../Include/MAX32657/mxc_delay.h | 146 +++++++ .../Include/MAX32657/mxc_device.h | 52 +++ .../Include/MAX32657/mxc_errors.h | 80 ++++ .../PeriphDrivers/Include/MAX32657/mxc_lock.h | 78 ++++ .../PeriphDrivers/Include/MAX32657/mxc_pins.h | 31 ++ .../PeriphDrivers/Include/MAX32657/mxc_sys.h | 408 ++++++++++++++++++ .../Include/MAX32657/nvic_table.h | 111 +++++ Libraries/PeriphDrivers/max32657_files.mk | 53 +++ 22 files changed, 1999 insertions(+) create mode 100644 Libraries/Boards/MAX32657/EvKit_V1/Include/board.h create mode 100644 Libraries/Boards/MAX32657/EvKit_V1/Source/board.c create mode 100644 Libraries/Boards/MAX32657/EvKit_V1/adapters.txt create mode 100644 Libraries/Boards/MAX32657/EvKit_V1/board.mk create mode 100644 Libraries/Boards/MAX32657/EvKit_V1/examples.txt create mode 100644 Libraries/Boards/MAX32657/EvKit_V1/target.txt create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.ld create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.mk create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/startup_max32657.S create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Source/heap.c create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c create mode 100644 Libraries/PeriphDrivers/Include/MAX32657/mxc.h create mode 100644 Libraries/PeriphDrivers/Include/MAX32657/mxc_assert.h create mode 100644 Libraries/PeriphDrivers/Include/MAX32657/mxc_delay.h create mode 100644 Libraries/PeriphDrivers/Include/MAX32657/mxc_device.h create mode 100644 Libraries/PeriphDrivers/Include/MAX32657/mxc_errors.h create mode 100644 Libraries/PeriphDrivers/Include/MAX32657/mxc_lock.h create mode 100644 Libraries/PeriphDrivers/Include/MAX32657/mxc_pins.h create mode 100644 Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h create mode 100644 Libraries/PeriphDrivers/Include/MAX32657/nvic_table.h create mode 100644 Libraries/PeriphDrivers/max32657_files.mk diff --git a/Libraries/Boards/MAX32657/EvKit_V1/Include/board.h b/Libraries/Boards/MAX32657/EvKit_V1/Include/board.h new file mode 100644 index 00000000000..c656e706544 --- /dev/null +++ b/Libraries/Boards/MAX32657/EvKit_V1/Include/board.h @@ -0,0 +1,90 @@ +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/** + * @file board.h + * @brief Board support package API. + */ + +#include + +// TODO(ME30): Update this file to match first EVKIT + +#ifndef LIBRARIES_BOARDS_MAX32657_EVKIT_V1_INCLUDE_BOARD_H_ +#define LIBRARIES_BOARDS_MAX32657_EVKIT_V1_INCLUDE_BOARD_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#ifndef CONSOLE_UART +#define CONSOLE_UART 0 /// UART instance to use for console +#endif + +#ifndef CONSOLE_BAUD +#define CONSOLE_BAUD 115200 /// Console baud rate +#endif + +#ifdef LED_OFF +#undef LED_OFF +#endif +#define LED_OFF 1 /// Override inactive state of LEDs + +#ifdef LED_ON +#undef LED_ON +#endif +#define LED_ON 0 /// Override active state of LEDs + +#define LED1 0 +#define LED_RED LED1 + +#define LED2 1 +#define LED_GREEN LED2 + +/** + * \brief Initialize the BSP and board interfaces. + * \returns #E_NO_ERROR if everything is successful + */ +int Board_Init(void); + +/** + * \brief Initialize or reinitialize the console. This may be necessary if the + * system clock rate is changed. + * \returns #E_NO_ERROR if everything is successful + */ +int Console_Init(void); + +/** + * \brief Shutdown the console. + * \returns #E_NO_ERROR if everything is successful + */ +int Console_Shutdown(void); + +/** + * \brief Attempt to prepare the console for sleep. + * \returns #E_NO_ERROR if ready to sleep, #E_BUSY if not ready for sleep. + */ +int Console_PrepForSleep(void); + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_BOARDS_MAX32657_EVKIT_V1_INCLUDE_BOARD_H_ diff --git a/Libraries/Boards/MAX32657/EvKit_V1/Source/board.c b/Libraries/Boards/MAX32657/EvKit_V1/Source/board.c new file mode 100644 index 00000000000..4d02252ff00 --- /dev/null +++ b/Libraries/Boards/MAX32657/EvKit_V1/Source/board.c @@ -0,0 +1,117 @@ +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#include +#include "mxc_device.h" +#include "mxc_sys.h" +#include "mxc_assert.h" +#include "board.h" +#include "uart.h" +#include "gpio.h" +#include "mxc_pins.h" +#include "led.h" +#include "pb.h" + +/***** Global Variables *****/ +mxc_uart_regs_t *ConsoleUart = MXC_UART_GET_UART(CONSOLE_UART); +extern uint32_t SystemCoreClock; + +// clang-format off +const mxc_gpio_cfg_t pb_pin[] = { + // TODO(ME30): Add push-buttons +}; +const unsigned int num_pbs = (sizeof(pb_pin) / sizeof(mxc_gpio_cfg_t)); + +const mxc_gpio_cfg_t led_pin[] = { + // TODO(ME30): Add LEDs +}; +const unsigned int num_leds = (sizeof(led_pin) / sizeof(mxc_gpio_cfg_t)); +// clang-format on + +/***** File Scope Variables *****/ + +/******************************************************************************/ +void mxc_assert(const char *expr, const char *file, int line) +{ + printf("MXC_ASSERT %s #%d: (%s)\n", file, line, expr); + + while (1) {} +} + +/******************************************************************************/ +/** + * NOTE: This weak definition is included to support Push Button interrupts in + * case the user does not define this interrupt handler in their application. + **/ +__weak void GPIO0_IRQHandler(void) +{ + MXC_GPIO_Handler(MXC_GPIO_GET_IDX(MXC_GPIO0)); +} + +/******************************************************************************/ +int Board_Init(void) +{ + int err; + + if ((err = Console_Init()) < E_NO_ERROR) { + return err; + } + + if ((err = PB_Init()) != E_NO_ERROR) { + MXC_ASSERT_FAIL(); + return err; + } + + if ((err = LED_Init()) != E_NO_ERROR) { + MXC_ASSERT_FAIL(); + return err; + } + + return E_NO_ERROR; +} + +/******************************************************************************/ +int Console_Init(void) +{ + int err; + + if ((err = MXC_UART_Init(ConsoleUart, CONSOLE_BAUD, MXC_UART_APB_CLK)) != E_NO_ERROR) { + return err; + } + + return E_NO_ERROR; +} + +int Console_Shutdown(void) +{ + int err; + + if ((err = MXC_UART_Shutdown(ConsoleUart)) != E_NO_ERROR) { + return err; + } + + return E_NO_ERROR; +} + +/******************************************************************************/ +void NMI_Handler(void) +{ + __NOP(); +} diff --git a/Libraries/Boards/MAX32657/EvKit_V1/adapters.txt b/Libraries/Boards/MAX32657/EvKit_V1/adapters.txt new file mode 100644 index 00000000000..9ee4ed2a720 --- /dev/null +++ b/Libraries/Boards/MAX32657/EvKit_V1/adapters.txt @@ -0,0 +1,2 @@ +CMSIS-DAP, interface/cmsis-dap.cfg +MAX32625_PICO, interface/cmsis-dap.cfg \ No newline at end of file diff --git a/Libraries/Boards/MAX32657/EvKit_V1/board.mk b/Libraries/Boards/MAX32657/EvKit_V1/board.mk new file mode 100644 index 00000000000..246fa72e684 --- /dev/null +++ b/Libraries/Boards/MAX32657/EvKit_V1/board.mk @@ -0,0 +1,43 @@ +############################################################################### + # + # Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + # Analog Devices, Inc.), + # Copyright (C) 2023-2024 Analog Devices, Inc. + # + # Licensed under the Apache License, Version 2.0 (the "License"); + # you may not use this file except in compliance with the License. + # You may obtain a copy of the License at + # + # http://www.apache.org/licenses/LICENSE-2.0 + # + # Unless required by applicable law or agreed to in writing, software + # distributed under the License is distributed on an "AS IS" BASIS, + # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + # See the License for the specific language governing permissions and + # limitations under the License. + # + ############################################################################## + +ifeq "$(BOARD_DIR)" "" +BOARD_DIR := $(dir $(abspath $(lastword $(MAKEFILE_LIST)))) +endif + +# Source files for this test (add path to VPATH below) +SRCS += board.c +SRCS += stdio.c +SRCS += led.c +SRCS += pb.c + +MISC_DRIVERS_DIR ?= $(MAXIM_PATH)/Libraries/MiscDrivers + +# Where to find BSP source files +VPATH += $(BOARD_DIR)/Source +VPATH += $(MISC_DRIVERS_DIR) +VPATH += $(MISC_DRIVERS_DIR)/LED +VPATH += $(MISC_DRIVERS_DIR)/PushButton + +# Where to find BSP header files +IPATH += $(BOARD_DIR)/Include +IPATH += $(MISC_DRIVERS_DIR) +IPATH += $(MISC_DRIVERS_DIR)/LED +IPATH += $(MISC_DRIVERS_DIR)/PushButton diff --git a/Libraries/Boards/MAX32657/EvKit_V1/examples.txt b/Libraries/Boards/MAX32657/EvKit_V1/examples.txt new file mode 100644 index 00000000000..b74d7d85b6a --- /dev/null +++ b/Libraries/Boards/MAX32657/EvKit_V1/examples.txt @@ -0,0 +1 @@ +TODO: Add list of supported examples diff --git a/Libraries/Boards/MAX32657/EvKit_V1/target.txt b/Libraries/Boards/MAX32657/EvKit_V1/target.txt new file mode 100644 index 00000000000..22a5ea5b254 --- /dev/null +++ b/Libraries/Boards/MAX32657/EvKit_V1/target.txt @@ -0,0 +1 @@ +max32657.cfg diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h new file mode 100644 index 00000000000..eb008889d52 --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h @@ -0,0 +1,32 @@ +/** + * @file max32657.h + * @brief Device-specific perhiperal header file + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_MAX32657_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_MAX32657_H_ + +// TODO(ME30): Top-level device header file +// TODO(ME30): Place max32657.svd file next to this one + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_MAX32660_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.ld b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.ld new file mode 100644 index 00000000000..695e2f01d09 --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.ld @@ -0,0 +1,197 @@ +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +MEMORY { + ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x00010000 /* 64kB ROM */ + FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000 /* 512KB Flash */ + SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 /* 128kB SRAM */ +} + +SECTIONS { + .rom : + { + KEEP(*(.rom_vector)) + *(.rom_handlers*) + } > ROM + + .text : + { + _text = .; + KEEP(*(.isr_vector)) + EXCLUDE_FILE (*riscv.o) *(.text*) /* Program code (exclude RISCV code) */ + *(.rodata*) /* read-only data: "const" */ + + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + /* C++ Exception handling */ + KEEP(*(.eh_frame*)) + _etext = .; + } > FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + /* Binary import */ + .bin_storage : + { + FILL(0xFF) + _bin_start_ = .; + KEEP(*(.bin_storage_img)) + _bin_end_ = .; + . = ALIGN(4); + } > FLASH + + .rom_code : + { + . = ALIGN(16); + _sran_code = .; + *(.rom_code_section) + _esran_code = .; + } > ROM + + .flash_code : + { + . = ALIGN(16); + _sran_code = .; + *(.flash_code_section) + _esran_code = .; + } > FLASH + + .sram_code : + { + . = ALIGN(16); + _sran_code = .; + *(.sram_code_section) + _esran_code = .; + } > SRAM + + /* it's used for C++ exception handling */ + /* we need to keep this to avoid overlapping */ + .ARM.exidx : + { + __exidx_start = .; + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + __exidx_end = .; + } > FLASH + + .data : + { + _data = ALIGN(., 4); + *(vtable) + *(.data*) /*read-write initialized data: initialized global variable*/ + *(.flashprog*) /* Flash program */ + + /* These array sections are used by __libc_init_array to call static C++ constructors */ + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + _edata = ALIGN(., 4); + } > SRAM AT>FLASH + __load_data = LOADADDR(.data); + + .bss : + { + . = ALIGN(4); + _bss = .; + *(.bss*) /*read-write zero initialized data: uninitialzed global variable*/ + *(COMMON) + _ebss = ALIGN(., 4); + } > SRAM + + .shared : + { + . = ALIGN(4); + _shared = .; + *(.mailbox*) + . = ALIGN(4); + *(.shared*) /*read-write zero initialized data: uninitialzed global variable*/ + _eshared = ALIGN(., 4); + } > SRAM AT>FLASH + __shared_data = LOADADDR(.shared); + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(SRAM) + LENGTH(SRAM); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (COPY): + { + *(.stack*) + } > SRAM + + .heap (COPY): + { + . = ALIGN(4); + *(.heap*) + __HeapLimit = ABSOLUTE(__StackLimit); + } > SRAM + + PROVIDE(__stack = __StackTop); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack") + + /* Section used by RISCV loader projects. See RISCV_LOAD documentation in the build system. */ + .riscv_flash : + { + /* Align address to mod 256 with a small offset. This is required to match the flash page size.*/ + . = ALIGN(256); /* ALIGN operatator is used here. Note that (. & 0x1FFFFF00) was used in the past, but a strange bug was seen on Windows where the & did not behave as expected.*/ + . += 0x100; + _riscv_boot = .; + KEEP(*riscv.o (.text*)) + } > FLASH +} diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.mk b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.mk new file mode 100644 index 00000000000..82b06cb91aa --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.mk @@ -0,0 +1,127 @@ +############################################################################### + # + # Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + # Analog Devices, Inc.), + # Copyright (C) 2023-2024 Analog Devices, Inc. + # + # Licensed under the Apache License, Version 2.0 (the "License"); + # you may not use this file except in compliance with the License. + # You may obtain a copy of the License at + # + # http://www.apache.org/licenses/LICENSE-2.0 + # + # Unless required by applicable law or agreed to in writing, software + # distributed under the License is distributed on an "AS IS" BASIS, + # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + # See the License for the specific language governing permissions and + # limitations under the License. + # + ############################################################################## + +ifeq "$(CMSIS_ROOT)" "" +# If CMSIS_ROOT is not specified, this Makefile will calculate CMSIS_ROOT relative to itself. +GCC_DIR := $(dir $(abspath $(lastword $(MAKEFILE_LIST)))) +CMSIS_ROOT := $(abspath $(GCC_DIR)../../../../..) +endif + +TARGET_UC:=MAX32657 +TARGET_LC:=max32657 + +# The build directory +ifeq "$(BUILD_DIR)" "" +ifeq "$(RISCV_CORE)" "" +BUILD_DIR=$(CURDIR)/build +else +BUILD_DIR=$(CURDIR)/buildrv +endif +endif + +STARTUPFILE ?= startup_$(TARGET_LC).S + +################################################################################ +# Detect target OS +# windows : native windows +# windows_msys : MSYS2 on windows +# windows_cygwin : Cygwin on windows (legacy config from old sdk) +# linux : Any linux distro +# macos : MacOS +ifeq "$(OS)" "Windows_NT" +_OS = windows + +UNAME_RESULT := $(shell uname -s 2>&1) +# MSYS2 may be present on Windows. In this case, +# linux utilities should be used. However, the OS environment +# variable will still be set to Windows_NT since we configure +# MSYS2 to inherit from Windows by default. +# Here we'll attempt to call uname (only present on MSYS2) +# while routing stderr -> stdout to avoid throwing an error +# if uname can't be found. +ifneq ($(findstring CYGWIN, $(UNAME_RESULT)), ) +CYGWIN=True +_OS = windows_cygwin +endif + +ifneq ($(findstring MSYS, $(UNAME_RESULT)), ) +MSYS=True +_OS = windows_msys +endif +ifneq ($(findstring MINGW, $(UNAME_RESULT)), ) +MSYS=True +_OS = windows_msys +endif + +else # OS + +UNAME_RESULT := $(shell uname -s) +ifeq "$(UNAME_RESULT)" "Linux" +_OS = linux +endif +ifeq "$(UNAME_RESULT)" "Darwin" +_OS = macos +endif + +endif + +################################################################################ + +# Default linkerfile +LINKERFILE ?= $(CMSIS_ROOT)/Device/Maxim/$(TARGET_UC)/Source/GCC/$(TARGET_LC).ld + +# Default entry-point +ENTRY ?= Reset_Handler + +# Default TARGET_REVISION +# "A1" in ASCII +ifeq "$(TARGET_REV)" "" +TARGET_REV=0x4131 +endif + +# Add target specific CMSIS source files +ifneq (${MAKECMDGOALS},lib) +SRCS += ${STARTUPFILE} +SRCS += heap.c +SRCS += system_$(TARGET_LC).c +endif + +# Add target specific CMSIS source directories +VPATH+=$(CMSIS_ROOT)/Device/Maxim/$(TARGET_UC)/Source/GCC +VPATH+=$(CMSIS_ROOT)/Device/Maxim/$(TARGET_UC)/Source + +# Add target specific CMSIS include directories +IPATH+=$(CMSIS_ROOT)/Device/Maxim/$(TARGET_UC)/Include + +# Add CMSIS Core files +CMSIS_VER ?= 5.9.0 +IPATH+=$(CMSIS_ROOT)/$(CMSIS_VER)/Core/Include + +# Add directory with linker include file +LIBPATH+=$(CMSIS_ROOT)/Device/Maxim/$(TARGET_UC)/Source/GCC + +# Set target architecture +MCPU := cortex-m33 + +# Include the rules and goals for building +include $(CMSIS_ROOT)/Device/Maxim/GCC/gcc.mk + +# Include rules for flashing +include $(CMSIS_ROOT)/../../Tools/Flash/flash.mk diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/startup_max32657.S b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/startup_max32657.S new file mode 100644 index 00000000000..4bad29772e9 --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/startup_max32657.S @@ -0,0 +1,195 @@ +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + + .syntax unified + .arch armv8-m + + .section .stack + .align 3 +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + // TODO: Update max stack size + .equ Stack_Size, 0x00001000 +#endif + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + .section .heap + .align 3 +#ifdef __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE +#else + // TODO: Update max heap size + .equ Heap_Size, 0x00000C00 +#endif + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .if Heap_Size + .space Heap_Size + .endif + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + + # TODO: Validate arch-specific handler layout + .section .isr_vector + .align 9 /* must be aligned to 512 byte boundary. VTOR requirement */ + .globl __isr_vector +__isr_vector: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + // TODO: Add device-specific interrupt table + /* Device-specific Interrupts */ + .long RSVXX_IRQHandler /* 0xXX 0xXXXX XX: Reserved */ + + .text + .thumb + .thumb_func + .align 2 + .globl Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =__StackTop + mov sp, r0 + + /* PreInit runs before any RAM initialization. Example usage: DDR setup, etc. */ + ldr r0, =PreInit + blx r0 + cbnz r0, .SKIPRAMINIT + +/* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __load_data: Where data sections are saved. + * _data /_edata: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__load_data + ldr r2, =_data + ldr r3, =_edata + +#if 0 +/* Here are two copies of loop implemenations. First one favors code size + * and the second one favors performance. Default uses the first one. + * Change to "#if 0" to use the second one */ +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 +#else + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: +#endif + +/* + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * _bss : start of BSS section. Must align to 4 + * _ebss : end of BSS section. Must align to 4 + */ + ldr r1, =_bss + ldr r2, =_ebss + + movs r0, 0 +.LC2: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC2 + +.SKIPRAMINIT: + + /* Perform system initialization after RAM initialization */ + ldr r0, =SystemInit + blx r0 + + /* This must be called to walk the constructor array for static C++ objects */ + /* Note: The linker file must have .data symbols for __X_array_start and __X_array_end */ + /* where X is {preinit, init, fini} */ + ldr r0, =__libc_init_array + blx r0 + + /* Transfer control to user's main program */ + ldr r0, =main + blx r0 + +.SPIN: + /* spin if main ever returns. */ + bl .SPIN + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + .macro def_irq_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + + // TODO: Update to match arch-specific handlers above + def_irq_handler NMI_Handler + def_irq_handler HardFault_Handler + def_irq_handler MemManage_Handler + def_irq_handler BusFault_Handler + def_irq_handler UsageFault_Handler + def_irq_handler SVC_Handler + def_irq_handler DebugMon_Handler + def_irq_handler PendSV_Handler + def_irq_handler SysTick_Handler + def_irq_handler Default_Handler + + // TODO: Add default device-specific handlers to match above + /* Device-specific Interrupts */ + def_irq_handler RSVXX_IRQHandler /* 0xXX 0xXXXX XX: Reserved */ + .end diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/heap.c b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/heap.c new file mode 100644 index 00000000000..80559e95034 --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/heap.c @@ -0,0 +1,50 @@ +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#include +#include +#include + +/* + sbrk + Increase program data space. + Malloc and related functions depend on this + */ +static char *heap_end = 0; +extern unsigned int __HeapBase; +extern unsigned int __HeapLimit; +caddr_t _sbrk(int incr) +{ + char *prev_heap_end; + + if (heap_end == 0) { + heap_end = (caddr_t)&__HeapBase; + } + prev_heap_end = heap_end; + + if ((unsigned int)(heap_end + incr) > (unsigned int)&__HeapLimit) { + errno = ENOMEM; + return (caddr_t)-1; + } + + heap_end += incr; + + return (caddr_t)prev_heap_end; +} diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c new file mode 100644 index 00000000000..5b3c0874344 --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c @@ -0,0 +1,19 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +// TODO(ME30): System implementation diff --git a/Libraries/PeriphDrivers/Include/MAX32657/mxc.h b/Libraries/PeriphDrivers/Include/MAX32657/mxc.h new file mode 100644 index 00000000000..666f6bbbb55 --- /dev/null +++ b/Libraries/PeriphDrivers/Include/MAX32657/mxc.h @@ -0,0 +1,72 @@ +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX78000_MXC_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX78000_MXC_H_ + +#ifdef __riscv +// TODO(JC): This is a somewhat ugly hack added to avoid +// implicit function warnings on RISC-V projects +// when LIB_BOARD was added to libs.mk. When the +// RISC-V build system is improved to use libs.mk +// this should be removed. +#ifndef LIB_BOARD +#define LIB_BOARD +#endif +#endif + +#include "mxc_device.h" +#include "mxc_delay.h" +#include "mxc_assert.h" +#include "mxc_errors.h" +#include "mxc_lock.h" +#include "mxc_pins.h" +#include "mxc_sys.h" +#include "nvic_table.h" +#ifdef LIB_BOARD +#include "board.h" +#endif + +/* + * Peripheral Driver Includes + */ +#include "adc.h" +#include "aes.h" +#include "cameraif.h" +#include "crc.h" +#include "dma.h" +#include "flc.h" +#include "gpio.h" +#include "i2c.h" +#include "i2s.h" +#include "icc.h" +#include "lp.h" +#include "owm.h" +#include "pt.h" +#include "rtc.h" +#include "sema.h" +#include "spi.h" +#include "tmr.h" +#include "trng.h" +#include "uart.h" +#include "wdt.h" +#include "wut.h" + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX78000_MXC_H_ diff --git a/Libraries/PeriphDrivers/Include/MAX32657/mxc_assert.h b/Libraries/PeriphDrivers/Include/MAX32657/mxc_assert.h new file mode 100644 index 00000000000..d5f490d0934 --- /dev/null +++ b/Libraries/PeriphDrivers/Include/MAX32657/mxc_assert.h @@ -0,0 +1,94 @@ +/** + * @file + * @brief Assertion checks for debugging. + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* Define to prevent redundant inclusion */ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_ASSERT_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_ASSERT_H_ + +/* **** Includes **** */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @ingroup syscfg + * @defgroup mxc_assertions Assertion Checks for Debugging + * @brief Assertion checks for debugging. + * @{ + */ +/* **** Definitions **** */ +/** + * @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be + * defined. + */ +///@cond +#ifdef MXC_ASSERT_ENABLE +/** + * Macro that checks the expression for true and generates an assertion. + * @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be + * defined. + */ +#define MXC_ASSERT(expr) \ + if (!(expr)) { \ + mxc_assert(#expr, __FILE__, __LINE__); \ + } +/** + * Macro that generates an assertion with the message "FAIL". + * @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be + * defined. + */ +#define MXC_ASSERT_FAIL() mxc_assert("FAIL", __FILE__, __LINE__); +#else +#define MXC_ASSERT(expr) +#define MXC_ASSERT_FAIL() +#endif +///@endcond +/* **** Globals **** */ + +/* **** Function Prototypes **** */ + +/** + * @brief Assert an error when the given expression fails during debugging. + * @param expr String with the expression that failed the assertion. + * @param file File containing the failed assertion. + * @param line Line number for the failed assertion. + * @note This is defined as a weak function and can be overridden at the + * application layer to print the debugging information. + * @code + * printf("%s, file: %s, line %d\n", expr, file, line); + * @endcode + * @note To use debug assertions, the symbol @c MXC_ASSERT_ENABLE must be + * defined. + */ +void mxc_assert(const char *expr, const char *file, int line); + +/**@} end of group MXC_Assertions*/ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_ASSERT_H_ diff --git a/Libraries/PeriphDrivers/Include/MAX32657/mxc_delay.h b/Libraries/PeriphDrivers/Include/MAX32657/mxc_delay.h new file mode 100644 index 00000000000..e88d315a4ea --- /dev/null +++ b/Libraries/PeriphDrivers/Include/MAX32657/mxc_delay.h @@ -0,0 +1,146 @@ +/** + * @file + * @brief Asynchronous delay routines based on the SysTick Timer. +*/ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* Define to prevent redundant inclusion */ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_DELAY_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_DELAY_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @ingroup devicelibs + * @defgroup MXC_delay Delay Utility Functions + * @brief Asynchronous delay routines based on the SysTick Timer + * @{ + */ + +/***** Definitions *****/ +/** + * Macro used to specify a microsecond timing parameter in seconds. + * \code + * x = SEC(3) // 3 seconds -> x = 3,000,000 + * \endcode + */ +#define MXC_DELAY_SEC(s) (((uint32_t)s) * 1000000UL) +/** + * Macro used to specify a microsecond timing parameter in milliseconds. + * \code + * x = MSEC(3) // 3ms -> x = 3,000 + * \endcode + */ +#define MXC_DELAY_MSEC(ms) (ms * 1000UL) +/** + * Macro used to specify a microsecond timing parameter. + * \code + * x = USEC(3) // 3us -> x = 3 + * \endcode + */ +#define MXC_DELAY_USEC(us) (us) + +/** + * @brief The callback routine used by MXC_DelayAsync() when the delay is complete + * or aborted early. + * + * @param result See \ref MXC_Error_Codes for the list of error codes. + */ +typedef void (*mxc_delay_complete_t)(int result); + +#ifdef __riscv + +/** + * @brief Blocks and delays for the specified number of microseconds. + * @details Uses the Performance Counter to create the requested delay. The current + * and settings of the performance counter registers will be destroyed. + * @param us microseconds to delay + * @return #E_NO_ERROR if no errors, @ref MXC_Error_Codes "error" if unsuccessful. + */ +int MXC_Delay(uint32_t us); + +int MXC_DelayAsync(uint32_t us, mxc_delay_complete_t callback); +int MXC_DelayCheck(void); +void MXC_DelayAbort(void); + +#else + +/***** Function Prototypes *****/ + +/** + * @brief Blocks and delays for the specified number of microseconds. + * @details Uses the SysTick to create the requested delay. If the SysTick is + * running, the current settings will be used. If the SysTick is not + * running, it will be started. + * @param us microseconds to delay + * @return #E_NO_ERROR if no errors, @ref MXC_Error_Codes "error" if unsuccessful. + */ +int MXC_Delay(uint32_t us); + +/** + * @brief Starts a non-blocking delay for the specified number of + * microseconds. + * @details Uses the SysTick to time the requested delay. If the SysTick is + * running, the current settings will be used. If the SysTick is not + * running, it will be started. + * @note MXC_Delay_handler() must be called from the SysTick interrupt service + * routine or at a rate greater than the SysTick overflow rate. + * @param us microseconds to delay + * @param callback Function pointer to the function to call after the delay has expired. + * @return #E_NO_ERROR if no errors, #E_BUSY if currently servicing another + * delay request. + */ +int MXC_DelayAsync(uint32_t us, mxc_delay_complete_t callback); + +/** + * @brief Returns the status of a non-blocking delay request + * @pre Start the asynchronous delay by calling MXC_Delay_start(). + * @return #E_BUSY until the requested delay time has expired. + */ +int MXC_DelayCheck(void); + +/** + * @brief Stops an asynchronous delay previously started. + * @pre Start the asynchronous delay by calling MXC_Delay_start(). + */ +void MXC_DelayAbort(void); + +/** + * @brief Processes the delay interrupt. + * @details This function must be called from the SysTick IRQ or polled at a + * rate greater than the SysTick overflow rate. + */ +void MXC_DelayHandler(void); + +/**@} end of group MXC_delay */ + +#endif /* __riscv */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_DELAY_H_ diff --git a/Libraries/PeriphDrivers/Include/MAX32657/mxc_device.h b/Libraries/PeriphDrivers/Include/MAX32657/mxc_device.h new file mode 100644 index 00000000000..5f19c29c894 --- /dev/null +++ b/Libraries/PeriphDrivers/Include/MAX32657/mxc_device.h @@ -0,0 +1,52 @@ +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_DEVICE_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_DEVICE_H_ + +#include "max32657.h" +#include "mxc_errors.h" +#include "mxc_pins.h" + +#ifndef TARGET +#error TARGET NOT DEFINED +#endif + +// Create a string definition for the TARGET +#define STRING_ARG(arg) #arg +#define STRING_NAME(name) STRING_ARG(name) +#define TARGET_NAME STRING_NAME(TARGET) + +// Define which revisions of the IP we are using +#ifndef TARGET_REV +#error TARGET_REV NOT DEFINED +#endif + +#if (TARGET_REV == 0x4131) +// A1 +#define MXC_TMR_REV 0 +#define MXC_UART_REV 0 +#else + +#error TARGET_REV NOT SUPPORTED + +#endif /* if(TARGET_REV == ...) */ + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_DEVICE_H_ diff --git a/Libraries/PeriphDrivers/Include/MAX32657/mxc_errors.h b/Libraries/PeriphDrivers/Include/MAX32657/mxc_errors.h new file mode 100644 index 00000000000..125e3b9fca3 --- /dev/null +++ b/Libraries/PeriphDrivers/Include/MAX32657/mxc_errors.h @@ -0,0 +1,80 @@ +/** + * @file + * @brief List of common error return codes for Maxim Integrated libraries. +*/ +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* Define to prevent redundant inclusion */ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_ERRORS_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_ERRORS_H_ + +/** + * @ingroup syscfg + * @defgroup MXC_Error_Codes Error Codes + * @brief A list of common error codes used by the API. + * @note A Negative Error Convention is used to avoid conflict with + * positive, Non-Error, returns. + * @{ + */ + +/** No Error */ +#define E_NO_ERROR 0 +/** No Error, success */ +#define E_SUCCESS 0 +/** Pointer is NULL */ +#define E_NULL_PTR -1 +/** No such device */ +#define E_NO_DEVICE -2 +/** Parameter not acceptable */ +#define E_BAD_PARAM -3 +/** Value not valid or allowed */ +#define E_INVALID -4 +/** Module not initialized */ +#define E_UNINITIALIZED -5 +/** Busy now, try again later */ +#define E_BUSY -6 +/** Operation not allowed in current state */ +#define E_BAD_STATE -7 +/** Generic error */ +#define E_UNKNOWN -8 +/** General communications error */ +#define E_COMM_ERR -9 +/** Operation timed out */ +#define E_TIME_OUT -10 +/** Expected response did not occur */ +#define E_NO_RESPONSE -11 +/** Operations resulted in unexpected overflow */ +#define E_OVERFLOW -12 +/** Operations resulted in unexpected underflow */ +#define E_UNDERFLOW -13 +/** Data or resource not available at this time */ +#define E_NONE_AVAIL -14 +/** Event was shutdown */ +#define E_SHUTDOWN -15 +/** Event was aborted */ +#define E_ABORT -16 +/** The requested operation is not supported */ +#define E_NOT_SUPPORTED -17 +/** The requested operation is failed */ +#define E_FAIL -255 +/**@} end of MXC_Error_Codes group */ + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_ERRORS_H_ diff --git a/Libraries/PeriphDrivers/Include/MAX32657/mxc_lock.h b/Libraries/PeriphDrivers/Include/MAX32657/mxc_lock.h new file mode 100644 index 00000000000..4b53f368493 --- /dev/null +++ b/Libraries/PeriphDrivers/Include/MAX32657/mxc_lock.h @@ -0,0 +1,78 @@ +/** + * @file + * @brief Exclusive access lock utility functions. +*/ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* Define to prevent redundant inclusion */ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_LOCK_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_LOCK_H_ + +/* **** Includes **** */ +#include "mxc_device.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @ingroup syscfg + * @defgroup mxc_lock_utilities Exclusive Access Locks + * @brief Lock functions to obtain and release a variable for exclusive + * access. These functions are marked interrupt safe if they are + * interrupt safe. + * @{ + */ + +/* **** Definitions **** */ + +/* **** Globals **** */ + +/* **** Function Prototypes **** */ + +/** + * @brief Attempts to acquire the lock. + * @details This in an interrupt safe function that can be used as a mutex. + * The lock variable must remain in scope until the lock is + * released. Will not block if another thread has already acquired + * the lock. + * @param lock Pointer to variable that is used for the lock. + * @param value Value to be place in the lock. Can not be 0. + * + * @return #E_NO_ERROR if everything successful, #E_BUSY if lock is taken. + */ +int MXC_GetLock(uint32_t *lock, uint32_t value); + +/** + * @brief Free the given lock. + * @param[in,out] lock Pointer to the variable used for the lock. When the lock + * is free, the value pointed to by @p lock is set to zero. + */ +void MXC_FreeLock(uint32_t *lock); + +/**@} end of group mxc_lock_utilities */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_LOCK_H_ diff --git a/Libraries/PeriphDrivers/Include/MAX32657/mxc_pins.h b/Libraries/PeriphDrivers/Include/MAX32657/mxc_pins.h new file mode 100644 index 00000000000..7a5dab91d6e --- /dev/null +++ b/Libraries/PeriphDrivers/Include/MAX32657/mxc_pins.h @@ -0,0 +1,31 @@ +/** + * @file mxc_pins.h + * @brief This file contains constant pin configurations for the peripherals. + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_PINS_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_PINS_H_ + +#include "gpio.h" + +// TODO(ME30) diff --git a/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h b/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h new file mode 100644 index 00000000000..ded3b795ffa --- /dev/null +++ b/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h @@ -0,0 +1,408 @@ +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/** + * @file mxc_sys.h + * @brief System level header file. + */ + +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_SYS_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_SYS_H_ + +#include "mxc_device.h" +#include "lpgcr_regs.h" +#include "gcr_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup mxc_sys System Configuration (MXC_SYS) + * @ingroup syscfg + * @details API for system configuration including clock source selection and entering critical sections of code. + * @{ + */ + +/** @brief System reset0 and reset1 enumeration. Used in MXC_SYS_PeriphReset0 function */ +typedef enum { + MXC_SYS_RESET0_DMA = MXC_F_GCR_RST0_DMA_POS, /**< Reset DMA */ + MXC_SYS_RESET0_WDT0 = MXC_F_GCR_RST0_WDT0_POS, /**< Reset WDT */ + MXC_SYS_RESET0_GPIO0 = MXC_F_GCR_RST0_GPIO0_POS, /**< Reset GPIO0 */ + MXC_SYS_RESET0_GPIO1 = MXC_F_GCR_RST0_GPIO1_POS, /**< Reset GPIO1 */ + MXC_SYS_RESET0_TMR0 = MXC_F_GCR_RST0_TMR0_POS, /**< Reset TMR0 */ + MXC_SYS_RESET0_TMR1 = MXC_F_GCR_RST0_TMR1_POS, /**< Reset TMR1 */ + MXC_SYS_RESET0_TMR2 = MXC_F_GCR_RST0_TMR2_POS, /**< Reset TMR2 */ + MXC_SYS_RESET0_TMR3 = MXC_F_GCR_RST0_TMR3_POS, /**< Reset TMR3 */ + MXC_SYS_RESET0_UART0 = MXC_F_GCR_RST0_UART0_POS, /**< Reset UART0 */ + MXC_SYS_RESET0_UART1 = MXC_F_GCR_RST0_UART1_POS, /**< Reset UART1 */ + MXC_SYS_RESET0_SPI1 = MXC_F_GCR_RST0_SPI1_POS, /**< Reset SPI1 */ + MXC_SYS_RESET0_I2C0 = MXC_F_GCR_RST0_I2C0_POS, /**< Reset I2C0 */ + MXC_SYS_RESET0_RTC = MXC_F_GCR_RST0_RTC_POS, /**< Reset RTC */ + MXC_SYS_RESET0_SMPHR = MXC_F_GCR_RST0_SMPHR_POS, /**< Reset SMPHR */ + MXC_SYS_RESET0_TRNG = MXC_F_GCR_RST0_TRNG_POS, /**< Reset TRNG */ + MXC_SYS_RESET0_CNN = MXC_F_GCR_RST0_CNN_POS, /**< Reset CNN */ + MXC_SYS_RESET0_ADC = MXC_F_GCR_RST0_ADC_POS, /**< Reset ADC */ + MXC_SYS_RESET0_UART2 = MXC_F_GCR_RST0_UART2_POS, /**< Reset UART2 */ + MXC_SYS_RESET0_SOFT = MXC_F_GCR_RST0_SOFT_POS, /**< Soft reset */ + MXC_SYS_RESET0_PERIPH = MXC_F_GCR_RST0_PERIPH_POS, /**< Peripheral reset */ + MXC_SYS_RESET0_SYS = MXC_F_GCR_RST0_SYS_POS, /**< System reset */ + /* RESET1 Below this line we add 32 to separate RESET0 and RESET1 */ + MXC_SYS_RESET1_I2C1 = (MXC_F_GCR_RST1_I2C1_POS + 32), /**< Reset I2C1 */ + MXC_SYS_RESET1_PT = (MXC_F_GCR_RST1_PT_POS + 32), /**< Reset PT */ + MXC_SYS_RESET1_OWM = (MXC_F_GCR_RST1_OWM_POS + 32), /**< Reset OWM */ + MXC_SYS_RESET1_CRC = (MXC_F_GCR_RST1_CRC_POS + 32), /**< Reset CRC */ + MXC_SYS_RESET1_AES = (MXC_F_GCR_RST1_AES_POS + 32), /**< Reset AES */ + MXC_SYS_RESET1_SMPHR = (MXC_F_GCR_RST1_SMPHR_POS + 32), /**< Reset SMPHR */ + MXC_SYS_RESET1_I2C2 = (MXC_F_GCR_RST1_I2C2_POS + 32), /**< Reset I2C2 */ + MXC_SYS_RESET1_I2S = (MXC_F_GCR_RST1_I2S_POS + 32), /**< Reset I2S*/ + MXC_SYS_RESET1_DVS = (MXC_F_GCR_RST1_DVS_POS + 32), /**< Reset DVS */ + MXC_SYS_RESET1_SIMO = (MXC_F_GCR_RST1_SIMO_POS + 32), /**< Reset SIMO */ + MXC_SYS_RESET1_SPI0 = (MXC_F_GCR_RST1_SPI0_POS + 32), /**< Reset SPI0 */ + MXC_SYS_RESET1_CPU1 = (MXC_F_GCR_RST1_CPU1_POS + 32), /**< Reset CPU1 */ + /* LPGCR RESET Below this line we add 64 to separate LPGCR and GCR */ + MXC_SYS_RESET_GPIO2 = (MXC_F_LPGCR_RST_GPIO2_POS + 64), /**< Reset GPIO2 */ + MXC_SYS_RESET_WDT1 = (MXC_F_LPGCR_RST_WDT1_POS + 64), /**< Reset WDT1 */ + MXC_SYS_RESET_TMR4 = (MXC_F_LPGCR_RST_TMR4_POS + 64), /**< Reset TMR4 */ + MXC_SYS_RESET_TMR5 = (MXC_F_LPGCR_RST_TMR5_POS + 64), /**< Reset TMR5 */ + MXC_SYS_RESET_UART3 = (MXC_F_LPGCR_RST_UART3_POS + 64), /**< Reset UART3 */ + MXC_SYS_RESET_LPCOMP = (MXC_F_LPGCR_RST_LPCOMP_POS + 64), /**< Reset LPCOMP */ +} mxc_sys_reset_t; + +/** @brief System clock disable enumeration. Used in MXC_SYS_ClockDisable and MXC_SYS_ClockEnable functions */ +typedef enum { + MXC_SYS_PERIPH_CLOCK_GPIO0 = + MXC_F_GCR_PCLKDIS0_GPIO0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_GPIO0 clock */ + MXC_SYS_PERIPH_CLOCK_GPIO1 = + MXC_F_GCR_PCLKDIS0_GPIO1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_GPIO1 clock */ + MXC_SYS_PERIPH_CLOCK_DMA = + MXC_F_GCR_PCLKDIS0_DMA_POS, /**< Disable MXC_F_GCR_PCLKDIS0_DMA clock */ + MXC_SYS_PERIPH_CLOCK_SPI1 = + MXC_F_GCR_PCLKDIS0_SPI1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI1 clock */ + MXC_SYS_PERIPH_CLOCK_UART0 = + MXC_F_GCR_PCLKDIS0_UART0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART0 clock */ + MXC_SYS_PERIPH_CLOCK_UART1 = + MXC_F_GCR_PCLKDIS0_UART1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART1 clock */ + MXC_SYS_PERIPH_CLOCK_I2C0 = + MXC_F_GCR_PCLKDIS0_I2C0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C0 clock */ + MXC_SYS_PERIPH_CLOCK_TMR0 = + MXC_F_GCR_PCLKDIS0_TMR0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_TMR0 clock */ + MXC_SYS_PERIPH_CLOCK_TMR1 = + MXC_F_GCR_PCLKDIS0_TMR1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_TMR1 clock */ + MXC_SYS_PERIPH_CLOCK_TMR2 = + MXC_F_GCR_PCLKDIS0_TMR2_POS, /**< Disable MXC_F_GCR_PCLKDIS0_TMR2 clock */ + MXC_SYS_PERIPH_CLOCK_TMR3 = + MXC_F_GCR_PCLKDIS0_TMR3_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T3 clock */ + MXC_SYS_PERIPH_CLOCK_ADC = + MXC_F_GCR_PCLKDIS0_ADC_POS, /**< Disable MXC_F_GCR_PCLKDIS0_ADC clock */ + MXC_SYS_PERIPH_CLOCK_CNN = + MXC_F_GCR_PCLKDIS0_CNN_POS, /**< Disable MXC_F_GCR_PCLKDIS0_CNN clock */ + MXC_SYS_PERIPH_CLOCK_I2C1 = + MXC_F_GCR_PCLKDIS0_I2C1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C1 clock */ + MXC_SYS_PERIPH_CLOCK_PT = MXC_F_GCR_PCLKDIS0_PT_POS, /**< Disable MXC_F_GCR_PCLKDIS0_PT clock */ + /* PCLKDIS1 Below this line we add 32 to separate PCLKDIS0 and PCLKDIS1 */ + MXC_SYS_PERIPH_CLOCK_UART2 = + (MXC_F_GCR_PCLKDIS1_UART2_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_UART2 clock */ + MXC_SYS_PERIPH_CLOCK_TRNG = + (MXC_F_GCR_PCLKDIS1_TRNG_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_TRNG clock */ + MXC_SYS_PERIPH_CLOCK_SMPHR = + (MXC_F_GCR_PCLKDIS1_SMPHR_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_SMPHR clock */ + MXC_SYS_PERIPH_CLOCK_OWIRE = + (MXC_F_GCR_PCLKDIS1_OWM_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_OWM clock */ + MXC_SYS_PERIPH_CLOCK_CRC = + (MXC_F_GCR_PCLKDIS1_CRC_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_CRC clock */ + MXC_SYS_PERIPH_CLOCK_AES = + (MXC_F_GCR_PCLKDIS1_AES_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_AES clock */ + MXC_SYS_PERIPH_CLOCK_I2S = + (MXC_F_GCR_PCLKDIS1_I2S_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_I2S clock */ + MXC_SYS_PERIPH_CLOCK_SPI0 = + (MXC_F_GCR_PCLKDIS1_SPI0_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_SPI0 clock */ + MXC_SYS_PERIPH_CLOCK_PCIF = + (MXC_F_GCR_PCLKDIS1_PCIF_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_PCIF clock */ + MXC_SYS_PERIPH_CLOCK_I2C2 = + (MXC_F_GCR_PCLKDIS1_I2C2_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_I2C2 clock */ + MXC_SYS_PERIPH_CLOCK_WDT0 = + (MXC_F_GCR_PCLKDIS1_WDT0_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_WDT0 clock */ + MXC_SYS_PERIPH_CLOCK_CPU1 = + (MXC_F_GCR_PCLKDIS1_CPU1_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_CPU1 clock */ + /* LPGCR PCLKDIS Below this line we add 64 to seperate GCR and LPGCR registers */ + MXC_SYS_PERIPH_CLOCK_GPIO2 = + (MXC_F_LPGCR_PCLKDIS_GPIO2_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_GPIO2 clock */ + MXC_SYS_PERIPH_CLOCK_WDT1 = + (MXC_F_LPGCR_PCLKDIS_WDT1_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_WDT2 clock */ + MXC_SYS_PERIPH_CLOCK_TMR4 = + (MXC_F_LPGCR_PCLKDIS_TMR4_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_TMR4 clock */ + MXC_SYS_PERIPH_CLOCK_TMR5 = + (MXC_F_LPGCR_PCLKDIS_TMR5_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_TMR5 clock */ + MXC_SYS_PERIPH_CLOCK_UART3 = + (MXC_F_LPGCR_PCLKDIS_UART3_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_UART3 clock */ + MXC_SYS_PERIPH_CLOCK_LPCOMP = + (MXC_F_LPGCR_PCLKDIS_LPCOMP_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_LPCOMP clock */ +} mxc_sys_periph_clock_t; + +/** @brief Enumeration to select System Clock source */ +typedef enum { + MXC_SYS_CLOCK_IPO = + MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO, /**< Select the Internal Primary Oscillator (IPO) */ + MXC_SYS_CLOCK_IBRO = + MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO, /**< Select the Internal Baud Rate Oscillator (IBRO) */ + MXC_SYS_CLOCK_ISO = + MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ISO, /**< Select the Internal Secondary Oscillator (ISO) */ + MXC_SYS_CLOCK_INRO = + MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO, /**< Select the Internal Nanoring Oscillator (INRO) */ + MXC_SYS_CLOCK_ERTCO = + MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO, /**< Select the External RTC Crystal Oscillator */ + MXC_SYS_CLOCK_EXTCLK = + MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK /**< Use the external system clock input */ +} mxc_sys_system_clock_t; + +/** @brief Enumeration to set the System Clock divider */ +typedef enum { + MXC_SYS_CLOCK_DIV_1 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV1, + MXC_SYS_CLOCK_DIV_2 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV2, + MXC_SYS_CLOCK_DIV_4 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV4, + MXC_SYS_CLOCK_DIV_8 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV8, + MXC_SYS_CLOCK_DIV_16 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV16, + MXC_SYS_CLOCK_DIV_32 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV32, + MXC_SYS_CLOCK_DIV_64 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV64, + MXC_SYS_CLOCK_DIV_128 = MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV128 +} mxc_sys_system_clock_div_t; + +#define MXC_SYS_USN_CHECKSUM_LEN 16 // Length of the USN + padding for checksum compute +#define MXC_SYS_USN_CSUM_FIELD_LEN 2 // Size of the checksum field in the USN +#define MXC_SYS_USN_LEN 13 // Size of the USN including the checksum + +/***** Function Prototypes *****/ + +typedef struct { + int ie_status; + int in_critical; +} mxc_crit_state_t; + +static mxc_crit_state_t _state = { .ie_status = (int)0xFFFFFFFF, .in_critical = 0 }; + +static inline void _mxc_crit_get_state(void) +{ +#ifndef __riscv + /* + On ARM M the 0th bit of the Priority Mask register indicates + whether interrupts are enabled or not. + + 0 = enabled + 1 = disabled + */ + uint32_t primask = __get_PRIMASK(); + _state.ie_status = (primask == 0); +#else + /* + On RISC-V bit position 3 (Machine Interrupt Enable) of the + mstatus register indicates whether interrupts are enabled. + + 0 = disabled + 1 = enabled + */ + uint32_t mstatus = get_mstatus(); + _state.ie_status = ((mstatus & (1 << 3)) != 0); +#endif +} + +/** + * @brief Enter a critical section of code that cannot be interrupted. Call @ref MXC_SYS_Crit_Exit to exit the critical section. + * @details Ex: + * @code + * MXC_SYS_Crit_Enter(); + * printf("Hello critical section!\n"); + * MXC_SYS_Crit_Exit(); + * @endcode + * The @ref MXC_CRITICAL macro is also provided as a convencience macro for wrapping a code section in this way. + * @returns None + */ +static inline void MXC_SYS_Crit_Enter(void) +{ + _mxc_crit_get_state(); + if (_state.ie_status) + __disable_irq(); + _state.in_critical = 1; +} + +/** + * @brief Exit a critical section of code from @ref MXC_SYS_Crit_Enter + * @returns None + */ +static inline void MXC_SYS_Crit_Exit(void) +{ + if (_state.ie_status) { + __enable_irq(); + } + _state.in_critical = 0; + _mxc_crit_get_state(); + /* + ^ Reset the state again to prevent edge case + where interrupts get disabled, then Crit_Exit() gets + called, which would inadvertently re-enable interrupts + from old state. + */ +} + +/** + * @brief Polls whether code is currently executing from a critical section. + * @returns 1 if code is currently in a critical section (interrupts are disabled). + * 0 if code is not in a critical section. + */ +static inline int MXC_SYS_In_Crit_Section(void) +{ + return _state.in_critical; +} + +// clang-format off +/** + * @brief Macro for wrapping a section of code to make it critical (interrupts disabled). Note: this macro + * does not support nesting. + * @details + * Ex: + * \code + * MXC_CRITICAL( + * printf("Hello critical section!\n"); + * ) + * \endcode + * This macro places a call to @ref MXC_SYS_Crit_Enter before the code, and a call to @ref MXC_SYS_Crit_Exit after. + * @param code The code section to wrap. + */ +#define MXC_CRITICAL(code) {\ + MXC_SYS_Crit_Enter();\ + code;\ + MXC_SYS_Crit_Exit();\ +} +// clang-format on + +/** + * @brief Reads the device USN and verifies the checksum. + * @param usn Pointer to store the USN. Array must be at least MXC_SYS_USN_LEN bytes long. + * @param checksum Optional pointer to store the AES checksum. If not NULL, checksum is verified with AES engine. + * @returns E_NO_ERROR if everything is successful. + */ +int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum); + +/** + * @brief Determines if the selected peripheral clock is enabled. + * @param clock Enumeration for desired clock. + * @returns 0 is the clock is disabled, non 0 if the clock is enabled. + */ +int MXC_SYS_IsClockEnabled(mxc_sys_periph_clock_t clock); + +/** + * @brief Disables the selected peripheral clock. + * @param clock Enumeration for desired clock. + */ +void MXC_SYS_ClockDisable(mxc_sys_periph_clock_t clock); + +/** + * @brief Enables the selected peripheral clock. + * @param clock Enumeration for desired clock. + */ +void MXC_SYS_ClockEnable(mxc_sys_periph_clock_t clock); + +/** + * @brief Enables the 32kHz oscillator + * @param mxc_sys_cfg Not used, may be NULL. + */ +void MXC_SYS_RTCClockEnable(void); + +/** + * @brief Disables the 32kHz oscillator + * @returns E_NO_ERROR if everything is successful + */ +int MXC_SYS_RTCClockDisable(void); + +/** + * @brief Enable System Clock Source without switching to it + * @param clock The clock to enable + * @return E_NO_ERROR if everything is successful + */ +int MXC_SYS_ClockSourceEnable(mxc_sys_system_clock_t clock); + +/** + * @brief Disable System Clock Source + * @param clock The clock to disable + * @return E_NO_ERROR if everything is successful + */ +int MXC_SYS_ClockSourceDisable(mxc_sys_system_clock_t clock); + +/** + * @brief Get the current system clock divider. + * @returns The enumerator for the current system clock divider. + */ +mxc_sys_system_clock_div_t MXC_SYS_GetClockDiv(void); + +/** + * @brief Set the system clock divider. + * @param div Enumeration for desired clock divider. + */ +void MXC_SYS_SetClockDiv(mxc_sys_system_clock_div_t div); + +/** + * @brief Select the system clock. + * @param clock Enumeration for desired clock. Note: If using the external clock input be sure to define EXTCLK_FREQ correctly. + * The default EXTCLK_FREQ value is defined in the system_max32657.h file and can be overridden at compile time. + * @returns E_NO_ERROR if everything is successful. + */ +int MXC_SYS_Clock_Select(mxc_sys_system_clock_t clock); + +/** + * @brief Wait for a clock to enable with timeout + * @param ready The clock to wait for + * @return E_NO_ERROR if ready, E_TIME_OUT if timeout + */ +int MXC_SYS_Clock_Timeout(uint32_t ready); + +/** + * @brief Reset the peripherals and/or CPU in the rstr0 or rstr1 register. + * @param Enumeration for what to reset. Can reset multiple items at once. + */ +void MXC_SYS_Reset_Periph(mxc_sys_reset_t reset); + +/** + * @brief Setup and run RISCV core + */ +void MXC_SYS_RISCVRun(void); + +/** + * @brief Shutdown the RISCV core + */ +void MXC_SYS_RISCVShutdown(void); + +/** + * @brief Returns the clock rate (in Hz) of the Risc-V core. + */ +uint32_t MXC_SYS_RiscVClockRate(void); + +/** + * @brief This function PERMANENTLY locks the Debug Access Port. + * + * @warning After executing this function you will never be able + * to reprogram the target micro. + */ +int MXC_SYS_LockDAP_Permanent(void); + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_SYS_H_ diff --git a/Libraries/PeriphDrivers/Include/MAX32657/nvic_table.h b/Libraries/PeriphDrivers/Include/MAX32657/nvic_table.h new file mode 100644 index 00000000000..e13fdfaaba8 --- /dev/null +++ b/Libraries/PeriphDrivers/Include/MAX32657/nvic_table.h @@ -0,0 +1,111 @@ +/** + * @file nvic_table.h + * @brief Interrupt vector table manipulation functions. + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX78000_NVIC_TABLE_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX78000_NVIC_TABLE_H_ + +#ifndef __riscv + +#ifdef __cplusplus +extern "C" { +#endif + +#include "max78000.h" + +/** + * @brief Set an IRQ hander callback function. If the IRQ table is in + * flash, this will copy it to RAM and set NVIC to RAM based table. + * + * @param irqn ARM external IRQ number + * @param irq_callback Function to be called at IRQ context + * + */ +void MXC_NVIC_SetVector(IRQn_Type irqn, void (*irq_callback)(void)); + +#if defined(__GNUC__) +#if __CM4_CMSIS_VERSION_MAIN == 0x03 +// NVIC_SetVector was custom-implemented in the PeriphDrivers library for +// CMSIS version 3. Newer versions of CMSIS provide an implementation of +// NVIC_SetVector with different functionality, so the Maxim implementation +// has been moved to MXC_NVIC_SetVector (above). + +// The MSDK will move to CMSIS version 5 in the future. + +// For CMSIS version 3, use MXC_NVIC_SetVector instead. +// For CMSIS version 5, you have the choice of using either. However, only +// MXC_NVIC_SetVector will work with legacy code. +inline __attribute__(( + deprecated("Use MXC_NVIC_SetVector instead. See nvic_table.h for more details."))) void +NVIC_SetVector(IRQn_Type irqn, void (*irq_callback)(void)) +{ + MXC_NVIC_SetVector(irqn, irq_callback); +} +#endif +#endif + +/** + * @brief Copy NVIC vector table to RAM and set NVIC to RAM based table. + * + */ +void NVIC_SetRAM(void); + +/** + * @brief Get Interrupt Vector + * @details Reads an interrupt vector from interrupt vector table. The + * interrupt number can be positive to specify a device specific + * interrupt, or negative to specify a processor exception. + * @param[in] IRQn Interrupt number. + * @return Address of interrupt handler function + */ +uint32_t MXC_NVIC_GetVector(IRQn_Type IRQn); + +#if defined(__GNUC__) +#if __CM4_CMSIS_VERSION_MAIN == 0x03 +// NVIC_GetVector was custom-implemented in the PeriphDrivers library for +// CMSIS version 3. Newer versions of CMSIS provide an implementation of +// NVIC_GetVector with different functionality, so the Maxim implementation +// has been moved to MXC_NVIC_GetVector (above). + +// The MSDK will move to CMSIS version 5 in the future. + +// For CMSIS version 3, use MXC_NVIC_SetVector instead. +// For CMSIS version 5, you have the choice of using either. However, only +// MXC_NVIC_GetVector will work with legacy code. +inline __attribute__(( + deprecated("Use MXC_NVIC_GetVector instead. See nvic_table.h for more details."))) void +NVIC_GetVector(IRQn_Type irqn) +{ + MXC_NVIC_GetVector(irqn); +} +#endif +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* !__riscv */ + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX78000_NVIC_TABLE_H_ diff --git a/Libraries/PeriphDrivers/max32657_files.mk b/Libraries/PeriphDrivers/max32657_files.mk new file mode 100644 index 00000000000..afaccda46e3 --- /dev/null +++ b/Libraries/PeriphDrivers/max32657_files.mk @@ -0,0 +1,53 @@ +############################################################################### + # + # Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + # Analog Devices, Inc.), + # Copyright (C) 2023-2024 Analog Devices, Inc. + # + # Licensed under the Apache License, Version 2.0 (the "License"); + # you may not use this file except in compliance with the License. + # You may obtain a copy of the License at + # + # http://www.apache.org/licenses/LICENSE-2.0 + # + # Unless required by applicable law or agreed to in writing, software + # distributed under the License is distributed on an "AS IS" BASIS, + # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + # See the License for the specific language governing permissions and + # limitations under the License. + # + ############################################################################## + +# This is the name of the build output file + +ifeq "$(TARGET)" "" +$(error TARGET must be specified) +endif + +TARGET_UC ?= $(subst m,M,$(subst a,A,$(subst x,X,$(TARGET)))) +TARGET_LC ?= $(subst M,m,$(subst A,a,$(subst X,x,$(TARGET)))) + +ifeq "$(COMPILER)" "" +$(error COMPILER must be specified) +endif + +# This is the path to the CMSIS root directory +ifeq "$(CMSIS_ROOT)" "" +CMSIS_ROOT=../CMSIS +endif +ifeq "$(LIBS_DIR)" "" +LIBS_DIR = $(CMSIS_ROOT)/.. +endif + +PERIPH_DIR := $(LIBS_DIR)/PeriphDrivers +SOURCE_DIR := $(PERIPH_DIR)/Source +INCLUDE_DIR := $(PERIPH_DIR)/Include + +PERIPH_DRIVER_INCLUDE_DIR += $(INCLUDE_DIR)/$(TARGET_UC)/ + +# TODO(ME30): Update this list with the correct files +# Source files +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_assert.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_delay.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_lock.c + From 98bc66dc4cfbda034c90435b57afcf787a2f69f4 Mon Sep 17 00:00:00 2001 From: Woo Date: Thu, 18 Apr 2024 18:17:01 -0500 Subject: [PATCH 03/93] Initial commit for updated ME30 register files --- .../Device/Maxim/MAX32657/Include/adc_regs.h | 287 + .../Device/Maxim/MAX32657/Include/aes_regs.h | 220 + .../Maxim/MAX32657/Include/aeskeys_regs.h | 109 + .../Device/Maxim/MAX32657/Include/crc_regs.h | 187 + .../Device/Maxim/MAX32657/Include/dma_regs.h | 410 + .../Device/Maxim/MAX32657/Include/dvs_regs.h | 355 + .../Device/Maxim/MAX32657/Include/fcr_regs.h | 265 + .../Device/Maxim/MAX32657/Include/flc_regs.h | 286 + .../Device/Maxim/MAX32657/Include/gcfr_regs.h | 124 + .../Device/Maxim/MAX32657/Include/gcr_regs.h | 1060 + .../Device/Maxim/MAX32657/Include/gpio_regs.h | 678 + .../Device/Maxim/MAX32657/Include/i2c_regs.h | 592 + .../Device/Maxim/MAX32657/Include/i2s_regs.h | 293 + .../Device/Maxim/MAX32657/Include/icc_regs.h | 158 + .../Maxim/MAX32657/Include/lpcmp_regs.h | 117 + .../Maxim/MAX32657/Include/lpgcr_regs.h | 149 + .../Maxim/MAX32657/Include/max32657.svd | 16641 ++++++++++++++++ .../Device/Maxim/MAX32657/Include/mcr_regs.h | 344 + .../Device/Maxim/MAX32657/Include/owm_regs.h | 230 + .../Device/Maxim/MAX32657/Include/pt_regs.h | 212 + .../Device/Maxim/MAX32657/Include/ptg_regs.h | 268 + .../Maxim/MAX32657/Include/pwrseq_regs.h | 1364 ++ .../Device/Maxim/MAX32657/Include/rtc_regs.h | 242 + .../Device/Maxim/MAX32657/Include/sema_regs.h | 203 + .../Device/Maxim/MAX32657/Include/simo_regs.h | 380 + .../Device/Maxim/MAX32657/Include/sir_regs.h | 179 + .../Device/Maxim/MAX32657/Include/spi_regs.h | 507 + .../Maxim/MAX32657/Include/system_max32657.h | 101 + .../Device/Maxim/MAX32657/Include/tmr_regs.h | 232 + .../Maxim/MAX32657/Include/trimsir_regs.h | 206 + .../Device/Maxim/MAX32657/Include/trng_regs.h | 267 + .../Device/Maxim/MAX32657/Include/uart_regs.h | 397 + .../Device/Maxim/MAX32657/Include/wdt_regs.h | 315 + .../Device/Maxim/MAX32657/Include/wut_regs.h | 244 + .../Source/ADC/adc_reva_me30.svd | 362 + .../Source/DMA/dma_reva_me30.svd | 715 + .../Source/FLC/flc_revb_me30.svd | 321 + .../Source/GPIO/gpio_reva_me30.svd | 712 + .../Source/I2C/i2c_reva_me30.svd | 1480 ++ .../Source/I2S/i2s_reva_me30.svd | 327 + .../PeriphDrivers/Source/LP/pwrseq_me30.svd | 3165 +++ .../PeriphDrivers/Source/LPCMP/lpcmp_reva.svd | 4 +- .../Source/LPCMP/lpcmp_reva_me30.svd | 59 + .../Source/OWM/owm_reva_me30.svd | 237 + .../Source/RTC/rtc_reva_me30.svd | 410 + .../Source/SPI/spi_reva_me30.svd | 1237 ++ .../PeriphDrivers/Source/SYS/SVD/fcr_me30.svd | 456 + .../Source/SYS/SVD/gcfr_me30.svd | 55 + .../PeriphDrivers/Source/SYS/SVD/gcr_me30.svd | 2011 ++ .../Source/SYS/SVD/lpgcr_me30.svd | 127 + .../PeriphDrivers/Source/SYS/SVD/mcr_me30.svd | 410 + .../PeriphDrivers/Source/SYS/SVD/sir_me30.svd | 202 + .../Source/SYS/SVD/trimsir_me30.svd | 181 + .../Source/TMR/tmr_reva_me30.svd | 313 + .../Source/TRNG/trng_revc_me30.svd | 349 + .../Source/UART/uart_revb_me30.svd | 482 + .../Source/WUT/wut_reva_me30.svd | 261 + 57 files changed, 41496 insertions(+), 2 deletions(-) create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/adc_regs.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/aes_regs.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/aeskeys_regs.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/crc_regs.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/dma_regs.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/dvs_regs.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/flc_regs.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcfr_regs.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/gpio_regs.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/i2c_regs.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/i2s_regs.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/icc_regs.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/lpcmp_regs.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/lpgcr_regs.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/mcr_regs.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/owm_regs.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/pt_regs.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/ptg_regs.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/pwrseq_regs.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/rtc_regs.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/sema_regs.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/simo_regs.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/sir_regs.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/spi_regs.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/tmr_regs.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/trimsir_regs.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/trng_regs.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/uart_regs.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/wdt_regs.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/wut_regs.h create mode 100644 Libraries/PeriphDrivers/Source/ADC/adc_reva_me30.svd create mode 100644 Libraries/PeriphDrivers/Source/DMA/dma_reva_me30.svd create mode 100644 Libraries/PeriphDrivers/Source/FLC/flc_revb_me30.svd create mode 100644 Libraries/PeriphDrivers/Source/GPIO/gpio_reva_me30.svd create mode 100644 Libraries/PeriphDrivers/Source/I2C/i2c_reva_me30.svd create mode 100644 Libraries/PeriphDrivers/Source/I2S/i2s_reva_me30.svd create mode 100644 Libraries/PeriphDrivers/Source/LP/pwrseq_me30.svd create mode 100644 Libraries/PeriphDrivers/Source/LPCMP/lpcmp_reva_me30.svd create mode 100644 Libraries/PeriphDrivers/Source/OWM/owm_reva_me30.svd create mode 100644 Libraries/PeriphDrivers/Source/RTC/rtc_reva_me30.svd create mode 100644 Libraries/PeriphDrivers/Source/SPI/spi_reva_me30.svd create mode 100644 Libraries/PeriphDrivers/Source/SYS/SVD/fcr_me30.svd create mode 100644 Libraries/PeriphDrivers/Source/SYS/SVD/gcfr_me30.svd create mode 100644 Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me30.svd create mode 100644 Libraries/PeriphDrivers/Source/SYS/SVD/lpgcr_me30.svd create mode 100644 Libraries/PeriphDrivers/Source/SYS/SVD/mcr_me30.svd create mode 100644 Libraries/PeriphDrivers/Source/SYS/SVD/sir_me30.svd create mode 100644 Libraries/PeriphDrivers/Source/SYS/SVD/trimsir_me30.svd create mode 100644 Libraries/PeriphDrivers/Source/TMR/tmr_reva_me30.svd create mode 100644 Libraries/PeriphDrivers/Source/TRNG/trng_revc_me30.svd create mode 100644 Libraries/PeriphDrivers/Source/UART/uart_revb_me30.svd create mode 100644 Libraries/PeriphDrivers/Source/WUT/wut_reva_me30.svd diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/adc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/adc_regs.h new file mode 100644 index 00000000000..6d6cdedabdf --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/adc_regs.h @@ -0,0 +1,287 @@ +/** + * @file adc_regs.h + * @brief Registers, Bit Masks and Bit Positions for the ADC Peripheral Module. + * @note This file is @generated. + * @ingroup adc_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_ADC_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_ADC_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup adc + * @defgroup adc_registers ADC_Registers + * @brief Registers, Bit Masks and Bit Positions for the ADC Peripheral Module. + * @details 10-bit Analog to Digital Converter + */ + +/** + * @ingroup adc_registers + * Structure type to access the ADC Registers. + */ +typedef struct { + __IO uint32_t ctrl; /**< \b 0x0000: ADC CTRL Register */ + __IO uint32_t status; /**< \b 0x0004: ADC STATUS Register */ + __IO uint32_t data; /**< \b 0x0008: ADC DATA Register */ + __IO uint32_t intr; /**< \b 0x000C: ADC INTR Register */ + __IO uint32_t limit[4]; /**< \b 0x0010: ADC LIMIT Register */ + __IO uint32_t deccnt; /**< \b 0x0020: ADC DECCNT Register */ +} mxc_adc_regs_t; + +/* Register offsets for module ADC */ +/** + * @ingroup adc_registers + * @defgroup ADC_Register_Offsets Register Offsets + * @brief ADC Peripheral Register Offsets from the ADC Base Peripheral Address. + * @{ + */ +#define MXC_R_ADC_CTRL ((uint32_t)0x00000000UL) /**< Offset from ADC Base Address: 0x0000 */ +#define MXC_R_ADC_STATUS ((uint32_t)0x00000004UL) /**< Offset from ADC Base Address: 0x0004 */ +#define MXC_R_ADC_DATA ((uint32_t)0x00000008UL) /**< Offset from ADC Base Address: 0x0008 */ +#define MXC_R_ADC_INTR ((uint32_t)0x0000000CUL) /**< Offset from ADC Base Address: 0x000C */ +#define MXC_R_ADC_LIMIT ((uint32_t)0x00000010UL) /**< Offset from ADC Base Address: 0x0010 */ +#define MXC_R_ADC_DECCNT ((uint32_t)0x00000020UL) /**< Offset from ADC Base Address: 0x0020 */ +/**@} end of group adc_registers */ + +/** + * @ingroup adc_registers + * @defgroup ADC_CTRL ADC_CTRL + * @brief ADC Control + * @{ + */ +#define MXC_F_ADC_CTRL_START_POS 0 /**< CTRL_START Position */ +#define MXC_F_ADC_CTRL_START ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_START_POS)) /**< CTRL_START Mask */ + +#define MXC_F_ADC_CTRL_PWR_POS 1 /**< CTRL_PWR Position */ +#define MXC_F_ADC_CTRL_PWR ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_PWR_POS)) /**< CTRL_PWR Mask */ + +#define MXC_F_ADC_CTRL_REBUF_PWR_POS 3 /**< CTRL_REBUF_PWR Position */ +#define MXC_F_ADC_CTRL_REBUF_PWR ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_REBUF_PWR_POS)) /**< CTRL_REBUF_PWR Mask */ + +#define MXC_F_ADC_CTRL_CHGPUMP_PWR_POS 4 /**< CTRL_CHGPUMP_PWR Position */ +#define MXC_F_ADC_CTRL_CHGPUMP_PWR ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_CHGPUMP_PWR_POS)) /**< CTRL_CHGPUMP_PWR Mask */ + +#define MXC_F_ADC_CTRL_REF_SCALE_POS 8 /**< CTRL_REF_SCALE Position */ +#define MXC_F_ADC_CTRL_REF_SCALE ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_REF_SCALE_POS)) /**< CTRL_REF_SCALE Mask */ + +#define MXC_F_ADC_CTRL_SCALE_POS 9 /**< CTRL_SCALE Position */ +#define MXC_F_ADC_CTRL_SCALE ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_SCALE_POS)) /**< CTRL_SCALE Mask */ + +#define MXC_F_ADC_CTRL_CLK_EN_POS 11 /**< CTRL_CLK_EN Position */ +#define MXC_F_ADC_CTRL_CLK_EN ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_CLK_EN_POS)) /**< CTRL_CLK_EN Mask */ + +#define MXC_F_ADC_CTRL_CH_SEL_POS 12 /**< CTRL_CH_SEL Position */ +#define MXC_F_ADC_CTRL_CH_SEL ((uint32_t)(0x1FUL << MXC_F_ADC_CTRL_CH_SEL_POS)) /**< CTRL_CH_SEL Mask */ +#define MXC_V_ADC_CTRL_CH_SEL_AIN0 ((uint32_t)0x0UL) /**< CTRL_CH_SEL_AIN0 Value */ +#define MXC_S_ADC_CTRL_CH_SEL_AIN0 (MXC_V_ADC_CTRL_CH_SEL_AIN0 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN0 Setting */ +#define MXC_V_ADC_CTRL_CH_SEL_AIN1 ((uint32_t)0x1UL) /**< CTRL_CH_SEL_AIN1 Value */ +#define MXC_S_ADC_CTRL_CH_SEL_AIN1 (MXC_V_ADC_CTRL_CH_SEL_AIN1 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN1 Setting */ +#define MXC_V_ADC_CTRL_CH_SEL_AIN2 ((uint32_t)0x2UL) /**< CTRL_CH_SEL_AIN2 Value */ +#define MXC_S_ADC_CTRL_CH_SEL_AIN2 (MXC_V_ADC_CTRL_CH_SEL_AIN2 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN2 Setting */ +#define MXC_V_ADC_CTRL_CH_SEL_AIN3 ((uint32_t)0x3UL) /**< CTRL_CH_SEL_AIN3 Value */ +#define MXC_S_ADC_CTRL_CH_SEL_AIN3 (MXC_V_ADC_CTRL_CH_SEL_AIN3 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN3 Setting */ +#define MXC_V_ADC_CTRL_CH_SEL_AIN4 ((uint32_t)0x4UL) /**< CTRL_CH_SEL_AIN4 Value */ +#define MXC_S_ADC_CTRL_CH_SEL_AIN4 (MXC_V_ADC_CTRL_CH_SEL_AIN4 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN4 Setting */ +#define MXC_V_ADC_CTRL_CH_SEL_AIN5 ((uint32_t)0x5UL) /**< CTRL_CH_SEL_AIN5 Value */ +#define MXC_S_ADC_CTRL_CH_SEL_AIN5 (MXC_V_ADC_CTRL_CH_SEL_AIN5 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN5 Setting */ +#define MXC_V_ADC_CTRL_CH_SEL_AIN6 ((uint32_t)0x6UL) /**< CTRL_CH_SEL_AIN6 Value */ +#define MXC_S_ADC_CTRL_CH_SEL_AIN6 (MXC_V_ADC_CTRL_CH_SEL_AIN6 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN6 Setting */ +#define MXC_V_ADC_CTRL_CH_SEL_AIN7 ((uint32_t)0x7UL) /**< CTRL_CH_SEL_AIN7 Value */ +#define MXC_S_ADC_CTRL_CH_SEL_AIN7 (MXC_V_ADC_CTRL_CH_SEL_AIN7 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN7 Setting */ +#define MXC_V_ADC_CTRL_CH_SEL_VCOREA ((uint32_t)0x8UL) /**< CTRL_CH_SEL_VCOREA Value */ +#define MXC_S_ADC_CTRL_CH_SEL_VCOREA (MXC_V_ADC_CTRL_CH_SEL_VCOREA << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VCOREA Setting */ +#define MXC_V_ADC_CTRL_CH_SEL_VCOREB ((uint32_t)0x9UL) /**< CTRL_CH_SEL_VCOREB Value */ +#define MXC_S_ADC_CTRL_CH_SEL_VCOREB (MXC_V_ADC_CTRL_CH_SEL_VCOREB << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VCOREB Setting */ +#define MXC_V_ADC_CTRL_CH_SEL_VRXOUT ((uint32_t)0xAUL) /**< CTRL_CH_SEL_VRXOUT Value */ +#define MXC_S_ADC_CTRL_CH_SEL_VRXOUT (MXC_V_ADC_CTRL_CH_SEL_VRXOUT << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VRXOUT Setting */ +#define MXC_V_ADC_CTRL_CH_SEL_VTXOUT ((uint32_t)0xBUL) /**< CTRL_CH_SEL_VTXOUT Value */ +#define MXC_S_ADC_CTRL_CH_SEL_VTXOUT (MXC_V_ADC_CTRL_CH_SEL_VTXOUT << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VTXOUT Setting */ +#define MXC_V_ADC_CTRL_CH_SEL_VDDA ((uint32_t)0xCUL) /**< CTRL_CH_SEL_VDDA Value */ +#define MXC_S_ADC_CTRL_CH_SEL_VDDA (MXC_V_ADC_CTRL_CH_SEL_VDDA << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VDDA Setting */ +#define MXC_V_ADC_CTRL_CH_SEL_VDDB ((uint32_t)0xDUL) /**< CTRL_CH_SEL_VDDB Value */ +#define MXC_S_ADC_CTRL_CH_SEL_VDDB (MXC_V_ADC_CTRL_CH_SEL_VDDB << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VDDB Setting */ +#define MXC_V_ADC_CTRL_CH_SEL_VDDIO ((uint32_t)0xEUL) /**< CTRL_CH_SEL_VDDIO Value */ +#define MXC_S_ADC_CTRL_CH_SEL_VDDIO (MXC_V_ADC_CTRL_CH_SEL_VDDIO << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VDDIO Setting */ +#define MXC_V_ADC_CTRL_CH_SEL_VDDIOH ((uint32_t)0xFUL) /**< CTRL_CH_SEL_VDDIOH Value */ +#define MXC_S_ADC_CTRL_CH_SEL_VDDIOH (MXC_V_ADC_CTRL_CH_SEL_VDDIOH << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VDDIOH Setting */ +#define MXC_V_ADC_CTRL_CH_SEL_VREGI ((uint32_t)0x10UL) /**< CTRL_CH_SEL_VREGI Value */ +#define MXC_S_ADC_CTRL_CH_SEL_VREGI (MXC_V_ADC_CTRL_CH_SEL_VREGI << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VREGI Setting */ + +#define MXC_F_ADC_CTRL_DIVSEL_POS 17 /**< CTRL_DIVSEL Position */ +#define MXC_F_ADC_CTRL_DIVSEL ((uint32_t)(0x3UL << MXC_F_ADC_CTRL_DIVSEL_POS)) /**< CTRL_DIVSEL Mask */ +#define MXC_V_ADC_CTRL_DIVSEL_DIV1 ((uint32_t)0x0UL) /**< CTRL_DIVSEL_DIV1 Value */ +#define MXC_S_ADC_CTRL_DIVSEL_DIV1 (MXC_V_ADC_CTRL_DIVSEL_DIV1 << MXC_F_ADC_CTRL_DIVSEL_POS) /**< CTRL_DIVSEL_DIV1 Setting */ +#define MXC_V_ADC_CTRL_DIVSEL_DIV2 ((uint32_t)0x1UL) /**< CTRL_DIVSEL_DIV2 Value */ +#define MXC_S_ADC_CTRL_DIVSEL_DIV2 (MXC_V_ADC_CTRL_DIVSEL_DIV2 << MXC_F_ADC_CTRL_DIVSEL_POS) /**< CTRL_DIVSEL_DIV2 Setting */ +#define MXC_V_ADC_CTRL_DIVSEL_DIV3 ((uint32_t)0x2UL) /**< CTRL_DIVSEL_DIV3 Value */ +#define MXC_S_ADC_CTRL_DIVSEL_DIV3 (MXC_V_ADC_CTRL_DIVSEL_DIV3 << MXC_F_ADC_CTRL_DIVSEL_POS) /**< CTRL_DIVSEL_DIV3 Setting */ +#define MXC_V_ADC_CTRL_DIVSEL_DIV4 ((uint32_t)0x3UL) /**< CTRL_DIVSEL_DIV4 Value */ +#define MXC_S_ADC_CTRL_DIVSEL_DIV4 (MXC_V_ADC_CTRL_DIVSEL_DIV4 << MXC_F_ADC_CTRL_DIVSEL_POS) /**< CTRL_DIVSEL_DIV4 Setting */ + +#define MXC_F_ADC_CTRL_DATA_ALIGN_POS 20 /**< CTRL_DATA_ALIGN Position */ +#define MXC_F_ADC_CTRL_DATA_ALIGN ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_DATA_ALIGN_POS)) /**< CTRL_DATA_ALIGN Mask */ + +/**@} end of group ADC_CTRL_Register */ + +/** + * @ingroup adc_registers + * @defgroup ADC_STATUS ADC_STATUS + * @brief ADC Status + * @{ + */ +#define MXC_F_ADC_STATUS_ACTIVE_POS 0 /**< STATUS_ACTIVE Position */ +#define MXC_F_ADC_STATUS_ACTIVE ((uint32_t)(0x1UL << MXC_F_ADC_STATUS_ACTIVE_POS)) /**< STATUS_ACTIVE Mask */ + +#define MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE_POS 2 /**< STATUS_AFE_PWR_UP_ACTIVE Position */ +#define MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE ((uint32_t)(0x1UL << MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE_POS)) /**< STATUS_AFE_PWR_UP_ACTIVE Mask */ + +#define MXC_F_ADC_STATUS_OVERFLOW_POS 3 /**< STATUS_OVERFLOW Position */ +#define MXC_F_ADC_STATUS_OVERFLOW ((uint32_t)(0x1UL << MXC_F_ADC_STATUS_OVERFLOW_POS)) /**< STATUS_OVERFLOW Mask */ + +/**@} end of group ADC_STATUS_Register */ + +/** + * @ingroup adc_registers + * @defgroup ADC_DATA ADC_DATA + * @brief ADC Output Data + * @{ + */ +#define MXC_F_ADC_DATA_DATA_POS 0 /**< DATA_DATA Position */ +#define MXC_F_ADC_DATA_DATA ((uint32_t)(0xFFFFUL << MXC_F_ADC_DATA_DATA_POS)) /**< DATA_DATA Mask */ + +/**@} end of group ADC_DATA_Register */ + +/** + * @ingroup adc_registers + * @defgroup ADC_INTR ADC_INTR + * @brief ADC Interrupt Control Register + * @{ + */ +#define MXC_F_ADC_INTR_DONE_IE_POS 0 /**< INTR_DONE_IE Position */ +#define MXC_F_ADC_INTR_DONE_IE ((uint32_t)(0x1UL << MXC_F_ADC_INTR_DONE_IE_POS)) /**< INTR_DONE_IE Mask */ + +#define MXC_F_ADC_INTR_REF_READY_IE_POS 1 /**< INTR_REF_READY_IE Position */ +#define MXC_F_ADC_INTR_REF_READY_IE ((uint32_t)(0x1UL << MXC_F_ADC_INTR_REF_READY_IE_POS)) /**< INTR_REF_READY_IE Mask */ + +#define MXC_F_ADC_INTR_HI_LIMIT_IE_POS 2 /**< INTR_HI_LIMIT_IE Position */ +#define MXC_F_ADC_INTR_HI_LIMIT_IE ((uint32_t)(0x1UL << MXC_F_ADC_INTR_HI_LIMIT_IE_POS)) /**< INTR_HI_LIMIT_IE Mask */ + +#define MXC_F_ADC_INTR_LO_LIMIT_IE_POS 3 /**< INTR_LO_LIMIT_IE Position */ +#define MXC_F_ADC_INTR_LO_LIMIT_IE ((uint32_t)(0x1UL << MXC_F_ADC_INTR_LO_LIMIT_IE_POS)) /**< INTR_LO_LIMIT_IE Mask */ + +#define MXC_F_ADC_INTR_OVERFLOW_IE_POS 4 /**< INTR_OVERFLOW_IE Position */ +#define MXC_F_ADC_INTR_OVERFLOW_IE ((uint32_t)(0x1UL << MXC_F_ADC_INTR_OVERFLOW_IE_POS)) /**< INTR_OVERFLOW_IE Mask */ + +#define MXC_F_ADC_INTR_DONE_IF_POS 16 /**< INTR_DONE_IF Position */ +#define MXC_F_ADC_INTR_DONE_IF ((uint32_t)(0x1UL << MXC_F_ADC_INTR_DONE_IF_POS)) /**< INTR_DONE_IF Mask */ + +#define MXC_F_ADC_INTR_REF_READY_IF_POS 17 /**< INTR_REF_READY_IF Position */ +#define MXC_F_ADC_INTR_REF_READY_IF ((uint32_t)(0x1UL << MXC_F_ADC_INTR_REF_READY_IF_POS)) /**< INTR_REF_READY_IF Mask */ + +#define MXC_F_ADC_INTR_HI_LIMIT_IF_POS 18 /**< INTR_HI_LIMIT_IF Position */ +#define MXC_F_ADC_INTR_HI_LIMIT_IF ((uint32_t)(0x1UL << MXC_F_ADC_INTR_HI_LIMIT_IF_POS)) /**< INTR_HI_LIMIT_IF Mask */ + +#define MXC_F_ADC_INTR_LO_LIMIT_IF_POS 19 /**< INTR_LO_LIMIT_IF Position */ +#define MXC_F_ADC_INTR_LO_LIMIT_IF ((uint32_t)(0x1UL << MXC_F_ADC_INTR_LO_LIMIT_IF_POS)) /**< INTR_LO_LIMIT_IF Mask */ + +#define MXC_F_ADC_INTR_OVERFLOW_IF_POS 20 /**< INTR_OVERFLOW_IF Position */ +#define MXC_F_ADC_INTR_OVERFLOW_IF ((uint32_t)(0x1UL << MXC_F_ADC_INTR_OVERFLOW_IF_POS)) /**< INTR_OVERFLOW_IF Mask */ + +#define MXC_F_ADC_INTR_PENDING_POS 22 /**< INTR_PENDING Position */ +#define MXC_F_ADC_INTR_PENDING ((uint32_t)(0x1UL << MXC_F_ADC_INTR_PENDING_POS)) /**< INTR_PENDING Mask */ + +/**@} end of group ADC_INTR_Register */ + +/** + * @ingroup adc_registers + * @defgroup ADC_LIMIT ADC_LIMIT + * @brief ADC Limit + * @{ + */ +#define MXC_F_ADC_LIMIT_CH_LO_LIMIT_POS 0 /**< LIMIT_CH_LO_LIMIT Position */ +#define MXC_F_ADC_LIMIT_CH_LO_LIMIT ((uint32_t)(0x3FFUL << MXC_F_ADC_LIMIT_CH_LO_LIMIT_POS)) /**< LIMIT_CH_LO_LIMIT Mask */ + +#define MXC_F_ADC_LIMIT_CH_HI_LIMIT_POS 12 /**< LIMIT_CH_HI_LIMIT Position */ +#define MXC_F_ADC_LIMIT_CH_HI_LIMIT ((uint32_t)(0x3FFUL << MXC_F_ADC_LIMIT_CH_HI_LIMIT_POS)) /**< LIMIT_CH_HI_LIMIT Mask */ + +#define MXC_F_ADC_LIMIT_CH_SEL_POS 24 /**< LIMIT_CH_SEL Position */ +#define MXC_F_ADC_LIMIT_CH_SEL ((uint32_t)(0xFUL << MXC_F_ADC_LIMIT_CH_SEL_POS)) /**< LIMIT_CH_SEL Mask */ + +#define MXC_F_ADC_LIMIT_CH_LO_LIMIT_EN_POS 28 /**< LIMIT_CH_LO_LIMIT_EN Position */ +#define MXC_F_ADC_LIMIT_CH_LO_LIMIT_EN ((uint32_t)(0x1UL << MXC_F_ADC_LIMIT_CH_LO_LIMIT_EN_POS)) /**< LIMIT_CH_LO_LIMIT_EN Mask */ + +#define MXC_F_ADC_LIMIT_CH_HI_LIMIT_EN_POS 29 /**< LIMIT_CH_HI_LIMIT_EN Position */ +#define MXC_F_ADC_LIMIT_CH_HI_LIMIT_EN ((uint32_t)(0x1UL << MXC_F_ADC_LIMIT_CH_HI_LIMIT_EN_POS)) /**< LIMIT_CH_HI_LIMIT_EN Mask */ + +/**@} end of group ADC_LIMIT_Register */ + +/** + * @ingroup adc_registers + * @defgroup ADC_DECCNT ADC_DECCNT + * @brief ADC Decimation Count. + * @{ + */ +#define MXC_F_ADC_DECCNT_DELAY_POS 0 /**< DECCNT_DELAY Position */ +#define MXC_F_ADC_DECCNT_DELAY ((uint32_t)(0xFFFFFFFFUL << MXC_F_ADC_DECCNT_DELAY_POS)) /**< DECCNT_DELAY Mask */ + +/**@} end of group ADC_DECCNT_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_ADC_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/aes_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/aes_regs.h new file mode 100644 index 00000000000..36a59717548 --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/aes_regs.h @@ -0,0 +1,220 @@ +/** + * @file aes_regs.h + * @brief Registers, Bit Masks and Bit Positions for the AES Peripheral Module. + * @note This file is @generated. + * @ingroup aes_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_AES_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_AES_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup aes + * @defgroup aes_registers AES_Registers + * @brief Registers, Bit Masks and Bit Positions for the AES Peripheral Module. + * @details AES Keys. + */ + +/** + * @ingroup aes_registers + * Structure type to access the AES Registers. + */ +typedef struct { + __IO uint32_t ctrl; /**< \b 0x0000: AES CTRL Register */ + __IO uint32_t status; /**< \b 0x0004: AES STATUS Register */ + __IO uint32_t intfl; /**< \b 0x0008: AES INTFL Register */ + __IO uint32_t inten; /**< \b 0x000C: AES INTEN Register */ + __IO uint32_t fifo; /**< \b 0x0010: AES FIFO Register */ +} mxc_aes_regs_t; + +/* Register offsets for module AES */ +/** + * @ingroup aes_registers + * @defgroup AES_Register_Offsets Register Offsets + * @brief AES Peripheral Register Offsets from the AES Base Peripheral Address. + * @{ + */ +#define MXC_R_AES_CTRL ((uint32_t)0x00000000UL) /**< Offset from AES Base Address: 0x0000 */ +#define MXC_R_AES_STATUS ((uint32_t)0x00000004UL) /**< Offset from AES Base Address: 0x0004 */ +#define MXC_R_AES_INTFL ((uint32_t)0x00000008UL) /**< Offset from AES Base Address: 0x0008 */ +#define MXC_R_AES_INTEN ((uint32_t)0x0000000CUL) /**< Offset from AES Base Address: 0x000C */ +#define MXC_R_AES_FIFO ((uint32_t)0x00000010UL) /**< Offset from AES Base Address: 0x0010 */ +/**@} end of group aes_registers */ + +/** + * @ingroup aes_registers + * @defgroup AES_CTRL AES_CTRL + * @brief AES Control Register + * @{ + */ +#define MXC_F_AES_CTRL_EN_POS 0 /**< CTRL_EN Position */ +#define MXC_F_AES_CTRL_EN ((uint32_t)(0x1UL << MXC_F_AES_CTRL_EN_POS)) /**< CTRL_EN Mask */ + +#define MXC_F_AES_CTRL_DMA_RX_EN_POS 1 /**< CTRL_DMA_RX_EN Position */ +#define MXC_F_AES_CTRL_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_AES_CTRL_DMA_RX_EN_POS)) /**< CTRL_DMA_RX_EN Mask */ + +#define MXC_F_AES_CTRL_DMA_TX_EN_POS 2 /**< CTRL_DMA_TX_EN Position */ +#define MXC_F_AES_CTRL_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_AES_CTRL_DMA_TX_EN_POS)) /**< CTRL_DMA_TX_EN Mask */ + +#define MXC_F_AES_CTRL_START_POS 3 /**< CTRL_START Position */ +#define MXC_F_AES_CTRL_START ((uint32_t)(0x1UL << MXC_F_AES_CTRL_START_POS)) /**< CTRL_START Mask */ + +#define MXC_F_AES_CTRL_INPUT_FLUSH_POS 4 /**< CTRL_INPUT_FLUSH Position */ +#define MXC_F_AES_CTRL_INPUT_FLUSH ((uint32_t)(0x1UL << MXC_F_AES_CTRL_INPUT_FLUSH_POS)) /**< CTRL_INPUT_FLUSH Mask */ + +#define MXC_F_AES_CTRL_OUTPUT_FLUSH_POS 5 /**< CTRL_OUTPUT_FLUSH Position */ +#define MXC_F_AES_CTRL_OUTPUT_FLUSH ((uint32_t)(0x1UL << MXC_F_AES_CTRL_OUTPUT_FLUSH_POS)) /**< CTRL_OUTPUT_FLUSH Mask */ + +#define MXC_F_AES_CTRL_KEY_SIZE_POS 6 /**< CTRL_KEY_SIZE Position */ +#define MXC_F_AES_CTRL_KEY_SIZE ((uint32_t)(0x3UL << MXC_F_AES_CTRL_KEY_SIZE_POS)) /**< CTRL_KEY_SIZE Mask */ +#define MXC_V_AES_CTRL_KEY_SIZE_AES128 ((uint32_t)0x0UL) /**< CTRL_KEY_SIZE_AES128 Value */ +#define MXC_S_AES_CTRL_KEY_SIZE_AES128 (MXC_V_AES_CTRL_KEY_SIZE_AES128 << MXC_F_AES_CTRL_KEY_SIZE_POS) /**< CTRL_KEY_SIZE_AES128 Setting */ +#define MXC_V_AES_CTRL_KEY_SIZE_AES192 ((uint32_t)0x1UL) /**< CTRL_KEY_SIZE_AES192 Value */ +#define MXC_S_AES_CTRL_KEY_SIZE_AES192 (MXC_V_AES_CTRL_KEY_SIZE_AES192 << MXC_F_AES_CTRL_KEY_SIZE_POS) /**< CTRL_KEY_SIZE_AES192 Setting */ +#define MXC_V_AES_CTRL_KEY_SIZE_AES256 ((uint32_t)0x2UL) /**< CTRL_KEY_SIZE_AES256 Value */ +#define MXC_S_AES_CTRL_KEY_SIZE_AES256 (MXC_V_AES_CTRL_KEY_SIZE_AES256 << MXC_F_AES_CTRL_KEY_SIZE_POS) /**< CTRL_KEY_SIZE_AES256 Setting */ + +#define MXC_F_AES_CTRL_TYPE_POS 8 /**< CTRL_TYPE Position */ +#define MXC_F_AES_CTRL_TYPE ((uint32_t)(0x3UL << MXC_F_AES_CTRL_TYPE_POS)) /**< CTRL_TYPE Mask */ + +/**@} end of group AES_CTRL_Register */ + +/** + * @ingroup aes_registers + * @defgroup AES_STATUS AES_STATUS + * @brief AES Status Register + * @{ + */ +#define MXC_F_AES_STATUS_BUSY_POS 0 /**< STATUS_BUSY Position */ +#define MXC_F_AES_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_AES_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */ + +#define MXC_F_AES_STATUS_INPUT_EM_POS 1 /**< STATUS_INPUT_EM Position */ +#define MXC_F_AES_STATUS_INPUT_EM ((uint32_t)(0x1UL << MXC_F_AES_STATUS_INPUT_EM_POS)) /**< STATUS_INPUT_EM Mask */ + +#define MXC_F_AES_STATUS_INPUT_FULL_POS 2 /**< STATUS_INPUT_FULL Position */ +#define MXC_F_AES_STATUS_INPUT_FULL ((uint32_t)(0x1UL << MXC_F_AES_STATUS_INPUT_FULL_POS)) /**< STATUS_INPUT_FULL Mask */ + +#define MXC_F_AES_STATUS_OUTPUT_EM_POS 3 /**< STATUS_OUTPUT_EM Position */ +#define MXC_F_AES_STATUS_OUTPUT_EM ((uint32_t)(0x1UL << MXC_F_AES_STATUS_OUTPUT_EM_POS)) /**< STATUS_OUTPUT_EM Mask */ + +#define MXC_F_AES_STATUS_OUTPUT_FULL_POS 4 /**< STATUS_OUTPUT_FULL Position */ +#define MXC_F_AES_STATUS_OUTPUT_FULL ((uint32_t)(0x1UL << MXC_F_AES_STATUS_OUTPUT_FULL_POS)) /**< STATUS_OUTPUT_FULL Mask */ + +/**@} end of group AES_STATUS_Register */ + +/** + * @ingroup aes_registers + * @defgroup AES_INTFL AES_INTFL + * @brief AES Interrupt Flag Register + * @{ + */ +#define MXC_F_AES_INTFL_DONE_POS 0 /**< INTFL_DONE Position */ +#define MXC_F_AES_INTFL_DONE ((uint32_t)(0x1UL << MXC_F_AES_INTFL_DONE_POS)) /**< INTFL_DONE Mask */ + +#define MXC_F_AES_INTFL_KEY_CHANGE_POS 1 /**< INTFL_KEY_CHANGE Position */ +#define MXC_F_AES_INTFL_KEY_CHANGE ((uint32_t)(0x1UL << MXC_F_AES_INTFL_KEY_CHANGE_POS)) /**< INTFL_KEY_CHANGE Mask */ + +#define MXC_F_AES_INTFL_KEY_ZERO_POS 2 /**< INTFL_KEY_ZERO Position */ +#define MXC_F_AES_INTFL_KEY_ZERO ((uint32_t)(0x1UL << MXC_F_AES_INTFL_KEY_ZERO_POS)) /**< INTFL_KEY_ZERO Mask */ + +#define MXC_F_AES_INTFL_OV_POS 3 /**< INTFL_OV Position */ +#define MXC_F_AES_INTFL_OV ((uint32_t)(0x1UL << MXC_F_AES_INTFL_OV_POS)) /**< INTFL_OV Mask */ + +#define MXC_F_AES_INTFL_KEY_ONE_POS 4 /**< INTFL_KEY_ONE Position */ +#define MXC_F_AES_INTFL_KEY_ONE ((uint32_t)(0x1UL << MXC_F_AES_INTFL_KEY_ONE_POS)) /**< INTFL_KEY_ONE Mask */ + +/**@} end of group AES_INTFL_Register */ + +/** + * @ingroup aes_registers + * @defgroup AES_INTEN AES_INTEN + * @brief AES Interrupt Enable Register + * @{ + */ +#define MXC_F_AES_INTEN_DONE_POS 0 /**< INTEN_DONE Position */ +#define MXC_F_AES_INTEN_DONE ((uint32_t)(0x1UL << MXC_F_AES_INTEN_DONE_POS)) /**< INTEN_DONE Mask */ + +#define MXC_F_AES_INTEN_KEY_CHANGE_POS 1 /**< INTEN_KEY_CHANGE Position */ +#define MXC_F_AES_INTEN_KEY_CHANGE ((uint32_t)(0x1UL << MXC_F_AES_INTEN_KEY_CHANGE_POS)) /**< INTEN_KEY_CHANGE Mask */ + +#define MXC_F_AES_INTEN_KEY_ZERO_POS 2 /**< INTEN_KEY_ZERO Position */ +#define MXC_F_AES_INTEN_KEY_ZERO ((uint32_t)(0x1UL << MXC_F_AES_INTEN_KEY_ZERO_POS)) /**< INTEN_KEY_ZERO Mask */ + +#define MXC_F_AES_INTEN_OV_POS 3 /**< INTEN_OV Position */ +#define MXC_F_AES_INTEN_OV ((uint32_t)(0x1UL << MXC_F_AES_INTEN_OV_POS)) /**< INTEN_OV Mask */ + +#define MXC_F_AES_INTEN_KEY_ONE_POS 4 /**< INTEN_KEY_ONE Position */ +#define MXC_F_AES_INTEN_KEY_ONE ((uint32_t)(0x1UL << MXC_F_AES_INTEN_KEY_ONE_POS)) /**< INTEN_KEY_ONE Mask */ + +/**@} end of group AES_INTEN_Register */ + +/** + * @ingroup aes_registers + * @defgroup AES_FIFO AES_FIFO + * @brief AES Data Register + * @{ + */ +#define MXC_F_AES_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ +#define MXC_F_AES_FIFO_DATA ((uint32_t)(0x1UL << MXC_F_AES_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ + +/**@} end of group AES_FIFO_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_AES_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/aeskeys_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/aeskeys_regs.h new file mode 100644 index 00000000000..d028c716491 --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/aeskeys_regs.h @@ -0,0 +1,109 @@ +/** + * @file aeskeys_regs.h + * @brief Registers, Bit Masks and Bit Positions for the AESKEYS Peripheral Module. + * @note This file is @generated. + * @ingroup aeskeys_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_AESKEYS_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_AESKEYS_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup aeskeys + * @ingroup aes + * @defgroup aeskeys_registers AESKEYS_Registers + * @brief Registers, Bit Masks and Bit Positions for the AESKEYS Peripheral Module. + * @details AES Key Registers. + */ + +/** + * @ingroup aeskeys_registers + * Structure type to access the AESKEYS Registers. + */ +typedef struct { + __IO uint32_t key0; /**< \b 0x00: AESKEYS KEY0 Register */ + __IO uint32_t key1; /**< \b 0x04: AESKEYS KEY1 Register */ + __IO uint32_t key2; /**< \b 0x08: AESKEYS KEY2 Register */ + __IO uint32_t key3; /**< \b 0x0C: AESKEYS KEY3 Register */ + __IO uint32_t key4; /**< \b 0x10: AESKEYS KEY4 Register */ + __IO uint32_t key5; /**< \b 0x14: AESKEYS KEY5 Register */ + __IO uint32_t key6; /**< \b 0x18: AESKEYS KEY6 Register */ + __IO uint32_t key7; /**< \b 0x1C: AESKEYS KEY7 Register */ +} mxc_aeskeys_regs_t; + +/* Register offsets for module AESKEYS */ +/** + * @ingroup aeskeys_registers + * @defgroup AESKEYS_Register_Offsets Register Offsets + * @brief AESKEYS Peripheral Register Offsets from the AESKEYS Base Peripheral Address. + * @{ + */ +#define MXC_R_AESKEYS_KEY0 ((uint32_t)0x00000000UL) /**< Offset from AESKEYS Base Address: 0x0000 */ +#define MXC_R_AESKEYS_KEY1 ((uint32_t)0x00000004UL) /**< Offset from AESKEYS Base Address: 0x0004 */ +#define MXC_R_AESKEYS_KEY2 ((uint32_t)0x00000008UL) /**< Offset from AESKEYS Base Address: 0x0008 */ +#define MXC_R_AESKEYS_KEY3 ((uint32_t)0x0000000CUL) /**< Offset from AESKEYS Base Address: 0x000C */ +#define MXC_R_AESKEYS_KEY4 ((uint32_t)0x00000010UL) /**< Offset from AESKEYS Base Address: 0x0010 */ +#define MXC_R_AESKEYS_KEY5 ((uint32_t)0x00000014UL) /**< Offset from AESKEYS Base Address: 0x0014 */ +#define MXC_R_AESKEYS_KEY6 ((uint32_t)0x00000018UL) /**< Offset from AESKEYS Base Address: 0x0018 */ +#define MXC_R_AESKEYS_KEY7 ((uint32_t)0x0000001CUL) /**< Offset from AESKEYS Base Address: 0x001C */ +/**@} end of group aeskeys_registers */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_AESKEYS_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/crc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/crc_regs.h new file mode 100644 index 00000000000..55311ca4a68 --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/crc_regs.h @@ -0,0 +1,187 @@ +/** + * @file crc_regs.h + * @brief Registers, Bit Masks and Bit Positions for the CRC Peripheral Module. + * @note This file is @generated. + * @ingroup crc_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_CRC_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_CRC_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup crc + * @defgroup crc_registers CRC_Registers + * @brief Registers, Bit Masks and Bit Positions for the CRC Peripheral Module. + * @details CRC Registers. + */ + +/** + * @ingroup crc_registers + * Structure type to access the CRC Registers. + */ +typedef struct { + __IO uint32_t ctrl; /**< \b 0x0000: CRC CTRL Register */ + union { + __IO uint32_t datain32; /**< \b 0x0004: CRC DATAIN32 Register */ + __IO uint16_t datain16[2]; /**< \b 0x0004: CRC DATAIN16 Register */ + __IO uint8_t datain8[4]; /**< \b 0x0004: CRC DATAIN8 Register */ + }; + __IO uint32_t poly; /**< \b 0x0008: CRC POLY Register */ + __IO uint32_t val; /**< \b 0x000C: CRC VAL Register */ +} mxc_crc_regs_t; + +/* Register offsets for module CRC */ +/** + * @ingroup crc_registers + * @defgroup CRC_Register_Offsets Register Offsets + * @brief CRC Peripheral Register Offsets from the CRC Base Peripheral Address. + * @{ + */ +#define MXC_R_CRC_CTRL ((uint32_t)0x00000000UL) /**< Offset from CRC Base Address: 0x0000 */ +#define MXC_R_CRC_DATAIN32 ((uint32_t)0x00000004UL) /**< Offset from CRC Base Address: 0x0004 */ +#define MXC_R_CRC_DATAIN16 ((uint32_t)0x00000004UL) /**< Offset from CRC Base Address: 0x0004 */ +#define MXC_R_CRC_DATAIN8 ((uint32_t)0x00000004UL) /**< Offset from CRC Base Address: 0x0004 */ +#define MXC_R_CRC_POLY ((uint32_t)0x00000008UL) /**< Offset from CRC Base Address: 0x0008 */ +#define MXC_R_CRC_VAL ((uint32_t)0x0000000CUL) /**< Offset from CRC Base Address: 0x000C */ +/**@} end of group crc_registers */ + +/** + * @ingroup crc_registers + * @defgroup CRC_CTRL CRC_CTRL + * @brief CRC Control + * @{ + */ +#define MXC_F_CRC_CTRL_EN_POS 0 /**< CTRL_EN Position */ +#define MXC_F_CRC_CTRL_EN ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_EN_POS)) /**< CTRL_EN Mask */ + +#define MXC_F_CRC_CTRL_DMA_EN_POS 1 /**< CTRL_DMA_EN Position */ +#define MXC_F_CRC_CTRL_DMA_EN ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_DMA_EN_POS)) /**< CTRL_DMA_EN Mask */ + +#define MXC_F_CRC_CTRL_MSB_POS 2 /**< CTRL_MSB Position */ +#define MXC_F_CRC_CTRL_MSB ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_MSB_POS)) /**< CTRL_MSB Mask */ + +#define MXC_F_CRC_CTRL_BYTE_SWAP_IN_POS 3 /**< CTRL_BYTE_SWAP_IN Position */ +#define MXC_F_CRC_CTRL_BYTE_SWAP_IN ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_BYTE_SWAP_IN_POS)) /**< CTRL_BYTE_SWAP_IN Mask */ + +#define MXC_F_CRC_CTRL_BYTE_SWAP_OUT_POS 4 /**< CTRL_BYTE_SWAP_OUT Position */ +#define MXC_F_CRC_CTRL_BYTE_SWAP_OUT ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_BYTE_SWAP_OUT_POS)) /**< CTRL_BYTE_SWAP_OUT Mask */ + +#define MXC_F_CRC_CTRL_BUSY_POS 16 /**< CTRL_BUSY Position */ +#define MXC_F_CRC_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_CRC_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */ + +/**@} end of group CRC_CTRL_Register */ + +/** + * @ingroup crc_registers + * @defgroup CRC_DATAIN32 CRC_DATAIN32 + * @brief CRC Data Input + * @{ + */ +#define MXC_F_CRC_DATAIN32_DATA_POS 0 /**< DATAIN32_DATA Position */ +#define MXC_F_CRC_DATAIN32_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_CRC_DATAIN32_DATA_POS)) /**< DATAIN32_DATA Mask */ + +/**@} end of group CRC_DATAIN32_Register */ + +/** + * @ingroup crc_registers + * @defgroup CRC_DATAIN16 CRC_DATAIN16 + * @brief CRC Data Input + * @{ + */ +#define MXC_F_CRC_DATAIN16_DATA_POS 0 /**< DATAIN16_DATA Position */ +#define MXC_F_CRC_DATAIN16_DATA ((uint16_t)(0xFFFFUL << MXC_F_CRC_DATAIN16_DATA_POS)) /**< DATAIN16_DATA Mask */ + +/**@} end of group CRC_DATAIN16_Register */ + +/** + * @ingroup crc_registers + * @defgroup CRC_DATAIN8 CRC_DATAIN8 + * @brief CRC Data Input + * @{ + */ +#define MXC_F_CRC_DATAIN8_DATA_POS 0 /**< DATAIN8_DATA Position */ +#define MXC_F_CRC_DATAIN8_DATA ((uint8_t)(0xFFUL << MXC_F_CRC_DATAIN8_DATA_POS)) /**< DATAIN8_DATA Mask */ + +/**@} end of group CRC_DATAIN8_Register */ + +/** + * @ingroup crc_registers + * @defgroup CRC_POLY CRC_POLY + * @brief CRC Polynomial + * @{ + */ +#define MXC_F_CRC_POLY_POLY_POS 0 /**< POLY_POLY Position */ +#define MXC_F_CRC_POLY_POLY ((uint32_t)(0xFFFFFFFFUL << MXC_F_CRC_POLY_POLY_POS)) /**< POLY_POLY Mask */ + +/**@} end of group CRC_POLY_Register */ + +/** + * @ingroup crc_registers + * @defgroup CRC_VAL CRC_VAL + * @brief Current CRC Value + * @{ + */ +#define MXC_F_CRC_VAL_VALUE_POS 0 /**< VAL_VALUE Position */ +#define MXC_F_CRC_VAL_VALUE ((uint32_t)(0xFFFFFFFFUL << MXC_F_CRC_VAL_VALUE_POS)) /**< VAL_VALUE Mask */ + +/**@} end of group CRC_VAL_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_CRC_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/dma_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/dma_regs.h new file mode 100644 index 00000000000..5517794c3af --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/dma_regs.h @@ -0,0 +1,410 @@ +/** + * @file dma_regs.h + * @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module. + * @note This file is @generated. + * @ingroup dma_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_DMA_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_DMA_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup dma + * @defgroup dma_registers DMA_Registers + * @brief Registers, Bit Masks and Bit Positions for the DMA Peripheral Module. + * @details DMA Controller Fully programmable, chaining capable DMA channels. + */ + +/** + * @ingroup dma_registers + * Structure type to access the DMA Registers. + */ +typedef struct { + __IO uint32_t ctrl; /**< \b 0x000: DMA CTRL Register */ + __IO uint32_t status; /**< \b 0x004: DMA STATUS Register */ + __IO uint32_t src; /**< \b 0x008: DMA SRC Register */ + __IO uint32_t dst; /**< \b 0x00C: DMA DST Register */ + __IO uint32_t cnt; /**< \b 0x010: DMA CNT Register */ + __IO uint32_t srcrld; /**< \b 0x014: DMA SRCRLD Register */ + __IO uint32_t dstrld; /**< \b 0x018: DMA DSTRLD Register */ + __IO uint32_t cntrld; /**< \b 0x01C: DMA CNTRLD Register */ +} mxc_dma_ch_regs_t; + +typedef struct { + __IO uint32_t inten; /**< \b 0x000: DMA INTEN Register */ + __I uint32_t intfl; /**< \b 0x004: DMA INTFL Register */ + __R uint32_t rsv_0x8_0xff[62]; + __IO mxc_dma_ch_regs_t ch[4]; /**< \b 0x100: DMA CH Register */ +} mxc_dma_regs_t; + +/* Register offsets for module DMA */ +/** + * @ingroup dma_registers + * @defgroup DMA_Register_Offsets Register Offsets + * @brief DMA Peripheral Register Offsets from the DMA Base Peripheral Address. + * @{ + */ +#define MXC_R_DMA_CTRL ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: 0x0000 */ +#define MXC_R_DMA_STATUS ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: 0x0004 */ +#define MXC_R_DMA_SRC ((uint32_t)0x00000008UL) /**< Offset from DMA Base Address: 0x0008 */ +#define MXC_R_DMA_DST ((uint32_t)0x0000000CUL) /**< Offset from DMA Base Address: 0x000C */ +#define MXC_R_DMA_CNT ((uint32_t)0x00000010UL) /**< Offset from DMA Base Address: 0x0010 */ +#define MXC_R_DMA_SRCRLD ((uint32_t)0x00000014UL) /**< Offset from DMA Base Address: 0x0014 */ +#define MXC_R_DMA_DSTRLD ((uint32_t)0x00000018UL) /**< Offset from DMA Base Address: 0x0018 */ +#define MXC_R_DMA_CNTRLD ((uint32_t)0x0000001CUL) /**< Offset from DMA Base Address: 0x001C */ +#define MXC_R_DMA_INTEN ((uint32_t)0x00000000UL) /**< Offset from DMA Base Address: 0x0000 */ +#define MXC_R_DMA_INTFL ((uint32_t)0x00000004UL) /**< Offset from DMA Base Address: 0x0004 */ +#define MXC_R_DMA_CH ((uint32_t)0x00000100UL) /**< Offset from DMA Base Address: 0x0100 */ +/**@} end of group dma_registers */ + +/** + * @ingroup dma_registers + * @defgroup DMA_INTEN DMA_INTEN + * @brief DMA Control Register. + * @{ + */ +#define MXC_F_DMA_INTEN_CH0_POS 0 /**< INTEN_CH0 Position */ +#define MXC_F_DMA_INTEN_CH0 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH0_POS)) /**< INTEN_CH0 Mask */ + +#define MXC_F_DMA_INTEN_CH1_POS 1 /**< INTEN_CH1 Position */ +#define MXC_F_DMA_INTEN_CH1 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH1_POS)) /**< INTEN_CH1 Mask */ + +#define MXC_F_DMA_INTEN_CH2_POS 2 /**< INTEN_CH2 Position */ +#define MXC_F_DMA_INTEN_CH2 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH2_POS)) /**< INTEN_CH2 Mask */ + +#define MXC_F_DMA_INTEN_CH3_POS 3 /**< INTEN_CH3 Position */ +#define MXC_F_DMA_INTEN_CH3 ((uint32_t)(0x1UL << MXC_F_DMA_INTEN_CH3_POS)) /**< INTEN_CH3 Mask */ + +/**@} end of group DMA_INTEN_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_INTFL DMA_INTFL + * @brief DMA Interrupt Register. + * @{ + */ +#define MXC_F_DMA_INTFL_CH0_POS 0 /**< INTFL_CH0 Position */ +#define MXC_F_DMA_INTFL_CH0 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH0_POS)) /**< INTFL_CH0 Mask */ + +#define MXC_F_DMA_INTFL_CH1_POS 1 /**< INTFL_CH1 Position */ +#define MXC_F_DMA_INTFL_CH1 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH1_POS)) /**< INTFL_CH1 Mask */ + +#define MXC_F_DMA_INTFL_CH2_POS 2 /**< INTFL_CH2 Position */ +#define MXC_F_DMA_INTFL_CH2 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH2_POS)) /**< INTFL_CH2 Mask */ + +#define MXC_F_DMA_INTFL_CH3_POS 3 /**< INTFL_CH3 Position */ +#define MXC_F_DMA_INTFL_CH3 ((uint32_t)(0x1UL << MXC_F_DMA_INTFL_CH3_POS)) /**< INTFL_CH3 Mask */ + +/**@} end of group DMA_INTFL_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_CTRL DMA_CTRL + * @brief DMA Channel Control Register. + * @{ + */ +#define MXC_F_DMA_CTRL_EN_POS 0 /**< CTRL_EN Position */ +#define MXC_F_DMA_CTRL_EN ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_EN_POS)) /**< CTRL_EN Mask */ + +#define MXC_F_DMA_CTRL_RLDEN_POS 1 /**< CTRL_RLDEN Position */ +#define MXC_F_DMA_CTRL_RLDEN ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_RLDEN_POS)) /**< CTRL_RLDEN Mask */ + +#define MXC_F_DMA_CTRL_PRI_POS 2 /**< CTRL_PRI Position */ +#define MXC_F_DMA_CTRL_PRI ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_PRI_POS)) /**< CTRL_PRI Mask */ +#define MXC_V_DMA_CTRL_PRI_HIGH ((uint32_t)0x0UL) /**< CTRL_PRI_HIGH Value */ +#define MXC_S_DMA_CTRL_PRI_HIGH (MXC_V_DMA_CTRL_PRI_HIGH << MXC_F_DMA_CTRL_PRI_POS) /**< CTRL_PRI_HIGH Setting */ +#define MXC_V_DMA_CTRL_PRI_MEDHIGH ((uint32_t)0x1UL) /**< CTRL_PRI_MEDHIGH Value */ +#define MXC_S_DMA_CTRL_PRI_MEDHIGH (MXC_V_DMA_CTRL_PRI_MEDHIGH << MXC_F_DMA_CTRL_PRI_POS) /**< CTRL_PRI_MEDHIGH Setting */ +#define MXC_V_DMA_CTRL_PRI_MEDLOW ((uint32_t)0x2UL) /**< CTRL_PRI_MEDLOW Value */ +#define MXC_S_DMA_CTRL_PRI_MEDLOW (MXC_V_DMA_CTRL_PRI_MEDLOW << MXC_F_DMA_CTRL_PRI_POS) /**< CTRL_PRI_MEDLOW Setting */ +#define MXC_V_DMA_CTRL_PRI_LOW ((uint32_t)0x3UL) /**< CTRL_PRI_LOW Value */ +#define MXC_S_DMA_CTRL_PRI_LOW (MXC_V_DMA_CTRL_PRI_LOW << MXC_F_DMA_CTRL_PRI_POS) /**< CTRL_PRI_LOW Setting */ + +#define MXC_F_DMA_CTRL_REQUEST_POS 4 /**< CTRL_REQUEST Position */ +#define MXC_F_DMA_CTRL_REQUEST ((uint32_t)(0x3FUL << MXC_F_DMA_CTRL_REQUEST_POS)) /**< CTRL_REQUEST Mask */ +#define MXC_V_DMA_CTRL_REQUEST_MEMTOMEM ((uint32_t)0x0UL) /**< CTRL_REQUEST_MEMTOMEM Value */ +#define MXC_S_DMA_CTRL_REQUEST_MEMTOMEM (MXC_V_DMA_CTRL_REQUEST_MEMTOMEM << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_MEMTOMEM Setting */ +#define MXC_V_DMA_CTRL_REQUEST_SPI1RX ((uint32_t)0x1UL) /**< CTRL_REQUEST_SPI1RX Value */ +#define MXC_S_DMA_CTRL_REQUEST_SPI1RX (MXC_V_DMA_CTRL_REQUEST_SPI1RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI1RX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_UART0RX ((uint32_t)0x4UL) /**< CTRL_REQUEST_UART0RX Value */ +#define MXC_S_DMA_CTRL_REQUEST_UART0RX (MXC_V_DMA_CTRL_REQUEST_UART0RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART0RX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_UART1RX ((uint32_t)0x5UL) /**< CTRL_REQUEST_UART1RX Value */ +#define MXC_S_DMA_CTRL_REQUEST_UART1RX (MXC_V_DMA_CTRL_REQUEST_UART1RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART1RX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_I2C0RX ((uint32_t)0x7UL) /**< CTRL_REQUEST_I2C0RX Value */ +#define MXC_S_DMA_CTRL_REQUEST_I2C0RX (MXC_V_DMA_CTRL_REQUEST_I2C0RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C0RX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_I2C1RX ((uint32_t)0x8UL) /**< CTRL_REQUEST_I2C1RX Value */ +#define MXC_S_DMA_CTRL_REQUEST_I2C1RX (MXC_V_DMA_CTRL_REQUEST_I2C1RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C1RX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_ADC ((uint32_t)0x9UL) /**< CTRL_REQUEST_ADC Value */ +#define MXC_S_DMA_CTRL_REQUEST_ADC (MXC_V_DMA_CTRL_REQUEST_ADC << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_ADC Setting */ +#define MXC_V_DMA_CTRL_REQUEST_I2C2RX ((uint32_t)0xAUL) /**< CTRL_REQUEST_I2C2RX Value */ +#define MXC_S_DMA_CTRL_REQUEST_I2C2RX (MXC_V_DMA_CTRL_REQUEST_I2C2RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C2RX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_UART2RX ((uint32_t)0xEUL) /**< CTRL_REQUEST_UART2RX Value */ +#define MXC_S_DMA_CTRL_REQUEST_UART2RX (MXC_V_DMA_CTRL_REQUEST_UART2RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART2RX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_SPI0RX ((uint32_t)0xFUL) /**< CTRL_REQUEST_SPI0RX Value */ +#define MXC_S_DMA_CTRL_REQUEST_SPI0RX (MXC_V_DMA_CTRL_REQUEST_SPI0RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI0RX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_AESRX ((uint32_t)0x10UL) /**< CTRL_REQUEST_AESRX Value */ +#define MXC_S_DMA_CTRL_REQUEST_AESRX (MXC_V_DMA_CTRL_REQUEST_AESRX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_AESRX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_UART3RX ((uint32_t)0x1CUL) /**< CTRL_REQUEST_UART3RX Value */ +#define MXC_S_DMA_CTRL_REQUEST_UART3RX (MXC_V_DMA_CTRL_REQUEST_UART3RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART3RX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_I2SRX ((uint32_t)0x1EUL) /**< CTRL_REQUEST_I2SRX Value */ +#define MXC_S_DMA_CTRL_REQUEST_I2SRX (MXC_V_DMA_CTRL_REQUEST_I2SRX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2SRX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_SPI1TX ((uint32_t)0x21UL) /**< CTRL_REQUEST_SPI1TX Value */ +#define MXC_S_DMA_CTRL_REQUEST_SPI1TX (MXC_V_DMA_CTRL_REQUEST_SPI1TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI1TX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_UART0TX ((uint32_t)0x24UL) /**< CTRL_REQUEST_UART0TX Value */ +#define MXC_S_DMA_CTRL_REQUEST_UART0TX (MXC_V_DMA_CTRL_REQUEST_UART0TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART0TX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_UART1TX ((uint32_t)0x25UL) /**< CTRL_REQUEST_UART1TX Value */ +#define MXC_S_DMA_CTRL_REQUEST_UART1TX (MXC_V_DMA_CTRL_REQUEST_UART1TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART1TX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_I2C0TX ((uint32_t)0x27UL) /**< CTRL_REQUEST_I2C0TX Value */ +#define MXC_S_DMA_CTRL_REQUEST_I2C0TX (MXC_V_DMA_CTRL_REQUEST_I2C0TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C0TX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_I2C1TX ((uint32_t)0x28UL) /**< CTRL_REQUEST_I2C1TX Value */ +#define MXC_S_DMA_CTRL_REQUEST_I2C1TX (MXC_V_DMA_CTRL_REQUEST_I2C1TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C1TX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_I2C2TX ((uint32_t)0x2AUL) /**< CTRL_REQUEST_I2C2TX Value */ +#define MXC_S_DMA_CTRL_REQUEST_I2C2TX (MXC_V_DMA_CTRL_REQUEST_I2C2TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C2TX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_CRCTX ((uint32_t)0x2CUL) /**< CTRL_REQUEST_CRCTX Value */ +#define MXC_S_DMA_CTRL_REQUEST_CRCTX (MXC_V_DMA_CTRL_REQUEST_CRCTX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_CRCTX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_UART2TX ((uint32_t)0x2EUL) /**< CTRL_REQUEST_UART2TX Value */ +#define MXC_S_DMA_CTRL_REQUEST_UART2TX (MXC_V_DMA_CTRL_REQUEST_UART2TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART2TX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_SPI0TX ((uint32_t)0x2FUL) /**< CTRL_REQUEST_SPI0TX Value */ +#define MXC_S_DMA_CTRL_REQUEST_SPI0TX (MXC_V_DMA_CTRL_REQUEST_SPI0TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI0TX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_AESTX ((uint32_t)0x30UL) /**< CTRL_REQUEST_AESTX Value */ +#define MXC_S_DMA_CTRL_REQUEST_AESTX (MXC_V_DMA_CTRL_REQUEST_AESTX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_AESTX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_UART3TX ((uint32_t)0x3CUL) /**< CTRL_REQUEST_UART3TX Value */ +#define MXC_S_DMA_CTRL_REQUEST_UART3TX (MXC_V_DMA_CTRL_REQUEST_UART3TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART3TX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_I2STX ((uint32_t)0x3EUL) /**< CTRL_REQUEST_I2STX Value */ +#define MXC_S_DMA_CTRL_REQUEST_I2STX (MXC_V_DMA_CTRL_REQUEST_I2STX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2STX Setting */ + +#define MXC_F_DMA_CTRL_TO_WAIT_POS 10 /**< CTRL_TO_WAIT Position */ +#define MXC_F_DMA_CTRL_TO_WAIT ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_TO_WAIT_POS)) /**< CTRL_TO_WAIT Mask */ + +#define MXC_F_DMA_CTRL_TO_PER_POS 11 /**< CTRL_TO_PER Position */ +#define MXC_F_DMA_CTRL_TO_PER ((uint32_t)(0x7UL << MXC_F_DMA_CTRL_TO_PER_POS)) /**< CTRL_TO_PER Mask */ +#define MXC_V_DMA_CTRL_TO_PER_TO4 ((uint32_t)0x0UL) /**< CTRL_TO_PER_TO4 Value */ +#define MXC_S_DMA_CTRL_TO_PER_TO4 (MXC_V_DMA_CTRL_TO_PER_TO4 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO4 Setting */ +#define MXC_V_DMA_CTRL_TO_PER_TO8 ((uint32_t)0x1UL) /**< CTRL_TO_PER_TO8 Value */ +#define MXC_S_DMA_CTRL_TO_PER_TO8 (MXC_V_DMA_CTRL_TO_PER_TO8 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO8 Setting */ +#define MXC_V_DMA_CTRL_TO_PER_TO16 ((uint32_t)0x2UL) /**< CTRL_TO_PER_TO16 Value */ +#define MXC_S_DMA_CTRL_TO_PER_TO16 (MXC_V_DMA_CTRL_TO_PER_TO16 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO16 Setting */ +#define MXC_V_DMA_CTRL_TO_PER_TO32 ((uint32_t)0x3UL) /**< CTRL_TO_PER_TO32 Value */ +#define MXC_S_DMA_CTRL_TO_PER_TO32 (MXC_V_DMA_CTRL_TO_PER_TO32 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO32 Setting */ +#define MXC_V_DMA_CTRL_TO_PER_TO64 ((uint32_t)0x4UL) /**< CTRL_TO_PER_TO64 Value */ +#define MXC_S_DMA_CTRL_TO_PER_TO64 (MXC_V_DMA_CTRL_TO_PER_TO64 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO64 Setting */ +#define MXC_V_DMA_CTRL_TO_PER_TO128 ((uint32_t)0x5UL) /**< CTRL_TO_PER_TO128 Value */ +#define MXC_S_DMA_CTRL_TO_PER_TO128 (MXC_V_DMA_CTRL_TO_PER_TO128 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO128 Setting */ +#define MXC_V_DMA_CTRL_TO_PER_TO256 ((uint32_t)0x6UL) /**< CTRL_TO_PER_TO256 Value */ +#define MXC_S_DMA_CTRL_TO_PER_TO256 (MXC_V_DMA_CTRL_TO_PER_TO256 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO256 Setting */ +#define MXC_V_DMA_CTRL_TO_PER_TO512 ((uint32_t)0x7UL) /**< CTRL_TO_PER_TO512 Value */ +#define MXC_S_DMA_CTRL_TO_PER_TO512 (MXC_V_DMA_CTRL_TO_PER_TO512 << MXC_F_DMA_CTRL_TO_PER_POS) /**< CTRL_TO_PER_TO512 Setting */ + +#define MXC_F_DMA_CTRL_TO_CLKDIV_POS 14 /**< CTRL_TO_CLKDIV Position */ +#define MXC_F_DMA_CTRL_TO_CLKDIV ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_TO_CLKDIV_POS)) /**< CTRL_TO_CLKDIV Mask */ +#define MXC_V_DMA_CTRL_TO_CLKDIV_DIS ((uint32_t)0x0UL) /**< CTRL_TO_CLKDIV_DIS Value */ +#define MXC_S_DMA_CTRL_TO_CLKDIV_DIS (MXC_V_DMA_CTRL_TO_CLKDIV_DIS << MXC_F_DMA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIS Setting */ +#define MXC_V_DMA_CTRL_TO_CLKDIV_DIV256 ((uint32_t)0x1UL) /**< CTRL_TO_CLKDIV_DIV256 Value */ +#define MXC_S_DMA_CTRL_TO_CLKDIV_DIV256 (MXC_V_DMA_CTRL_TO_CLKDIV_DIV256 << MXC_F_DMA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIV256 Setting */ +#define MXC_V_DMA_CTRL_TO_CLKDIV_DIV64K ((uint32_t)0x2UL) /**< CTRL_TO_CLKDIV_DIV64K Value */ +#define MXC_S_DMA_CTRL_TO_CLKDIV_DIV64K (MXC_V_DMA_CTRL_TO_CLKDIV_DIV64K << MXC_F_DMA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIV64K Setting */ +#define MXC_V_DMA_CTRL_TO_CLKDIV_DIV16M ((uint32_t)0x3UL) /**< CTRL_TO_CLKDIV_DIV16M Value */ +#define MXC_S_DMA_CTRL_TO_CLKDIV_DIV16M (MXC_V_DMA_CTRL_TO_CLKDIV_DIV16M << MXC_F_DMA_CTRL_TO_CLKDIV_POS) /**< CTRL_TO_CLKDIV_DIV16M Setting */ + +#define MXC_F_DMA_CTRL_SRCWD_POS 16 /**< CTRL_SRCWD Position */ +#define MXC_F_DMA_CTRL_SRCWD ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_SRCWD_POS)) /**< CTRL_SRCWD Mask */ +#define MXC_V_DMA_CTRL_SRCWD_BYTE ((uint32_t)0x0UL) /**< CTRL_SRCWD_BYTE Value */ +#define MXC_S_DMA_CTRL_SRCWD_BYTE (MXC_V_DMA_CTRL_SRCWD_BYTE << MXC_F_DMA_CTRL_SRCWD_POS) /**< CTRL_SRCWD_BYTE Setting */ +#define MXC_V_DMA_CTRL_SRCWD_HALFWORD ((uint32_t)0x1UL) /**< CTRL_SRCWD_HALFWORD Value */ +#define MXC_S_DMA_CTRL_SRCWD_HALFWORD (MXC_V_DMA_CTRL_SRCWD_HALFWORD << MXC_F_DMA_CTRL_SRCWD_POS) /**< CTRL_SRCWD_HALFWORD Setting */ +#define MXC_V_DMA_CTRL_SRCWD_WORD ((uint32_t)0x2UL) /**< CTRL_SRCWD_WORD Value */ +#define MXC_S_DMA_CTRL_SRCWD_WORD (MXC_V_DMA_CTRL_SRCWD_WORD << MXC_F_DMA_CTRL_SRCWD_POS) /**< CTRL_SRCWD_WORD Setting */ + +#define MXC_F_DMA_CTRL_SRCINC_POS 18 /**< CTRL_SRCINC Position */ +#define MXC_F_DMA_CTRL_SRCINC ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_SRCINC_POS)) /**< CTRL_SRCINC Mask */ + +#define MXC_F_DMA_CTRL_DSTWD_POS 20 /**< CTRL_DSTWD Position */ +#define MXC_F_DMA_CTRL_DSTWD ((uint32_t)(0x3UL << MXC_F_DMA_CTRL_DSTWD_POS)) /**< CTRL_DSTWD Mask */ +#define MXC_V_DMA_CTRL_DSTWD_BYTE ((uint32_t)0x0UL) /**< CTRL_DSTWD_BYTE Value */ +#define MXC_S_DMA_CTRL_DSTWD_BYTE (MXC_V_DMA_CTRL_DSTWD_BYTE << MXC_F_DMA_CTRL_DSTWD_POS) /**< CTRL_DSTWD_BYTE Setting */ +#define MXC_V_DMA_CTRL_DSTWD_HALFWORD ((uint32_t)0x1UL) /**< CTRL_DSTWD_HALFWORD Value */ +#define MXC_S_DMA_CTRL_DSTWD_HALFWORD (MXC_V_DMA_CTRL_DSTWD_HALFWORD << MXC_F_DMA_CTRL_DSTWD_POS) /**< CTRL_DSTWD_HALFWORD Setting */ +#define MXC_V_DMA_CTRL_DSTWD_WORD ((uint32_t)0x2UL) /**< CTRL_DSTWD_WORD Value */ +#define MXC_S_DMA_CTRL_DSTWD_WORD (MXC_V_DMA_CTRL_DSTWD_WORD << MXC_F_DMA_CTRL_DSTWD_POS) /**< CTRL_DSTWD_WORD Setting */ + +#define MXC_F_DMA_CTRL_DSTINC_POS 22 /**< CTRL_DSTINC Position */ +#define MXC_F_DMA_CTRL_DSTINC ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_DSTINC_POS)) /**< CTRL_DSTINC Mask */ + +#define MXC_F_DMA_CTRL_BURST_SIZE_POS 24 /**< CTRL_BURST_SIZE Position */ +#define MXC_F_DMA_CTRL_BURST_SIZE ((uint32_t)(0x1FUL << MXC_F_DMA_CTRL_BURST_SIZE_POS)) /**< CTRL_BURST_SIZE Mask */ + +#define MXC_F_DMA_CTRL_DIS_IE_POS 30 /**< CTRL_DIS_IE Position */ +#define MXC_F_DMA_CTRL_DIS_IE ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_DIS_IE_POS)) /**< CTRL_DIS_IE Mask */ + +#define MXC_F_DMA_CTRL_CTZ_IE_POS 31 /**< CTRL_CTZ_IE Position */ +#define MXC_F_DMA_CTRL_CTZ_IE ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_CTZ_IE_POS)) /**< CTRL_CTZ_IE Mask */ + +/**@} end of group DMA_CTRL_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_STATUS DMA_STATUS + * @brief DMA Channel Status Register. + * @{ + */ +#define MXC_F_DMA_STATUS_STATUS_POS 0 /**< STATUS_STATUS Position */ +#define MXC_F_DMA_STATUS_STATUS ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_STATUS_POS)) /**< STATUS_STATUS Mask */ + +#define MXC_F_DMA_STATUS_IPEND_POS 1 /**< STATUS_IPEND Position */ +#define MXC_F_DMA_STATUS_IPEND ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_IPEND_POS)) /**< STATUS_IPEND Mask */ + +#define MXC_F_DMA_STATUS_CTZ_IF_POS 2 /**< STATUS_CTZ_IF Position */ +#define MXC_F_DMA_STATUS_CTZ_IF ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_CTZ_IF_POS)) /**< STATUS_CTZ_IF Mask */ + +#define MXC_F_DMA_STATUS_RLD_IF_POS 3 /**< STATUS_RLD_IF Position */ +#define MXC_F_DMA_STATUS_RLD_IF ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_RLD_IF_POS)) /**< STATUS_RLD_IF Mask */ + +#define MXC_F_DMA_STATUS_BUS_ERR_POS 4 /**< STATUS_BUS_ERR Position */ +#define MXC_F_DMA_STATUS_BUS_ERR ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_BUS_ERR_POS)) /**< STATUS_BUS_ERR Mask */ + +#define MXC_F_DMA_STATUS_TO_IF_POS 6 /**< STATUS_TO_IF Position */ +#define MXC_F_DMA_STATUS_TO_IF ((uint32_t)(0x1UL << MXC_F_DMA_STATUS_TO_IF_POS)) /**< STATUS_TO_IF Mask */ + +/**@} end of group DMA_STATUS_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_SRC DMA_SRC + * @brief Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or + * 4, depending on the data width of each AHB cycle. For peripheral transfers, some + * or all of the actual address bits are fixed. If SRCINC=0, this register remains + * constant. In the case where a count-to-zero condition occurs while RLDEN=1, the + * register is reloaded with the contents of DMA_SRC_RLD. + * @{ + */ +#define MXC_F_DMA_SRC_ADDR_POS 0 /**< SRC_ADDR Position */ +#define MXC_F_DMA_SRC_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_SRC_ADDR_POS)) /**< SRC_ADDR Mask */ + +/**@} end of group DMA_SRC_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_DST DMA_DST + * @brief Destination Device Address. For peripheral transfers, some or all of the actual + * address bits are fixed. If DSTINC=1, this register is incremented on every AHB + * write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the + * data width of each AHB cycle. In the case where a count-to-zero condition occurs + * while RLDEN=1, the register is reloaded with DMA_DST_RLD. + * @{ + */ +#define MXC_F_DMA_DST_ADDR_POS 0 /**< DST_ADDR Position */ +#define MXC_F_DMA_DST_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_DMA_DST_ADDR_POS)) /**< DST_ADDR Mask */ + +/**@} end of group DMA_DST_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_CNT DMA_CNT + * @brief DMA Counter. The user loads this register with the number of bytes to transfer. + * This counter decreases on every AHB cycle into the DMA FIFO. The decrement will + * be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter + * reaches 0, a count-to-zero condition is triggered. + * @{ + */ +#define MXC_F_DMA_CNT_CNT_POS 0 /**< CNT_CNT Position */ +#define MXC_F_DMA_CNT_CNT ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNT_CNT_POS)) /**< CNT_CNT Mask */ + +/**@} end of group DMA_CNT_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_SRCRLD DMA_SRCRLD + * @brief Source Address Reload Value. The value of this register is loaded into DMA0_SRC + * upon a count-to-zero condition. + * @{ + */ +#define MXC_F_DMA_SRCRLD_ADDR_POS 0 /**< SRCRLD_ADDR Position */ +#define MXC_F_DMA_SRCRLD_ADDR ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_SRCRLD_ADDR_POS)) /**< SRCRLD_ADDR Mask */ + +/**@} end of group DMA_SRCRLD_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_DSTRLD DMA_DSTRLD + * @brief Destination Address Reload Value. The value of this register is loaded into + * DMA0_DST upon a count-to-zero condition. + * @{ + */ +#define MXC_F_DMA_DSTRLD_ADDR_POS 0 /**< DSTRLD_ADDR Position */ +#define MXC_F_DMA_DSTRLD_ADDR ((uint32_t)(0x7FFFFFFFUL << MXC_F_DMA_DSTRLD_ADDR_POS)) /**< DSTRLD_ADDR Mask */ + +/**@} end of group DMA_DSTRLD_Register */ + +/** + * @ingroup dma_registers + * @defgroup DMA_CNTRLD DMA_CNTRLD + * @brief DMA Channel Count Reload Register. + * @{ + */ +#define MXC_F_DMA_CNTRLD_CNT_POS 0 /**< CNTRLD_CNT Position */ +#define MXC_F_DMA_CNTRLD_CNT ((uint32_t)(0xFFFFFFUL << MXC_F_DMA_CNTRLD_CNT_POS)) /**< CNTRLD_CNT Mask */ + +#define MXC_F_DMA_CNTRLD_EN_POS 31 /**< CNTRLD_EN Position */ +#define MXC_F_DMA_CNTRLD_EN ((uint32_t)(0x1UL << MXC_F_DMA_CNTRLD_EN_POS)) /**< CNTRLD_EN Mask */ + +/**@} end of group DMA_CNTRLD_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_DMA_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/dvs_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/dvs_regs.h new file mode 100644 index 00000000000..42bfde14fd3 --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/dvs_regs.h @@ -0,0 +1,355 @@ +/** + * @file dvs_regs.h + * @brief Registers, Bit Masks and Bit Positions for the DVS Peripheral Module. + * @note This file is @generated. + * @ingroup dvs_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_DVS_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_DVS_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup dvs + * @defgroup dvs_registers DVS_Registers + * @brief Registers, Bit Masks and Bit Positions for the DVS Peripheral Module. + * @details Dynamic Voltage Scaling + */ + +/** + * @ingroup dvs_registers + * Structure type to access the DVS Registers. + */ +typedef struct { + __IO uint32_t ctl; /**< \b 0x00: DVS CTL Register */ + __IO uint32_t stat; /**< \b 0x04: DVS STAT Register */ + __IO uint32_t direct; /**< \b 0x08: DVS DIRECT Register */ + __IO uint32_t mon; /**< \b 0x00C: DVS MON Register */ + __IO uint32_t adj_up; /**< \b 0x010: DVS ADJ_UP Register */ + __IO uint32_t adj_dwn; /**< \b 0x014: DVS ADJ_DWN Register */ + __IO uint32_t thres_cmp; /**< \b 0x018: DVS THRES_CMP Register */ + __IO uint32_t tap_sel[5]; /**< \b 0x1C: DVS TAP_SEL Register */ +} mxc_dvs_regs_t; + +/* Register offsets for module DVS */ +/** + * @ingroup dvs_registers + * @defgroup DVS_Register_Offsets Register Offsets + * @brief DVS Peripheral Register Offsets from the DVS Base Peripheral Address. + * @{ + */ +#define MXC_R_DVS_CTL ((uint32_t)0x00000000UL) /**< Offset from DVS Base Address: 0x0000 */ +#define MXC_R_DVS_STAT ((uint32_t)0x00000004UL) /**< Offset from DVS Base Address: 0x0004 */ +#define MXC_R_DVS_DIRECT ((uint32_t)0x00000008UL) /**< Offset from DVS Base Address: 0x0008 */ +#define MXC_R_DVS_MON ((uint32_t)0x0000000CUL) /**< Offset from DVS Base Address: 0x000C */ +#define MXC_R_DVS_ADJ_UP ((uint32_t)0x00000010UL) /**< Offset from DVS Base Address: 0x0010 */ +#define MXC_R_DVS_ADJ_DWN ((uint32_t)0x00000014UL) /**< Offset from DVS Base Address: 0x0014 */ +#define MXC_R_DVS_THRES_CMP ((uint32_t)0x00000018UL) /**< Offset from DVS Base Address: 0x0018 */ +#define MXC_R_DVS_TAP_SEL ((uint32_t)0x0000001CUL) /**< Offset from DVS Base Address: 0x001C */ +/**@} end of group dvs_registers */ + +/** + * @ingroup dvs_registers + * @defgroup DVS_CTL DVS_CTL + * @brief Control Register + * @{ + */ +#define MXC_F_DVS_CTL_MON_ENA_POS 0 /**< CTL_MON_ENA Position */ +#define MXC_F_DVS_CTL_MON_ENA ((uint32_t)(0x1UL << MXC_F_DVS_CTL_MON_ENA_POS)) /**< CTL_MON_ENA Mask */ + +#define MXC_F_DVS_CTL_ADJ_ENA_POS 1 /**< CTL_ADJ_ENA Position */ +#define MXC_F_DVS_CTL_ADJ_ENA ((uint32_t)(0x1UL << MXC_F_DVS_CTL_ADJ_ENA_POS)) /**< CTL_ADJ_ENA Mask */ + +#define MXC_F_DVS_CTL_PS_FB_DIS_POS 2 /**< CTL_PS_FB_DIS Position */ +#define MXC_F_DVS_CTL_PS_FB_DIS ((uint32_t)(0x1UL << MXC_F_DVS_CTL_PS_FB_DIS_POS)) /**< CTL_PS_FB_DIS Mask */ + +#define MXC_F_DVS_CTL_CTRL_TAP_ENA_POS 3 /**< CTL_CTRL_TAP_ENA Position */ +#define MXC_F_DVS_CTL_CTRL_TAP_ENA ((uint32_t)(0x1UL << MXC_F_DVS_CTL_CTRL_TAP_ENA_POS)) /**< CTL_CTRL_TAP_ENA Mask */ + +#define MXC_F_DVS_CTL_PROP_DLY_POS 4 /**< CTL_PROP_DLY Position */ +#define MXC_F_DVS_CTL_PROP_DLY ((uint32_t)(0x3UL << MXC_F_DVS_CTL_PROP_DLY_POS)) /**< CTL_PROP_DLY Mask */ + +#define MXC_F_DVS_CTL_MON_ONESHOT_POS 6 /**< CTL_MON_ONESHOT Position */ +#define MXC_F_DVS_CTL_MON_ONESHOT ((uint32_t)(0x1UL << MXC_F_DVS_CTL_MON_ONESHOT_POS)) /**< CTL_MON_ONESHOT Mask */ + +#define MXC_F_DVS_CTL_GO_DIRECT_POS 7 /**< CTL_GO_DIRECT Position */ +#define MXC_F_DVS_CTL_GO_DIRECT ((uint32_t)(0x1UL << MXC_F_DVS_CTL_GO_DIRECT_POS)) /**< CTL_GO_DIRECT Mask */ + +#define MXC_F_DVS_CTL_DIRECT_REG_POS 8 /**< CTL_DIRECT_REG Position */ +#define MXC_F_DVS_CTL_DIRECT_REG ((uint32_t)(0x1UL << MXC_F_DVS_CTL_DIRECT_REG_POS)) /**< CTL_DIRECT_REG Mask */ + +#define MXC_F_DVS_CTL_PRIME_ENA_POS 9 /**< CTL_PRIME_ENA Position */ +#define MXC_F_DVS_CTL_PRIME_ENA ((uint32_t)(0x1UL << MXC_F_DVS_CTL_PRIME_ENA_POS)) /**< CTL_PRIME_ENA Mask */ + +#define MXC_F_DVS_CTL_LIMIT_IE_POS 10 /**< CTL_LIMIT_IE Position */ +#define MXC_F_DVS_CTL_LIMIT_IE ((uint32_t)(0x1UL << MXC_F_DVS_CTL_LIMIT_IE_POS)) /**< CTL_LIMIT_IE Mask */ + +#define MXC_F_DVS_CTL_RANGE_IE_POS 11 /**< CTL_RANGE_IE Position */ +#define MXC_F_DVS_CTL_RANGE_IE ((uint32_t)(0x1UL << MXC_F_DVS_CTL_RANGE_IE_POS)) /**< CTL_RANGE_IE Mask */ + +#define MXC_F_DVS_CTL_ADJ_IE_POS 12 /**< CTL_ADJ_IE Position */ +#define MXC_F_DVS_CTL_ADJ_IE ((uint32_t)(0x1UL << MXC_F_DVS_CTL_ADJ_IE_POS)) /**< CTL_ADJ_IE Mask */ + +#define MXC_F_DVS_CTL_REF_SEL_POS 13 /**< CTL_REF_SEL Position */ +#define MXC_F_DVS_CTL_REF_SEL ((uint32_t)(0xFUL << MXC_F_DVS_CTL_REF_SEL_POS)) /**< CTL_REF_SEL Mask */ + +#define MXC_F_DVS_CTL_INC_VAL_POS 17 /**< CTL_INC_VAL Position */ +#define MXC_F_DVS_CTL_INC_VAL ((uint32_t)(0x7UL << MXC_F_DVS_CTL_INC_VAL_POS)) /**< CTL_INC_VAL Mask */ + +#define MXC_F_DVS_CTL_DVS_PS_APB_DIS_POS 20 /**< CTL_DVS_PS_APB_DIS Position */ +#define MXC_F_DVS_CTL_DVS_PS_APB_DIS ((uint32_t)(0x1UL << MXC_F_DVS_CTL_DVS_PS_APB_DIS_POS)) /**< CTL_DVS_PS_APB_DIS Mask */ + +#define MXC_F_DVS_CTL_DVS_HI_RANGE_ANY_POS 21 /**< CTL_DVS_HI_RANGE_ANY Position */ +#define MXC_F_DVS_CTL_DVS_HI_RANGE_ANY ((uint32_t)(0x1UL << MXC_F_DVS_CTL_DVS_HI_RANGE_ANY_POS)) /**< CTL_DVS_HI_RANGE_ANY Mask */ + +#define MXC_F_DVS_CTL_FB_TO_IE_POS 22 /**< CTL_FB_TO_IE Position */ +#define MXC_F_DVS_CTL_FB_TO_IE ((uint32_t)(0x1UL << MXC_F_DVS_CTL_FB_TO_IE_POS)) /**< CTL_FB_TO_IE Mask */ + +#define MXC_F_DVS_CTL_FC_LV_IE_POS 23 /**< CTL_FC_LV_IE Position */ +#define MXC_F_DVS_CTL_FC_LV_IE ((uint32_t)(0x1UL << MXC_F_DVS_CTL_FC_LV_IE_POS)) /**< CTL_FC_LV_IE Mask */ + +#define MXC_F_DVS_CTL_PD_ACK_ENA_POS 24 /**< CTL_PD_ACK_ENA Position */ +#define MXC_F_DVS_CTL_PD_ACK_ENA ((uint32_t)(0x1UL << MXC_F_DVS_CTL_PD_ACK_ENA_POS)) /**< CTL_PD_ACK_ENA Mask */ + +#define MXC_F_DVS_CTL_ADJ_ABORT_POS 25 /**< CTL_ADJ_ABORT Position */ +#define MXC_F_DVS_CTL_ADJ_ABORT ((uint32_t)(0x1UL << MXC_F_DVS_CTL_ADJ_ABORT_POS)) /**< CTL_ADJ_ABORT Mask */ + +/**@} end of group DVS_CTL_Register */ + +/** + * @ingroup dvs_registers + * @defgroup DVS_STAT DVS_STAT + * @brief Status Fields + * @{ + */ +#define MXC_F_DVS_STAT_DVS_STATE_POS 0 /**< STAT_DVS_STATE Position */ +#define MXC_F_DVS_STAT_DVS_STATE ((uint32_t)(0xFUL << MXC_F_DVS_STAT_DVS_STATE_POS)) /**< STAT_DVS_STATE Mask */ + +#define MXC_F_DVS_STAT_ADJ_UP_ENA_POS 4 /**< STAT_ADJ_UP_ENA Position */ +#define MXC_F_DVS_STAT_ADJ_UP_ENA ((uint32_t)(0x1UL << MXC_F_DVS_STAT_ADJ_UP_ENA_POS)) /**< STAT_ADJ_UP_ENA Mask */ + +#define MXC_F_DVS_STAT_ADJ_DWN_ENA_POS 5 /**< STAT_ADJ_DWN_ENA Position */ +#define MXC_F_DVS_STAT_ADJ_DWN_ENA ((uint32_t)(0x1UL << MXC_F_DVS_STAT_ADJ_DWN_ENA_POS)) /**< STAT_ADJ_DWN_ENA Mask */ + +#define MXC_F_DVS_STAT_ADJ_ACTIVE_POS 6 /**< STAT_ADJ_ACTIVE Position */ +#define MXC_F_DVS_STAT_ADJ_ACTIVE ((uint32_t)(0x1UL << MXC_F_DVS_STAT_ADJ_ACTIVE_POS)) /**< STAT_ADJ_ACTIVE Mask */ + +#define MXC_F_DVS_STAT_CTR_TAP_OK_POS 7 /**< STAT_CTR_TAP_OK Position */ +#define MXC_F_DVS_STAT_CTR_TAP_OK ((uint32_t)(0x1UL << MXC_F_DVS_STAT_CTR_TAP_OK_POS)) /**< STAT_CTR_TAP_OK Mask */ + +#define MXC_F_DVS_STAT_CTR_TAP_SEL_POS 8 /**< STAT_CTR_TAP_SEL Position */ +#define MXC_F_DVS_STAT_CTR_TAP_SEL ((uint32_t)(0x1UL << MXC_F_DVS_STAT_CTR_TAP_SEL_POS)) /**< STAT_CTR_TAP_SEL Mask */ + +#define MXC_F_DVS_STAT_SLOW_TRIP_DET_POS 9 /**< STAT_SLOW_TRIP_DET Position */ +#define MXC_F_DVS_STAT_SLOW_TRIP_DET ((uint32_t)(0x1UL << MXC_F_DVS_STAT_SLOW_TRIP_DET_POS)) /**< STAT_SLOW_TRIP_DET Mask */ + +#define MXC_F_DVS_STAT_FAST_TRIP_DET_POS 10 /**< STAT_FAST_TRIP_DET Position */ +#define MXC_F_DVS_STAT_FAST_TRIP_DET ((uint32_t)(0x1UL << MXC_F_DVS_STAT_FAST_TRIP_DET_POS)) /**< STAT_FAST_TRIP_DET Mask */ + +#define MXC_F_DVS_STAT_PS_IN_RANGE_POS 11 /**< STAT_PS_IN_RANGE Position */ +#define MXC_F_DVS_STAT_PS_IN_RANGE ((uint32_t)(0x1UL << MXC_F_DVS_STAT_PS_IN_RANGE_POS)) /**< STAT_PS_IN_RANGE Mask */ + +#define MXC_F_DVS_STAT_PS_VCNTR_POS 12 /**< STAT_PS_VCNTR Position */ +#define MXC_F_DVS_STAT_PS_VCNTR ((uint32_t)(0x7FUL << MXC_F_DVS_STAT_PS_VCNTR_POS)) /**< STAT_PS_VCNTR Mask */ + +#define MXC_F_DVS_STAT_MON_DLY_OK_POS 19 /**< STAT_MON_DLY_OK Position */ +#define MXC_F_DVS_STAT_MON_DLY_OK ((uint32_t)(0x1UL << MXC_F_DVS_STAT_MON_DLY_OK_POS)) /**< STAT_MON_DLY_OK Mask */ + +#define MXC_F_DVS_STAT_ADJ_DLY_OK_POS 20 /**< STAT_ADJ_DLY_OK Position */ +#define MXC_F_DVS_STAT_ADJ_DLY_OK ((uint32_t)(0x1UL << MXC_F_DVS_STAT_ADJ_DLY_OK_POS)) /**< STAT_ADJ_DLY_OK Mask */ + +#define MXC_F_DVS_STAT_LO_LIMIT_DET_POS 21 /**< STAT_LO_LIMIT_DET Position */ +#define MXC_F_DVS_STAT_LO_LIMIT_DET ((uint32_t)(0x1UL << MXC_F_DVS_STAT_LO_LIMIT_DET_POS)) /**< STAT_LO_LIMIT_DET Mask */ + +#define MXC_F_DVS_STAT_HI_LIMIT_DET_POS 22 /**< STAT_HI_LIMIT_DET Position */ +#define MXC_F_DVS_STAT_HI_LIMIT_DET ((uint32_t)(0x1UL << MXC_F_DVS_STAT_HI_LIMIT_DET_POS)) /**< STAT_HI_LIMIT_DET Mask */ + +#define MXC_F_DVS_STAT_VALID_TAP_POS 23 /**< STAT_VALID_TAP Position */ +#define MXC_F_DVS_STAT_VALID_TAP ((uint32_t)(0x1UL << MXC_F_DVS_STAT_VALID_TAP_POS)) /**< STAT_VALID_TAP Mask */ + +#define MXC_F_DVS_STAT_LIMIT_ERR_POS 24 /**< STAT_LIMIT_ERR Position */ +#define MXC_F_DVS_STAT_LIMIT_ERR ((uint32_t)(0x1UL << MXC_F_DVS_STAT_LIMIT_ERR_POS)) /**< STAT_LIMIT_ERR Mask */ + +#define MXC_F_DVS_STAT_RANGE_ERR_POS 25 /**< STAT_RANGE_ERR Position */ +#define MXC_F_DVS_STAT_RANGE_ERR ((uint32_t)(0x1UL << MXC_F_DVS_STAT_RANGE_ERR_POS)) /**< STAT_RANGE_ERR Mask */ + +#define MXC_F_DVS_STAT_ADJ_ERR_POS 26 /**< STAT_ADJ_ERR Position */ +#define MXC_F_DVS_STAT_ADJ_ERR ((uint32_t)(0x1UL << MXC_F_DVS_STAT_ADJ_ERR_POS)) /**< STAT_ADJ_ERR Mask */ + +#define MXC_F_DVS_STAT_REF_SEL_ERR_POS 27 /**< STAT_REF_SEL_ERR Position */ +#define MXC_F_DVS_STAT_REF_SEL_ERR ((uint32_t)(0x1UL << MXC_F_DVS_STAT_REF_SEL_ERR_POS)) /**< STAT_REF_SEL_ERR Mask */ + +#define MXC_F_DVS_STAT_FB_TO_ERR_POS 28 /**< STAT_FB_TO_ERR Position */ +#define MXC_F_DVS_STAT_FB_TO_ERR ((uint32_t)(0x1UL << MXC_F_DVS_STAT_FB_TO_ERR_POS)) /**< STAT_FB_TO_ERR Mask */ + +#define MXC_F_DVS_STAT_FB_TO_ERR_S_POS 29 /**< STAT_FB_TO_ERR_S Position */ +#define MXC_F_DVS_STAT_FB_TO_ERR_S ((uint32_t)(0x1UL << MXC_F_DVS_STAT_FB_TO_ERR_S_POS)) /**< STAT_FB_TO_ERR_S Mask */ + +#define MXC_F_DVS_STAT_FC_LV_DET_INT_POS 30 /**< STAT_FC_LV_DET_INT Position */ +#define MXC_F_DVS_STAT_FC_LV_DET_INT ((uint32_t)(0x1UL << MXC_F_DVS_STAT_FC_LV_DET_INT_POS)) /**< STAT_FC_LV_DET_INT Mask */ + +#define MXC_F_DVS_STAT_FC_LV_DET_S_POS 31 /**< STAT_FC_LV_DET_S Position */ +#define MXC_F_DVS_STAT_FC_LV_DET_S ((uint32_t)(0x1UL << MXC_F_DVS_STAT_FC_LV_DET_S_POS)) /**< STAT_FC_LV_DET_S Mask */ + +/**@} end of group DVS_STAT_Register */ + +/** + * @ingroup dvs_registers + * @defgroup DVS_DIRECT DVS_DIRECT + * @brief Direct control of target voltage + * @{ + */ +#define MXC_F_DVS_DIRECT_VOLTAGE_POS 0 /**< DIRECT_VOLTAGE Position */ +#define MXC_F_DVS_DIRECT_VOLTAGE ((uint32_t)(0x7FUL << MXC_F_DVS_DIRECT_VOLTAGE_POS)) /**< DIRECT_VOLTAGE Mask */ + +/**@} end of group DVS_DIRECT_Register */ + +/** + * @ingroup dvs_registers + * @defgroup DVS_MON DVS_MON + * @brief Monitor Delay + * @{ + */ +#define MXC_F_DVS_MON_DLY_POS 0 /**< MON_DLY Position */ +#define MXC_F_DVS_MON_DLY ((uint32_t)(0xFFFFFFUL << MXC_F_DVS_MON_DLY_POS)) /**< MON_DLY Mask */ + +#define MXC_F_DVS_MON_PRE_POS 24 /**< MON_PRE Position */ +#define MXC_F_DVS_MON_PRE ((uint32_t)(0xFFUL << MXC_F_DVS_MON_PRE_POS)) /**< MON_PRE Mask */ + +/**@} end of group DVS_MON_Register */ + +/** + * @ingroup dvs_registers + * @defgroup DVS_ADJ_UP DVS_ADJ_UP + * @brief Up Delay Register + * @{ + */ +#define MXC_F_DVS_ADJ_UP_DLY_POS 0 /**< ADJ_UP_DLY Position */ +#define MXC_F_DVS_ADJ_UP_DLY ((uint32_t)(0xFFFFUL << MXC_F_DVS_ADJ_UP_DLY_POS)) /**< ADJ_UP_DLY Mask */ + +#define MXC_F_DVS_ADJ_UP_PRE_POS 16 /**< ADJ_UP_PRE Position */ +#define MXC_F_DVS_ADJ_UP_PRE ((uint32_t)(0xFFUL << MXC_F_DVS_ADJ_UP_PRE_POS)) /**< ADJ_UP_PRE Mask */ + +/**@} end of group DVS_ADJ_UP_Register */ + +/** + * @ingroup dvs_registers + * @defgroup DVS_ADJ_DWN DVS_ADJ_DWN + * @brief Down Delay Register + * @{ + */ +#define MXC_F_DVS_ADJ_DWN_DLY_POS 0 /**< ADJ_DWN_DLY Position */ +#define MXC_F_DVS_ADJ_DWN_DLY ((uint32_t)(0xFFFFUL << MXC_F_DVS_ADJ_DWN_DLY_POS)) /**< ADJ_DWN_DLY Mask */ + +#define MXC_F_DVS_ADJ_DWN_PRE_POS 16 /**< ADJ_DWN_PRE Position */ +#define MXC_F_DVS_ADJ_DWN_PRE ((uint32_t)(0xFFUL << MXC_F_DVS_ADJ_DWN_PRE_POS)) /**< ADJ_DWN_PRE Mask */ + +/**@} end of group DVS_ADJ_DWN_Register */ + +/** + * @ingroup dvs_registers + * @defgroup DVS_THRES_CMP DVS_THRES_CMP + * @brief Up Delay Register + * @{ + */ +#define MXC_F_DVS_THRES_CMP_VCNTR_THRES_CNT_POS 0 /**< THRES_CMP_VCNTR_THRES_CNT Position */ +#define MXC_F_DVS_THRES_CMP_VCNTR_THRES_CNT ((uint32_t)(0x7FUL << MXC_F_DVS_THRES_CMP_VCNTR_THRES_CNT_POS)) /**< THRES_CMP_VCNTR_THRES_CNT Mask */ + +#define MXC_F_DVS_THRES_CMP_VCNTR_THRES_MASK_POS 8 /**< THRES_CMP_VCNTR_THRES_MASK Position */ +#define MXC_F_DVS_THRES_CMP_VCNTR_THRES_MASK ((uint32_t)(0x7FUL << MXC_F_DVS_THRES_CMP_VCNTR_THRES_MASK_POS)) /**< THRES_CMP_VCNTR_THRES_MASK Mask */ + +/**@} end of group DVS_THRES_CMP_Register */ + +/** + * @ingroup dvs_registers + * @defgroup DVS_TAP_SEL DVS_TAP_SEL + * @brief DVS Tap Select Register + * @{ + */ +#define MXC_F_DVS_TAP_SEL_LO_POS 0 /**< TAP_SEL_LO Position */ +#define MXC_F_DVS_TAP_SEL_LO ((uint32_t)(0x1FUL << MXC_F_DVS_TAP_SEL_LO_POS)) /**< TAP_SEL_LO Mask */ + +#define MXC_F_DVS_TAP_SEL_LO_TAP_STAT_POS 5 /**< TAP_SEL_LO_TAP_STAT Position */ +#define MXC_F_DVS_TAP_SEL_LO_TAP_STAT ((uint32_t)(0x1UL << MXC_F_DVS_TAP_SEL_LO_TAP_STAT_POS)) /**< TAP_SEL_LO_TAP_STAT Mask */ + +#define MXC_F_DVS_TAP_SEL_CTR_TAP_STAT_POS 6 /**< TAP_SEL_CTR_TAP_STAT Position */ +#define MXC_F_DVS_TAP_SEL_CTR_TAP_STAT ((uint32_t)(0x1UL << MXC_F_DVS_TAP_SEL_CTR_TAP_STAT_POS)) /**< TAP_SEL_CTR_TAP_STAT Mask */ + +#define MXC_F_DVS_TAP_SEL_HI_TAP_STAT_POS 7 /**< TAP_SEL_HI_TAP_STAT Position */ +#define MXC_F_DVS_TAP_SEL_HI_TAP_STAT ((uint32_t)(0x1UL << MXC_F_DVS_TAP_SEL_HI_TAP_STAT_POS)) /**< TAP_SEL_HI_TAP_STAT Mask */ + +#define MXC_F_DVS_TAP_SEL_HI_POS 8 /**< TAP_SEL_HI Position */ +#define MXC_F_DVS_TAP_SEL_HI ((uint32_t)(0x1FUL << MXC_F_DVS_TAP_SEL_HI_POS)) /**< TAP_SEL_HI Mask */ + +#define MXC_F_DVS_TAP_SEL_CTR_POS 16 /**< TAP_SEL_CTR Position */ +#define MXC_F_DVS_TAP_SEL_CTR ((uint32_t)(0x1FUL << MXC_F_DVS_TAP_SEL_CTR_POS)) /**< TAP_SEL_CTR Mask */ + +#define MXC_F_DVS_TAP_SEL_COARSE_POS 24 /**< TAP_SEL_COARSE Position */ +#define MXC_F_DVS_TAP_SEL_COARSE ((uint32_t)(0x7UL << MXC_F_DVS_TAP_SEL_COARSE_POS)) /**< TAP_SEL_COARSE Mask */ + +#define MXC_F_DVS_TAP_SEL_DET_DLY_POS 29 /**< TAP_SEL_DET_DLY Position */ +#define MXC_F_DVS_TAP_SEL_DET_DLY ((uint32_t)(0x3UL << MXC_F_DVS_TAP_SEL_DET_DLY_POS)) /**< TAP_SEL_DET_DLY Mask */ + +#define MXC_F_DVS_TAP_SEL_DELAY_ACT_POS 31 /**< TAP_SEL_DELAY_ACT Position */ +#define MXC_F_DVS_TAP_SEL_DELAY_ACT ((uint32_t)(0x1UL << MXC_F_DVS_TAP_SEL_DELAY_ACT_POS)) /**< TAP_SEL_DELAY_ACT Mask */ + +/**@} end of group DVS_TAP_SEL_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_DVS_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h new file mode 100644 index 00000000000..42eead07591 --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h @@ -0,0 +1,265 @@ +/** + * @file fcr_regs.h + * @brief Registers, Bit Masks and Bit Positions for the FCR Peripheral Module. + * @note This file is @generated. + * @ingroup fcr_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_FCR_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_FCR_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup fcr + * @defgroup fcr_registers FCR_Registers + * @brief Registers, Bit Masks and Bit Positions for the FCR Peripheral Module. + * @details Function Control Register. + */ + +/** + * @ingroup fcr_registers + * Structure type to access the FCR Registers. + */ +typedef struct { + __IO uint32_t fctrl0; /**< \b 0x00: FCR FCTRL0 Register */ + __IO uint32_t fctrl1; /**< \b 0x04: FCR FCTRL1 Register */ + __IO uint32_t fctrl2; /**< \b 0x08: FCR FCTRL2 Register */ + __IO uint32_t fctrl3; /**< \b 0x0C: FCR FCTRL3 Register */ + __R uint32_t rsv_0x10_0x1b[3]; + __IO uint32_t gp; /**< \b 0x1C: FCR GP Register */ + __IO uint32_t msrtrim; /**< \b 0x20: FCR MSRTRIM Register */ + __IO uint32_t flvfilt; /**< \b 0x24: FCR FLVFILT Register */ +} mxc_fcr_regs_t; + +/* Register offsets for module FCR */ +/** + * @ingroup fcr_registers + * @defgroup FCR_Register_Offsets Register Offsets + * @brief FCR Peripheral Register Offsets from the FCR Base Peripheral Address. + * @{ + */ +#define MXC_R_FCR_FCTRL0 ((uint32_t)0x00000000UL) /**< Offset from FCR Base Address: 0x0000 */ +#define MXC_R_FCR_FCTRL1 ((uint32_t)0x00000004UL) /**< Offset from FCR Base Address: 0x0004 */ +#define MXC_R_FCR_FCTRL2 ((uint32_t)0x00000008UL) /**< Offset from FCR Base Address: 0x0008 */ +#define MXC_R_FCR_FCTRL3 ((uint32_t)0x0000000CUL) /**< Offset from FCR Base Address: 0x000C */ +#define MXC_R_FCR_GP ((uint32_t)0x0000001CUL) /**< Offset from FCR Base Address: 0x001C */ +#define MXC_R_FCR_MSRTRIM ((uint32_t)0x00000020UL) /**< Offset from FCR Base Address: 0x0020 */ +#define MXC_R_FCR_FLVFILT ((uint32_t)0x00000024UL) /**< Offset from FCR Base Address: 0x0024 */ +/**@} end of group fcr_registers */ + +/** + * @ingroup fcr_registers + * @defgroup FCR_FCTRL0 FCR_FCTRL0 + * @brief Register 0. + * @{ + */ +#define MXC_F_FCR_FCTRL0_USBCLKSEL_POS 16 /**< FCTRL0_USBCLKSEL Position */ +#define MXC_F_FCR_FCTRL0_USBCLKSEL ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_USBCLKSEL_POS)) /**< FCTRL0_USBCLKSEL Mask */ + +#define MXC_F_FCR_FCTRL0_I2C0DGEN0_POS 20 /**< FCTRL0_I2C0DGEN0 Position */ +#define MXC_F_FCR_FCTRL0_I2C0DGEN0 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0DGEN0_POS)) /**< FCTRL0_I2C0DGEN0 Mask */ + +#define MXC_F_FCR_FCTRL0_I2C0DGEN1_POS 21 /**< FCTRL0_I2C0DGEN1 Position */ +#define MXC_F_FCR_FCTRL0_I2C0DGEN1 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0DGEN1_POS)) /**< FCTRL0_I2C0DGEN1 Mask */ + +#define MXC_F_FCR_FCTRL0_I2C1DGEN0_POS 22 /**< FCTRL0_I2C1DGEN0 Position */ +#define MXC_F_FCR_FCTRL0_I2C1DGEN0 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1DGEN0_POS)) /**< FCTRL0_I2C1DGEN0 Mask */ + +#define MXC_F_FCR_FCTRL0_I2C1DGEN1_POS 23 /**< FCTRL0_I2C1DGEN1 Position */ +#define MXC_F_FCR_FCTRL0_I2C1DGEN1 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1DGEN1_POS)) /**< FCTRL0_I2C1DGEN1 Mask */ + +#define MXC_F_FCR_FCTRL0_I2C2ADGEN0_POS 24 /**< FCTRL0_I2C2ADGEN0 Position */ +#define MXC_F_FCR_FCTRL0_I2C2ADGEN0 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2ADGEN0_POS)) /**< FCTRL0_I2C2ADGEN0 Mask */ + +#define MXC_F_FCR_FCTRL0_I2C2ADGEN1_POS 25 /**< FCTRL0_I2C2ADGEN1 Position */ +#define MXC_F_FCR_FCTRL0_I2C2ADGEN1 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2ADGEN1_POS)) /**< FCTRL0_I2C2ADGEN1 Mask */ + +#define MXC_F_FCR_FCTRL0_I2C2BDGEN0_POS 26 /**< FCTRL0_I2C2BDGEN0 Position */ +#define MXC_F_FCR_FCTRL0_I2C2BDGEN0 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2BDGEN0_POS)) /**< FCTRL0_I2C2BDGEN0 Mask */ + +#define MXC_F_FCR_FCTRL0_I2C2BDGEN1_POS 27 /**< FCTRL0_I2C2BDGEN1 Position */ +#define MXC_F_FCR_FCTRL0_I2C2BDGEN1 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2BDGEN1_POS)) /**< FCTRL0_I2C2BDGEN1 Mask */ + +#define MXC_F_FCR_FCTRL0_I2C2CDGEN0_POS 28 /**< FCTRL0_I2C2CDGEN0 Position */ +#define MXC_F_FCR_FCTRL0_I2C2CDGEN0 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2CDGEN0_POS)) /**< FCTRL0_I2C2CDGEN0 Mask */ + +#define MXC_F_FCR_FCTRL0_I2C2CDGEN1_POS 29 /**< FCTRL0_I2C2CDGEN1 Position */ +#define MXC_F_FCR_FCTRL0_I2C2CDGEN1 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2CDGEN1_POS)) /**< FCTRL0_I2C2CDGEN1 Mask */ + +/**@} end of group FCR_FCTRL0_Register */ + +/** + * @ingroup fcr_registers + * @defgroup FCR_FCTRL1 FCR_FCTRL1 + * @brief Register 1. + * @{ + */ +#define MXC_F_FCR_FCTRL1_AC_EN_POS 0 /**< FCTRL1_AC_EN Position */ +#define MXC_F_FCR_FCTRL1_AC_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL1_AC_EN_POS)) /**< FCTRL1_AC_EN Mask */ + +#define MXC_F_FCR_FCTRL1_AC_RUN_POS 1 /**< FCTRL1_AC_RUN Position */ +#define MXC_F_FCR_FCTRL1_AC_RUN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL1_AC_RUN_POS)) /**< FCTRL1_AC_RUN Mask */ + +#define MXC_F_FCR_FCTRL1_LOAD_TRIM_POS 2 /**< FCTRL1_LOAD_TRIM Position */ +#define MXC_F_FCR_FCTRL1_LOAD_TRIM ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL1_LOAD_TRIM_POS)) /**< FCTRL1_LOAD_TRIM Mask */ + +#define MXC_F_FCR_FCTRL1_GAIN_INV_POS 3 /**< FCTRL1_GAIN_INV Position */ +#define MXC_F_FCR_FCTRL1_GAIN_INV ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL1_GAIN_INV_POS)) /**< FCTRL1_GAIN_INV Mask */ + +#define MXC_F_FCR_FCTRL1_ATOMIC_POS 4 /**< FCTRL1_ATOMIC Position */ +#define MXC_F_FCR_FCTRL1_ATOMIC ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL1_ATOMIC_POS)) /**< FCTRL1_ATOMIC Mask */ + +#define MXC_F_FCR_FCTRL1_MU_POS 8 /**< FCTRL1_MU Position */ +#define MXC_F_FCR_FCTRL1_MU ((uint32_t)(0xFFFUL << MXC_F_FCR_FCTRL1_MU_POS)) /**< FCTRL1_MU Mask */ + +#define MXC_F_FCR_FCTRL1_AC_TRIM_POS 23 /**< FCTRL1_AC_TRIM Position */ +#define MXC_F_FCR_FCTRL1_AC_TRIM ((uint32_t)(0x1FFUL << MXC_F_FCR_FCTRL1_AC_TRIM_POS)) /**< FCTRL1_AC_TRIM Mask */ + +/**@} end of group FCR_FCTRL1_Register */ + +/** + * @ingroup fcr_registers + * @defgroup FCR_FCTRL2 FCR_FCTRL2 + * @brief Register 2. + * @{ + */ +#define MXC_F_FCR_FCTRL2_NFC_FWD_EN_POS 0 /**< FCTRL2_NFC_FWD_EN Position */ +#define MXC_F_FCR_FCTRL2_NFC_FWD_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL2_NFC_FWD_EN_POS)) /**< FCTRL2_NFC_FWD_EN Mask */ + +#define MXC_F_FCR_FCTRL2_NFC_CLK_EN_POS 1 /**< FCTRL2_NFC_CLK_EN Position */ +#define MXC_F_FCR_FCTRL2_NFC_CLK_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL2_NFC_CLK_EN_POS)) /**< FCTRL2_NFC_CLK_EN Mask */ + +#define MXC_F_FCR_FCTRL2_NFC_FWD_TX_DATA_OVR_POS 2 /**< FCTRL2_NFC_FWD_TX_DATA_OVR Position */ +#define MXC_F_FCR_FCTRL2_NFC_FWD_TX_DATA_OVR ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL2_NFC_FWD_TX_DATA_OVR_POS)) /**< FCTRL2_NFC_FWD_TX_DATA_OVR Mask */ + +#define MXC_F_FCR_FCTRL2_XO_EN_DGL_POS 3 /**< FCTRL2_XO_EN_DGL Position */ +#define MXC_F_FCR_FCTRL2_XO_EN_DGL ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL2_XO_EN_DGL_POS)) /**< FCTRL2_XO_EN_DGL Mask */ + +#define MXC_F_FCR_FCTRL2_RX_BIAS_PD_POS 4 /**< FCTRL2_RX_BIAS_PD Position */ +#define MXC_F_FCR_FCTRL2_RX_BIAS_PD ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL2_RX_BIAS_PD_POS)) /**< FCTRL2_RX_BIAS_PD Mask */ + +#define MXC_F_FCR_FCTRL2_RX_BIAS_EN_POS 5 /**< FCTRL2_RX_BIAS_EN Position */ +#define MXC_F_FCR_FCTRL2_RX_BIAS_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL2_RX_BIAS_EN_POS)) /**< FCTRL2_RX_BIAS_EN Mask */ + +#define MXC_F_FCR_FCTRL2_RX_TM_VBG_VABUS_POS 6 /**< FCTRL2_RX_TM_VBG_VABUS Position */ +#define MXC_F_FCR_FCTRL2_RX_TM_VBG_VABUS ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL2_RX_TM_VBG_VABUS_POS)) /**< FCTRL2_RX_TM_VBG_VABUS Mask */ + +#define MXC_F_FCR_FCTRL2_RX_TM_BIAS_POS 7 /**< FCTRL2_RX_TM_BIAS Position */ +#define MXC_F_FCR_FCTRL2_RX_TM_BIAS ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL2_RX_TM_BIAS_POS)) /**< FCTRL2_RX_TM_BIAS Mask */ + +#define MXC_F_FCR_FCTRL2_NFC_FWD_DOUT_POS 8 /**< FCTRL2_NFC_FWD_DOUT Position */ +#define MXC_F_FCR_FCTRL2_NFC_FWD_DOUT ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL2_NFC_FWD_DOUT_POS)) /**< FCTRL2_NFC_FWD_DOUT Mask */ + +/**@} end of group FCR_FCTRL2_Register */ + +/** + * @ingroup fcr_registers + * @defgroup FCR_FCTRL3 FCR_FCTRL3 + * @brief Register 3. + * @{ + */ +#define MXC_F_FCR_FCTRL3_DONECNT_POS 0 /**< FCTRL3_DONECNT Position */ +#define MXC_F_FCR_FCTRL3_DONECNT ((uint32_t)(0xFFUL << MXC_F_FCR_FCTRL3_DONECNT_POS)) /**< FCTRL3_DONECNT Mask */ + +/**@} end of group FCR_FCTRL3_Register */ + +/** + * @ingroup fcr_registers + * @defgroup FCR_GP FCR_GP + * @brief General Purpose Register. + * @{ + */ +#define MXC_F_FCR_GP_GP_POS 0 /**< GP_GP Position */ +#define MXC_F_FCR_GP_GP ((uint32_t)(0xFFFFFFFFUL << MXC_F_FCR_GP_GP_POS)) /**< GP_GP Mask */ + +/**@} end of group FCR_GP_Register */ + +/** + * @ingroup fcr_registers + * @defgroup FCR_MSRTRIM FCR_MSRTRIM + * @brief MSR Trim Register. + * @{ + */ +#define MXC_F_FCR_MSRTRIM_R1_POS 0 /**< MSRTRIM_R1 Position */ +#define MXC_F_FCR_MSRTRIM_R1 ((uint32_t)(0x3UL << MXC_F_FCR_MSRTRIM_R1_POS)) /**< MSRTRIM_R1 Mask */ + +#define MXC_F_FCR_MSRTRIM_R2_POS 2 /**< MSRTRIM_R2 Position */ +#define MXC_F_FCR_MSRTRIM_R2 ((uint32_t)(0x7UL << MXC_F_FCR_MSRTRIM_R2_POS)) /**< MSRTRIM_R2 Mask */ + +/**@} end of group FCR_MSRTRIM_Register */ + +/** + * @ingroup fcr_registers + * @defgroup FCR_FLVFILT FCR_FLVFILT + * @brief Flash Low Voltage Filter Control Register. + * @{ + */ +#define MXC_F_FCR_FLVFILT_NUM_POS 0 /**< FLVFILT_NUM Position */ +#define MXC_F_FCR_FLVFILT_NUM ((uint32_t)(0xFFUL << MXC_F_FCR_FLVFILT_NUM_POS)) /**< FLVFILT_NUM Mask */ + +#define MXC_F_FCR_FLVFILT_RATE_POS 8 /**< FLVFILT_RATE Position */ +#define MXC_F_FCR_FLVFILT_RATE ((uint32_t)(0xFFUL << MXC_F_FCR_FLVFILT_RATE_POS)) /**< FLVFILT_RATE Mask */ + +#define MXC_F_FCR_FLVFILT_DELAY_POS 16 /**< FLVFILT_DELAY Position */ +#define MXC_F_FCR_FLVFILT_DELAY ((uint32_t)(0xFFUL << MXC_F_FCR_FLVFILT_DELAY_POS)) /**< FLVFILT_DELAY Mask */ + +/**@} end of group FCR_FLVFILT_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_FCR_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/flc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/flc_regs.h new file mode 100644 index 00000000000..fff8fabef3a --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/flc_regs.h @@ -0,0 +1,286 @@ +/** + * @file flc_regs.h + * @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module. + * @note This file is @generated. + * @ingroup flc_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_FLC_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_FLC_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup flc + * @defgroup flc_registers FLC_Registers + * @brief Registers, Bit Masks and Bit Positions for the FLC Peripheral Module. + * @details Flash Memory Control. + */ + +/** + * @ingroup flc_registers + * Structure type to access the FLC Registers. + */ +typedef struct { + __IO uint32_t addr; /**< \b 0x00: FLC ADDR Register */ + __IO uint32_t clkdiv; /**< \b 0x04: FLC CLKDIV Register */ + __IO uint32_t ctrl; /**< \b 0x08: FLC CTRL Register */ + __R uint32_t rsv_0xc_0x23[6]; + __IO uint32_t intr; /**< \b 0x024: FLC INTR Register */ + __R uint32_t rsv_0x28; + __IO uint32_t eccdata; /**< \b 0x2C: FLC ECCDATA Register */ + __IO uint32_t data[4]; /**< \b 0x30: FLC DATA Register */ + __O uint32_t actrl; /**< \b 0x40: FLC ACTRL Register */ + __R uint32_t rsv_0x44_0x7f[15]; + __IO uint32_t welr0; /**< \b 0x80: FLC WELR0 Register */ + __R uint32_t rsv_0x84; + __IO uint32_t welr1; /**< \b 0x88: FLC WELR1 Register */ + __R uint32_t rsv_0x8c; + __IO uint32_t rlr0; /**< \b 0x90: FLC RLR0 Register */ + __R uint32_t rsv_0x94; + __IO uint32_t rlr1; /**< \b 0x98: FLC RLR1 Register */ +} mxc_flc_regs_t; + +/* Register offsets for module FLC */ +/** + * @ingroup flc_registers + * @defgroup FLC_Register_Offsets Register Offsets + * @brief FLC Peripheral Register Offsets from the FLC Base Peripheral Address. + * @{ + */ +#define MXC_R_FLC_ADDR ((uint32_t)0x00000000UL) /**< Offset from FLC Base Address: 0x0000 */ +#define MXC_R_FLC_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: 0x0004 */ +#define MXC_R_FLC_CTRL ((uint32_t)0x00000008UL) /**< Offset from FLC Base Address: 0x0008 */ +#define MXC_R_FLC_INTR ((uint32_t)0x00000024UL) /**< Offset from FLC Base Address: 0x0024 */ +#define MXC_R_FLC_ECCDATA ((uint32_t)0x0000002CUL) /**< Offset from FLC Base Address: 0x002C */ +#define MXC_R_FLC_DATA ((uint32_t)0x00000030UL) /**< Offset from FLC Base Address: 0x0030 */ +#define MXC_R_FLC_ACTRL ((uint32_t)0x00000040UL) /**< Offset from FLC Base Address: 0x0040 */ +#define MXC_R_FLC_WELR0 ((uint32_t)0x00000080UL) /**< Offset from FLC Base Address: 0x0080 */ +#define MXC_R_FLC_WELR1 ((uint32_t)0x00000088UL) /**< Offset from FLC Base Address: 0x0088 */ +#define MXC_R_FLC_RLR0 ((uint32_t)0x00000090UL) /**< Offset from FLC Base Address: 0x0090 */ +#define MXC_R_FLC_RLR1 ((uint32_t)0x00000098UL) /**< Offset from FLC Base Address: 0x0098 */ +/**@} end of group flc_registers */ + +/** + * @ingroup flc_registers + * @defgroup FLC_ADDR FLC_ADDR + * @brief Flash Write Address. + * @{ + */ +#define MXC_F_FLC_ADDR_ADDR_POS 0 /**< ADDR_ADDR Position */ +#define MXC_F_FLC_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */ + +/**@} end of group FLC_ADDR_Register */ + +/** + * @ingroup flc_registers + * @defgroup FLC_CLKDIV FLC_CLKDIV + * @brief Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 + * MHz clock for Flash controller. + * @{ + */ +#define MXC_F_FLC_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */ +#define MXC_F_FLC_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */ + +/**@} end of group FLC_CLKDIV_Register */ + +/** + * @ingroup flc_registers + * @defgroup FLC_CTRL FLC_CTRL + * @brief Flash Control Register. + * @{ + */ +#define MXC_F_FLC_CTRL_WR_POS 0 /**< CTRL_WR Position */ +#define MXC_F_FLC_CTRL_WR ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_WR_POS)) /**< CTRL_WR Mask */ + +#define MXC_F_FLC_CTRL_ME_POS 1 /**< CTRL_ME Position */ +#define MXC_F_FLC_CTRL_ME ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_ME_POS)) /**< CTRL_ME Mask */ + +#define MXC_F_FLC_CTRL_PGE_POS 2 /**< CTRL_PGE Position */ +#define MXC_F_FLC_CTRL_PGE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_PGE_POS)) /**< CTRL_PGE Mask */ + +#define MXC_F_FLC_CTRL_ERASE_CODE_POS 8 /**< CTRL_ERASE_CODE Position */ +#define MXC_F_FLC_CTRL_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS)) /**< CTRL_ERASE_CODE Mask */ +#define MXC_V_FLC_CTRL_ERASE_CODE_NOP ((uint32_t)0x0UL) /**< CTRL_ERASE_CODE_NOP Value */ +#define MXC_S_FLC_CTRL_ERASE_CODE_NOP (MXC_V_FLC_CTRL_ERASE_CODE_NOP << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_NOP Setting */ +#define MXC_V_FLC_CTRL_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL) /**< CTRL_ERASE_CODE_ERASEPAGE Value */ +#define MXC_S_FLC_CTRL_ERASE_CODE_ERASEPAGE (MXC_V_FLC_CTRL_ERASE_CODE_ERASEPAGE << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEPAGE Setting */ +#define MXC_V_FLC_CTRL_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL) /**< CTRL_ERASE_CODE_ERASEALL Value */ +#define MXC_S_FLC_CTRL_ERASE_CODE_ERASEALL (MXC_V_FLC_CTRL_ERASE_CODE_ERASEALL << MXC_F_FLC_CTRL_ERASE_CODE_POS) /**< CTRL_ERASE_CODE_ERASEALL Setting */ + +#define MXC_F_FLC_CTRL_PEND_POS 24 /**< CTRL_PEND Position */ +#define MXC_F_FLC_CTRL_PEND ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_PEND_POS)) /**< CTRL_PEND Mask */ + +#define MXC_F_FLC_CTRL_LVE_POS 25 /**< CTRL_LVE Position */ +#define MXC_F_FLC_CTRL_LVE ((uint32_t)(0x1UL << MXC_F_FLC_CTRL_LVE_POS)) /**< CTRL_LVE Mask */ + +#define MXC_F_FLC_CTRL_UNLOCK_POS 28 /**< CTRL_UNLOCK Position */ +#define MXC_F_FLC_CTRL_UNLOCK ((uint32_t)(0xFUL << MXC_F_FLC_CTRL_UNLOCK_POS)) /**< CTRL_UNLOCK Mask */ +#define MXC_V_FLC_CTRL_UNLOCK_UNLOCKED ((uint32_t)0x2UL) /**< CTRL_UNLOCK_UNLOCKED Value */ +#define MXC_S_FLC_CTRL_UNLOCK_UNLOCKED (MXC_V_FLC_CTRL_UNLOCK_UNLOCKED << MXC_F_FLC_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_UNLOCKED Setting */ +#define MXC_V_FLC_CTRL_UNLOCK_LOCKED ((uint32_t)0x3UL) /**< CTRL_UNLOCK_LOCKED Value */ +#define MXC_S_FLC_CTRL_UNLOCK_LOCKED (MXC_V_FLC_CTRL_UNLOCK_LOCKED << MXC_F_FLC_CTRL_UNLOCK_POS) /**< CTRL_UNLOCK_LOCKED Setting */ + +/**@} end of group FLC_CTRL_Register */ + +/** + * @ingroup flc_registers + * @defgroup FLC_INTR FLC_INTR + * @brief Flash Interrupt Register. + * @{ + */ +#define MXC_F_FLC_INTR_DONE_IF_POS 0 /**< INTR_DONE_IF Position */ +#define MXC_F_FLC_INTR_DONE_IF ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_IF_POS)) /**< INTR_DONE_IF Mask */ + +#define MXC_F_FLC_INTR_AF_IF_POS 1 /**< INTR_AF_IF Position */ +#define MXC_F_FLC_INTR_AF_IF ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AF_IF_POS)) /**< INTR_AF_IF Mask */ + +#define MXC_F_FLC_INTR_DONE_IE_POS 8 /**< INTR_DONE_IE Position */ +#define MXC_F_FLC_INTR_DONE_IE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_IE_POS)) /**< INTR_DONE_IE Mask */ + +#define MXC_F_FLC_INTR_AF_IE_POS 9 /**< INTR_AF_IE Position */ +#define MXC_F_FLC_INTR_AF_IE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AF_IE_POS)) /**< INTR_AF_IE Mask */ + +/**@} end of group FLC_INTR_Register */ + +/** + * @ingroup flc_registers + * @defgroup FLC_ECCDATA FLC_ECCDATA + * @brief ECC Data Register. + * @{ + */ +#define MXC_F_FLC_ECCDATA_EVEN_POS 0 /**< ECCDATA_EVEN Position */ +#define MXC_F_FLC_ECCDATA_EVEN ((uint32_t)(0x1FFUL << MXC_F_FLC_ECCDATA_EVEN_POS)) /**< ECCDATA_EVEN Mask */ + +#define MXC_F_FLC_ECCDATA_ODD_POS 16 /**< ECCDATA_ODD Position */ +#define MXC_F_FLC_ECCDATA_ODD ((uint32_t)(0x1FFUL << MXC_F_FLC_ECCDATA_ODD_POS)) /**< ECCDATA_ODD Mask */ + +/**@} end of group FLC_ECCDATA_Register */ + +/** + * @ingroup flc_registers + * @defgroup FLC_DATA FLC_DATA + * @brief Flash Write Data. + * @{ + */ +#define MXC_F_FLC_DATA_DATA_POS 0 /**< DATA_DATA Position */ +#define MXC_F_FLC_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_DATA_DATA_POS)) /**< DATA_DATA Mask */ + +/**@} end of group FLC_DATA_Register */ + +/** + * @ingroup flc_registers + * @defgroup FLC_ACTRL FLC_ACTRL + * @brief Access Control Register. Writing the ACTRL register with the following values in + * the order shown, allows read and write access to the system and user Information + * block: pflc-actrl = 0x3a7f5ca3; pflc-actrl = 0xa1e34f20; pflc-actrl + * = 0x9608b2c1. When unlocked, a write of any word will disable access to system + * and user information block. Readback of this register is always zero. + * @{ + */ +#define MXC_F_FLC_ACTRL_ACTRL_POS 0 /**< ACTRL_ACTRL Position */ +#define MXC_F_FLC_ACTRL_ACTRL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ACTRL_ACTRL_POS)) /**< ACTRL_ACTRL Mask */ + +/**@} end of group FLC_ACTRL_Register */ + +/** + * @ingroup flc_registers + * @defgroup FLC_WELR0 FLC_WELR0 + * @brief WELR0 + * @{ + */ +#define MXC_F_FLC_WELR0_WELR0_POS 0 /**< WELR0_WELR0 Position */ +#define MXC_F_FLC_WELR0_WELR0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_WELR0_WELR0_POS)) /**< WELR0_WELR0 Mask */ + +/**@} end of group FLC_WELR0_Register */ + +/** + * @ingroup flc_registers + * @defgroup FLC_WELR1 FLC_WELR1 + * @brief WELR1 + * @{ + */ +#define MXC_F_FLC_WELR1_WELR1_POS 0 /**< WELR1_WELR1 Position */ +#define MXC_F_FLC_WELR1_WELR1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_WELR1_WELR1_POS)) /**< WELR1_WELR1 Mask */ + +/**@} end of group FLC_WELR1_Register */ + +/** + * @ingroup flc_registers + * @defgroup FLC_RLR0 FLC_RLR0 + * @brief RLR0 + * @{ + */ +#define MXC_F_FLC_RLR0_RLR0_POS 0 /**< RLR0_RLR0 Position */ +#define MXC_F_FLC_RLR0_RLR0 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_RLR0_RLR0_POS)) /**< RLR0_RLR0 Mask */ + +/**@} end of group FLC_RLR0_Register */ + +/** + * @ingroup flc_registers + * @defgroup FLC_RLR1 FLC_RLR1 + * @brief RLR1 + * @{ + */ +#define MXC_F_FLC_RLR1_RLR1_POS 0 /**< RLR1_RLR1 Position */ +#define MXC_F_FLC_RLR1_RLR1 ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_RLR1_RLR1_POS)) /**< RLR1_RLR1 Mask */ + +/**@} end of group FLC_RLR1_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_FLC_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcfr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcfr_regs.h new file mode 100644 index 00000000000..41c304907d5 --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcfr_regs.h @@ -0,0 +1,124 @@ +/** + * @file gcfr_regs.h + * @brief Registers, Bit Masks and Bit Positions for the GCFR Peripheral Module. + * @note This file is @generated. + * @ingroup gcfr_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_GCFR_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_GCFR_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup gcfr + * @defgroup gcfr_registers GCFR_Registers + * @brief Registers, Bit Masks and Bit Positions for the GCFR Peripheral Module. + * @details Global Control Function Register. + */ + +/** + * @ingroup gcfr_registers + * Structure type to access the GCFR Registers. + */ +typedef struct { + __IO uint32_t reg0; /**< \b 0x00: GCFR REG0 Register */ + __IO uint32_t reg1; /**< \b 0x04: GCFR REG1 Register */ +} mxc_gcfr_regs_t; + +/* Register offsets for module GCFR */ +/** + * @ingroup gcfr_registers + * @defgroup GCFR_Register_Offsets Register Offsets + * @brief GCFR Peripheral Register Offsets from the GCFR Base Peripheral Address. + * @{ + */ +#define MXC_R_GCFR_REG0 ((uint32_t)0x00000000UL) /**< Offset from GCFR Base Address: 0x0000 */ +#define MXC_R_GCFR_REG1 ((uint32_t)0x00000004UL) /**< Offset from GCFR Base Address: 0x0004 */ +/**@} end of group gcfr_registers */ + +/** + * @ingroup gcfr_registers + * @defgroup GCFR_REG0 GCFR_REG0 + * @brief Register 0. + * @{ + */ +#define MXC_F_GCFR_REG0_ISO_WUP_POS 0 /**< REG0_ISO_WUP Position */ +#define MXC_F_GCFR_REG0_ISO_WUP ((uint32_t)(0x1FFUL << MXC_F_GCFR_REG0_ISO_WUP_POS)) /**< REG0_ISO_WUP Mask */ + +#define MXC_F_GCFR_REG0_IPO_WUP_POS 16 /**< REG0_IPO_WUP Position */ +#define MXC_F_GCFR_REG0_IPO_WUP ((uint32_t)(0x7FFUL << MXC_F_GCFR_REG0_IPO_WUP_POS)) /**< REG0_IPO_WUP Mask */ + +/**@} end of group GCFR_REG0_Register */ + +/** + * @ingroup gcfr_registers + * @defgroup GCFR_REG1 GCFR_REG1 + * @brief Register 1. + * @{ + */ +#define MXC_F_GCFR_REG1_ERFO_WUP_POS 0 /**< REG1_ERFO_WUP Position */ +#define MXC_F_GCFR_REG1_ERFO_WUP ((uint32_t)(0x3FFFUL << MXC_F_GCFR_REG1_ERFO_WUP_POS)) /**< REG1_ERFO_WUP Mask */ + +#define MXC_F_GCFR_REG1_IBRO_WUP_POS 16 /**< REG1_IBRO_WUP Position */ +#define MXC_F_GCFR_REG1_IBRO_WUP ((uint32_t)(0x3FUL << MXC_F_GCFR_REG1_IBRO_WUP_POS)) /**< REG1_IBRO_WUP Mask */ + +/**@} end of group GCFR_REG1_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_GCFR_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h new file mode 100644 index 00000000000..efd1e4aa891 --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h @@ -0,0 +1,1060 @@ +/** + * @file gcr_regs.h + * @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module. + * @note This file is @generated. + * @ingroup gcr_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_GCR_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_GCR_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup gcr + * @defgroup gcr_registers GCR_Registers + * @brief Registers, Bit Masks and Bit Positions for the GCR Peripheral Module. + * @details Global Control Registers. + */ + +/** + * @ingroup gcr_registers + * Structure type to access the GCR Registers. + */ +typedef struct { + __IO uint32_t sysctrl; /**< \b 0x00: GCR SYSCTRL Register */ + __IO uint32_t rst0; /**< \b 0x04: GCR RST0 Register */ + __IO uint32_t clkctrl; /**< \b 0x08: GCR CLKCTRL Register */ + __IO uint32_t pm; /**< \b 0x0C: GCR PM Register */ + __R uint32_t rsv_0x10_0x17[2]; + __IO uint32_t pclkdiv; /**< \b 0x18: GCR PCLKDIV Register */ + __R uint32_t rsv_0x1c_0x23[2]; + __IO uint32_t pclkdis0; /**< \b 0x24: GCR PCLKDIS0 Register */ + __IO uint32_t memctrl; /**< \b 0x28: GCR MEMCTRL Register */ + __IO uint32_t memz; /**< \b 0x2C: GCR MEMZ Register */ + __R uint32_t rsv_0x30_0x3f[4]; + __IO uint32_t sysst; /**< \b 0x40: GCR SYSST Register */ + __IO uint32_t rst1; /**< \b 0x44: GCR RST1 Register */ + __IO uint32_t pclkdis1; /**< \b 0x48: GCR PCLKDIS1 Register */ + __IO uint32_t eventen; /**< \b 0x4C: GCR EVENTEN Register */ + __I uint32_t revision; /**< \b 0x50: GCR REVISION Register */ + __IO uint32_t sysinten; /**< \b 0x54: GCR SYSINTEN Register */ + __IO uint32_t ipocnt; /**< \b 0x58: GCR IPOCNT Register */ + __R uint32_t rsv_0x5c_0x63[2]; + __IO uint32_t eccerr; /**< \b 0x64: GCR ECCERR Register */ + __IO uint32_t eccced; /**< \b 0x68: GCR ECCCED Register */ + __IO uint32_t eccinten; /**< \b 0x6C: GCR ECCINTEN Register */ + __IO uint32_t eccaddr; /**< \b 0x70: GCR ECCADDR Register */ + __IO uint32_t btleldoctrl; /**< \b 0x74: GCR BTLELDOCTRL Register */ + __IO uint32_t btleldodly; /**< \b 0x78: GCR BTLELDODLY Register */ + __R uint32_t rsv_0x7c; + __IO uint32_t flvrst; /**< \b 0x80: GCR FLVRST Register */ + __IO uint32_t flvclkctrl; /**< \b 0x84: GCR FLVCLKCTRL Register */ + __IO uint32_t flvstat; /**< \b 0x88: GCR FLVSTAT Register */ +} mxc_gcr_regs_t; + +/* Register offsets for module GCR */ +/** + * @ingroup gcr_registers + * @defgroup GCR_Register_Offsets Register Offsets + * @brief GCR Peripheral Register Offsets from the GCR Base Peripheral Address. + * @{ + */ +#define MXC_R_GCR_SYSCTRL ((uint32_t)0x00000000UL) /**< Offset from GCR Base Address: 0x0000 */ +#define MXC_R_GCR_RST0 ((uint32_t)0x00000004UL) /**< Offset from GCR Base Address: 0x0004 */ +#define MXC_R_GCR_CLKCTRL ((uint32_t)0x00000008UL) /**< Offset from GCR Base Address: 0x0008 */ +#define MXC_R_GCR_PM ((uint32_t)0x0000000CUL) /**< Offset from GCR Base Address: 0x000C */ +#define MXC_R_GCR_PCLKDIV ((uint32_t)0x00000018UL) /**< Offset from GCR Base Address: 0x0018 */ +#define MXC_R_GCR_PCLKDIS0 ((uint32_t)0x00000024UL) /**< Offset from GCR Base Address: 0x0024 */ +#define MXC_R_GCR_MEMCTRL ((uint32_t)0x00000028UL) /**< Offset from GCR Base Address: 0x0028 */ +#define MXC_R_GCR_MEMZ ((uint32_t)0x0000002CUL) /**< Offset from GCR Base Address: 0x002C */ +#define MXC_R_GCR_SYSST ((uint32_t)0x00000040UL) /**< Offset from GCR Base Address: 0x0040 */ +#define MXC_R_GCR_RST1 ((uint32_t)0x00000044UL) /**< Offset from GCR Base Address: 0x0044 */ +#define MXC_R_GCR_PCLKDIS1 ((uint32_t)0x00000048UL) /**< Offset from GCR Base Address: 0x0048 */ +#define MXC_R_GCR_EVENTEN ((uint32_t)0x0000004CUL) /**< Offset from GCR Base Address: 0x004C */ +#define MXC_R_GCR_REVISION ((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: 0x0050 */ +#define MXC_R_GCR_SYSINTEN ((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: 0x0054 */ +#define MXC_R_GCR_IPOCNT ((uint32_t)0x00000058UL) /**< Offset from GCR Base Address: 0x0058 */ +#define MXC_R_GCR_ECCERR ((uint32_t)0x00000064UL) /**< Offset from GCR Base Address: 0x0064 */ +#define MXC_R_GCR_ECCCED ((uint32_t)0x00000068UL) /**< Offset from GCR Base Address: 0x0068 */ +#define MXC_R_GCR_ECCINTEN ((uint32_t)0x0000006CUL) /**< Offset from GCR Base Address: 0x006C */ +#define MXC_R_GCR_ECCADDR ((uint32_t)0x00000070UL) /**< Offset from GCR Base Address: 0x0070 */ +#define MXC_R_GCR_BTLELDOCTRL ((uint32_t)0x00000074UL) /**< Offset from GCR Base Address: 0x0074 */ +#define MXC_R_GCR_BTLELDODLY ((uint32_t)0x00000078UL) /**< Offset from GCR Base Address: 0x0078 */ +#define MXC_R_GCR_FLVRST ((uint32_t)0x00000080UL) /**< Offset from GCR Base Address: 0x0080 */ +#define MXC_R_GCR_FLVCLKCTRL ((uint32_t)0x00000084UL) /**< Offset from GCR Base Address: 0x0084 */ +#define MXC_R_GCR_FLVSTAT ((uint32_t)0x00000088UL) /**< Offset from GCR Base Address: 0x0088 */ +/**@} end of group gcr_registers */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_SYSCTRL GCR_SYSCTRL + * @brief System Control. + * @{ + */ +#define MXC_F_GCR_SYSCTRL_BSTAP_EN_POS 0 /**< SYSCTRL_BSTAP_EN Position */ +#define MXC_F_GCR_SYSCTRL_BSTAP_EN ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_BSTAP_EN_POS)) /**< SYSCTRL_BSTAP_EN Mask */ + +#define MXC_F_GCR_SYSCTRL_SBUSARB_POS 1 /**< SYSCTRL_SBUSARB Position */ +#define MXC_F_GCR_SYSCTRL_SBUSARB ((uint32_t)(0x3UL << MXC_F_GCR_SYSCTRL_SBUSARB_POS)) /**< SYSCTRL_SBUSARB Mask */ +#define MXC_V_GCR_SYSCTRL_SBUSARB_FIX ((uint32_t)0x0UL) /**< SYSCTRL_SBUSARB_FIX Value */ +#define MXC_S_GCR_SYSCTRL_SBUSARB_FIX (MXC_V_GCR_SYSCTRL_SBUSARB_FIX << MXC_F_GCR_SYSCTRL_SBUSARB_POS) /**< SYSCTRL_SBUSARB_FIX Setting */ +#define MXC_V_GCR_SYSCTRL_SBUSARB_ROUND ((uint32_t)0x1UL) /**< SYSCTRL_SBUSARB_ROUND Value */ +#define MXC_S_GCR_SYSCTRL_SBUSARB_ROUND (MXC_V_GCR_SYSCTRL_SBUSARB_ROUND << MXC_F_GCR_SYSCTRL_SBUSARB_POS) /**< SYSCTRL_SBUSARB_ROUND Setting */ + +#define MXC_F_GCR_SYSCTRL_FLASH_PAGE_FLIP_POS 4 /**< SYSCTRL_FLASH_PAGE_FLIP Position */ +#define MXC_F_GCR_SYSCTRL_FLASH_PAGE_FLIP ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_FLASH_PAGE_FLIP_POS)) /**< SYSCTRL_FLASH_PAGE_FLIP Mask */ + +#define MXC_F_GCR_SYSCTRL_FPU_DIS_POS 5 /**< SYSCTRL_FPU_DIS Position */ +#define MXC_F_GCR_SYSCTRL_FPU_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_FPU_DIS_POS)) /**< SYSCTRL_FPU_DIS Mask */ + +#define MXC_F_GCR_SYSCTRL_ICC_FLUSH_POS 6 /**< SYSCTRL_ICC_FLUSH Position */ +#define MXC_F_GCR_SYSCTRL_ICC_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_ICC_FLUSH_POS)) /**< SYSCTRL_ICC_FLUSH Mask */ + +#define MXC_F_GCR_SYSCTRL_SRCC_FLUSH_POS 7 /**< SYSCTRL_SRCC_FLUSH Position */ +#define MXC_F_GCR_SYSCTRL_SRCC_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_SRCC_FLUSH_POS)) /**< SYSCTRL_SRCC_FLUSH Mask */ + +#define MXC_F_GCR_SYSCTRL_SRCC_DIS_POS 9 /**< SYSCTRL_SRCC_DIS Position */ +#define MXC_F_GCR_SYSCTRL_SRCC_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_SRCC_DIS_POS)) /**< SYSCTRL_SRCC_DIS Mask */ + +#define MXC_F_GCR_SYSCTRL_CHKRES1_POS 11 /**< SYSCTRL_CHKRES1 Position */ +#define MXC_F_GCR_SYSCTRL_CHKRES1 ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CHKRES1_POS)) /**< SYSCTRL_CHKRES1 Mask */ + +#define MXC_F_GCR_SYSCTRL_CCHK1_POS 12 /**< SYSCTRL_CCHK1 Position */ +#define MXC_F_GCR_SYSCTRL_CCHK1 ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CCHK1_POS)) /**< SYSCTRL_CCHK1 Mask */ + +#define MXC_F_GCR_SYSCTRL_CCHK0_POS 13 /**< SYSCTRL_CCHK0 Position */ +#define MXC_F_GCR_SYSCTRL_CCHK0 ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CCHK0_POS)) /**< SYSCTRL_CCHK0 Mask */ + +#define MXC_F_GCR_SYSCTRL_CHKRES0_POS 15 /**< SYSCTRL_CHKRES0 Position */ +#define MXC_F_GCR_SYSCTRL_CHKRES0 ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CHKRES0_POS)) /**< SYSCTRL_CHKRES0 Mask */ + +#define MXC_F_GCR_SYSCTRL_OVR_POS 16 /**< SYSCTRL_OVR Position */ +#define MXC_F_GCR_SYSCTRL_OVR ((uint32_t)(0x3UL << MXC_F_GCR_SYSCTRL_OVR_POS)) /**< SYSCTRL_OVR Mask */ + +/**@} end of group GCR_SYSCTRL_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_RST0 GCR_RST0 + * @brief Reset. + * @{ + */ +#define MXC_F_GCR_RST0_DMA_POS 0 /**< RST0_DMA Position */ +#define MXC_F_GCR_RST0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_RST0_DMA_POS)) /**< RST0_DMA Mask */ + +#define MXC_F_GCR_RST0_WDT0_POS 1 /**< RST0_WDT0 Position */ +#define MXC_F_GCR_RST0_WDT0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_WDT0_POS)) /**< RST0_WDT0 Mask */ + +#define MXC_F_GCR_RST0_GPIO0_POS 2 /**< RST0_GPIO0 Position */ +#define MXC_F_GCR_RST0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO0_POS)) /**< RST0_GPIO0 Mask */ + +#define MXC_F_GCR_RST0_GPIO1_POS 3 /**< RST0_GPIO1 Position */ +#define MXC_F_GCR_RST0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO1_POS)) /**< RST0_GPIO1 Mask */ + +#define MXC_F_GCR_RST0_TMR0_POS 5 /**< RST0_TMR0 Position */ +#define MXC_F_GCR_RST0_TMR0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR0_POS)) /**< RST0_TMR0 Mask */ + +#define MXC_F_GCR_RST0_TMR1_POS 6 /**< RST0_TMR1 Position */ +#define MXC_F_GCR_RST0_TMR1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR1_POS)) /**< RST0_TMR1 Mask */ + +#define MXC_F_GCR_RST0_TMR2_POS 7 /**< RST0_TMR2 Position */ +#define MXC_F_GCR_RST0_TMR2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR2_POS)) /**< RST0_TMR2 Mask */ + +#define MXC_F_GCR_RST0_TMR3_POS 8 /**< RST0_TMR3 Position */ +#define MXC_F_GCR_RST0_TMR3 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR3_POS)) /**< RST0_TMR3 Mask */ + +#define MXC_F_GCR_RST0_TMR4_POS 9 /**< RST0_TMR4 Position */ +#define MXC_F_GCR_RST0_TMR4 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR4_POS)) /**< RST0_TMR4 Mask */ + +#define MXC_F_GCR_RST0_TMR5_POS 10 /**< RST0_TMR5 Position */ +#define MXC_F_GCR_RST0_TMR5 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR5_POS)) /**< RST0_TMR5 Mask */ + +#define MXC_F_GCR_RST0_UART0_POS 11 /**< RST0_UART0 Position */ +#define MXC_F_GCR_RST0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART0_POS)) /**< RST0_UART0 Mask */ + +#define MXC_F_GCR_RST0_UART1_POS 12 /**< RST0_UART1 Position */ +#define MXC_F_GCR_RST0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART1_POS)) /**< RST0_UART1 Mask */ + +#define MXC_F_GCR_RST0_SPI0_POS 13 /**< RST0_SPI0 Position */ +#define MXC_F_GCR_RST0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI0_POS)) /**< RST0_SPI0 Mask */ + +#define MXC_F_GCR_RST0_SPI1_POS 14 /**< RST0_SPI1 Position */ +#define MXC_F_GCR_RST0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI1_POS)) /**< RST0_SPI1 Mask */ + +#define MXC_F_GCR_RST0_SPI2_POS 15 /**< RST0_SPI2 Position */ +#define MXC_F_GCR_RST0_SPI2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI2_POS)) /**< RST0_SPI2 Mask */ + +#define MXC_F_GCR_RST0_I2C0_POS 16 /**< RST0_I2C0 Position */ +#define MXC_F_GCR_RST0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_I2C0_POS)) /**< RST0_I2C0 Mask */ + +#define MXC_F_GCR_RST0_RTC_POS 17 /**< RST0_RTC Position */ +#define MXC_F_GCR_RST0_RTC ((uint32_t)(0x1UL << MXC_F_GCR_RST0_RTC_POS)) /**< RST0_RTC Mask */ + +#define MXC_F_GCR_RST0_TMR6_POS 20 /**< RST0_TMR6 Position */ +#define MXC_F_GCR_RST0_TMR6 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR6_POS)) /**< RST0_TMR6 Mask */ + +#define MXC_F_GCR_RST0_TMR7_POS 21 /**< RST0_TMR7 Position */ +#define MXC_F_GCR_RST0_TMR7 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR7_POS)) /**< RST0_TMR7 Mask */ + +#define MXC_F_GCR_RST0_SEMA_POS 22 /**< RST0_SEMA Position */ +#define MXC_F_GCR_RST0_SEMA ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SEMA_POS)) /**< RST0_SEMA Mask */ + +#define MXC_F_GCR_RST0_TRNG_POS 24 /**< RST0_TRNG Position */ +#define MXC_F_GCR_RST0_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TRNG_POS)) /**< RST0_TRNG Mask */ + +#define MXC_F_GCR_RST0_ADC_POS 26 /**< RST0_ADC Position */ +#define MXC_F_GCR_RST0_ADC ((uint32_t)(0x1UL << MXC_F_GCR_RST0_ADC_POS)) /**< RST0_ADC Mask */ + +#define MXC_F_GCR_RST0_UART2_POS 28 /**< RST0_UART2 Position */ +#define MXC_F_GCR_RST0_UART2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART2_POS)) /**< RST0_UART2 Mask */ + +#define MXC_F_GCR_RST0_SOFT_POS 29 /**< RST0_SOFT Position */ +#define MXC_F_GCR_RST0_SOFT ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SOFT_POS)) /**< RST0_SOFT Mask */ + +#define MXC_F_GCR_RST0_PERIPH_POS 30 /**< RST0_PERIPH Position */ +#define MXC_F_GCR_RST0_PERIPH ((uint32_t)(0x1UL << MXC_F_GCR_RST0_PERIPH_POS)) /**< RST0_PERIPH Mask */ + +#define MXC_F_GCR_RST0_SYS_POS 31 /**< RST0_SYS Position */ +#define MXC_F_GCR_RST0_SYS ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SYS_POS)) /**< RST0_SYS Mask */ + +/**@} end of group GCR_RST0_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_CLKCTRL GCR_CLKCTRL + * @brief Clock Control. + * @{ + */ +#define MXC_F_GCR_CLKCTRL_PCLK_DIV_POS 3 /**< CLKCTRL_PCLK_DIV Position */ +#define MXC_F_GCR_CLKCTRL_PCLK_DIV ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_PCLK_DIV_POS)) /**< CLKCTRL_PCLK_DIV Mask */ +#define MXC_V_GCR_CLKCTRL_PCLK_DIV_DIV1 ((uint32_t)0x0UL) /**< CLKCTRL_PCLK_DIV_DIV1 Value */ +#define MXC_S_GCR_CLKCTRL_PCLK_DIV_DIV1 (MXC_V_GCR_CLKCTRL_PCLK_DIV_DIV1 << MXC_F_GCR_CLKCTRL_PCLK_DIV_POS) /**< CLKCTRL_PCLK_DIV_DIV1 Setting */ +#define MXC_V_GCR_CLKCTRL_PCLK_DIV_DIV2 ((uint32_t)0x1UL) /**< CLKCTRL_PCLK_DIV_DIV2 Value */ +#define MXC_S_GCR_CLKCTRL_PCLK_DIV_DIV2 (MXC_V_GCR_CLKCTRL_PCLK_DIV_DIV2 << MXC_F_GCR_CLKCTRL_PCLK_DIV_POS) /**< CLKCTRL_PCLK_DIV_DIV2 Setting */ +#define MXC_V_GCR_CLKCTRL_PCLK_DIV_DIV4 ((uint32_t)0x2UL) /**< CLKCTRL_PCLK_DIV_DIV4 Value */ +#define MXC_S_GCR_CLKCTRL_PCLK_DIV_DIV4 (MXC_V_GCR_CLKCTRL_PCLK_DIV_DIV4 << MXC_F_GCR_CLKCTRL_PCLK_DIV_POS) /**< CLKCTRL_PCLK_DIV_DIV4 Setting */ +#define MXC_V_GCR_CLKCTRL_PCLK_DIV_DIV8 ((uint32_t)0x3UL) /**< CLKCTRL_PCLK_DIV_DIV8 Value */ +#define MXC_S_GCR_CLKCTRL_PCLK_DIV_DIV8 (MXC_V_GCR_CLKCTRL_PCLK_DIV_DIV8 << MXC_F_GCR_CLKCTRL_PCLK_DIV_POS) /**< CLKCTRL_PCLK_DIV_DIV8 Setting */ + +#define MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS 6 /**< CLKCTRL_SYSCLK_DIV Position */ +#define MXC_F_GCR_CLKCTRL_SYSCLK_DIV ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS)) /**< CLKCTRL_SYSCLK_DIV Mask */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV1 ((uint32_t)0x0UL) /**< CLKCTRL_SYSCLK_DIV_DIV1 Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV1 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV1 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV1 Setting */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV2 ((uint32_t)0x1UL) /**< CLKCTRL_SYSCLK_DIV_DIV2 Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV2 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV2 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV2 Setting */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV4 ((uint32_t)0x2UL) /**< CLKCTRL_SYSCLK_DIV_DIV4 Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV4 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV4 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV4 Setting */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV8 ((uint32_t)0x3UL) /**< CLKCTRL_SYSCLK_DIV_DIV8 Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV8 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV8 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV8 Setting */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV16 ((uint32_t)0x4UL) /**< CLKCTRL_SYSCLK_DIV_DIV16 Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV16 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV16 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV16 Setting */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV32 ((uint32_t)0x5UL) /**< CLKCTRL_SYSCLK_DIV_DIV32 Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV32 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV32 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV32 Setting */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV64 ((uint32_t)0x6UL) /**< CLKCTRL_SYSCLK_DIV_DIV64 Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV64 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV64 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV64 Setting */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV128 ((uint32_t)0x7UL) /**< CLKCTRL_SYSCLK_DIV_DIV128 Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_DIV_DIV128 (MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV128 << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS) /**< CLKCTRL_SYSCLK_DIV_DIV128 Setting */ + +#define MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS 9 /**< CLKCTRL_SYSCLK_SEL Position */ +#define MXC_F_GCR_CLKCTRL_SYSCLK_SEL ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS)) /**< CLKCTRL_SYSCLK_SEL Mask */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ISO ((uint32_t)0x0UL) /**< CLKCTRL_SYSCLK_SEL_ISO Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ISO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ISO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_ISO Setting */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO ((uint32_t)0x2UL) /**< CLKCTRL_SYSCLK_SEL_ERFO Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERFO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_ERFO Setting */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO ((uint32_t)0x3UL) /**< CLKCTRL_SYSCLK_SEL_INRO Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_INRO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_INRO Setting */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO ((uint32_t)0x4UL) /**< CLKCTRL_SYSCLK_SEL_IPO Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_IPO Setting */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO ((uint32_t)0x5UL) /**< CLKCTRL_SYSCLK_SEL_IBRO Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IBRO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_IBRO Setting */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO ((uint32_t)0x6UL) /**< CLKCTRL_SYSCLK_SEL_ERTCO Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_ERTCO Setting */ + +#define MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS 13 /**< CLKCTRL_SYSCLK_RDY Position */ +#define MXC_F_GCR_CLKCTRL_SYSCLK_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS)) /**< CLKCTRL_SYSCLK_RDY Mask */ + +#define MXC_F_GCR_CLKCTRL_IPO_DIV_POS 14 /**< CLKCTRL_IPO_DIV Position */ +#define MXC_F_GCR_CLKCTRL_IPO_DIV ((uint32_t)(0x3UL << MXC_F_GCR_CLKCTRL_IPO_DIV_POS)) /**< CLKCTRL_IPO_DIV Mask */ +#define MXC_V_GCR_CLKCTRL_IPO_DIV_DIV1 ((uint32_t)0x0UL) /**< CLKCTRL_IPO_DIV_DIV1 Value */ +#define MXC_S_GCR_CLKCTRL_IPO_DIV_DIV1 (MXC_V_GCR_CLKCTRL_IPO_DIV_DIV1 << MXC_F_GCR_CLKCTRL_IPO_DIV_POS) /**< CLKCTRL_IPO_DIV_DIV1 Setting */ +#define MXC_V_GCR_CLKCTRL_IPO_DIV_DIV2 ((uint32_t)0x1UL) /**< CLKCTRL_IPO_DIV_DIV2 Value */ +#define MXC_S_GCR_CLKCTRL_IPO_DIV_DIV2 (MXC_V_GCR_CLKCTRL_IPO_DIV_DIV2 << MXC_F_GCR_CLKCTRL_IPO_DIV_POS) /**< CLKCTRL_IPO_DIV_DIV2 Setting */ +#define MXC_V_GCR_CLKCTRL_IPO_DIV_DIV4 ((uint32_t)0x2UL) /**< CLKCTRL_IPO_DIV_DIV4 Value */ +#define MXC_S_GCR_CLKCTRL_IPO_DIV_DIV4 (MXC_V_GCR_CLKCTRL_IPO_DIV_DIV4 << MXC_F_GCR_CLKCTRL_IPO_DIV_POS) /**< CLKCTRL_IPO_DIV_DIV4 Setting */ +#define MXC_V_GCR_CLKCTRL_IPO_DIV_DIV8 ((uint32_t)0x3UL) /**< CLKCTRL_IPO_DIV_DIV8 Value */ +#define MXC_S_GCR_CLKCTRL_IPO_DIV_DIV8 (MXC_V_GCR_CLKCTRL_IPO_DIV_DIV8 << MXC_F_GCR_CLKCTRL_IPO_DIV_POS) /**< CLKCTRL_IPO_DIV_DIV8 Setting */ + +#define MXC_F_GCR_CLKCTRL_ERFO_EN_POS 16 /**< CLKCTRL_ERFO_EN Position */ +#define MXC_F_GCR_CLKCTRL_ERFO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERFO_EN_POS)) /**< CLKCTRL_ERFO_EN Mask */ + +#define MXC_F_GCR_CLKCTRL_ERTCO_EN_POS 17 /**< CLKCTRL_ERTCO_EN Position */ +#define MXC_F_GCR_CLKCTRL_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERTCO_EN_POS)) /**< CLKCTRL_ERTCO_EN Mask */ + +#define MXC_F_GCR_CLKCTRL_ISO_EN_POS 18 /**< CLKCTRL_ISO_EN Position */ +#define MXC_F_GCR_CLKCTRL_ISO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ISO_EN_POS)) /**< CLKCTRL_ISO_EN Mask */ + +#define MXC_F_GCR_CLKCTRL_IPO_EN_POS 19 /**< CLKCTRL_IPO_EN Position */ +#define MXC_F_GCR_CLKCTRL_IPO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_EN_POS)) /**< CLKCTRL_IPO_EN Mask */ + +#define MXC_F_GCR_CLKCTRL_IBRO_EN_POS 20 /**< CLKCTRL_IBRO_EN Position */ +#define MXC_F_GCR_CLKCTRL_IBRO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_EN_POS)) /**< CLKCTRL_IBRO_EN Mask */ + +#define MXC_F_GCR_CLKCTRL_IBRO_VS_POS 21 /**< CLKCTRL_IBRO_VS Position */ +#define MXC_F_GCR_CLKCTRL_IBRO_VS ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_VS_POS)) /**< CLKCTRL_IBRO_VS Mask */ + +#define MXC_F_GCR_CLKCTRL_ERFO_RDY_POS 24 /**< CLKCTRL_ERFO_RDY Position */ +#define MXC_F_GCR_CLKCTRL_ERFO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERFO_RDY_POS)) /**< CLKCTRL_ERFO_RDY Mask */ + +#define MXC_F_GCR_CLKCTRL_ERTCO_RDY_POS 25 /**< CLKCTRL_ERTCO_RDY Position */ +#define MXC_F_GCR_CLKCTRL_ERTCO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERTCO_RDY_POS)) /**< CLKCTRL_ERTCO_RDY Mask */ + +#define MXC_F_GCR_CLKCTRL_ISO_RDY_POS 26 /**< CLKCTRL_ISO_RDY Position */ +#define MXC_F_GCR_CLKCTRL_ISO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ISO_RDY_POS)) /**< CLKCTRL_ISO_RDY Mask */ + +#define MXC_F_GCR_CLKCTRL_IPO_RDY_POS 27 /**< CLKCTRL_IPO_RDY Position */ +#define MXC_F_GCR_CLKCTRL_IPO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_RDY_POS)) /**< CLKCTRL_IPO_RDY Mask */ + +#define MXC_F_GCR_CLKCTRL_IBRO_RDY_POS 28 /**< CLKCTRL_IBRO_RDY Position */ +#define MXC_F_GCR_CLKCTRL_IBRO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IBRO_RDY_POS)) /**< CLKCTRL_IBRO_RDY Mask */ + +#define MXC_F_GCR_CLKCTRL_INRO_RDY_POS 29 /**< CLKCTRL_INRO_RDY Position */ +#define MXC_F_GCR_CLKCTRL_INRO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_INRO_RDY_POS)) /**< CLKCTRL_INRO_RDY Mask */ + +/**@} end of group GCR_CLKCTRL_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_PM GCR_PM + * @brief Power Management. + * @{ + */ +#define MXC_F_GCR_PM_MODE_POS 0 /**< PM_MODE Position */ +#define MXC_F_GCR_PM_MODE ((uint32_t)(0x7UL << MXC_F_GCR_PM_MODE_POS)) /**< PM_MODE Mask */ +#define MXC_V_GCR_PM_MODE_ACTIVE ((uint32_t)0x0UL) /**< PM_MODE_ACTIVE Value */ +#define MXC_S_GCR_PM_MODE_ACTIVE (MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_ACTIVE Setting */ +#define MXC_V_GCR_PM_MODE_DEEPSLEEP ((uint32_t)0x2UL) /**< PM_MODE_DEEPSLEEP Value */ +#define MXC_S_GCR_PM_MODE_DEEPSLEEP (MXC_V_GCR_PM_MODE_DEEPSLEEP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_DEEPSLEEP Setting */ +#define MXC_V_GCR_PM_MODE_SHUTDOWN ((uint32_t)0x3UL) /**< PM_MODE_SHUTDOWN Value */ +#define MXC_S_GCR_PM_MODE_SHUTDOWN (MXC_V_GCR_PM_MODE_SHUTDOWN << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_SHUTDOWN Setting */ +#define MXC_V_GCR_PM_MODE_BACKUP ((uint32_t)0x4UL) /**< PM_MODE_BACKUP Value */ +#define MXC_S_GCR_PM_MODE_BACKUP (MXC_V_GCR_PM_MODE_BACKUP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_BACKUP Setting */ + +#define MXC_F_GCR_PM_GPIO_WE_POS 4 /**< PM_GPIO_WE Position */ +#define MXC_F_GCR_PM_GPIO_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_GPIO_WE_POS)) /**< PM_GPIO_WE Mask */ + +#define MXC_F_GCR_PM_RTC_WE_POS 5 /**< PM_RTC_WE Position */ +#define MXC_F_GCR_PM_RTC_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_RTC_WE_POS)) /**< PM_RTC_WE Mask */ + +#define MXC_F_GCR_PM_USB_WE_POS 6 /**< PM_USB_WE Position */ +#define MXC_F_GCR_PM_USB_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_USB_WE_POS)) /**< PM_USB_WE Mask */ + +#define MXC_F_GCR_PM_ERFO_PD_POS 12 /**< PM_ERFO_PD Position */ +#define MXC_F_GCR_PM_ERFO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_ERFO_PD_POS)) /**< PM_ERFO_PD Mask */ + +#define MXC_F_GCR_PM_ISO_PD_POS 15 /**< PM_ISO_PD Position */ +#define MXC_F_GCR_PM_ISO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_ISO_PD_POS)) /**< PM_ISO_PD Mask */ + +#define MXC_F_GCR_PM_IPO_PD_POS 16 /**< PM_IPO_PD Position */ +#define MXC_F_GCR_PM_IPO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_IPO_PD_POS)) /**< PM_IPO_PD Mask */ + +#define MXC_F_GCR_PM_IBRO_PD_POS 17 /**< PM_IBRO_PD Position */ +#define MXC_F_GCR_PM_IBRO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_IBRO_PD_POS)) /**< PM_IBRO_PD Mask */ + +#define MXC_F_GCR_PM_ERFO_BP_POS 20 /**< PM_ERFO_BP Position */ +#define MXC_F_GCR_PM_ERFO_BP ((uint32_t)(0x1UL << MXC_F_GCR_PM_ERFO_BP_POS)) /**< PM_ERFO_BP Mask */ + +/**@} end of group GCR_PM_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_PCLKDIV GCR_PCLKDIV + * @brief Peripheral Clock Divider. + * @{ + */ +#define MXC_F_GCR_PCLKDIV_ADCFRQ_POS 10 /**< PCLKDIV_ADCFRQ Position */ +#define MXC_F_GCR_PCLKDIV_ADCFRQ ((uint32_t)(0xFUL << MXC_F_GCR_PCLKDIV_ADCFRQ_POS)) /**< PCLKDIV_ADCFRQ Mask */ + +#define MXC_F_GCR_PCLKDIV_AONCLKDIV_POS 14 /**< PCLKDIV_AONCLKDIV Position */ +#define MXC_F_GCR_PCLKDIV_AONCLKDIV ((uint32_t)(0x3UL << MXC_F_GCR_PCLKDIV_AONCLKDIV_POS)) /**< PCLKDIV_AONCLKDIV Mask */ +#define MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV4 ((uint32_t)0x0UL) /**< PCLKDIV_AONCLKDIV_DIV4 Value */ +#define MXC_S_GCR_PCLKDIV_AONCLKDIV_DIV4 (MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV4 << MXC_F_GCR_PCLKDIV_AONCLKDIV_POS) /**< PCLKDIV_AONCLKDIV_DIV4 Setting */ +#define MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV8 ((uint32_t)0x1UL) /**< PCLKDIV_AONCLKDIV_DIV8 Value */ +#define MXC_S_GCR_PCLKDIV_AONCLKDIV_DIV8 (MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV8 << MXC_F_GCR_PCLKDIV_AONCLKDIV_POS) /**< PCLKDIV_AONCLKDIV_DIV8 Setting */ +#define MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV16 ((uint32_t)0x2UL) /**< PCLKDIV_AONCLKDIV_DIV16 Value */ +#define MXC_S_GCR_PCLKDIV_AONCLKDIV_DIV16 (MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV16 << MXC_F_GCR_PCLKDIV_AONCLKDIV_POS) /**< PCLKDIV_AONCLKDIV_DIV16 Setting */ +#define MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV32 ((uint32_t)0x3UL) /**< PCLKDIV_AONCLKDIV_DIV32 Value */ +#define MXC_S_GCR_PCLKDIV_AONCLKDIV_DIV32 (MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV32 << MXC_F_GCR_PCLKDIV_AONCLKDIV_POS) /**< PCLKDIV_AONCLKDIV_DIV32 Setting */ + +/**@} end of group GCR_PCLKDIV_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_PCLKDIS0 GCR_PCLKDIS0 + * @brief Peripheral Clock Disable. + * @{ + */ +#define MXC_F_GCR_PCLKDIS0_GPIO0_POS 0 /**< PCLKDIS0_GPIO0 Position */ +#define MXC_F_GCR_PCLKDIS0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_GPIO0_POS)) /**< PCLKDIS0_GPIO0 Mask */ + +#define MXC_F_GCR_PCLKDIS0_GPIO1_POS 1 /**< PCLKDIS0_GPIO1 Position */ +#define MXC_F_GCR_PCLKDIS0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_GPIO1_POS)) /**< PCLKDIS0_GPIO1 Mask */ + +#define MXC_F_GCR_PCLKDIS0_DMA_POS 5 /**< PCLKDIS0_DMA Position */ +#define MXC_F_GCR_PCLKDIS0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_DMA_POS)) /**< PCLKDIS0_DMA Mask */ + +#define MXC_F_GCR_PCLKDIS0_SPI0_POS 6 /**< PCLKDIS0_SPI0 Position */ +#define MXC_F_GCR_PCLKDIS0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI0_POS)) /**< PCLKDIS0_SPI0 Mask */ + +#define MXC_F_GCR_PCLKDIS0_SPI1_POS 7 /**< PCLKDIS0_SPI1 Position */ +#define MXC_F_GCR_PCLKDIS0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI1_POS)) /**< PCLKDIS0_SPI1 Mask */ + +#define MXC_F_GCR_PCLKDIS0_SPI2_POS 8 /**< PCLKDIS0_SPI2 Position */ +#define MXC_F_GCR_PCLKDIS0_SPI2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI2_POS)) /**< PCLKDIS0_SPI2 Mask */ + +#define MXC_F_GCR_PCLKDIS0_UART0_POS 9 /**< PCLKDIS0_UART0 Position */ +#define MXC_F_GCR_PCLKDIS0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_UART0_POS)) /**< PCLKDIS0_UART0 Mask */ + +#define MXC_F_GCR_PCLKDIS0_UART1_POS 10 /**< PCLKDIS0_UART1 Position */ +#define MXC_F_GCR_PCLKDIS0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_UART1_POS)) /**< PCLKDIS0_UART1 Mask */ + +#define MXC_F_GCR_PCLKDIS0_I2C0_POS 13 /**< PCLKDIS0_I2C0 Position */ +#define MXC_F_GCR_PCLKDIS0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_I2C0_POS)) /**< PCLKDIS0_I2C0 Mask */ + +#define MXC_F_GCR_PCLKDIS0_TMR0_POS 15 /**< PCLKDIS0_TMR0 Position */ +#define MXC_F_GCR_PCLKDIS0_TMR0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR0_POS)) /**< PCLKDIS0_TMR0 Mask */ + +#define MXC_F_GCR_PCLKDIS0_TMR1_POS 16 /**< PCLKDIS0_TMR1 Position */ +#define MXC_F_GCR_PCLKDIS0_TMR1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR1_POS)) /**< PCLKDIS0_TMR1 Mask */ + +#define MXC_F_GCR_PCLKDIS0_TMR2_POS 17 /**< PCLKDIS0_TMR2 Position */ +#define MXC_F_GCR_PCLKDIS0_TMR2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR2_POS)) /**< PCLKDIS0_TMR2 Mask */ + +#define MXC_F_GCR_PCLKDIS0_TMR3_POS 18 /**< PCLKDIS0_TMR3 Position */ +#define MXC_F_GCR_PCLKDIS0_TMR3 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR3_POS)) /**< PCLKDIS0_TMR3 Mask */ + +#define MXC_F_GCR_PCLKDIS0_TMR4_POS 19 /**< PCLKDIS0_TMR4 Position */ +#define MXC_F_GCR_PCLKDIS0_TMR4 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR4_POS)) /**< PCLKDIS0_TMR4 Mask */ + +#define MXC_F_GCR_PCLKDIS0_TMR5_POS 20 /**< PCLKDIS0_TMR5 Position */ +#define MXC_F_GCR_PCLKDIS0_TMR5 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR5_POS)) /**< PCLKDIS0_TMR5 Mask */ + +#define MXC_F_GCR_PCLKDIS0_ADC_POS 23 /**< PCLKDIS0_ADC Position */ +#define MXC_F_GCR_PCLKDIS0_ADC ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_ADC_POS)) /**< PCLKDIS0_ADC Mask */ + +#define MXC_F_GCR_PCLKDIS0_TMR6_POS 24 /**< PCLKDIS0_TMR6 Position */ +#define MXC_F_GCR_PCLKDIS0_TMR6 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR6_POS)) /**< PCLKDIS0_TMR6 Mask */ + +#define MXC_F_GCR_PCLKDIS0_TMR7_POS 25 /**< PCLKDIS0_TMR7 Position */ +#define MXC_F_GCR_PCLKDIS0_TMR7 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR7_POS)) /**< PCLKDIS0_TMR7 Mask */ + +#define MXC_F_GCR_PCLKDIS0_I2C1_POS 28 /**< PCLKDIS0_I2C1 Position */ +#define MXC_F_GCR_PCLKDIS0_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_I2C1_POS)) /**< PCLKDIS0_I2C1 Mask */ + +#define MXC_F_GCR_PCLKDIS0_PT_POS 29 /**< PCLKDIS0_PT Position */ +#define MXC_F_GCR_PCLKDIS0_PT ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_PT_POS)) /**< PCLKDIS0_PT Mask */ + +/**@} end of group GCR_PCLKDIS0_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_MEMCTRL GCR_MEMCTRL + * @brief Memory Clock Control Register. + * @{ + */ +#define MXC_F_GCR_MEMCTRL_FWS_POS 0 /**< MEMCTRL_FWS Position */ +#define MXC_F_GCR_MEMCTRL_FWS ((uint32_t)(0x7UL << MXC_F_GCR_MEMCTRL_FWS_POS)) /**< MEMCTRL_FWS Mask */ + +#define MXC_F_GCR_MEMCTRL_SRAM_WS_POS 4 /**< MEMCTRL_SRAM_WS Position */ +#define MXC_F_GCR_MEMCTRL_SRAM_WS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_SRAM_WS_POS)) /**< MEMCTRL_SRAM_WS Mask */ + +#define MXC_F_GCR_MEMCTRL_ROM1_WS_POS 7 /**< MEMCTRL_ROM1_WS Position */ +#define MXC_F_GCR_MEMCTRL_ROM1_WS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_ROM1_WS_POS)) /**< MEMCTRL_ROM1_WS Mask */ + +#define MXC_F_GCR_MEMCTRL_RAM0_WS_POS 8 /**< MEMCTRL_RAM0_WS Position */ +#define MXC_F_GCR_MEMCTRL_RAM0_WS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM0_WS_POS)) /**< MEMCTRL_RAM0_WS Mask */ + +#define MXC_F_GCR_MEMCTRL_RAM1_WS_POS 9 /**< MEMCTRL_RAM1_WS Position */ +#define MXC_F_GCR_MEMCTRL_RAM1_WS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM1_WS_POS)) /**< MEMCTRL_RAM1_WS Mask */ + +#define MXC_F_GCR_MEMCTRL_RAM2_WS_POS 10 /**< MEMCTRL_RAM2_WS Position */ +#define MXC_F_GCR_MEMCTRL_RAM2_WS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM2_WS_POS)) /**< MEMCTRL_RAM2_WS Mask */ + +#define MXC_F_GCR_MEMCTRL_RAM3_WS_POS 11 /**< MEMCTRL_RAM3_WS Position */ +#define MXC_F_GCR_MEMCTRL_RAM3_WS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM3_WS_POS)) /**< MEMCTRL_RAM3_WS Mask */ + +#define MXC_F_GCR_MEMCTRL_RAM4_WS_POS 12 /**< MEMCTRL_RAM4_WS Position */ +#define MXC_F_GCR_MEMCTRL_RAM4_WS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM4_WS_POS)) /**< MEMCTRL_RAM4_WS Mask */ + +#define MXC_F_GCR_MEMCTRL_RAM5_WS_POS 13 /**< MEMCTRL_RAM5_WS Position */ +#define MXC_F_GCR_MEMCTRL_RAM5_WS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM5_WS_POS)) /**< MEMCTRL_RAM5_WS Mask */ + +#define MXC_F_GCR_MEMCTRL_RAM0LS_EN_POS 16 /**< MEMCTRL_RAM0LS_EN Position */ +#define MXC_F_GCR_MEMCTRL_RAM0LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM0LS_EN_POS)) /**< MEMCTRL_RAM0LS_EN Mask */ + +#define MXC_F_GCR_MEMCTRL_RAM1LS_EN_POS 17 /**< MEMCTRL_RAM1LS_EN Position */ +#define MXC_F_GCR_MEMCTRL_RAM1LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM1LS_EN_POS)) /**< MEMCTRL_RAM1LS_EN Mask */ + +#define MXC_F_GCR_MEMCTRL_RAM2LS_EN_POS 18 /**< MEMCTRL_RAM2LS_EN Position */ +#define MXC_F_GCR_MEMCTRL_RAM2LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM2LS_EN_POS)) /**< MEMCTRL_RAM2LS_EN Mask */ + +#define MXC_F_GCR_MEMCTRL_RAM3LS_EN_POS 19 /**< MEMCTRL_RAM3LS_EN Position */ +#define MXC_F_GCR_MEMCTRL_RAM3LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM3LS_EN_POS)) /**< MEMCTRL_RAM3LS_EN Mask */ + +#define MXC_F_GCR_MEMCTRL_RAM4LS_EN_POS 20 /**< MEMCTRL_RAM4LS_EN Position */ +#define MXC_F_GCR_MEMCTRL_RAM4LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM4LS_EN_POS)) /**< MEMCTRL_RAM4LS_EN Mask */ + +#define MXC_F_GCR_MEMCTRL_RAM5LS_EN_POS 21 /**< MEMCTRL_RAM5LS_EN Position */ +#define MXC_F_GCR_MEMCTRL_RAM5LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM5LS_EN_POS)) /**< MEMCTRL_RAM5LS_EN Mask */ + +#define MXC_F_GCR_MEMCTRL_ICCLS_EN_POS 24 /**< MEMCTRL_ICCLS_EN Position */ +#define MXC_F_GCR_MEMCTRL_ICCLS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_ICCLS_EN_POS)) /**< MEMCTRL_ICCLS_EN Mask */ + +#define MXC_F_GCR_MEMCTRL_ICCXIPLS_EN_POS 25 /**< MEMCTRL_ICCXIPLS_EN Position */ +#define MXC_F_GCR_MEMCTRL_ICCXIPLS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_ICCXIPLS_EN_POS)) /**< MEMCTRL_ICCXIPLS_EN Mask */ + +#define MXC_F_GCR_MEMCTRL_SRCCLS_EN_POS 26 /**< MEMCTRL_SRCCLS_EN Position */ +#define MXC_F_GCR_MEMCTRL_SRCCLS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_SRCCLS_EN_POS)) /**< MEMCTRL_SRCCLS_EN Mask */ + +#define MXC_F_GCR_MEMCTRL_USBLS_EN_POS 28 /**< MEMCTRL_USBLS_EN Position */ +#define MXC_F_GCR_MEMCTRL_USBLS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_USBLS_EN_POS)) /**< MEMCTRL_USBLS_EN Mask */ + +#define MXC_F_GCR_MEMCTRL_ROM0LS_EN_POS 29 /**< MEMCTRL_ROM0LS_EN Position */ +#define MXC_F_GCR_MEMCTRL_ROM0LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_ROM0LS_EN_POS)) /**< MEMCTRL_ROM0LS_EN Mask */ + +#define MXC_F_GCR_MEMCTRL_ROM1LS_EN_POS 30 /**< MEMCTRL_ROM1LS_EN Position */ +#define MXC_F_GCR_MEMCTRL_ROM1LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_ROM1LS_EN_POS)) /**< MEMCTRL_ROM1LS_EN Mask */ + +/**@} end of group GCR_MEMCTRL_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_MEMZ GCR_MEMZ + * @brief Memory Zeroize Control. + * @{ + */ +#define MXC_F_GCR_MEMZ_RAM0_POS 0 /**< MEMZ_RAM0 Position */ +#define MXC_F_GCR_MEMZ_RAM0 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM0_POS)) /**< MEMZ_RAM0 Mask */ + +#define MXC_F_GCR_MEMZ_RAM1_POS 1 /**< MEMZ_RAM1 Position */ +#define MXC_F_GCR_MEMZ_RAM1 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM1_POS)) /**< MEMZ_RAM1 Mask */ + +#define MXC_F_GCR_MEMZ_RAM2_POS 2 /**< MEMZ_RAM2 Position */ +#define MXC_F_GCR_MEMZ_RAM2 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM2_POS)) /**< MEMZ_RAM2 Mask */ + +#define MXC_F_GCR_MEMZ_RAM3_POS 3 /**< MEMZ_RAM3 Position */ +#define MXC_F_GCR_MEMZ_RAM3 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM3_POS)) /**< MEMZ_RAM3 Mask */ + +#define MXC_F_GCR_MEMZ_RAM4_POS 4 /**< MEMZ_RAM4 Position */ +#define MXC_F_GCR_MEMZ_RAM4 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM4_POS)) /**< MEMZ_RAM4 Mask */ + +#define MXC_F_GCR_MEMZ_RAM5_POS 5 /**< MEMZ_RAM5 Position */ +#define MXC_F_GCR_MEMZ_RAM5 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM5_POS)) /**< MEMZ_RAM5 Mask */ + +#define MXC_F_GCR_MEMZ_RAM6_POS 6 /**< MEMZ_RAM6 Position */ +#define MXC_F_GCR_MEMZ_RAM6 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM6_POS)) /**< MEMZ_RAM6 Mask */ + +#define MXC_F_GCR_MEMZ_ICC_POS 8 /**< MEMZ_ICC Position */ +#define MXC_F_GCR_MEMZ_ICC ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_ICC_POS)) /**< MEMZ_ICC Mask */ + +#define MXC_F_GCR_MEMZ_ICCXIP_POS 9 /**< MEMZ_ICCXIP Position */ +#define MXC_F_GCR_MEMZ_ICCXIP ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_ICCXIP_POS)) /**< MEMZ_ICCXIP Mask */ + +#define MXC_F_GCR_MEMZ_SRCCDATA_POS 10 /**< MEMZ_SRCCDATA Position */ +#define MXC_F_GCR_MEMZ_SRCCDATA ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_SRCCDATA_POS)) /**< MEMZ_SRCCDATA Mask */ + +#define MXC_F_GCR_MEMZ_SRCCTAG_POS 11 /**< MEMZ_SRCCTAG Position */ +#define MXC_F_GCR_MEMZ_SRCCTAG ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_SRCCTAG_POS)) /**< MEMZ_SRCCTAG Mask */ + +#define MXC_F_GCR_MEMZ_USBFIFO_POS 13 /**< MEMZ_USBFIFO Position */ +#define MXC_F_GCR_MEMZ_USBFIFO ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_USBFIFO_POS)) /**< MEMZ_USBFIFO Mask */ + +/**@} end of group GCR_MEMZ_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_SYSST GCR_SYSST + * @brief System Status Register. + * @{ + */ +#define MXC_F_GCR_SYSST_ICELOCK_POS 0 /**< SYSST_ICELOCK Position */ +#define MXC_F_GCR_SYSST_ICELOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_ICELOCK_POS)) /**< SYSST_ICELOCK Mask */ + +#define MXC_F_GCR_SYSST_CODEAUTHERR_POS 1 /**< SYSST_CODEAUTHERR Position */ +#define MXC_F_GCR_SYSST_CODEAUTHERR ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_CODEAUTHERR_POS)) /**< SYSST_CODEAUTHERR Mask */ + +#define MXC_F_GCR_SYSST_DATAAUTHERR_POS 2 /**< SYSST_DATAAUTHERR Position */ +#define MXC_F_GCR_SYSST_DATAAUTHERR ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_DATAAUTHERR_POS)) /**< SYSST_DATAAUTHERR Mask */ + +#define MXC_F_GCR_SYSST_SCMEMF_POS 5 /**< SYSST_SCMEMF Position */ +#define MXC_F_GCR_SYSST_SCMEMF ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_SCMEMF_POS)) /**< SYSST_SCMEMF Mask */ + +/**@} end of group GCR_SYSST_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_RST1 GCR_RST1 + * @brief Reset 1. + * @{ + */ +#define MXC_F_GCR_RST1_I2C1_POS 0 /**< RST1_I2C1 Position */ +#define MXC_F_GCR_RST1_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C1_POS)) /**< RST1_I2C1 Mask */ + +#define MXC_F_GCR_RST1_PT_POS 1 /**< RST1_PT Position */ +#define MXC_F_GCR_RST1_PT ((uint32_t)(0x1UL << MXC_F_GCR_RST1_PT_POS)) /**< RST1_PT Mask */ + +#define MXC_F_GCR_RST1_OWIRE_POS 7 /**< RST1_OWIRE Position */ +#define MXC_F_GCR_RST1_OWIRE ((uint32_t)(0x1UL << MXC_F_GCR_RST1_OWIRE_POS)) /**< RST1_OWIRE Mask */ + +#define MXC_F_GCR_RST1_WDT1_POS 8 /**< RST1_WDT1 Position */ +#define MXC_F_GCR_RST1_WDT1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_WDT1_POS)) /**< RST1_WDT1 Mask */ + +#define MXC_F_GCR_RST1_CRC_POS 9 /**< RST1_CRC Position */ +#define MXC_F_GCR_RST1_CRC ((uint32_t)(0x1UL << MXC_F_GCR_RST1_CRC_POS)) /**< RST1_CRC Mask */ + +#define MXC_F_GCR_RST1_AES_POS 10 /**< RST1_AES Position */ +#define MXC_F_GCR_RST1_AES ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AES_POS)) /**< RST1_AES Mask */ + +#define MXC_F_GCR_RST1_I2S_POS 13 /**< RST1_I2S Position */ +#define MXC_F_GCR_RST1_I2S ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2S_POS)) /**< RST1_I2S Mask */ + +#define MXC_F_GCR_RST1_AC_POS 14 /**< RST1_AC Position */ +#define MXC_F_GCR_RST1_AC ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AC_POS)) /**< RST1_AC Mask */ + +#define MXC_F_GCR_RST1_SEMA_POS 16 /**< RST1_SEMA Position */ +#define MXC_F_GCR_RST1_SEMA ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SEMA_POS)) /**< RST1_SEMA Mask */ + +#define MXC_F_GCR_RST1_I2C2_POS 17 /**< RST1_I2C2 Position */ +#define MXC_F_GCR_RST1_I2C2 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C2_POS)) /**< RST1_I2C2 Mask */ + +#define MXC_F_GCR_RST1_UART3_POS 18 /**< RST1_UART3 Position */ +#define MXC_F_GCR_RST1_UART3 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_UART3_POS)) /**< RST1_UART3 Mask */ + +#define MXC_F_GCR_RST1_UART4_POS 19 /**< RST1_UART4 Position */ +#define MXC_F_GCR_RST1_UART4 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_UART4_POS)) /**< RST1_UART4 Mask */ + +#define MXC_F_GCR_RST1_UART5_POS 20 /**< RST1_UART5 Position */ +#define MXC_F_GCR_RST1_UART5 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_UART5_POS)) /**< RST1_UART5 Mask */ + +/**@} end of group GCR_RST1_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_PCLKDIS1 GCR_PCLKDIS1 + * @brief Peripheral Clock Disable. + * @{ + */ +#define MXC_F_GCR_PCLKDIS1_BTLE_POS 0 /**< PCLKDIS1_BTLE Position */ +#define MXC_F_GCR_PCLKDIS1_BTLE ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_BTLE_POS)) /**< PCLKDIS1_BTLE Mask */ + +#define MXC_F_GCR_PCLKDIS1_UART2_POS 1 /**< PCLKDIS1_UART2 Position */ +#define MXC_F_GCR_PCLKDIS1_UART2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_UART2_POS)) /**< PCLKDIS1_UART2 Mask */ + +#define MXC_F_GCR_PCLKDIS1_TRNG_POS 2 /**< PCLKDIS1_TRNG Position */ +#define MXC_F_GCR_PCLKDIS1_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_TRNG_POS)) /**< PCLKDIS1_TRNG Mask */ + +#define MXC_F_GCR_PCLKDIS1_WDT0_POS 4 /**< PCLKDIS1_WDT0 Position */ +#define MXC_F_GCR_PCLKDIS1_WDT0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_WDT0_POS)) /**< PCLKDIS1_WDT0 Mask */ + +#define MXC_F_GCR_PCLKDIS1_WDT1_POS 5 /**< PCLKDIS1_WDT1 Position */ +#define MXC_F_GCR_PCLKDIS1_WDT1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_WDT1_POS)) /**< PCLKDIS1_WDT1 Mask */ + +#define MXC_F_GCR_PCLKDIS1_SRCC_POS 7 /**< PCLKDIS1_SRCC Position */ +#define MXC_F_GCR_PCLKDIS1_SRCC ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_SRCC_POS)) /**< PCLKDIS1_SRCC Mask */ + +#define MXC_F_GCR_PCLKDIS1_SEMA_POS 9 /**< PCLKDIS1_SEMA Position */ +#define MXC_F_GCR_PCLKDIS1_SEMA ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_SEMA_POS)) /**< PCLKDIS1_SEMA Mask */ + +#define MXC_F_GCR_PCLKDIS1_OWIRE_POS 13 /**< PCLKDIS1_OWIRE Position */ +#define MXC_F_GCR_PCLKDIS1_OWIRE ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_OWIRE_POS)) /**< PCLKDIS1_OWIRE Mask */ + +#define MXC_F_GCR_PCLKDIS1_CRC_POS 14 /**< PCLKDIS1_CRC Position */ +#define MXC_F_GCR_PCLKDIS1_CRC ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_CRC_POS)) /**< PCLKDIS1_CRC Mask */ + +#define MXC_F_GCR_PCLKDIS1_AES_POS 15 /**< PCLKDIS1_AES Position */ +#define MXC_F_GCR_PCLKDIS1_AES ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_AES_POS)) /**< PCLKDIS1_AES Mask */ + +#define MXC_F_GCR_PCLKDIS1_I2S_POS 16 /**< PCLKDIS1_I2S Position */ +#define MXC_F_GCR_PCLKDIS1_I2S ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_I2S_POS)) /**< PCLKDIS1_I2S Mask */ + +#define MXC_F_GCR_PCLKDIS1_I2C2_POS 21 /**< PCLKDIS1_I2C2 Position */ +#define MXC_F_GCR_PCLKDIS1_I2C2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_I2C2_POS)) /**< PCLKDIS1_I2C2 Mask */ + +#define MXC_F_GCR_PCLKDIS1_UART3_POS 22 /**< PCLKDIS1_UART3 Position */ +#define MXC_F_GCR_PCLKDIS1_UART3 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_UART3_POS)) /**< PCLKDIS1_UART3 Mask */ + +#define MXC_F_GCR_PCLKDIS1_UART4_POS 23 /**< PCLKDIS1_UART4 Position */ +#define MXC_F_GCR_PCLKDIS1_UART4 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_UART4_POS)) /**< PCLKDIS1_UART4 Mask */ + +#define MXC_F_GCR_PCLKDIS1_UART5_POS 24 /**< PCLKDIS1_UART5 Position */ +#define MXC_F_GCR_PCLKDIS1_UART5 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_UART5_POS)) /**< PCLKDIS1_UART5 Mask */ + +/**@} end of group GCR_PCLKDIS1_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_EVENTEN GCR_EVENTEN + * @brief Event Enable Register. + * @{ + */ +#define MXC_F_GCR_EVENTEN_DMA_POS 0 /**< EVENTEN_DMA Position */ +#define MXC_F_GCR_EVENTEN_DMA ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_DMA_POS)) /**< EVENTEN_DMA Mask */ + +#define MXC_F_GCR_EVENTEN_RX_POS 1 /**< EVENTEN_RX Position */ +#define MXC_F_GCR_EVENTEN_RX ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_RX_POS)) /**< EVENTEN_RX Mask */ + +#define MXC_F_GCR_EVENTEN_TX_POS 2 /**< EVENTEN_TX Position */ +#define MXC_F_GCR_EVENTEN_TX ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_TX_POS)) /**< EVENTEN_TX Mask */ + +/**@} end of group GCR_EVENTEN_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_REVISION GCR_REVISION + * @brief Revision Register. + * @{ + */ +#define MXC_F_GCR_REVISION_REVISION_POS 0 /**< REVISION_REVISION Position */ +#define MXC_F_GCR_REVISION_REVISION ((uint32_t)(0xFFFFUL << MXC_F_GCR_REVISION_REVISION_POS)) /**< REVISION_REVISION Mask */ + +/**@} end of group GCR_REVISION_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_SYSINTEN GCR_SYSINTEN + * @brief System Status Interrupt Enable Register. + * @{ + */ +#define MXC_F_GCR_SYSINTEN_ICEUNLOCK_POS 0 /**< SYSINTEN_ICEUNLOCK Position */ +#define MXC_F_GCR_SYSINTEN_ICEUNLOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSINTEN_ICEUNLOCK_POS)) /**< SYSINTEN_ICEUNLOCK Mask */ + +#define MXC_F_GCR_SYSINTEN_CIE_POS 1 /**< SYSINTEN_CIE Position */ +#define MXC_F_GCR_SYSINTEN_CIE ((uint32_t)(0x1UL << MXC_F_GCR_SYSINTEN_CIE_POS)) /**< SYSINTEN_CIE Mask */ + +#define MXC_F_GCR_SYSINTEN_SCMF_POS 5 /**< SYSINTEN_SCMF Position */ +#define MXC_F_GCR_SYSINTEN_SCMF ((uint32_t)(0x1UL << MXC_F_GCR_SYSINTEN_SCMF_POS)) /**< SYSINTEN_SCMF Mask */ + +/**@} end of group GCR_SYSINTEN_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_IPOCNT GCR_IPOCNT + * @brief IPO Warmup Count Register. + * @{ + */ +#define MXC_F_GCR_IPOCNT_WMUPCNT_POS 0 /**< IPOCNT_WMUPCNT Position */ +#define MXC_F_GCR_IPOCNT_WMUPCNT ((uint32_t)(0x3FFUL << MXC_F_GCR_IPOCNT_WMUPCNT_POS)) /**< IPOCNT_WMUPCNT Mask */ + +/**@} end of group GCR_IPOCNT_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_ECCERR GCR_ECCERR + * @brief ECC Error Register + * @{ + */ +#define MXC_F_GCR_ECCERR_RAM0_POS 0 /**< ECCERR_RAM0 Position */ +#define MXC_F_GCR_ECCERR_RAM0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM0_POS)) /**< ECCERR_RAM0 Mask */ + +#define MXC_F_GCR_ECCERR_RAM1_POS 1 /**< ECCERR_RAM1 Position */ +#define MXC_F_GCR_ECCERR_RAM1 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM1_POS)) /**< ECCERR_RAM1 Mask */ + +#define MXC_F_GCR_ECCERR_RAM2_POS 2 /**< ECCERR_RAM2 Position */ +#define MXC_F_GCR_ECCERR_RAM2 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM2_POS)) /**< ECCERR_RAM2 Mask */ + +#define MXC_F_GCR_ECCERR_RAM3_POS 3 /**< ECCERR_RAM3 Position */ +#define MXC_F_GCR_ECCERR_RAM3 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM3_POS)) /**< ECCERR_RAM3 Mask */ + +#define MXC_F_GCR_ECCERR_RAM4_POS 4 /**< ECCERR_RAM4 Position */ +#define MXC_F_GCR_ECCERR_RAM4 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM4_POS)) /**< ECCERR_RAM4 Mask */ + +#define MXC_F_GCR_ECCERR_RAM5_POS 5 /**< ECCERR_RAM5 Position */ +#define MXC_F_GCR_ECCERR_RAM5 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM5_POS)) /**< ECCERR_RAM5 Mask */ + +#define MXC_F_GCR_ECCERR_ICC_POS 8 /**< ECCERR_ICC Position */ +#define MXC_F_GCR_ECCERR_ICC ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_ICC_POS)) /**< ECCERR_ICC Mask */ + +#define MXC_F_GCR_ECCERR_ICCXIP_POS 10 /**< ECCERR_ICCXIP Position */ +#define MXC_F_GCR_ECCERR_ICCXIP ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_ICCXIP_POS)) /**< ECCERR_ICCXIP Mask */ + +#define MXC_F_GCR_ECCERR_FLASH_POS 11 /**< ECCERR_FLASH Position */ +#define MXC_F_GCR_ECCERR_FLASH ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_FLASH_POS)) /**< ECCERR_FLASH Mask */ + +/**@} end of group GCR_ECCERR_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_ECCCED GCR_ECCCED + * @brief ECC Not Double Error Detect Register + * @{ + */ +#define MXC_F_GCR_ECCCED_RAM0_POS 0 /**< ECCCED_RAM0 Position */ +#define MXC_F_GCR_ECCCED_RAM0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM0_POS)) /**< ECCCED_RAM0 Mask */ + +#define MXC_F_GCR_ECCCED_RAM1_POS 1 /**< ECCCED_RAM1 Position */ +#define MXC_F_GCR_ECCCED_RAM1 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM1_POS)) /**< ECCCED_RAM1 Mask */ + +#define MXC_F_GCR_ECCCED_RAM2_POS 2 /**< ECCCED_RAM2 Position */ +#define MXC_F_GCR_ECCCED_RAM2 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM2_POS)) /**< ECCCED_RAM2 Mask */ + +#define MXC_F_GCR_ECCCED_RAM3_POS 3 /**< ECCCED_RAM3 Position */ +#define MXC_F_GCR_ECCCED_RAM3 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM3_POS)) /**< ECCCED_RAM3 Mask */ + +#define MXC_F_GCR_ECCCED_RAM4_POS 4 /**< ECCCED_RAM4 Position */ +#define MXC_F_GCR_ECCCED_RAM4 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM4_POS)) /**< ECCCED_RAM4 Mask */ + +#define MXC_F_GCR_ECCCED_RAM5_POS 5 /**< ECCCED_RAM5 Position */ +#define MXC_F_GCR_ECCCED_RAM5 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM5_POS)) /**< ECCCED_RAM5 Mask */ + +#define MXC_F_GCR_ECCCED_ICC_POS 8 /**< ECCCED_ICC Position */ +#define MXC_F_GCR_ECCCED_ICC ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_ICC_POS)) /**< ECCCED_ICC Mask */ + +#define MXC_F_GCR_ECCCED_ICCXIP_POS 10 /**< ECCCED_ICCXIP Position */ +#define MXC_F_GCR_ECCCED_ICCXIP ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_ICCXIP_POS)) /**< ECCCED_ICCXIP Mask */ + +#define MXC_F_GCR_ECCCED_FLASH_POS 11 /**< ECCCED_FLASH Position */ +#define MXC_F_GCR_ECCCED_FLASH ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_FLASH_POS)) /**< ECCCED_FLASH Mask */ + +/**@} end of group GCR_ECCCED_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_ECCINTEN GCR_ECCINTEN + * @brief ECC Interrupt Enable Register + * @{ + */ +#define MXC_F_GCR_ECCINTEN_RAM0_POS 0 /**< ECCINTEN_RAM0 Position */ +#define MXC_F_GCR_ECCINTEN_RAM0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCINTEN_RAM0_POS)) /**< ECCINTEN_RAM0 Mask */ + +#define MXC_F_GCR_ECCINTEN_RAM1_POS 1 /**< ECCINTEN_RAM1 Position */ +#define MXC_F_GCR_ECCINTEN_RAM1 ((uint32_t)(0x1UL << MXC_F_GCR_ECCINTEN_RAM1_POS)) /**< ECCINTEN_RAM1 Mask */ + +#define MXC_F_GCR_ECCINTEN_RAM2_POS 2 /**< ECCINTEN_RAM2 Position */ +#define MXC_F_GCR_ECCINTEN_RAM2 ((uint32_t)(0x1UL << MXC_F_GCR_ECCINTEN_RAM2_POS)) /**< ECCINTEN_RAM2 Mask */ + +#define MXC_F_GCR_ECCINTEN_RAM3_POS 3 /**< ECCINTEN_RAM3 Position */ +#define MXC_F_GCR_ECCINTEN_RAM3 ((uint32_t)(0x1UL << MXC_F_GCR_ECCINTEN_RAM3_POS)) /**< ECCINTEN_RAM3 Mask */ + +#define MXC_F_GCR_ECCINTEN_RAM4_POS 4 /**< ECCINTEN_RAM4 Position */ +#define MXC_F_GCR_ECCINTEN_RAM4 ((uint32_t)(0x1UL << MXC_F_GCR_ECCINTEN_RAM4_POS)) /**< ECCINTEN_RAM4 Mask */ + +#define MXC_F_GCR_ECCINTEN_RAM5_POS 5 /**< ECCINTEN_RAM5 Position */ +#define MXC_F_GCR_ECCINTEN_RAM5 ((uint32_t)(0x1UL << MXC_F_GCR_ECCINTEN_RAM5_POS)) /**< ECCINTEN_RAM5 Mask */ + +#define MXC_F_GCR_ECCINTEN_ICC_POS 8 /**< ECCINTEN_ICC Position */ +#define MXC_F_GCR_ECCINTEN_ICC ((uint32_t)(0x1UL << MXC_F_GCR_ECCINTEN_ICC_POS)) /**< ECCINTEN_ICC Mask */ + +#define MXC_F_GCR_ECCINTEN_ICCXIP_POS 10 /**< ECCINTEN_ICCXIP Position */ +#define MXC_F_GCR_ECCINTEN_ICCXIP ((uint32_t)(0x1UL << MXC_F_GCR_ECCINTEN_ICCXIP_POS)) /**< ECCINTEN_ICCXIP Mask */ + +#define MXC_F_GCR_ECCINTEN_FLASH_POS 11 /**< ECCINTEN_FLASH Position */ +#define MXC_F_GCR_ECCINTEN_FLASH ((uint32_t)(0x1UL << MXC_F_GCR_ECCINTEN_FLASH_POS)) /**< ECCINTEN_FLASH Mask */ + +/**@} end of group GCR_ECCINTEN_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_ECCADDR GCR_ECCADDR + * @brief ECC Error Address Register + * @{ + */ +#define MXC_F_GCR_ECCADDR_DADDR_POS 0 /**< ECCADDR_DADDR Position */ +#define MXC_F_GCR_ECCADDR_DADDR ((uint32_t)(0x3FFFUL << MXC_F_GCR_ECCADDR_DADDR_POS)) /**< ECCADDR_DADDR Mask */ + +#define MXC_F_GCR_ECCADDR_DB_POS 14 /**< ECCADDR_DB Position */ +#define MXC_F_GCR_ECCADDR_DB ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_DB_POS)) /**< ECCADDR_DB Mask */ + +#define MXC_F_GCR_ECCADDR_DE_POS 15 /**< ECCADDR_DE Position */ +#define MXC_F_GCR_ECCADDR_DE ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_DE_POS)) /**< ECCADDR_DE Mask */ + +#define MXC_F_GCR_ECCADDR_TADDR_POS 16 /**< ECCADDR_TADDR Position */ +#define MXC_F_GCR_ECCADDR_TADDR ((uint32_t)(0x3FFFUL << MXC_F_GCR_ECCADDR_TADDR_POS)) /**< ECCADDR_TADDR Mask */ + +#define MXC_F_GCR_ECCADDR_TB_POS 30 /**< ECCADDR_TB Position */ +#define MXC_F_GCR_ECCADDR_TB ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_TB_POS)) /**< ECCADDR_TB Mask */ + +#define MXC_F_GCR_ECCADDR_TE_POS 31 /**< ECCADDR_TE Position */ +#define MXC_F_GCR_ECCADDR_TE ((uint32_t)(0x1UL << MXC_F_GCR_ECCADDR_TE_POS)) /**< ECCADDR_TE Mask */ + +/**@} end of group GCR_ECCADDR_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_BTLELDOCTRL GCR_BTLELDOCTRL + * @brief BTLE LDO Control Register + * @{ + */ +#define MXC_F_GCR_BTLELDOCTRL_TX_EN_POS 0 /**< BTLELDOCTRL_TX_EN Position */ +#define MXC_F_GCR_BTLELDOCTRL_TX_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_TX_EN_POS)) /**< BTLELDOCTRL_TX_EN Mask */ + +#define MXC_F_GCR_BTLELDOCTRL_TX_PD_EN_POS 1 /**< BTLELDOCTRL_TX_PD_EN Position */ +#define MXC_F_GCR_BTLELDOCTRL_TX_PD_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_TX_PD_EN_POS)) /**< BTLELDOCTRL_TX_PD_EN Mask */ + +#define MXC_F_GCR_BTLELDOCTRL_TX_VSEL_POS 2 /**< BTLELDOCTRL_TX_VSEL Position */ +#define MXC_F_GCR_BTLELDOCTRL_TX_VSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_TX_VSEL_POS)) /**< BTLELDOCTRL_TX_VSEL Mask */ + +#define MXC_F_GCR_BTLELDOCTRL_RX_EN_POS 4 /**< BTLELDOCTRL_RX_EN Position */ +#define MXC_F_GCR_BTLELDOCTRL_RX_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RX_EN_POS)) /**< BTLELDOCTRL_RX_EN Mask */ + +#define MXC_F_GCR_BTLELDOCTRL_RX_PD_EN_POS 5 /**< BTLELDOCTRL_RX_PD_EN Position */ +#define MXC_F_GCR_BTLELDOCTRL_RX_PD_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RX_PD_EN_POS)) /**< BTLELDOCTRL_RX_PD_EN Mask */ + +#define MXC_F_GCR_BTLELDOCTRL_RX_VSEL_POS 6 /**< BTLELDOCTRL_RX_VSEL Position */ +#define MXC_F_GCR_BTLELDOCTRL_RX_VSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_RX_VSEL_POS)) /**< BTLELDOCTRL_RX_VSEL Mask */ + +#define MXC_F_GCR_BTLELDOCTRL_RX_BP_EN_POS 8 /**< BTLELDOCTRL_RX_BP_EN Position */ +#define MXC_F_GCR_BTLELDOCTRL_RX_BP_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RX_BP_EN_POS)) /**< BTLELDOCTRL_RX_BP_EN Mask */ + +#define MXC_F_GCR_BTLELDOCTRL_RX_DISCH_POS 9 /**< BTLELDOCTRL_RX_DISCH Position */ +#define MXC_F_GCR_BTLELDOCTRL_RX_DISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RX_DISCH_POS)) /**< BTLELDOCTRL_RX_DISCH Mask */ + +#define MXC_F_GCR_BTLELDOCTRL_TX_BP_EN_POS 10 /**< BTLELDOCTRL_TX_BP_EN Position */ +#define MXC_F_GCR_BTLELDOCTRL_TX_BP_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_TX_BP_EN_POS)) /**< BTLELDOCTRL_TX_BP_EN Mask */ + +#define MXC_F_GCR_BTLELDOCTRL_TX_DISCH_POS 11 /**< BTLELDOCTRL_TX_DISCH Position */ +#define MXC_F_GCR_BTLELDOCTRL_TX_DISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_TX_DISCH_POS)) /**< BTLELDOCTRL_TX_DISCH Mask */ + +#define MXC_F_GCR_BTLELDOCTRL_TX_EN_DLY_POS 12 /**< BTLELDOCTRL_TX_EN_DLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_TX_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_TX_EN_DLY_POS)) /**< BTLELDOCTRL_TX_EN_DLY Mask */ + +#define MXC_F_GCR_BTLELDOCTRL_RX_EN_DLY_POS 13 /**< BTLELDOCTRL_RX_EN_DLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_RX_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RX_EN_DLY_POS)) /**< BTLELDOCTRL_RX_EN_DLY Mask */ + +#define MXC_F_GCR_BTLELDOCTRL_RX_BP_EN_DLY_POS 14 /**< BTLELDOCTRL_RX_BP_EN_DLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_RX_BP_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RX_BP_EN_DLY_POS)) /**< BTLELDOCTRL_RX_BP_EN_DLY Mask */ + +#define MXC_F_GCR_BTLELDOCTRL_TX_BP_EN_DLY_POS 15 /**< BTLELDOCTRL_TX_BP_EN_DLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_TX_BP_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_TX_BP_EN_DLY_POS)) /**< BTLELDOCTRL_TX_BP_EN_DLY Mask */ + +/**@} end of group GCR_BTLELDOCTRL_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_BTLELDODLY GCR_BTLELDODLY + * @brief BTLE LDO Delay Register + * @{ + */ +#define MXC_F_GCR_BTLELDODLY_BP_CNT_POS 0 /**< BTLELDODLY_BP_CNT Position */ +#define MXC_F_GCR_BTLELDODLY_BP_CNT ((uint32_t)(0xFFUL << MXC_F_GCR_BTLELDODLY_BP_CNT_POS)) /**< BTLELDODLY_BP_CNT Mask */ + +#define MXC_F_GCR_BTLELDODLY_RX_CNT_POS 8 /**< BTLELDODLY_RX_CNT Position */ +#define MXC_F_GCR_BTLELDODLY_RX_CNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLELDODLY_RX_CNT_POS)) /**< BTLELDODLY_RX_CNT Mask */ + +#define MXC_F_GCR_BTLELDODLY_TX_CNT_POS 20 /**< BTLELDODLY_TX_CNT Position */ +#define MXC_F_GCR_BTLELDODLY_TX_CNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLELDODLY_TX_CNT_POS)) /**< BTLELDODLY_TX_CNT Mask */ + +/**@} end of group GCR_BTLELDODLY_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_FLVRST GCR_FLVRST + * @brief Flash Low Voltage Reset Control Register + * @{ + */ +#define MXC_F_GCR_FLVRST_EN_POS 0 /**< FLVRST_EN Position */ +#define MXC_F_GCR_FLVRST_EN ((uint32_t)(0x1UL << MXC_F_GCR_FLVRST_EN_POS)) /**< FLVRST_EN Mask */ + +/**@} end of group GCR_FLVRST_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_FLVCLKCTRL GCR_FLVCLKCTRL + * @brief Flash Low Voltage Clock Control Register + * @{ + */ +#define MXC_F_GCR_FLVCLKCTRL_DIV_POS 0 /**< FLVCLKCTRL_DIV Position */ +#define MXC_F_GCR_FLVCLKCTRL_DIV ((uint32_t)(0x3UL << MXC_F_GCR_FLVCLKCTRL_DIV_POS)) /**< FLVCLKCTRL_DIV Mask */ +#define MXC_V_GCR_FLVCLKCTRL_DIV_512 ((uint32_t)0x0UL) /**< FLVCLKCTRL_DIV_512 Value */ +#define MXC_S_GCR_FLVCLKCTRL_DIV_512 (MXC_V_GCR_FLVCLKCTRL_DIV_512 << MXC_F_GCR_FLVCLKCTRL_DIV_POS) /**< FLVCLKCTRL_DIV_512 Setting */ +#define MXC_V_GCR_FLVCLKCTRL_DIV_256 ((uint32_t)0x1UL) /**< FLVCLKCTRL_DIV_256 Value */ +#define MXC_S_GCR_FLVCLKCTRL_DIV_256 (MXC_V_GCR_FLVCLKCTRL_DIV_256 << MXC_F_GCR_FLVCLKCTRL_DIV_POS) /**< FLVCLKCTRL_DIV_256 Setting */ +#define MXC_V_GCR_FLVCLKCTRL_DIV_128 ((uint32_t)0x2UL) /**< FLVCLKCTRL_DIV_128 Value */ +#define MXC_S_GCR_FLVCLKCTRL_DIV_128 (MXC_V_GCR_FLVCLKCTRL_DIV_128 << MXC_F_GCR_FLVCLKCTRL_DIV_POS) /**< FLVCLKCTRL_DIV_128 Setting */ +#define MXC_V_GCR_FLVCLKCTRL_DIV_64 ((uint32_t)0x3UL) /**< FLVCLKCTRL_DIV_64 Value */ +#define MXC_S_GCR_FLVCLKCTRL_DIV_64 (MXC_V_GCR_FLVCLKCTRL_DIV_64 << MXC_F_GCR_FLVCLKCTRL_DIV_POS) /**< FLVCLKCTRL_DIV_64 Setting */ + +/**@} end of group GCR_FLVCLKCTRL_Register */ + +/** + * @ingroup gcr_registers + * @defgroup GCR_FLVSTAT GCR_FLVSTAT + * @brief Flash Low Voltage Status Register + * @{ + */ +#define MXC_F_GCR_FLVSTAT_FLV_POS 0 /**< FLVSTAT_FLV Position */ +#define MXC_F_GCR_FLVSTAT_FLV ((uint32_t)(0x1UL << MXC_F_GCR_FLVSTAT_FLV_POS)) /**< FLVSTAT_FLV Mask */ + +#define MXC_F_GCR_FLVSTAT_ONES_POS 6 /**< FLVSTAT_ONES Position */ +#define MXC_F_GCR_FLVSTAT_ONES ((uint32_t)(0x1UL << MXC_F_GCR_FLVSTAT_ONES_POS)) /**< FLVSTAT_ONES Mask */ + +#define MXC_F_GCR_FLVSTAT_ZEROS_POS 7 /**< FLVSTAT_ZEROS Position */ +#define MXC_F_GCR_FLVSTAT_ZEROS ((uint32_t)(0x1UL << MXC_F_GCR_FLVSTAT_ZEROS_POS)) /**< FLVSTAT_ZEROS Mask */ + +#define MXC_F_GCR_FLVSTAT_ONES_FL_POS 14 /**< FLVSTAT_ONES_FL Position */ +#define MXC_F_GCR_FLVSTAT_ONES_FL ((uint32_t)(0x1UL << MXC_F_GCR_FLVSTAT_ONES_FL_POS)) /**< FLVSTAT_ONES_FL Mask */ + +#define MXC_F_GCR_FLVSTAT_ZEROS_FL_POS 15 /**< FLVSTAT_ZEROS_FL Position */ +#define MXC_F_GCR_FLVSTAT_ZEROS_FL ((uint32_t)(0x1UL << MXC_F_GCR_FLVSTAT_ZEROS_FL_POS)) /**< FLVSTAT_ZEROS_FL Mask */ + +#define MXC_F_GCR_FLVSTAT_BUF_POS 16 /**< FLVSTAT_BUF Position */ +#define MXC_F_GCR_FLVSTAT_BUF ((uint32_t)(0x3FFUL << MXC_F_GCR_FLVSTAT_BUF_POS)) /**< FLVSTAT_BUF Mask */ + +/**@} end of group GCR_FLVSTAT_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_GCR_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gpio_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gpio_regs.h new file mode 100644 index 00000000000..f7f759f9ed1 --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gpio_regs.h @@ -0,0 +1,678 @@ +/** + * @file gpio_regs.h + * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module. + * @note This file is @generated. + * @ingroup gpio_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_GPIO_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_GPIO_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup gpio + * @defgroup gpio_registers GPIO_Registers + * @brief Registers, Bit Masks and Bit Positions for the GPIO Peripheral Module. + * @details Individual I/O for each GPIO + */ + +/** + * @ingroup gpio_registers + * Structure type to access the GPIO Registers. + */ +typedef struct { + __IO uint32_t en0; /**< \b 0x00: GPIO EN0 Register */ + __IO uint32_t en0_set; /**< \b 0x04: GPIO EN0_SET Register */ + __IO uint32_t en0_clr; /**< \b 0x08: GPIO EN0_CLR Register */ + __IO uint32_t outen; /**< \b 0x0C: GPIO OUTEN Register */ + __IO uint32_t outen_set; /**< \b 0x10: GPIO OUTEN_SET Register */ + __IO uint32_t outen_clr; /**< \b 0x14: GPIO OUTEN_CLR Register */ + __IO uint32_t out; /**< \b 0x18: GPIO OUT Register */ + __O uint32_t out_set; /**< \b 0x1C: GPIO OUT_SET Register */ + __O uint32_t out_clr; /**< \b 0x20: GPIO OUT_CLR Register */ + __I uint32_t in; /**< \b 0x24: GPIO IN Register */ + __IO uint32_t intmode; /**< \b 0x28: GPIO INTMODE Register */ + __IO uint32_t intpol; /**< \b 0x2C: GPIO INTPOL Register */ + __IO uint32_t inen; /**< \b 0x30: GPIO INEN Register */ + __IO uint32_t inten; /**< \b 0x34: GPIO INTEN Register */ + __IO uint32_t inten_set; /**< \b 0x38: GPIO INTEN_SET Register */ + __IO uint32_t inten_clr; /**< \b 0x3C: GPIO INTEN_CLR Register */ + __I uint32_t intfl; /**< \b 0x40: GPIO INTFL Register */ + __R uint32_t rsv_0x44; + __IO uint32_t intfl_clr; /**< \b 0x48: GPIO INTFL_CLR Register */ + __IO uint32_t wken; /**< \b 0x4C: GPIO WKEN Register */ + __IO uint32_t wken_set; /**< \b 0x50: GPIO WKEN_SET Register */ + __IO uint32_t wken_clr; /**< \b 0x54: GPIO WKEN_CLR Register */ + __R uint32_t rsv_0x58; + __IO uint32_t dualedge; /**< \b 0x5C: GPIO DUALEDGE Register */ + __IO uint32_t padctrl0; /**< \b 0x60: GPIO PADCTRL0 Register */ + __IO uint32_t padctrl1; /**< \b 0x64: GPIO PADCTRL1 Register */ + __IO uint32_t en1; /**< \b 0x68: GPIO EN1 Register */ + __IO uint32_t en1_set; /**< \b 0x6C: GPIO EN1_SET Register */ + __IO uint32_t en1_clr; /**< \b 0x70: GPIO EN1_CLR Register */ + __IO uint32_t en2; /**< \b 0x74: GPIO EN2 Register */ + __IO uint32_t en2_set; /**< \b 0x78: GPIO EN2_SET Register */ + __IO uint32_t en2_clr; /**< \b 0x7C: GPIO EN2_CLR Register */ + __R uint32_t rsv_0x80_0xa7[10]; + __IO uint32_t hysen; /**< \b 0xA8: GPIO HYSEN Register */ + __IO uint32_t srsel; /**< \b 0xAC: GPIO SRSEL Register */ + __IO uint32_t ds0; /**< \b 0xB0: GPIO DS0 Register */ + __IO uint32_t ds1; /**< \b 0xB4: GPIO DS1 Register */ + __IO uint32_t pssel; /**< \b 0xB8: GPIO PSSEL Register */ + __R uint32_t rsv_0xbc; + __IO uint32_t vssel; /**< \b 0xC0: GPIO VSSEL Register */ +} mxc_gpio_regs_t; + +/* Register offsets for module GPIO */ +/** + * @ingroup gpio_registers + * @defgroup GPIO_Register_Offsets Register Offsets + * @brief GPIO Peripheral Register Offsets from the GPIO Base Peripheral Address. + * @{ + */ +#define MXC_R_GPIO_EN0 ((uint32_t)0x00000000UL) /**< Offset from GPIO Base Address: 0x0000 */ +#define MXC_R_GPIO_EN0_SET ((uint32_t)0x00000004UL) /**< Offset from GPIO Base Address: 0x0004 */ +#define MXC_R_GPIO_EN0_CLR ((uint32_t)0x00000008UL) /**< Offset from GPIO Base Address: 0x0008 */ +#define MXC_R_GPIO_OUTEN ((uint32_t)0x0000000CUL) /**< Offset from GPIO Base Address: 0x000C */ +#define MXC_R_GPIO_OUTEN_SET ((uint32_t)0x00000010UL) /**< Offset from GPIO Base Address: 0x0010 */ +#define MXC_R_GPIO_OUTEN_CLR ((uint32_t)0x00000014UL) /**< Offset from GPIO Base Address: 0x0014 */ +#define MXC_R_GPIO_OUT ((uint32_t)0x00000018UL) /**< Offset from GPIO Base Address: 0x0018 */ +#define MXC_R_GPIO_OUT_SET ((uint32_t)0x0000001CUL) /**< Offset from GPIO Base Address: 0x001C */ +#define MXC_R_GPIO_OUT_CLR ((uint32_t)0x00000020UL) /**< Offset from GPIO Base Address: 0x0020 */ +#define MXC_R_GPIO_IN ((uint32_t)0x00000024UL) /**< Offset from GPIO Base Address: 0x0024 */ +#define MXC_R_GPIO_INTMODE ((uint32_t)0x00000028UL) /**< Offset from GPIO Base Address: 0x0028 */ +#define MXC_R_GPIO_INTPOL ((uint32_t)0x0000002CUL) /**< Offset from GPIO Base Address: 0x002C */ +#define MXC_R_GPIO_INEN ((uint32_t)0x00000030UL) /**< Offset from GPIO Base Address: 0x0030 */ +#define MXC_R_GPIO_INTEN ((uint32_t)0x00000034UL) /**< Offset from GPIO Base Address: 0x0034 */ +#define MXC_R_GPIO_INTEN_SET ((uint32_t)0x00000038UL) /**< Offset from GPIO Base Address: 0x0038 */ +#define MXC_R_GPIO_INTEN_CLR ((uint32_t)0x0000003CUL) /**< Offset from GPIO Base Address: 0x003C */ +#define MXC_R_GPIO_INTFL ((uint32_t)0x00000040UL) /**< Offset from GPIO Base Address: 0x0040 */ +#define MXC_R_GPIO_INTFL_CLR ((uint32_t)0x00000048UL) /**< Offset from GPIO Base Address: 0x0048 */ +#define MXC_R_GPIO_WKEN ((uint32_t)0x0000004CUL) /**< Offset from GPIO Base Address: 0x004C */ +#define MXC_R_GPIO_WKEN_SET ((uint32_t)0x00000050UL) /**< Offset from GPIO Base Address: 0x0050 */ +#define MXC_R_GPIO_WKEN_CLR ((uint32_t)0x00000054UL) /**< Offset from GPIO Base Address: 0x0054 */ +#define MXC_R_GPIO_DUALEDGE ((uint32_t)0x0000005CUL) /**< Offset from GPIO Base Address: 0x005C */ +#define MXC_R_GPIO_PADCTRL0 ((uint32_t)0x00000060UL) /**< Offset from GPIO Base Address: 0x0060 */ +#define MXC_R_GPIO_PADCTRL1 ((uint32_t)0x00000064UL) /**< Offset from GPIO Base Address: 0x0064 */ +#define MXC_R_GPIO_EN1 ((uint32_t)0x00000068UL) /**< Offset from GPIO Base Address: 0x0068 */ +#define MXC_R_GPIO_EN1_SET ((uint32_t)0x0000006CUL) /**< Offset from GPIO Base Address: 0x006C */ +#define MXC_R_GPIO_EN1_CLR ((uint32_t)0x00000070UL) /**< Offset from GPIO Base Address: 0x0070 */ +#define MXC_R_GPIO_EN2 ((uint32_t)0x00000074UL) /**< Offset from GPIO Base Address: 0x0074 */ +#define MXC_R_GPIO_EN2_SET ((uint32_t)0x00000078UL) /**< Offset from GPIO Base Address: 0x0078 */ +#define MXC_R_GPIO_EN2_CLR ((uint32_t)0x0000007CUL) /**< Offset from GPIO Base Address: 0x007C */ +#define MXC_R_GPIO_HYSEN ((uint32_t)0x000000A8UL) /**< Offset from GPIO Base Address: 0x00A8 */ +#define MXC_R_GPIO_SRSEL ((uint32_t)0x000000ACUL) /**< Offset from GPIO Base Address: 0x00AC */ +#define MXC_R_GPIO_DS0 ((uint32_t)0x000000B0UL) /**< Offset from GPIO Base Address: 0x00B0 */ +#define MXC_R_GPIO_DS1 ((uint32_t)0x000000B4UL) /**< Offset from GPIO Base Address: 0x00B4 */ +#define MXC_R_GPIO_PSSEL ((uint32_t)0x000000B8UL) /**< Offset from GPIO Base Address: 0x00B8 */ +#define MXC_R_GPIO_VSSEL ((uint32_t)0x000000C0UL) /**< Offset from GPIO Base Address: 0x00C0 */ +/**@} end of group gpio_registers */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN0 GPIO_EN0 + * @brief GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one + * GPIO pin on the associated port. + * @{ + */ +#define MXC_F_GPIO_EN0_ALL_POS 0 /**< EN0_ALL Position */ +#define MXC_F_GPIO_EN0_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_ALL_POS)) /**< EN0_ALL Mask */ +#define MXC_V_GPIO_EN0_ALL_ALTERNATE ((uint32_t)0x0UL) /**< EN0_ALL_ALTERNATE Value */ +#define MXC_S_GPIO_EN0_ALL_ALTERNATE (MXC_V_GPIO_EN0_ALL_ALTERNATE << MXC_F_GPIO_EN0_ALL_POS) /**< EN0_ALL_ALTERNATE Setting */ +#define MXC_V_GPIO_EN0_ALL_GPIO ((uint32_t)0x1UL) /**< EN0_ALL_GPIO Value */ +#define MXC_S_GPIO_EN0_ALL_GPIO (MXC_V_GPIO_EN0_ALL_GPIO << MXC_F_GPIO_EN0_ALL_POS) /**< EN0_ALL_GPIO Setting */ + +/**@} end of group GPIO_EN0_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN0_SET GPIO_EN0_SET + * @brief GPIO Set Function Enable Register. Writing a 1 to one or more bits in this + * register sets the bits in the same positions in GPIO_EN to 1, without affecting + * other bits in that register. + * @{ + */ +#define MXC_F_GPIO_EN0_SET_ALL_POS 0 /**< EN0_SET_ALL Position */ +#define MXC_F_GPIO_EN0_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_SET_ALL_POS)) /**< EN0_SET_ALL Mask */ + +/**@} end of group GPIO_EN0_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN0_CLR GPIO_EN0_CLR + * @brief GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this + * register clears the bits in the same positions in GPIO_EN to 0, without + * affecting other bits in that register. + * @{ + */ +#define MXC_F_GPIO_EN0_CLR_ALL_POS 0 /**< EN0_CLR_ALL Position */ +#define MXC_F_GPIO_EN0_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN0_CLR_ALL_POS)) /**< EN0_CLR_ALL Mask */ + +/**@} end of group GPIO_EN0_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_OUTEN GPIO_OUTEN + * @brief GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one + * GPIO pin in the associated port. + * @{ + */ +#define MXC_F_GPIO_OUTEN_ALL_POS 0 /**< OUTEN_ALL Position */ +#define MXC_F_GPIO_OUTEN_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUTEN_ALL_POS)) /**< OUTEN_ALL Mask */ +#define MXC_V_GPIO_OUTEN_ALL_DIS ((uint32_t)0x0UL) /**< OUTEN_ALL_DIS Value */ +#define MXC_S_GPIO_OUTEN_ALL_DIS (MXC_V_GPIO_OUTEN_ALL_DIS << MXC_F_GPIO_OUTEN_ALL_POS) /**< OUTEN_ALL_DIS Setting */ +#define MXC_V_GPIO_OUTEN_ALL_EN ((uint32_t)0x1UL) /**< OUTEN_ALL_EN Value */ +#define MXC_S_GPIO_OUTEN_ALL_EN (MXC_V_GPIO_OUTEN_ALL_EN << MXC_F_GPIO_OUTEN_ALL_POS) /**< OUTEN_ALL_EN Setting */ + +/**@} end of group GPIO_OUTEN_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_OUTEN_SET GPIO_OUTEN_SET + * @brief GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits + * in this register sets the bits in the same positions in GPIO_OUT_EN to 1, + * without affecting other bits in that register. + * @{ + */ +#define MXC_F_GPIO_OUTEN_SET_ALL_POS 0 /**< OUTEN_SET_ALL Position */ +#define MXC_F_GPIO_OUTEN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUTEN_SET_ALL_POS)) /**< OUTEN_SET_ALL Mask */ + +/**@} end of group GPIO_OUTEN_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_OUTEN_CLR GPIO_OUTEN_CLR + * @brief GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more + * bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, + * without affecting other bits in that register. + * @{ + */ +#define MXC_F_GPIO_OUTEN_CLR_ALL_POS 0 /**< OUTEN_CLR_ALL Position */ +#define MXC_F_GPIO_OUTEN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUTEN_CLR_ALL_POS)) /**< OUTEN_CLR_ALL Mask */ + +/**@} end of group GPIO_OUTEN_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_OUT GPIO_OUT + * @brief GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the + * associated port. This register can be written either directly, or by using the + * GPIO_OUT_SET and GPIO_OUT_CLR registers. + * @{ + */ +#define MXC_F_GPIO_OUT_ALL_POS 0 /**< OUT_ALL Position */ +#define MXC_F_GPIO_OUT_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_ALL_POS)) /**< OUT_ALL Mask */ +#define MXC_V_GPIO_OUT_ALL_LOW ((uint32_t)0x0UL) /**< OUT_ALL_LOW Value */ +#define MXC_S_GPIO_OUT_ALL_LOW (MXC_V_GPIO_OUT_ALL_LOW << MXC_F_GPIO_OUT_ALL_POS) /**< OUT_ALL_LOW Setting */ +#define MXC_V_GPIO_OUT_ALL_HIGH ((uint32_t)0x1UL) /**< OUT_ALL_HIGH Value */ +#define MXC_S_GPIO_OUT_ALL_HIGH (MXC_V_GPIO_OUT_ALL_HIGH << MXC_F_GPIO_OUT_ALL_POS) /**< OUT_ALL_HIGH Setting */ + +/**@} end of group GPIO_OUT_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_OUT_SET GPIO_OUT_SET + * @brief GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits + * in the same positions in GPIO_OUT to 1, without affecting other bits in that + * register. + * @{ + */ +#define MXC_F_GPIO_OUT_SET_ALL_POS 0 /**< OUT_SET_ALL Position */ +#define MXC_F_GPIO_OUT_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_SET_ALL_POS)) /**< OUT_SET_ALL Mask */ +#define MXC_V_GPIO_OUT_SET_ALL_NO ((uint32_t)0x0UL) /**< OUT_SET_ALL_NO Value */ +#define MXC_S_GPIO_OUT_SET_ALL_NO (MXC_V_GPIO_OUT_SET_ALL_NO << MXC_F_GPIO_OUT_SET_ALL_POS) /**< OUT_SET_ALL_NO Setting */ +#define MXC_V_GPIO_OUT_SET_ALL_SET ((uint32_t)0x1UL) /**< OUT_SET_ALL_SET Value */ +#define MXC_S_GPIO_OUT_SET_ALL_SET (MXC_V_GPIO_OUT_SET_ALL_SET << MXC_F_GPIO_OUT_SET_ALL_POS) /**< OUT_SET_ALL_SET Setting */ + +/**@} end of group GPIO_OUT_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_OUT_CLR GPIO_OUT_CLR + * @brief GPIO Output Clear. Writing a 1 to one or more bits in this register clears the + * bits in the same positions in GPIO_OUT to 0, without affecting other bits in + * that register. + * @{ + */ +#define MXC_F_GPIO_OUT_CLR_ALL_POS 0 /**< OUT_CLR_ALL Position */ +#define MXC_F_GPIO_OUT_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_OUT_CLR_ALL_POS)) /**< OUT_CLR_ALL Mask */ + +/**@} end of group GPIO_OUT_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_IN GPIO_IN + * @brief GPIO Input Register. Read-only register to read from the logic states of the + * GPIO pins on this port. + * @{ + */ +#define MXC_F_GPIO_IN_ALL_POS 0 /**< IN_ALL Position */ +#define MXC_F_GPIO_IN_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_IN_ALL_POS)) /**< IN_ALL Mask */ + +/**@} end of group GPIO_IN_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INTMODE GPIO_INTMODE + * @brief GPIO Interrupt Mode Register. Each bit in this register controls the interrupt + * mode setting for the associated GPIO pin on this port. + * @{ + */ +#define MXC_F_GPIO_INTMODE_ALL_POS 0 /**< INTMODE_ALL Position */ +#define MXC_F_GPIO_INTMODE_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTMODE_ALL_POS)) /**< INTMODE_ALL Mask */ +#define MXC_V_GPIO_INTMODE_ALL_LEVEL ((uint32_t)0x0UL) /**< INTMODE_ALL_LEVEL Value */ +#define MXC_S_GPIO_INTMODE_ALL_LEVEL (MXC_V_GPIO_INTMODE_ALL_LEVEL << MXC_F_GPIO_INTMODE_ALL_POS) /**< INTMODE_ALL_LEVEL Setting */ +#define MXC_V_GPIO_INTMODE_ALL_EDGE ((uint32_t)0x1UL) /**< INTMODE_ALL_EDGE Value */ +#define MXC_S_GPIO_INTMODE_ALL_EDGE (MXC_V_GPIO_INTMODE_ALL_EDGE << MXC_F_GPIO_INTMODE_ALL_POS) /**< INTMODE_ALL_EDGE Setting */ + +/**@} end of group GPIO_INTMODE_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INTPOL GPIO_INTPOL + * @brief GPIO Interrupt Polarity Register. Each bit in this register controls the + * interrupt polarity setting for one GPIO pin in the associated port. + * @{ + */ +#define MXC_F_GPIO_INTPOL_ALL_POS 0 /**< INTPOL_ALL Position */ +#define MXC_F_GPIO_INTPOL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTPOL_ALL_POS)) /**< INTPOL_ALL Mask */ +#define MXC_V_GPIO_INTPOL_ALL_FALLING ((uint32_t)0x0UL) /**< INTPOL_ALL_FALLING Value */ +#define MXC_S_GPIO_INTPOL_ALL_FALLING (MXC_V_GPIO_INTPOL_ALL_FALLING << MXC_F_GPIO_INTPOL_ALL_POS) /**< INTPOL_ALL_FALLING Setting */ +#define MXC_V_GPIO_INTPOL_ALL_RISING ((uint32_t)0x1UL) /**< INTPOL_ALL_RISING Value */ +#define MXC_S_GPIO_INTPOL_ALL_RISING (MXC_V_GPIO_INTPOL_ALL_RISING << MXC_F_GPIO_INTPOL_ALL_POS) /**< INTPOL_ALL_RISING Setting */ + +/**@} end of group GPIO_INTPOL_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INTEN GPIO_INTEN + * @brief GPIO Interrupt Enable Register. Each bit in this register controls the GPIO + * interrupt enable for the associated pin on the GPIO port. + * @{ + */ +#define MXC_F_GPIO_INTEN_ALL_POS 0 /**< INTEN_ALL Position */ +#define MXC_F_GPIO_INTEN_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTEN_ALL_POS)) /**< INTEN_ALL Mask */ +#define MXC_V_GPIO_INTEN_ALL_DIS ((uint32_t)0x0UL) /**< INTEN_ALL_DIS Value */ +#define MXC_S_GPIO_INTEN_ALL_DIS (MXC_V_GPIO_INTEN_ALL_DIS << MXC_F_GPIO_INTEN_ALL_POS) /**< INTEN_ALL_DIS Setting */ +#define MXC_V_GPIO_INTEN_ALL_EN ((uint32_t)0x1UL) /**< INTEN_ALL_EN Value */ +#define MXC_S_GPIO_INTEN_ALL_EN (MXC_V_GPIO_INTEN_ALL_EN << MXC_F_GPIO_INTEN_ALL_POS) /**< INTEN_ALL_EN Setting */ + +/**@} end of group GPIO_INTEN_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INTEN_SET GPIO_INTEN_SET + * @brief GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets + * the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits + * in that register. + * @{ + */ +#define MXC_F_GPIO_INTEN_SET_ALL_POS 0 /**< INTEN_SET_ALL Position */ +#define MXC_F_GPIO_INTEN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTEN_SET_ALL_POS)) /**< INTEN_SET_ALL Mask */ +#define MXC_V_GPIO_INTEN_SET_ALL_NO ((uint32_t)0x0UL) /**< INTEN_SET_ALL_NO Value */ +#define MXC_S_GPIO_INTEN_SET_ALL_NO (MXC_V_GPIO_INTEN_SET_ALL_NO << MXC_F_GPIO_INTEN_SET_ALL_POS) /**< INTEN_SET_ALL_NO Setting */ +#define MXC_V_GPIO_INTEN_SET_ALL_SET ((uint32_t)0x1UL) /**< INTEN_SET_ALL_SET Value */ +#define MXC_S_GPIO_INTEN_SET_ALL_SET (MXC_V_GPIO_INTEN_SET_ALL_SET << MXC_F_GPIO_INTEN_SET_ALL_POS) /**< INTEN_SET_ALL_SET Setting */ + +/**@} end of group GPIO_INTEN_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INTEN_CLR GPIO_INTEN_CLR + * @brief GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register + * clears the bits in the same positions in GPIO_INT_EN to 0, without affecting + * other bits in that register. + * @{ + */ +#define MXC_F_GPIO_INTEN_CLR_ALL_POS 0 /**< INTEN_CLR_ALL Position */ +#define MXC_F_GPIO_INTEN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTEN_CLR_ALL_POS)) /**< INTEN_CLR_ALL Mask */ +#define MXC_V_GPIO_INTEN_CLR_ALL_NO ((uint32_t)0x0UL) /**< INTEN_CLR_ALL_NO Value */ +#define MXC_S_GPIO_INTEN_CLR_ALL_NO (MXC_V_GPIO_INTEN_CLR_ALL_NO << MXC_F_GPIO_INTEN_CLR_ALL_POS) /**< INTEN_CLR_ALL_NO Setting */ +#define MXC_V_GPIO_INTEN_CLR_ALL_CLEAR ((uint32_t)0x1UL) /**< INTEN_CLR_ALL_CLEAR Value */ +#define MXC_S_GPIO_INTEN_CLR_ALL_CLEAR (MXC_V_GPIO_INTEN_CLR_ALL_CLEAR << MXC_F_GPIO_INTEN_CLR_ALL_POS) /**< INTEN_CLR_ALL_CLEAR Setting */ + +/**@} end of group GPIO_INTEN_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INTFL GPIO_INTFL + * @brief GPIO Interrupt Status Register. Each bit in this register contains the pending + * interrupt status for the associated GPIO pin in this port. + * @{ + */ +#define MXC_F_GPIO_INTFL_ALL_POS 0 /**< INTFL_ALL Position */ +#define MXC_F_GPIO_INTFL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTFL_ALL_POS)) /**< INTFL_ALL Mask */ +#define MXC_V_GPIO_INTFL_ALL_NO ((uint32_t)0x0UL) /**< INTFL_ALL_NO Value */ +#define MXC_S_GPIO_INTFL_ALL_NO (MXC_V_GPIO_INTFL_ALL_NO << MXC_F_GPIO_INTFL_ALL_POS) /**< INTFL_ALL_NO Setting */ +#define MXC_V_GPIO_INTFL_ALL_PENDING ((uint32_t)0x1UL) /**< INTFL_ALL_PENDING Value */ +#define MXC_S_GPIO_INTFL_ALL_PENDING (MXC_V_GPIO_INTFL_ALL_PENDING << MXC_F_GPIO_INTFL_ALL_POS) /**< INTFL_ALL_PENDING Setting */ + +/**@} end of group GPIO_INTFL_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_INTFL_CLR GPIO_INTFL_CLR + * @brief GPIO Status Clear. Writing a 1 to one or more bits in this register clears the + * bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits + * in that register. + * @{ + */ +#define MXC_F_GPIO_INTFL_CLR_ALL_POS 0 /**< INTFL_CLR_ALL Position */ +#define MXC_F_GPIO_INTFL_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_INTFL_CLR_ALL_POS)) /**< INTFL_CLR_ALL Mask */ + +/**@} end of group GPIO_INTFL_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_WKEN GPIO_WKEN + * @brief GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup + * enable for the associated GPIO pin in this port. + * @{ + */ +#define MXC_F_GPIO_WKEN_ALL_POS 0 /**< WKEN_ALL Position */ +#define MXC_F_GPIO_WKEN_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WKEN_ALL_POS)) /**< WKEN_ALL Mask */ +#define MXC_V_GPIO_WKEN_ALL_DIS ((uint32_t)0x0UL) /**< WKEN_ALL_DIS Value */ +#define MXC_S_GPIO_WKEN_ALL_DIS (MXC_V_GPIO_WKEN_ALL_DIS << MXC_F_GPIO_WKEN_ALL_POS) /**< WKEN_ALL_DIS Setting */ +#define MXC_V_GPIO_WKEN_ALL_EN ((uint32_t)0x1UL) /**< WKEN_ALL_EN Value */ +#define MXC_S_GPIO_WKEN_ALL_EN (MXC_V_GPIO_WKEN_ALL_EN << MXC_F_GPIO_WKEN_ALL_POS) /**< WKEN_ALL_EN Setting */ + +/**@} end of group GPIO_WKEN_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_WKEN_SET GPIO_WKEN_SET + * @brief GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the + * bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in + * that register. + * @{ + */ +#define MXC_F_GPIO_WKEN_SET_ALL_POS 0 /**< WKEN_SET_ALL Position */ +#define MXC_F_GPIO_WKEN_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WKEN_SET_ALL_POS)) /**< WKEN_SET_ALL Mask */ + +/**@} end of group GPIO_WKEN_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_WKEN_CLR GPIO_WKEN_CLR + * @brief GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears + * the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other + * bits in that register. + * @{ + */ +#define MXC_F_GPIO_WKEN_CLR_ALL_POS 0 /**< WKEN_CLR_ALL Position */ +#define MXC_F_GPIO_WKEN_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_WKEN_CLR_ALL_POS)) /**< WKEN_CLR_ALL Mask */ + +/**@} end of group GPIO_WKEN_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_DUALEDGE GPIO_DUALEDGE + * @brief GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual + * edge mode for the associated GPIO pin in this port. + * @{ + */ +#define MXC_F_GPIO_DUALEDGE_ALL_POS 0 /**< DUALEDGE_ALL Position */ +#define MXC_F_GPIO_DUALEDGE_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DUALEDGE_ALL_POS)) /**< DUALEDGE_ALL Mask */ +#define MXC_V_GPIO_DUALEDGE_ALL_NO ((uint32_t)0x0UL) /**< DUALEDGE_ALL_NO Value */ +#define MXC_S_GPIO_DUALEDGE_ALL_NO (MXC_V_GPIO_DUALEDGE_ALL_NO << MXC_F_GPIO_DUALEDGE_ALL_POS) /**< DUALEDGE_ALL_NO Setting */ +#define MXC_V_GPIO_DUALEDGE_ALL_EN ((uint32_t)0x1UL) /**< DUALEDGE_ALL_EN Value */ +#define MXC_S_GPIO_DUALEDGE_ALL_EN (MXC_V_GPIO_DUALEDGE_ALL_EN << MXC_F_GPIO_DUALEDGE_ALL_POS) /**< DUALEDGE_ALL_EN Setting */ + +/**@} end of group GPIO_DUALEDGE_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_PADCTRL0 GPIO_PADCTRL0 + * @brief GPIO Input Mode Config 0. Each bit in this register enables the weak pull-up for + * the associated GPIO pin in this port. + * @{ + */ +#define MXC_F_GPIO_PADCTRL0_ALL_POS 0 /**< PADCTRL0_ALL Position */ +#define MXC_F_GPIO_PADCTRL0_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PADCTRL0_ALL_POS)) /**< PADCTRL0_ALL Mask */ +#define MXC_V_GPIO_PADCTRL0_ALL_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL0_ALL_IMPEDANCE Value */ +#define MXC_S_GPIO_PADCTRL0_ALL_IMPEDANCE (MXC_V_GPIO_PADCTRL0_ALL_IMPEDANCE << MXC_F_GPIO_PADCTRL0_ALL_POS) /**< PADCTRL0_ALL_IMPEDANCE Setting */ +#define MXC_V_GPIO_PADCTRL0_ALL_PU ((uint32_t)0x1UL) /**< PADCTRL0_ALL_PU Value */ +#define MXC_S_GPIO_PADCTRL0_ALL_PU (MXC_V_GPIO_PADCTRL0_ALL_PU << MXC_F_GPIO_PADCTRL0_ALL_POS) /**< PADCTRL0_ALL_PU Setting */ +#define MXC_V_GPIO_PADCTRL0_ALL_PD ((uint32_t)0x2UL) /**< PADCTRL0_ALL_PD Value */ +#define MXC_S_GPIO_PADCTRL0_ALL_PD (MXC_V_GPIO_PADCTRL0_ALL_PD << MXC_F_GPIO_PADCTRL0_ALL_POS) /**< PADCTRL0_ALL_PD Setting */ + +/**@} end of group GPIO_PADCTRL0_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_PADCTRL1 GPIO_PADCTRL1 + * @brief GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for + * the associated GPIO pin in this port. + * @{ + */ +#define MXC_F_GPIO_PADCTRL1_ALL_POS 0 /**< PADCTRL1_ALL Position */ +#define MXC_F_GPIO_PADCTRL1_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PADCTRL1_ALL_POS)) /**< PADCTRL1_ALL Mask */ +#define MXC_V_GPIO_PADCTRL1_ALL_IMPEDANCE ((uint32_t)0x0UL) /**< PADCTRL1_ALL_IMPEDANCE Value */ +#define MXC_S_GPIO_PADCTRL1_ALL_IMPEDANCE (MXC_V_GPIO_PADCTRL1_ALL_IMPEDANCE << MXC_F_GPIO_PADCTRL1_ALL_POS) /**< PADCTRL1_ALL_IMPEDANCE Setting */ +#define MXC_V_GPIO_PADCTRL1_ALL_PU ((uint32_t)0x1UL) /**< PADCTRL1_ALL_PU Value */ +#define MXC_S_GPIO_PADCTRL1_ALL_PU (MXC_V_GPIO_PADCTRL1_ALL_PU << MXC_F_GPIO_PADCTRL1_ALL_POS) /**< PADCTRL1_ALL_PU Setting */ +#define MXC_V_GPIO_PADCTRL1_ALL_PD ((uint32_t)0x2UL) /**< PADCTRL1_ALL_PD Value */ +#define MXC_S_GPIO_PADCTRL1_ALL_PD (MXC_V_GPIO_PADCTRL1_ALL_PD << MXC_F_GPIO_PADCTRL1_ALL_POS) /**< PADCTRL1_ALL_PD Setting */ + +/**@} end of group GPIO_PADCTRL1_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN1 GPIO_EN1 + * @brief GPIO Alternate Function Enable Register. Each bit in this register selects + * between primary/secondary functions for the associated GPIO pin in this port. + * @{ + */ +#define MXC_F_GPIO_EN1_ALL_POS 0 /**< EN1_ALL Position */ +#define MXC_F_GPIO_EN1_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_ALL_POS)) /**< EN1_ALL Mask */ +#define MXC_V_GPIO_EN1_ALL_PRIMARY ((uint32_t)0x0UL) /**< EN1_ALL_PRIMARY Value */ +#define MXC_S_GPIO_EN1_ALL_PRIMARY (MXC_V_GPIO_EN1_ALL_PRIMARY << MXC_F_GPIO_EN1_ALL_POS) /**< EN1_ALL_PRIMARY Setting */ +#define MXC_V_GPIO_EN1_ALL_SECONDARY ((uint32_t)0x1UL) /**< EN1_ALL_SECONDARY Value */ +#define MXC_S_GPIO_EN1_ALL_SECONDARY (MXC_V_GPIO_EN1_ALL_SECONDARY << MXC_F_GPIO_EN1_ALL_POS) /**< EN1_ALL_SECONDARY Setting */ + +/**@} end of group GPIO_EN1_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN1_SET GPIO_EN1_SET + * @brief GPIO Alternate Function Set. Writing a 1 to one or more bits in this register + * sets the bits in the same positions in GPIO_EN1 to 1, without affecting other + * bits in that register. + * @{ + */ +#define MXC_F_GPIO_EN1_SET_ALL_POS 0 /**< EN1_SET_ALL Position */ +#define MXC_F_GPIO_EN1_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_SET_ALL_POS)) /**< EN1_SET_ALL Mask */ + +/**@} end of group GPIO_EN1_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN1_CLR GPIO_EN1_CLR + * @brief GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register + * clears the bits in the same positions in GPIO_EN1 to 0, without affecting other + * bits in that register. + * @{ + */ +#define MXC_F_GPIO_EN1_CLR_ALL_POS 0 /**< EN1_CLR_ALL Position */ +#define MXC_F_GPIO_EN1_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN1_CLR_ALL_POS)) /**< EN1_CLR_ALL Mask */ + +/**@} end of group GPIO_EN1_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN2 GPIO_EN2 + * @brief GPIO Alternate Function Enable Register. Each bit in this register selects + * between primary/secondary functions for the associated GPIO pin in this port. + * @{ + */ +#define MXC_F_GPIO_EN2_ALL_POS 0 /**< EN2_ALL Position */ +#define MXC_F_GPIO_EN2_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_ALL_POS)) /**< EN2_ALL Mask */ +#define MXC_V_GPIO_EN2_ALL_PRIMARY ((uint32_t)0x0UL) /**< EN2_ALL_PRIMARY Value */ +#define MXC_S_GPIO_EN2_ALL_PRIMARY (MXC_V_GPIO_EN2_ALL_PRIMARY << MXC_F_GPIO_EN2_ALL_POS) /**< EN2_ALL_PRIMARY Setting */ +#define MXC_V_GPIO_EN2_ALL_SECONDARY ((uint32_t)0x1UL) /**< EN2_ALL_SECONDARY Value */ +#define MXC_S_GPIO_EN2_ALL_SECONDARY (MXC_V_GPIO_EN2_ALL_SECONDARY << MXC_F_GPIO_EN2_ALL_POS) /**< EN2_ALL_SECONDARY Setting */ + +/**@} end of group GPIO_EN2_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN2_SET GPIO_EN2_SET + * @brief GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register + * sets the bits in the same positions in GPIO_EN2 to 1, without affecting other + * bits in that register. + * @{ + */ +#define MXC_F_GPIO_EN2_SET_ALL_POS 0 /**< EN2_SET_ALL Position */ +#define MXC_F_GPIO_EN2_SET_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_SET_ALL_POS)) /**< EN2_SET_ALL Mask */ + +/**@} end of group GPIO_EN2_SET_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_EN2_CLR GPIO_EN2_CLR + * @brief GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this + * register clears the bits in the same positions in GPIO_EN2 to 0, without + * affecting other bits in that register. + * @{ + */ +#define MXC_F_GPIO_EN2_CLR_ALL_POS 0 /**< EN2_CLR_ALL Position */ +#define MXC_F_GPIO_EN2_CLR_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_EN2_CLR_ALL_POS)) /**< EN2_CLR_ALL Mask */ + +/**@} end of group GPIO_EN2_CLR_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_HYSEN GPIO_HYSEN + * @brief GPIO Input Hysteresis Enable. + * @{ + */ +#define MXC_F_GPIO_HYSEN_ALL_POS 0 /**< HYSEN_ALL Position */ +#define MXC_F_GPIO_HYSEN_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_HYSEN_ALL_POS)) /**< HYSEN_ALL Mask */ + +/**@} end of group GPIO_HYSEN_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_SRSEL GPIO_SRSEL + * @brief GPIO Slew Rate Enable Register. + * @{ + */ +#define MXC_F_GPIO_SRSEL_ALL_POS 0 /**< SRSEL_ALL Position */ +#define MXC_F_GPIO_SRSEL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_SRSEL_ALL_POS)) /**< SRSEL_ALL Mask */ +#define MXC_V_GPIO_SRSEL_ALL_FAST ((uint32_t)0x0UL) /**< SRSEL_ALL_FAST Value */ +#define MXC_S_GPIO_SRSEL_ALL_FAST (MXC_V_GPIO_SRSEL_ALL_FAST << MXC_F_GPIO_SRSEL_ALL_POS) /**< SRSEL_ALL_FAST Setting */ +#define MXC_V_GPIO_SRSEL_ALL_SLOW ((uint32_t)0x1UL) /**< SRSEL_ALL_SLOW Value */ +#define MXC_S_GPIO_SRSEL_ALL_SLOW (MXC_V_GPIO_SRSEL_ALL_SLOW << MXC_F_GPIO_SRSEL_ALL_POS) /**< SRSEL_ALL_SLOW Setting */ + +/**@} end of group GPIO_SRSEL_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_DS0 GPIO_DS0 + * @brief GPIO Drive Strength 0 Register. Each bit in this register selects the drive + * strength for the associated GPIO pin in this port. Refer to the Datasheet for + * sink/source current of GPIO pins in each mode. + * @{ + */ +#define MXC_F_GPIO_DS0_ALL_POS 0 /**< DS0_ALL Position */ +#define MXC_F_GPIO_DS0_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS0_ALL_POS)) /**< DS0_ALL Mask */ +#define MXC_V_GPIO_DS0_ALL_LD ((uint32_t)0x0UL) /**< DS0_ALL_LD Value */ +#define MXC_S_GPIO_DS0_ALL_LD (MXC_V_GPIO_DS0_ALL_LD << MXC_F_GPIO_DS0_ALL_POS) /**< DS0_ALL_LD Setting */ +#define MXC_V_GPIO_DS0_ALL_HD ((uint32_t)0x1UL) /**< DS0_ALL_HD Value */ +#define MXC_S_GPIO_DS0_ALL_HD (MXC_V_GPIO_DS0_ALL_HD << MXC_F_GPIO_DS0_ALL_POS) /**< DS0_ALL_HD Setting */ + +/**@} end of group GPIO_DS0_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_DS1 GPIO_DS1 + * @brief GPIO Drive Strength 1 Register. Each bit in this register selects the drive + * strength for the associated GPIO pin in this port. Refer to the Datasheet for + * sink/source current of GPIO pins in each mode. + * @{ + */ +#define MXC_F_GPIO_DS1_ALL_POS 0 /**< DS1_ALL Position */ +#define MXC_F_GPIO_DS1_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_DS1_ALL_POS)) /**< DS1_ALL Mask */ + +/**@} end of group GPIO_DS1_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_PSSEL GPIO_PSSEL + * @brief GPIO Pull Select Mode. + * @{ + */ +#define MXC_F_GPIO_PSSEL_ALL_POS 0 /**< PSSEL_ALL Position */ +#define MXC_F_GPIO_PSSEL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_PSSEL_ALL_POS)) /**< PSSEL_ALL Mask */ + +/**@} end of group GPIO_PSSEL_Register */ + +/** + * @ingroup gpio_registers + * @defgroup GPIO_VSSEL GPIO_VSSEL + * @brief GPIO Voltage Select. + * @{ + */ +#define MXC_F_GPIO_VSSEL_ALL_POS 0 /**< VSSEL_ALL Position */ +#define MXC_F_GPIO_VSSEL_ALL ((uint32_t)(0xFFFFFFFFUL << MXC_F_GPIO_VSSEL_ALL_POS)) /**< VSSEL_ALL Mask */ + +/**@} end of group GPIO_VSSEL_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_GPIO_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/i2c_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/i2c_regs.h new file mode 100644 index 00000000000..aa4ae41c411 --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/i2c_regs.h @@ -0,0 +1,592 @@ +/** + * @file i2c_regs.h + * @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module. + * @note This file is @generated. + * @ingroup i2c_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_I2C_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_I2C_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup i2c + * @defgroup i2c_registers I2C_Registers + * @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module. + * @details Inter-Integrated Circuit. + */ + +/** + * @ingroup i2c_registers + * Structure type to access the I2C Registers. + */ +typedef struct { + __IO uint32_t ctrl; /**< \b 0x00: I2C CTRL Register */ + __IO uint32_t status; /**< \b 0x04: I2C STATUS Register */ + __IO uint32_t intfl0; /**< \b 0x08: I2C INTFL0 Register */ + __IO uint32_t inten0; /**< \b 0x0C: I2C INTEN0 Register */ + __IO uint32_t intfl1; /**< \b 0x10: I2C INTFL1 Register */ + __IO uint32_t inten1; /**< \b 0x14: I2C INTEN1 Register */ + __IO uint32_t fifolen; /**< \b 0x18: I2C FIFOLEN Register */ + __IO uint32_t rxctrl0; /**< \b 0x1C: I2C RXCTRL0 Register */ + __IO uint32_t rxctrl1; /**< \b 0x20: I2C RXCTRL1 Register */ + __IO uint32_t txctrl0; /**< \b 0x24: I2C TXCTRL0 Register */ + __IO uint32_t txctrl1; /**< \b 0x28: I2C TXCTRL1 Register */ + __IO uint32_t fifo; /**< \b 0x2C: I2C FIFO Register */ + __IO uint32_t mstctrl; /**< \b 0x30: I2C MSTCTRL Register */ + __IO uint32_t clklo; /**< \b 0x34: I2C CLKLO Register */ + __IO uint32_t clkhi; /**< \b 0x38: I2C CLKHI Register */ + __IO uint32_t hsclk; /**< \b 0x3C: I2C HSCLK Register */ + __IO uint32_t timeout; /**< \b 0x40: I2C TIMEOUT Register */ + __R uint32_t rsv_0x44; + __IO uint32_t dma; /**< \b 0x48: I2C DMA Register */ + union { + __IO uint32_t slave_multi[4]; /**< \b 0x4C: I2C SLAVE_MULTI Register */ + struct { + __IO uint32_t slave0; /**< \b 0x4C: I2C SLAVE0 Register */ + __IO uint32_t slave1; /**< \b 0x50: I2C SLAVE1 Register */ + __IO uint32_t slave2; /**< \b 0x54: I2C SLAVE2 Register */ + __IO uint32_t slave3; /**< \b 0x58: I2C SLAVE3 Register */ + }; + }; +} mxc_i2c_regs_t; + +/* Register offsets for module I2C */ +/** + * @ingroup i2c_registers + * @defgroup I2C_Register_Offsets Register Offsets + * @brief I2C Peripheral Register Offsets from the I2C Base Peripheral Address. + * @{ + */ +#define MXC_R_I2C_CTRL ((uint32_t)0x00000000UL) /**< Offset from I2C Base Address: 0x0000 */ +#define MXC_R_I2C_STATUS ((uint32_t)0x00000004UL) /**< Offset from I2C Base Address: 0x0004 */ +#define MXC_R_I2C_INTFL0 ((uint32_t)0x00000008UL) /**< Offset from I2C Base Address: 0x0008 */ +#define MXC_R_I2C_INTEN0 ((uint32_t)0x0000000CUL) /**< Offset from I2C Base Address: 0x000C */ +#define MXC_R_I2C_INTFL1 ((uint32_t)0x00000010UL) /**< Offset from I2C Base Address: 0x0010 */ +#define MXC_R_I2C_INTEN1 ((uint32_t)0x00000014UL) /**< Offset from I2C Base Address: 0x0014 */ +#define MXC_R_I2C_FIFOLEN ((uint32_t)0x00000018UL) /**< Offset from I2C Base Address: 0x0018 */ +#define MXC_R_I2C_RXCTRL0 ((uint32_t)0x0000001CUL) /**< Offset from I2C Base Address: 0x001C */ +#define MXC_R_I2C_RXCTRL1 ((uint32_t)0x00000020UL) /**< Offset from I2C Base Address: 0x0020 */ +#define MXC_R_I2C_TXCTRL0 ((uint32_t)0x00000024UL) /**< Offset from I2C Base Address: 0x0024 */ +#define MXC_R_I2C_TXCTRL1 ((uint32_t)0x00000028UL) /**< Offset from I2C Base Address: 0x0028 */ +#define MXC_R_I2C_FIFO ((uint32_t)0x0000002CUL) /**< Offset from I2C Base Address: 0x002C */ +#define MXC_R_I2C_MSTCTRL ((uint32_t)0x00000030UL) /**< Offset from I2C Base Address: 0x0030 */ +#define MXC_R_I2C_CLKLO ((uint32_t)0x00000034UL) /**< Offset from I2C Base Address: 0x0034 */ +#define MXC_R_I2C_CLKHI ((uint32_t)0x00000038UL) /**< Offset from I2C Base Address: 0x0038 */ +#define MXC_R_I2C_HSCLK ((uint32_t)0x0000003CUL) /**< Offset from I2C Base Address: 0x003C */ +#define MXC_R_I2C_TIMEOUT ((uint32_t)0x00000040UL) /**< Offset from I2C Base Address: 0x0040 */ +#define MXC_R_I2C_DMA ((uint32_t)0x00000048UL) /**< Offset from I2C Base Address: 0x0048 */ +#define MXC_R_I2C_SLAVE_MULTI ((uint32_t)0x0000004CUL) /**< Offset from I2C Base Address: 0x004C */ +#define MXC_R_I2C_SLAVE0 ((uint32_t)0x0000004CUL) /**< Offset from I2C Base Address: 0x004C */ +#define MXC_R_I2C_SLAVE1 ((uint32_t)0x00000050UL) /**< Offset from I2C Base Address: 0x0050 */ +#define MXC_R_I2C_SLAVE2 ((uint32_t)0x00000054UL) /**< Offset from I2C Base Address: 0x0054 */ +#define MXC_R_I2C_SLAVE3 ((uint32_t)0x00000058UL) /**< Offset from I2C Base Address: 0x0058 */ +/**@} end of group i2c_registers */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_CTRL I2C_CTRL + * @brief Control Register0. + * @{ + */ +#define MXC_F_I2C_CTRL_EN_POS 0 /**< CTRL_EN Position */ +#define MXC_F_I2C_CTRL_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_EN_POS)) /**< CTRL_EN Mask */ + +#define MXC_F_I2C_CTRL_MST_MODE_POS 1 /**< CTRL_MST_MODE Position */ +#define MXC_F_I2C_CTRL_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_MST_MODE_POS)) /**< CTRL_MST_MODE Mask */ + +#define MXC_F_I2C_CTRL_GC_ADDR_EN_POS 2 /**< CTRL_GC_ADDR_EN Position */ +#define MXC_F_I2C_CTRL_GC_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_GC_ADDR_EN_POS)) /**< CTRL_GC_ADDR_EN Mask */ + +#define MXC_F_I2C_CTRL_IRXM_EN_POS 3 /**< CTRL_IRXM_EN Position */ +#define MXC_F_I2C_CTRL_IRXM_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_IRXM_EN_POS)) /**< CTRL_IRXM_EN Mask */ + +#define MXC_F_I2C_CTRL_IRXM_ACK_POS 4 /**< CTRL_IRXM_ACK Position */ +#define MXC_F_I2C_CTRL_IRXM_ACK ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_IRXM_ACK_POS)) /**< CTRL_IRXM_ACK Mask */ + +#define MXC_F_I2C_CTRL_SCL_OUT_POS 6 /**< CTRL_SCL_OUT Position */ +#define MXC_F_I2C_CTRL_SCL_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_OUT_POS)) /**< CTRL_SCL_OUT Mask */ + +#define MXC_F_I2C_CTRL_SDA_OUT_POS 7 /**< CTRL_SDA_OUT Position */ +#define MXC_F_I2C_CTRL_SDA_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_OUT_POS)) /**< CTRL_SDA_OUT Mask */ + +#define MXC_F_I2C_CTRL_SCL_POS 8 /**< CTRL_SCL Position */ +#define MXC_F_I2C_CTRL_SCL ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_POS)) /**< CTRL_SCL Mask */ + +#define MXC_F_I2C_CTRL_SDA_POS 9 /**< CTRL_SDA Position */ +#define MXC_F_I2C_CTRL_SDA ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_POS)) /**< CTRL_SDA Mask */ + +#define MXC_F_I2C_CTRL_BB_EN_POS 10 /**< CTRL_BB_EN Position */ +#define MXC_F_I2C_CTRL_BB_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_BB_EN_POS)) /**< CTRL_BB_EN Mask */ + +#define MXC_F_I2C_CTRL_READ_POS 11 /**< CTRL_READ Position */ +#define MXC_F_I2C_CTRL_READ ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_READ_POS)) /**< CTRL_READ Mask */ + +#define MXC_F_I2C_CTRL_CLKSTR_DIS_POS 12 /**< CTRL_CLKSTR_DIS Position */ +#define MXC_F_I2C_CTRL_CLKSTR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_CLKSTR_DIS_POS)) /**< CTRL_CLKSTR_DIS Mask */ + +#define MXC_F_I2C_CTRL_ONE_MST_MODE_POS 13 /**< CTRL_ONE_MST_MODE Position */ +#define MXC_F_I2C_CTRL_ONE_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_ONE_MST_MODE_POS)) /**< CTRL_ONE_MST_MODE Mask */ + +#define MXC_F_I2C_CTRL_HS_EN_POS 15 /**< CTRL_HS_EN Position */ +#define MXC_F_I2C_CTRL_HS_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_HS_EN_POS)) /**< CTRL_HS_EN Mask */ + +/**@} end of group I2C_CTRL_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_STATUS I2C_STATUS + * @brief Status Register. + * @{ + */ +#define MXC_F_I2C_STATUS_BUSY_POS 0 /**< STATUS_BUSY Position */ +#define MXC_F_I2C_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */ + +#define MXC_F_I2C_STATUS_RX_EM_POS 1 /**< STATUS_RX_EM Position */ +#define MXC_F_I2C_STATUS_RX_EM ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_EM_POS)) /**< STATUS_RX_EM Mask */ + +#define MXC_F_I2C_STATUS_RX_FULL_POS 2 /**< STATUS_RX_FULL Position */ +#define MXC_F_I2C_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */ + +#define MXC_F_I2C_STATUS_TX_EM_POS 3 /**< STATUS_TX_EM Position */ +#define MXC_F_I2C_STATUS_TX_EM ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_EM_POS)) /**< STATUS_TX_EM Mask */ + +#define MXC_F_I2C_STATUS_TX_FULL_POS 4 /**< STATUS_TX_FULL Position */ +#define MXC_F_I2C_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */ + +#define MXC_F_I2C_STATUS_MST_BUSY_POS 5 /**< STATUS_MST_BUSY Position */ +#define MXC_F_I2C_STATUS_MST_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_MST_BUSY_POS)) /**< STATUS_MST_BUSY Mask */ + +/**@} end of group I2C_STATUS_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_INTFL0 I2C_INTFL0 + * @brief Interrupt Status Register. + * @{ + */ +#define MXC_F_I2C_INTFL0_DONE_POS 0 /**< INTFL0_DONE Position */ +#define MXC_F_I2C_INTFL0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DONE_POS)) /**< INTFL0_DONE Mask */ + +#define MXC_F_I2C_INTFL0_IRXM_POS 1 /**< INTFL0_IRXM Position */ +#define MXC_F_I2C_INTFL0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_IRXM_POS)) /**< INTFL0_IRXM Mask */ + +#define MXC_F_I2C_INTFL0_GC_ADDR_MATCH_POS 2 /**< INTFL0_GC_ADDR_MATCH Position */ +#define MXC_F_I2C_INTFL0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_GC_ADDR_MATCH_POS)) /**< INTFL0_GC_ADDR_MATCH Mask */ + +#define MXC_F_I2C_INTFL0_ADDR_MATCH_POS 3 /**< INTFL0_ADDR_MATCH Position */ +#define MXC_F_I2C_INTFL0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADDR_MATCH_POS)) /**< INTFL0_ADDR_MATCH Mask */ + +#define MXC_F_I2C_INTFL0_RX_THD_POS 4 /**< INTFL0_RX_THD Position */ +#define MXC_F_I2C_INTFL0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_RX_THD_POS)) /**< INTFL0_RX_THD Mask */ + +#define MXC_F_I2C_INTFL0_TX_THD_POS 5 /**< INTFL0_TX_THD Position */ +#define MXC_F_I2C_INTFL0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TX_THD_POS)) /**< INTFL0_TX_THD Mask */ + +#define MXC_F_I2C_INTFL0_STOP_POS 6 /**< INTFL0_STOP Position */ +#define MXC_F_I2C_INTFL0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STOP_POS)) /**< INTFL0_STOP Mask */ + +#define MXC_F_I2C_INTFL0_ADDR_ACK_POS 7 /**< INTFL0_ADDR_ACK Position */ +#define MXC_F_I2C_INTFL0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADDR_ACK_POS)) /**< INTFL0_ADDR_ACK Mask */ + +#define MXC_F_I2C_INTFL0_ARB_ERR_POS 8 /**< INTFL0_ARB_ERR Position */ +#define MXC_F_I2C_INTFL0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ARB_ERR_POS)) /**< INTFL0_ARB_ERR Mask */ + +#define MXC_F_I2C_INTFL0_TO_ERR_POS 9 /**< INTFL0_TO_ERR Position */ +#define MXC_F_I2C_INTFL0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TO_ERR_POS)) /**< INTFL0_TO_ERR Mask */ + +#define MXC_F_I2C_INTFL0_ADDR_NACK_ERR_POS 10 /**< INTFL0_ADDR_NACK_ERR Position */ +#define MXC_F_I2C_INTFL0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADDR_NACK_ERR_POS)) /**< INTFL0_ADDR_NACK_ERR Mask */ + +#define MXC_F_I2C_INTFL0_DATA_ERR_POS 11 /**< INTFL0_DATA_ERR Position */ +#define MXC_F_I2C_INTFL0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DATA_ERR_POS)) /**< INTFL0_DATA_ERR Mask */ + +#define MXC_F_I2C_INTFL0_DNR_ERR_POS 12 /**< INTFL0_DNR_ERR Position */ +#define MXC_F_I2C_INTFL0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DNR_ERR_POS)) /**< INTFL0_DNR_ERR Mask */ + +#define MXC_F_I2C_INTFL0_START_ERR_POS 13 /**< INTFL0_START_ERR Position */ +#define MXC_F_I2C_INTFL0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_START_ERR_POS)) /**< INTFL0_START_ERR Mask */ + +#define MXC_F_I2C_INTFL0_STOP_ERR_POS 14 /**< INTFL0_STOP_ERR Position */ +#define MXC_F_I2C_INTFL0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STOP_ERR_POS)) /**< INTFL0_STOP_ERR Mask */ + +#define MXC_F_I2C_INTFL0_TX_LOCKOUT_POS 15 /**< INTFL0_TX_LOCKOUT Position */ +#define MXC_F_I2C_INTFL0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TX_LOCKOUT_POS)) /**< INTFL0_TX_LOCKOUT Mask */ + +#define MXC_F_I2C_INTFL0_MAMI_POS 16 /**< INTFL0_MAMI Position */ +#define MXC_F_I2C_INTFL0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_INTFL0_MAMI_POS)) /**< INTFL0_MAMI Mask */ + +#define MXC_F_I2C_INTFL0_RD_ADDR_MATCH_POS 22 /**< INTFL0_RD_ADDR_MATCH Position */ +#define MXC_F_I2C_INTFL0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_RD_ADDR_MATCH_POS)) /**< INTFL0_RD_ADDR_MATCH Mask */ + +#define MXC_F_I2C_INTFL0_WR_ADDR_MATCH_POS 23 /**< INTFL0_WR_ADDR_MATCH Position */ +#define MXC_F_I2C_INTFL0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_WR_ADDR_MATCH_POS)) /**< INTFL0_WR_ADDR_MATCH Mask */ + +/**@} end of group I2C_INTFL0_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_INTEN0 I2C_INTEN0 + * @brief Interrupt Enable Register. + * @{ + */ +#define MXC_F_I2C_INTEN0_DONE_POS 0 /**< INTEN0_DONE Position */ +#define MXC_F_I2C_INTEN0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DONE_POS)) /**< INTEN0_DONE Mask */ + +#define MXC_F_I2C_INTEN0_IRXM_POS 1 /**< INTEN0_IRXM Position */ +#define MXC_F_I2C_INTEN0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_IRXM_POS)) /**< INTEN0_IRXM Mask */ + +#define MXC_F_I2C_INTEN0_GC_ADDR_MATCH_POS 2 /**< INTEN0_GC_ADDR_MATCH Position */ +#define MXC_F_I2C_INTEN0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_GC_ADDR_MATCH_POS)) /**< INTEN0_GC_ADDR_MATCH Mask */ + +#define MXC_F_I2C_INTEN0_ADDR_MATCH_POS 3 /**< INTEN0_ADDR_MATCH Position */ +#define MXC_F_I2C_INTEN0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADDR_MATCH_POS)) /**< INTEN0_ADDR_MATCH Mask */ + +#define MXC_F_I2C_INTEN0_RX_THD_POS 4 /**< INTEN0_RX_THD Position */ +#define MXC_F_I2C_INTEN0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_RX_THD_POS)) /**< INTEN0_RX_THD Mask */ + +#define MXC_F_I2C_INTEN0_TX_THD_POS 5 /**< INTEN0_TX_THD Position */ +#define MXC_F_I2C_INTEN0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TX_THD_POS)) /**< INTEN0_TX_THD Mask */ + +#define MXC_F_I2C_INTEN0_STOP_POS 6 /**< INTEN0_STOP Position */ +#define MXC_F_I2C_INTEN0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOP_POS)) /**< INTEN0_STOP Mask */ + +#define MXC_F_I2C_INTEN0_ADDR_ACK_POS 7 /**< INTEN0_ADDR_ACK Position */ +#define MXC_F_I2C_INTEN0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADDR_ACK_POS)) /**< INTEN0_ADDR_ACK Mask */ + +#define MXC_F_I2C_INTEN0_ARB_ERR_POS 8 /**< INTEN0_ARB_ERR Position */ +#define MXC_F_I2C_INTEN0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ARB_ERR_POS)) /**< INTEN0_ARB_ERR Mask */ + +#define MXC_F_I2C_INTEN0_TO_ERR_POS 9 /**< INTEN0_TO_ERR Position */ +#define MXC_F_I2C_INTEN0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TO_ERR_POS)) /**< INTEN0_TO_ERR Mask */ + +#define MXC_F_I2C_INTEN0_ADDR_NACK_ERR_POS 10 /**< INTEN0_ADDR_NACK_ERR Position */ +#define MXC_F_I2C_INTEN0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADDR_NACK_ERR_POS)) /**< INTEN0_ADDR_NACK_ERR Mask */ + +#define MXC_F_I2C_INTEN0_DATA_ERR_POS 11 /**< INTEN0_DATA_ERR Position */ +#define MXC_F_I2C_INTEN0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DATA_ERR_POS)) /**< INTEN0_DATA_ERR Mask */ + +#define MXC_F_I2C_INTEN0_DNR_ERR_POS 12 /**< INTEN0_DNR_ERR Position */ +#define MXC_F_I2C_INTEN0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DNR_ERR_POS)) /**< INTEN0_DNR_ERR Mask */ + +#define MXC_F_I2C_INTEN0_START_ERR_POS 13 /**< INTEN0_START_ERR Position */ +#define MXC_F_I2C_INTEN0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_START_ERR_POS)) /**< INTEN0_START_ERR Mask */ + +#define MXC_F_I2C_INTEN0_STOP_ERR_POS 14 /**< INTEN0_STOP_ERR Position */ +#define MXC_F_I2C_INTEN0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOP_ERR_POS)) /**< INTEN0_STOP_ERR Mask */ + +#define MXC_F_I2C_INTEN0_TX_LOCKOUT_POS 15 /**< INTEN0_TX_LOCKOUT Position */ +#define MXC_F_I2C_INTEN0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TX_LOCKOUT_POS)) /**< INTEN0_TX_LOCKOUT Mask */ + +#define MXC_F_I2C_INTEN0_MAMI_POS 16 /**< INTEN0_MAMI Position */ +#define MXC_F_I2C_INTEN0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_INTEN0_MAMI_POS)) /**< INTEN0_MAMI Mask */ + +#define MXC_F_I2C_INTEN0_RD_ADDR_MATCH_POS 22 /**< INTEN0_RD_ADDR_MATCH Position */ +#define MXC_F_I2C_INTEN0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_RD_ADDR_MATCH_POS)) /**< INTEN0_RD_ADDR_MATCH Mask */ + +#define MXC_F_I2C_INTEN0_WR_ADDR_MATCH_POS 23 /**< INTEN0_WR_ADDR_MATCH Position */ +#define MXC_F_I2C_INTEN0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_WR_ADDR_MATCH_POS)) /**< INTEN0_WR_ADDR_MATCH Mask */ + +/**@} end of group I2C_INTEN0_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_INTFL1 I2C_INTFL1 + * @brief Interrupt Status Register 1. + * @{ + */ +#define MXC_F_I2C_INTFL1_RX_OV_POS 0 /**< INTFL1_RX_OV Position */ +#define MXC_F_I2C_INTFL1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_RX_OV_POS)) /**< INTFL1_RX_OV Mask */ + +#define MXC_F_I2C_INTFL1_TX_UN_POS 1 /**< INTFL1_TX_UN Position */ +#define MXC_F_I2C_INTFL1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_TX_UN_POS)) /**< INTFL1_TX_UN Mask */ + +#define MXC_F_I2C_INTFL1_START_POS 2 /**< INTFL1_START Position */ +#define MXC_F_I2C_INTFL1_START ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_START_POS)) /**< INTFL1_START Mask */ + +/**@} end of group I2C_INTFL1_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_INTEN1 I2C_INTEN1 + * @brief Interrupt Staus Register 1. + * @{ + */ +#define MXC_F_I2C_INTEN1_RX_OV_POS 0 /**< INTEN1_RX_OV Position */ +#define MXC_F_I2C_INTEN1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_RX_OV_POS)) /**< INTEN1_RX_OV Mask */ + +#define MXC_F_I2C_INTEN1_TX_UN_POS 1 /**< INTEN1_TX_UN Position */ +#define MXC_F_I2C_INTEN1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_TX_UN_POS)) /**< INTEN1_TX_UN Mask */ + +#define MXC_F_I2C_INTEN1_START_POS 2 /**< INTEN1_START Position */ +#define MXC_F_I2C_INTEN1_START ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_START_POS)) /**< INTEN1_START Mask */ + +/**@} end of group I2C_INTEN1_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_FIFOLEN I2C_FIFOLEN + * @brief FIFO Configuration Register. + * @{ + */ +#define MXC_F_I2C_FIFOLEN_RX_DEPTH_POS 0 /**< FIFOLEN_RX_DEPTH Position */ +#define MXC_F_I2C_FIFOLEN_RX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_FIFOLEN_RX_DEPTH_POS)) /**< FIFOLEN_RX_DEPTH Mask */ + +#define MXC_F_I2C_FIFOLEN_TX_DEPTH_POS 8 /**< FIFOLEN_TX_DEPTH Position */ +#define MXC_F_I2C_FIFOLEN_TX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_FIFOLEN_TX_DEPTH_POS)) /**< FIFOLEN_TX_DEPTH Mask */ + +/**@} end of group I2C_FIFOLEN_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_RXCTRL0 I2C_RXCTRL0 + * @brief Receive Control Register 0. + * @{ + */ +#define MXC_F_I2C_RXCTRL0_DNR_POS 0 /**< RXCTRL0_DNR Position */ +#define MXC_F_I2C_RXCTRL0_DNR ((uint32_t)(0x1UL << MXC_F_I2C_RXCTRL0_DNR_POS)) /**< RXCTRL0_DNR Mask */ + +#define MXC_F_I2C_RXCTRL0_FLUSH_POS 7 /**< RXCTRL0_FLUSH Position */ +#define MXC_F_I2C_RXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_RXCTRL0_FLUSH_POS)) /**< RXCTRL0_FLUSH Mask */ + +#define MXC_F_I2C_RXCTRL0_THD_LVL_POS 8 /**< RXCTRL0_THD_LVL Position */ +#define MXC_F_I2C_RXCTRL0_THD_LVL ((uint32_t)(0xFUL << MXC_F_I2C_RXCTRL0_THD_LVL_POS)) /**< RXCTRL0_THD_LVL Mask */ + +/**@} end of group I2C_RXCTRL0_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_RXCTRL1 I2C_RXCTRL1 + * @brief Receive Control Register 1. + * @{ + */ +#define MXC_F_I2C_RXCTRL1_CNT_POS 0 /**< RXCTRL1_CNT Position */ +#define MXC_F_I2C_RXCTRL1_CNT ((uint32_t)(0xFFUL << MXC_F_I2C_RXCTRL1_CNT_POS)) /**< RXCTRL1_CNT Mask */ + +#define MXC_F_I2C_RXCTRL1_LVL_POS 8 /**< RXCTRL1_LVL Position */ +#define MXC_F_I2C_RXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_RXCTRL1_LVL_POS)) /**< RXCTRL1_LVL Mask */ + +/**@} end of group I2C_RXCTRL1_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_TXCTRL0 I2C_TXCTRL0 + * @brief Transmit Control Register 0. + * @{ + */ +#define MXC_F_I2C_TXCTRL0_PRELOAD_MODE_POS 0 /**< TXCTRL0_PRELOAD_MODE Position */ +#define MXC_F_I2C_TXCTRL0_PRELOAD_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_PRELOAD_MODE_POS)) /**< TXCTRL0_PRELOAD_MODE Mask */ + +#define MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS 1 /**< TXCTRL0_TX_READY_MODE Position */ +#define MXC_F_I2C_TXCTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS)) /**< TXCTRL0_TX_READY_MODE Mask */ + +#define MXC_F_I2C_TXCTRL0_GC_ADDR_FLUSH_DIS_POS 2 /**< TXCTRL0_GC_ADDR_FLUSH_DIS Position */ +#define MXC_F_I2C_TXCTRL0_GC_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_GC_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_GC_ADDR_FLUSH_DIS Mask */ + +#define MXC_F_I2C_TXCTRL0_WR_ADDR_FLUSH_DIS_POS 3 /**< TXCTRL0_WR_ADDR_FLUSH_DIS Position */ +#define MXC_F_I2C_TXCTRL0_WR_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_WR_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_WR_ADDR_FLUSH_DIS Mask */ + +#define MXC_F_I2C_TXCTRL0_RD_ADDR_FLUSH_DIS_POS 4 /**< TXCTRL0_RD_ADDR_FLUSH_DIS Position */ +#define MXC_F_I2C_TXCTRL0_RD_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_RD_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_RD_ADDR_FLUSH_DIS Mask */ + +#define MXC_F_I2C_TXCTRL0_NACK_FLUSH_DIS_POS 5 /**< TXCTRL0_NACK_FLUSH_DIS Position */ +#define MXC_F_I2C_TXCTRL0_NACK_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_NACK_FLUSH_DIS_POS)) /**< TXCTRL0_NACK_FLUSH_DIS Mask */ + +#define MXC_F_I2C_TXCTRL0_FLUSH_POS 7 /**< TXCTRL0_FLUSH Position */ +#define MXC_F_I2C_TXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_FLUSH_POS)) /**< TXCTRL0_FLUSH Mask */ + +#define MXC_F_I2C_TXCTRL0_THD_VAL_POS 8 /**< TXCTRL0_THD_VAL Position */ +#define MXC_F_I2C_TXCTRL0_THD_VAL ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL0_THD_VAL_POS)) /**< TXCTRL0_THD_VAL Mask */ + +/**@} end of group I2C_TXCTRL0_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_TXCTRL1 I2C_TXCTRL1 + * @brief Transmit Control Register 1. + * @{ + */ +#define MXC_F_I2C_TXCTRL1_PRELOAD_RDY_POS 0 /**< TXCTRL1_PRELOAD_RDY Position */ +#define MXC_F_I2C_TXCTRL1_PRELOAD_RDY ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_PRELOAD_RDY_POS)) /**< TXCTRL1_PRELOAD_RDY Mask */ + +#define MXC_F_I2C_TXCTRL1_LAST_POS 1 /**< TXCTRL1_LAST Position */ +#define MXC_F_I2C_TXCTRL1_LAST ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_LAST_POS)) /**< TXCTRL1_LAST Mask */ + +#define MXC_F_I2C_TXCTRL1_LVL_POS 8 /**< TXCTRL1_LVL Position */ +#define MXC_F_I2C_TXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL1_LVL_POS)) /**< TXCTRL1_LVL Mask */ + +/**@} end of group I2C_TXCTRL1_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_FIFO I2C_FIFO + * @brief Data Register. + * @{ + */ +#define MXC_F_I2C_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ +#define MXC_F_I2C_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ + +/**@} end of group I2C_FIFO_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_MSTCTRL I2C_MSTCTRL + * @brief Master Control Register. + * @{ + */ +#define MXC_F_I2C_MSTCTRL_START_POS 0 /**< MSTCTRL_START Position */ +#define MXC_F_I2C_MSTCTRL_START ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_START_POS)) /**< MSTCTRL_START Mask */ + +#define MXC_F_I2C_MSTCTRL_RESTART_POS 1 /**< MSTCTRL_RESTART Position */ +#define MXC_F_I2C_MSTCTRL_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_RESTART_POS)) /**< MSTCTRL_RESTART Mask */ + +#define MXC_F_I2C_MSTCTRL_STOP_POS 2 /**< MSTCTRL_STOP Position */ +#define MXC_F_I2C_MSTCTRL_STOP ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_STOP_POS)) /**< MSTCTRL_STOP Mask */ + +#define MXC_F_I2C_MSTCTRL_EX_ADDR_EN_POS 7 /**< MSTCTRL_EX_ADDR_EN Position */ +#define MXC_F_I2C_MSTCTRL_EX_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_EX_ADDR_EN_POS)) /**< MSTCTRL_EX_ADDR_EN Mask */ + +#define MXC_F_I2C_MSTCTRL_CODE_POS 8 /**< MSTCTRL_CODE Position */ +#define MXC_F_I2C_MSTCTRL_CODE ((uint32_t)(0x7UL << MXC_F_I2C_MSTCTRL_CODE_POS)) /**< MSTCTRL_CODE Mask */ + +#define MXC_F_I2C_MSTCTRL_IGN_ACK_POS 12 /**< MSTCTRL_IGN_ACK Position */ +#define MXC_F_I2C_MSTCTRL_IGN_ACK ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_IGN_ACK_POS)) /**< MSTCTRL_IGN_ACK Mask */ + +/**@} end of group I2C_MSTCTRL_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_CLKLO I2C_CLKLO + * @brief Clock Low Register. + * @{ + */ +#define MXC_F_I2C_CLKLO_LO_POS 0 /**< CLKLO_LO Position */ +#define MXC_F_I2C_CLKLO_LO ((uint32_t)(0x1FFUL << MXC_F_I2C_CLKLO_LO_POS)) /**< CLKLO_LO Mask */ + +/**@} end of group I2C_CLKLO_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_CLKHI I2C_CLKHI + * @brief Clock high Register. + * @{ + */ +#define MXC_F_I2C_CLKHI_HI_POS 0 /**< CLKHI_HI Position */ +#define MXC_F_I2C_CLKHI_HI ((uint32_t)(0x1FFUL << MXC_F_I2C_CLKHI_HI_POS)) /**< CLKHI_HI Mask */ + +/**@} end of group I2C_CLKHI_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_HSCLK I2C_HSCLK + * @brief Clock high Register. + * @{ + */ +#define MXC_F_I2C_HSCLK_LO_POS 0 /**< HSCLK_LO Position */ +#define MXC_F_I2C_HSCLK_LO ((uint32_t)(0xFFUL << MXC_F_I2C_HSCLK_LO_POS)) /**< HSCLK_LO Mask */ + +#define MXC_F_I2C_HSCLK_HI_POS 8 /**< HSCLK_HI Position */ +#define MXC_F_I2C_HSCLK_HI ((uint32_t)(0xFFUL << MXC_F_I2C_HSCLK_HI_POS)) /**< HSCLK_HI Mask */ + +/**@} end of group I2C_HSCLK_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_TIMEOUT I2C_TIMEOUT + * @brief Timeout Register + * @{ + */ +#define MXC_F_I2C_TIMEOUT_SCL_TO_VAL_POS 0 /**< TIMEOUT_SCL_TO_VAL Position */ +#define MXC_F_I2C_TIMEOUT_SCL_TO_VAL ((uint32_t)(0xFFFFUL << MXC_F_I2C_TIMEOUT_SCL_TO_VAL_POS)) /**< TIMEOUT_SCL_TO_VAL Mask */ + +/**@} end of group I2C_TIMEOUT_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_DMA I2C_DMA + * @brief DMA Register. + * @{ + */ +#define MXC_F_I2C_DMA_TX_EN_POS 0 /**< DMA_TX_EN Position */ +#define MXC_F_I2C_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */ + +#define MXC_F_I2C_DMA_RX_EN_POS 1 /**< DMA_RX_EN Position */ +#define MXC_F_I2C_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */ + +/**@} end of group I2C_DMA_Register */ + +/** + * @ingroup i2c_registers + * @defgroup I2C_SLAVE_MULTI I2C_SLAVE_MULTI + * @brief Slave Address Register. + * @{ + */ +#define MXC_F_I2C_SLAVE_MULTI_ADDR_POS 0 /**< SLAVE_MULTI_ADDR Position */ +#define MXC_F_I2C_SLAVE_MULTI_ADDR ((uint32_t)(0x3FFUL << MXC_F_I2C_SLAVE_MULTI_ADDR_POS)) /**< SLAVE_MULTI_ADDR Mask */ + +#define MXC_F_I2C_SLAVE_MULTI_DIS_POS 10 /**< SLAVE_MULTI_DIS Position */ +#define MXC_F_I2C_SLAVE_MULTI_DIS ((uint32_t)(0x1UL << MXC_F_I2C_SLAVE_MULTI_DIS_POS)) /**< SLAVE_MULTI_DIS Mask */ + +#define MXC_F_I2C_SLAVE_MULTI_EXT_ADDR_EN_POS 15 /**< SLAVE_MULTI_EXT_ADDR_EN Position */ +#define MXC_F_I2C_SLAVE_MULTI_EXT_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_SLAVE_MULTI_EXT_ADDR_EN_POS)) /**< SLAVE_MULTI_EXT_ADDR_EN Mask */ + +/**@} end of group I2C_SLAVE_MULTI_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_I2C_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/i2s_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/i2s_regs.h new file mode 100644 index 00000000000..c211a8e56e0 --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/i2s_regs.h @@ -0,0 +1,293 @@ +/** + * @file i2s_regs.h + * @brief Registers, Bit Masks and Bit Positions for the I2S Peripheral Module. + * @note This file is @generated. + * @ingroup i2s_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_I2S_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_I2S_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup i2s + * @defgroup i2s_registers I2S_Registers + * @brief Registers, Bit Masks and Bit Positions for the I2S Peripheral Module. + * @details Inter-IC Sound Interface. + */ + +/** + * @ingroup i2s_registers + * Structure type to access the I2S Registers. + */ +typedef struct { + __IO uint32_t ctrl0ch0; /**< \b 0x00: I2S CTRL0CH0 Register */ + __R uint32_t rsv_0x4_0xf[3]; + __IO uint32_t ctrl1ch0; /**< \b 0x10: I2S CTRL1CH0 Register */ + __R uint32_t rsv_0x14_0x1f[3]; + __IO uint32_t filtch0; /**< \b 0x20: I2S FILTCH0 Register */ + __R uint32_t rsv_0x24_0x2f[3]; + __IO uint32_t dmach0; /**< \b 0x30: I2S DMACH0 Register */ + __R uint32_t rsv_0x34_0x3f[3]; + __IO uint32_t fifoch0; /**< \b 0x40: I2S FIFOCH0 Register */ + __R uint32_t rsv_0x44_0x4f[3]; + __IO uint32_t intfl; /**< \b 0x50: I2S INTFL Register */ + __IO uint32_t inten; /**< \b 0x54: I2S INTEN Register */ + __IO uint32_t extsetup; /**< \b 0x58: I2S EXTSETUP Register */ + __IO uint32_t wken; /**< \b 0x5C: I2S WKEN Register */ + __IO uint32_t wkfl; /**< \b 0x60: I2S WKFL Register */ +} mxc_i2s_regs_t; + +/* Register offsets for module I2S */ +/** + * @ingroup i2s_registers + * @defgroup I2S_Register_Offsets Register Offsets + * @brief I2S Peripheral Register Offsets from the I2S Base Peripheral Address. + * @{ + */ +#define MXC_R_I2S_CTRL0CH0 ((uint32_t)0x00000000UL) /**< Offset from I2S Base Address: 0x0000 */ +#define MXC_R_I2S_CTRL1CH0 ((uint32_t)0x00000010UL) /**< Offset from I2S Base Address: 0x0010 */ +#define MXC_R_I2S_FILTCH0 ((uint32_t)0x00000020UL) /**< Offset from I2S Base Address: 0x0020 */ +#define MXC_R_I2S_DMACH0 ((uint32_t)0x00000030UL) /**< Offset from I2S Base Address: 0x0030 */ +#define MXC_R_I2S_FIFOCH0 ((uint32_t)0x00000040UL) /**< Offset from I2S Base Address: 0x0040 */ +#define MXC_R_I2S_INTFL ((uint32_t)0x00000050UL) /**< Offset from I2S Base Address: 0x0050 */ +#define MXC_R_I2S_INTEN ((uint32_t)0x00000054UL) /**< Offset from I2S Base Address: 0x0054 */ +#define MXC_R_I2S_EXTSETUP ((uint32_t)0x00000058UL) /**< Offset from I2S Base Address: 0x0058 */ +#define MXC_R_I2S_WKEN ((uint32_t)0x0000005CUL) /**< Offset from I2S Base Address: 0x005C */ +#define MXC_R_I2S_WKFL ((uint32_t)0x00000060UL) /**< Offset from I2S Base Address: 0x0060 */ +/**@} end of group i2s_registers */ + +/** + * @ingroup i2s_registers + * @defgroup I2S_CTRL0CH0 I2S_CTRL0CH0 + * @brief Global mode channel. + * @{ + */ +#define MXC_F_I2S_CTRL0CH0_LSB_FIRST_POS 1 /**< CTRL0CH0_LSB_FIRST Position */ +#define MXC_F_I2S_CTRL0CH0_LSB_FIRST ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_LSB_FIRST_POS)) /**< CTRL0CH0_LSB_FIRST Mask */ + +#define MXC_F_I2S_CTRL0CH0_PDM_FILT_POS 2 /**< CTRL0CH0_PDM_FILT Position */ +#define MXC_F_I2S_CTRL0CH0_PDM_FILT ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_PDM_FILT_POS)) /**< CTRL0CH0_PDM_FILT Mask */ + +#define MXC_F_I2S_CTRL0CH0_PDM_EN_POS 3 /**< CTRL0CH0_PDM_EN Position */ +#define MXC_F_I2S_CTRL0CH0_PDM_EN ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_PDM_EN_POS)) /**< CTRL0CH0_PDM_EN Mask */ + +#define MXC_F_I2S_CTRL0CH0_USEDDR_POS 4 /**< CTRL0CH0_USEDDR Position */ +#define MXC_F_I2S_CTRL0CH0_USEDDR ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_USEDDR_POS)) /**< CTRL0CH0_USEDDR Mask */ + +#define MXC_F_I2S_CTRL0CH0_PDM_INV_POS 5 /**< CTRL0CH0_PDM_INV Position */ +#define MXC_F_I2S_CTRL0CH0_PDM_INV ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_PDM_INV_POS)) /**< CTRL0CH0_PDM_INV Mask */ + +#define MXC_F_I2S_CTRL0CH0_CH_MODE_POS 6 /**< CTRL0CH0_CH_MODE Position */ +#define MXC_F_I2S_CTRL0CH0_CH_MODE ((uint32_t)(0x3UL << MXC_F_I2S_CTRL0CH0_CH_MODE_POS)) /**< CTRL0CH0_CH_MODE Mask */ + +#define MXC_F_I2S_CTRL0CH0_WS_POL_POS 8 /**< CTRL0CH0_WS_POL Position */ +#define MXC_F_I2S_CTRL0CH0_WS_POL ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_WS_POL_POS)) /**< CTRL0CH0_WS_POL Mask */ + +#define MXC_F_I2S_CTRL0CH0_MSB_LOC_POS 9 /**< CTRL0CH0_MSB_LOC Position */ +#define MXC_F_I2S_CTRL0CH0_MSB_LOC ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_MSB_LOC_POS)) /**< CTRL0CH0_MSB_LOC Mask */ + +#define MXC_F_I2S_CTRL0CH0_ALIGN_POS 10 /**< CTRL0CH0_ALIGN Position */ +#define MXC_F_I2S_CTRL0CH0_ALIGN ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_ALIGN_POS)) /**< CTRL0CH0_ALIGN Mask */ + +#define MXC_F_I2S_CTRL0CH0_EXT_SEL_POS 11 /**< CTRL0CH0_EXT_SEL Position */ +#define MXC_F_I2S_CTRL0CH0_EXT_SEL ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_EXT_SEL_POS)) /**< CTRL0CH0_EXT_SEL Mask */ + +#define MXC_F_I2S_CTRL0CH0_STEREO_POS 12 /**< CTRL0CH0_STEREO Position */ +#define MXC_F_I2S_CTRL0CH0_STEREO ((uint32_t)(0x3UL << MXC_F_I2S_CTRL0CH0_STEREO_POS)) /**< CTRL0CH0_STEREO Mask */ + +#define MXC_F_I2S_CTRL0CH0_WSIZE_POS 14 /**< CTRL0CH0_WSIZE Position */ +#define MXC_F_I2S_CTRL0CH0_WSIZE ((uint32_t)(0x3UL << MXC_F_I2S_CTRL0CH0_WSIZE_POS)) /**< CTRL0CH0_WSIZE Mask */ + +#define MXC_F_I2S_CTRL0CH0_TX_EN_POS 16 /**< CTRL0CH0_TX_EN Position */ +#define MXC_F_I2S_CTRL0CH0_TX_EN ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_TX_EN_POS)) /**< CTRL0CH0_TX_EN Mask */ + +#define MXC_F_I2S_CTRL0CH0_RX_EN_POS 17 /**< CTRL0CH0_RX_EN Position */ +#define MXC_F_I2S_CTRL0CH0_RX_EN ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_RX_EN_POS)) /**< CTRL0CH0_RX_EN Mask */ + +#define MXC_F_I2S_CTRL0CH0_FLUSH_POS 18 /**< CTRL0CH0_FLUSH Position */ +#define MXC_F_I2S_CTRL0CH0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_FLUSH_POS)) /**< CTRL0CH0_FLUSH Mask */ + +#define MXC_F_I2S_CTRL0CH0_RST_POS 19 /**< CTRL0CH0_RST Position */ +#define MXC_F_I2S_CTRL0CH0_RST ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_RST_POS)) /**< CTRL0CH0_RST Mask */ + +#define MXC_F_I2S_CTRL0CH0_FIFO_LSB_POS 20 /**< CTRL0CH0_FIFO_LSB Position */ +#define MXC_F_I2S_CTRL0CH0_FIFO_LSB ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_FIFO_LSB_POS)) /**< CTRL0CH0_FIFO_LSB Mask */ + +#define MXC_F_I2S_CTRL0CH0_RX_THD_VAL_POS 24 /**< CTRL0CH0_RX_THD_VAL Position */ +#define MXC_F_I2S_CTRL0CH0_RX_THD_VAL ((uint32_t)(0xFFUL << MXC_F_I2S_CTRL0CH0_RX_THD_VAL_POS)) /**< CTRL0CH0_RX_THD_VAL Mask */ + +/**@} end of group I2S_CTRL0CH0_Register */ + +/** + * @ingroup i2s_registers + * @defgroup I2S_CTRL1CH0 I2S_CTRL1CH0 + * @brief Local channel Setup. + * @{ + */ +#define MXC_F_I2S_CTRL1CH0_BITS_WORD_POS 0 /**< CTRL1CH0_BITS_WORD Position */ +#define MXC_F_I2S_CTRL1CH0_BITS_WORD ((uint32_t)(0x1FUL << MXC_F_I2S_CTRL1CH0_BITS_WORD_POS)) /**< CTRL1CH0_BITS_WORD Mask */ + +#define MXC_F_I2S_CTRL1CH0_EN_POS 8 /**< CTRL1CH0_EN Position */ +#define MXC_F_I2S_CTRL1CH0_EN ((uint32_t)(0x1UL << MXC_F_I2S_CTRL1CH0_EN_POS)) /**< CTRL1CH0_EN Mask */ + +#define MXC_F_I2S_CTRL1CH0_SMP_SIZE_POS 9 /**< CTRL1CH0_SMP_SIZE Position */ +#define MXC_F_I2S_CTRL1CH0_SMP_SIZE ((uint32_t)(0x1FUL << MXC_F_I2S_CTRL1CH0_SMP_SIZE_POS)) /**< CTRL1CH0_SMP_SIZE Mask */ + +#define MXC_F_I2S_CTRL1CH0_CLKSEL_POS 14 /**< CTRL1CH0_CLKSEL Position */ +#define MXC_F_I2S_CTRL1CH0_CLKSEL ((uint32_t)(0x1UL << MXC_F_I2S_CTRL1CH0_CLKSEL_POS)) /**< CTRL1CH0_CLKSEL Mask */ + +#define MXC_F_I2S_CTRL1CH0_ADJUST_POS 15 /**< CTRL1CH0_ADJUST Position */ +#define MXC_F_I2S_CTRL1CH0_ADJUST ((uint32_t)(0x1UL << MXC_F_I2S_CTRL1CH0_ADJUST_POS)) /**< CTRL1CH0_ADJUST Mask */ + +#define MXC_F_I2S_CTRL1CH0_CLKDIV_POS 16 /**< CTRL1CH0_CLKDIV Position */ +#define MXC_F_I2S_CTRL1CH0_CLKDIV ((uint32_t)(0xFFFFUL << MXC_F_I2S_CTRL1CH0_CLKDIV_POS)) /**< CTRL1CH0_CLKDIV Mask */ + +/**@} end of group I2S_CTRL1CH0_Register */ + +/** + * @ingroup i2s_registers + * @defgroup I2S_DMACH0 I2S_DMACH0 + * @brief DMA Control. + * @{ + */ +#define MXC_F_I2S_DMACH0_DMA_TX_THD_VAL_POS 0 /**< DMACH0_DMA_TX_THD_VAL Position */ +#define MXC_F_I2S_DMACH0_DMA_TX_THD_VAL ((uint32_t)(0x7FUL << MXC_F_I2S_DMACH0_DMA_TX_THD_VAL_POS)) /**< DMACH0_DMA_TX_THD_VAL Mask */ + +#define MXC_F_I2S_DMACH0_DMA_TX_EN_POS 7 /**< DMACH0_DMA_TX_EN Position */ +#define MXC_F_I2S_DMACH0_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_I2S_DMACH0_DMA_TX_EN_POS)) /**< DMACH0_DMA_TX_EN Mask */ + +#define MXC_F_I2S_DMACH0_DMA_RX_THD_VAL_POS 8 /**< DMACH0_DMA_RX_THD_VAL Position */ +#define MXC_F_I2S_DMACH0_DMA_RX_THD_VAL ((uint32_t)(0x7FUL << MXC_F_I2S_DMACH0_DMA_RX_THD_VAL_POS)) /**< DMACH0_DMA_RX_THD_VAL Mask */ + +#define MXC_F_I2S_DMACH0_DMA_RX_EN_POS 15 /**< DMACH0_DMA_RX_EN Position */ +#define MXC_F_I2S_DMACH0_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_I2S_DMACH0_DMA_RX_EN_POS)) /**< DMACH0_DMA_RX_EN Mask */ + +#define MXC_F_I2S_DMACH0_TX_LVL_POS 16 /**< DMACH0_TX_LVL Position */ +#define MXC_F_I2S_DMACH0_TX_LVL ((uint32_t)(0xFFUL << MXC_F_I2S_DMACH0_TX_LVL_POS)) /**< DMACH0_TX_LVL Mask */ + +#define MXC_F_I2S_DMACH0_RX_LVL_POS 24 /**< DMACH0_RX_LVL Position */ +#define MXC_F_I2S_DMACH0_RX_LVL ((uint32_t)(0xFFUL << MXC_F_I2S_DMACH0_RX_LVL_POS)) /**< DMACH0_RX_LVL Mask */ + +/**@} end of group I2S_DMACH0_Register */ + +/** + * @ingroup i2s_registers + * @defgroup I2S_FIFOCH0 I2S_FIFOCH0 + * @brief I2S Fifo. + * @{ + */ +#define MXC_F_I2S_FIFOCH0_DATA_POS 0 /**< FIFOCH0_DATA Position */ +#define MXC_F_I2S_FIFOCH0_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_I2S_FIFOCH0_DATA_POS)) /**< FIFOCH0_DATA Mask */ + +/**@} end of group I2S_FIFOCH0_Register */ + +/** + * @ingroup i2s_registers + * @defgroup I2S_INTFL I2S_INTFL + * @brief ISR Status. + * @{ + */ +#define MXC_F_I2S_INTFL_RX_OV_CH0_POS 0 /**< INTFL_RX_OV_CH0 Position */ +#define MXC_F_I2S_INTFL_RX_OV_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_RX_OV_CH0_POS)) /**< INTFL_RX_OV_CH0 Mask */ + +#define MXC_F_I2S_INTFL_RX_THD_CH0_POS 1 /**< INTFL_RX_THD_CH0 Position */ +#define MXC_F_I2S_INTFL_RX_THD_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_RX_THD_CH0_POS)) /**< INTFL_RX_THD_CH0 Mask */ + +#define MXC_F_I2S_INTFL_TX_OB_CH0_POS 2 /**< INTFL_TX_OB_CH0 Position */ +#define MXC_F_I2S_INTFL_TX_OB_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_TX_OB_CH0_POS)) /**< INTFL_TX_OB_CH0 Mask */ + +#define MXC_F_I2S_INTFL_TX_HE_CH0_POS 3 /**< INTFL_TX_HE_CH0 Position */ +#define MXC_F_I2S_INTFL_TX_HE_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_TX_HE_CH0_POS)) /**< INTFL_TX_HE_CH0 Mask */ + +/**@} end of group I2S_INTFL_Register */ + +/** + * @ingroup i2s_registers + * @defgroup I2S_INTEN I2S_INTEN + * @brief Interrupt Enable. + * @{ + */ +#define MXC_F_I2S_INTEN_RX_OV_CH0_POS 0 /**< INTEN_RX_OV_CH0 Position */ +#define MXC_F_I2S_INTEN_RX_OV_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTEN_RX_OV_CH0_POS)) /**< INTEN_RX_OV_CH0 Mask */ + +#define MXC_F_I2S_INTEN_RX_THD_CH0_POS 1 /**< INTEN_RX_THD_CH0 Position */ +#define MXC_F_I2S_INTEN_RX_THD_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTEN_RX_THD_CH0_POS)) /**< INTEN_RX_THD_CH0 Mask */ + +#define MXC_F_I2S_INTEN_TX_OB_CH0_POS 2 /**< INTEN_TX_OB_CH0 Position */ +#define MXC_F_I2S_INTEN_TX_OB_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTEN_TX_OB_CH0_POS)) /**< INTEN_TX_OB_CH0 Mask */ + +#define MXC_F_I2S_INTEN_TX_HE_CH0_POS 3 /**< INTEN_TX_HE_CH0 Position */ +#define MXC_F_I2S_INTEN_TX_HE_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTEN_TX_HE_CH0_POS)) /**< INTEN_TX_HE_CH0 Mask */ + +/**@} end of group I2S_INTEN_Register */ + +/** + * @ingroup i2s_registers + * @defgroup I2S_EXTSETUP I2S_EXTSETUP + * @brief Ext Control. + * @{ + */ +#define MXC_F_I2S_EXTSETUP_EXT_BITS_WORD_POS 0 /**< EXTSETUP_EXT_BITS_WORD Position */ +#define MXC_F_I2S_EXTSETUP_EXT_BITS_WORD ((uint32_t)(0x1FUL << MXC_F_I2S_EXTSETUP_EXT_BITS_WORD_POS)) /**< EXTSETUP_EXT_BITS_WORD Mask */ + +/**@} end of group I2S_EXTSETUP_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_I2S_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/icc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/icc_regs.h new file mode 100644 index 00000000000..9ed18f4a4ef --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/icc_regs.h @@ -0,0 +1,158 @@ +/** + * @file icc_regs.h + * @brief Registers, Bit Masks and Bit Positions for the ICC Peripheral Module. + * @note This file is @generated. + * @ingroup icc_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_ICC_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_ICC_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup icc + * @defgroup icc_registers ICC_Registers + * @brief Registers, Bit Masks and Bit Positions for the ICC Peripheral Module. + * @details Instruction Cache Controller Registers + */ + +/** + * @ingroup icc_registers + * Structure type to access the ICC Registers. + */ +typedef struct { + __I uint32_t info; /**< \b 0x0000: ICC INFO Register */ + __I uint32_t sz; /**< \b 0x0004: ICC SZ Register */ + __R uint32_t rsv_0x8_0xff[62]; + __IO uint32_t ctrl; /**< \b 0x0100: ICC CTRL Register */ + __R uint32_t rsv_0x104_0x6ff[383]; + __IO uint32_t invalidate; /**< \b 0x0700: ICC INVALIDATE Register */ +} mxc_icc_regs_t; + +/* Register offsets for module ICC */ +/** + * @ingroup icc_registers + * @defgroup ICC_Register_Offsets Register Offsets + * @brief ICC Peripheral Register Offsets from the ICC Base Peripheral Address. + * @{ + */ +#define MXC_R_ICC_INFO ((uint32_t)0x00000000UL) /**< Offset from ICC Base Address: 0x0000 */ +#define MXC_R_ICC_SZ ((uint32_t)0x00000004UL) /**< Offset from ICC Base Address: 0x0004 */ +#define MXC_R_ICC_CTRL ((uint32_t)0x00000100UL) /**< Offset from ICC Base Address: 0x0100 */ +#define MXC_R_ICC_INVALIDATE ((uint32_t)0x00000700UL) /**< Offset from ICC Base Address: 0x0700 */ +/**@} end of group icc_registers */ + +/** + * @ingroup icc_registers + * @defgroup ICC_INFO ICC_INFO + * @brief Cache ID Register. + * @{ + */ +#define MXC_F_ICC_INFO_RELNUM_POS 0 /**< INFO_RELNUM Position */ +#define MXC_F_ICC_INFO_RELNUM ((uint32_t)(0x3FUL << MXC_F_ICC_INFO_RELNUM_POS)) /**< INFO_RELNUM Mask */ + +#define MXC_F_ICC_INFO_PARTNUM_POS 6 /**< INFO_PARTNUM Position */ +#define MXC_F_ICC_INFO_PARTNUM ((uint32_t)(0xFUL << MXC_F_ICC_INFO_PARTNUM_POS)) /**< INFO_PARTNUM Mask */ + +#define MXC_F_ICC_INFO_ID_POS 10 /**< INFO_ID Position */ +#define MXC_F_ICC_INFO_ID ((uint32_t)(0x3FUL << MXC_F_ICC_INFO_ID_POS)) /**< INFO_ID Mask */ + +/**@} end of group ICC_INFO_Register */ + +/** + * @ingroup icc_registers + * @defgroup ICC_SZ ICC_SZ + * @brief Memory Configuration Register. + * @{ + */ +#define MXC_F_ICC_SZ_CCH_POS 0 /**< SZ_CCH Position */ +#define MXC_F_ICC_SZ_CCH ((uint32_t)(0xFFFFUL << MXC_F_ICC_SZ_CCH_POS)) /**< SZ_CCH Mask */ + +#define MXC_F_ICC_SZ_MEM_POS 16 /**< SZ_MEM Position */ +#define MXC_F_ICC_SZ_MEM ((uint32_t)(0xFFFFUL << MXC_F_ICC_SZ_MEM_POS)) /**< SZ_MEM Mask */ + +/**@} end of group ICC_SZ_Register */ + +/** + * @ingroup icc_registers + * @defgroup ICC_CTRL ICC_CTRL + * @brief Cache Control and Status Register. + * @{ + */ +#define MXC_F_ICC_CTRL_EN_POS 0 /**< CTRL_EN Position */ +#define MXC_F_ICC_CTRL_EN ((uint32_t)(0x1UL << MXC_F_ICC_CTRL_EN_POS)) /**< CTRL_EN Mask */ + +#define MXC_F_ICC_CTRL_RDY_POS 16 /**< CTRL_RDY Position */ +#define MXC_F_ICC_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_ICC_CTRL_RDY_POS)) /**< CTRL_RDY Mask */ + +/**@} end of group ICC_CTRL_Register */ + +/** + * @ingroup icc_registers + * @defgroup ICC_INVALIDATE ICC_INVALIDATE + * @brief Invalidate All Registers. + * @{ + */ +#define MXC_F_ICC_INVALIDATE_INVALID_POS 0 /**< INVALIDATE_INVALID Position */ +#define MXC_F_ICC_INVALIDATE_INVALID ((uint32_t)(0xFFFFFFFFUL << MXC_F_ICC_INVALIDATE_INVALID_POS)) /**< INVALIDATE_INVALID Mask */ + +/**@} end of group ICC_INVALIDATE_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_ICC_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/lpcmp_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/lpcmp_regs.h new file mode 100644 index 00000000000..fd1c04b8994 --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/lpcmp_regs.h @@ -0,0 +1,117 @@ +/** + * @file lpcmp_regs.h + * @brief Registers, Bit Masks and Bit Positions for the LPCMP Peripheral Module. + * @note This file is @generated. + * @ingroup lpcmp_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_LPCMP_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_LPCMP_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup lpcmp + * @defgroup lpcmp_registers LPCMP_Registers + * @brief Registers, Bit Masks and Bit Positions for the LPCMP Peripheral Module. + * @details Low Power Comparator + */ + +/** + * @ingroup lpcmp_registers + * Structure type to access the LPCMP Registers. + */ +typedef struct { + __IO uint32_t ctrl[3]; /**< \b 0x00: LPCMP CTRL Register */ +} mxc_lpcmp_regs_t; + +/* Register offsets for module LPCMP */ +/** + * @ingroup lpcmp_registers + * @defgroup LPCMP_Register_Offsets Register Offsets + * @brief LPCMP Peripheral Register Offsets from the LPCMP Base Peripheral Address. + * @{ + */ +#define MXC_R_LPCMP_CTRL ((uint32_t)0x00000000UL) /**< Offset from LPCMP Base Address: 0x0000 */ +/**@} end of group lpcmp_registers */ + +/** + * @ingroup lpcmp_registers + * @defgroup LPCMP_CTRL LPCMP_CTRL + * @brief Comparator Control Register. + * @{ + */ +#define MXC_F_LPCMP_CTRL_EN_POS 0 /**< CTRL_EN Position */ +#define MXC_F_LPCMP_CTRL_EN ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_EN_POS)) /**< CTRL_EN Mask */ + +#define MXC_F_LPCMP_CTRL_POL_POS 5 /**< CTRL_POL Position */ +#define MXC_F_LPCMP_CTRL_POL ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_POL_POS)) /**< CTRL_POL Mask */ + +#define MXC_F_LPCMP_CTRL_INT_EN_POS 6 /**< CTRL_INT_EN Position */ +#define MXC_F_LPCMP_CTRL_INT_EN ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_INT_EN_POS)) /**< CTRL_INT_EN Mask */ + +#define MXC_F_LPCMP_CTRL_OUT_POS 14 /**< CTRL_OUT Position */ +#define MXC_F_LPCMP_CTRL_OUT ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_OUT_POS)) /**< CTRL_OUT Mask */ + +#define MXC_F_LPCMP_CTRL_INT_FL_POS 15 /**< CTRL_INT_FL Position */ +#define MXC_F_LPCMP_CTRL_INT_FL ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_INT_FL_POS)) /**< CTRL_INT_FL Mask */ + +/**@} end of group LPCMP_CTRL_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_LPCMP_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/lpgcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/lpgcr_regs.h new file mode 100644 index 00000000000..44381a1e7e3 --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/lpgcr_regs.h @@ -0,0 +1,149 @@ +/** + * @file lpgcr_regs.h + * @brief Registers, Bit Masks and Bit Positions for the LPGCR Peripheral Module. + * @note This file is @generated. + * @ingroup lpgcr_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_LPGCR_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_LPGCR_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup lpgcr + * @defgroup lpgcr_registers LPGCR_Registers + * @brief Registers, Bit Masks and Bit Positions for the LPGCR Peripheral Module. + * @details Low Power Global Control. + */ + +/** + * @ingroup lpgcr_registers + * Structure type to access the LPGCR Registers. + */ +typedef struct { + __R uint32_t rsv_0x0_0x7[2]; + __IO uint32_t rst; /**< \b 0x08: LPGCR RST Register */ + __IO uint32_t pclkdis; /**< \b 0x0C: LPGCR PCLKDIS Register */ +} mxc_lpgcr_regs_t; + +/* Register offsets for module LPGCR */ +/** + * @ingroup lpgcr_registers + * @defgroup LPGCR_Register_Offsets Register Offsets + * @brief LPGCR Peripheral Register Offsets from the LPGCR Base Peripheral Address. + * @{ + */ +#define MXC_R_LPGCR_RST ((uint32_t)0x00000008UL) /**< Offset from LPGCR Base Address: 0x0008 */ +#define MXC_R_LPGCR_PCLKDIS ((uint32_t)0x0000000CUL) /**< Offset from LPGCR Base Address: 0x000C */ +/**@} end of group lpgcr_registers */ + +/** + * @ingroup lpgcr_registers + * @defgroup LPGCR_RST LPGCR_RST + * @brief Low Power Reset Register. + * @{ + */ +#define MXC_F_LPGCR_RST_GPIO2_POS 0 /**< RST_GPIO2 Position */ +#define MXC_F_LPGCR_RST_GPIO2 ((uint32_t)(0x1UL << MXC_F_LPGCR_RST_GPIO2_POS)) /**< RST_GPIO2 Mask */ + +#define MXC_F_LPGCR_RST_WDT1_POS 1 /**< RST_WDT1 Position */ +#define MXC_F_LPGCR_RST_WDT1 ((uint32_t)(0x1UL << MXC_F_LPGCR_RST_WDT1_POS)) /**< RST_WDT1 Mask */ + +#define MXC_F_LPGCR_RST_TMR4_POS 2 /**< RST_TMR4 Position */ +#define MXC_F_LPGCR_RST_TMR4 ((uint32_t)(0x1UL << MXC_F_LPGCR_RST_TMR4_POS)) /**< RST_TMR4 Mask */ + +#define MXC_F_LPGCR_RST_TMR5_POS 3 /**< RST_TMR5 Position */ +#define MXC_F_LPGCR_RST_TMR5 ((uint32_t)(0x1UL << MXC_F_LPGCR_RST_TMR5_POS)) /**< RST_TMR5 Mask */ + +#define MXC_F_LPGCR_RST_UART3_POS 4 /**< RST_UART3 Position */ +#define MXC_F_LPGCR_RST_UART3 ((uint32_t)(0x1UL << MXC_F_LPGCR_RST_UART3_POS)) /**< RST_UART3 Mask */ + +#define MXC_F_LPGCR_RST_LPCOMP_POS 6 /**< RST_LPCOMP Position */ +#define MXC_F_LPGCR_RST_LPCOMP ((uint32_t)(0x1UL << MXC_F_LPGCR_RST_LPCOMP_POS)) /**< RST_LPCOMP Mask */ + +/**@} end of group LPGCR_RST_Register */ + +/** + * @ingroup lpgcr_registers + * @defgroup LPGCR_PCLKDIS LPGCR_PCLKDIS + * @brief Low Power Peripheral Clock Disable Register. + * @{ + */ +#define MXC_F_LPGCR_PCLKDIS_GPIO2_POS 0 /**< PCLKDIS_GPIO2 Position */ +#define MXC_F_LPGCR_PCLKDIS_GPIO2 ((uint32_t)(0x1UL << MXC_F_LPGCR_PCLKDIS_GPIO2_POS)) /**< PCLKDIS_GPIO2 Mask */ + +#define MXC_F_LPGCR_PCLKDIS_WDT1_POS 1 /**< PCLKDIS_WDT1 Position */ +#define MXC_F_LPGCR_PCLKDIS_WDT1 ((uint32_t)(0x1UL << MXC_F_LPGCR_PCLKDIS_WDT1_POS)) /**< PCLKDIS_WDT1 Mask */ + +#define MXC_F_LPGCR_PCLKDIS_TMR4_POS 2 /**< PCLKDIS_TMR4 Position */ +#define MXC_F_LPGCR_PCLKDIS_TMR4 ((uint32_t)(0x1UL << MXC_F_LPGCR_PCLKDIS_TMR4_POS)) /**< PCLKDIS_TMR4 Mask */ + +#define MXC_F_LPGCR_PCLKDIS_TMR5_POS 3 /**< PCLKDIS_TMR5 Position */ +#define MXC_F_LPGCR_PCLKDIS_TMR5 ((uint32_t)(0x1UL << MXC_F_LPGCR_PCLKDIS_TMR5_POS)) /**< PCLKDIS_TMR5 Mask */ + +#define MXC_F_LPGCR_PCLKDIS_UART3_POS 4 /**< PCLKDIS_UART3 Position */ +#define MXC_F_LPGCR_PCLKDIS_UART3 ((uint32_t)(0x1UL << MXC_F_LPGCR_PCLKDIS_UART3_POS)) /**< PCLKDIS_UART3 Mask */ + +#define MXC_F_LPGCR_PCLKDIS_LPCOMP_POS 6 /**< PCLKDIS_LPCOMP Position */ +#define MXC_F_LPGCR_PCLKDIS_LPCOMP ((uint32_t)(0x1UL << MXC_F_LPGCR_PCLKDIS_LPCOMP_POS)) /**< PCLKDIS_LPCOMP Mask */ + +/**@} end of group LPGCR_PCLKDIS_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_LPGCR_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd new file mode 100644 index 00000000000..6278f7f4a3a --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd @@ -0,0 +1,16641 @@ + + + Maxim-Integrated + Maxim + max32657 + ARMCM33 + 1.0 + TBD + + CM4 + r2p1 + little + true + true + 3 + false + + 8 + 32 + 0x20 + read-write + 0x00000000 + 0xFFFFFFFF + + + ADC + 10-bit Analog to Digital Converter + 0x40034000 + 32 + read-write + + 0 + 0x1000 + registers + + + ADC + ADC IRQ + 20 + + + + CTRL + ADC Control + 0x0000 + read-write + + + START + Start ADC Conversion + [0:0] + read-write + + + PWR + ADC Power Up + [1:1] + read-write + + + REBUF_PWR + ADC Reference Buffer Power Up + [3:3] + read-write + + + CHGPUMP_PWR + ADC Charge Pump Power Up + [4:4] + read-write + + + REF_SCALE + ADC Reference Scale + [8:8] + read-write + + + SCALE + ADC Scale + [9:9] + read-write + + + CLK_EN + ADC Clock Enable + [11:11] + read-write + + + CH_SEL + ADC Channel Select + [16:12] + read-write + + + AIN0 + 0 + + + AIN1 + 1 + + + AIN2 + 2 + + + AIN3 + 3 + + + AIN4 + 4 + + + AIN5 + 5 + + + AIN6 + 6 + + + AIN7 + 7 + + + VcoreA + 8 + + + VcoreB + 9 + + + Vrxout + 10 + + + Vtxout + 11 + + + VddA + 12 + + + VddB + VddB/4 + 13 + + + Vddio + Vddio/4 + 14 + + + Vddioh + Vddioh/4 + 15 + + + VregI + VregI/4 + 16 + + + + + DIVSEL + Scales the external inputs, all inputs are scaled the same + [18:17] + read-write + + + DIV1 + 0 + + + DIV2 + 1 + + + DIV3 + 2 + + + DIV4 + 3 + + + + + DATA_ALIGN + ADC Data Alignment Select + [20:20] + read-write + + + + + STATUS + ADC Status + 0x0004 + read-write + + + ACTIVE + ADC Conversion In Progress + [0:0] + read-only + + + AFE_PWR_UP_ACTIVE + AFE Power Up Delay Active + [2:2] + read-only + + + OVERFLOW + ADC Overflow + [3:3] + read-only + + + + + DATA + ADC Output Data + 0x0008 + read-write + + + DATA + ADC Converted Sample Data Output + [15:0] + read-only + + + + + INTR + ADC Interrupt Control Register + 0x000C + read-write + + + DONE_IE + ADC Done Interrupt Enable + [0:0] + read-write + + + REF_READY_IE + ADC Reference Ready Interrupt Enable + [1:1] + read-write + + + HI_LIMIT_IE + ADC Hi Limit Monitor Interrupt Enable + [2:2] + read-write + + + LO_LIMIT_IE + ADC Lo Limit Monitor Interrupt Enable + [3:3] + read-write + + + OVERFLOW_IE + ADC Overflow Interrupt Enable + [4:4] + read-write + + + DONE_IF + ADC Done Interrupt Flag + [16:16] + read-write + oneToClear + + + REF_READY_IF + ADC Reference Ready Interrupt Flag + [17:17] + read-write + oneToClear + + + HI_LIMIT_IF + ADC Hi Limit Monitor Interrupt Flag + [18:18] + read-write + oneToClear + + + LO_LIMIT_IF + ADC Lo Limit Monitor Interrupt Flag + [19:19] + read-write + oneToClear + + + OVERFLOW_IF + ADC Overflow Interrupt Flag + [20:20] + read-write + oneToClear + + + PENDING + ADC Interrupt Pending Status + [22:22] + read-only + + + + + 4 + 4 + LIMIT[%s] + ADC Limit + 0x0010 + read-write + + + CH_LO_LIMIT + Low Limit Threshold + [9:0] + read-write + + + CH_HI_LIMIT + High Limit Threshold + [21:12] + read-write + + + CH_SEL + ADC Channel Select + [27:24] + read-write + + + CH_LO_LIMIT_EN + Low Limit Monitoring Enable + [28:28] + read-write + + + CH_HI_LIMIT_EN + High Limit Monitoring Enable + [29:29] + read-write + + + + + DECCNT + ADC Decimation Count. + 0x0020 + read-write + + + DELAY + Delay. + [31:0] + read-write + + + + + + + + AESKEYS + AES Key Registers. + 0x40007800 + + 0x00 + 0x400 + registers + + + + KEY0 + AES Key 0. + 0x00 + 32 + + + KEY1 + AES Key 1. + 0x04 + 32 + + + KEY2 + AES Key 2. + 0x08 + 32 + + + KEY3 + AES Key 3. + 0x0C + 32 + + + KEY4 + AES Key 4. + 0x10 + 32 + + + KEY5 + AES Key 5. + 0x14 + 32 + + + KEY6 + AES Key 6. + 0x18 + 32 + + + KEY7 + AES Key 7. + 0x1C + 32 + + + + + + AES + AES Keys. + 0x40007400 + + 0x00 + 0x400 + registers + + + + CTRL + AES Control Register + 0x0000 + 32 + + + EN + AES Enable + [0:0] + read-write + + + DMA_RX_EN + DMA Request To Read Data Output FIFO + [1:1] + read-write + + + DMA_TX_EN + DMA Request To Write Data Input FIFO + [2:2] + read-write + + + START + Start AES Calculation + [3:3] + read-write + + + INPUT_FLUSH + Flush the data input FIFO + [4:4] + read-write + + + OUTPUT_FLUSH + Flush the data output FIFO + [5:5] + read-write + + + KEY_SIZE + Encryption Key Size + [7:6] + read-write + + + AES128 + 128 Bits. + 0 + + + AES192 + 192 Bits. + 1 + + + AES256 + 256 Bits. + 2 + + + + + TYPE + Encryption Type Selection + [9:8] + read-write + + + + + STATUS + AES Status Register + 0x0004 + + + BUSY + AES Busy Status + [0:0] + read-write + + + INPUT_EM + Data input FIFO empty status + [1:1] + read-write + + + INPUT_FULL + Data input FIFO full status + [2:2] + read-write + + + OUTPUT_EM + Data output FIFO empty status + [3:3] + read-write + + + OUTPUT_FULL + Data output FIFO full status + [4:4] + read-write + + + + + INTFL + AES Interrupt Flag Register + 0x0008 + + + DONE + AES Done Interrupt + [0:0] + read-write + + + KEY_CHANGE + External AES Key Changed Interrupt + [1:1] + read-write + + + KEY_ZERO + External AES Key Zero Interrupt + [2:2] + read-write + + + OV + Data Output FIFO Overrun Interrupt + [3:3] + read-write + + + KEY_ONE + KEY_ONE + [4:4] + read-write + + + + + INTEN + AES Interrupt Enable Register + 0x000C + + + DONE + AES Done Interrupt Enable + [0:0] + read-write + + + KEY_CHANGE + External AES Key Changed Interrupt Enable + [1:1] + read-write + + + KEY_ZERO + External AES Key Zero Interrupt Enable + [2:2] + read-write + + + OV + Data Output FIFO Overrun Interrupt Enable + [3:3] + read-write + + + KEY_ONE + KEY_ONE + [4:4] + read-write + + + + + FIFO + AES Data Register + 0x0010 + + + DATA + AES FIFO + [0:0] + read-write + + + + + + + + CRC + CRC Registers. + 0x4000F000 + + 0x00 + 0x1000 + registers + + + + CTRL + CRC Control + 0x0000 + 32 + + + EN + CRC Enable + [0:0] + read-write + + + DMA_EN + DMA Request Enable + [1:1] + read-write + + + MSB + MSB Select + [2:2] + read-write + + + BYTE_SWAP_IN + Byte Swap CRC Data Input + [3:3] + read-write + + + BYTE_SWAP_OUT + Byte Swap CRC Value Output + [4:4] + read-write + + + BUSY + CRC Busy + [16:16] + read-write + + + + + DATAIN32 + CRC Data Input + 0x0004 + + + DATA + CRC Data + [31:0] + read-write + + + + + 2 + 2 + DATAIN16[%s] + CRC Data Input + 0x0004 + 16 + read-write + + + DATA + CRC Data + 0 + 16 + read-write + + + + + 4 + 1 + DATAIN8[%s] + CRC Data Input + 0x0004 + 8 + read-write + + + DATA + CRC Data + 0 + 8 + read-write + + + + + POLY + CRC Polynomial + 0x0008 + + + POLY + CRC Polynomial + [31:0] + read-write + + + + + VAL + Current CRC Value + 0x000C + + + VALUE + Current CRC Value + [31:0] + read-write + + + + + + + + DMA + DMA Controller Fully programmable, chaining capable DMA channels. + 0x40028000 + 32 + + 0x00 + 0x1000 + registers + + + DMA0 + 28 + + + DMA1 + 29 + + + DMA2 + 30 + + + DMA3 + 31 + + + + INTEN + DMA Control Register. + 0x000 + + + CH0 + Channel 0 Interrupt Enable. + 0 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + CH1 + Channel 1 Interrupt Enable. + 1 + 1 + + + CH2 + Channel 2 Interrupt Enable. + 2 + 1 + + + CH3 + Channel 3 Interrupt Enable. + 3 + 1 + + + + + INTFL + DMA Interrupt Register. + 0x004 + read-only + + + CH0 + Channel Interrupt. To clear an interrupt, all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN. + 0 + 1 + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + CH1 + 1 + 1 + + + CH2 + 2 + 1 + + + CH3 + 3 + 1 + + + + + 4 + 0x20 + CH[%s] + DMA Channel registers. + dma_ch + 0x100 + read-write + + CTRL + DMA Channel Control Register. + 0x000 + + + EN + Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0. + 0 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + RLDEN + Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed. + 1 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + PRI + DMA Priority. + 2 + 2 + + + high + Highest Priority. + 0 + + + medHigh + Medium High Priority. + 1 + + + medLow + Medium Low Priority. + 2 + + + low + Lowest Priority. + 3 + + + + + REQUEST + Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active. + 4 + 6 + + + MEMTOMEM + Memory To Memory + 0x00 + + + SPI1RX + SPI1 RX + 0x01 + + + UART0RX + UART0 RX + 0x04 + + + UART1RX + UART1 RX + 0x05 + + + I2C0RX + I2C0 RX + 0x07 + + + I2C1RX + I2C1 RX + 0x08 + + + ADC + ADC + 0x09 + + + I2C2RX + I2C2 RX + 0x0A + + + UART2RX + UART2 RX + 0x0E + + + SPI0RX + SPI0 RX + 0x0F + + + AESRX + AES RX + 0x10 + + + UART3RX + UART3 RX + 0x1C + + + I2SRX + I2S RX + 0x1E + + + SPI1TX + SPI1 TX + 0x21 + + + UART0TX + UART0 TX + 0x24 + + + UART1TX + UART1 TX + 0x25 + + + I2C0TX + I2C0 TX + 0x27 + + + I2C1TX + I2C1 TX + 0x28 + + + I2C2TX + I2C2 TX + 0x2A + + + CRCTX + CRC TX + 0x2C + + + UART2TX + UART2 TX + 0x2E + + + SPI0TX + SPI0 TX + 0x2F + + + AESTX + AES TX + 0x30 + + + UART3TX + UART3 TX + 0x3C + + + I2STX + I2S TX + 0x3E + + + + + TO_WAIT + Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive. + 10 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + TO_PER + Timeout Period Select. + 11 + 3 + + + to4 + Timeout of 3 to 4 prescale clocks. + 0 + + + to8 + Timeout of 7 to 8 prescale clocks. + 1 + + + to16 + Timeout of 15 to 16 prescale clocks. + 2 + + + to32 + Timeout of 31 to 32 prescale clocks. + 3 + + + to64 + Timeout of 63 to 64 prescale clocks. + 4 + + + to128 + Timeout of 127 to 128 prescale clocks. + 5 + + + to256 + Timeout of 255 to 256 prescale clocks. + 6 + + + to512 + Timeout of 511 to 512 prescale clocks. + 7 + + + + + TO_CLKDIV + Pre-Scale Select. Selects the Pre-Scale divider for timer clock input. + 14 + 2 + + + dis + Disable timer. + 0 + + + div256 + hclk / 256. + 1 + + + div64k + hclk / 64k. + 2 + + + div16M + hclk / 16M. + 3 + + + + + SRCWD + Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value. + 16 + 2 + + + byte + Byte. + 0 + + + halfWord + Halfword. + 1 + + + word + Word. + 2 + + + + + SRCINC + Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals. + 18 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + DSTWD + Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width). + 20 + 2 + + + byte + Byte. + 0 + + + halfWord + Halfword. + 1 + + + word + Word. + 2 + + + + + DSTINC + Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals. + 22 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + BURST_SIZE + Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field. + 24 + 5 + + + DIS_IE + Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0. + 30 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + CTZ_IE + Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs. + 31 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + + + STATUS + DMA Channel Status Register. + 0x004 + + + STATUS + Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already). + 0 + 1 + read-only + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + IPEND + Channel Interrupt. + 1 + 1 + read-only + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + CTZ_IF + Count-to-Zero (CTZ) Interrupt Flag + 2 + 1 + oneToClear + + + RLD_IF + Reload Event Interrupt Flag. + 3 + 1 + oneToClear + + + BUS_ERR + Bus Error. Indicates that an AHB abort was received and the channel has been disabled. + 4 + 1 + oneToClear + + + TO_IF + Time-Out Event Interrupt Flag. + 6 + 1 + oneToClear + + + + + SRC + Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD. + 0x008 + + + ADDR + 0 + 32 + + + + + DST + Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD. + 0x00C + + + ADDR + 0 + 32 + + + + + CNT + DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered. + 0x010 + + + CNT + DMA Counter. + 0 + 24 + + + + + SRCRLD + Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition. + 0x014 + + + ADDR + Source Address Reload Value. + 0 + 31 + + + + + DSTRLD + Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition. + 0x018 + + + ADDR + Destination Address Reload Value. + 0 + 31 + + + + + CNTRLD + DMA Channel Count Reload Register. + 0x01C + + + CNT + Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition. + 0 + 24 + + + EN + Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs. + 31 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + + + + + + + DVS + Dynamic Voltage Scaling + DVS_ + 0x40003C00 + + 0x00 + 0x0030 + registers + + + DVS + Dynamic Voltage Scaling Interrupt + 83 + + + + CTL + Control Register + 0x00 + + + MON_ENA + Enable the DVS monitoring circuit + 0 + 1 + + + ADJ_ENA + Enable the power supply adjustment based on measurements + 1 + 1 + + + PS_FB_DIS + Power Supply Feedback Disable + 2 + 1 + + + CTRL_TAP_ENA + Use the TAP Select for automatic adjustment or monitoring + 3 + 1 + + + PROP_DLY + Additional delay to monitor lines + 4 + 2 + + + MON_ONESHOT + Measure delay once + 6 + 1 + + + GO_DIRECT + Operate in automatic mode or move directly + 7 + 1 + + + DIRECT_REG + Step incrementally to target voltage + 8 + 1 + + + PRIME_ENA + Include a delay line priming signal before monitoring + 9 + 1 + + + LIMIT_IE + Enable Limit Error Interrupt + 10 + 1 + + + RANGE_IE + Enable Range Error Interrupt + 11 + 1 + + + ADJ_IE + Enable Adjustment Error Interrupt + 12 + 1 + + + REF_SEL + Select TAP used for voltage adjustment + 13 + 4 + + + INC_VAL + Step size to increment voltage when in automatic mode + 17 + 3 + + + DVS_PS_APB_DIS + Prevent the application code from adjusting Vcore + 20 + 1 + + + DVS_HI_RANGE_ANY + Any high range signal from a delay line will cause a voltage adjustment + 21 + 1 + + + FB_TO_IE + Enable Voltage Adjustment Timeout Interrupt + 22 + 1 + + + FC_LV_IE + Enable Low Voltage Interrupt + 23 + 1 + + + PD_ACK_ENA + Prevent DVS from ack'ing a request to enter a low power mode until in the idle state + 24 + 1 + + + ADJ_ABORT + Causes the DVS to enter the idle state immediately on a request to enter a low power mode + 25 + 1 + + + + + STAT + Status Fields + 0x04 + 0x00000000 + + + DVS_STATE + State machine state + 0 + 4 + + + ADJ_UP_ENA + DVS Raising voltage + 4 + 1 + + + ADJ_DWN_ENA + DVS Lowering voltage + 5 + 1 + + + ADJ_ACTIVE + Adjustment to a Direct Voltage + 6 + 1 + + + CTR_TAP_OK + Tap Enabled and the Tap is withing Hi/Low limits + 7 + 1 + + + CTR_TAP_SEL + Status of selected center tap delay line detect output + 8 + 1 + + + SLOW_TRIP_DET + Provides the current combined status of all selected Low Range delay lines + 9 + 1 + + + FAST_TRIP_DET + Provides the current combined status of all selected High Range delay lines + 10 + 1 + + + PS_IN_RANGE + Indicates if the power supply is in range + 11 + 1 + + + PS_VCNTR + Voltage Count value sent to the power supply + 12 + 7 + + + MON_DLY_OK + Indicates the monitor delay count is at 0 + 19 + 1 + + + ADJ_DLY_OK + Indicates the adjustment delay count is at 0 + 20 + 1 + + + LO_LIMIT_DET + Power supply voltage counter is at low limit + 21 + 1 + + + HI_LIMIT_DET + Power supply voltage counter is at high limit + 22 + 1 + + + VALID_TAP + At least one delay line has been enabled + 23 + 1 + + + LIMIT_ERR + Interrupt flag that indicates a voltage count is at/beyond manufacturer limits + 24 + 1 + + + RANGE_ERR + Interrupt flag that indicates a tap has an invalid value + 25 + 1 + + + ADJ_ERR + Interrupt flag that indicates up and down adjustment requested simultaneously + 26 + 1 + + + REF_SEL_ERR + Indicates the ref select register bit is out of range + 27 + 1 + + + FB_TO_ERR + Interrupt flag that indicates a timeout while adjusting the voltage + 28 + 1 + + + FB_TO_ERR_S + Interrupt flag that mirror FB_TO_ERR and is write one clear + 29 + 1 + + + FC_LV_DET_INT + Interrupt flag that indicates the power supply voltage requested is below the low threshold + 30 + 1 + + + FC_LV_DET_S + Interrupt flag that mirrors FC_LV_DET_INT + 31 + 1 + + + + + DIRECT + Direct control of target voltage + 0x08 + + + VOLTAGE + Sets the target power supply value + 0 + 7 + + + + + MON + Monitor Delay + 0x00C + + + DLY + Number of prescaled clocks between delay line samples + 0 + 24 + + + PRE + Number of clocks before DVS_MON_DLY is decremented + 24 + 8 + + + + + ADJ_UP + Up Delay Register + 0x010 + + + DLY + Number of prescaled clocks between updates of the adjustment delay counter + 0 + 16 + + + PRE + Number of clocks before DVS_ADJ_UP_DLY is decremented + 16 + 8 + + + + + ADJ_DWN + Down Delay Register + 0x014 + + + DLY + Number of prescaled clocks between updates of the adjustment delay counter + 0 + 16 + + + PRE + Number of clocks before DVS_ADJ_DWN_DLY is decremented + 16 + 8 + + + + + THRES_CMP + Up Delay Register + 0x018 + + + VCNTR_THRES_CNT + Value used to determine 'low voltage' range + 0 + 7 + + + VCNTR_THRES_MASK + Mask applied to threshold and vcount to determine if the device is in a low voltage range + 8 + 7 + + + + + 5 + 4 + TAP_SEL[%s] + DVS Tap Select Register + 0x1C + + + LO + Select delay line tap for lower bound of auto adjustment + 0 + 5 + + + LO_TAP_STAT + Returns last delay line tap value + 5 + 1 + + + CTR_TAP_STAT + Returns last delay line tap value + 6 + 1 + + + HI_TAP_STAT + Returns last delay line tap value + 7 + 1 + + + HI + Selects delay line tap for high point of auto adjustment + 8 + 5 + + + CTR + Selects delay line tap for center point of auto adjustment + 16 + 5 + + + COARSE + Selects delay line tap for coarse or fixed delay portion of the line + 24 + 3 + + + DET_DLY + Number of HCLK between delay line launch and sampling + 29 + 2 + + + DELAY_ACT + Set if the delay is active + 31 + 1 + + + + + + + + FCR + Function Control Register. + 0x40000800 + + 0x00 + 0x400 + registers + + + + FCTRL0 + Register 0. + 0x00 + read-write + + + USBCLKSEL + USB External Core Clock Select. + 16 + 1 + + + sys + Generated clock from system clock. + 0 + + + dig + Digital clock from a GPIO. + 1 + + + + + I2C0DGEN0 + I2C0 SDA Glitch Filter Enable. + 20 + 1 + + + dis + Filter disabled. + 0 + + + en + Filter enabled. + 1 + + + + + I2C0DGEN1 + I2C0 SCL Glitch Filter Enable. + 21 + 1 + + + dis + Filter disabled. + 0 + + + en + Filter enabled. + 1 + + + + + I2C1DGEN0 + I2C1 SDA Glitch Filter Enable. + 22 + 1 + + + dis + Filter disabled. + 0 + + + en + Filter enabled. + 1 + + + + + I2C1DGEN1 + I2C1 SCL Glitch Filter Enable. + 23 + 1 + + + dis + Filter disabled. + 0 + + + en + Filter enabled. + 1 + + + + + I2C2ADGEN0 + I2C2 AF2 SDA Glitch Filter Enable. + 24 + 1 + + + dis + Filter disabled. + 0 + + + en + Filter enabled. + 1 + + + + + I2C2ADGEN1 + I2C2 AF2 SCL Glitch Filter Enable. + 25 + 1 + + + dis + Filter disabled. + 0 + + + en + Filter enabled. + 1 + + + + + I2C2BDGEN0 + I2C2 AF3 SDA Glitch Filter Enable. + 26 + 1 + + + dis + Filter disabled. + 0 + + + en + Filter enabled. + 1 + + + + + I2C2BDGEN1 + I2C2 AF3 SCL Glitch Filter Enable. + 27 + 1 + + + dis + Filter disabled. + 0 + + + en + Filter enabled. + 1 + + + + + I2C2CDGEN0 + I2C2 AF4 SDA Glitch Filter Enable + 28 + 1 + + + dis + Filter disabled. + 0 + + + en + Filter enabled. + 1 + + + + + I2C2CDGEN1 + I2C2 AF4 SCL Glitch Filter Enable + 29 + 1 + + + dis + Filter disabled. + 0 + + + en + Filter enabled. + 1 + + + + + + + FCTRL1 + Register 1. + 0x04 + read-write + + + AC_EN + Auto-calibration Enable. + 0 + 1 + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + AC_RUN + Autocalibration Run. + 1 + 1 + + + not + Not Running. + 0 + + + run + Running. + 1 + + + + + LOAD_TRIM + Load Trim. + 2 + 1 + + + GAIN_INV + Invert Gain. + 3 + 1 + + + not + Not Running. + 0 + + + run + Running. + 1 + + + + + ATOMIC + Atomic mode. + 4 + 1 + + + not + Not Running. + 0 + + + run + Running. + 1 + + + + + MU + MU value. + 8 + 12 + + + AC_TRIM + 150MHz HFIO Auto Calibration Trim + 23 + 9 + + + + + FCTRL2 + Register 2. + 0x08 + read-write + + + NFC_FWD_EN + Enabled FWD mode for NFC block + 0 + 1 + + + NFC_CLK_EN + Enabled the NFC blocks clock divider in Analog + 1 + 1 + + + NFC_FWD_TX_DATA_OVR + FWD input for NFC block + 2 + 1 + + + XO_EN_DGL + TBD + 3 + 1 + + + RX_BIAS_PD + Power down enable for NFC receiver analog block + 4 + 1 + + + RX_BIAS_EN + Enable the NFC receiver analog blocks + 5 + 1 + + + RX_TM_VBG_VABUS + TBD + 6 + 1 + + + RX_TM_BIAS + TBD + 7 + 1 + + + NFC_FWD_DOUT + FWD output from FNC block + 8 + 1 + + + + + FCTRL3 + Register 3. + 0x0C + read-write + + + DONECNT + Auto-calibration Done Counter Setting. + 0 + 8 + + + + + GP + General Purpose Register. + 0x1C + read-write + + + GP + General Purpose. + 0 + 32 + + + + + MSRTRIM + MSR Trim Register. + 0x20 + read-write + + + R1 + MSR Trim R1. + 0 + 2 + + + R2 + MSR Trim R2. + 2 + 3 + + + + + FLVFILT + Flash Low Voltage Filter Control Register. + 0x24 + read-write + + + NUM + Defines the number of consecutive samples of FLV status that must be good for ROM to continue. + 0 + 8 + + + RATE + Defines the rate for ROM sampling of the FLV status. + 8 + 8 + + + DELAY + Defines the delay from change in system clock divider until ROM begins filtering process of the FLV status. + 16 + 8 + + + + + + + + FLC + Flash Memory Control. + FLSH_ + 0x40029000 + + 0x00 + 0x400 + registers + + + Flash_Controller + Flash Controller interrupt. + 23 + + + + ADDR + Flash Write Address. + 0x00 + + + ADDR + Address for next operation. + 0 + 32 + + + + + CLKDIV + Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller. + 0x04 + 0x00000064 + + + CLKDIV + Flash Clock Divide. The clock is divided by this value to generate a 1MHz clock for flash controller. + 0 + 8 + + + + + CTRL + Flash Control Register. + 0x08 + + + WR + Write. This bit is automatically cleared after the operation. + 0 + 1 + + + complete + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + ME + Mass Erase. This bit is automatically cleared after the operation. + 1 + 1 + + + PGE + Page Erase. This bit is automatically cleared after the operation. + 2 + 1 + + + ERASE_CODE + Erase Code. The ERASE_CODE must be set up property before erase operation can be initiated. These bits are automatically cleared after the operation is complete. + 8 + 8 + + + nop + No operation. + 0 + + + erasePage + Enable Page Erase. + 0x55 + + + eraseAll + Enable Mass Erase. The debug port must be enabled. + 0xAA + + + + + PEND + Flash Pending. When Flash operation is in progress (busy), Flash reads and writes will fail. When PEND is set, write to all Flash registers, with exception of the Flash interrupt register, are ignored. + 24 + 1 + read-only + + + idle + Idle. + 0 + + + busy + Busy. + 1 + + + + + LVE + Low Voltage enable. + 25 + 1 + + + UNLOCK + Flash Unlock. The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed. + 28 + 4 + + + unlocked + Flash Unlocked. + 2 + + + locked + Flash Locked. + 3 + + + + + + + INTR + Flash Interrupt Register. + 0x024 + + + DONE_IF + Flash Done Interrupt. This bit is set to 1 upon Flash write or erase completion. + 0 + 1 + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + AF_IF + Flash Access Fail. This bit is set when an attempt is made to write the flash while the flash is busy or the flash is locked. This bit can only be set to 1 by hardware. + 1 + 1 + + + noError + No Failure. + 0 + + + error + Failure occurs. + 1 + + + + + DONE_IE + Flash Done Interrupt Enable. + 8 + 1 + + + disable + Disable. + 0 + + + enable + Enable. + 1 + + + + + AF_IE + 9 + 1 + + + + + ECCDATA + ECC Data Register. + 0x2C + + + EVEN + Error Correction Code Odd Data. + 0 + 9 + + + ODD + Error Correction Code Even Data. + 16 + 9 + + + + + 4 + 4 + DATA[%s] + Flash Write Data. + 0x30 + + + DATA + Data next operation. + 0 + 32 + + + + + ACTRL + Access Control Register. Writing the ACTRL register with the following values in the order shown, allows read and write access to the system and user Information block: + pflc-actrl = 0x3a7f5ca3; + pflc-actrl = 0xa1e34f20; + pflc-actrl = 0x9608b2c1. When unlocked, a write of any word will disable access to system and user information block. Readback of this register is always zero. + 0x40 + write-only + + + ACTRL + Access control. + 0 + 32 + + + + + WELR0 + WELR0 + 0x80 + + + WELR0 + Access control. + 0 + 32 + + + + + WELR1 + WELR1 + 0x88 + + + WELR1 + Access control. + 0 + 32 + + + + + RLR0 + RLR0 + 0x90 + + + RLR0 + Access control. + 0 + 32 + + + + + RLR1 + RLR1 + 0x98 + + + RLR1 + Access control. + 0 + 32 + + + + + + + + GCR + Global Control Registers. + 0x40000000 + + 0 + 0x400 + registers + + + + SYSCTRL + System Control. + 0x00 + 0xFFFFFFFE + + + BSTAP_EN + Boundary Scan TAP enable. When enabled, the JTAG port is connected to the Boundary Scan TAP. Otherwise, the port is connected to the ARM ICE function. This bit is reset by the POR. Reset value and access depend on the part number. + 0 + 1 + + + dis + Boundary Scan TAP port disabled. + 0 + + + en + Boundary Scan TAP port enabled. + 1 + + + + + SBUSARB + System bus abritration scheme. These bits are used to select between Fixed-burst abritration and Round-Robin scheme. The Round-Robin scheme is selected by default. These bits are reset by the system reset. + 1 + 2 + + + fix + Fixed Burst abritration. + 0 + + + round + Round-robin scheme. + 1 + + + + + FLASH_PAGE_FLIP + Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer. + 4 + 1 + + + normal + Physical layout matches logical layout. + 0 + + + swapped + Bottom half mapped to logical top half and vice versa. + 1 + + + + + FPU_DIS + Cortex M4 Floating Point Disable This bit is used to disable the floating-point unit of the Cortex-M4. + 5 + 1 + + + ICC_FLUSH + Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. + 6 + 1 + + + normal + Normal Code Cache Operation + 0 + + + flush + Code Caches and CPU instruction buffer are flushed + 1 + + + + + SRCC_FLUSH + Data Cache Flush. The system cache (s) will be flushed when this bit is set. + 7 + 1 + + + normal + Normal System Cache Operation + 0 + + + flush + System Cache is flushed + 1 + + + + + SRCC_DIS + Data Cache Disable. The system cache (s) will be completely disabled when this bit is set. + 9 + 1 + + + en + Is enabled. + 0 + + + dis + Is Disabled. + 1 + + + + + CHKRES1 + ROM1 Checksum Result. This bit is only valid when the checksum is done and CCHK1 bit is cleared.. + 11 + 1 + + + complete + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + CCHK1 + Compute ROM1 Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. + 12 + 1 + + + complete + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + CCHK0 + Compute ROM0 Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. + 13 + 1 + + + complete + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + CHKRES0 + ROM0 Checksum Result. This bit is only valid when the checksum is done and CCHK0 bit is cleared.. + 15 + 1 + + + pass + ROM Checksum Correct. + 0 + + + fail + ROM Checksum Fail. + 1 + + + + + OVR + Operating Voltage Range. + 16 + 2 + + + + + RST0 + Reset. + 0x04 + + + DMA + DMA Reset. + 0 + 1 + + + WDT0 + Watchdog Timer Reset. + 1 + 1 + + + GPIO0 + GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states. + 2 + 1 + + + GPIO1 + GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states. + 3 + 1 + + + TMR0 + Timer0 Reset. Setting this bit to 1 resets Timer 0 blocks. + 5 + 1 + + + TMR1 + Timer1 Reset. Setting this bit to 1 resets Timer 1 blocks. + 6 + 1 + + + TMR2 + Timer2 Reset. Setting this bit to 1 resets Timer 2 blocks. + 7 + 1 + + + TMR3 + Timer3 Reset. Setting this bit to 1 resets Timer 3 blocks. + 8 + 1 + + + TMR4 + Timer4 Reset. Setting this bit to 1 resets Timer 4 blocks. + 9 + 1 + + + TMR5 + Timer5 Reset. Setting this bit to 1 resets Timer 5 blocks. + 10 + 1 + + + UART0 + UART0 Reset. Setting this bit to 1 resets all UART 0 blocks. + 11 + 1 + + + UART1 + UART1 Reset. Setting this bit to 1 resets all UART 1 blocks. + 12 + 1 + + + SPI0 + SPI0 Reset. Setting this bit to 1 resets all SPI 0 blocks. + 13 + 1 + + + SPI1 + SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks. + 14 + 1 + + + SPI2 + SPI2 Reset. Setting this bit to 1 resets all SPI 2 blocks. + 15 + 1 + + + I2C0 + I2C0 Reset. + 16 + 1 + + + RTC + Real Time Clock Reset. + 17 + 1 + + + TMR6 + Timer6 Reset. Setting this bit to 1 resets Timer 6 blocks. + 20 + 1 + + + TMR7 + Timer7 Reset. Setting this bit to 1 resets Timer 7 blocks. + 21 + 1 + + + SEMA + Semaphore Reset. + 22 + 1 + + + TRNG + TODO(5-2-2023): Remove this bit before release. TRNG Reset. Setting this bit resets the TRNG block. + 24 + 1 + + + ADC + Analog to Digital Reset. + 26 + 1 + + + UART2 + UART2 Reset. Setting this bit to 1 resets all UART 2 blocks. + 28 + 1 + + + SOFT + Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer. + 29 + 1 + + + PERIPH + Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset. + 30 + 1 + + + SYS + System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer. + 31 + 1 + + + + + CLKCTRL + Clock Control. + 0x08 + 0x00000008 + + + PCLK_DIV + PCLK Divider. + 3 + 3 + + + div1 + Divide by 1. + 0 + + + div2 + Divide by 2. + 1 + + + div4 + Divide by 4. + 2 + + + div8 + Divide by 8. + 3 + + + + + SYSCLK_DIV + Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0. + 6 + 3 + + + div1 + Divide by 1. + 0 + + + div2 + Divide by 2. + 1 + + + div4 + Divide by 4. + 2 + + + div8 + Divide by 8. + 3 + + + div16 + Divide by 16. + 4 + + + div32 + Divide by 32. + 5 + + + div64 + Divide by 64. + 6 + + + div128 + Divide by 128. + 7 + + + + + SYSCLK_SEL + Clock Source Select. This 3 bit field selects the source for the system clock. + 9 + 3 + + + ISO + Internal Secondary Oscilatior Clock + 0 + + + ERFO + 27MHz Crystal is used for the system clock. + 2 + + + INRO + 8kHz Internal Nano Ring Oscillator is used for the system clock. + 3 + + + IPO + The internal Primary oscillator is used for the system clock. + 4 + + + IBRO + The internal Baud Rate oscillator is used for the system clock. + 5 + + + ERTCO + 32kHz is used for the system clock. + 6 + + + + + SYSCLK_RDY + Clock Ready. This read only bit reflects whether the currently selected system clock source is running. + 13 + 1 + read-only + + + busy + Switchover to the new clock source (as selected by CLKSEL) has not yet occurred. + 0 + + + ready + System clock running from CLKSEL clock source. + 1 + + + + + IPO_DIV + IPO clock divider + 14 + 2 + + + DIV1 + Divide 1. + 0 + + + DIV2 + Divide 2. + 1 + + + DIV4 + Divide 4. + 2 + + + DIV8 + Divide 8. + 3 + + + + + ERFO_EN + 27MHz Crystal Oscillator Enable. + 16 + 1 + + + dis + Is Disabled. + 0 + + + en + Is Enabled. + 1 + + + + + ERTCO_EN + 32kHz Crystal Oscillator Enable. + 17 + 1 + + + ISO_EN + 60MHz High Frequency Internal Reference Clock Enable. + 18 + 1 + + + IPO_EN + 96MHz High Frequency Internal Reference Clock Enable. + 19 + 1 + + + IBRO_EN + 8MHz High Frequency Internal Reference Clock Enable. + 20 + 1 + + + IBRO_VS + 7.3728MHz Internal Oscillator Voltage Source Select + 21 + 1 + + + ERFO_RDY + 27MHz Crystal Oscillator Ready + 24 + 1 + read-only + + + not + Is not Ready. + 0 + + + ready + Is Ready. + 1 + + + + + ERTCO_RDY + 32kHz Crystal Oscillator Ready + 25 + 1 + + + ISO_RDY + 60MHz ISO Ready. + 26 + 1 + + + IPO_RDY + Internal Primary Oscillator Ready. + 27 + 1 + + + IBRO_RDY + Internal Baud Rate Oscillator Ready. + 28 + 1 + + + INRO_RDY + Internal Nano Ring Oscillator Low Frequency Reference Clock Ready. + 29 + 1 + + + + + PM + Power Management. + 0x0C + + + MODE + Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode. + 0 + 3 + + + active + Active Mode. + 0 + + + deepsleep + DeepSleep Mode. + 2 + + + shutdown + Shutdown Mode. + 3 + + + backup + Backup Mode. + 4 + + + + + GPIO_WE + GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set. + 4 + 1 + + + RTC_WE + RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers. + 5 + 1 + + + USB_WE + USB Wake Up Enable. This bit enables USB activity as wakeup source. + 6 + 1 + + + ERFO_PD + Radio Frequency oscilator Crystal Power Down. This bit selects the power state in DEEPSLEEP mode. + 12 + 1 + + + active + Mode is Active. + 0 + + + deepsleep + Powered down in DEEPSLEEP. + 1 + + + + + ISO_PD + Internal Secondary Oscilator Power Down. This bit selects the power state in DEEPSLEEP mode. + 15 + 1 + + + active + Mode is Active. + 0 + + + deepsleep + Powered down in DEEPSLEEP. + 1 + + + + + IPO_PD + Internal Primary Oscilatory power down. This bit selects the power state in DEEPSLEEP mode. + 16 + 1 + + + active + Mode is Active. + 0 + + + deepsleep + Powered down in DEEPSLEEP. + 1 + + + + + IBRO_PD + Internal Baud Rate Oscillator power down. This bit selects the power state in DEEPSLEEP mode. + 17 + 1 + + + active + Mode is Active. + 0 + + + deepsleep + Powered down in DEEPSLEEP. + 1 + + + + + ERFO_BP + XTAL Bypass + 20 + 1 + + + normal + Normal + 0 + + + bypass + Bypass + 1 + + + + + + + PCLKDIV + Peripheral Clock Divider. + 0x18 + 0x00000001 + + + ADCFRQ + ADC clock Frequency. These bits define the ADC clock frequency. FADC = FPCLK / (ADCFRQ). + 10 + 4 + + + AONCLKDIV + Always-ON (AON) domain Clock Divider. These bits define the AON domain clock divider. + 14 + 2 + + + DIV4 + PCLK divide by 4. + 0 + + + DIV8 + PCLK divide by 8. + 1 + + + DIV16 + PCLK divide by 16. + 2 + + + DIV32 + PCLK divide by 32. + 3 + + + + + + + PCLKDIS0 + Peripheral Clock Disable. + 0x24 + + + GPIO0 + GPIO0 Clock Disable. + 0 + 1 + + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + GPIO1 + GPIO1 Disable. + 1 + 1 + + + DMA + DMA Disable. + 5 + 1 + + + SPI0 + SPI 0 Disable. + 6 + 1 + + + SPI1 + SPI 1 Disable. + 7 + 1 + + + SPI2 + SPI 2 Disable. + 8 + 1 + + + UART0 + UART 0 Disable. + 9 + 1 + + + UART1 + UART 1 Disable. + 10 + 1 + + + I2C0 + I2C 0 Disable. + 13 + 1 + + + TMR0 + Timer 0 Disable. + 15 + 1 + + + TMR1 + Timer 1 Disable. + 16 + 1 + + + TMR2 + Timer 2 Disable. + 17 + 1 + + + TMR3 + Timer 3 Disable. + 18 + 1 + + + TMR4 + Timer 4 Disable. + 19 + 1 + + + TMR5 + Timer 5 Disable. + 20 + 1 + + + ADC + ADC Disable. + 23 + 1 + + + TMR6 + Timer 6 Disable. + 24 + 1 + + + TMR7 + Timer 7 Disable. + 25 + 1 + + + I2C1 + I2C 1 Disable. + 28 + 1 + + + PT + PT Clock Disable. + 29 + 1 + + + + + MEMCTRL + Memory Clock Control Register. + 0x28 + + + FWS + Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2. + 0 + 3 + + + SRAM_WS + SRAM Wait State Enable + 4 + 1 + + + ROM1_WS + ROM1 Wait State Enable + 7 + 1 + + + RAM0_WS + System RAM 0 Wait State Enable + 8 + 1 + + + RAM1_WS + System RAM 1 Wait State Enable + 9 + 1 + + + RAM2_WS + System RAM 2 Wait State Enable + 10 + 1 + + + RAM3_WS + System RAM 3 Wait State Enable + 11 + 1 + + + RAM4_WS + System RAM 4 Wait State Enable + 12 + 1 + + + RAM5_WS + System RAM 5 Wait State Enable + 13 + 1 + + + RAM0LS_EN + System RAM 0 Light Sleep Mode. + 16 + 1 + + + active + RAM is active. + 0 + + + light_sleep + RAM is in Light Sleep mode. + 1 + + + + + RAM1LS_EN + System RAM 1 Light Sleep Mode. + 17 + 1 + + + RAM2LS_EN + System RAM 2 Light Sleep Mode. + 18 + 1 + + + RAM3LS_EN + System RAM 3 Light Sleep Mode. + 19 + 1 + + + RAM4LS_EN + System RAM 4 Light Sleep Mode. + 20 + 1 + + + RAM5LS_EN + System RAM 5 Light Sleep Mode. + 21 + 1 + + + ICCLS_EN + ICache RAM Light Sleep Mode. + 24 + 1 + + + ICCXIPLS_EN + ICACHE-XIP RAM Light Sleep Mode. + 25 + 1 + + + SRCCLS_EN + SysCache RAM Light Sleep Mode. + 26 + 1 + + + USBLS_EN + USB FIFO Light Sleep Mode. + 28 + 1 + + + ROM0LS_EN + ROM0 Light Sleep Mode. + 29 + 1 + + + ROM1LS_EN + ROM1 Light Sleep Mode. + 30 + 1 + + + + + MEMZ + Memory Zeroize Control. + 0x2C + + + RAM0 + System RAM Block 0. + 0 + 1 + + + nop + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + RAM1 + System RAM Block 1. + 1 + 1 + + + RAM2 + System RAM Block 2. + 2 + 1 + + + RAM3 + System RAM Block 3. + 3 + 1 + + + RAM4 + System RAM Block 4. + 4 + 1 + + + RAM5 + System RAM Block 5. + 5 + 1 + + + RAM6 + System RAM Block 6. + 6 + 1 + + + ICC + Instruction Cache. + 8 + 1 + + + ICCXIP + Instruction Cache XIP Data and Tag Ram zeroizatoin. + 9 + 1 + + + SRCCDATA + System Cache Data Ram Zeroization. + 10 + 1 + + + SRCCTAG + System Cache Tag Zeroization. + 11 + 1 + + + USBFIFO + USB FIFO Zeroization. + 13 + 1 + + + + + SYSST + System Status Register. + 0x40 + + + ICELOCK + ARM ICE Lock Status. + 0 + 1 + + + unlocked + ICE is unlocked. + 0 + + + locked + ICE is locked. + 1 + + + + + CODEAUTHERR + Code Authentication Error Flag. This bit indicates a code authentication error has occured in XiP interface. + 1 + 1 + + + norm + Normal Operating Condition. + 0 + + + code + Code Integrity Error. + 1 + + + + + DATAAUTHERR + Data Authentication Error Flag. This bit indicates a data authentication error has occured in XiP interface. + 2 + 1 + + + norm + Normal Operating Condition. + 0 + + + code + Code Integrity Error. + 1 + + + + + SCMEMF + System Cache Memory Fault Flag. This bit indicates a memory fault has occured in the System Cache while receiving data from the Hyperbus Interface. + 5 + 1 + + + norm + Normal Operating Condition. + 0 + + + memory + Memory Fault. + 1 + + + + + + + RST1 + Reset 1. + 0x44 + + + I2C1 + I2C1 Reset. + 0 + 1 + + + PT + PT Reset. + 1 + 1 + + + OWIRE + OWIRE Reset. + 7 + 1 + + + WDT1 + WDT1 Reset. + 8 + 1 + + + CRC + CRC Reset. + 9 + 1 + + + AES + AES Reset. + 10 + 1 + + + I2S + I2S Reset. + 13 + 1 + + + AC + AC Reset. + 14 + 1 + + + SEMA + Semaphore Reset. + 16 + 1 + + + I2C2 + I2C2 Reset. + 17 + 1 + + + UART3 + UART3 Reset. + 18 + 1 + + + UART4 + UART4 Reset. + 19 + 1 + + + UART5 + UART5 Reset. + 20 + 1 + + + + + PCLKDIS1 + Peripheral Clock Disable. + 0x48 + + + BTLE + Bluetooth Clock Disable. + 0 + 1 + + + en + Enable. + 0 + + + dis + Disable. + 1 + + + + + UART2 + UART2 Disable. + 1 + 1 + + + en + Enable. + 0 + + + dis + Disable. + 1 + + + + + TRNG + TRNG Disable. + 2 + 1 + + + WDT0 + WDT0 Clock Disable + 4 + 1 + + + WDT1 + WDT1 Clock Disable + 5 + 1 + + + SRCC + System Cache Clock Disable. + 7 + 1 + + + SEMA + Semaphore Clock Disable. + 9 + 1 + + + OWIRE + One-Wire Clock Disable. + 13 + 1 + + + CRC + CRC Clock Disable. + 14 + 1 + + + AES + AES Clock Disable. + 15 + 1 + + + I2S + I2S Clock Disable. + 16 + 1 + + + I2C2 + I2C2 Clock Disable + 21 + 1 + + + UART3 + UART3 Clock Disable + 22 + 1 + + + UART4 + UART4 Clock Disable + 23 + 1 + + + UART5 + UART5 Clock Disable + 24 + 1 + + + + + EVENTEN + Event Enable Register. + 0x4C + + + DMA + Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode. + 0 + 1 + + + RX + Enable RXEV pin event. When this bit is set, a logic high of GPIO0[24] will cause an RXEV event to wake the CPU from WFE sleep mode. + 1 + 1 + + + TX + Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO[25]. + 2 + 1 + + + + + REVISION + Revision Register. + 0x50 + read-only + + + REVISION + Manufacturer Chip Revision. + 0 + 16 + + + + + SYSINTEN + System Status Interrupt Enable Register. + 0x54 + + + ICEUNLOCK + ARM ICE Unlock Interrupt Enable. + 0 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + CIE + Code Integrity Error Interrupt Enable. + 1 + 1 + + + SCMF + System Cache Memory Fault Interrupt Enable. + 5 + 1 + + + + + IPOCNT + IPO Warmup Count Register. + 0x58 + + + WMUPCNT + TBD + 0 + 10 + + + + + ECCERR + ECC Error Register + 0x64 + + + RAM0 + ECC System RAM0 Error Flag. Write 1 to clear. + 0 + 1 + + + RAM1 + ECC System RAM1 Error Flag. Write 1 to clear. + 1 + 1 + + + RAM2 + ECC System RAM2 Error Flag. Write 1 to clear. + 2 + 1 + + + RAM3 + ECC System RAM3 Error Flag. Write 1 to clear. + 3 + 1 + + + RAM4 + ECC System RAM4 Error Flag. Write 1 to clear. + 4 + 1 + + + RAM5 + ECC System RAM5 Error Flag. Write 1 to clear. + 5 + 1 + + + ICC + ECC Icache0 Error Flag. Write 1 to clear. + 8 + 1 + + + ICCXIP + ECC SFCC Instruction Cache Error Flag. Write 1 to clear. + 10 + 1 + + + FLASH + ECC Flash0 Error Flag. Write 1 to clear. + 11 + 1 + + + + + ECCCED + ECC Not Double Error Detect Register + 0x68 + + + RAM0 + ECC System RAM0 Error Flag. Write 1 to clear. + 0 + 1 + + + RAM1 + ECC System RAM1 Not Double Error Detect. Write 1 to clear. + 1 + 1 + + + RAM2 + ECC System RAM2 Not Double Error Detect. Write 1 to clear. + 2 + 1 + + + RAM3 + ECC System RAM3 Not Double Error Detect. Write 1 to clear. + 3 + 1 + + + RAM4 + ECC System RAM4 Not Double Error Detect. Write 1 to clear. + 4 + 1 + + + RAM5 + ECC System RAM5 Not Double Error Detect. Write 1 to clear. + 5 + 1 + + + ICC + ECC Icache0 Not Double Error Detect. Write 1 to clear. + 8 + 1 + + + ICCXIP + ECC IcacheXIP Not Double Error Detect. Write 1 to clear. + 10 + 1 + + + FLASH + ECC Flash0 Not Double Error Detect. Write 1 to clear. + 11 + 1 + + + + + ECCINTEN + ECC Interrupt Enable Register + 0x6C + + + RAM0 + ECC System RAM0 Interrupt Enable. + 0 + 1 + + + RAM1 + ECC System RAM1 Interrupt Enable. + 1 + 1 + + + RAM2 + ECC System RAM2 Interrupt Enable. + 2 + 1 + + + RAM3 + ECC System RAM3 Interrupt Enable. + 3 + 1 + + + RAM4 + ECC System RAM4 Interrupt Enable. + 4 + 1 + + + RAM5 + ECC System RAM5 Interrupt Enable. + 5 + 1 + + + ICC + ECC Icache0 Interrupt Enable. + 8 + 1 + + + ICCXIP + ECC IcacheXIP Interrupt Enable. + 10 + 1 + + + FLASH + ECC Flash0 Interrupt Enable. + 11 + 1 + + + + + ECCADDR + ECC Error Address Register + 0x70 + + + DADDR + Address of Error in Data RAM. + 0 + 14 + + + DB + Data Bank, + 14 + 1 + + + DE + Data Error Flag. + 15 + 1 + + + TADDR + Address of Error in Tag RAM. + 16 + 14 + + + TB + Tag Bank. + 30 + 1 + + + TE + Tag Error Flag. + 31 + 1 + + + + + BTLELDOCTRL + BTLE LDO Control Register + 0x74 + + + TX_EN + LDOTX enable. + 0 + 1 + + + TX_PD_EN + LDOTX Pull Down. + 1 + 1 + + + TX_VSEL + Voltage Selection for NFC LDO + 2 + 2 + + + RX_EN + LDORX enable. + 4 + 1 + + + RX_PD_EN + LDORX Pull DOwn. + 5 + 1 + + + RX_VSEL + LDORX Voltage Setting. + 6 + 2 + + + RX_BP_EN + LDORX Bypass Enable. + 8 + 1 + + + RX_DISCH + LDORX Discharge. + 9 + 1 + + + TX_BP_EN + LDOTX Bypass Enable. + 10 + 1 + + + TX_DISCH + LDOTX Discharge. + 11 + 1 + + + TX_EN_DLY + LDOTX Enable Delay. + 12 + 1 + + + RX_EN_DLY + LDORX Enable Delay. + 13 + 1 + + + RX_BP_EN_DLY + LDORX Bypass Enable Delay. + 14 + 1 + + + TX_BP_EN_DLY + LDOTX Bypass Enable Delay. + 15 + 1 + + + + + BTLELDODLY + BTLE LDO Delay Register + 0x78 + + + BP_CNT + Bypass delay count. + 0 + 8 + + + RX_CNT + RX delay count. + 8 + 9 + + + TX_CNT + TX delay count. + 20 + 9 + + + + + FLVRST + Flash Low Voltage Reset Control Register + 0x80 + + + EN + Flash Low Voltage Reset Enable. + 0 + 1 + + + + + FLVCLKCTRL + Flash Low Voltage Clock Control Register + 0x84 + + + DIV + Flash Low Voltage Clock Divider Select. + 0 + 2 + + + 512 + Divide 512. + 0 + + + 256 + Divide 256 + 1 + + + 128 + Divide 128 + 2 + + + 64 + Divide 64 + 3 + + + + + + + FLVSTAT + Flash Low Voltage Status Register + 0x88 + + + FLV + Live Flash Low Voltage Detect Status. + 0 + 1 + + + ONES + FLV Buffer contains all ones if supply is above safe operating range. + 6 + 1 + + + ZEROS + FLV Buffer contains all zeros if supply is below safe operating voltage. + 7 + 1 + + + ONES_FL + Sticky version of ONES status. Write 1 to clear. + 14 + 1 + + + ZEROS_FL + Sticky version of ZEROS status. Write 1 to clear. + 15 + 1 + + + BUF + 10 Sample History of FLV status. + 16 + 10 + + + + + + + + GCFR + Global Control Function Register. + 0x40005800 + + 0x00 + 0x400 + registers + + + + REG0 + Register 0. + 0x00 + read-write + + + ISO_WUP + ISO Warm Up Value. + 0 + 9 + + + IPO_WUP + IPO Warm Up Value. + 16 + 11 + + + + + REG1 + Register 1. + 0x04 + read-write + + + ERFO_WUP + ERFO Warm Up Value. + 0 + 14 + + + IBRO_WUP + IBRO Warm Up Value. + 16 + 6 + + + + + + + + GPIO0 + Individual I/O for each GPIO + GPIO + 0x40008000 + + 0x00 + 0x1000 + registers + + + GPIO0 + GPIO0 interrupt. + 24 + + + + EN0 + GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port. + 0x00 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + ALTERNATE + Alternate function enabled. + 0 + + + GPIO + GPIO function is enabled. + 1 + + + + + + + EN0_SET + GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1, without affecting other bits in that register. + 0x04 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN0_CLR + GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register. + 0x08 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + OUTEN + GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port. + 0x0C + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + dis + GPIO Output Disable + 0 + + + en + GPIO Output Enable + 1 + + + + + + + OUTEN_SET + GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1, without affecting other bits in that register. + 0x10 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + OUTEN_CLR + GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, without affecting other bits in that register. + 0x14 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + OUT + GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers. + 0x18 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + low + Drive Logic 0 (low) on GPIO output. + 0 + + + high + Drive logic 1 (high) on GPIO output. + 1 + + + + + + + OUT_SET + GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1, without affecting other bits in that register. + 0x1C + write-only + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + no + No Effect. + 0 + + + set + Set GPIO_OUT bit in this position to '1' + 1 + + + + + + + OUT_CLR + GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0, without affecting other bits in that register. + 0x20 + write-only + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + IN + GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port. + 0x24 + read-only + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + INTMODE + GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port. + 0x28 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + level + Interrupts for this pin are level triggered. + 0 + + + edge + Interrupts for this pin are edge triggered. + 1 + + + + + + + INTPOL + GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port. + 0x2C + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + falling + Interrupts are latched on a falling edge or low level condition for this pin. + 0 + + + rising + Interrupts are latched on a rising edge or high condition for this pin. + 1 + + + + + + + INEN + GPIO Input Enable + 0x30 + + + INTEN + GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port. + 0x34 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + dis + Interrupts are disabled for this GPIO pin. + 0 + + + en + Interrupts are enabled for this GPIO pin. + 1 + + + + + + + INTEN_SET + GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits in that register. + 0x38 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + no + No effect. + 0 + + + set + Set GPIO_INT_EN bit in this position to '1' + 1 + + + + + + + INTEN_CLR + GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0, without affecting other bits in that register. + 0x3C + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + no + No Effect. + 0 + + + clear + Clear GPIO_INT_EN bit in this position to '0' + 1 + + + + + + + INTFL + GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port. + 0x40 + read-only + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + no + No Interrupt is pending on this GPIO pin. + 0 + + + pending + An Interrupt is pending on this GPIO pin. + 1 + + + + + + + INTFL_CLR + GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits in that register. + 0x48 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + WKEN + GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port. + 0x4C + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + dis + PMU wakeup for this GPIO is disabled. + 0 + + + en + PMU wakeup for this GPIO is enabled. + 1 + + + + + + + WKEN_SET + GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in that register. + 0x50 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + WKEN_CLR + GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other bits in that register. + 0x54 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + DUALEDGE + GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port. + 0x5C + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + no + No Effect. + 0 + + + en + Dual Edge mode is enabled. If edge-triggered interrupts are enabled on this GPIO pin, then both rising and falling edges will trigger interrupts regardless of the GPIO_INT_POL setting. + 1 + + + + + + + PADCTRL0 + GPIO Input Mode Config 0. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port. + 0x60 + + + ALL + The two bits in GPIO_PADCTRL0 and GPIO_PADCTRL1 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. + 0 + 32 + + + impedance + High Impedance. + 0 + + + pu + Weak pull-up mode. + 1 + + + pd + weak pull-down mode. + 2 + + + + + + + PADCTRL1 + GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port. + 0x64 + + + ALL + The two bits in GPIO_PADCTRL0 and GPIO_PADCTRL1 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. + 0 + 32 + + + impedance + High Impedance. + 0 + + + pu + Weak pull-up mode. + 1 + + + pd + weak pull-down mode. + 2 + + + + + + + EN1 + GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. + 0x68 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + primary + Primary function selected. + 0 + + + secondary + Secondary function selected. + 1 + + + + + + + EN1_SET + GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register. + 0x6C + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN1_CLR + GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register. + 0x70 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN2 + GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. + 0x74 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + primary + Primary function selected. + 0 + + + secondary + Secondary function selected. + 1 + + + + + + + EN2_SET + GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1, without affecting other bits in that register. + 0x78 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN2_CLR + GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0, without affecting other bits in that register. + 0x7C + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + HYSEN + GPIO Input Hysteresis Enable. + 0xA8 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + SRSEL + GPIO Slew Rate Enable Register. + 0xAC + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + FAST + Fast Slew Rate selected. + 0 + + + SLOW + Slow Slew Rate selected. + 1 + + + + + + + DS0 + GPIO Drive Strength 0 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. + 0xB0 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + ld + GPIO port pin is in low-drive mode. + 0 + + + hd + GPIO port pin is in high-drive mode. + 1 + + + + + + + DS1 + GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. + 0xB4 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + PSSEL + GPIO Pull Select Mode. + 0xB8 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + VSSEL + GPIO Voltage Select. + 0xC0 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + + + + GPIO1 + Individual I/O for each GPIO 1 + 0x40009000 + + GPIO1 + GPIO1 IRQ + 25 + + + + + GPIO2 + Individual I/O for each GPIO 2 + 0x40080400 + + GPIO2 + GPIO2 IRQ + 26 + + + + + I2C0 + Inter-Integrated Circuit. + I2C + 0x4001D000 + 32 + + 0x00 + 0x1000 + registers + + + I2C0 + I2C0 IRQ + 13 + + + + CTRL + Control Register0. + 0x00 + + + EN + I2C Enable. + [0:0] + read-write + + + dis + Disable I2C. + 0 + + + en + enable I2C. + 1 + + + + + MST_MODE + Master Mode Enable. + [1:1] + read-write + + + slave_mode + Slave Mode. + 0 + + + master_mode + Master Mode. + 1 + + + + + GC_ADDR_EN + General Call Address Enable. + [2:2] + read-write + + + dis + Ignore Gneral Call Address. + 0 + + + en + Acknowledge general call address. + 1 + + + + + IRXM_EN + Interactive Receive Mode. + [3:3] + read-write + + + dis + Disable Interactive Receive Mode. + 0 + + + en + Enable Interactive Receive Mode. + 1 + + + + + IRXM_ACK + Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0. + [4:4] + read-write + + + ack + return ACK (pulling SDA LOW). + 0 + + + nack + return NACK (leaving SDA HIGH). + 1 + + + + + SCL_OUT + SCL Output. This bits control SCL output when SWOE =1. + [6:6] + read-write + + + drive_scl_low + Drive SCL low. + 0 + + + release_scl + Release SCL. + 1 + + + + + SDA_OUT + SDA Output. This bits control SDA output when SWOE = 1. + [7:7] + read-write + + + drive_sda_low + Drive SDA low. + 0 + + + release_sda + Release SDA. + 1 + + + + + SCL + SCL status. This bit reflects the logic gate of SCL signal. + [8:8] + read-only + + + SDA + SDA status. THis bit reflects the logic gate of SDA signal. + [9:9] + read-only + + + BB_EN + Software Output Enable. + [10:10] + read-write + + + outputs_disable + I2C Outputs SCLO and SDAO disabled. + 0 + + + outputs_enable + I2C Outputs SCLO and SDAO enabled. + 1 + + + + + READ + Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match (GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set. + [11:11] + read-only + + + write + Write. + 0 + + + read + Read. + 1 + + + + + CLKSTR_DIS + This bit will disable slave clock stretching when set. + [12:12] + read-write + + + en + Slave clock stretching enabled. + 0 + + + dis + Slave clock stretching disabled. + 1 + + + + + ONE_MST_MODE + SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low. + [13:13] + read-write + + + dis + Standard open-drain operation: + drive low for 0, Hi-Z for 1 + 0 + + + en + Non-standard push-pull operation: + drive low for 0, drive high for 1 + 1 + + + + + HS_EN + High speed mode enable + [15:15] + read-write + + + + + STATUS + Status Register. + 0x04 + + + BUSY + Bus Status. + [0:0] + read-only + + + idle + I2C Bus Idle. + 0 + + + busy + I2C Bus Busy. + 1 + + + + + RX_EM + RX empty. + [1:1] + read-only + + + not_empty + Not Empty. + 0 + + + empty + Empty. + 1 + + + + + RX_FULL + RX Full. + [2:2] + read-only + + + not_full + Not Full. + 0 + + + full + Full. + 1 + + + + + TX_EM + TX Empty. + [3:3] + + + not_empty + Not Empty. + 0 + + + empty + Empty. + 1 + + + + + TX_FULL + TX Full. + [4:4] + + + not_empty + Not Empty. + 0 + + + empty + Empty. + 1 + + + + + MST_BUSY + Clock Mode. + [5:5] + read-only + + + not_actively_driving_scl_clock + Device not actively driving SCL clock cycles. + 0 + + + actively_driving_scl_clock + Device operating as master and actively driving SCL clock cycles. + 1 + + + + + + + INTFL0 + Interrupt Status Register. + 0x08 + + + DONE + Transfer Done Interrupt. + [0:0] + + INT_FL0_Done + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + IRXM + Interactive Receive Interrupt. + [1:1] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + GC_ADDR_MATCH + Slave General Call Address Match Interrupt. + [2:2] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + ADDR_MATCH + Slave Address Match Interrupt. + [3:3] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + RX_THD + Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level. + [4:4] + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. RX_FIFO equal or more bytes than the threshold. + 1 + + + + + TX_THD + Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level. + [5:5] + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. + 1 + + + + + STOP + STOP Interrupt. + [6:6] + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. + 1 + + + + + ADDR_ACK + Address Acknowledge Interrupt. + [7:7] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + ARB_ERR + Arbritation error Interrupt. + [8:8] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + TO_ERR + timeout Error Interrupt. + [9:9] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + ADDR_NACK_ERR + Address NACK Error Interrupt. + [10:10] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + DATA_ERR + Data NACK Error Interrupt. + [11:11] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + DNR_ERR + Do Not Respond Error Interrupt. + [12:12] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + START_ERR + Start Error Interrupt. + [13:13] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + STOP_ERR + Stop Error Interrupt. + [14:14] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + TX_LOCKOUT + Transmit Lock Out Interrupt. + [15:15] + + + MAMI + Multiple Address Match Interrupt + [21:16] + + + RD_ADDR_MATCH + Slave Read Address Match Interrupt + [22:22] + + + WR_ADDR_MATCH + Slave Write Address Match Interrupt + [23:23] + + + + + INTEN0 + Interrupt Enable Register. + 0x0C + read-write + + + DONE + Transfer Done Interrupt Enable. + [0:0] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when DONE = 1. + 1 + + + + + IRXM + Description not available. + [1:1] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when RX_MODE = 1. + 1 + + + + + GC_ADDR_MATCH + Slave mode general call address match received input enable. + [2:2] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when GEN_CTRL_ADDR = 1. + 1 + + + + + ADDR_MATCH + Slave mode incoming address match interrupt. + [3:3] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when ADDR_MATCH = 1. + 1 + + + + + RX_THD + RX FIFO Above Treshold Level Interrupt Enable. + [4:4] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + TX_THD + TX FIFO Below Treshold Level Interrupt Enable. + [5:5] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + STOP + Stop Interrupt Enable + [6:6] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when STOP = 1. + 1 + + + + + ADDR_ACK + Received Address ACK from Slave Interrupt. + [7:7] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + ARB_ERR + Master Mode Arbitration Lost Interrupt. + [8:8] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + TO_ERR + Timeout Error Interrupt Enable. + [9:9] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + ADDR_NACK_ERR + Master Mode Address NACK Received Interrupt. + [10:10] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + DATA_ERR + Master Mode Data NACK Received Interrupt. + [11:11] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + DNR_ERR + Slave Mode Do Not Respond Interrupt. + [12:12] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + START_ERR + Out of Sequence START condition detected interrupt. + [13:13] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + STOP_ERR + Out of Sequence STOP condition detected interrupt. + [14:14] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + TX_LOCKOUT + TX FIFO Locked Out Interrupt. + [15:15] + + + MAMI + Multiple Address Match Interrupt + [21:16] + + + RD_ADDR_MATCH + Slave Read Address Match Interrupt + [22:22] + + + WR_ADDR_MATCH + Slave Write Address Match Interrupt + [23:23] + + + + + INTFL1 + Interrupt Status Register 1. + 0x10 + + + RX_OV + Receiver Overflow Interrupt. When operating as a slave receiver, this bit is set when you reach the first data bit and the RX FIFO and shift register are both full. + [0:0] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + TX_UN + Transmit Underflow Interrupt. When operating as a slave transmitter, this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet). + [1:1] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + START + START Condition Status Flag. + [2:2] + + + + + INTEN1 + Interrupt Staus Register 1. + 0x14 + read-write + + + RX_OV + Receiver Overflow Interrupt Enable. + [0:0] + + + dis + No Interrupt is Pending. + 0 + + + en + An interrupt is pending. + 1 + + + + + TX_UN + Transmit Underflow Interrupt Enable. + [1:1] + + + dis + No Interrupt is Pending. + 0 + + + en + An interrupt is pending. + 1 + + + + + START + START Condition Interrupt Enable. + [2:2] + + + + + FIFOLEN + FIFO Configuration Register. + 0x18 + + + RX_DEPTH + Receive FIFO Length. + [7:0] + read-only + + + TX_DEPTH + Transmit FIFO Length. + [15:8] + read-only + + + + + RXCTRL0 + Receive Control Register 0. + 0x1C + + + DNR + Do Not Respond. + [0:0] + + + respond + Always respond to address match. + 0 + + + not_respond_rx_fifo_empty + Do not respond to address match when RX_FIFO is not empty. + 1 + + + + + FLUSH + Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status. + [7:7] + + + not_flushed + FIFO not flushed. + 0 + + + flush + Flush RX_FIFO. + 1 + + + + + THD_LVL + Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold. + [11:8] + + + + + RXCTRL1 + Receive Control Register 1. + 0x20 + + + CNT + Receive Count Bits. These bits define the number of bytes to be received in a transaction, except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction. + [7:0] + + + LVL + Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0. + [11:8] + read-only + + + + + TXCTRL0 + Transmit Control Register 0. + 0x24 + + + PRELOAD_MODE + Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match. + [0:0] + + + TX_READY_MODE + Transmit FIFO Ready Manual Mode. + [1:1] + + + en + HW control of I2CTXRDY enabled. + 0 + + + dis + HW control of I2CTXRDY disabled. + 1 + + + + + GC_ADDR_FLUSH_DIS + TX FIFO General Call Address Match Auto Flush Disable. + [2:2] + + + en + Enabled. + 0 + + + dis + Disabled. + 1 + + + + + WR_ADDR_FLUSH_DIS + TX FIFO Slave Address Match Write Auto Flush Disable. + [3:3] + + + en + Enabled. + 0 + + + dis + Disabled. + 1 + + + + + RD_ADDR_FLUSH_DIS + TX FIFO Slave Address Match Read Auto Flush Disable. + [4:4] + + + en + Enabled. + 0 + + + dis + Disabled. + 1 + + + + + NACK_FLUSH_DIS + TX FIFO received NACK Auto Flush Disable. + [5:5] + + + en + Enabled. + 0 + + + dis + Disabled. + 1 + + + + + FLUSH + Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation. + [7:7] + + + not_flushed + FIFO not flushed. + 0 + + + flush + Flush TX_FIFO. + 1 + + + + + THD_VAL + Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold. + [11:8] + + + + + TXCTRL1 + Transmit Control Register 1. + 0x28 + + + PRELOAD_RDY + Transmit FIFO Preload Ready. + [0:0] + + + LAST + Transmit Last. + [1:1] + + + LVL + Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO. + [11:8] + read-only + + + + + FIFO + Data Register. + 0x2C + + + DATA + Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location. + 0 + 8 + + + + + MSTCTRL + Master Control Register. + 0x30 + + + START + Setting this bit to 1 will start a master transfer. + [0:0] + + + RESTART + Setting this bit to 1 will generate a repeated START. + [1:1] + + + STOP + Setting this bit to 1 will generate a STOP condition. + [2:2] + + + EX_ADDR_EN + Slave Extend Address Select. + [7:7] + + + 7_bits_address + 7-bit address. + 0 + + + 10_bits_address + 10-bit address. + 1 + + + + + CODE + Master Code. + [10:8] + + + IGN_ACK + Master Ignore Acknowledge. + [12:12] + + + + + CLKLO + Clock Low Register. + 0x34 + + + LO + Clock low. In master mode, these bits define the SCL low period. In slave mode, these bits define the time SCL will be held low after data is outputted. + [8:0] + + + + + CLKHI + Clock high Register. + 0x38 + + + HI + Clock High. In master mode, these bits define the SCL high period. + [8:0] + + + + + HSCLK + Clock high Register. + 0x3C + + + LO + Clock Low. This field sets the Hs-Mode clock low count. In Slave mode, this is the time SCL is held low after data is output on SDA. + [7:0] + + + HI + Clock High. This field sets the Hs-Mode clock high count. In Slave mode, this is the time SCL is held high after data is output on SDA + [15:8] + + + + + TIMEOUT + Timeout Register + 0x40 + + + SCL_TO_VAL + Timeout + [15:0] + + + + + DMA + DMA Register. + 0x48 + + + TX_EN + TX channel enable. + [0:0] + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + RX_EN + RX channel enable. + [1:1] + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + + + 4 + 4 + SLAVE_MULTI[%s] + Slave Address Register. + SLAVE0 + 0x4C + 32 + read-write + + + ADDR + Slave Address. + [9:0] + + + DIS + Slave Disable. + [10:10] + + + EXT_ADDR_EN + Extended Address Select. + [15:15] + + + 7_bits_address + 7-bit address. + 0 + + + 10_bits_address + 10-bit address. + 1 + + + + + + + SLAVE0 + Slave Address Register. + 0x4C + + + SLAVE1 + Slave Address Register. + 0x50 + + + SLAVE2 + Slave Address Register. + 0x54 + + + SLAVE3 + Slave Address Register. + 0x58 + + + + + + I2C1 + Inter-Integrated Circuit. 1 + 0x4001E000 + + I2C1 + I2C1 IRQ + 36 + + + + + I2C2 + Inter-Integrated Circuit. 2 + 0x4001F000 + + I2C2 + I2C2 IRQ + 62 + + + + + I2S + Inter-IC Sound Interface. + I2S + 0x40060000 + 32 + + 0x00 + 0x1000 + registers + + + I2S + I2S IRQ + 99 + + + + CTRL0CH0 + Global mode channel. + 0x00 + + + LSB_FIRST + LSB Transmit Receive First. + [1:1] + read-write + + + PDM_FILT + PDM Filter. + [2:2] + read-write + + + PDM_EN + PDM Enable. + [3:3] + read-write + + + USEDDR + DDR. + [4:4] + read-write + + + PDM_INV + Invert PDM. + [5:5] + read-write + + + CH_MODE + SCK Select. + [7:6] + read-write + + + WS_POL + WS polarity select. + [8:8] + read-write + + + MSB_LOC + MSB location. + [9:9] + read-only + + + ALIGN + Align to MSB or LSB. + [10:10] + read-only + + + EXT_SEL + External SCK/WS selection. + [11:11] + read-write + + + STEREO + Stereo mode of I2S. + [13:12] + read-only + + + WSIZE + Data size when write to FIFO. + [15:14] + read-write + + + TX_EN + TX channel enable. + [16:16] + read-write + + + RX_EN + RX channel enable. + [17:17] + read-write + + + FLUSH + Flushes the TX/RX FIFO buffer. + [18:18] + read-write + + + RST + Write 1 to reset channel. + [19:19] + read-write + + + FIFO_LSB + Bit Field Control. + [20:20] + read-write + + + RX_THD_VAL + depth of receive FIFO for threshold interrupt generation. + [31:24] + read-write + + + + + CTRL1CH0 + Local channel Setup. + 0x10 + + + BITS_WORD + I2S word length. + [4:0] + read-write + + + EN + I2S clock enable. + [8:8] + read-write + + + SMP_SIZE + I2S sample size length. + [13:9] + read-write + + + CLKSEL + Select source clock for internal SCK mode. + [14:14] + read-write + + + ADJUST + LSB/MSB Justify. + [15:15] + read-write + + + CLKDIV + I2S clock frequency divisor. + [31:16] + read-write + + + + + FILTCH0 + Filter. + 0x20 + + + DMACH0 + DMA Control. + 0x30 + + + DMA_TX_THD_VAL + TX FIFO Level DMA Trigger. + [6:0] + read-write + + + DMA_TX_EN + TX DMA channel enable. + [7:7] + read-write + + + DMA_RX_THD_VAL + RX FIFO Level DMA Trigger. + [14:8] + read-write + + + DMA_RX_EN + RX DMA channel enable. + [15:15] + read-write + + + TX_LVL + Number of data word in the TX FIFO. + [23:16] + read-write + + + RX_LVL + Number of data word in the RX FIFO. + [31:24] + read-write + + + + + FIFOCH0 + I2S Fifo. + 0x40 + + + DATA + Load/unload location for TX and RX FIFO buffers. + [31:0] + read-write + + + + + INTFL + ISR Status. + 0x50 + + + RX_OV_CH0 + Status for RX FIFO Overrun interrupt. + [0:0] + read-write + + + RX_THD_CH0 + Status for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field. + [1:1] + read-write + + + TX_OB_CH0 + Status for interrupt when TX FIFO has only one byte remaining. + [2:2] + read-write + + + TX_HE_CH0 + Status for interrupt when TX FIFO is half empty. + [3:3] + read-write + + + + + INTEN + Interrupt Enable. + 0x54 + + + RX_OV_CH0 + Enable for RX FIFO Overrun interrupt. + [0:0] + read-write + + + RX_THD_CH0 + Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field. + [1:1] + read-write + + + TX_OB_CH0 + Enable for interrupt when TX FIFO has only one byte remaining. + [2:2] + read-write + + + TX_HE_CH0 + Enable for interrupt when TX FIFO is half empty. + [3:3] + read-write + + + + + EXTSETUP + Ext Control. + 0x58 + + + EXT_BITS_WORD + Word Length for ch_mode. + [4:0] + read-write + + + + + WKEN + Wakeup Enable. + 0x5C + + + WKFL + Wakeup Flags. + 0x60 + + + + + + ICC0 + Instruction Cache Controller Registers + 0x4002A000 + + 0x00 + 0x800 + registers + + + + INFO + Cache ID Register. + 0x0000 + read-only + + + RELNUM + Release Number. Identifies the RTL release version. + 0 + 6 + + + PARTNUM + Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter. + 6 + 4 + + + ID + Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter. + 10 + 6 + + + + + SZ + Memory Configuration Register. + 0x0004 + read-only + 0x00080008 + + + CCH + Cache Size. Indicates total size in Kbytes of cache. + 0 + 16 + + + MEM + Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller. + 16 + 16 + + + + + CTRL + Cache Control and Status Register. + 0x0100 + + + EN + Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated. + 0 + 1 + + + dis + Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array. + 0 + + + en + Cache Enabled. + 1 + + + + + RDY + Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready. + 16 + 1 + read-only + + + notReady + Not Ready. + 0 + + + ready + Ready. + 1 + + + + + + + INVALIDATE + Invalidate All Registers. + 0x0700 + read-write + + + INVALID + Invalidate. + 0 + 32 + + + + + + + + LPCMP + Low Power Comparator + 0x40088000 + + 0x00 + 0x400 + registers + + + LPCMP + Low Power Comparato + 103 + + + + 3 + 4 + CTRL[%s] + Comparator Control Register. + 0x00 + + + EN + Comparator Enable. + 0 + 1 + + + POL + Polarity Select + 5 + 1 + + + INT_EN + IRQ Enable. + 6 + 1 + + + OUT + Raw Compartor Input. + 14 + 1 + + + INT_FL + IRQ Flag + 15 + 1 + + + + + + + + LPGCR + Low Power Global Control. + 0x40080000 + + 0x00 + 0x400 + registers + + + + RST + Low Power Reset Register. + 0x08 + + + GPIO2 + Low Power GPIO 2 Reset. + 0 + 1 + + reset + read-write + + reset_done + Reset complete. + 0 + + + busy + Starts Reset or indicates reset in progress. + 1 + + + + + WDT1 + Low Power Watchdog Timer 1 Reset. + 1 + 1 + + + TMR4 + Low Power Timer 4 Reset. + 2 + 1 + + + TMR5 + Low Power Timer 5 Reset. + 3 + 1 + + + UART3 + Low Power UART 3 Reset. + 4 + 1 + + + LPCOMP + Low Power Comparator Reset. + 6 + 1 + + + + + PCLKDIS + Low Power Peripheral Clock Disable Register. + 0x0C + + + GPIO2 + Low Power GPIO 2 Clock Disable. + 0 + 1 + + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + WDT1 + Low Power Watchdog 1 Clock Disable. + 1 + 1 + + + TMR4 + Low Power Timer 4 Clock Disable. + 2 + 1 + + + TMR5 + Low Power Timer 5 Clock Disable. + 3 + 1 + + + UART3 + Low Power UART 3 Clock Disable. + 4 + 1 + + + LPCOMP + Low Power Comparator Clock Disable. + 6 + 1 + + + + + + + + MCR + Misc Control. + 0x40006C00 + + 0x00 + 0x400 + registers + + + + ECCEN + ECC Enable Register + 0x00 + + + RAM0 + ECC System RAM0 Enable. + 0 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + + + IPOTRIM + IPO Manual Trim Register + 0x04 + + + VAL + Manual Trim Value. + 0 + 8 + + + RANGE + Trim Range Select. + 8 + 1 + + + + + OUTEN + Output Enable Register. + 0x08 + + + SQWOUT_EN + Square Wave Output Enable. + 0 + 1 + + + PDOWN_EN + Power Down Output Enable. + 1 + 1 + + + + + CMP_CTRL + Comparator Control Register. + 0x0C + + + EN + Comparator Enable. + 0 + 1 + + + POL + Polarity Select + 5 + 1 + + + INTR_EN + IRQ Enable. + 6 + 1 + + + OUT + Comparator Output State. + 14 + 1 + + + INTR_FL + IRQ Flag + 15 + 1 + + + + + CTRL + Control Register + 0x10 + + + CMP_HYST + Comparator hysteresis control. + 0 + 2 + + + INRO_EN + INRO Enable. + 2 + 1 + + + ERTCO_EN + ERTCO Enable. + 3 + 1 + + + IBRO_EN + IBRO Enable. + 4 + 1 + + + ERTCO_LP_EN + Enable 32K Oscillator input. + 5 + 1 + + + PADPUP_RST + Enable the Reset Pad Pull Up Resistors + 9 + 1 + + + 1m + 1MOhm Pullup + 0 + + + 25k + 25kOhm Pullup. + 1 + + + + + PADVDDIOHSEL_RST + Reset VIDDIOH Select. + 10 + 1 + + + + + RTCRST + Reset Register. + 0x18 + + + RTC + RTC Reset. + 0 + 1 + + + + + RTCTRIM + RTC Trim Register. + 0x1C + + + X1 + RTC Trim X1. + 0 + 5 + + + X2 + RTC Trim X2. + 8 + 5 + + + + + GPIO3_CTRL + GPIO3 Pin Control Register. + 0x20 + + + P30_OUT + GPIO3 Pin 0 Data Output. + 0 + 1 + + + P30_OUTEN + GPIO3 Pin 0 Output Enable. + 1 + 1 + + + P30_PUPEN + GPIO3 Pin 0 Pull-up Enable. + 2 + 1 + + + P30_IN + GPIO3 Pin 0 Input Status. + 3 + 1 + + + P31_OUT + GPIO3 Pin 1 Data Output. + 4 + 1 + + + P31_OUTEN + GPIO3 Pin 1 Output Enable. + 5 + 1 + + + P31_PUPEN + GPIO3 Pin 1 Pull-up Enable. + 6 + 1 + + + P31_IN + GPIO3 Pin 1 Input Status. + 7 + 1 + + + + + LDOCTRL + LDO Control Register. + 0x60 + + + 0P9V_EN + LDO 0.9V Enable. + 0 + 1 + + + + + PWRMONST + LDO Control Register. + 0x64 + + + PORZ_VLOSS + Sticky bit indicating power-on status of core power domains of VDDIO, VDDIOH, VCOR + 0 + 1 + + + PORZ_VBAT + Sticky bit indicating power-on status of the battery. + 1 + 1 + + + PORZ_VBB + Sticky bit indicating power-on status of the VBB. + 2 + 1 + + + PORZ_VDDCA + Sticky bit indicating power-on status of VAON_SW supply. + 4 + 1 + + + PORZ_VDDCB + Sticky bit indicating power-on status of VCORE_PAD supply. + 5 + 1 + + + PORZ_VDDA + Sticky bit indicating power-on status of VDDA (for analog) supply. + 6 + 1 + + + PORZ_VDDB + Sticky bit indicating power-on status of VDDB (for USB) supply. + 7 + 1 + + + RSTZ_VDDCB + Sticky bit indicating reset condition on VCORE supply. + 9 + 1 + + + RSTZ_VDDA + Sticky bit indicating reset condition on VDDA (analog) supply. + 10 + 1 + + + RSTZ_VDDB + Sticky bit indicating reset condition on VDDB (USB) supply. + 11 + 1 + + + RSTZ_VDDIO + Sticky bit indicating reset condition on VDDIO supply. + 12 + 1 + + + RSTZ_VDDIOH + Sticky bit indicating reset condition on VDDIOH supply. + 13 + 1 + + + RSTZ_VBB + Sticky bit indicating reset condition on VBB supply. + 14 + 1 + + + RSTZ_LDO0P9V + Sticky bit indicating reset condition on 0.9V USB supply. + 16 + 1 + + + RSTZ_VDDCA + Sticky bit indicating reset condition on VCORE in Analog supply. + 17 + 1 + + + RSTZ_VCOREHV + Sticky bit indicating high voltage reset condition on VCORE supply. + 18 + 1 + + + RSTZ_VDDIOHV + Sticky bit indicating high voltage reset condition on VDDIO supply. + 19 + 1 + + + RSTZ_VDDIOHHV + Sticky bit indicating high voltage reset condition on VDDIOH supply. + 20 + 1 + + + RSTZ_VNFCRX + Sticky bit indicating reset condition on VNFCRX supply. + 21 + 1 + + + RSTZ_VNFCTX + Sticky bit indicating reset condition on VNFCTX supply. + 22 + 1 + + + RSTZ_VNFC1V + Sticky bit indicating reset condition on VNFC1V supply. + 23 + 1 + + + + + + + + OWM + 1-Wire Master Interface. + 0x4003D000 + 32 + read-write + + 0 + 0x1000 + registers + + + OneWire + 67 + + + + CTRL0 + 1-Wire Master Control Register. + 0x0000 + read-write + + + LL_EN + Enable Long Line Mode. + [0:0] + read-write + + + FPRESDET + Force Line During Presence Detect. + [1:1] + read-write + + + BB_EN + Bit Bang Enable. + [2:2] + read-write + + + EXT_PU_MODE + Provide an extra output control to control an external pullup. + [3:3] + read-write + + + EXT_PU_EN + Enable External Pullup. + [4:4] + read-write + + + SB_EN + Enable Single Bit TX/RX Mode. + [5:5] + read-write + + + OD + Enables overdrive speed for 1-Wire operations. + [6:6] + read-write + + + INT_PU_EN + Enable intenral pullup. + [7:7] + read-write + + + + + CLKDIV + 1-Wire Master Clock Divisor. + 0x0004 + read-write + + + DIVISOR + Clock Divisor for 1Mhz. + [7:0] + read-write + + + + + CTRL1 + 1-Wire Master Control/Status. + 0x0008 + read-write + + + RST + Start OW Reset. + [0:0] + read-write + + + SRA_EN + Enable SRA Mode. + [1:1] + read-write + + + BB_OUT_EN + Bit Bang Output Enable. + [2:2] + read-write + + + INPUT_ST + OW Input State. + [3:3] + read-only + + + OD_SPEC_ST + Overdrive Spec Mode. + [4:4] + read-only + + + PRESDET_ST + Presence Pulse Detected. + [7:7] + read-only + + + + + DATA + 1-Wire Master Data Buffer. + 0x000C + read-write + + + DATA + TX/RX Buffer. + [7:0] + read-write + + + + + INTFL + 1-Wire Master Interrupt Flags. + 0x0010 + read-write + + + RST_DONE + OW Reset Sequence Completed. + [0:0] + read-write + + + TX_EM + TX Data Empty Interrupt Flag. + [1:1] + read-write + + + RX_RDY + RX Data Ready Interrupt Flag + [2:2] + read-write + + + LINE_SHORT + OW Line Short Detected Interrupt Flag. + [3:3] + read-write + + + LINE_LOW + OW Line Low Detected Interrupt Flag. + [4:4] + read-write + + + + + INTEN + 1-Wire Master Interrupt Enables. + 0x0014 + read-write + + + RST_DONE + OW Reset Sequence Completed. + [0:0] + read-write + oneToClear + + + TX_EM + Tx Data Empty Interrupt Enable. + [1:1] + read-write + oneToClear + + + RX_RDY + Rx Data Ready Interrupt Enable. + [2:2] + read-write + oneToClear + + + LINE_SHORT + OW Line Short Detected Interrupt Enable. + [3:3] + read-write + oneToClear + + + LINE_LOW + OW Line Low Detected Interrupt Enable. + [4:4] + read-write + oneToClear + + + + + + + + PT + Pulse Train + Pulse_Train + 0x4003C020 + 32 + read-write + + 0 + 0x0010 + registers + + + + RATE_LENGTH + Pulse Train Configuration + 0x0000 + read-write + + + rate_control + Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train. + 0 + 27 + read-write + + + mode + Pulse Train Output Mode/Train Length + 27 + 5 + read-write + + + 32_BIT + Pulse train, 32 bit pattern. + 0 + + + SQUARE_WAVE + Square wave mode. + 1 + + + 2_BIT + Pulse train, 2 bit pattern. + 2 + + + 3_BIT + Pulse train, 3 bit pattern. + 3 + + + 4_BIT + Pulse train, 4 bit pattern. + 4 + + + 5_BIT + Pulse train, 5 bit pattern. + 5 + + + 6_BIT + Pulse train, 6 bit pattern. + 6 + + + 7_BIT + Pulse train, 7 bit pattern. + 7 + + + 8_BIT + Pulse train, 8 bit pattern. + 8 + + + 9_BIT + Pulse train, 9 bit pattern. + 9 + + + 10_BIT + Pulse train, 10 bit pattern. + 10 + + + 11_BIT + Pulse train, 11 bit pattern. + 11 + + + 12_BIT + Pulse train, 12 bit pattern. + 12 + + + 13_BIT + Pulse train, 13 bit pattern. + 13 + + + 14_BIT + Pulse train, 14 bit pattern. + 14 + + + 15_BIT + Pulse train, 15 bit pattern. + 15 + + + 16_BIT + Pulse train, 16 bit pattern. + 16 + + + 17_BIT + Pulse train, 17 bit pattern. + 17 + + + 18_BIT + Pulse train, 18 bit pattern. + 18 + + + 19_BIT + Pulse train, 19 bit pattern. + 19 + + + 20_BIT + Pulse train, 20 bit pattern. + 20 + + + 21_BIT + Pulse train, 21 bit pattern. + 21 + + + 22_BIT + Pulse train, 22 bit pattern. + 22 + + + 23_BIT + Pulse train, 23 bit pattern. + 23 + + + 24_BIT + Pulse train, 24 bit pattern. + 24 + + + 25_BIT + Pulse train, 25 bit pattern. + 25 + + + 26_BIT + Pulse train, 26 bit pattern. + 26 + + + 27_BIT + Pulse train, 27 bit pattern. + 27 + + + 28_BIT + Pulse train, 28 bit pattern. + 28 + + + 29_BIT + Pulse train, 29 bit pattern. + 29 + + + 30_BIT + Pulse train, 30 bit pattern. + 30 + + + 31_BIT + Pulse train, 31 bit pattern. + 31 + + + + + + + TRAIN + Write the repeating bit pattern that is shifted out, LSB first, when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length. + 0x0004 + read-write + + + LOOP + Pulse Train Loop Count + 0x0008 + read-write + + + count + Number of loops for this pulse train to repeat. + 0 + 16 + read-write + + + delay + Delay between loops of the Pulse Train in PT Peripheral Clock cycles + 16 + 12 + read-write + + + + + RESTART + Pulse Train Auto-Restart Configuration. + 0x000C + read-write + + + pt_x_select + Auto-Restart PT X Select + 0 + 5 + read-write + + + on_pt_x_loop_exit + Enable Auto-Restart on PT X Loop Exit + 7 + 1 + read-write + + + pt_y_select + Auto-Restart PT Y Select + 8 + 5 + read-write + + + on_pt_y_loop_exit + Enable Auto-Restart on PT Y Loop Exit + 15 + 1 + read-write + + + + + + + + PT1 + Pulse Train 1 + 0x4003C030 + + + + PT2 + Pulse Train 2 + 0x4003C040 + + + + PT3 + Pulse Train 3 + 0x4003C050 + + + + PTG + Pulse Train Generation + Pulse_Train + 0x4003C000 + 32 + read-write + + 0 + 0x0018 + registers + + + PT + Pulse Train IRQ + 59 + + + + ENABLE + Global Enable/Disable Controls for All Pulse Trains + 0x0000 + read-write + + + pt0 + Enable/Disable control for PT0 + 0 + 1 + read-write + + + pt1 + Enable/Disable control for PT1 + 1 + 1 + read-write + + + pt2 + Enable/Disable control for PT2 + 2 + 1 + read-write + + + pt3 + Enable/Disable control for PT3 + 3 + 1 + read-write + + + + + RESYNC + Global Resync (All Pulse Trains) Control + 0x0004 + read-write + + + pt0 + Resync control for PT0 + 0 + 1 + read-write + + + pt1 + Resync control for PT1 + 1 + 1 + read-write + + + pt2 + Resync control for PT2 + 2 + 1 + read-write + + + pt3 + Resync control for PT3 + 3 + 1 + read-write + + + + + STOP_INTFL + Pulse Train Stop Interrupt Flags + 0x0008 + read-write + + + pt0 + Pulse Train 0 Stopped Interrupt Flag + 0 + 1 + read-write + + + pt1 + Pulse Train 1 Stopped Interrupt Flag + 1 + 1 + read-write + + + pt2 + Pulse Train 2 Stopped Interrupt Flag + 2 + 1 + read-write + + + pt3 + Pulse Train 3 Stopped Interrupt Flag + 3 + 1 + read-write + + + + + STOP_INTEN + Pulse Train Stop Interrupt Enable/Disable + 0x000C + read-write + + + pt0 + Pulse Train 0 Stopped Interrupt Enable/Disable + 0 + 1 + read-write + + + pt1 + Pulse Train 1 Stopped Interrupt Enable/Disable + 1 + 1 + read-write + + + pt2 + Pulse Train 2 Stopped Interrupt Enable/Disable + 2 + 1 + read-write + + + pt3 + Pulse Train 3 Stopped Interrupt Enable/Disable + 3 + 1 + read-write + + + + + SAFE_EN + Pulse Train Global Safe Enable. + 0x0010 + write-only + + + PT0 + 0 + 1 + write-only + + + PT1 + 1 + 1 + write-only + + + PT2 + 2 + 1 + write-only + + + PT3 + 3 + 1 + write-only + + + + + SAFE_DIS + Pulse Train Global Safe Disable. + 0x0014 + write-only + + + PT0 + 0 + 1 + write-only + + + PT1 + 1 + 1 + write-only + + + PT2 + 2 + 1 + write-only + + + PT3 + 3 + 1 + write-only + + + + + READY_INTFL + Pulse Train Ready Interrupt Flags + 0x0018 + read-write + + + pt0 + Pulse Train 0 Ready Interrupt Flag + 0 + 1 + read-write + + + pt1 + Pulse Train 1 Ready Interrupt Flag + 1 + 1 + read-write + + + pt2 + Pulse Train 2 Ready Interrupt Flag + 2 + 1 + read-write + + + pt3 + Pulse Train 3 Ready Interrupt Flag + 3 + 1 + read-write + + + + + READY_INTEN + Pulse Train Ready Interrupt Enable/Disable + 0x001C + read-write + + + pt0 + Pulse Train 0 Ready Interrupt Enable/Disable + 0 + 1 + read-write + + + pt1 + Pulse Train 1 Ready Interrupt Enable/Disable + 1 + 1 + read-write + + + pt2 + Pulse Train 2 Ready Interrupt Enable/Disable + 2 + 1 + read-write + + + pt3 + Pulse Train 3 Ready Interrupt Enable/Disable + 3 + 1 + read-write + + + + + + + + PWRSEQ + Power Sequencer / Low Power Control Register. + 0x40006800 + + 0x00 + 0x400 + registers + + + + LPCTRL + Low Power Control Register. + 0x00 + + + RAMRET_EN + System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. + 0 + 4 + + + OVR + Operating Voltage Range + 4 + 2 + + + 1_1V + 1.1V + 2 + + + + + RETREG_EN + Retention Regulator Enable. This bit controls the retention regulator in BACKUP mode. + 8 + 1 + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + FASTWK_EN + Fast Wake-Up Mode. This bit enables fast wake-up from DeepSleep mode. (5uS typical). + 10 + 1 + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + BG_DIS + Bandgap OFF. This controls the System Bandgap in DeepSleep mode. + 11 + 1 + + + on + Bandgap is always ON. + 0 + + + off + Bandgap is OFF in DeepSleep mode (default). + 1 + + + + + PORVDDCMON_DIS + VDDC (VCore) Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDC supply in DeepSleep and BACKUP mode. + 12 + 1 + + + VDDIOHHVMON_DIS + VDDIOH High Voltage Monitor Disable. This bit controls the power monitor on VDDIOH supply in all operating modes. + 17 + 1 + + + VDDIOHVMON_DIS + VDDIO High Voltage Monitor Disable. This bit controls the power monitor on VDDIO supply in all operating modes. + 18 + 1 + + + VCOREHVMON_DIS + VCORE High Voltage Monitor Disable. This bit controls the power monitor on VCORE supply in all operating modes. + 19 + 1 + + + VDDCMON_DIS + VDDC (Vcore) Monitor Disable. This bit controls the power monitor on the VCore supply in all operating modes. + 20 + 1 + + + en + Enable if Bandgap is ON (default) + 0 + + + dis + Disabled. + 1 + + + + + VRTCMON_DIS + VRTC Monitor Disable. This bit controls the power monitor on the Always-On Supply in all operating modes. + 21 + 1 + + + en + Enable if Bandgap is ON (default) + 0 + + + dis + Disabled. + 1 + + + + + VDDAMON_DIS + VDDA Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes. + 22 + 1 + + + en + Enable if Bandgap is ON (default) + 0 + + + dis + Disabled. + 1 + + + + + VDDIOMON_DIS + VDDIO Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes. + 23 + 1 + + + en + Enable if Bandgap is ON (default) + 0 + + + dis + Disabled. + 1 + + + + + VDDIOHMON_DIS + VDDIOH Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes. + 24 + 1 + + + en + Enable if Bandgap is ON (default) + 0 + + + dis + Disabled. + 1 + + + + + VDDBMON_DIS + VDDB Monitor Disable. This bit controls the Power-On Reset monitor on VDDB supply in all operating mods. + 27 + 1 + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + + + LPWKFL0 + Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO0. + 0x04 + + + ALL + Wakeup Flags. + 0 + 31 + + + + + LPWKEN0 + Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0. + 0x08 + + + ALL + Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. + 0 + 31 + + + + + LPWKFL1 + Low Power I/O Wakeup Status Register 1. This register indicates the low power wakeup status for GPIO1. + 0x0C + + + LPWKEN1 + Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup functionality for GPIO1. + 0x10 + + + LPWKFL2 + Low Power I/O Wakeup Status Register 2. This register indicates the low power wakeup status for GPIO2. + 0x14 + + + LPWKEN2 + Low Power I/O Wakeup Enable Register 2. This register enables low power wakeup functionality for GPIO2. + 0x18 + + + LPWKFL3 + Low Power I/O Wakeup Status Register 3. This register indicates the low power wakeup status for GPIO3. + 0x1C + + + LPWKEN3 + Low Power I/O Wakeup Enable Register 3. This register enables low power wakeup functionality for GPIO3. + 0x20 + + + LPPWKFL + Low Power Peripheral Wakeup Status Register. + 0x30 + + + USBLS + USB UTMI Linestate Detect Wakeup Flag (write one to clear). One or both of these bits will be set when the USB bus activity causes the linestate to change and the device to wake while USB wakeup is enabled using PMLUSBWKEN. + 0 + 2 + + + AINCOMP0 + Analog Input Comparator Wakeup Flag. + 4 + 1 + + + USBVBUS + USB VBUS Detect Wakeup Flag (write one to clear). This bit will be set when the USB power supply is powered on or powered off. + 2 + 1 + + + BACKUP + Battery Back Wakeup Flag (write one to clear). This bit will be set when exiting Battery Backup Mode. + 16 + 1 + + + RSTDET + Reset Detect Wakeup Flag (write one to clear). This bit will be set when the external reset causes wakeup + 17 + 1 + + + + + LPPWKEN + Low Power Peripheral Wakeup Enable Register. + 0x34 + + + USBLS + USB UTMI Linestate Detect Wakeup Enable. These bits allow wakeup from the corresponding USB linestate signal (s) on transition (s) from low to high or high to low when PM.USBWKEN is set. + 0 + 2 + + + USBVBUS + USB VBUS Detect Wakeup Enable. This bit allows wakeup from the USB power supply on or off status. + 2 + 1 + + + AINCOMP0 + AINCOMP0 Wakeup Enable. This bit allows wakeup from the AINCOMP0. + 4 + 1 + + + WDT0 + WDT0 Wakeup Enable. This bit allows wakeup from the WDT0. + 8 + 1 + + + WDT1 + WDT1 Wakeup Enable. This bit allows wakeup from the WDT1. + 9 + 1 + + + CPU1 + CPU1 Wakeup Enable. This bit allows wakeup from the CPU1. + 10 + 1 + + + TMR0 + TMR0 Wakeup Enable. This bit allows wakeup from the TMR0. + 11 + 1 + + + TMR1 + TMR1 Wakeup Enable. This bit allows wakeup from the TMR1. + 12 + 1 + + + TMR2 + TMR2 Wakeup Enable. This bit allows wakeup from the TMR2. + 13 + 1 + + + TMR3 + TMR3 Wakeup Enable. This bit allows wakeup from the TMR3. + 14 + 1 + + + TMR4 + TMR4 Wakeup Enable. This bit allows wakeup from the TMR4. + 15 + 1 + + + TMR5 + TMR5 Wakeup Enable. This bit allows wakeup from the TMR5. + 16 + 1 + + + UART0 + UART0 Wakeup Enable. This bit allows wakeup from the UART0. + 17 + 1 + + + UART1 + UART1 Wakeup Enable. This bit allows wakeup from the UART1. + 18 + 1 + + + UART2 + UART2 Wakeup Enable. This bit allows wakeup from the UART2. + 19 + 1 + + + UART3 + UART3 Wakeup Enable. This bit allows wakeup from the UART3. + 20 + 1 + + + I2C0 + I2C0 Wakeup Enable. This bit allows wakeup from the I2C0. + 21 + 1 + + + I2C1 + I2C1 Wakeup Enable. This bit allows wakeup from the I2C1. + 22 + 1 + + + I2C2 + I2C2 Wakeup Enable. This bit allows wakeup from the I2C2. + 23 + 1 + + + I2S + I2S Wakeup Enable. This bit allows wakeup from the I2S. + 24 + 1 + + + SPI1 + SPI1 Wakeup Enable. This bit allows wakeup from the SPI1. + 25 + 1 + + + LPCMP + LPCMP Wakeup Enable. This bit allows wakeup from the LPCMP. + 26 + 1 + + + + + LPMEMSD + Low Power Memory Shutdown Control. + 0x40 + + + RAM0 + System RAM block 0 Shut Down. + 0 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + RAM1 + System RAM block 1 Shut Down. + 1 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + RAM2 + System RAM block 2 Shut Down. + 2 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + RAM3 + System RAM block 3 Shut Down. + 3 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + RAM4 + System RAM block 4 Shut Down. + 4 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + RAM5 + System RAM block 5 Shut Down. + 5 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + ICC + Instruction Cache RAM Shut Down. + 7 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + ICCXIP + XiP Instruction Cache RAM Shut Down. + 8 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + SRCC + System Cache RAM Shut Down. + 9 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + USBFIFO + USB FIFO Shut Down. + 11 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + ROM0 + ROM0 Shut Down. (CPU0 ROM) + 12 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + MEU + MEU MEM Shut Down. + 13 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + ROM1 + ROM1 Shut Down. + 15 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + + + LPVDDPD + Low Power VDD Domain Power Down Control. + 0x44 + + + BTLE + Power Down. + 1 + 1 + + + + + GP0 + General Purpose Register 0 + 0x48 + + + GP1 + General Purpose Register 1 + 0x4C + + + LPWKPOL0A + Low Power Wakeup Polarity Select for GPIO0. + 0x50 + + + 0 + Polarity Select for Wakeup Events for Pin 0. + 0 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 1 + Polarity Select for Wakeup Events for Pin 1. + 2 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 2 + Polarity Select for Wakeup Events for Pin 2. + 4 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 3 + Polarity Select for Wakeup Events for Pin 3. + 6 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 4 + Polarity Select for Wakeup Events for Pin 4. + 8 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 5 + Polarity Select for Wakeup Events for Pin 5. + 10 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 6 + Polarity Select for Wakeup Events for Pin 6. + 12 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 7 + Polarity Select for Wakeup Events for Pin 7. + 14 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 8 + Polarity Select for Wakeup Events for Pin 8. + 16 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 9 + Polarity Select for Wakeup Events for Pin 9. + 18 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 10 + Polarity Select for Wakeup Events for Pin 10. + 20 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 11 + Polarity Select for Wakeup Events for Pin 11. + 22 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 12 + Polarity Select for Wakeup Events for Pin 12. + 24 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 13 + Polarity Select for Wakeup Events for Pin 13. + 26 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 14 + Polarity Select for Wakeup Events for Pin 14. + 28 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 15 + Polarity Select for Wakeup Events for Pin 15. + 30 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + + + LPWKPOL0B + Low Power Wakeup Polarity Select for GPIO0. + 0x54 + + + 16 + Polarity Select for Wakeup Events for Pin 16. + 0 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 17 + Polarity Select for Wakeup Events for Pin 17. + 2 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 18 + Polarity Select for Wakeup Events for Pin 18. + 4 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 19 + Polarity Select for Wakeup Events for Pin 19. + 6 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 20 + Polarity Select for Wakeup Events for Pin 20. + 8 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 21 + Polarity Select for Wakeup Events for Pin 21. + 10 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 22 + Polarity Select for Wakeup Events for Pin 22. + 12 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 23 + Polarity Select for Wakeup Events for Pin 23. + 14 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 24 + Polarity Select for Wakeup Events for Pin 24. + 16 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 25 + Polarity Select for Wakeup Events for Pin 25. + 18 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 26 + Polarity Select for Wakeup Events for Pin 26. + 20 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 27 + Polarity Select for Wakeup Events for Pin 27. + 22 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 28 + Polarity Select for Wakeup Events for Pin 28. + 24 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 29 + Polarity Select for Wakeup Events for Pin 29. + 26 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 30 + Polarity Select for Wakeup Events for Pin 30. + 28 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 31 + Polarity Select for Wakeup Events for Pin 31. + 30 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + + + LPWKPOL1A + Low Power Wakeup Polarity Select for GPIO1. + 0x58 + + + 0 + Polarity Select for Wakeup Events for Pin 0. + 0 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 1 + Polarity Select for Wakeup Events for Pin 1. + 2 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 2 + Polarity Select for Wakeup Events for Pin 2. + 4 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 3 + Polarity Select for Wakeup Events for Pin 3. + 6 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 4 + Polarity Select for Wakeup Events for Pin 4. + 8 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 5 + Polarity Select for Wakeup Events for Pin 5. + 10 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 6 + Polarity Select for Wakeup Events for Pin 6. + 12 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 7 + Polarity Select for Wakeup Events for Pin 7. + 14 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 8 + Polarity Select for Wakeup Events for Pin 8. + 16 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 9 + Polarity Select for Wakeup Events for Pin 9. + 18 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 10 + Polarity Select for Wakeup Events for Pin 10. + 20 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 11 + Polarity Select for Wakeup Events for Pin 11. + 22 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 12 + Polarity Select for Wakeup Events for Pin 12. + 24 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 13 + Polarity Select for Wakeup Events for Pin 13. + 26 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 14 + Polarity Select for Wakeup Events for Pin 14. + 28 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 15 + Polarity Select for Wakeup Events for Pin 15. + 30 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + + + LPWKPOL1B + Low Power Wakeup Polarity Select for GPIO1. + 0x5C + + + 16 + Polarity Select for Wakeup Events for Pin 16. + 0 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 17 + Polarity Select for Wakeup Events for Pin 17. + 2 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 18 + Polarity Select for Wakeup Events for Pin 18. + 4 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 19 + Polarity Select for Wakeup Events for Pin 19. + 6 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 20 + Polarity Select for Wakeup Events for Pin 20. + 8 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 21 + Polarity Select for Wakeup Events for Pin 21. + 10 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 22 + Polarity Select for Wakeup Events for Pin 22. + 12 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 23 + Polarity Select for Wakeup Events for Pin 23. + 14 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 24 + Polarity Select for Wakeup Events for Pin 24. + 16 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 25 + Polarity Select for Wakeup Events for Pin 25. + 18 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 26 + Polarity Select for Wakeup Events for Pin 26. + 20 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 27 + Polarity Select for Wakeup Events for Pin 27. + 22 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 28 + Polarity Select for Wakeup Events for Pin 28. + 24 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 29 + Polarity Select for Wakeup Events for Pin 29. + 26 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 30 + Polarity Select for Wakeup Events for Pin 30. + 28 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 31 + Polarity Select for Wakeup Events for Pin 31. + 30 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + + + LPWKPOL2A + Low Power Wakeup Polarity Select for GPIO2. + 0x60 + + + 0 + Polarity Select for Wakeup Events for Pin 0. + 0 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 1 + Polarity Select for Wakeup Events for Pin 1. + 2 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 2 + Polarity Select for Wakeup Events for Pin 2. + 4 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 3 + Polarity Select for Wakeup Events for Pin 3. + 6 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 4 + Polarity Select for Wakeup Events for Pin 4. + 8 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 5 + Polarity Select for Wakeup Events for Pin 5. + 10 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 6 + Polarity Select for Wakeup Events for Pin 6. + 12 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 7 + Polarity Select for Wakeup Events for Pin 7. + 14 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 8 + Polarity Select for Wakeup Events for Pin 8. + 16 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 9 + Polarity Select for Wakeup Events for Pin 9. + 18 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 10 + Polarity Select for Wakeup Events for Pin 10. + 20 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 11 + Polarity Select for Wakeup Events for Pin 11. + 22 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 12 + Polarity Select for Wakeup Events for Pin 12. + 24 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 13 + Polarity Select for Wakeup Events for Pin 13. + 26 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 14 + Polarity Select for Wakeup Events for Pin 14. + 28 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 15 + Polarity Select for Wakeup Events for Pin 15. + 30 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + + + LPWKPOL2B + Low Power Wakeup Polarity Select for GPIO2. + 0x64 + + + 16 + Polarity Select for Wakeup Events for Pin 16. + 0 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 17 + Polarity Select for Wakeup Events for Pin 17. + 2 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 18 + Polarity Select for Wakeup Events for Pin 18. + 4 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 19 + Polarity Select for Wakeup Events for Pin 19. + 6 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 20 + Polarity Select for Wakeup Events for Pin 20. + 8 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 21 + Polarity Select for Wakeup Events for Pin 21. + 10 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 22 + Polarity Select for Wakeup Events for Pin 22. + 12 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 23 + Polarity Select for Wakeup Events for Pin 23. + 14 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 24 + Polarity Select for Wakeup Events for Pin 24. + 16 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 25 + Polarity Select for Wakeup Events for Pin 25. + 18 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 26 + Polarity Select for Wakeup Events for Pin 26. + 20 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 27 + Polarity Select for Wakeup Events for Pin 27. + 22 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 28 + Polarity Select for Wakeup Events for Pin 28. + 24 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 29 + Polarity Select for Wakeup Events for Pin 29. + 26 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 30 + Polarity Select for Wakeup Events for Pin 30. + 28 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 31 + Polarity Select for Wakeup Events for Pin 31. + 30 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + + + LPWKPOL3 + Low Power Wakeup Polarity Select for GPIO3. + 0x68 + + + 0 + Polarity Select for Wakeup Events for Pin 0. + 0 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 1 + Polarity Select for Wakeup Events for Pin 1. + 2 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 2 + Polarity Select for Wakeup Events for Pin 2. + 4 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 3 + Polarity Select for Wakeup Events for Pin 3. + 6 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 4 + Polarity Select for Wakeup Events for Pin 4. + 8 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 5 + Polarity Select for Wakeup Events for Pin 5. + 10 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 6 + Polarity Select for Wakeup Events for Pin 6. + 12 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 7 + Polarity Select for Wakeup Events for Pin 7. + 14 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + + + + + + RTC + Real Time Clock and Alarm. + 0x40006000 + + 0x00 + 0x400 + registers + + + RTC + RTC interrupt. + 3 + + + + SEC + RTC Second Counter. This register contains the 32-bit second counter. + 0x00 + 0x00000000 + + + SEC + Seconds Counter. + 0 + 32 + + + + + SSEC + RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented when this register rolls over from 0xFF to 0x00. + 0x04 + 0x00000000 + + + SSEC + Sub-Seconds Counter (12-bit). + 0 + 12 + + + + + TODA + Time-of-day Alarm. + 0x08 + 0x00000000 + + + TOD_ALARM + Time-of-day Alarm. + 0 + 20 + + + + + SSECA + RTC sub-second alarm. This register contains the reload value for the sub-second alarm. + 0x0C + 0x00000000 + + + SSEC_ALARM + This register contains the reload value for the sub-second alarm. + 0 + 32 + + + + + CTRL + RTC Control Register. + 0x10 + 0x00000008 + 0xFFFFFF38 + + + EN + Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0. + 0 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + TOD_ALARM_IE + Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. + 1 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + SSEC_ALARM_IE + Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. + 2 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + BUSY + RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware. + 3 + 1 + read-only + + + idle + Idle. + 0 + + + busy + Busy. + 1 + + + + + RDY + RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register. + 4 + 1 + + + busy + Register has not updated. + 0 + + + ready + Ready. + 1 + + + + + RDY_IE + RTC Ready Interrupt Enable. + 5 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + TOD_ALARM_IF + Time-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. + 6 + 1 + read-only + + + inactive + Not active. + 0 + + + pending + Active. + 1 + + + + + SSEC_ALARM_IF + Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. + 7 + 1 + read-only + + + inactive + Not active. + 0 + + + pending + Active. + 1 + + + + + SQW_EN + Square Wave Output Enable. + 8 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + SQW_SEL + Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin. + 9 + 2 + + + freq1Hz + 1 Hz (Compensated). + 0 + + + freq512Hz + 512 Hz (Compensated). + 1 + + + freq4KHz + 4 KHz. + 2 + + + + + RD_EN + Asynchronous Counter Read Enable. + 14 + 1 + + + sync + Synchronous. + 0 + + + async + Asynchronous. + 1 + + + + + WR_EN + Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits. + 15 + 1 + + + ignore + Ignored. + 0 + + + allow + Allowed. + 1 + + + + + + + TRIM + RTC Trim Register. + 0x14 + 0x00000000 + + + TRIM + RTC Trim. This register contains the 2's complement value that specifies the trim resolution. Each increment or decrement of the bit adds or subtracts 1ppm at each 4KHz clock value, with a maximum correction of +/- 127ppm. + 0 + 8 + + + VBAT_TMR + VBAT Timer Value. When RTC is running off of VBAT, this field is incremented every 32 seconds. + 8 + 24 + + + + + OSCCTRL + RTC Oscillator Control Register. + 0x18 + 0x00000000 + + + FILTER_EN + Enable Filter. + 0 + 1 + + + IBIAS_SEL + IBIAS Select. + 1 + 1 + + + 2x + 2x + 0 + + + 4x + 4x + 1 + + + + + HYST_EN + RTC Hysteresis Enable. + 2 + 1 + + + IBIAS_EN + RTC IBIAS Enable. + 3 + 1 + + + BYPASS + RTC Crystal Bypass + 4 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + SQW_32K + RTC 32kHz Square Wave Output + 5 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + + + + + + SEMA + The Semaphore peripheral allows multiple cores in a system to cooperate when accessing shred resources. + The peripheral contains eight semaphores that can be atomically set and cleared. It is left to the discretion of the software + architect to decide how and when the semaphores are used and how they are allocated. Existing hardware does not have to be + + modified for this type of cooperative sharing, and the use of semaphores is exclusively within the software domain. + 0x4003E000 + + 0x00 + 0x1000 + registers + + + + 8 + 4 + SEMAPHORES[%s] + Read to test and set, returns prior value. Write 0 to clear semaphore. + 0x00 + 32 + + + sema + 0 + 1 + + + + + irq0 + Semaphore IRQ0 register. + 0x40 + 32 + + + en + 0 + 1 + + + cm4_irq + 16 + 1 + + + + + mail0 + Semaphore Mailbox 0 register. + 0x44 + 32 + + + data + 0 + 32 + + + + + irq1 + Semaphore IRQ1 register. + 0x48 + 32 + + + en + 0 + 1 + + + rv32_irq + 16 + 1 + + + + + mail1 + Semaphore Mailbox 1 register. + 0x4C + 32 + + + data + 0 + 32 + + + + + status + Semaphore status bits. 0 indicates the semaphore is free, 1 indicates taken. + 0x100 + 32 + + + status0 + 0 + 1 + + + status1 + 1 + 1 + + + status2 + 2 + 1 + + + status3 + 3 + 1 + + + status4 + 4 + 1 + + + status5 + 5 + 1 + + + status6 + 6 + 1 + + + status7 + 7 + 1 + + + + + + + + SIMO + Single Inductor Multiple Output Switching Converter + 0x40004400 + + 0x00 + 0x400 + registers + + + + VREGO_A + Buck Voltage Regulator A Control Register + 0x0004 + read-write + + + VSETA + Regulator Output Voltage Setting + 0 + 7 + + + RANGEA + Regulator Output Range Set + 7 + 1 + + + low + Low output voltage range + 0 + + + high + High output voltage range + 1 + + + + + + + VREGO_B + Buck Voltage Regulator B Control Register + 0x0008 + read-write + + + VSETB + Regulator Output Voltage Setting + 0 + 7 + + + RANGEB + Regulator Output Range Set + 7 + 1 + + + low + Low output voltage range + 0 + + + high + High output voltage range + 1 + + + + + + + VREGO_C + Buck Voltage Regulator C Control Register + 0x000C + read-write + + + VSETC + Regulator Output Voltage Setting + 0 + 7 + + + RANGEC + Regulator Output Range Set + 7 + 1 + + + low + Low output voltage range + 0 + + + high + High output voltage range + 1 + + + + + + + VREGO_D + Buck Voltage Regulator D Control Register + 0x0010 + read-write + + + VSETD + Regulator Output Voltage Setting + 0 + 7 + + + RANGED + Regulator Output Range Set + 7 + 1 + + + low + Low output voltage range + 0 + + + high + High output voltage range + 1 + + + + + + + IPKA + High Side FET Peak Current VREGO_A/VREGO_B Register + 0x0014 + read-write + + + IPKSETA + Voltage Regulator Peak Current Setting + 0 + 4 + + + IPKSETB + Voltage Regulator Peak Current Setting + 4 + 4 + + + + + IPKB + High Side FET Peak Current VREGO_C/VREGO_D Register + 0x0018 + read-write + + + IPKSETC + Voltage Regulator Peak Current Setting + 0 + 4 + + + IPKSETD + Voltage Regulator Peak Current Setting + 4 + 4 + + + + + MAXTON + Maximum High Side FET Time On Register + 0x001C + read-write + + + TONSET + Sets the maximum on time for the high side FET, each increment represents 500ns + 0 + 4 + + + + + ILOAD_A + Buck Cycle Count VREGO_A Register + 0x0020 + read-only + + + ILOADA + Number of buck cycles that occur within the cycle clock + 0 + 8 + + + + + ILOAD_B + Buck Cycle Count VREGO_B Register + 0x0024 + read-only + + + ILOADB + Number of buck cycles that occur within the cycle clock + 0 + 8 + + + + + ILOAD_C + Buck Cycle Count VREGO_C Register + 0x0028 + read-only + + + ILOADC + Number of buck cycles that occur within the cycle clock + 0 + 8 + + + + + ILOAD_D + Buck Cycle Count VREGO_D Register + 0x002C + read-only + + + ILOADD + Number of buck cycles that occur within the cycle clock + 0 + 8 + + + + + BUCK_ALERT_THR_A + Buck Cycle Count Alert VERGO_A Register + 0x0030 + read-write + + + BUCKTHRA + Threshold for ILOADA to generate the BUCK_ALERT + 0 + 8 + + + + + BUCK_ALERT_THR_B + Buck Cycle Count Alert VERGO_B Register + 0x0034 + read-write + + + BUCKTHRB + Threshold for ILOADB to generate the BUCK_ALERT + 0 + 8 + + + + + BUCK_ALERT_THR_C + Buck Cycle Count Alert VERGO_C Register + 0x0038 + read-write + + + BUCKTHRC + Threshold for ILOADC to generate the BUCK_ALERT + 0 + 8 + + + + + BUCK_ALERT_THR_D + Buck Cycle Count Alert VERGO_D Register + 0x003C + read-write + + + BUCKTHRD + Threshold for ILOADD to generate the BUCK_ALERT + 0 + 8 + + + + + BUCK_OUT_READY + Buck Regulator Output Ready Register + 0x0040 + read-only + + + BUCKOUTRDYA + When set, indicates that the output voltage has reached its regulated value + 0 + 1 + + + notrdy + Output voltage not in range + 0 + + + rdy + Output voltage in range + 1 + + + + + BUCKOUTRDYB + When set, indicates that the output voltage has reached its regulated value + 1 + 1 + + + BUCKOUTRDYC + When set, indicates that the output voltage has reached its regulated value + 2 + 1 + + + BUCKOUTRDYD + When set, indicates that the output voltage has reached its regulated value + 3 + 1 + + + + + ZERO_CROSS_CAL_A + Zero Cross Calibration VERGO_A Register + 0x0044 + read-only + + + ZXCALA + Zero Cross Calibrartion Value VREGO_A + 0 + 4 + + + + + ZERO_CROSS_CAL_B + Zero Cross Calibration VERGO_B Register + 0x0048 + read-only + + + ZXCALB + Zero Cross Calibrartion Value VREGO_B + 0 + 4 + + + + + ZERO_CROSS_CAL_C + Zero Cross Calibration VERGO_C Register + 0x004C + read-only + + + ZXCALC + Zero Cross Calibrartion Value VREGO_C + 0 + 4 + + + + + ZERO_CROSS_CAL_D + Zero Cross Calibration VERGO_D Register + 0x0050 + read-only + + + ZXCALD + Zero Cross Calibrartion Value VREGO_D + 0 + 4 + + + + + + + + SIR + System Initialization Registers. + 0x40000400 + read-only + + 0x00 + 0x400 + registers + + + + SISTAT + System Initialization Status Register. + 0x00 + read-only + + + MAGIC + Magic Word Validation. This bit is set by the system initialization block following power-up. + 0 + 1 + read-only + + read + + magicNotSet + Magic word was not set (OTP has not been initialized properly). + 0 + + + magicSet + Magic word was set (OTP contains valid settings). + 1 + + + + + CRCERR + CRC Error Status. This bit is set by the system initialization block following power-up. + 1 + 1 + read-only + + read + + noError + No CRC errors occurred during the read of the OTP memory block. + 0 + + + error + A CRC error occurred while reading the OTP. The address of the failure location in the OTP memory is stored in the ERRADDR register. + 1 + + + + + + + ADDR + Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1). + 0x04 + read-only + + + ERRADDR + 0 + 32 + + + + + BTLELDOTRIM + BTLE LDO Trim register. + 0x48 + read-write + + + TX + TX LDO trim value. + 0 + 5 + read-write + + + RX + RX LDO trim value. + 8 + 5 + read-write + + + + + FSTAT + funcstat register. + 0x100 + read-only + + + FPU + FPU Function. + 0 + 1 + + + no + 0 + + + yes + 1 + + + + + ADC + 10-bit Sigma Delta ADC. + 2 + 1 + + + no + 0 + + + yes + 1 + + + + + SEMA + Semaphore function. + 7 + 1 + + + no + 0 + + + yes + 1 + + + + + + + SFSTAT + Security function status register. + 0x104 + read-only + + + SECBOOT + Security Boot. + 0 + 1 + + + TRNG + TRNG Function. + 2 + 1 + + + no + 0 + + + yes + 1 + + + + + AES + AES Block. + 3 + 1 + + + no + 0 + + + yes + 1 + + + + + + + + + + SPI + SPI peripheral. + 0x400BE000 + + 0x00 + 0x1000 + registers + + + SPI0 + 56 + + + + FIFO32 + Register for reading and writing the FIFO. + 0x00 + 32 + read-write + + + DATA + Read to pull from RX FIFO, write to put into TX FIFO. + 0 + 32 + + + + + 2 + 2 + FIFO16[%s] + Register for reading and writing the FIFO. + FIFO32 + 0x00 + 16 + read-write + + + DATA + Read to pull from RX FIFO, write to put into TX FIFO. + 0 + 16 + + + + + 4 + 1 + FIFO8[%s] + Register for reading and writing the FIFO. + FIFO32 + 0x00 + 8 + read-write + + + DATA + Read to pull from RX FIFO, write to put into TX FIFO. + 0 + 8 + + + + + CTRL0 + Register for controlling SPI peripheral. + 0x04 + read-write + + + EN + SPI Enable. + 0 + 1 + + + dis + SPI is disabled. + 0 + + + en + SPI is enabled. + 1 + + + + + MST_MODE + Master Mode Enable. + 1 + 1 + + + dis + SPI is Slave mode. + 0 + + + en + SPI is Master mode. + 1 + + + + + SS_IO + Slave Select 0, IO direction, to support Multi-Master mode,Slave Select 0 can be input in Master mode. This bit has no effect in slave mode. + 4 + 1 + + + output + Slave select 0 is output. + 0 + + + input + Slave Select 0 is input, only valid if MMEN=1. + 1 + + + + + START + Start Transmit. + 5 + 1 + + + start + Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction. + 1 + + + + + SS_CTRL + Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction. + 8 + 1 + + + DEASSERT + SPI De-asserts Slave Select at the end of a transaction. + 0 + + + ASSERT + SPI leaves Slave Select asserted at the end of a transaction. + 1 + + + + + SS_ACTIVE + Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected. + 16 + 4 + + + SS0 + SS0 is selected. + 0x1 + + + SS1 + SS1 is selected. + 0x2 + + + SS2 + SS2 is selected. + 0x4 + + + SS3 + SS3 is selected. + 0x8 + + + + + + + CTRL1 + Register for controlling SPI peripheral. + 0x08 + read-write + + + TX_NUM_CHAR + Nubmer of Characters to transmit. + 0 + 16 + + + RX_NUM_CHAR + Nubmer of Characters to receive. + 16 + 16 + + + + + CTRL2 + Register for controlling SPI peripheral. + 0x0C + read-write + + + CLKPHA + Clock Phase. + 0 + 1 + + + Rising_Edge + Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2 + 0 + + + Falling_Edge + Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3 + 1 + + + + + CLKPOL + Clock Polarity. + 1 + 1 + + + Normal + Normal Clock. Use when in SPI Mode 0 and Mode 1 + 0 + + + Inverted + Inverted Clock. Use when in SPI Mode 2 and Mode 3 + 1 + + + + + SCLK_FB_INV + Clock Polarity. + 4 + 1 + + + Normal + Normal Clock. Use when in SPI Mode 0 and Mode 1 + 0 + + + Inverted + Inverted Clock. Use when in SPI Mode 2 and Mode 3 + 1 + + + + + NUMBITS + Number of Bits per character. + 8 + 4 + + + 16 + 16 bits per character. + 0 + + + 1 + 1 bits per character. + 1 + + + 2 + 2 bits per character. + 2 + + + 3 + 3 bits per character. + 3 + + + 4 + 4 bits per character. + 4 + + + 5 + 5 bits per character. + 5 + + + 6 + 6 bits per character. + 6 + + + 7 + 7 bits per character. + 7 + + + 8 + 8 bits per character. + 8 + + + 9 + 9 bits per character. + 9 + + + 10 + 10 bits per character. + 10 + + + 11 + 11 bits per character. + 11 + + + 12 + 12 bits per character. + 12 + + + 13 + 13 bits per character. + 13 + + + 14 + 14 bits per character. + 14 + + + 15 + 15 bits per character. + 15 + + + + + DATA_WIDTH + SPI Data width. + 12 + 2 + + + Mono + 1 data pin. + 0 + + + Dual + 2 data pins. + 1 + + + Quad + 4 data pins. + 2 + + + + + THREE_WIRE + Three Wire mode. MOSI/MISO pin(s) shared. Only Mono mode suports Four-Wire. + 15 + 1 + + + dis + Use four wire mode (Mono only). + 0 + + + en + Use three wire mode. + 1 + + + + + SSPOL + Slave Select Polarity, each Slave Select can have unique polarity. + 16 + 4 + + + SS0_high + SS0 active high. + 0x1 + + + SS1_high + SS1 active high. + 0x2 + + + SS2_high + SS2 active high. + 0x4 + + + SS3_high + SS3 active high. + 0x8 + + + + + + + SSTIME + Register for controlling SPI peripheral/Slave Select Timing. + 0x10 + read-write + + + PRE + Slave Select Pre delay 1. + 0 + 8 + + + 256 + 256 system clocks between SS active and first serial clock edge. + 0 + + + + + POST + Slave Select Post delay 2. + 8 + 8 + + + 256 + 256 system clocks between last serial clock edge and SS inactive. + 0 + + + + + INACT + Slave Select Inactive delay. + 16 + 8 + + + 256 + 256 system clocks between transactions. + 0 + + + + + + + CLKCTRL + Register for controlling SPI clock rate. + 0x14 + read-write + + + LO + Low duty cycle control. In timer mode, reload[7:0]. + 0 + 8 + + + Dis + Duty cycle control of serial clock generation is disabled. + 0 + + + + + HI + High duty cycle control. In timer mode, reload[15:8]. + 8 + 8 + + + Dis + Duty cycle control of serial clock generation is disabled. + 0 + + + + + CLKDIV + System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock. + 16 + 4 + + + + + DMA + Register for controlling DMA. + 0x1C + read-write + + + TX_THD_VAL + Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered. + 0 + 5 + + + TX_FIFO_EN + Transmit FIFO enabled for SPI transactions. + 6 + 1 + + + dis + Transmit FIFO is not enabled. + 0 + + + en + Transmit FIFO is enabled. + 1 + + + + + TX_FLUSH + Clear TX FIFO, clear is accomplished by resetting the read and write + pointers. This should be done when FIFO is not being accessed on the SPI side. + . + 7 + 1 + + + CLEAR + Clear the Transmit FIFO, clears any pending TX FIFO status. + 1 + + + + + TX_LVL + Count of entries in TX FIFO. + 8 + 6 + read-only + + + TX_EN + TX DMA Enable. + 15 + 1 + + + DIS + TX DMA requests are disabled, andy pending DMA requests are cleared. + 0 + + + en + TX DMA requests are enabled. + 1 + + + + + RX_THD_VAL + Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered. + 16 + 5 + + + RX_FIFO_EN + Receive FIFO enabled for SPI transactions. + 22 + 1 + + + DIS + Receive FIFO is not enabled. + 0 + + + en + Receive FIFO is enabled. + 1 + + + + + RX_FLUSH + Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side. + 23 + 1 + + + CLEAR + Clear the Receive FIFO, clears any pending RX FIFO status. + 1 + + + + + RX_LVL + Count of entries in RX FIFO. + 24 + 6 + read-only + + + RX_EN + RX DMA Enable. + 31 + 1 + + + dis + RX DMA requests are disabled, any pending DMA requests are cleared. + 0 + + + en + RX DMA requests are enabled. + 1 + + + + + + + INTFL + Register for reading and clearing interrupt flags. All bits are write 1 to clear. + 0x20 + read-write + + + TX_THD + TX FIFO Threshold Crossed. + 0 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TX_EM + TX FIFO Empty. + 1 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_THD + RX FIFO Threshold Crossed. + 2 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_FULL + RX FIFO FULL. + 3 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + SSA + Slave Select Asserted. + 4 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + SSD + Slave Select Deasserted. + 5 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + FAULT + Multi-Master Mode Fault. + 8 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + ABORT + Slave Abort Detected. + 9 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + MST_DONE + Master Done, set when SPI Master has completed any transactions. + 11 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TX_OV + Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO. + 12 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TX_UN + Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO. + 13 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_OV + Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO. + 14 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_UN + Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO. + 15 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + + + INTEN + Register for enabling interrupts. + 0x24 + read-write + + + TX_THD + TX FIFO Threshold interrupt enable. + 0 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + TX_EM + TX FIFO Empty interrupt enable. + 1 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + RX_THD + RX FIFO Threshold Crossed interrupt enable. + 2 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + RX_FULL + RX FIFO FULL interrupt enable. + 3 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + SSA + Slave Select Asserted interrupt enable. + 4 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + SSD + Slave Select Deasserted interrupt enable. + 5 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + FAULT + Multi-Master Mode Fault interrupt enable. + 8 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + ABORT + Slave Abort Detected interrupt enable. + 9 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + MST_DONE + Master Done interrupt enable. + 11 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + TX_OV + Transmit FIFO Overrun interrupt enable. + 12 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + TX_UN + Transmit FIFO Underrun interrupt enable. + 13 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + RX_OV + Receive FIFO Overrun interrupt enable. + 14 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + RX_UN + Receive FIFO Underrun interrupt enable. + 15 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + + + WKFL + Register for wake up flags. All bits in this register are write 1 to clear. + 0x28 + read-write + + + TX_THD + Wake on TX FIFO Threshold Crossed. + 0 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TX_EM + Wake on TX FIFO Empty. + 1 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_THD + Wake on RX FIFO Threshold Crossed. + 2 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_FULL + Wake on RX FIFO Full. + 3 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + + + WKEN + Register for wake up enable. + 0x2C + read-write + + + TX_THD + Wake on TX FIFO Threshold Crossed Enable. + 0 + 1 + + + dis + Wakeup source disabled. + 0 + + + en + Wakeup source enabled. + 1 + + + + + TX_EM + Wake on TX FIFO Empty Enable. + 1 + 1 + + + dis + Wakeup source disabled. + 0 + + + en + Wakeup source enabled. + 1 + + + + + RX_THD + Wake on RX FIFO Threshold Crossed Enable. + 2 + 1 + + + dis + Wakeup source disabled. + 0 + + + en + Wakeup source enabled. + 1 + + + + + RX_FULL + Wake on RX FIFO Full Enable. + 3 + 1 + + + dis + Wakeup source disabled. + 0 + + + en + Wakeup source enabled. + 1 + + + + + + + STATUS + SPI Status register. + 0x30 + read-only + + + BUSY + SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. + 0 + 1 + + + not + SPI not active. + 0 + + + active + SPI active. + 1 + + + + + + + + + + SPI1 + SPI peripheral. 1 + 0x40046000 + + SPI1 + SPI1 IRQ + 32 + + + + + TMR0 + 32-bit reloadable timer that can be used for timing and event counting. + Timers + 0x40010000 + + 0x00 + 0x1000 + registers + + + TMR0 + TMR0 IRQ + 5 + + + + CNT + Count. This register stores the current timer count. + 0x00 + 0x00000001 + + + COUNT + Count. + 0 + 32 + + + + + CMP + Compare. This register stores the compare value, which is used to set the maximum count value to initiate a reload of the timer to 0x0001. + 0x04 + 0x0000FFFF + + + COMPARE + Compare. + 0 + 32 + + + + + PWM + PWM. This register stores the value that is compared to the current timer count. + 0x08 + + + PWM + PWM + 0 + 32 + + + + + INTFL + Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt. + 0x0C + oneToClear + + + IRQ + Clear Interrupt. + 0 + 1 + + + + + CTRL + Timer Control Register. + 0x10 + + + MODE + Timer Mode. + 0 + 3 + + + oneShot + One Shot Mode. + 0 + + + continuous + Continuous Mode. + 1 + + + counter + Counter Mode. + 2 + + + pwm + PWM Mode. + 3 + + + capture + Capture Mode. + 4 + + + compare + Compare Mode. + 5 + + + gated + Gated Mode. + 6 + + + captureCompare + Capture/Compare Mode. + 7 + + + + + CLKDIV + Prescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock, F_CNT_CLK = PCLK (HZ) /prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres[2:0]. + 3 + 3 + + + div1 + Divide by 1. + 0 + + + div2 + Divide by 2. + 1 + + + div4 + Divide by 4. + 2 + + + div8 + Divide by 8. + 3 + + + div16 + Divide by 16. + 4 + + + div32 + Divide by 32. + 5 + + + div64 + Divide by 64. + 6 + + + div128 + Divide by 128. + 7 + + + + + POL + Timer input/output polarity bit. + 6 + 1 + + + activeHi + Active High. + 0 + + + activeLo + Active Low. + 1 + + + + + EN + Timer Enable. + 7 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + CLKDIV3 + MSB of prescaler value. + 8 + 1 + + + PWMSYNC + Timer PWM Synchronization Mode Enable. + 9 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + NOLHPOL + Timer PWM output 0A polarity bit. + 10 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + NOLLPOL + Timer PWM output 0A' polarity bit. + 11 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + PWMCKBD + Timer PWM output 0A Mode Disable. + 12 + 1 + + + dis + Disable. + 1 + + + en + Enable. + 0 + + + + + + + NOLCMP + Timer Non-Overlapping Compare Register. + 0x14 + + + LO + Non-overlapping Low Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A and next rising edge of PWM output 0A'. + 0 + 8 + + + HI + Non-overlapping High Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A' and next rising edge of PWM output 0A. + 8 + 8 + + + + + + + + TMR1 + 32-bit reloadable timer that can be used for timing and event counting. 1 + 0x40011000 + + TMR1 + TMR1 IRQ + 6 + + + + + TMR2 + 32-bit reloadable timer that can be used for timing and event counting. 2 + 0x40012000 + + TMR2 + TMR2 IRQ + 7 + + + + + TMR3 + 32-bit reloadable timer that can be used for timing and event counting. 3 + 0x40013000 + + TMR3 + TMR3 IRQ + 8 + + + + + TMR4 + 32-bit reloadable timer that can be used for timing and event counting. 4 + 0x40080C00 + + TMR4 + TMR4 IRQ + 9 + + + + + TMR5 + 32-bit reloadable timer that can be used for timing and event counting. 5 + 0x40081000 + + TMR5 + TMR5 IRQ + 10 + + + + + TRIMSIR + Trim System Initilazation Registers + 0x40005400 + + 0x00 + 0x400 + registers + + + + RTC + RTC Trim System Initialization Register. + 0x08 + + + X1TRIM + RTC X1 Trim. + 16 + 5 + + + X2TRIM + RTC X2 Trim. + 21 + 5 + + + LOCK + Lock. + 31 + 1 + + + + + SIMO + SIMO Trim System Initialization Register. + 0x34 + read-only + + + CLKDIV + SIMO Clock Divide. + 0 + 3 + + + DIV1 + 0 + + + DIV16 + 1 + + + DIV32 + 3 + + + DIV64 + 5 + + + DIV128 + 7 + + + + + + + IPOLO + IPO Low Trim System Initialization Register. + 0x3C + read-only + + + IPO_LIMITLO + IPO Low Limit Trim. + 0 + 8 + + + + + CTRL + Control Trim System Initialization Register. + 0x40 + + + VDDA_LIMITLO + VDDA Low Trim Limit. + 0 + 7 + + + VDDA_LIMITHI + VDDA High Trim Limit. + 8 + 7 + + + IPO_LIMITHI + IPO High Trim Limit. + 15 + 9 + + + INRO_SEL + INRO Clock Select. + 24 + 2 + + + 8KHZ + 0 + + + 16KHZ + 1 + + + 30KHZ + 2 + + + + + INRO_TRIM + INRO Clock Trim. + 29 + 3 + + + + + INRO + RTC Trim System Initialization Register. + 0x44 + + + TRIM16K + INRO 16KHz Trim. + 0 + 3 + + + TRIM30K + INRO 30KHz Trim. + 3 + 3 + + + LPCLKSEL + INRO Low Power Mode Clock Select. + 6 + 2 + + + 8KHZ + 0 + + + 16KHZ + 1 + + + 30KHZ + 2 + + + + + + + + + + TRNG + Random Number Generator. + 0x4004D000 + + 0x00 + 0x1000 + registers + + + TRNG + TRNG interrupt. + 4 + + + + CTRL + TRNG Control Register. + 0x00 + 0x00000003 + + + OD_HEALTH + Start On-Demand health test. + 0 + 1 + + + RND_IE + To enable IRQ generation when a new 32-bit Random number is ready. + 1 + 1 + + + disable + Disable + 0 + + + enable + Enable + 1 + + + + + HEALTH_IE + Enable IRQ generation when a health test fails. + 2 + 1 + + + AESKG_MEU + Generate and transfer 256 bit MEU key to AES Key storage. + 3 + 1 + + + AESKG_MEMPROT_XIP + Generate and transfer 128 bit MEMPROT_XIP key to AES key storage. + 4 + 1 + + + AESKG_MEMPROT_DIP + Generate and transfer 128 bit MEMPROT_DIP key to AES key storage. + 5 + 1 + + + OD_ROMON + Start ring oscillator monitor on demand test. + 6 + 1 + + + OD_EE + Start entropy estimator on demand test. + 7 + 1 + + + ROMON_EE_FOE + Ring Oscillator Monitors and Entropy Estimator Freeze on Error. + 8 + 1 + + + ROMON_EE_FOD + Ring Oscillator Monitors and Entropy Estimator Freeze on Done. + 9 + 1 + + + EBLS + Entropy Bit Load Select. + 10 + 1 + + + KEYWIPE + To wipe the Battery Backed key. + 15 + 1 + + + GET_TERO_CNT + Get Tero Count. + 16 + 1 + + + EE_DONE_IE + Entropy Estimator Done Interrupt Enable. + 23 + 1 + + + ROMON_DIS + Ring Oscillator Disable. + 24 + 3 + + + RO_0 + Ring Oscillator 0. + 1 + + + RO_1 + Ring Oscillator 1. + 2 + + + RO_2 + Ring Oscillator 2. + 4 + + + + + ROMON_DIV2 + Divide ring by 2. + 28 + 3 + + + RO_0 + Ring Oscillator 0. + 0 + + + RO_1 + Ring Oscillator 1. + 1 + + + RO_2 + Ring Oscillator 2. + 2 + + + + + + + STATUS + Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000. + 0x04 + + + RDY + 32-bit random data is ready to read from TRNG_DATA register. Reading TRNG_DATA when RND_RDY=0 will return all 0's. IRQ is generated when RND_RDY=1 if TRNG_CN.RND_IRQ_EN=1. + 0 + 1 + + + Busy + TRNG Busy + 0 + + + Ready + 32 bit random data is ready + 1 + + + + + OD_HEALTH + On-Demand health test status. + 1 + 1 + + + HEALTH + Health test status. + 2 + 1 + + + SRCFAIL + Entropy source has failed. + 3 + 1 + + + AES_KEYGEN + AESKGD. + 4 + 1 + + + OD_ROMON + On demand ring oscillator test status. + 6 + 1 + + + OD_EE + On demand entropy estimator status. + 7 + 1 + + + PP_ERR + Post process error. + 8 + 1 + + + ROMON_0_ERR + Ring Oscillator 0 Monitor Error. + 9 + 1 + + + ROMON_1_ERR + Ring Oscillator 1 Monitor Error. + 10 + 1 + + + ROMON_2_ERR + Ring Oscillator 2 Monitor Error. + 11 + 1 + + + EE_ERR_THR + Entropy Estimator Threshold Error. + 12 + 1 + + + EE_ERR_OOB + Entropy Estimator Out of Bounds Error.. + 13 + 1 + + + EE_ERR_LOCK + Entropy Estimator Lock Error. + 14 + 1 + + + TERO_CNT_RDY + TERO Count Ready. + 16 + 1 + + + RC_ERR + Repetition Count Error. + 17 + 1 + + + AP_ERR + Adaptive Proportion Error. + 18 + 1 + + + DATA_DONE + Data register has been loaded with at least 32 new entropy bits. + 19 + 1 + + + DATA_NIST_DONE + Data NIST register has been loaded with at least 32 new entropy bits. + 20 + 1 + + + HEALTH_DONE + Health Test Done. + 21 + 1 + + + ROMON_DONE + Ring Oscillator Monitor Test Done. + 22 + 1 + + + EE_DONE + Entropy Estimator Test Done. + 23 + 1 + + + + + DATA + Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000. + 0x08 + read-only + + + DATA + Data. The content of this register is valid only when RNG_IS =1. When TNRG is disabled, read returns 0x0000 0000. + 0 + 32 + + + + + DATA_NIST + Data NIST Register. + 0x38 + + + DATA + Ring Oscillator 1 Monitor Last Ring Oscillator Count. + 0 + 32 + + + + + + + + UART + UART Low Power Registers + 0x40042000 + + 0x00 + 0x1000 + registers + + + + CTRL + Control register + 0x0000 + + + RX_THD_VAL + This field specifies the depth of receive FIFO for interrupt generation (value 0 and > 16 are ignored) + 0 + 4 + + + PAR_EN + Parity Enable + 4 + 1 + + + PAR_EO + when PAREN=1 selects odd or even parity odd is 1 even is 0 + 5 + 1 + + + PAR_MD + Selects parity based on 1s or 0s count (when PAREN=1) + 6 + 1 + + + CTS_DIS + CTS Sampling Disable + 7 + 1 + + + TX_FLUSH + Flushes the TX FIFO buffer. This bit is automatically cleared by hardware when flush is completed. + 8 + 1 + + + RX_FLUSH + Flushes the RX FIFO buffer. This bit is automatically cleared by hardware when flush is completed. + 9 + 1 + + + CHAR_SIZE + Selects UART character size + 10 + 2 + + + 5bits + 5 bits + 0 + + + 6bits + 6 bits + 1 + + + 7bits + 7 bits + 2 + + + 8bits + 8 bits + 3 + + + + + STOPBITS + Selects the number of stop bits that will be generated + 12 + 1 + + + HFC_EN + Enables/disables hardware flow control + 13 + 1 + + + RTS_NEG + The condition to negate RTS in HFC mode. + 14 + 1 + + + CLK_EN + Baud clock enable + 15 + 1 + + + CLK_SEL + To select the UART clock source for the UART engine (except APB registers). Secondary clock (used for baud rate generator) can be asynchronous from APB clock. + 16 + 2 + + + Peripheral_Clock + apb clock + 0 + + + External_Clock + Clock 1 + 1 + + + CLK2 + Clock 2 + 2 + + + CLK3 + Clock 3 + 3 + + + + + CLK_RDY + Baud clock Ready read only bit + 19 + 1 + + + CLK_GATE + UART Clock Auto Gating mode + 20 + 1 + + + + + STATUS + Status register + 0x0004 + read-only + + + TX_BUSY + Read-only flag indicating the UART transmit status + 0 + 1 + + + RX_BUSY + Read-only flag indicating the UART receiver status + 1 + 1 + + + RX_EM + Read-only flag indicating the RX FIFO state + 4 + 1 + + + RX_FULL + Read-only flag indicating the RX FIFO state + 5 + 1 + + + TX_EM + Read-only flag indicating the TX FIFO state + 6 + 1 + + + TX_FULL + Read-only flag indicating the TX FIFO state + 7 + 1 + + + RX_LVL + Indicates the number of bytes currently in the RX FIFO (0-RX FIFO_ELTS) + 8 + 4 + + + TX_LVL + Indicates the number of bytes currently in the TX FIFO (0-TX FIFO_ELTS) + 12 + 4 + + + + + INTEN + Interrupt Enable control register + 0x0008 + + + RX_FERR + Enable Interrupt For RX Frame Error + 0 + 1 + + + RX_PAR + Enable Interrupt For RX Parity Error + 1 + 1 + + + CTS_EV + Enable Interrupt For CTS signal change Error + 2 + 1 + + + RX_OV + Enable Interrupt For RX FIFO Overrun Error + 3 + 1 + + + RX_THD + Enable Interrupt For RX FIFO reaches the number of bytes configured by RXTHD + 4 + 1 + + + TX_OB + Enable Interrupt For TX FIFO when only one byte is remaining. + 5 + 1 + + + TX_HE + Enable Interrupt For TX FIFO has half empty + 6 + 1 + + + RX_FULL + Enable for RX FIFO Full interrupt. + 7 + 1 + + + + + INTFL + Interrupt status flags Control register + 0x000C + + + RX_FERR + Flag for RX Frame Error Interrupt. + 0 + 1 + + + RX_PAR + Flag for RX Parity Error interrupt + 1 + 1 + + + CTS_EV + Flag for CTS signal change interrupt (hardware flow control disabled) + 2 + 1 + + + RX_OV + Flag for RX FIFO Overrun interrupt + 3 + 1 + + + RX_THD + Flag for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field + 4 + 1 + + + TX_OB + Flag for interrupt when TX FIFO has only one byte is remaining. + 5 + 1 + + + TX_HE + Flag for interrupt when TX FIFO is half empty + 6 + 1 + + + RX_FULL + Flag for full RX FIFO. + 7 + 1 + + + + + CLKDIV + Clock Divider register + 0x0010 + + + CLKDIV + Baud rate divisor value + 0 + 20 + + + + + OSR + Over Sampling Rate register + 0x0014 + + + OSR + OSR + 0 + 3 + + + + + TXPEEK + TX FIFO Output Peek register + 0x0018 + + + DATA + Read TX FIFO next data. Reading from this field does not affect the contents of TX FIFO. Note that the parity bit is available from this field. + 0 + 8 + + + + + PIN + Pin register + 0x001C + + + CTS + Current sampled value of CTS IO + 0 + 1 + read-only + + + RTS + This bit controls the value to apply on the RTS IO. If set to 1, the RTS IO is set to high level. If set to 0, the RTS IO is set to low level. + 1 + 1 + + + + + FIFO + FIFO Read/Write register + 0x0020 + + + DATA + Load/unload location for TX and RX FIFO buffers. + 0 + 8 + + + RX_PAR + Parity error flag for next byte to be read from FIFO. + 8 + 1 + + + + + DMA + DMA Configuration register + 0x0030 + + + TX_THD_VAL + TX FIFO Level DMA Trigger If the TX FIFO level is less than this value, then the TX FIFO DMA interface will send a signal to system DMA to notify that TX FIFO is ready to receive data from memory. + 0 + 4 + + + TX_EN + TX DMA channel enable + 4 + 1 + + + RX_THD_VAL + Rx FIFO Level DMA Trigger If the RX FIFO level is greater than this value, then the RX FIFO DMA interface will send a signal to the system DMA to notify that RX FIFO has characters to transfer to memory. + 5 + 4 + + + RX_EN + RX DMA channel enable + 9 + 1 + + + + + WKEN + Wake up enable Control register + 0x0034 + + + RX_NE + Wake-Up Enable for RX FIFO Not Empty + 0 + 1 + + + RX_FULL + Wake-Up Enable for RX FIFO Full + 1 + 1 + + + RX_THD + Wake-Up Enable for RX FIFO Threshold Met + 2 + 1 + + + + + WKFL + Wake up Flags register + 0x0038 + + + RX_NE + Wake-Up Flag for RX FIFO Not Empty + 0 + 1 + + + RX_FULL + Wake-Up Flag for RX FIFO Full + 1 + 1 + + + RX_THD + Wake-Up Flag for RX FIFO Threshold Met + 2 + 1 + + + + + + + + UART1 + UART Low Power Registers 1 + 0x40043000 + + + + UART2 + UART Low Power Registers 2 + 0x40044000 + + + + UART3 + UART Low Power Registers 3 + 0x40081400 + + + + WDT + Windowed Watchdog Timer + 0x40003000 + + 0x00 + 0x0400 + registers + + + WWDT + 1 + + + + CTRL + Watchdog Timer Control Register. + 0x00 + read-write + + + INT_LATE_VAL + Windowed Watchdog Interrupt Upper Limit. Sets the number of WDTCLK cycles until a windowed watchdog timer interrupt is generated (if enabled) if the CPU does not write the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset. + 0 + 4 + + + wdt2pow31 + 2**31 clock cycles. + 0 + + + wdt2pow30 + 2**30 clock cycles. + 1 + + + wdt2pow29 + 2**29 clock cycles. + 2 + + + wdt2pow28 + 2**28 clock cycles. + 3 + + + wdt2pow27 + 2^27 clock cycles. + 4 + + + wdt2pow26 + 2**26 clock cycles. + 5 + + + wdt2pow25 + 2**25 clock cycles. + 6 + + + wdt2pow24 + 2**24 clock cycles. + 7 + + + wdt2pow23 + 2**23 clock cycles. + 8 + + + wdt2pow22 + 2**22 clock cycles. + 9 + + + wdt2pow21 + 2**21 clock cycles. + 10 + + + wdt2pow20 + 2**20 clock cycles. + 11 + + + wdt2pow19 + 2**19 clock cycles. + 12 + + + wdt2pow18 + 2**18 clock cycles. + 13 + + + wdt2pow17 + 2**17 clock cycles. + 14 + + + wdt2pow16 + 2**16 clock cycles. + 15 + + + + + RST_LATE_VAL + Windowed Watchdog Reset Upper Limit. Sets the number of WDTCLK cycles until a system reset occurs (if enabled) if the CPU does not write the watchdog reset sequence to the WDT_RST register before the watchdog timer has counted this time period since the last timer reset. + 4 + 4 + + + wdt2pow31 + 2**31 clock cycles. + 0 + + + wdt2pow30 + 2**30 clock cycles. + 1 + + + wdt2pow29 + 2**29 clock cycles. + 2 + + + wdt2pow28 + 2**28 clock cycles. + 3 + + + wdt2pow27 + 2^27 clock cycles. + 4 + + + wdt2pow26 + 2**26 clock cycles. + 5 + + + wdt2pow25 + 2**25 clock cycles. + 6 + + + wdt2pow24 + 2**24 clock cycles. + 7 + + + wdt2pow23 + 2**23 clock cycles. + 8 + + + wdt2pow22 + 2**22 clock cycles. + 9 + + + wdt2pow21 + 2**21 clock cycles. + 10 + + + wdt2pow20 + 2**20 clock cycles. + 11 + + + wdt2pow19 + 2**19 clock cycles. + 12 + + + wdt2pow18 + 2**18 clock cycles. + 13 + + + wdt2pow17 + 2**17 clock cycles. + 14 + + + wdt2pow16 + 2**16 clock cycles. + 15 + + + + + EN + Windowed Watchdog Timer Enable. + 8 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + INT_LATE + Windowed Watchdog Timer Interrupt Flag Too Late. + 9 + 1 + + read-write + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + WDT_INT_EN + Windowed Watchdog Timer Interrupt Enable. + 10 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + WDT_RST_EN + Windowed Watchdog Timer Reset Enable. + 11 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + INT_EARLY + Windowed Watchdog Timer Interrupt Flag Too Soon. + 12 + 1 + + read-write + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + INT_EARLY_VAL + Windowed Watchdog Interrupt Lower Limit. Sets the number of WDTCLK cycles that establishes the lower boundary of the watchdog window. A windowed watchdog timer interrupt is generated (if enabled) if the CPU writes the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset. + 16 + 4 + + + wdt2pow31 + 2**31 clock cycles. + 0 + + + wdt2pow30 + 2**30 clock cycles. + 1 + + + wdt2pow29 + 2**29 clock cycles. + 2 + + + wdt2pow28 + 2**28 clock cycles. + 3 + + + wdt2pow27 + 2^27 clock cycles. + 4 + + + wdt2pow26 + 2**26 clock cycles. + 5 + + + wdt2pow25 + 2**25 clock cycles. + 6 + + + wdt2pow24 + 2**24 clock cycles. + 7 + + + wdt2pow23 + 2**23 clock cycles. + 8 + + + wdt2pow22 + 2**22 clock cycles. + 9 + + + wdt2pow21 + 2**21 clock cycles. + 10 + + + wdt2pow20 + 2**20 clock cycles. + 11 + + + wdt2pow19 + 2**19 clock cycles. + 12 + + + wdt2pow18 + 2**18 clock cycles. + 13 + + + wdt2pow17 + 2**17 clock cycles. + 14 + + + wdt2pow16 + 2**16 clock cycles. + 15 + + + + + RST_EARLY_VAL + Windowed Watchdog Reset Lower Limit. Sets the number of WDTCLK cycles that establishes the lower boundary of the watchdog window. A system reset occurs (if enabled) if the CPU writes the windowed watchdog reset sequence to the WWDT_RST register before the watchdog timer has counted this time period since the last timer reset. + 20 + 4 + + + wdt2pow31 + 2**31 clock cycles. + 0 + + + wdt2pow30 + 2**30 clock cycles. + 1 + + + wdt2pow29 + 2**29 clock cycles. + 2 + + + wdt2pow28 + 2**28 clock cycles. + 3 + + + wdt2pow27 + 2^27 clock cycles. + 4 + + + wdt2pow26 + 2**26 clock cycles. + 5 + + + wdt2pow25 + 2**25 clock cycles. + 6 + + + wdt2pow24 + 2**24 clock cycles. + 7 + + + wdt2pow23 + 2**23 clock cycles. + 8 + + + wdt2pow22 + 2**22 clock cycles. + 9 + + + wdt2pow21 + 2**21 clock cycles. + 10 + + + wdt2pow20 + 2**20 clock cycles. + 11 + + + wdt2pow19 + 2**19 clock cycles. + 12 + + + wdt2pow18 + 2**18 clock cycles. + 13 + + + wdt2pow17 + 2**17 clock cycles. + 14 + + + wdt2pow16 + 2**16 clock cycles. + 15 + + + + + CLKRDY_IE + Switch Ready Interrupt Enable. Fires an interrupt when it is safe to swithc the clock. + 27 + 1 + + + CLKRDY + Clock Status. + 28 + 1 + + + WIN_EN + Enables the Windowed Watchdog Function. + 29 + 1 + + + dis + Windowed Mode Disabled (i.e. Compatibility Mode). + 0 + + + en + Windowed Mode Enabled. + 1 + + + + + RST_EARLY + Windowed Watchdog Timer Reset Flag Too Soon. + 30 + 1 + + read-write + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + RST_LATE + Windowed Watchdog Timer Reset Flag Too Late. + 31 + 1 + + read-write + + noEvent + The event has not occurred. + 0 + + + occurred + The event has occurred. + 1 + + + + + + + RST + Windowed Watchdog Timer Reset Register. + 0x04 + write-only + + + RESET + Writing the watchdog counter 'reset sequence' to this register resets the watchdog counter. If the watchdog count exceeds INT_PERIOD_UPPER_LIMIT then a watchdog interrupt will occur, if enabled. If the watchdog count exceeds RST_PERIOD_UPPER_LIMIT then a watchdog reset will occur, if enabled. + 0 + 8 + + + seq0 + The first value to be written to reset the WDT. + 0x000000A5 + + + seq1 + The second value to be written to reset the WDT. + 0x0000005A + + + + + + + CLKSEL + Windowed Watchdog Timer Clock Select Register. + 0x08 + read-write + + + SOURCE + WWDT Clock Selection Register. + 0 + 3 + + + + + CNT + Windowed Watchdog Timer Count Register. + 0x0C + read-only + + + COUNT + Current Value of the Windowed Watchdog Timer Counter. + 0 + 32 + + + + + + + + WDT1 + Windowed Watchdog Timer 1 + 0x40080800 + + WDT1 + WDT1 IRQ + 57 + + + + + WUT + 32-bit reloadable timer that can be used for timing and wakeup. + 0x40006400 + + 0x00 + 0x400 + registers + + + WUT + WUT IRQ + 53 + + + + CNT + Count. This register stores the current timer count. + 0x00 + 0x00000001 + + + COUNT + Timer Count Value. + 0 + 32 + + + + + CMP + Compare. This register stores the compare value, which is used to set the maximum count value to initiate a reload of the timer to 0x0001. + 0x04 + 0x0000FFFF + + + COMPARE + Timer Compare Value. + 0 + 32 + + + + + INTR + Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt. + 0x0C + oneToClear + + + IF_CLR + Clear Interrupt. + 0 + 1 + + + + + CTRL + Timer Control Register. + 0x10 + + + TMODE + Timer Mode. + 0 + 3 + + + oneShot + One Shot Mode. + 0 + + + continuous + Continuous Mode. + 1 + + + counter + Counter Mode. + 2 + + + capture + Capture Mode. + 4 + + + compare + Compare Mode. + 5 + + + gated + Gated Mode. + 6 + + + captureCompare + Capture/Compare Mode. + 7 + + + + + PRES + Prescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock, F_CNT_CLK = PCLK(HZ)/prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres[2:0]. + 3 + 3 + + + div1 + Divide by 1. + 0 + + + div2 + Divide by 2. + 1 + + + div4 + Divide by 4. + 2 + + + div8 + Divide by 8. + 3 + + + div16 + Divide by 16. + 4 + + + div32 + Divide by 32. + 5 + + + div64 + Divide by 64. + 6 + + + div128 + Divide by 128. + 7 + + + + + TPOL + Timer input/output polarity bit. + 6 + 1 + + + activeHi + Active High. + 0 + + + activeLo + Active Low. + 1 + + + + + TEN + Timer Enable. + 7 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + PRES3 + MSB of prescaler value. + 8 + 1 + + + + + NOLCMP + Timer Non-Overlapping Compare Register. + 0x14 + + + NOL_LO + Non-overlapping Low Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A and next rising edge of PWM output 0A'. + 0 + 8 + + + NOL_HI + Non-overlapping High Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A' and next rising edge of PWM output 0A. + 8 + 8 + + + + + PRESET + Preset register. + 0x18 + + + PRESET + Preset Value. + 0 + 32 + + + + + RELOAD + Reload register. + 0x1C + + + RELOAD + Rerload Value. + 0 + 32 + + + + + SNAPSHOT + Snapshot register. + 0x20 + + + SNAPSHOT + Snapshot Value. + 0 + 32 + + + + + + + + diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mcr_regs.h new file mode 100644 index 00000000000..0fb91c5f55b --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mcr_regs.h @@ -0,0 +1,344 @@ +/** + * @file mcr_regs.h + * @brief Registers, Bit Masks and Bit Positions for the MCR Peripheral Module. + * @note This file is @generated. + * @ingroup mcr_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_MCR_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_MCR_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup mcr + * @defgroup mcr_registers MCR_Registers + * @brief Registers, Bit Masks and Bit Positions for the MCR Peripheral Module. + * @details Misc Control. + */ + +/** + * @ingroup mcr_registers + * Structure type to access the MCR Registers. + */ +typedef struct { + __IO uint32_t eccen; /**< \b 0x00: MCR ECCEN Register */ + __IO uint32_t ipotrim; /**< \b 0x04: MCR IPOTRIM Register */ + __IO uint32_t outen; /**< \b 0x08: MCR OUTEN Register */ + __IO uint32_t cmp_ctrl; /**< \b 0x0C: MCR CMP_CTRL Register */ + __IO uint32_t ctrl; /**< \b 0x10: MCR CTRL Register */ + __R uint32_t rsv_0x14; + __IO uint32_t rtcrst; /**< \b 0x18: MCR RTCRST Register */ + __IO uint32_t rtctrim; /**< \b 0x1C: MCR RTCTRIM Register */ + __IO uint32_t gpio3_ctrl; /**< \b 0x20: MCR GPIO3_CTRL Register */ + __R uint32_t rsv_0x24_0x5f[15]; + __IO uint32_t ldoctrl; /**< \b 0x60: MCR LDOCTRL Register */ + __IO uint32_t pwrmonst; /**< \b 0x64: MCR PWRMONST Register */ +} mxc_mcr_regs_t; + +/* Register offsets for module MCR */ +/** + * @ingroup mcr_registers + * @defgroup MCR_Register_Offsets Register Offsets + * @brief MCR Peripheral Register Offsets from the MCR Base Peripheral Address. + * @{ + */ +#define MXC_R_MCR_ECCEN ((uint32_t)0x00000000UL) /**< Offset from MCR Base Address: 0x0000 */ +#define MXC_R_MCR_IPOTRIM ((uint32_t)0x00000004UL) /**< Offset from MCR Base Address: 0x0004 */ +#define MXC_R_MCR_OUTEN ((uint32_t)0x00000008UL) /**< Offset from MCR Base Address: 0x0008 */ +#define MXC_R_MCR_CMP_CTRL ((uint32_t)0x0000000CUL) /**< Offset from MCR Base Address: 0x000C */ +#define MXC_R_MCR_CTRL ((uint32_t)0x00000010UL) /**< Offset from MCR Base Address: 0x0010 */ +#define MXC_R_MCR_RTCRST ((uint32_t)0x00000018UL) /**< Offset from MCR Base Address: 0x0018 */ +#define MXC_R_MCR_RTCTRIM ((uint32_t)0x0000001CUL) /**< Offset from MCR Base Address: 0x001C */ +#define MXC_R_MCR_GPIO3_CTRL ((uint32_t)0x00000020UL) /**< Offset from MCR Base Address: 0x0020 */ +#define MXC_R_MCR_LDOCTRL ((uint32_t)0x00000060UL) /**< Offset from MCR Base Address: 0x0060 */ +#define MXC_R_MCR_PWRMONST ((uint32_t)0x00000064UL) /**< Offset from MCR Base Address: 0x0064 */ +/**@} end of group mcr_registers */ + +/** + * @ingroup mcr_registers + * @defgroup MCR_ECCEN MCR_ECCEN + * @brief ECC Enable Register + * @{ + */ +#define MXC_F_MCR_ECCEN_RAM0_POS 0 /**< ECCEN_RAM0 Position */ +#define MXC_F_MCR_ECCEN_RAM0 ((uint32_t)(0x1UL << MXC_F_MCR_ECCEN_RAM0_POS)) /**< ECCEN_RAM0 Mask */ + +/**@} end of group MCR_ECCEN_Register */ + +/** + * @ingroup mcr_registers + * @defgroup MCR_IPOTRIM MCR_IPOTRIM + * @brief IPO Manual Trim Register + * @{ + */ +#define MXC_F_MCR_IPOTRIM_VAL_POS 0 /**< IPOTRIM_VAL Position */ +#define MXC_F_MCR_IPOTRIM_VAL ((uint32_t)(0xFFUL << MXC_F_MCR_IPOTRIM_VAL_POS)) /**< IPOTRIM_VAL Mask */ + +#define MXC_F_MCR_IPOTRIM_RANGE_POS 8 /**< IPOTRIM_RANGE Position */ +#define MXC_F_MCR_IPOTRIM_RANGE ((uint32_t)(0x1UL << MXC_F_MCR_IPOTRIM_RANGE_POS)) /**< IPOTRIM_RANGE Mask */ + +/**@} end of group MCR_IPOTRIM_Register */ + +/** + * @ingroup mcr_registers + * @defgroup MCR_OUTEN MCR_OUTEN + * @brief Output Enable Register. + * @{ + */ +#define MXC_F_MCR_OUTEN_SQWOUT_EN_POS 0 /**< OUTEN_SQWOUT_EN Position */ +#define MXC_F_MCR_OUTEN_SQWOUT_EN ((uint32_t)(0x1UL << MXC_F_MCR_OUTEN_SQWOUT_EN_POS)) /**< OUTEN_SQWOUT_EN Mask */ + +#define MXC_F_MCR_OUTEN_PDOWN_EN_POS 1 /**< OUTEN_PDOWN_EN Position */ +#define MXC_F_MCR_OUTEN_PDOWN_EN ((uint32_t)(0x1UL << MXC_F_MCR_OUTEN_PDOWN_EN_POS)) /**< OUTEN_PDOWN_EN Mask */ + +/**@} end of group MCR_OUTEN_Register */ + +/** + * @ingroup mcr_registers + * @defgroup MCR_CMP_CTRL MCR_CMP_CTRL + * @brief Comparator Control Register. + * @{ + */ +#define MXC_F_MCR_CMP_CTRL_EN_POS 0 /**< CMP_CTRL_EN Position */ +#define MXC_F_MCR_CMP_CTRL_EN ((uint32_t)(0x1UL << MXC_F_MCR_CMP_CTRL_EN_POS)) /**< CMP_CTRL_EN Mask */ + +#define MXC_F_MCR_CMP_CTRL_POL_POS 5 /**< CMP_CTRL_POL Position */ +#define MXC_F_MCR_CMP_CTRL_POL ((uint32_t)(0x1UL << MXC_F_MCR_CMP_CTRL_POL_POS)) /**< CMP_CTRL_POL Mask */ + +#define MXC_F_MCR_CMP_CTRL_INTR_EN_POS 6 /**< CMP_CTRL_INTR_EN Position */ +#define MXC_F_MCR_CMP_CTRL_INTR_EN ((uint32_t)(0x1UL << MXC_F_MCR_CMP_CTRL_INTR_EN_POS)) /**< CMP_CTRL_INTR_EN Mask */ + +#define MXC_F_MCR_CMP_CTRL_OUT_POS 14 /**< CMP_CTRL_OUT Position */ +#define MXC_F_MCR_CMP_CTRL_OUT ((uint32_t)(0x1UL << MXC_F_MCR_CMP_CTRL_OUT_POS)) /**< CMP_CTRL_OUT Mask */ + +#define MXC_F_MCR_CMP_CTRL_INTR_FL_POS 15 /**< CMP_CTRL_INTR_FL Position */ +#define MXC_F_MCR_CMP_CTRL_INTR_FL ((uint32_t)(0x1UL << MXC_F_MCR_CMP_CTRL_INTR_FL_POS)) /**< CMP_CTRL_INTR_FL Mask */ + +/**@} end of group MCR_CMP_CTRL_Register */ + +/** + * @ingroup mcr_registers + * @defgroup MCR_CTRL MCR_CTRL + * @brief Control Register + * @{ + */ +#define MXC_F_MCR_CTRL_CMP_HYST_POS 0 /**< CTRL_CMP_HYST Position */ +#define MXC_F_MCR_CTRL_CMP_HYST ((uint32_t)(0x3UL << MXC_F_MCR_CTRL_CMP_HYST_POS)) /**< CTRL_CMP_HYST Mask */ + +#define MXC_F_MCR_CTRL_INRO_EN_POS 2 /**< CTRL_INRO_EN Position */ +#define MXC_F_MCR_CTRL_INRO_EN ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_INRO_EN_POS)) /**< CTRL_INRO_EN Mask */ + +#define MXC_F_MCR_CTRL_ERTCO_EN_POS 3 /**< CTRL_ERTCO_EN Position */ +#define MXC_F_MCR_CTRL_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_ERTCO_EN_POS)) /**< CTRL_ERTCO_EN Mask */ + +#define MXC_F_MCR_CTRL_IBRO_EN_POS 4 /**< CTRL_IBRO_EN Position */ +#define MXC_F_MCR_CTRL_IBRO_EN ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_IBRO_EN_POS)) /**< CTRL_IBRO_EN Mask */ + +#define MXC_F_MCR_CTRL_ERTCO_LP_EN_POS 5 /**< CTRL_ERTCO_LP_EN Position */ +#define MXC_F_MCR_CTRL_ERTCO_LP_EN ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_ERTCO_LP_EN_POS)) /**< CTRL_ERTCO_LP_EN Mask */ + +#define MXC_F_MCR_CTRL_PADPUP_RST_POS 9 /**< CTRL_PADPUP_RST Position */ +#define MXC_F_MCR_CTRL_PADPUP_RST ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_PADPUP_RST_POS)) /**< CTRL_PADPUP_RST Mask */ + +#define MXC_F_MCR_CTRL_PADVDDIOHSEL_RST_POS 10 /**< CTRL_PADVDDIOHSEL_RST Position */ +#define MXC_F_MCR_CTRL_PADVDDIOHSEL_RST ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_PADVDDIOHSEL_RST_POS)) /**< CTRL_PADVDDIOHSEL_RST Mask */ + +/**@} end of group MCR_CTRL_Register */ + +/** + * @ingroup mcr_registers + * @defgroup MCR_RTCRST MCR_RTCRST + * @brief Reset Register. + * @{ + */ +#define MXC_F_MCR_RTCRST_RTC_POS 0 /**< RTCRST_RTC Position */ +#define MXC_F_MCR_RTCRST_RTC ((uint32_t)(0x1UL << MXC_F_MCR_RTCRST_RTC_POS)) /**< RTCRST_RTC Mask */ + +/**@} end of group MCR_RTCRST_Register */ + +/** + * @ingroup mcr_registers + * @defgroup MCR_RTCTRIM MCR_RTCTRIM + * @brief RTC Trim Register. + * @{ + */ +#define MXC_F_MCR_RTCTRIM_X1_POS 0 /**< RTCTRIM_X1 Position */ +#define MXC_F_MCR_RTCTRIM_X1 ((uint32_t)(0x1FUL << MXC_F_MCR_RTCTRIM_X1_POS)) /**< RTCTRIM_X1 Mask */ + +#define MXC_F_MCR_RTCTRIM_X2_POS 8 /**< RTCTRIM_X2 Position */ +#define MXC_F_MCR_RTCTRIM_X2 ((uint32_t)(0x1FUL << MXC_F_MCR_RTCTRIM_X2_POS)) /**< RTCTRIM_X2 Mask */ + +/**@} end of group MCR_RTCTRIM_Register */ + +/** + * @ingroup mcr_registers + * @defgroup MCR_GPIO3_CTRL MCR_GPIO3_CTRL + * @brief GPIO3 Pin Control Register. + * @{ + */ +#define MXC_F_MCR_GPIO3_CTRL_P30_OUT_POS 0 /**< GPIO3_CTRL_P30_OUT Position */ +#define MXC_F_MCR_GPIO3_CTRL_P30_OUT ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P30_OUT_POS)) /**< GPIO3_CTRL_P30_OUT Mask */ + +#define MXC_F_MCR_GPIO3_CTRL_P30_OUTEN_POS 1 /**< GPIO3_CTRL_P30_OUTEN Position */ +#define MXC_F_MCR_GPIO3_CTRL_P30_OUTEN ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P30_OUTEN_POS)) /**< GPIO3_CTRL_P30_OUTEN Mask */ + +#define MXC_F_MCR_GPIO3_CTRL_P30_PUPEN_POS 2 /**< GPIO3_CTRL_P30_PUPEN Position */ +#define MXC_F_MCR_GPIO3_CTRL_P30_PUPEN ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P30_PUPEN_POS)) /**< GPIO3_CTRL_P30_PUPEN Mask */ + +#define MXC_F_MCR_GPIO3_CTRL_P30_IN_POS 3 /**< GPIO3_CTRL_P30_IN Position */ +#define MXC_F_MCR_GPIO3_CTRL_P30_IN ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P30_IN_POS)) /**< GPIO3_CTRL_P30_IN Mask */ + +#define MXC_F_MCR_GPIO3_CTRL_P31_OUT_POS 4 /**< GPIO3_CTRL_P31_OUT Position */ +#define MXC_F_MCR_GPIO3_CTRL_P31_OUT ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P31_OUT_POS)) /**< GPIO3_CTRL_P31_OUT Mask */ + +#define MXC_F_MCR_GPIO3_CTRL_P31_OUTEN_POS 5 /**< GPIO3_CTRL_P31_OUTEN Position */ +#define MXC_F_MCR_GPIO3_CTRL_P31_OUTEN ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P31_OUTEN_POS)) /**< GPIO3_CTRL_P31_OUTEN Mask */ + +#define MXC_F_MCR_GPIO3_CTRL_P31_PUPEN_POS 6 /**< GPIO3_CTRL_P31_PUPEN Position */ +#define MXC_F_MCR_GPIO3_CTRL_P31_PUPEN ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P31_PUPEN_POS)) /**< GPIO3_CTRL_P31_PUPEN Mask */ + +#define MXC_F_MCR_GPIO3_CTRL_P31_IN_POS 7 /**< GPIO3_CTRL_P31_IN Position */ +#define MXC_F_MCR_GPIO3_CTRL_P31_IN ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P31_IN_POS)) /**< GPIO3_CTRL_P31_IN Mask */ + +/**@} end of group MCR_GPIO3_CTRL_Register */ + +/** + * @ingroup mcr_registers + * @defgroup MCR_LDOCTRL MCR_LDOCTRL + * @brief LDO Control Register. + * @{ + */ +#define MXC_F_MCR_LDOCTRL_0P9V_EN_POS 0 /**< LDOCTRL_0P9V_EN Position */ +#define MXC_F_MCR_LDOCTRL_0P9V_EN ((uint32_t)(0x1UL << MXC_F_MCR_LDOCTRL_0P9V_EN_POS)) /**< LDOCTRL_0P9V_EN Mask */ + +/**@} end of group MCR_LDOCTRL_Register */ + +/** + * @ingroup mcr_registers + * @defgroup MCR_PWRMONST MCR_PWRMONST + * @brief LDO Control Register. + * @{ + */ +#define MXC_F_MCR_PWRMONST_PORZ_VLOSS_POS 0 /**< PWRMONST_PORZ_VLOSS Position */ +#define MXC_F_MCR_PWRMONST_PORZ_VLOSS ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_PORZ_VLOSS_POS)) /**< PWRMONST_PORZ_VLOSS Mask */ + +#define MXC_F_MCR_PWRMONST_PORZ_VBAT_POS 1 /**< PWRMONST_PORZ_VBAT Position */ +#define MXC_F_MCR_PWRMONST_PORZ_VBAT ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_PORZ_VBAT_POS)) /**< PWRMONST_PORZ_VBAT Mask */ + +#define MXC_F_MCR_PWRMONST_PORZ_VBB_POS 2 /**< PWRMONST_PORZ_VBB Position */ +#define MXC_F_MCR_PWRMONST_PORZ_VBB ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_PORZ_VBB_POS)) /**< PWRMONST_PORZ_VBB Mask */ + +#define MXC_F_MCR_PWRMONST_PORZ_VDDCA_POS 4 /**< PWRMONST_PORZ_VDDCA Position */ +#define MXC_F_MCR_PWRMONST_PORZ_VDDCA ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_PORZ_VDDCA_POS)) /**< PWRMONST_PORZ_VDDCA Mask */ + +#define MXC_F_MCR_PWRMONST_PORZ_VDDCB_POS 5 /**< PWRMONST_PORZ_VDDCB Position */ +#define MXC_F_MCR_PWRMONST_PORZ_VDDCB ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_PORZ_VDDCB_POS)) /**< PWRMONST_PORZ_VDDCB Mask */ + +#define MXC_F_MCR_PWRMONST_PORZ_VDDA_POS 6 /**< PWRMONST_PORZ_VDDA Position */ +#define MXC_F_MCR_PWRMONST_PORZ_VDDA ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_PORZ_VDDA_POS)) /**< PWRMONST_PORZ_VDDA Mask */ + +#define MXC_F_MCR_PWRMONST_PORZ_VDDB_POS 7 /**< PWRMONST_PORZ_VDDB Position */ +#define MXC_F_MCR_PWRMONST_PORZ_VDDB ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_PORZ_VDDB_POS)) /**< PWRMONST_PORZ_VDDB Mask */ + +#define MXC_F_MCR_PWRMONST_RSTZ_VDDCB_POS 9 /**< PWRMONST_RSTZ_VDDCB Position */ +#define MXC_F_MCR_PWRMONST_RSTZ_VDDCB ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VDDCB_POS)) /**< PWRMONST_RSTZ_VDDCB Mask */ + +#define MXC_F_MCR_PWRMONST_RSTZ_VDDA_POS 10 /**< PWRMONST_RSTZ_VDDA Position */ +#define MXC_F_MCR_PWRMONST_RSTZ_VDDA ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VDDA_POS)) /**< PWRMONST_RSTZ_VDDA Mask */ + +#define MXC_F_MCR_PWRMONST_RSTZ_VDDB_POS 11 /**< PWRMONST_RSTZ_VDDB Position */ +#define MXC_F_MCR_PWRMONST_RSTZ_VDDB ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VDDB_POS)) /**< PWRMONST_RSTZ_VDDB Mask */ + +#define MXC_F_MCR_PWRMONST_RSTZ_VDDIO_POS 12 /**< PWRMONST_RSTZ_VDDIO Position */ +#define MXC_F_MCR_PWRMONST_RSTZ_VDDIO ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VDDIO_POS)) /**< PWRMONST_RSTZ_VDDIO Mask */ + +#define MXC_F_MCR_PWRMONST_RSTZ_VDDIOH_POS 13 /**< PWRMONST_RSTZ_VDDIOH Position */ +#define MXC_F_MCR_PWRMONST_RSTZ_VDDIOH ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VDDIOH_POS)) /**< PWRMONST_RSTZ_VDDIOH Mask */ + +#define MXC_F_MCR_PWRMONST_RSTZ_VBB_POS 14 /**< PWRMONST_RSTZ_VBB Position */ +#define MXC_F_MCR_PWRMONST_RSTZ_VBB ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VBB_POS)) /**< PWRMONST_RSTZ_VBB Mask */ + +#define MXC_F_MCR_PWRMONST_RSTZ_LDO0P9V_POS 16 /**< PWRMONST_RSTZ_LDO0P9V Position */ +#define MXC_F_MCR_PWRMONST_RSTZ_LDO0P9V ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_LDO0P9V_POS)) /**< PWRMONST_RSTZ_LDO0P9V Mask */ + +#define MXC_F_MCR_PWRMONST_RSTZ_VDDCA_POS 17 /**< PWRMONST_RSTZ_VDDCA Position */ +#define MXC_F_MCR_PWRMONST_RSTZ_VDDCA ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VDDCA_POS)) /**< PWRMONST_RSTZ_VDDCA Mask */ + +#define MXC_F_MCR_PWRMONST_RSTZ_VCOREHV_POS 18 /**< PWRMONST_RSTZ_VCOREHV Position */ +#define MXC_F_MCR_PWRMONST_RSTZ_VCOREHV ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VCOREHV_POS)) /**< PWRMONST_RSTZ_VCOREHV Mask */ + +#define MXC_F_MCR_PWRMONST_RSTZ_VDDIOHV_POS 19 /**< PWRMONST_RSTZ_VDDIOHV Position */ +#define MXC_F_MCR_PWRMONST_RSTZ_VDDIOHV ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VDDIOHV_POS)) /**< PWRMONST_RSTZ_VDDIOHV Mask */ + +#define MXC_F_MCR_PWRMONST_RSTZ_VDDIOHHV_POS 20 /**< PWRMONST_RSTZ_VDDIOHHV Position */ +#define MXC_F_MCR_PWRMONST_RSTZ_VDDIOHHV ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VDDIOHHV_POS)) /**< PWRMONST_RSTZ_VDDIOHHV Mask */ + +#define MXC_F_MCR_PWRMONST_RSTZ_VNFCRX_POS 21 /**< PWRMONST_RSTZ_VNFCRX Position */ +#define MXC_F_MCR_PWRMONST_RSTZ_VNFCRX ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VNFCRX_POS)) /**< PWRMONST_RSTZ_VNFCRX Mask */ + +#define MXC_F_MCR_PWRMONST_RSTZ_VNFCTX_POS 22 /**< PWRMONST_RSTZ_VNFCTX Position */ +#define MXC_F_MCR_PWRMONST_RSTZ_VNFCTX ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VNFCTX_POS)) /**< PWRMONST_RSTZ_VNFCTX Mask */ + +#define MXC_F_MCR_PWRMONST_RSTZ_VNFC1V_POS 23 /**< PWRMONST_RSTZ_VNFC1V Position */ +#define MXC_F_MCR_PWRMONST_RSTZ_VNFC1V ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VNFC1V_POS)) /**< PWRMONST_RSTZ_VNFC1V Mask */ + +/**@} end of group MCR_PWRMONST_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_MCR_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/owm_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/owm_regs.h new file mode 100644 index 00000000000..99c5b7e3ea8 --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/owm_regs.h @@ -0,0 +1,230 @@ +/** + * @file owm_regs.h + * @brief Registers, Bit Masks and Bit Positions for the OWM Peripheral Module. + * @note This file is @generated. + * @ingroup owm_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_OWM_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_OWM_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup owm + * @defgroup owm_registers OWM_Registers + * @brief Registers, Bit Masks and Bit Positions for the OWM Peripheral Module. + * @details 1-Wire Master Interface. + */ + +/** + * @ingroup owm_registers + * Structure type to access the OWM Registers. + */ +typedef struct { + __IO uint32_t ctrl0; /**< \b 0x0000: OWM CTRL0 Register */ + __IO uint32_t clkdiv; /**< \b 0x0004: OWM CLKDIV Register */ + __IO uint32_t ctrl1; /**< \b 0x0008: OWM CTRL1 Register */ + __IO uint32_t data; /**< \b 0x000C: OWM DATA Register */ + __IO uint32_t intfl; /**< \b 0x0010: OWM INTFL Register */ + __IO uint32_t inten; /**< \b 0x0014: OWM INTEN Register */ +} mxc_owm_regs_t; + +/* Register offsets for module OWM */ +/** + * @ingroup owm_registers + * @defgroup OWM_Register_Offsets Register Offsets + * @brief OWM Peripheral Register Offsets from the OWM Base Peripheral Address. + * @{ + */ +#define MXC_R_OWM_CTRL0 ((uint32_t)0x00000000UL) /**< Offset from OWM Base Address: 0x0000 */ +#define MXC_R_OWM_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from OWM Base Address: 0x0004 */ +#define MXC_R_OWM_CTRL1 ((uint32_t)0x00000008UL) /**< Offset from OWM Base Address: 0x0008 */ +#define MXC_R_OWM_DATA ((uint32_t)0x0000000CUL) /**< Offset from OWM Base Address: 0x000C */ +#define MXC_R_OWM_INTFL ((uint32_t)0x00000010UL) /**< Offset from OWM Base Address: 0x0010 */ +#define MXC_R_OWM_INTEN ((uint32_t)0x00000014UL) /**< Offset from OWM Base Address: 0x0014 */ +/**@} end of group owm_registers */ + +/** + * @ingroup owm_registers + * @defgroup OWM_CTRL0 OWM_CTRL0 + * @brief 1-Wire Master Control Register. + * @{ + */ +#define MXC_F_OWM_CTRL0_LL_EN_POS 0 /**< CTRL0_LL_EN Position */ +#define MXC_F_OWM_CTRL0_LL_EN ((uint32_t)(0x1UL << MXC_F_OWM_CTRL0_LL_EN_POS)) /**< CTRL0_LL_EN Mask */ + +#define MXC_F_OWM_CTRL0_FPRESDET_POS 1 /**< CTRL0_FPRESDET Position */ +#define MXC_F_OWM_CTRL0_FPRESDET ((uint32_t)(0x1UL << MXC_F_OWM_CTRL0_FPRESDET_POS)) /**< CTRL0_FPRESDET Mask */ + +#define MXC_F_OWM_CTRL0_BB_EN_POS 2 /**< CTRL0_BB_EN Position */ +#define MXC_F_OWM_CTRL0_BB_EN ((uint32_t)(0x1UL << MXC_F_OWM_CTRL0_BB_EN_POS)) /**< CTRL0_BB_EN Mask */ + +#define MXC_F_OWM_CTRL0_EXT_PU_MODE_POS 3 /**< CTRL0_EXT_PU_MODE Position */ +#define MXC_F_OWM_CTRL0_EXT_PU_MODE ((uint32_t)(0x1UL << MXC_F_OWM_CTRL0_EXT_PU_MODE_POS)) /**< CTRL0_EXT_PU_MODE Mask */ + +#define MXC_F_OWM_CTRL0_EXT_PU_EN_POS 4 /**< CTRL0_EXT_PU_EN Position */ +#define MXC_F_OWM_CTRL0_EXT_PU_EN ((uint32_t)(0x1UL << MXC_F_OWM_CTRL0_EXT_PU_EN_POS)) /**< CTRL0_EXT_PU_EN Mask */ + +#define MXC_F_OWM_CTRL0_SB_EN_POS 5 /**< CTRL0_SB_EN Position */ +#define MXC_F_OWM_CTRL0_SB_EN ((uint32_t)(0x1UL << MXC_F_OWM_CTRL0_SB_EN_POS)) /**< CTRL0_SB_EN Mask */ + +#define MXC_F_OWM_CTRL0_OD_POS 6 /**< CTRL0_OD Position */ +#define MXC_F_OWM_CTRL0_OD ((uint32_t)(0x1UL << MXC_F_OWM_CTRL0_OD_POS)) /**< CTRL0_OD Mask */ + +#define MXC_F_OWM_CTRL0_INT_PU_EN_POS 7 /**< CTRL0_INT_PU_EN Position */ +#define MXC_F_OWM_CTRL0_INT_PU_EN ((uint32_t)(0x1UL << MXC_F_OWM_CTRL0_INT_PU_EN_POS)) /**< CTRL0_INT_PU_EN Mask */ + +/**@} end of group OWM_CTRL0_Register */ + +/** + * @ingroup owm_registers + * @defgroup OWM_CLKDIV OWM_CLKDIV + * @brief 1-Wire Master Clock Divisor. + * @{ + */ +#define MXC_F_OWM_CLKDIV_DIVISOR_POS 0 /**< CLKDIV_DIVISOR Position */ +#define MXC_F_OWM_CLKDIV_DIVISOR ((uint32_t)(0xFFUL << MXC_F_OWM_CLKDIV_DIVISOR_POS)) /**< CLKDIV_DIVISOR Mask */ + +/**@} end of group OWM_CLKDIV_Register */ + +/** + * @ingroup owm_registers + * @defgroup OWM_CTRL1 OWM_CTRL1 + * @brief 1-Wire Master Control/Status. + * @{ + */ +#define MXC_F_OWM_CTRL1_RST_POS 0 /**< CTRL1_RST Position */ +#define MXC_F_OWM_CTRL1_RST ((uint32_t)(0x1UL << MXC_F_OWM_CTRL1_RST_POS)) /**< CTRL1_RST Mask */ + +#define MXC_F_OWM_CTRL1_SRA_EN_POS 1 /**< CTRL1_SRA_EN Position */ +#define MXC_F_OWM_CTRL1_SRA_EN ((uint32_t)(0x1UL << MXC_F_OWM_CTRL1_SRA_EN_POS)) /**< CTRL1_SRA_EN Mask */ + +#define MXC_F_OWM_CTRL1_BB_OUT_EN_POS 2 /**< CTRL1_BB_OUT_EN Position */ +#define MXC_F_OWM_CTRL1_BB_OUT_EN ((uint32_t)(0x1UL << MXC_F_OWM_CTRL1_BB_OUT_EN_POS)) /**< CTRL1_BB_OUT_EN Mask */ + +#define MXC_F_OWM_CTRL1_INPUT_ST_POS 3 /**< CTRL1_INPUT_ST Position */ +#define MXC_F_OWM_CTRL1_INPUT_ST ((uint32_t)(0x1UL << MXC_F_OWM_CTRL1_INPUT_ST_POS)) /**< CTRL1_INPUT_ST Mask */ + +#define MXC_F_OWM_CTRL1_OD_SPEC_ST_POS 4 /**< CTRL1_OD_SPEC_ST Position */ +#define MXC_F_OWM_CTRL1_OD_SPEC_ST ((uint32_t)(0x1UL << MXC_F_OWM_CTRL1_OD_SPEC_ST_POS)) /**< CTRL1_OD_SPEC_ST Mask */ + +#define MXC_F_OWM_CTRL1_PRESDET_ST_POS 7 /**< CTRL1_PRESDET_ST Position */ +#define MXC_F_OWM_CTRL1_PRESDET_ST ((uint32_t)(0x1UL << MXC_F_OWM_CTRL1_PRESDET_ST_POS)) /**< CTRL1_PRESDET_ST Mask */ + +/**@} end of group OWM_CTRL1_Register */ + +/** + * @ingroup owm_registers + * @defgroup OWM_DATA OWM_DATA + * @brief 1-Wire Master Data Buffer. + * @{ + */ +#define MXC_F_OWM_DATA_DATA_POS 0 /**< DATA_DATA Position */ +#define MXC_F_OWM_DATA_DATA ((uint32_t)(0xFFUL << MXC_F_OWM_DATA_DATA_POS)) /**< DATA_DATA Mask */ + +/**@} end of group OWM_DATA_Register */ + +/** + * @ingroup owm_registers + * @defgroup OWM_INTFL OWM_INTFL + * @brief 1-Wire Master Interrupt Flags. + * @{ + */ +#define MXC_F_OWM_INTFL_RST_DONE_POS 0 /**< INTFL_RST_DONE Position */ +#define MXC_F_OWM_INTFL_RST_DONE ((uint32_t)(0x1UL << MXC_F_OWM_INTFL_RST_DONE_POS)) /**< INTFL_RST_DONE Mask */ + +#define MXC_F_OWM_INTFL_TX_EM_POS 1 /**< INTFL_TX_EM Position */ +#define MXC_F_OWM_INTFL_TX_EM ((uint32_t)(0x1UL << MXC_F_OWM_INTFL_TX_EM_POS)) /**< INTFL_TX_EM Mask */ + +#define MXC_F_OWM_INTFL_RX_RDY_POS 2 /**< INTFL_RX_RDY Position */ +#define MXC_F_OWM_INTFL_RX_RDY ((uint32_t)(0x1UL << MXC_F_OWM_INTFL_RX_RDY_POS)) /**< INTFL_RX_RDY Mask */ + +#define MXC_F_OWM_INTFL_LINE_SHORT_POS 3 /**< INTFL_LINE_SHORT Position */ +#define MXC_F_OWM_INTFL_LINE_SHORT ((uint32_t)(0x1UL << MXC_F_OWM_INTFL_LINE_SHORT_POS)) /**< INTFL_LINE_SHORT Mask */ + +#define MXC_F_OWM_INTFL_LINE_LOW_POS 4 /**< INTFL_LINE_LOW Position */ +#define MXC_F_OWM_INTFL_LINE_LOW ((uint32_t)(0x1UL << MXC_F_OWM_INTFL_LINE_LOW_POS)) /**< INTFL_LINE_LOW Mask */ + +/**@} end of group OWM_INTFL_Register */ + +/** + * @ingroup owm_registers + * @defgroup OWM_INTEN OWM_INTEN + * @brief 1-Wire Master Interrupt Enables. + * @{ + */ +#define MXC_F_OWM_INTEN_RST_DONE_POS 0 /**< INTEN_RST_DONE Position */ +#define MXC_F_OWM_INTEN_RST_DONE ((uint32_t)(0x1UL << MXC_F_OWM_INTEN_RST_DONE_POS)) /**< INTEN_RST_DONE Mask */ + +#define MXC_F_OWM_INTEN_TX_EM_POS 1 /**< INTEN_TX_EM Position */ +#define MXC_F_OWM_INTEN_TX_EM ((uint32_t)(0x1UL << MXC_F_OWM_INTEN_TX_EM_POS)) /**< INTEN_TX_EM Mask */ + +#define MXC_F_OWM_INTEN_RX_RDY_POS 2 /**< INTEN_RX_RDY Position */ +#define MXC_F_OWM_INTEN_RX_RDY ((uint32_t)(0x1UL << MXC_F_OWM_INTEN_RX_RDY_POS)) /**< INTEN_RX_RDY Mask */ + +#define MXC_F_OWM_INTEN_LINE_SHORT_POS 3 /**< INTEN_LINE_SHORT Position */ +#define MXC_F_OWM_INTEN_LINE_SHORT ((uint32_t)(0x1UL << MXC_F_OWM_INTEN_LINE_SHORT_POS)) /**< INTEN_LINE_SHORT Mask */ + +#define MXC_F_OWM_INTEN_LINE_LOW_POS 4 /**< INTEN_LINE_LOW Position */ +#define MXC_F_OWM_INTEN_LINE_LOW ((uint32_t)(0x1UL << MXC_F_OWM_INTEN_LINE_LOW_POS)) /**< INTEN_LINE_LOW Mask */ + +/**@} end of group OWM_INTEN_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_OWM_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/pt_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/pt_regs.h new file mode 100644 index 00000000000..1ad7f8b27bd --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/pt_regs.h @@ -0,0 +1,212 @@ +/** + * @file pt_regs.h + * @brief Registers, Bit Masks and Bit Positions for the PT Peripheral Module. + * @note This file is @generated. + * @ingroup pt_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_PT_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_PT_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup pt + * @defgroup pt_registers PT_Registers + * @brief Registers, Bit Masks and Bit Positions for the PT Peripheral Module. + * @details Pulse Train + */ + +/** + * @ingroup pt_registers + * Structure type to access the PT Registers. + */ +typedef struct { + __IO uint32_t rate_length; /**< \b 0x0000: PT RATE_LENGTH Register */ + __IO uint32_t train; /**< \b 0x0004: PT TRAIN Register */ + __IO uint32_t loop; /**< \b 0x0008: PT LOOP Register */ + __IO uint32_t restart; /**< \b 0x000C: PT RESTART Register */ +} mxc_pt_regs_t; + +/* Register offsets for module PT */ +/** + * @ingroup pt_registers + * @defgroup PT_Register_Offsets Register Offsets + * @brief PT Peripheral Register Offsets from the PT Base Peripheral Address. + * @{ + */ +#define MXC_R_PT_RATE_LENGTH ((uint32_t)0x00000000UL) /**< Offset from PT Base Address: 0x0000 */ +#define MXC_R_PT_TRAIN ((uint32_t)0x00000004UL) /**< Offset from PT Base Address: 0x0004 */ +#define MXC_R_PT_LOOP ((uint32_t)0x00000008UL) /**< Offset from PT Base Address: 0x0008 */ +#define MXC_R_PT_RESTART ((uint32_t)0x0000000CUL) /**< Offset from PT Base Address: 0x000C */ +/**@} end of group pt_registers */ + +/** + * @ingroup pt_registers + * @defgroup PT_RATE_LENGTH PT_RATE_LENGTH + * @brief Pulse Train Configuration + * @{ + */ +#define MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS 0 /**< RATE_LENGTH_RATE_CONTROL Position */ +#define MXC_F_PT_RATE_LENGTH_RATE_CONTROL ((uint32_t)(0x7FFFFFFUL << MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS)) /**< RATE_LENGTH_RATE_CONTROL Mask */ + +#define MXC_F_PT_RATE_LENGTH_MODE_POS 27 /**< RATE_LENGTH_MODE Position */ +#define MXC_F_PT_RATE_LENGTH_MODE ((uint32_t)(0x1FUL << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< RATE_LENGTH_MODE Mask */ +#define MXC_V_PT_RATE_LENGTH_MODE_32_BIT ((uint32_t)0x0UL) /**< RATE_LENGTH_MODE_32_BIT Value */ +#define MXC_S_PT_RATE_LENGTH_MODE_32_BIT (MXC_V_PT_RATE_LENGTH_MODE_32_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_32_BIT Setting */ +#define MXC_V_PT_RATE_LENGTH_MODE_SQUARE_WAVE ((uint32_t)0x1UL) /**< RATE_LENGTH_MODE_SQUARE_WAVE Value */ +#define MXC_S_PT_RATE_LENGTH_MODE_SQUARE_WAVE (MXC_V_PT_RATE_LENGTH_MODE_SQUARE_WAVE << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_SQUARE_WAVE Setting */ +#define MXC_V_PT_RATE_LENGTH_MODE_2_BIT ((uint32_t)0x2UL) /**< RATE_LENGTH_MODE_2_BIT Value */ +#define MXC_S_PT_RATE_LENGTH_MODE_2_BIT (MXC_V_PT_RATE_LENGTH_MODE_2_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_2_BIT Setting */ +#define MXC_V_PT_RATE_LENGTH_MODE_3_BIT ((uint32_t)0x3UL) /**< RATE_LENGTH_MODE_3_BIT Value */ +#define MXC_S_PT_RATE_LENGTH_MODE_3_BIT (MXC_V_PT_RATE_LENGTH_MODE_3_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_3_BIT Setting */ +#define MXC_V_PT_RATE_LENGTH_MODE_4_BIT ((uint32_t)0x4UL) /**< RATE_LENGTH_MODE_4_BIT Value */ +#define MXC_S_PT_RATE_LENGTH_MODE_4_BIT (MXC_V_PT_RATE_LENGTH_MODE_4_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_4_BIT Setting */ +#define MXC_V_PT_RATE_LENGTH_MODE_5_BIT ((uint32_t)0x5UL) /**< RATE_LENGTH_MODE_5_BIT Value */ +#define MXC_S_PT_RATE_LENGTH_MODE_5_BIT (MXC_V_PT_RATE_LENGTH_MODE_5_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_5_BIT Setting */ +#define MXC_V_PT_RATE_LENGTH_MODE_6_BIT ((uint32_t)0x6UL) /**< RATE_LENGTH_MODE_6_BIT Value */ +#define MXC_S_PT_RATE_LENGTH_MODE_6_BIT (MXC_V_PT_RATE_LENGTH_MODE_6_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_6_BIT Setting */ +#define MXC_V_PT_RATE_LENGTH_MODE_7_BIT ((uint32_t)0x7UL) /**< RATE_LENGTH_MODE_7_BIT Value */ +#define MXC_S_PT_RATE_LENGTH_MODE_7_BIT (MXC_V_PT_RATE_LENGTH_MODE_7_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_7_BIT Setting */ +#define MXC_V_PT_RATE_LENGTH_MODE_8_BIT ((uint32_t)0x8UL) /**< RATE_LENGTH_MODE_8_BIT Value */ +#define MXC_S_PT_RATE_LENGTH_MODE_8_BIT (MXC_V_PT_RATE_LENGTH_MODE_8_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_8_BIT Setting */ +#define MXC_V_PT_RATE_LENGTH_MODE_9_BIT ((uint32_t)0x9UL) /**< RATE_LENGTH_MODE_9_BIT Value */ +#define MXC_S_PT_RATE_LENGTH_MODE_9_BIT (MXC_V_PT_RATE_LENGTH_MODE_9_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_9_BIT Setting */ +#define MXC_V_PT_RATE_LENGTH_MODE_10_BIT ((uint32_t)0xAUL) /**< RATE_LENGTH_MODE_10_BIT Value */ +#define MXC_S_PT_RATE_LENGTH_MODE_10_BIT (MXC_V_PT_RATE_LENGTH_MODE_10_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_10_BIT Setting */ +#define MXC_V_PT_RATE_LENGTH_MODE_11_BIT ((uint32_t)0xBUL) /**< RATE_LENGTH_MODE_11_BIT Value */ +#define MXC_S_PT_RATE_LENGTH_MODE_11_BIT (MXC_V_PT_RATE_LENGTH_MODE_11_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_11_BIT Setting */ +#define MXC_V_PT_RATE_LENGTH_MODE_12_BIT ((uint32_t)0xCUL) /**< RATE_LENGTH_MODE_12_BIT Value */ +#define MXC_S_PT_RATE_LENGTH_MODE_12_BIT (MXC_V_PT_RATE_LENGTH_MODE_12_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_12_BIT Setting */ +#define MXC_V_PT_RATE_LENGTH_MODE_13_BIT ((uint32_t)0xDUL) /**< RATE_LENGTH_MODE_13_BIT Value */ +#define MXC_S_PT_RATE_LENGTH_MODE_13_BIT (MXC_V_PT_RATE_LENGTH_MODE_13_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_13_BIT Setting */ +#define MXC_V_PT_RATE_LENGTH_MODE_14_BIT ((uint32_t)0xEUL) /**< RATE_LENGTH_MODE_14_BIT Value */ +#define MXC_S_PT_RATE_LENGTH_MODE_14_BIT (MXC_V_PT_RATE_LENGTH_MODE_14_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_14_BIT Setting */ +#define MXC_V_PT_RATE_LENGTH_MODE_15_BIT ((uint32_t)0xFUL) /**< RATE_LENGTH_MODE_15_BIT Value */ +#define MXC_S_PT_RATE_LENGTH_MODE_15_BIT (MXC_V_PT_RATE_LENGTH_MODE_15_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_15_BIT Setting */ +#define MXC_V_PT_RATE_LENGTH_MODE_16_BIT ((uint32_t)0x10UL) /**< RATE_LENGTH_MODE_16_BIT Value */ +#define MXC_S_PT_RATE_LENGTH_MODE_16_BIT (MXC_V_PT_RATE_LENGTH_MODE_16_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_16_BIT Setting */ +#define MXC_V_PT_RATE_LENGTH_MODE_17_BIT ((uint32_t)0x11UL) /**< RATE_LENGTH_MODE_17_BIT Value */ +#define MXC_S_PT_RATE_LENGTH_MODE_17_BIT (MXC_V_PT_RATE_LENGTH_MODE_17_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_17_BIT Setting */ +#define MXC_V_PT_RATE_LENGTH_MODE_18_BIT ((uint32_t)0x12UL) /**< RATE_LENGTH_MODE_18_BIT Value */ +#define MXC_S_PT_RATE_LENGTH_MODE_18_BIT (MXC_V_PT_RATE_LENGTH_MODE_18_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_18_BIT Setting */ +#define MXC_V_PT_RATE_LENGTH_MODE_19_BIT ((uint32_t)0x13UL) /**< RATE_LENGTH_MODE_19_BIT Value */ +#define MXC_S_PT_RATE_LENGTH_MODE_19_BIT (MXC_V_PT_RATE_LENGTH_MODE_19_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_19_BIT Setting */ +#define MXC_V_PT_RATE_LENGTH_MODE_20_BIT ((uint32_t)0x14UL) /**< RATE_LENGTH_MODE_20_BIT Value */ +#define MXC_S_PT_RATE_LENGTH_MODE_20_BIT (MXC_V_PT_RATE_LENGTH_MODE_20_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_20_BIT Setting */ +#define MXC_V_PT_RATE_LENGTH_MODE_21_BIT ((uint32_t)0x15UL) /**< RATE_LENGTH_MODE_21_BIT Value */ +#define MXC_S_PT_RATE_LENGTH_MODE_21_BIT (MXC_V_PT_RATE_LENGTH_MODE_21_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_21_BIT Setting */ +#define MXC_V_PT_RATE_LENGTH_MODE_22_BIT ((uint32_t)0x16UL) /**< RATE_LENGTH_MODE_22_BIT Value */ +#define MXC_S_PT_RATE_LENGTH_MODE_22_BIT (MXC_V_PT_RATE_LENGTH_MODE_22_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_22_BIT Setting */ +#define MXC_V_PT_RATE_LENGTH_MODE_23_BIT ((uint32_t)0x17UL) /**< RATE_LENGTH_MODE_23_BIT Value */ +#define MXC_S_PT_RATE_LENGTH_MODE_23_BIT (MXC_V_PT_RATE_LENGTH_MODE_23_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_23_BIT Setting */ +#define MXC_V_PT_RATE_LENGTH_MODE_24_BIT ((uint32_t)0x18UL) /**< RATE_LENGTH_MODE_24_BIT Value */ +#define MXC_S_PT_RATE_LENGTH_MODE_24_BIT (MXC_V_PT_RATE_LENGTH_MODE_24_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_24_BIT Setting */ +#define MXC_V_PT_RATE_LENGTH_MODE_25_BIT ((uint32_t)0x19UL) /**< RATE_LENGTH_MODE_25_BIT Value */ +#define MXC_S_PT_RATE_LENGTH_MODE_25_BIT (MXC_V_PT_RATE_LENGTH_MODE_25_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_25_BIT Setting */ +#define MXC_V_PT_RATE_LENGTH_MODE_26_BIT ((uint32_t)0x1AUL) /**< RATE_LENGTH_MODE_26_BIT Value */ +#define MXC_S_PT_RATE_LENGTH_MODE_26_BIT (MXC_V_PT_RATE_LENGTH_MODE_26_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_26_BIT Setting */ +#define MXC_V_PT_RATE_LENGTH_MODE_27_BIT ((uint32_t)0x1BUL) /**< RATE_LENGTH_MODE_27_BIT Value */ +#define MXC_S_PT_RATE_LENGTH_MODE_27_BIT (MXC_V_PT_RATE_LENGTH_MODE_27_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_27_BIT Setting */ +#define MXC_V_PT_RATE_LENGTH_MODE_28_BIT ((uint32_t)0x1CUL) /**< RATE_LENGTH_MODE_28_BIT Value */ +#define MXC_S_PT_RATE_LENGTH_MODE_28_BIT (MXC_V_PT_RATE_LENGTH_MODE_28_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_28_BIT Setting */ +#define MXC_V_PT_RATE_LENGTH_MODE_29_BIT ((uint32_t)0x1DUL) /**< RATE_LENGTH_MODE_29_BIT Value */ +#define MXC_S_PT_RATE_LENGTH_MODE_29_BIT (MXC_V_PT_RATE_LENGTH_MODE_29_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_29_BIT Setting */ +#define MXC_V_PT_RATE_LENGTH_MODE_30_BIT ((uint32_t)0x1EUL) /**< RATE_LENGTH_MODE_30_BIT Value */ +#define MXC_S_PT_RATE_LENGTH_MODE_30_BIT (MXC_V_PT_RATE_LENGTH_MODE_30_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_30_BIT Setting */ +#define MXC_V_PT_RATE_LENGTH_MODE_31_BIT ((uint32_t)0x1FUL) /**< RATE_LENGTH_MODE_31_BIT Value */ +#define MXC_S_PT_RATE_LENGTH_MODE_31_BIT (MXC_V_PT_RATE_LENGTH_MODE_31_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_31_BIT Setting */ + +/**@} end of group PT_RATE_LENGTH_Register */ + +/** + * @ingroup pt_registers + * @defgroup PT_LOOP PT_LOOP + * @brief Pulse Train Loop Count + * @{ + */ +#define MXC_F_PT_LOOP_COUNT_POS 0 /**< LOOP_COUNT Position */ +#define MXC_F_PT_LOOP_COUNT ((uint32_t)(0xFFFFUL << MXC_F_PT_LOOP_COUNT_POS)) /**< LOOP_COUNT Mask */ + +#define MXC_F_PT_LOOP_DELAY_POS 16 /**< LOOP_DELAY Position */ +#define MXC_F_PT_LOOP_DELAY ((uint32_t)(0xFFFUL << MXC_F_PT_LOOP_DELAY_POS)) /**< LOOP_DELAY Mask */ + +/**@} end of group PT_LOOP_Register */ + +/** + * @ingroup pt_registers + * @defgroup PT_RESTART PT_RESTART + * @brief Pulse Train Auto-Restart Configuration. + * @{ + */ +#define MXC_F_PT_RESTART_PT_X_SELECT_POS 0 /**< RESTART_PT_X_SELECT Position */ +#define MXC_F_PT_RESTART_PT_X_SELECT ((uint32_t)(0x1FUL << MXC_F_PT_RESTART_PT_X_SELECT_POS)) /**< RESTART_PT_X_SELECT Mask */ + +#define MXC_F_PT_RESTART_ON_PT_X_LOOP_EXIT_POS 7 /**< RESTART_ON_PT_X_LOOP_EXIT Position */ +#define MXC_F_PT_RESTART_ON_PT_X_LOOP_EXIT ((uint32_t)(0x1UL << MXC_F_PT_RESTART_ON_PT_X_LOOP_EXIT_POS)) /**< RESTART_ON_PT_X_LOOP_EXIT Mask */ + +#define MXC_F_PT_RESTART_PT_Y_SELECT_POS 8 /**< RESTART_PT_Y_SELECT Position */ +#define MXC_F_PT_RESTART_PT_Y_SELECT ((uint32_t)(0x1FUL << MXC_F_PT_RESTART_PT_Y_SELECT_POS)) /**< RESTART_PT_Y_SELECT Mask */ + +#define MXC_F_PT_RESTART_ON_PT_Y_LOOP_EXIT_POS 15 /**< RESTART_ON_PT_Y_LOOP_EXIT Position */ +#define MXC_F_PT_RESTART_ON_PT_Y_LOOP_EXIT ((uint32_t)(0x1UL << MXC_F_PT_RESTART_ON_PT_Y_LOOP_EXIT_POS)) /**< RESTART_ON_PT_Y_LOOP_EXIT Mask */ + +/**@} end of group PT_RESTART_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_PT_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/ptg_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/ptg_regs.h new file mode 100644 index 00000000000..7510105d626 --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/ptg_regs.h @@ -0,0 +1,268 @@ +/** + * @file ptg_regs.h + * @brief Registers, Bit Masks and Bit Positions for the PTG Peripheral Module. + * @note This file is @generated. + * @ingroup ptg_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_PTG_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_PTG_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup ptg + * @defgroup ptg_registers PTG_Registers + * @brief Registers, Bit Masks and Bit Positions for the PTG Peripheral Module. + * @details Pulse Train Generation + */ + +/** + * @ingroup ptg_registers + * Structure type to access the PTG Registers. + */ +typedef struct { + __IO uint32_t enable; /**< \b 0x0000: PTG ENABLE Register */ + __IO uint32_t resync; /**< \b 0x0004: PTG RESYNC Register */ + __IO uint32_t stop_intfl; /**< \b 0x0008: PTG STOP_INTFL Register */ + __IO uint32_t stop_inten; /**< \b 0x000C: PTG STOP_INTEN Register */ + __O uint32_t safe_en; /**< \b 0x0010: PTG SAFE_EN Register */ + __O uint32_t safe_dis; /**< \b 0x0014: PTG SAFE_DIS Register */ + __IO uint32_t ready_intfl; /**< \b 0x0018: PTG READY_INTFL Register */ + __IO uint32_t ready_inten; /**< \b 0x001C: PTG READY_INTEN Register */ +} mxc_ptg_regs_t; + +/* Register offsets for module PTG */ +/** + * @ingroup ptg_registers + * @defgroup PTG_Register_Offsets Register Offsets + * @brief PTG Peripheral Register Offsets from the PTG Base Peripheral Address. + * @{ + */ +#define MXC_R_PTG_ENABLE ((uint32_t)0x00000000UL) /**< Offset from PTG Base Address: 0x0000 */ +#define MXC_R_PTG_RESYNC ((uint32_t)0x00000004UL) /**< Offset from PTG Base Address: 0x0004 */ +#define MXC_R_PTG_STOP_INTFL ((uint32_t)0x00000008UL) /**< Offset from PTG Base Address: 0x0008 */ +#define MXC_R_PTG_STOP_INTEN ((uint32_t)0x0000000CUL) /**< Offset from PTG Base Address: 0x000C */ +#define MXC_R_PTG_SAFE_EN ((uint32_t)0x00000010UL) /**< Offset from PTG Base Address: 0x0010 */ +#define MXC_R_PTG_SAFE_DIS ((uint32_t)0x00000014UL) /**< Offset from PTG Base Address: 0x0014 */ +#define MXC_R_PTG_READY_INTFL ((uint32_t)0x00000018UL) /**< Offset from PTG Base Address: 0x0018 */ +#define MXC_R_PTG_READY_INTEN ((uint32_t)0x0000001CUL) /**< Offset from PTG Base Address: 0x001C */ +/**@} end of group ptg_registers */ + +/** + * @ingroup ptg_registers + * @defgroup PTG_ENABLE PTG_ENABLE + * @brief Global Enable/Disable Controls for All Pulse Trains + * @{ + */ +#define MXC_F_PTG_ENABLE_PT0_POS 0 /**< ENABLE_PT0 Position */ +#define MXC_F_PTG_ENABLE_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT0_POS)) /**< ENABLE_PT0 Mask */ + +#define MXC_F_PTG_ENABLE_PT1_POS 1 /**< ENABLE_PT1 Position */ +#define MXC_F_PTG_ENABLE_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT1_POS)) /**< ENABLE_PT1 Mask */ + +#define MXC_F_PTG_ENABLE_PT2_POS 2 /**< ENABLE_PT2 Position */ +#define MXC_F_PTG_ENABLE_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT2_POS)) /**< ENABLE_PT2 Mask */ + +#define MXC_F_PTG_ENABLE_PT3_POS 3 /**< ENABLE_PT3 Position */ +#define MXC_F_PTG_ENABLE_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT3_POS)) /**< ENABLE_PT3 Mask */ + +/**@} end of group PTG_ENABLE_Register */ + +/** + * @ingroup ptg_registers + * @defgroup PTG_RESYNC PTG_RESYNC + * @brief Global Resync (All Pulse Trains) Control + * @{ + */ +#define MXC_F_PTG_RESYNC_PT0_POS 0 /**< RESYNC_PT0 Position */ +#define MXC_F_PTG_RESYNC_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT0_POS)) /**< RESYNC_PT0 Mask */ + +#define MXC_F_PTG_RESYNC_PT1_POS 1 /**< RESYNC_PT1 Position */ +#define MXC_F_PTG_RESYNC_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT1_POS)) /**< RESYNC_PT1 Mask */ + +#define MXC_F_PTG_RESYNC_PT2_POS 2 /**< RESYNC_PT2 Position */ +#define MXC_F_PTG_RESYNC_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT2_POS)) /**< RESYNC_PT2 Mask */ + +#define MXC_F_PTG_RESYNC_PT3_POS 3 /**< RESYNC_PT3 Position */ +#define MXC_F_PTG_RESYNC_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT3_POS)) /**< RESYNC_PT3 Mask */ + +/**@} end of group PTG_RESYNC_Register */ + +/** + * @ingroup ptg_registers + * @defgroup PTG_STOP_INTFL PTG_STOP_INTFL + * @brief Pulse Train Stop Interrupt Flags + * @{ + */ +#define MXC_F_PTG_STOP_INTFL_PT0_POS 0 /**< STOP_INTFL_PT0 Position */ +#define MXC_F_PTG_STOP_INTFL_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTFL_PT0_POS)) /**< STOP_INTFL_PT0 Mask */ + +#define MXC_F_PTG_STOP_INTFL_PT1_POS 1 /**< STOP_INTFL_PT1 Position */ +#define MXC_F_PTG_STOP_INTFL_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTFL_PT1_POS)) /**< STOP_INTFL_PT1 Mask */ + +#define MXC_F_PTG_STOP_INTFL_PT2_POS 2 /**< STOP_INTFL_PT2 Position */ +#define MXC_F_PTG_STOP_INTFL_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTFL_PT2_POS)) /**< STOP_INTFL_PT2 Mask */ + +#define MXC_F_PTG_STOP_INTFL_PT3_POS 3 /**< STOP_INTFL_PT3 Position */ +#define MXC_F_PTG_STOP_INTFL_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTFL_PT3_POS)) /**< STOP_INTFL_PT3 Mask */ + +/**@} end of group PTG_STOP_INTFL_Register */ + +/** + * @ingroup ptg_registers + * @defgroup PTG_STOP_INTEN PTG_STOP_INTEN + * @brief Pulse Train Stop Interrupt Enable/Disable + * @{ + */ +#define MXC_F_PTG_STOP_INTEN_PT0_POS 0 /**< STOP_INTEN_PT0 Position */ +#define MXC_F_PTG_STOP_INTEN_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTEN_PT0_POS)) /**< STOP_INTEN_PT0 Mask */ + +#define MXC_F_PTG_STOP_INTEN_PT1_POS 1 /**< STOP_INTEN_PT1 Position */ +#define MXC_F_PTG_STOP_INTEN_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTEN_PT1_POS)) /**< STOP_INTEN_PT1 Mask */ + +#define MXC_F_PTG_STOP_INTEN_PT2_POS 2 /**< STOP_INTEN_PT2 Position */ +#define MXC_F_PTG_STOP_INTEN_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTEN_PT2_POS)) /**< STOP_INTEN_PT2 Mask */ + +#define MXC_F_PTG_STOP_INTEN_PT3_POS 3 /**< STOP_INTEN_PT3 Position */ +#define MXC_F_PTG_STOP_INTEN_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTEN_PT3_POS)) /**< STOP_INTEN_PT3 Mask */ + +/**@} end of group PTG_STOP_INTEN_Register */ + +/** + * @ingroup ptg_registers + * @defgroup PTG_SAFE_EN PTG_SAFE_EN + * @brief Pulse Train Global Safe Enable. + * @{ + */ +#define MXC_F_PTG_SAFE_EN_PT0_POS 0 /**< SAFE_EN_PT0 Position */ +#define MXC_F_PTG_SAFE_EN_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT0_POS)) /**< SAFE_EN_PT0 Mask */ + +#define MXC_F_PTG_SAFE_EN_PT1_POS 1 /**< SAFE_EN_PT1 Position */ +#define MXC_F_PTG_SAFE_EN_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT1_POS)) /**< SAFE_EN_PT1 Mask */ + +#define MXC_F_PTG_SAFE_EN_PT2_POS 2 /**< SAFE_EN_PT2 Position */ +#define MXC_F_PTG_SAFE_EN_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT2_POS)) /**< SAFE_EN_PT2 Mask */ + +#define MXC_F_PTG_SAFE_EN_PT3_POS 3 /**< SAFE_EN_PT3 Position */ +#define MXC_F_PTG_SAFE_EN_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT3_POS)) /**< SAFE_EN_PT3 Mask */ + +/**@} end of group PTG_SAFE_EN_Register */ + +/** + * @ingroup ptg_registers + * @defgroup PTG_SAFE_DIS PTG_SAFE_DIS + * @brief Pulse Train Global Safe Disable. + * @{ + */ +#define MXC_F_PTG_SAFE_DIS_PT0_POS 0 /**< SAFE_DIS_PT0 Position */ +#define MXC_F_PTG_SAFE_DIS_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT0_POS)) /**< SAFE_DIS_PT0 Mask */ + +#define MXC_F_PTG_SAFE_DIS_PT1_POS 1 /**< SAFE_DIS_PT1 Position */ +#define MXC_F_PTG_SAFE_DIS_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT1_POS)) /**< SAFE_DIS_PT1 Mask */ + +#define MXC_F_PTG_SAFE_DIS_PT2_POS 2 /**< SAFE_DIS_PT2 Position */ +#define MXC_F_PTG_SAFE_DIS_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT2_POS)) /**< SAFE_DIS_PT2 Mask */ + +#define MXC_F_PTG_SAFE_DIS_PT3_POS 3 /**< SAFE_DIS_PT3 Position */ +#define MXC_F_PTG_SAFE_DIS_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT3_POS)) /**< SAFE_DIS_PT3 Mask */ + +/**@} end of group PTG_SAFE_DIS_Register */ + +/** + * @ingroup ptg_registers + * @defgroup PTG_READY_INTFL PTG_READY_INTFL + * @brief Pulse Train Ready Interrupt Flags + * @{ + */ +#define MXC_F_PTG_READY_INTFL_PT0_POS 0 /**< READY_INTFL_PT0 Position */ +#define MXC_F_PTG_READY_INTFL_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT0_POS)) /**< READY_INTFL_PT0 Mask */ + +#define MXC_F_PTG_READY_INTFL_PT1_POS 1 /**< READY_INTFL_PT1 Position */ +#define MXC_F_PTG_READY_INTFL_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT1_POS)) /**< READY_INTFL_PT1 Mask */ + +#define MXC_F_PTG_READY_INTFL_PT2_POS 2 /**< READY_INTFL_PT2 Position */ +#define MXC_F_PTG_READY_INTFL_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT2_POS)) /**< READY_INTFL_PT2 Mask */ + +#define MXC_F_PTG_READY_INTFL_PT3_POS 3 /**< READY_INTFL_PT3 Position */ +#define MXC_F_PTG_READY_INTFL_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT3_POS)) /**< READY_INTFL_PT3 Mask */ + +/**@} end of group PTG_READY_INTFL_Register */ + +/** + * @ingroup ptg_registers + * @defgroup PTG_READY_INTEN PTG_READY_INTEN + * @brief Pulse Train Ready Interrupt Enable/Disable + * @{ + */ +#define MXC_F_PTG_READY_INTEN_PT0_POS 0 /**< READY_INTEN_PT0 Position */ +#define MXC_F_PTG_READY_INTEN_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT0_POS)) /**< READY_INTEN_PT0 Mask */ + +#define MXC_F_PTG_READY_INTEN_PT1_POS 1 /**< READY_INTEN_PT1 Position */ +#define MXC_F_PTG_READY_INTEN_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT1_POS)) /**< READY_INTEN_PT1 Mask */ + +#define MXC_F_PTG_READY_INTEN_PT2_POS 2 /**< READY_INTEN_PT2 Position */ +#define MXC_F_PTG_READY_INTEN_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT2_POS)) /**< READY_INTEN_PT2 Mask */ + +#define MXC_F_PTG_READY_INTEN_PT3_POS 3 /**< READY_INTEN_PT3 Position */ +#define MXC_F_PTG_READY_INTEN_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT3_POS)) /**< READY_INTEN_PT3 Mask */ + +/**@} end of group PTG_READY_INTEN_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_PTG_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/pwrseq_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/pwrseq_regs.h new file mode 100644 index 00000000000..31e6bfe4f4f --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/pwrseq_regs.h @@ -0,0 +1,1364 @@ +/** + * @file pwrseq_regs.h + * @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module. + * @note This file is @generated. + * @ingroup pwrseq_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_PWRSEQ_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_PWRSEQ_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup pwrseq + * @defgroup pwrseq_registers PWRSEQ_Registers + * @brief Registers, Bit Masks and Bit Positions for the PWRSEQ Peripheral Module. + * @details Power Sequencer / Low Power Control Register. + */ + +/** + * @ingroup pwrseq_registers + * Structure type to access the PWRSEQ Registers. + */ +typedef struct { + __IO uint32_t lpctrl; /**< \b 0x00: PWRSEQ LPCTRL Register */ + __IO uint32_t lpwkfl0; /**< \b 0x04: PWRSEQ LPWKFL0 Register */ + __IO uint32_t lpwken0; /**< \b 0x08: PWRSEQ LPWKEN0 Register */ + __IO uint32_t lpwkfl1; /**< \b 0x0C: PWRSEQ LPWKFL1 Register */ + __IO uint32_t lpwken1; /**< \b 0x10: PWRSEQ LPWKEN1 Register */ + __IO uint32_t lpwkfl2; /**< \b 0x14: PWRSEQ LPWKFL2 Register */ + __IO uint32_t lpwken2; /**< \b 0x18: PWRSEQ LPWKEN2 Register */ + __IO uint32_t lpwkfl3; /**< \b 0x1C: PWRSEQ LPWKFL3 Register */ + __IO uint32_t lpwken3; /**< \b 0x20: PWRSEQ LPWKEN3 Register */ + __R uint32_t rsv_0x24_0x2f[3]; + __IO uint32_t lppwkfl; /**< \b 0x30: PWRSEQ LPPWKFL Register */ + __IO uint32_t lppwken; /**< \b 0x34: PWRSEQ LPPWKEN Register */ + __R uint32_t rsv_0x38_0x3f[2]; + __IO uint32_t lpmemsd; /**< \b 0x40: PWRSEQ LPMEMSD Register */ + __IO uint32_t lpvddpd; /**< \b 0x44: PWRSEQ LPVDDPD Register */ + __IO uint32_t gp0; /**< \b 0x48: PWRSEQ GP0 Register */ + __IO uint32_t gp1; /**< \b 0x4C: PWRSEQ GP1 Register */ + __IO uint32_t lpwkpol0a; /**< \b 0x50: PWRSEQ LPWKPOL0A Register */ + __IO uint32_t lpwkpol0b; /**< \b 0x54: PWRSEQ LPWKPOL0B Register */ + __IO uint32_t lpwkpol1a; /**< \b 0x58: PWRSEQ LPWKPOL1A Register */ + __IO uint32_t lpwkpol1b; /**< \b 0x5C: PWRSEQ LPWKPOL1B Register */ + __IO uint32_t lpwkpol2a; /**< \b 0x60: PWRSEQ LPWKPOL2A Register */ + __IO uint32_t lpwkpol2b; /**< \b 0x64: PWRSEQ LPWKPOL2B Register */ + __IO uint32_t lpwkpol3; /**< \b 0x68: PWRSEQ LPWKPOL3 Register */ +} mxc_pwrseq_regs_t; + +/* Register offsets for module PWRSEQ */ +/** + * @ingroup pwrseq_registers + * @defgroup PWRSEQ_Register_Offsets Register Offsets + * @brief PWRSEQ Peripheral Register Offsets from the PWRSEQ Base Peripheral Address. + * @{ + */ +#define MXC_R_PWRSEQ_LPCTRL ((uint32_t)0x00000000UL) /**< Offset from PWRSEQ Base Address: 0x0000 */ +#define MXC_R_PWRSEQ_LPWKFL0 ((uint32_t)0x00000004UL) /**< Offset from PWRSEQ Base Address: 0x0004 */ +#define MXC_R_PWRSEQ_LPWKEN0 ((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: 0x0008 */ +#define MXC_R_PWRSEQ_LPWKFL1 ((uint32_t)0x0000000CUL) /**< Offset from PWRSEQ Base Address: 0x000C */ +#define MXC_R_PWRSEQ_LPWKEN1 ((uint32_t)0x00000010UL) /**< Offset from PWRSEQ Base Address: 0x0010 */ +#define MXC_R_PWRSEQ_LPWKFL2 ((uint32_t)0x00000014UL) /**< Offset from PWRSEQ Base Address: 0x0014 */ +#define MXC_R_PWRSEQ_LPWKEN2 ((uint32_t)0x00000018UL) /**< Offset from PWRSEQ Base Address: 0x0018 */ +#define MXC_R_PWRSEQ_LPWKFL3 ((uint32_t)0x0000001CUL) /**< Offset from PWRSEQ Base Address: 0x001C */ +#define MXC_R_PWRSEQ_LPWKEN3 ((uint32_t)0x00000020UL) /**< Offset from PWRSEQ Base Address: 0x0020 */ +#define MXC_R_PWRSEQ_LPPWKFL ((uint32_t)0x00000030UL) /**< Offset from PWRSEQ Base Address: 0x0030 */ +#define MXC_R_PWRSEQ_LPPWKEN ((uint32_t)0x00000034UL) /**< Offset from PWRSEQ Base Address: 0x0034 */ +#define MXC_R_PWRSEQ_LPMEMSD ((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: 0x0040 */ +#define MXC_R_PWRSEQ_LPVDDPD ((uint32_t)0x00000044UL) /**< Offset from PWRSEQ Base Address: 0x0044 */ +#define MXC_R_PWRSEQ_GP0 ((uint32_t)0x00000048UL) /**< Offset from PWRSEQ Base Address: 0x0048 */ +#define MXC_R_PWRSEQ_GP1 ((uint32_t)0x0000004CUL) /**< Offset from PWRSEQ Base Address: 0x004C */ +#define MXC_R_PWRSEQ_LPWKPOL0A ((uint32_t)0x00000050UL) /**< Offset from PWRSEQ Base Address: 0x0050 */ +#define MXC_R_PWRSEQ_LPWKPOL0B ((uint32_t)0x00000054UL) /**< Offset from PWRSEQ Base Address: 0x0054 */ +#define MXC_R_PWRSEQ_LPWKPOL1A ((uint32_t)0x00000058UL) /**< Offset from PWRSEQ Base Address: 0x0058 */ +#define MXC_R_PWRSEQ_LPWKPOL1B ((uint32_t)0x0000005CUL) /**< Offset from PWRSEQ Base Address: 0x005C */ +#define MXC_R_PWRSEQ_LPWKPOL2A ((uint32_t)0x00000060UL) /**< Offset from PWRSEQ Base Address: 0x0060 */ +#define MXC_R_PWRSEQ_LPWKPOL2B ((uint32_t)0x00000064UL) /**< Offset from PWRSEQ Base Address: 0x0064 */ +#define MXC_R_PWRSEQ_LPWKPOL3 ((uint32_t)0x00000068UL) /**< Offset from PWRSEQ Base Address: 0x0068 */ +/**@} end of group pwrseq_registers */ + +/** + * @ingroup pwrseq_registers + * @defgroup PWRSEQ_LPCTRL PWRSEQ_LPCTRL + * @brief Low Power Control Register. + * @{ + */ +#define MXC_F_PWRSEQ_LPCTRL_RAMRET_EN_POS 0 /**< LPCTRL_RAMRET_EN Position */ +#define MXC_F_PWRSEQ_LPCTRL_RAMRET_EN ((uint32_t)(0xFUL << MXC_F_PWRSEQ_LPCTRL_RAMRET_EN_POS)) /**< LPCTRL_RAMRET_EN Mask */ + +#define MXC_F_PWRSEQ_LPCTRL_OVR_POS 4 /**< LPCTRL_OVR Position */ +#define MXC_F_PWRSEQ_LPCTRL_OVR ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPCTRL_OVR_POS)) /**< LPCTRL_OVR Mask */ +#define MXC_V_PWRSEQ_LPCTRL_OVR_1_1V ((uint32_t)0x2UL) /**< LPCTRL_OVR_1_1V Value */ +#define MXC_S_PWRSEQ_LPCTRL_OVR_1_1V (MXC_V_PWRSEQ_LPCTRL_OVR_1_1V << MXC_F_PWRSEQ_LPCTRL_OVR_POS) /**< LPCTRL_OVR_1_1V Setting */ + +#define MXC_F_PWRSEQ_LPCTRL_RETREG_EN_POS 8 /**< LPCTRL_RETREG_EN Position */ +#define MXC_F_PWRSEQ_LPCTRL_RETREG_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_RETREG_EN_POS)) /**< LPCTRL_RETREG_EN Mask */ + +#define MXC_F_PWRSEQ_LPCTRL_FASTWK_EN_POS 10 /**< LPCTRL_FASTWK_EN Position */ +#define MXC_F_PWRSEQ_LPCTRL_FASTWK_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_FASTWK_EN_POS)) /**< LPCTRL_FASTWK_EN Mask */ + +#define MXC_F_PWRSEQ_LPCTRL_BG_DIS_POS 11 /**< LPCTRL_BG_DIS Position */ +#define MXC_F_PWRSEQ_LPCTRL_BG_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_BG_DIS_POS)) /**< LPCTRL_BG_DIS Mask */ + +#define MXC_F_PWRSEQ_LPCTRL_PORVDDCMON_DIS_POS 12 /**< LPCTRL_PORVDDCMON_DIS Position */ +#define MXC_F_PWRSEQ_LPCTRL_PORVDDCMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_PORVDDCMON_DIS_POS)) /**< LPCTRL_PORVDDCMON_DIS Mask */ + +#define MXC_F_PWRSEQ_LPCTRL_VDDIOHHVMON_DIS_POS 17 /**< LPCTRL_VDDIOHHVMON_DIS Position */ +#define MXC_F_PWRSEQ_LPCTRL_VDDIOHHVMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VDDIOHHVMON_DIS_POS)) /**< LPCTRL_VDDIOHHVMON_DIS Mask */ + +#define MXC_F_PWRSEQ_LPCTRL_VDDIOHVMON_DIS_POS 18 /**< LPCTRL_VDDIOHVMON_DIS Position */ +#define MXC_F_PWRSEQ_LPCTRL_VDDIOHVMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VDDIOHVMON_DIS_POS)) /**< LPCTRL_VDDIOHVMON_DIS Mask */ + +#define MXC_F_PWRSEQ_LPCTRL_VCOREHVMON_DIS_POS 19 /**< LPCTRL_VCOREHVMON_DIS Position */ +#define MXC_F_PWRSEQ_LPCTRL_VCOREHVMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VCOREHVMON_DIS_POS)) /**< LPCTRL_VCOREHVMON_DIS Mask */ + +#define MXC_F_PWRSEQ_LPCTRL_VDDCMON_DIS_POS 20 /**< LPCTRL_VDDCMON_DIS Position */ +#define MXC_F_PWRSEQ_LPCTRL_VDDCMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VDDCMON_DIS_POS)) /**< LPCTRL_VDDCMON_DIS Mask */ + +#define MXC_F_PWRSEQ_LPCTRL_VRTCMON_DIS_POS 21 /**< LPCTRL_VRTCMON_DIS Position */ +#define MXC_F_PWRSEQ_LPCTRL_VRTCMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VRTCMON_DIS_POS)) /**< LPCTRL_VRTCMON_DIS Mask */ + +#define MXC_F_PWRSEQ_LPCTRL_VDDAMON_DIS_POS 22 /**< LPCTRL_VDDAMON_DIS Position */ +#define MXC_F_PWRSEQ_LPCTRL_VDDAMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VDDAMON_DIS_POS)) /**< LPCTRL_VDDAMON_DIS Mask */ + +#define MXC_F_PWRSEQ_LPCTRL_VDDIOMON_DIS_POS 23 /**< LPCTRL_VDDIOMON_DIS Position */ +#define MXC_F_PWRSEQ_LPCTRL_VDDIOMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VDDIOMON_DIS_POS)) /**< LPCTRL_VDDIOMON_DIS Mask */ + +#define MXC_F_PWRSEQ_LPCTRL_VDDIOHMON_DIS_POS 24 /**< LPCTRL_VDDIOHMON_DIS Position */ +#define MXC_F_PWRSEQ_LPCTRL_VDDIOHMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VDDIOHMON_DIS_POS)) /**< LPCTRL_VDDIOHMON_DIS Mask */ + +#define MXC_F_PWRSEQ_LPCTRL_VDDBMON_DIS_POS 27 /**< LPCTRL_VDDBMON_DIS Position */ +#define MXC_F_PWRSEQ_LPCTRL_VDDBMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VDDBMON_DIS_POS)) /**< LPCTRL_VDDBMON_DIS Mask */ + +/**@} end of group PWRSEQ_LPCTRL_Register */ + +/** + * @ingroup pwrseq_registers + * @defgroup PWRSEQ_LPWKFL0 PWRSEQ_LPWKFL0 + * @brief Low Power I/O Wakeup Status Register 0. This register indicates the low power + * wakeup status for GPIO0. + * @{ + */ +#define MXC_F_PWRSEQ_LPWKFL0_ALL_POS 0 /**< LPWKFL0_ALL Position */ +#define MXC_F_PWRSEQ_LPWKFL0_ALL ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRSEQ_LPWKFL0_ALL_POS)) /**< LPWKFL0_ALL Mask */ + +/**@} end of group PWRSEQ_LPWKFL0_Register */ + +/** + * @ingroup pwrseq_registers + * @defgroup PWRSEQ_LPWKEN0 PWRSEQ_LPWKEN0 + * @brief Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup + * functionality for GPIO0. + * @{ + */ +#define MXC_F_PWRSEQ_LPWKEN0_ALL_POS 0 /**< LPWKEN0_ALL Position */ +#define MXC_F_PWRSEQ_LPWKEN0_ALL ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRSEQ_LPWKEN0_ALL_POS)) /**< LPWKEN0_ALL Mask */ + +/**@} end of group PWRSEQ_LPWKEN0_Register */ + +/** + * @ingroup pwrseq_registers + * @defgroup PWRSEQ_LPPWKFL PWRSEQ_LPPWKFL + * @brief Low Power Peripheral Wakeup Status Register. + * @{ + */ +#define MXC_F_PWRSEQ_LPPWKFL_USBLS_POS 0 /**< LPPWKFL_USBLS Position */ +#define MXC_F_PWRSEQ_LPPWKFL_USBLS ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPPWKFL_USBLS_POS)) /**< LPPWKFL_USBLS Mask */ + +#define MXC_F_PWRSEQ_LPPWKFL_AINCOMP0_POS 4 /**< LPPWKFL_AINCOMP0 Position */ +#define MXC_F_PWRSEQ_LPPWKFL_AINCOMP0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKFL_AINCOMP0_POS)) /**< LPPWKFL_AINCOMP0 Mask */ + +#define MXC_F_PWRSEQ_LPPWKFL_USBVBUS_POS 2 /**< LPPWKFL_USBVBUS Position */ +#define MXC_F_PWRSEQ_LPPWKFL_USBVBUS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKFL_USBVBUS_POS)) /**< LPPWKFL_USBVBUS Mask */ + +#define MXC_F_PWRSEQ_LPPWKFL_BACKUP_POS 16 /**< LPPWKFL_BACKUP Position */ +#define MXC_F_PWRSEQ_LPPWKFL_BACKUP ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKFL_BACKUP_POS)) /**< LPPWKFL_BACKUP Mask */ + +#define MXC_F_PWRSEQ_LPPWKFL_RSTDET_POS 17 /**< LPPWKFL_RSTDET Position */ +#define MXC_F_PWRSEQ_LPPWKFL_RSTDET ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKFL_RSTDET_POS)) /**< LPPWKFL_RSTDET Mask */ + +/**@} end of group PWRSEQ_LPPWKFL_Register */ + +/** + * @ingroup pwrseq_registers + * @defgroup PWRSEQ_LPPWKEN PWRSEQ_LPPWKEN + * @brief Low Power Peripheral Wakeup Enable Register. + * @{ + */ +#define MXC_F_PWRSEQ_LPPWKEN_USBLS_POS 0 /**< LPPWKEN_USBLS Position */ +#define MXC_F_PWRSEQ_LPPWKEN_USBLS ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPPWKEN_USBLS_POS)) /**< LPPWKEN_USBLS Mask */ + +#define MXC_F_PWRSEQ_LPPWKEN_USBVBUS_POS 2 /**< LPPWKEN_USBVBUS Position */ +#define MXC_F_PWRSEQ_LPPWKEN_USBVBUS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_USBVBUS_POS)) /**< LPPWKEN_USBVBUS Mask */ + +#define MXC_F_PWRSEQ_LPPWKEN_AINCOMP0_POS 4 /**< LPPWKEN_AINCOMP0 Position */ +#define MXC_F_PWRSEQ_LPPWKEN_AINCOMP0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_AINCOMP0_POS)) /**< LPPWKEN_AINCOMP0 Mask */ + +#define MXC_F_PWRSEQ_LPPWKEN_WDT0_POS 8 /**< LPPWKEN_WDT0 Position */ +#define MXC_F_PWRSEQ_LPPWKEN_WDT0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_WDT0_POS)) /**< LPPWKEN_WDT0 Mask */ + +#define MXC_F_PWRSEQ_LPPWKEN_WDT1_POS 9 /**< LPPWKEN_WDT1 Position */ +#define MXC_F_PWRSEQ_LPPWKEN_WDT1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_WDT1_POS)) /**< LPPWKEN_WDT1 Mask */ + +#define MXC_F_PWRSEQ_LPPWKEN_CPU1_POS 10 /**< LPPWKEN_CPU1 Position */ +#define MXC_F_PWRSEQ_LPPWKEN_CPU1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_CPU1_POS)) /**< LPPWKEN_CPU1 Mask */ + +#define MXC_F_PWRSEQ_LPPWKEN_TMR0_POS 11 /**< LPPWKEN_TMR0 Position */ +#define MXC_F_PWRSEQ_LPPWKEN_TMR0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_TMR0_POS)) /**< LPPWKEN_TMR0 Mask */ + +#define MXC_F_PWRSEQ_LPPWKEN_TMR1_POS 12 /**< LPPWKEN_TMR1 Position */ +#define MXC_F_PWRSEQ_LPPWKEN_TMR1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_TMR1_POS)) /**< LPPWKEN_TMR1 Mask */ + +#define MXC_F_PWRSEQ_LPPWKEN_TMR2_POS 13 /**< LPPWKEN_TMR2 Position */ +#define MXC_F_PWRSEQ_LPPWKEN_TMR2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_TMR2_POS)) /**< LPPWKEN_TMR2 Mask */ + +#define MXC_F_PWRSEQ_LPPWKEN_TMR3_POS 14 /**< LPPWKEN_TMR3 Position */ +#define MXC_F_PWRSEQ_LPPWKEN_TMR3 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_TMR3_POS)) /**< LPPWKEN_TMR3 Mask */ + +#define MXC_F_PWRSEQ_LPPWKEN_TMR4_POS 15 /**< LPPWKEN_TMR4 Position */ +#define MXC_F_PWRSEQ_LPPWKEN_TMR4 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_TMR4_POS)) /**< LPPWKEN_TMR4 Mask */ + +#define MXC_F_PWRSEQ_LPPWKEN_TMR5_POS 16 /**< LPPWKEN_TMR5 Position */ +#define MXC_F_PWRSEQ_LPPWKEN_TMR5 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_TMR5_POS)) /**< LPPWKEN_TMR5 Mask */ + +#define MXC_F_PWRSEQ_LPPWKEN_UART0_POS 17 /**< LPPWKEN_UART0 Position */ +#define MXC_F_PWRSEQ_LPPWKEN_UART0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_UART0_POS)) /**< LPPWKEN_UART0 Mask */ + +#define MXC_F_PWRSEQ_LPPWKEN_UART1_POS 18 /**< LPPWKEN_UART1 Position */ +#define MXC_F_PWRSEQ_LPPWKEN_UART1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_UART1_POS)) /**< LPPWKEN_UART1 Mask */ + +#define MXC_F_PWRSEQ_LPPWKEN_UART2_POS 19 /**< LPPWKEN_UART2 Position */ +#define MXC_F_PWRSEQ_LPPWKEN_UART2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_UART2_POS)) /**< LPPWKEN_UART2 Mask */ + +#define MXC_F_PWRSEQ_LPPWKEN_UART3_POS 20 /**< LPPWKEN_UART3 Position */ +#define MXC_F_PWRSEQ_LPPWKEN_UART3 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_UART3_POS)) /**< LPPWKEN_UART3 Mask */ + +#define MXC_F_PWRSEQ_LPPWKEN_I2C0_POS 21 /**< LPPWKEN_I2C0 Position */ +#define MXC_F_PWRSEQ_LPPWKEN_I2C0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_I2C0_POS)) /**< LPPWKEN_I2C0 Mask */ + +#define MXC_F_PWRSEQ_LPPWKEN_I2C1_POS 22 /**< LPPWKEN_I2C1 Position */ +#define MXC_F_PWRSEQ_LPPWKEN_I2C1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_I2C1_POS)) /**< LPPWKEN_I2C1 Mask */ + +#define MXC_F_PWRSEQ_LPPWKEN_I2C2_POS 23 /**< LPPWKEN_I2C2 Position */ +#define MXC_F_PWRSEQ_LPPWKEN_I2C2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_I2C2_POS)) /**< LPPWKEN_I2C2 Mask */ + +#define MXC_F_PWRSEQ_LPPWKEN_I2S_POS 24 /**< LPPWKEN_I2S Position */ +#define MXC_F_PWRSEQ_LPPWKEN_I2S ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_I2S_POS)) /**< LPPWKEN_I2S Mask */ + +#define MXC_F_PWRSEQ_LPPWKEN_SPI1_POS 25 /**< LPPWKEN_SPI1 Position */ +#define MXC_F_PWRSEQ_LPPWKEN_SPI1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_SPI1_POS)) /**< LPPWKEN_SPI1 Mask */ + +#define MXC_F_PWRSEQ_LPPWKEN_LPCMP_POS 26 /**< LPPWKEN_LPCMP Position */ +#define MXC_F_PWRSEQ_LPPWKEN_LPCMP ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_LPCMP_POS)) /**< LPPWKEN_LPCMP Mask */ + +/**@} end of group PWRSEQ_LPPWKEN_Register */ + +/** + * @ingroup pwrseq_registers + * @defgroup PWRSEQ_LPMEMSD PWRSEQ_LPMEMSD + * @brief Low Power Memory Shutdown Control. + * @{ + */ +#define MXC_F_PWRSEQ_LPMEMSD_RAM0_POS 0 /**< LPMEMSD_RAM0 Position */ +#define MXC_F_PWRSEQ_LPMEMSD_RAM0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM0_POS)) /**< LPMEMSD_RAM0 Mask */ + +#define MXC_F_PWRSEQ_LPMEMSD_RAM1_POS 1 /**< LPMEMSD_RAM1 Position */ +#define MXC_F_PWRSEQ_LPMEMSD_RAM1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM1_POS)) /**< LPMEMSD_RAM1 Mask */ + +#define MXC_F_PWRSEQ_LPMEMSD_RAM2_POS 2 /**< LPMEMSD_RAM2 Position */ +#define MXC_F_PWRSEQ_LPMEMSD_RAM2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM2_POS)) /**< LPMEMSD_RAM2 Mask */ + +#define MXC_F_PWRSEQ_LPMEMSD_RAM3_POS 3 /**< LPMEMSD_RAM3 Position */ +#define MXC_F_PWRSEQ_LPMEMSD_RAM3 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM3_POS)) /**< LPMEMSD_RAM3 Mask */ + +#define MXC_F_PWRSEQ_LPMEMSD_RAM4_POS 4 /**< LPMEMSD_RAM4 Position */ +#define MXC_F_PWRSEQ_LPMEMSD_RAM4 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM4_POS)) /**< LPMEMSD_RAM4 Mask */ + +#define MXC_F_PWRSEQ_LPMEMSD_RAM5_POS 5 /**< LPMEMSD_RAM5 Position */ +#define MXC_F_PWRSEQ_LPMEMSD_RAM5 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM5_POS)) /**< LPMEMSD_RAM5 Mask */ + +#define MXC_F_PWRSEQ_LPMEMSD_ICC_POS 7 /**< LPMEMSD_ICC Position */ +#define MXC_F_PWRSEQ_LPMEMSD_ICC ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ICC_POS)) /**< LPMEMSD_ICC Mask */ + +#define MXC_F_PWRSEQ_LPMEMSD_ICCXIP_POS 8 /**< LPMEMSD_ICCXIP Position */ +#define MXC_F_PWRSEQ_LPMEMSD_ICCXIP ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ICCXIP_POS)) /**< LPMEMSD_ICCXIP Mask */ + +#define MXC_F_PWRSEQ_LPMEMSD_SRCC_POS 9 /**< LPMEMSD_SRCC Position */ +#define MXC_F_PWRSEQ_LPMEMSD_SRCC ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRCC_POS)) /**< LPMEMSD_SRCC Mask */ + +#define MXC_F_PWRSEQ_LPMEMSD_USBFIFO_POS 11 /**< LPMEMSD_USBFIFO Position */ +#define MXC_F_PWRSEQ_LPMEMSD_USBFIFO ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_USBFIFO_POS)) /**< LPMEMSD_USBFIFO Mask */ + +#define MXC_F_PWRSEQ_LPMEMSD_ROM0_POS 12 /**< LPMEMSD_ROM0 Position */ +#define MXC_F_PWRSEQ_LPMEMSD_ROM0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ROM0_POS)) /**< LPMEMSD_ROM0 Mask */ + +#define MXC_F_PWRSEQ_LPMEMSD_MEU_POS 13 /**< LPMEMSD_MEU Position */ +#define MXC_F_PWRSEQ_LPMEMSD_MEU ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_MEU_POS)) /**< LPMEMSD_MEU Mask */ + +#define MXC_F_PWRSEQ_LPMEMSD_ROM1_POS 15 /**< LPMEMSD_ROM1 Position */ +#define MXC_F_PWRSEQ_LPMEMSD_ROM1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ROM1_POS)) /**< LPMEMSD_ROM1 Mask */ + +/**@} end of group PWRSEQ_LPMEMSD_Register */ + +/** + * @ingroup pwrseq_registers + * @defgroup PWRSEQ_LPVDDPD PWRSEQ_LPVDDPD + * @brief Low Power VDD Domain Power Down Control. + * @{ + */ +#define MXC_F_PWRSEQ_LPVDDPD_BTLE_POS 1 /**< LPVDDPD_BTLE Position */ +#define MXC_F_PWRSEQ_LPVDDPD_BTLE ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPVDDPD_BTLE_POS)) /**< LPVDDPD_BTLE Mask */ + +/**@} end of group PWRSEQ_LPVDDPD_Register */ + +/** + * @ingroup pwrseq_registers + * @defgroup PWRSEQ_LPWKPOL0A PWRSEQ_LPWKPOL0A + * @brief Low Power Wakeup Polarity Select for GPIO0. + * @{ + */ +#define MXC_F_PWRSEQ_LPWKPOL0A_0_POS 0 /**< LPWKPOL0A_0 Position */ +#define MXC_F_PWRSEQ_LPWKPOL0A_0 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0A_0_POS)) /**< LPWKPOL0A_0 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL0A_0_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0A_0_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_0_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0A_0_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0A_0_POS) /**< LPWKPOL0A_0_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0A_0_RISING ((uint32_t)0x1UL) /**< LPWKPOL0A_0_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_0_RISING (MXC_V_PWRSEQ_LPWKPOL0A_0_RISING << MXC_F_PWRSEQ_LPWKPOL0A_0_POS) /**< LPWKPOL0A_0_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0A_0_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0A_0_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_0_FALLING (MXC_V_PWRSEQ_LPWKPOL0A_0_FALLING << MXC_F_PWRSEQ_LPWKPOL0A_0_POS) /**< LPWKPOL0A_0_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL0A_1_POS 2 /**< LPWKPOL0A_1 Position */ +#define MXC_F_PWRSEQ_LPWKPOL0A_1 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0A_1_POS)) /**< LPWKPOL0A_1 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL0A_1_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0A_1_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_1_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0A_1_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0A_1_POS) /**< LPWKPOL0A_1_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0A_1_RISING ((uint32_t)0x1UL) /**< LPWKPOL0A_1_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_1_RISING (MXC_V_PWRSEQ_LPWKPOL0A_1_RISING << MXC_F_PWRSEQ_LPWKPOL0A_1_POS) /**< LPWKPOL0A_1_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0A_1_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0A_1_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_1_FALLING (MXC_V_PWRSEQ_LPWKPOL0A_1_FALLING << MXC_F_PWRSEQ_LPWKPOL0A_1_POS) /**< LPWKPOL0A_1_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL0A_2_POS 4 /**< LPWKPOL0A_2 Position */ +#define MXC_F_PWRSEQ_LPWKPOL0A_2 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0A_2_POS)) /**< LPWKPOL0A_2 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL0A_2_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0A_2_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_2_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0A_2_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0A_2_POS) /**< LPWKPOL0A_2_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0A_2_RISING ((uint32_t)0x1UL) /**< LPWKPOL0A_2_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_2_RISING (MXC_V_PWRSEQ_LPWKPOL0A_2_RISING << MXC_F_PWRSEQ_LPWKPOL0A_2_POS) /**< LPWKPOL0A_2_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0A_2_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0A_2_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_2_FALLING (MXC_V_PWRSEQ_LPWKPOL0A_2_FALLING << MXC_F_PWRSEQ_LPWKPOL0A_2_POS) /**< LPWKPOL0A_2_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL0A_3_POS 6 /**< LPWKPOL0A_3 Position */ +#define MXC_F_PWRSEQ_LPWKPOL0A_3 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0A_3_POS)) /**< LPWKPOL0A_3 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL0A_3_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0A_3_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_3_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0A_3_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0A_3_POS) /**< LPWKPOL0A_3_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0A_3_RISING ((uint32_t)0x1UL) /**< LPWKPOL0A_3_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_3_RISING (MXC_V_PWRSEQ_LPWKPOL0A_3_RISING << MXC_F_PWRSEQ_LPWKPOL0A_3_POS) /**< LPWKPOL0A_3_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0A_3_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0A_3_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_3_FALLING (MXC_V_PWRSEQ_LPWKPOL0A_3_FALLING << MXC_F_PWRSEQ_LPWKPOL0A_3_POS) /**< LPWKPOL0A_3_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL0A_4_POS 8 /**< LPWKPOL0A_4 Position */ +#define MXC_F_PWRSEQ_LPWKPOL0A_4 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0A_4_POS)) /**< LPWKPOL0A_4 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL0A_4_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0A_4_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_4_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0A_4_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0A_4_POS) /**< LPWKPOL0A_4_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0A_4_RISING ((uint32_t)0x1UL) /**< LPWKPOL0A_4_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_4_RISING (MXC_V_PWRSEQ_LPWKPOL0A_4_RISING << MXC_F_PWRSEQ_LPWKPOL0A_4_POS) /**< LPWKPOL0A_4_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0A_4_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0A_4_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_4_FALLING (MXC_V_PWRSEQ_LPWKPOL0A_4_FALLING << MXC_F_PWRSEQ_LPWKPOL0A_4_POS) /**< LPWKPOL0A_4_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL0A_5_POS 10 /**< LPWKPOL0A_5 Position */ +#define MXC_F_PWRSEQ_LPWKPOL0A_5 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0A_5_POS)) /**< LPWKPOL0A_5 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL0A_5_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0A_5_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_5_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0A_5_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0A_5_POS) /**< LPWKPOL0A_5_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0A_5_RISING ((uint32_t)0x1UL) /**< LPWKPOL0A_5_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_5_RISING (MXC_V_PWRSEQ_LPWKPOL0A_5_RISING << MXC_F_PWRSEQ_LPWKPOL0A_5_POS) /**< LPWKPOL0A_5_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0A_5_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0A_5_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_5_FALLING (MXC_V_PWRSEQ_LPWKPOL0A_5_FALLING << MXC_F_PWRSEQ_LPWKPOL0A_5_POS) /**< LPWKPOL0A_5_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL0A_6_POS 12 /**< LPWKPOL0A_6 Position */ +#define MXC_F_PWRSEQ_LPWKPOL0A_6 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0A_6_POS)) /**< LPWKPOL0A_6 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL0A_6_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0A_6_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_6_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0A_6_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0A_6_POS) /**< LPWKPOL0A_6_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0A_6_RISING ((uint32_t)0x1UL) /**< LPWKPOL0A_6_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_6_RISING (MXC_V_PWRSEQ_LPWKPOL0A_6_RISING << MXC_F_PWRSEQ_LPWKPOL0A_6_POS) /**< LPWKPOL0A_6_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0A_6_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0A_6_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_6_FALLING (MXC_V_PWRSEQ_LPWKPOL0A_6_FALLING << MXC_F_PWRSEQ_LPWKPOL0A_6_POS) /**< LPWKPOL0A_6_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL0A_7_POS 14 /**< LPWKPOL0A_7 Position */ +#define MXC_F_PWRSEQ_LPWKPOL0A_7 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0A_7_POS)) /**< LPWKPOL0A_7 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL0A_7_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0A_7_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_7_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0A_7_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0A_7_POS) /**< LPWKPOL0A_7_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0A_7_RISING ((uint32_t)0x1UL) /**< LPWKPOL0A_7_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_7_RISING (MXC_V_PWRSEQ_LPWKPOL0A_7_RISING << MXC_F_PWRSEQ_LPWKPOL0A_7_POS) /**< LPWKPOL0A_7_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0A_7_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0A_7_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_7_FALLING (MXC_V_PWRSEQ_LPWKPOL0A_7_FALLING << MXC_F_PWRSEQ_LPWKPOL0A_7_POS) /**< LPWKPOL0A_7_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL0A_8_POS 16 /**< LPWKPOL0A_8 Position */ +#define MXC_F_PWRSEQ_LPWKPOL0A_8 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0A_8_POS)) /**< LPWKPOL0A_8 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL0A_8_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0A_8_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_8_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0A_8_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0A_8_POS) /**< LPWKPOL0A_8_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0A_8_RISING ((uint32_t)0x1UL) /**< LPWKPOL0A_8_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_8_RISING (MXC_V_PWRSEQ_LPWKPOL0A_8_RISING << MXC_F_PWRSEQ_LPWKPOL0A_8_POS) /**< LPWKPOL0A_8_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0A_8_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0A_8_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_8_FALLING (MXC_V_PWRSEQ_LPWKPOL0A_8_FALLING << MXC_F_PWRSEQ_LPWKPOL0A_8_POS) /**< LPWKPOL0A_8_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL0A_9_POS 18 /**< LPWKPOL0A_9 Position */ +#define MXC_F_PWRSEQ_LPWKPOL0A_9 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0A_9_POS)) /**< LPWKPOL0A_9 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL0A_9_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0A_9_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_9_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0A_9_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0A_9_POS) /**< LPWKPOL0A_9_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0A_9_RISING ((uint32_t)0x1UL) /**< LPWKPOL0A_9_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_9_RISING (MXC_V_PWRSEQ_LPWKPOL0A_9_RISING << MXC_F_PWRSEQ_LPWKPOL0A_9_POS) /**< LPWKPOL0A_9_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0A_9_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0A_9_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_9_FALLING (MXC_V_PWRSEQ_LPWKPOL0A_9_FALLING << MXC_F_PWRSEQ_LPWKPOL0A_9_POS) /**< LPWKPOL0A_9_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL0A_10_POS 20 /**< LPWKPOL0A_10 Position */ +#define MXC_F_PWRSEQ_LPWKPOL0A_10 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0A_10_POS)) /**< LPWKPOL0A_10 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL0A_10_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0A_10_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_10_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0A_10_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0A_10_POS) /**< LPWKPOL0A_10_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0A_10_RISING ((uint32_t)0x1UL) /**< LPWKPOL0A_10_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_10_RISING (MXC_V_PWRSEQ_LPWKPOL0A_10_RISING << MXC_F_PWRSEQ_LPWKPOL0A_10_POS) /**< LPWKPOL0A_10_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0A_10_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0A_10_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_10_FALLING (MXC_V_PWRSEQ_LPWKPOL0A_10_FALLING << MXC_F_PWRSEQ_LPWKPOL0A_10_POS) /**< LPWKPOL0A_10_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL0A_11_POS 22 /**< LPWKPOL0A_11 Position */ +#define MXC_F_PWRSEQ_LPWKPOL0A_11 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0A_11_POS)) /**< LPWKPOL0A_11 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL0A_11_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0A_11_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_11_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0A_11_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0A_11_POS) /**< LPWKPOL0A_11_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0A_11_RISING ((uint32_t)0x1UL) /**< LPWKPOL0A_11_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_11_RISING (MXC_V_PWRSEQ_LPWKPOL0A_11_RISING << MXC_F_PWRSEQ_LPWKPOL0A_11_POS) /**< LPWKPOL0A_11_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0A_11_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0A_11_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_11_FALLING (MXC_V_PWRSEQ_LPWKPOL0A_11_FALLING << MXC_F_PWRSEQ_LPWKPOL0A_11_POS) /**< LPWKPOL0A_11_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL0A_12_POS 24 /**< LPWKPOL0A_12 Position */ +#define MXC_F_PWRSEQ_LPWKPOL0A_12 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0A_12_POS)) /**< LPWKPOL0A_12 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL0A_12_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0A_12_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_12_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0A_12_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0A_12_POS) /**< LPWKPOL0A_12_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0A_12_RISING ((uint32_t)0x1UL) /**< LPWKPOL0A_12_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_12_RISING (MXC_V_PWRSEQ_LPWKPOL0A_12_RISING << MXC_F_PWRSEQ_LPWKPOL0A_12_POS) /**< LPWKPOL0A_12_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0A_12_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0A_12_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_12_FALLING (MXC_V_PWRSEQ_LPWKPOL0A_12_FALLING << MXC_F_PWRSEQ_LPWKPOL0A_12_POS) /**< LPWKPOL0A_12_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL0A_13_POS 26 /**< LPWKPOL0A_13 Position */ +#define MXC_F_PWRSEQ_LPWKPOL0A_13 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0A_13_POS)) /**< LPWKPOL0A_13 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL0A_13_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0A_13_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_13_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0A_13_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0A_13_POS) /**< LPWKPOL0A_13_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0A_13_RISING ((uint32_t)0x1UL) /**< LPWKPOL0A_13_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_13_RISING (MXC_V_PWRSEQ_LPWKPOL0A_13_RISING << MXC_F_PWRSEQ_LPWKPOL0A_13_POS) /**< LPWKPOL0A_13_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0A_13_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0A_13_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_13_FALLING (MXC_V_PWRSEQ_LPWKPOL0A_13_FALLING << MXC_F_PWRSEQ_LPWKPOL0A_13_POS) /**< LPWKPOL0A_13_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL0A_14_POS 28 /**< LPWKPOL0A_14 Position */ +#define MXC_F_PWRSEQ_LPWKPOL0A_14 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0A_14_POS)) /**< LPWKPOL0A_14 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL0A_14_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0A_14_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_14_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0A_14_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0A_14_POS) /**< LPWKPOL0A_14_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0A_14_RISING ((uint32_t)0x1UL) /**< LPWKPOL0A_14_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_14_RISING (MXC_V_PWRSEQ_LPWKPOL0A_14_RISING << MXC_F_PWRSEQ_LPWKPOL0A_14_POS) /**< LPWKPOL0A_14_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0A_14_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0A_14_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_14_FALLING (MXC_V_PWRSEQ_LPWKPOL0A_14_FALLING << MXC_F_PWRSEQ_LPWKPOL0A_14_POS) /**< LPWKPOL0A_14_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL0A_15_POS 30 /**< LPWKPOL0A_15 Position */ +#define MXC_F_PWRSEQ_LPWKPOL0A_15 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0A_15_POS)) /**< LPWKPOL0A_15 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL0A_15_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0A_15_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_15_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0A_15_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0A_15_POS) /**< LPWKPOL0A_15_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0A_15_RISING ((uint32_t)0x1UL) /**< LPWKPOL0A_15_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_15_RISING (MXC_V_PWRSEQ_LPWKPOL0A_15_RISING << MXC_F_PWRSEQ_LPWKPOL0A_15_POS) /**< LPWKPOL0A_15_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0A_15_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0A_15_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0A_15_FALLING (MXC_V_PWRSEQ_LPWKPOL0A_15_FALLING << MXC_F_PWRSEQ_LPWKPOL0A_15_POS) /**< LPWKPOL0A_15_FALLING Setting */ + +/**@} end of group PWRSEQ_LPWKPOL0A_Register */ + +/** + * @ingroup pwrseq_registers + * @defgroup PWRSEQ_LPWKPOL0B PWRSEQ_LPWKPOL0B + * @brief Low Power Wakeup Polarity Select for GPIO0. + * @{ + */ +#define MXC_F_PWRSEQ_LPWKPOL0B_16_POS 0 /**< LPWKPOL0B_16 Position */ +#define MXC_F_PWRSEQ_LPWKPOL0B_16 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0B_16_POS)) /**< LPWKPOL0B_16 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL0B_16_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0B_16_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_16_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0B_16_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0B_16_POS) /**< LPWKPOL0B_16_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0B_16_RISING ((uint32_t)0x1UL) /**< LPWKPOL0B_16_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_16_RISING (MXC_V_PWRSEQ_LPWKPOL0B_16_RISING << MXC_F_PWRSEQ_LPWKPOL0B_16_POS) /**< LPWKPOL0B_16_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0B_16_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0B_16_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_16_FALLING (MXC_V_PWRSEQ_LPWKPOL0B_16_FALLING << MXC_F_PWRSEQ_LPWKPOL0B_16_POS) /**< LPWKPOL0B_16_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL0B_17_POS 2 /**< LPWKPOL0B_17 Position */ +#define MXC_F_PWRSEQ_LPWKPOL0B_17 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0B_17_POS)) /**< LPWKPOL0B_17 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL0B_17_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0B_17_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_17_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0B_17_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0B_17_POS) /**< LPWKPOL0B_17_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0B_17_RISING ((uint32_t)0x1UL) /**< LPWKPOL0B_17_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_17_RISING (MXC_V_PWRSEQ_LPWKPOL0B_17_RISING << MXC_F_PWRSEQ_LPWKPOL0B_17_POS) /**< LPWKPOL0B_17_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0B_17_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0B_17_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_17_FALLING (MXC_V_PWRSEQ_LPWKPOL0B_17_FALLING << MXC_F_PWRSEQ_LPWKPOL0B_17_POS) /**< LPWKPOL0B_17_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL0B_18_POS 4 /**< LPWKPOL0B_18 Position */ +#define MXC_F_PWRSEQ_LPWKPOL0B_18 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0B_18_POS)) /**< LPWKPOL0B_18 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL0B_18_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0B_18_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_18_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0B_18_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0B_18_POS) /**< LPWKPOL0B_18_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0B_18_RISING ((uint32_t)0x1UL) /**< LPWKPOL0B_18_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_18_RISING (MXC_V_PWRSEQ_LPWKPOL0B_18_RISING << MXC_F_PWRSEQ_LPWKPOL0B_18_POS) /**< LPWKPOL0B_18_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0B_18_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0B_18_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_18_FALLING (MXC_V_PWRSEQ_LPWKPOL0B_18_FALLING << MXC_F_PWRSEQ_LPWKPOL0B_18_POS) /**< LPWKPOL0B_18_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL0B_19_POS 6 /**< LPWKPOL0B_19 Position */ +#define MXC_F_PWRSEQ_LPWKPOL0B_19 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0B_19_POS)) /**< LPWKPOL0B_19 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL0B_19_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0B_19_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_19_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0B_19_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0B_19_POS) /**< LPWKPOL0B_19_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0B_19_RISING ((uint32_t)0x1UL) /**< LPWKPOL0B_19_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_19_RISING (MXC_V_PWRSEQ_LPWKPOL0B_19_RISING << MXC_F_PWRSEQ_LPWKPOL0B_19_POS) /**< LPWKPOL0B_19_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0B_19_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0B_19_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_19_FALLING (MXC_V_PWRSEQ_LPWKPOL0B_19_FALLING << MXC_F_PWRSEQ_LPWKPOL0B_19_POS) /**< LPWKPOL0B_19_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL0B_20_POS 8 /**< LPWKPOL0B_20 Position */ +#define MXC_F_PWRSEQ_LPWKPOL0B_20 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0B_20_POS)) /**< LPWKPOL0B_20 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL0B_20_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0B_20_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_20_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0B_20_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0B_20_POS) /**< LPWKPOL0B_20_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0B_20_RISING ((uint32_t)0x1UL) /**< LPWKPOL0B_20_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_20_RISING (MXC_V_PWRSEQ_LPWKPOL0B_20_RISING << MXC_F_PWRSEQ_LPWKPOL0B_20_POS) /**< LPWKPOL0B_20_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0B_20_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0B_20_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_20_FALLING (MXC_V_PWRSEQ_LPWKPOL0B_20_FALLING << MXC_F_PWRSEQ_LPWKPOL0B_20_POS) /**< LPWKPOL0B_20_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL0B_21_POS 10 /**< LPWKPOL0B_21 Position */ +#define MXC_F_PWRSEQ_LPWKPOL0B_21 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0B_21_POS)) /**< LPWKPOL0B_21 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL0B_21_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0B_21_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_21_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0B_21_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0B_21_POS) /**< LPWKPOL0B_21_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0B_21_RISING ((uint32_t)0x1UL) /**< LPWKPOL0B_21_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_21_RISING (MXC_V_PWRSEQ_LPWKPOL0B_21_RISING << MXC_F_PWRSEQ_LPWKPOL0B_21_POS) /**< LPWKPOL0B_21_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0B_21_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0B_21_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_21_FALLING (MXC_V_PWRSEQ_LPWKPOL0B_21_FALLING << MXC_F_PWRSEQ_LPWKPOL0B_21_POS) /**< LPWKPOL0B_21_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL0B_22_POS 12 /**< LPWKPOL0B_22 Position */ +#define MXC_F_PWRSEQ_LPWKPOL0B_22 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0B_22_POS)) /**< LPWKPOL0B_22 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL0B_22_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0B_22_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_22_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0B_22_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0B_22_POS) /**< LPWKPOL0B_22_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0B_22_RISING ((uint32_t)0x1UL) /**< LPWKPOL0B_22_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_22_RISING (MXC_V_PWRSEQ_LPWKPOL0B_22_RISING << MXC_F_PWRSEQ_LPWKPOL0B_22_POS) /**< LPWKPOL0B_22_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0B_22_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0B_22_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_22_FALLING (MXC_V_PWRSEQ_LPWKPOL0B_22_FALLING << MXC_F_PWRSEQ_LPWKPOL0B_22_POS) /**< LPWKPOL0B_22_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL0B_23_POS 14 /**< LPWKPOL0B_23 Position */ +#define MXC_F_PWRSEQ_LPWKPOL0B_23 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0B_23_POS)) /**< LPWKPOL0B_23 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL0B_23_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0B_23_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_23_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0B_23_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0B_23_POS) /**< LPWKPOL0B_23_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0B_23_RISING ((uint32_t)0x1UL) /**< LPWKPOL0B_23_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_23_RISING (MXC_V_PWRSEQ_LPWKPOL0B_23_RISING << MXC_F_PWRSEQ_LPWKPOL0B_23_POS) /**< LPWKPOL0B_23_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0B_23_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0B_23_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_23_FALLING (MXC_V_PWRSEQ_LPWKPOL0B_23_FALLING << MXC_F_PWRSEQ_LPWKPOL0B_23_POS) /**< LPWKPOL0B_23_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL0B_24_POS 16 /**< LPWKPOL0B_24 Position */ +#define MXC_F_PWRSEQ_LPWKPOL0B_24 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0B_24_POS)) /**< LPWKPOL0B_24 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL0B_24_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0B_24_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_24_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0B_24_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0B_24_POS) /**< LPWKPOL0B_24_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0B_24_RISING ((uint32_t)0x1UL) /**< LPWKPOL0B_24_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_24_RISING (MXC_V_PWRSEQ_LPWKPOL0B_24_RISING << MXC_F_PWRSEQ_LPWKPOL0B_24_POS) /**< LPWKPOL0B_24_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0B_24_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0B_24_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_24_FALLING (MXC_V_PWRSEQ_LPWKPOL0B_24_FALLING << MXC_F_PWRSEQ_LPWKPOL0B_24_POS) /**< LPWKPOL0B_24_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL0B_25_POS 18 /**< LPWKPOL0B_25 Position */ +#define MXC_F_PWRSEQ_LPWKPOL0B_25 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0B_25_POS)) /**< LPWKPOL0B_25 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL0B_25_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0B_25_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_25_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0B_25_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0B_25_POS) /**< LPWKPOL0B_25_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0B_25_RISING ((uint32_t)0x1UL) /**< LPWKPOL0B_25_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_25_RISING (MXC_V_PWRSEQ_LPWKPOL0B_25_RISING << MXC_F_PWRSEQ_LPWKPOL0B_25_POS) /**< LPWKPOL0B_25_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0B_25_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0B_25_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_25_FALLING (MXC_V_PWRSEQ_LPWKPOL0B_25_FALLING << MXC_F_PWRSEQ_LPWKPOL0B_25_POS) /**< LPWKPOL0B_25_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL0B_26_POS 20 /**< LPWKPOL0B_26 Position */ +#define MXC_F_PWRSEQ_LPWKPOL0B_26 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0B_26_POS)) /**< LPWKPOL0B_26 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL0B_26_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0B_26_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_26_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0B_26_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0B_26_POS) /**< LPWKPOL0B_26_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0B_26_RISING ((uint32_t)0x1UL) /**< LPWKPOL0B_26_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_26_RISING (MXC_V_PWRSEQ_LPWKPOL0B_26_RISING << MXC_F_PWRSEQ_LPWKPOL0B_26_POS) /**< LPWKPOL0B_26_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0B_26_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0B_26_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_26_FALLING (MXC_V_PWRSEQ_LPWKPOL0B_26_FALLING << MXC_F_PWRSEQ_LPWKPOL0B_26_POS) /**< LPWKPOL0B_26_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL0B_27_POS 22 /**< LPWKPOL0B_27 Position */ +#define MXC_F_PWRSEQ_LPWKPOL0B_27 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0B_27_POS)) /**< LPWKPOL0B_27 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL0B_27_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0B_27_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_27_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0B_27_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0B_27_POS) /**< LPWKPOL0B_27_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0B_27_RISING ((uint32_t)0x1UL) /**< LPWKPOL0B_27_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_27_RISING (MXC_V_PWRSEQ_LPWKPOL0B_27_RISING << MXC_F_PWRSEQ_LPWKPOL0B_27_POS) /**< LPWKPOL0B_27_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0B_27_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0B_27_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_27_FALLING (MXC_V_PWRSEQ_LPWKPOL0B_27_FALLING << MXC_F_PWRSEQ_LPWKPOL0B_27_POS) /**< LPWKPOL0B_27_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL0B_28_POS 24 /**< LPWKPOL0B_28 Position */ +#define MXC_F_PWRSEQ_LPWKPOL0B_28 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0B_28_POS)) /**< LPWKPOL0B_28 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL0B_28_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0B_28_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_28_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0B_28_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0B_28_POS) /**< LPWKPOL0B_28_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0B_28_RISING ((uint32_t)0x1UL) /**< LPWKPOL0B_28_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_28_RISING (MXC_V_PWRSEQ_LPWKPOL0B_28_RISING << MXC_F_PWRSEQ_LPWKPOL0B_28_POS) /**< LPWKPOL0B_28_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0B_28_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0B_28_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_28_FALLING (MXC_V_PWRSEQ_LPWKPOL0B_28_FALLING << MXC_F_PWRSEQ_LPWKPOL0B_28_POS) /**< LPWKPOL0B_28_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL0B_29_POS 26 /**< LPWKPOL0B_29 Position */ +#define MXC_F_PWRSEQ_LPWKPOL0B_29 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0B_29_POS)) /**< LPWKPOL0B_29 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL0B_29_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0B_29_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_29_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0B_29_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0B_29_POS) /**< LPWKPOL0B_29_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0B_29_RISING ((uint32_t)0x1UL) /**< LPWKPOL0B_29_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_29_RISING (MXC_V_PWRSEQ_LPWKPOL0B_29_RISING << MXC_F_PWRSEQ_LPWKPOL0B_29_POS) /**< LPWKPOL0B_29_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0B_29_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0B_29_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_29_FALLING (MXC_V_PWRSEQ_LPWKPOL0B_29_FALLING << MXC_F_PWRSEQ_LPWKPOL0B_29_POS) /**< LPWKPOL0B_29_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL0B_30_POS 28 /**< LPWKPOL0B_30 Position */ +#define MXC_F_PWRSEQ_LPWKPOL0B_30 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0B_30_POS)) /**< LPWKPOL0B_30 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL0B_30_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0B_30_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_30_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0B_30_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0B_30_POS) /**< LPWKPOL0B_30_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0B_30_RISING ((uint32_t)0x1UL) /**< LPWKPOL0B_30_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_30_RISING (MXC_V_PWRSEQ_LPWKPOL0B_30_RISING << MXC_F_PWRSEQ_LPWKPOL0B_30_POS) /**< LPWKPOL0B_30_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0B_30_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0B_30_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_30_FALLING (MXC_V_PWRSEQ_LPWKPOL0B_30_FALLING << MXC_F_PWRSEQ_LPWKPOL0B_30_POS) /**< LPWKPOL0B_30_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL0B_31_POS 30 /**< LPWKPOL0B_31 Position */ +#define MXC_F_PWRSEQ_LPWKPOL0B_31 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0B_31_POS)) /**< LPWKPOL0B_31 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL0B_31_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0B_31_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_31_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0B_31_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0B_31_POS) /**< LPWKPOL0B_31_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0B_31_RISING ((uint32_t)0x1UL) /**< LPWKPOL0B_31_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_31_RISING (MXC_V_PWRSEQ_LPWKPOL0B_31_RISING << MXC_F_PWRSEQ_LPWKPOL0B_31_POS) /**< LPWKPOL0B_31_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL0B_31_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0B_31_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL0B_31_FALLING (MXC_V_PWRSEQ_LPWKPOL0B_31_FALLING << MXC_F_PWRSEQ_LPWKPOL0B_31_POS) /**< LPWKPOL0B_31_FALLING Setting */ + +/**@} end of group PWRSEQ_LPWKPOL0B_Register */ + +/** + * @ingroup pwrseq_registers + * @defgroup PWRSEQ_LPWKPOL1A PWRSEQ_LPWKPOL1A + * @brief Low Power Wakeup Polarity Select for GPIO1. + * @{ + */ +#define MXC_F_PWRSEQ_LPWKPOL1A_0_POS 0 /**< LPWKPOL1A_0 Position */ +#define MXC_F_PWRSEQ_LPWKPOL1A_0 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1A_0_POS)) /**< LPWKPOL1A_0 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL1A_0_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1A_0_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_0_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1A_0_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1A_0_POS) /**< LPWKPOL1A_0_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1A_0_RISING ((uint32_t)0x1UL) /**< LPWKPOL1A_0_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_0_RISING (MXC_V_PWRSEQ_LPWKPOL1A_0_RISING << MXC_F_PWRSEQ_LPWKPOL1A_0_POS) /**< LPWKPOL1A_0_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1A_0_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1A_0_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_0_FALLING (MXC_V_PWRSEQ_LPWKPOL1A_0_FALLING << MXC_F_PWRSEQ_LPWKPOL1A_0_POS) /**< LPWKPOL1A_0_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL1A_1_POS 2 /**< LPWKPOL1A_1 Position */ +#define MXC_F_PWRSEQ_LPWKPOL1A_1 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1A_1_POS)) /**< LPWKPOL1A_1 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL1A_1_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1A_1_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_1_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1A_1_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1A_1_POS) /**< LPWKPOL1A_1_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1A_1_RISING ((uint32_t)0x1UL) /**< LPWKPOL1A_1_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_1_RISING (MXC_V_PWRSEQ_LPWKPOL1A_1_RISING << MXC_F_PWRSEQ_LPWKPOL1A_1_POS) /**< LPWKPOL1A_1_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1A_1_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1A_1_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_1_FALLING (MXC_V_PWRSEQ_LPWKPOL1A_1_FALLING << MXC_F_PWRSEQ_LPWKPOL1A_1_POS) /**< LPWKPOL1A_1_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL1A_2_POS 4 /**< LPWKPOL1A_2 Position */ +#define MXC_F_PWRSEQ_LPWKPOL1A_2 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1A_2_POS)) /**< LPWKPOL1A_2 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL1A_2_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1A_2_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_2_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1A_2_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1A_2_POS) /**< LPWKPOL1A_2_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1A_2_RISING ((uint32_t)0x1UL) /**< LPWKPOL1A_2_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_2_RISING (MXC_V_PWRSEQ_LPWKPOL1A_2_RISING << MXC_F_PWRSEQ_LPWKPOL1A_2_POS) /**< LPWKPOL1A_2_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1A_2_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1A_2_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_2_FALLING (MXC_V_PWRSEQ_LPWKPOL1A_2_FALLING << MXC_F_PWRSEQ_LPWKPOL1A_2_POS) /**< LPWKPOL1A_2_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL1A_3_POS 6 /**< LPWKPOL1A_3 Position */ +#define MXC_F_PWRSEQ_LPWKPOL1A_3 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1A_3_POS)) /**< LPWKPOL1A_3 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL1A_3_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1A_3_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_3_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1A_3_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1A_3_POS) /**< LPWKPOL1A_3_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1A_3_RISING ((uint32_t)0x1UL) /**< LPWKPOL1A_3_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_3_RISING (MXC_V_PWRSEQ_LPWKPOL1A_3_RISING << MXC_F_PWRSEQ_LPWKPOL1A_3_POS) /**< LPWKPOL1A_3_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1A_3_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1A_3_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_3_FALLING (MXC_V_PWRSEQ_LPWKPOL1A_3_FALLING << MXC_F_PWRSEQ_LPWKPOL1A_3_POS) /**< LPWKPOL1A_3_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL1A_4_POS 8 /**< LPWKPOL1A_4 Position */ +#define MXC_F_PWRSEQ_LPWKPOL1A_4 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1A_4_POS)) /**< LPWKPOL1A_4 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL1A_4_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1A_4_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_4_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1A_4_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1A_4_POS) /**< LPWKPOL1A_4_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1A_4_RISING ((uint32_t)0x1UL) /**< LPWKPOL1A_4_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_4_RISING (MXC_V_PWRSEQ_LPWKPOL1A_4_RISING << MXC_F_PWRSEQ_LPWKPOL1A_4_POS) /**< LPWKPOL1A_4_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1A_4_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1A_4_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_4_FALLING (MXC_V_PWRSEQ_LPWKPOL1A_4_FALLING << MXC_F_PWRSEQ_LPWKPOL1A_4_POS) /**< LPWKPOL1A_4_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL1A_5_POS 10 /**< LPWKPOL1A_5 Position */ +#define MXC_F_PWRSEQ_LPWKPOL1A_5 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1A_5_POS)) /**< LPWKPOL1A_5 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL1A_5_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1A_5_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_5_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1A_5_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1A_5_POS) /**< LPWKPOL1A_5_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1A_5_RISING ((uint32_t)0x1UL) /**< LPWKPOL1A_5_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_5_RISING (MXC_V_PWRSEQ_LPWKPOL1A_5_RISING << MXC_F_PWRSEQ_LPWKPOL1A_5_POS) /**< LPWKPOL1A_5_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1A_5_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1A_5_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_5_FALLING (MXC_V_PWRSEQ_LPWKPOL1A_5_FALLING << MXC_F_PWRSEQ_LPWKPOL1A_5_POS) /**< LPWKPOL1A_5_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL1A_6_POS 12 /**< LPWKPOL1A_6 Position */ +#define MXC_F_PWRSEQ_LPWKPOL1A_6 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1A_6_POS)) /**< LPWKPOL1A_6 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL1A_6_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1A_6_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_6_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1A_6_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1A_6_POS) /**< LPWKPOL1A_6_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1A_6_RISING ((uint32_t)0x1UL) /**< LPWKPOL1A_6_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_6_RISING (MXC_V_PWRSEQ_LPWKPOL1A_6_RISING << MXC_F_PWRSEQ_LPWKPOL1A_6_POS) /**< LPWKPOL1A_6_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1A_6_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1A_6_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_6_FALLING (MXC_V_PWRSEQ_LPWKPOL1A_6_FALLING << MXC_F_PWRSEQ_LPWKPOL1A_6_POS) /**< LPWKPOL1A_6_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL1A_7_POS 14 /**< LPWKPOL1A_7 Position */ +#define MXC_F_PWRSEQ_LPWKPOL1A_7 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1A_7_POS)) /**< LPWKPOL1A_7 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL1A_7_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1A_7_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_7_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1A_7_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1A_7_POS) /**< LPWKPOL1A_7_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1A_7_RISING ((uint32_t)0x1UL) /**< LPWKPOL1A_7_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_7_RISING (MXC_V_PWRSEQ_LPWKPOL1A_7_RISING << MXC_F_PWRSEQ_LPWKPOL1A_7_POS) /**< LPWKPOL1A_7_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1A_7_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1A_7_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_7_FALLING (MXC_V_PWRSEQ_LPWKPOL1A_7_FALLING << MXC_F_PWRSEQ_LPWKPOL1A_7_POS) /**< LPWKPOL1A_7_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL1A_8_POS 16 /**< LPWKPOL1A_8 Position */ +#define MXC_F_PWRSEQ_LPWKPOL1A_8 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1A_8_POS)) /**< LPWKPOL1A_8 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL1A_8_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1A_8_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_8_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1A_8_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1A_8_POS) /**< LPWKPOL1A_8_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1A_8_RISING ((uint32_t)0x1UL) /**< LPWKPOL1A_8_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_8_RISING (MXC_V_PWRSEQ_LPWKPOL1A_8_RISING << MXC_F_PWRSEQ_LPWKPOL1A_8_POS) /**< LPWKPOL1A_8_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1A_8_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1A_8_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_8_FALLING (MXC_V_PWRSEQ_LPWKPOL1A_8_FALLING << MXC_F_PWRSEQ_LPWKPOL1A_8_POS) /**< LPWKPOL1A_8_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL1A_9_POS 18 /**< LPWKPOL1A_9 Position */ +#define MXC_F_PWRSEQ_LPWKPOL1A_9 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1A_9_POS)) /**< LPWKPOL1A_9 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL1A_9_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1A_9_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_9_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1A_9_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1A_9_POS) /**< LPWKPOL1A_9_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1A_9_RISING ((uint32_t)0x1UL) /**< LPWKPOL1A_9_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_9_RISING (MXC_V_PWRSEQ_LPWKPOL1A_9_RISING << MXC_F_PWRSEQ_LPWKPOL1A_9_POS) /**< LPWKPOL1A_9_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1A_9_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1A_9_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_9_FALLING (MXC_V_PWRSEQ_LPWKPOL1A_9_FALLING << MXC_F_PWRSEQ_LPWKPOL1A_9_POS) /**< LPWKPOL1A_9_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL1A_10_POS 20 /**< LPWKPOL1A_10 Position */ +#define MXC_F_PWRSEQ_LPWKPOL1A_10 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1A_10_POS)) /**< LPWKPOL1A_10 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL1A_10_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1A_10_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_10_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1A_10_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1A_10_POS) /**< LPWKPOL1A_10_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1A_10_RISING ((uint32_t)0x1UL) /**< LPWKPOL1A_10_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_10_RISING (MXC_V_PWRSEQ_LPWKPOL1A_10_RISING << MXC_F_PWRSEQ_LPWKPOL1A_10_POS) /**< LPWKPOL1A_10_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1A_10_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1A_10_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_10_FALLING (MXC_V_PWRSEQ_LPWKPOL1A_10_FALLING << MXC_F_PWRSEQ_LPWKPOL1A_10_POS) /**< LPWKPOL1A_10_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL1A_11_POS 22 /**< LPWKPOL1A_11 Position */ +#define MXC_F_PWRSEQ_LPWKPOL1A_11 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1A_11_POS)) /**< LPWKPOL1A_11 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL1A_11_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1A_11_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_11_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1A_11_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1A_11_POS) /**< LPWKPOL1A_11_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1A_11_RISING ((uint32_t)0x1UL) /**< LPWKPOL1A_11_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_11_RISING (MXC_V_PWRSEQ_LPWKPOL1A_11_RISING << MXC_F_PWRSEQ_LPWKPOL1A_11_POS) /**< LPWKPOL1A_11_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1A_11_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1A_11_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_11_FALLING (MXC_V_PWRSEQ_LPWKPOL1A_11_FALLING << MXC_F_PWRSEQ_LPWKPOL1A_11_POS) /**< LPWKPOL1A_11_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL1A_12_POS 24 /**< LPWKPOL1A_12 Position */ +#define MXC_F_PWRSEQ_LPWKPOL1A_12 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1A_12_POS)) /**< LPWKPOL1A_12 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL1A_12_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1A_12_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_12_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1A_12_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1A_12_POS) /**< LPWKPOL1A_12_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1A_12_RISING ((uint32_t)0x1UL) /**< LPWKPOL1A_12_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_12_RISING (MXC_V_PWRSEQ_LPWKPOL1A_12_RISING << MXC_F_PWRSEQ_LPWKPOL1A_12_POS) /**< LPWKPOL1A_12_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1A_12_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1A_12_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_12_FALLING (MXC_V_PWRSEQ_LPWKPOL1A_12_FALLING << MXC_F_PWRSEQ_LPWKPOL1A_12_POS) /**< LPWKPOL1A_12_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL1A_13_POS 26 /**< LPWKPOL1A_13 Position */ +#define MXC_F_PWRSEQ_LPWKPOL1A_13 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1A_13_POS)) /**< LPWKPOL1A_13 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL1A_13_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1A_13_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_13_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1A_13_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1A_13_POS) /**< LPWKPOL1A_13_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1A_13_RISING ((uint32_t)0x1UL) /**< LPWKPOL1A_13_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_13_RISING (MXC_V_PWRSEQ_LPWKPOL1A_13_RISING << MXC_F_PWRSEQ_LPWKPOL1A_13_POS) /**< LPWKPOL1A_13_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1A_13_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1A_13_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_13_FALLING (MXC_V_PWRSEQ_LPWKPOL1A_13_FALLING << MXC_F_PWRSEQ_LPWKPOL1A_13_POS) /**< LPWKPOL1A_13_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL1A_14_POS 28 /**< LPWKPOL1A_14 Position */ +#define MXC_F_PWRSEQ_LPWKPOL1A_14 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1A_14_POS)) /**< LPWKPOL1A_14 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL1A_14_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1A_14_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_14_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1A_14_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1A_14_POS) /**< LPWKPOL1A_14_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1A_14_RISING ((uint32_t)0x1UL) /**< LPWKPOL1A_14_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_14_RISING (MXC_V_PWRSEQ_LPWKPOL1A_14_RISING << MXC_F_PWRSEQ_LPWKPOL1A_14_POS) /**< LPWKPOL1A_14_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1A_14_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1A_14_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_14_FALLING (MXC_V_PWRSEQ_LPWKPOL1A_14_FALLING << MXC_F_PWRSEQ_LPWKPOL1A_14_POS) /**< LPWKPOL1A_14_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL1A_15_POS 30 /**< LPWKPOL1A_15 Position */ +#define MXC_F_PWRSEQ_LPWKPOL1A_15 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1A_15_POS)) /**< LPWKPOL1A_15 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL1A_15_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1A_15_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_15_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1A_15_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1A_15_POS) /**< LPWKPOL1A_15_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1A_15_RISING ((uint32_t)0x1UL) /**< LPWKPOL1A_15_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_15_RISING (MXC_V_PWRSEQ_LPWKPOL1A_15_RISING << MXC_F_PWRSEQ_LPWKPOL1A_15_POS) /**< LPWKPOL1A_15_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1A_15_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1A_15_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1A_15_FALLING (MXC_V_PWRSEQ_LPWKPOL1A_15_FALLING << MXC_F_PWRSEQ_LPWKPOL1A_15_POS) /**< LPWKPOL1A_15_FALLING Setting */ + +/**@} end of group PWRSEQ_LPWKPOL1A_Register */ + +/** + * @ingroup pwrseq_registers + * @defgroup PWRSEQ_LPWKPOL1B PWRSEQ_LPWKPOL1B + * @brief Low Power Wakeup Polarity Select for GPIO1. + * @{ + */ +#define MXC_F_PWRSEQ_LPWKPOL1B_16_POS 0 /**< LPWKPOL1B_16 Position */ +#define MXC_F_PWRSEQ_LPWKPOL1B_16 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1B_16_POS)) /**< LPWKPOL1B_16 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL1B_16_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1B_16_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_16_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1B_16_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1B_16_POS) /**< LPWKPOL1B_16_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1B_16_RISING ((uint32_t)0x1UL) /**< LPWKPOL1B_16_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_16_RISING (MXC_V_PWRSEQ_LPWKPOL1B_16_RISING << MXC_F_PWRSEQ_LPWKPOL1B_16_POS) /**< LPWKPOL1B_16_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1B_16_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1B_16_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_16_FALLING (MXC_V_PWRSEQ_LPWKPOL1B_16_FALLING << MXC_F_PWRSEQ_LPWKPOL1B_16_POS) /**< LPWKPOL1B_16_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL1B_17_POS 2 /**< LPWKPOL1B_17 Position */ +#define MXC_F_PWRSEQ_LPWKPOL1B_17 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1B_17_POS)) /**< LPWKPOL1B_17 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL1B_17_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1B_17_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_17_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1B_17_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1B_17_POS) /**< LPWKPOL1B_17_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1B_17_RISING ((uint32_t)0x1UL) /**< LPWKPOL1B_17_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_17_RISING (MXC_V_PWRSEQ_LPWKPOL1B_17_RISING << MXC_F_PWRSEQ_LPWKPOL1B_17_POS) /**< LPWKPOL1B_17_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1B_17_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1B_17_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_17_FALLING (MXC_V_PWRSEQ_LPWKPOL1B_17_FALLING << MXC_F_PWRSEQ_LPWKPOL1B_17_POS) /**< LPWKPOL1B_17_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL1B_18_POS 4 /**< LPWKPOL1B_18 Position */ +#define MXC_F_PWRSEQ_LPWKPOL1B_18 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1B_18_POS)) /**< LPWKPOL1B_18 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL1B_18_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1B_18_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_18_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1B_18_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1B_18_POS) /**< LPWKPOL1B_18_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1B_18_RISING ((uint32_t)0x1UL) /**< LPWKPOL1B_18_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_18_RISING (MXC_V_PWRSEQ_LPWKPOL1B_18_RISING << MXC_F_PWRSEQ_LPWKPOL1B_18_POS) /**< LPWKPOL1B_18_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1B_18_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1B_18_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_18_FALLING (MXC_V_PWRSEQ_LPWKPOL1B_18_FALLING << MXC_F_PWRSEQ_LPWKPOL1B_18_POS) /**< LPWKPOL1B_18_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL1B_19_POS 6 /**< LPWKPOL1B_19 Position */ +#define MXC_F_PWRSEQ_LPWKPOL1B_19 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1B_19_POS)) /**< LPWKPOL1B_19 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL1B_19_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1B_19_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_19_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1B_19_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1B_19_POS) /**< LPWKPOL1B_19_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1B_19_RISING ((uint32_t)0x1UL) /**< LPWKPOL1B_19_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_19_RISING (MXC_V_PWRSEQ_LPWKPOL1B_19_RISING << MXC_F_PWRSEQ_LPWKPOL1B_19_POS) /**< LPWKPOL1B_19_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1B_19_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1B_19_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_19_FALLING (MXC_V_PWRSEQ_LPWKPOL1B_19_FALLING << MXC_F_PWRSEQ_LPWKPOL1B_19_POS) /**< LPWKPOL1B_19_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL1B_20_POS 8 /**< LPWKPOL1B_20 Position */ +#define MXC_F_PWRSEQ_LPWKPOL1B_20 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1B_20_POS)) /**< LPWKPOL1B_20 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL1B_20_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1B_20_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_20_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1B_20_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1B_20_POS) /**< LPWKPOL1B_20_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1B_20_RISING ((uint32_t)0x1UL) /**< LPWKPOL1B_20_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_20_RISING (MXC_V_PWRSEQ_LPWKPOL1B_20_RISING << MXC_F_PWRSEQ_LPWKPOL1B_20_POS) /**< LPWKPOL1B_20_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1B_20_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1B_20_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_20_FALLING (MXC_V_PWRSEQ_LPWKPOL1B_20_FALLING << MXC_F_PWRSEQ_LPWKPOL1B_20_POS) /**< LPWKPOL1B_20_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL1B_21_POS 10 /**< LPWKPOL1B_21 Position */ +#define MXC_F_PWRSEQ_LPWKPOL1B_21 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1B_21_POS)) /**< LPWKPOL1B_21 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL1B_21_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1B_21_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_21_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1B_21_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1B_21_POS) /**< LPWKPOL1B_21_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1B_21_RISING ((uint32_t)0x1UL) /**< LPWKPOL1B_21_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_21_RISING (MXC_V_PWRSEQ_LPWKPOL1B_21_RISING << MXC_F_PWRSEQ_LPWKPOL1B_21_POS) /**< LPWKPOL1B_21_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1B_21_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1B_21_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_21_FALLING (MXC_V_PWRSEQ_LPWKPOL1B_21_FALLING << MXC_F_PWRSEQ_LPWKPOL1B_21_POS) /**< LPWKPOL1B_21_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL1B_22_POS 12 /**< LPWKPOL1B_22 Position */ +#define MXC_F_PWRSEQ_LPWKPOL1B_22 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1B_22_POS)) /**< LPWKPOL1B_22 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL1B_22_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1B_22_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_22_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1B_22_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1B_22_POS) /**< LPWKPOL1B_22_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1B_22_RISING ((uint32_t)0x1UL) /**< LPWKPOL1B_22_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_22_RISING (MXC_V_PWRSEQ_LPWKPOL1B_22_RISING << MXC_F_PWRSEQ_LPWKPOL1B_22_POS) /**< LPWKPOL1B_22_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1B_22_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1B_22_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_22_FALLING (MXC_V_PWRSEQ_LPWKPOL1B_22_FALLING << MXC_F_PWRSEQ_LPWKPOL1B_22_POS) /**< LPWKPOL1B_22_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL1B_23_POS 14 /**< LPWKPOL1B_23 Position */ +#define MXC_F_PWRSEQ_LPWKPOL1B_23 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1B_23_POS)) /**< LPWKPOL1B_23 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL1B_23_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1B_23_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_23_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1B_23_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1B_23_POS) /**< LPWKPOL1B_23_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1B_23_RISING ((uint32_t)0x1UL) /**< LPWKPOL1B_23_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_23_RISING (MXC_V_PWRSEQ_LPWKPOL1B_23_RISING << MXC_F_PWRSEQ_LPWKPOL1B_23_POS) /**< LPWKPOL1B_23_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1B_23_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1B_23_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_23_FALLING (MXC_V_PWRSEQ_LPWKPOL1B_23_FALLING << MXC_F_PWRSEQ_LPWKPOL1B_23_POS) /**< LPWKPOL1B_23_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL1B_24_POS 16 /**< LPWKPOL1B_24 Position */ +#define MXC_F_PWRSEQ_LPWKPOL1B_24 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1B_24_POS)) /**< LPWKPOL1B_24 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL1B_24_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1B_24_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_24_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1B_24_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1B_24_POS) /**< LPWKPOL1B_24_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1B_24_RISING ((uint32_t)0x1UL) /**< LPWKPOL1B_24_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_24_RISING (MXC_V_PWRSEQ_LPWKPOL1B_24_RISING << MXC_F_PWRSEQ_LPWKPOL1B_24_POS) /**< LPWKPOL1B_24_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1B_24_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1B_24_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_24_FALLING (MXC_V_PWRSEQ_LPWKPOL1B_24_FALLING << MXC_F_PWRSEQ_LPWKPOL1B_24_POS) /**< LPWKPOL1B_24_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL1B_25_POS 18 /**< LPWKPOL1B_25 Position */ +#define MXC_F_PWRSEQ_LPWKPOL1B_25 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1B_25_POS)) /**< LPWKPOL1B_25 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL1B_25_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1B_25_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_25_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1B_25_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1B_25_POS) /**< LPWKPOL1B_25_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1B_25_RISING ((uint32_t)0x1UL) /**< LPWKPOL1B_25_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_25_RISING (MXC_V_PWRSEQ_LPWKPOL1B_25_RISING << MXC_F_PWRSEQ_LPWKPOL1B_25_POS) /**< LPWKPOL1B_25_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1B_25_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1B_25_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_25_FALLING (MXC_V_PWRSEQ_LPWKPOL1B_25_FALLING << MXC_F_PWRSEQ_LPWKPOL1B_25_POS) /**< LPWKPOL1B_25_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL1B_26_POS 20 /**< LPWKPOL1B_26 Position */ +#define MXC_F_PWRSEQ_LPWKPOL1B_26 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1B_26_POS)) /**< LPWKPOL1B_26 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL1B_26_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1B_26_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_26_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1B_26_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1B_26_POS) /**< LPWKPOL1B_26_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1B_26_RISING ((uint32_t)0x1UL) /**< LPWKPOL1B_26_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_26_RISING (MXC_V_PWRSEQ_LPWKPOL1B_26_RISING << MXC_F_PWRSEQ_LPWKPOL1B_26_POS) /**< LPWKPOL1B_26_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1B_26_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1B_26_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_26_FALLING (MXC_V_PWRSEQ_LPWKPOL1B_26_FALLING << MXC_F_PWRSEQ_LPWKPOL1B_26_POS) /**< LPWKPOL1B_26_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL1B_27_POS 22 /**< LPWKPOL1B_27 Position */ +#define MXC_F_PWRSEQ_LPWKPOL1B_27 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1B_27_POS)) /**< LPWKPOL1B_27 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL1B_27_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1B_27_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_27_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1B_27_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1B_27_POS) /**< LPWKPOL1B_27_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1B_27_RISING ((uint32_t)0x1UL) /**< LPWKPOL1B_27_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_27_RISING (MXC_V_PWRSEQ_LPWKPOL1B_27_RISING << MXC_F_PWRSEQ_LPWKPOL1B_27_POS) /**< LPWKPOL1B_27_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1B_27_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1B_27_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_27_FALLING (MXC_V_PWRSEQ_LPWKPOL1B_27_FALLING << MXC_F_PWRSEQ_LPWKPOL1B_27_POS) /**< LPWKPOL1B_27_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL1B_28_POS 24 /**< LPWKPOL1B_28 Position */ +#define MXC_F_PWRSEQ_LPWKPOL1B_28 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1B_28_POS)) /**< LPWKPOL1B_28 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL1B_28_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1B_28_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_28_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1B_28_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1B_28_POS) /**< LPWKPOL1B_28_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1B_28_RISING ((uint32_t)0x1UL) /**< LPWKPOL1B_28_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_28_RISING (MXC_V_PWRSEQ_LPWKPOL1B_28_RISING << MXC_F_PWRSEQ_LPWKPOL1B_28_POS) /**< LPWKPOL1B_28_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1B_28_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1B_28_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_28_FALLING (MXC_V_PWRSEQ_LPWKPOL1B_28_FALLING << MXC_F_PWRSEQ_LPWKPOL1B_28_POS) /**< LPWKPOL1B_28_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL1B_29_POS 26 /**< LPWKPOL1B_29 Position */ +#define MXC_F_PWRSEQ_LPWKPOL1B_29 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1B_29_POS)) /**< LPWKPOL1B_29 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL1B_29_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1B_29_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_29_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1B_29_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1B_29_POS) /**< LPWKPOL1B_29_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1B_29_RISING ((uint32_t)0x1UL) /**< LPWKPOL1B_29_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_29_RISING (MXC_V_PWRSEQ_LPWKPOL1B_29_RISING << MXC_F_PWRSEQ_LPWKPOL1B_29_POS) /**< LPWKPOL1B_29_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1B_29_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1B_29_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_29_FALLING (MXC_V_PWRSEQ_LPWKPOL1B_29_FALLING << MXC_F_PWRSEQ_LPWKPOL1B_29_POS) /**< LPWKPOL1B_29_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL1B_30_POS 28 /**< LPWKPOL1B_30 Position */ +#define MXC_F_PWRSEQ_LPWKPOL1B_30 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1B_30_POS)) /**< LPWKPOL1B_30 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL1B_30_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1B_30_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_30_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1B_30_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1B_30_POS) /**< LPWKPOL1B_30_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1B_30_RISING ((uint32_t)0x1UL) /**< LPWKPOL1B_30_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_30_RISING (MXC_V_PWRSEQ_LPWKPOL1B_30_RISING << MXC_F_PWRSEQ_LPWKPOL1B_30_POS) /**< LPWKPOL1B_30_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1B_30_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1B_30_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_30_FALLING (MXC_V_PWRSEQ_LPWKPOL1B_30_FALLING << MXC_F_PWRSEQ_LPWKPOL1B_30_POS) /**< LPWKPOL1B_30_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL1B_31_POS 30 /**< LPWKPOL1B_31 Position */ +#define MXC_F_PWRSEQ_LPWKPOL1B_31 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1B_31_POS)) /**< LPWKPOL1B_31 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL1B_31_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1B_31_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_31_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1B_31_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1B_31_POS) /**< LPWKPOL1B_31_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1B_31_RISING ((uint32_t)0x1UL) /**< LPWKPOL1B_31_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_31_RISING (MXC_V_PWRSEQ_LPWKPOL1B_31_RISING << MXC_F_PWRSEQ_LPWKPOL1B_31_POS) /**< LPWKPOL1B_31_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL1B_31_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1B_31_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL1B_31_FALLING (MXC_V_PWRSEQ_LPWKPOL1B_31_FALLING << MXC_F_PWRSEQ_LPWKPOL1B_31_POS) /**< LPWKPOL1B_31_FALLING Setting */ + +/**@} end of group PWRSEQ_LPWKPOL1B_Register */ + +/** + * @ingroup pwrseq_registers + * @defgroup PWRSEQ_LPWKPOL2A PWRSEQ_LPWKPOL2A + * @brief Low Power Wakeup Polarity Select for GPIO2. + * @{ + */ +#define MXC_F_PWRSEQ_LPWKPOL2A_0_POS 0 /**< LPWKPOL2A_0 Position */ +#define MXC_F_PWRSEQ_LPWKPOL2A_0 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2A_0_POS)) /**< LPWKPOL2A_0 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL2A_0_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2A_0_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_0_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2A_0_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2A_0_POS) /**< LPWKPOL2A_0_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2A_0_RISING ((uint32_t)0x1UL) /**< LPWKPOL2A_0_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_0_RISING (MXC_V_PWRSEQ_LPWKPOL2A_0_RISING << MXC_F_PWRSEQ_LPWKPOL2A_0_POS) /**< LPWKPOL2A_0_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2A_0_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2A_0_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_0_FALLING (MXC_V_PWRSEQ_LPWKPOL2A_0_FALLING << MXC_F_PWRSEQ_LPWKPOL2A_0_POS) /**< LPWKPOL2A_0_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL2A_1_POS 2 /**< LPWKPOL2A_1 Position */ +#define MXC_F_PWRSEQ_LPWKPOL2A_1 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2A_1_POS)) /**< LPWKPOL2A_1 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL2A_1_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2A_1_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_1_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2A_1_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2A_1_POS) /**< LPWKPOL2A_1_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2A_1_RISING ((uint32_t)0x1UL) /**< LPWKPOL2A_1_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_1_RISING (MXC_V_PWRSEQ_LPWKPOL2A_1_RISING << MXC_F_PWRSEQ_LPWKPOL2A_1_POS) /**< LPWKPOL2A_1_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2A_1_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2A_1_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_1_FALLING (MXC_V_PWRSEQ_LPWKPOL2A_1_FALLING << MXC_F_PWRSEQ_LPWKPOL2A_1_POS) /**< LPWKPOL2A_1_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL2A_2_POS 4 /**< LPWKPOL2A_2 Position */ +#define MXC_F_PWRSEQ_LPWKPOL2A_2 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2A_2_POS)) /**< LPWKPOL2A_2 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL2A_2_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2A_2_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_2_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2A_2_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2A_2_POS) /**< LPWKPOL2A_2_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2A_2_RISING ((uint32_t)0x1UL) /**< LPWKPOL2A_2_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_2_RISING (MXC_V_PWRSEQ_LPWKPOL2A_2_RISING << MXC_F_PWRSEQ_LPWKPOL2A_2_POS) /**< LPWKPOL2A_2_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2A_2_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2A_2_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_2_FALLING (MXC_V_PWRSEQ_LPWKPOL2A_2_FALLING << MXC_F_PWRSEQ_LPWKPOL2A_2_POS) /**< LPWKPOL2A_2_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL2A_3_POS 6 /**< LPWKPOL2A_3 Position */ +#define MXC_F_PWRSEQ_LPWKPOL2A_3 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2A_3_POS)) /**< LPWKPOL2A_3 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL2A_3_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2A_3_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_3_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2A_3_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2A_3_POS) /**< LPWKPOL2A_3_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2A_3_RISING ((uint32_t)0x1UL) /**< LPWKPOL2A_3_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_3_RISING (MXC_V_PWRSEQ_LPWKPOL2A_3_RISING << MXC_F_PWRSEQ_LPWKPOL2A_3_POS) /**< LPWKPOL2A_3_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2A_3_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2A_3_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_3_FALLING (MXC_V_PWRSEQ_LPWKPOL2A_3_FALLING << MXC_F_PWRSEQ_LPWKPOL2A_3_POS) /**< LPWKPOL2A_3_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL2A_4_POS 8 /**< LPWKPOL2A_4 Position */ +#define MXC_F_PWRSEQ_LPWKPOL2A_4 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2A_4_POS)) /**< LPWKPOL2A_4 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL2A_4_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2A_4_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_4_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2A_4_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2A_4_POS) /**< LPWKPOL2A_4_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2A_4_RISING ((uint32_t)0x1UL) /**< LPWKPOL2A_4_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_4_RISING (MXC_V_PWRSEQ_LPWKPOL2A_4_RISING << MXC_F_PWRSEQ_LPWKPOL2A_4_POS) /**< LPWKPOL2A_4_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2A_4_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2A_4_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_4_FALLING (MXC_V_PWRSEQ_LPWKPOL2A_4_FALLING << MXC_F_PWRSEQ_LPWKPOL2A_4_POS) /**< LPWKPOL2A_4_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL2A_5_POS 10 /**< LPWKPOL2A_5 Position */ +#define MXC_F_PWRSEQ_LPWKPOL2A_5 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2A_5_POS)) /**< LPWKPOL2A_5 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL2A_5_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2A_5_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_5_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2A_5_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2A_5_POS) /**< LPWKPOL2A_5_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2A_5_RISING ((uint32_t)0x1UL) /**< LPWKPOL2A_5_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_5_RISING (MXC_V_PWRSEQ_LPWKPOL2A_5_RISING << MXC_F_PWRSEQ_LPWKPOL2A_5_POS) /**< LPWKPOL2A_5_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2A_5_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2A_5_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_5_FALLING (MXC_V_PWRSEQ_LPWKPOL2A_5_FALLING << MXC_F_PWRSEQ_LPWKPOL2A_5_POS) /**< LPWKPOL2A_5_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL2A_6_POS 12 /**< LPWKPOL2A_6 Position */ +#define MXC_F_PWRSEQ_LPWKPOL2A_6 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2A_6_POS)) /**< LPWKPOL2A_6 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL2A_6_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2A_6_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_6_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2A_6_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2A_6_POS) /**< LPWKPOL2A_6_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2A_6_RISING ((uint32_t)0x1UL) /**< LPWKPOL2A_6_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_6_RISING (MXC_V_PWRSEQ_LPWKPOL2A_6_RISING << MXC_F_PWRSEQ_LPWKPOL2A_6_POS) /**< LPWKPOL2A_6_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2A_6_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2A_6_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_6_FALLING (MXC_V_PWRSEQ_LPWKPOL2A_6_FALLING << MXC_F_PWRSEQ_LPWKPOL2A_6_POS) /**< LPWKPOL2A_6_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL2A_7_POS 14 /**< LPWKPOL2A_7 Position */ +#define MXC_F_PWRSEQ_LPWKPOL2A_7 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2A_7_POS)) /**< LPWKPOL2A_7 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL2A_7_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2A_7_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_7_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2A_7_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2A_7_POS) /**< LPWKPOL2A_7_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2A_7_RISING ((uint32_t)0x1UL) /**< LPWKPOL2A_7_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_7_RISING (MXC_V_PWRSEQ_LPWKPOL2A_7_RISING << MXC_F_PWRSEQ_LPWKPOL2A_7_POS) /**< LPWKPOL2A_7_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2A_7_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2A_7_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_7_FALLING (MXC_V_PWRSEQ_LPWKPOL2A_7_FALLING << MXC_F_PWRSEQ_LPWKPOL2A_7_POS) /**< LPWKPOL2A_7_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL2A_8_POS 16 /**< LPWKPOL2A_8 Position */ +#define MXC_F_PWRSEQ_LPWKPOL2A_8 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2A_8_POS)) /**< LPWKPOL2A_8 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL2A_8_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2A_8_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_8_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2A_8_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2A_8_POS) /**< LPWKPOL2A_8_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2A_8_RISING ((uint32_t)0x1UL) /**< LPWKPOL2A_8_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_8_RISING (MXC_V_PWRSEQ_LPWKPOL2A_8_RISING << MXC_F_PWRSEQ_LPWKPOL2A_8_POS) /**< LPWKPOL2A_8_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2A_8_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2A_8_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_8_FALLING (MXC_V_PWRSEQ_LPWKPOL2A_8_FALLING << MXC_F_PWRSEQ_LPWKPOL2A_8_POS) /**< LPWKPOL2A_8_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL2A_9_POS 18 /**< LPWKPOL2A_9 Position */ +#define MXC_F_PWRSEQ_LPWKPOL2A_9 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2A_9_POS)) /**< LPWKPOL2A_9 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL2A_9_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2A_9_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_9_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2A_9_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2A_9_POS) /**< LPWKPOL2A_9_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2A_9_RISING ((uint32_t)0x1UL) /**< LPWKPOL2A_9_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_9_RISING (MXC_V_PWRSEQ_LPWKPOL2A_9_RISING << MXC_F_PWRSEQ_LPWKPOL2A_9_POS) /**< LPWKPOL2A_9_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2A_9_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2A_9_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_9_FALLING (MXC_V_PWRSEQ_LPWKPOL2A_9_FALLING << MXC_F_PWRSEQ_LPWKPOL2A_9_POS) /**< LPWKPOL2A_9_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL2A_10_POS 20 /**< LPWKPOL2A_10 Position */ +#define MXC_F_PWRSEQ_LPWKPOL2A_10 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2A_10_POS)) /**< LPWKPOL2A_10 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL2A_10_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2A_10_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_10_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2A_10_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2A_10_POS) /**< LPWKPOL2A_10_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2A_10_RISING ((uint32_t)0x1UL) /**< LPWKPOL2A_10_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_10_RISING (MXC_V_PWRSEQ_LPWKPOL2A_10_RISING << MXC_F_PWRSEQ_LPWKPOL2A_10_POS) /**< LPWKPOL2A_10_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2A_10_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2A_10_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_10_FALLING (MXC_V_PWRSEQ_LPWKPOL2A_10_FALLING << MXC_F_PWRSEQ_LPWKPOL2A_10_POS) /**< LPWKPOL2A_10_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL2A_11_POS 22 /**< LPWKPOL2A_11 Position */ +#define MXC_F_PWRSEQ_LPWKPOL2A_11 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2A_11_POS)) /**< LPWKPOL2A_11 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL2A_11_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2A_11_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_11_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2A_11_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2A_11_POS) /**< LPWKPOL2A_11_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2A_11_RISING ((uint32_t)0x1UL) /**< LPWKPOL2A_11_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_11_RISING (MXC_V_PWRSEQ_LPWKPOL2A_11_RISING << MXC_F_PWRSEQ_LPWKPOL2A_11_POS) /**< LPWKPOL2A_11_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2A_11_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2A_11_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_11_FALLING (MXC_V_PWRSEQ_LPWKPOL2A_11_FALLING << MXC_F_PWRSEQ_LPWKPOL2A_11_POS) /**< LPWKPOL2A_11_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL2A_12_POS 24 /**< LPWKPOL2A_12 Position */ +#define MXC_F_PWRSEQ_LPWKPOL2A_12 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2A_12_POS)) /**< LPWKPOL2A_12 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL2A_12_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2A_12_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_12_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2A_12_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2A_12_POS) /**< LPWKPOL2A_12_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2A_12_RISING ((uint32_t)0x1UL) /**< LPWKPOL2A_12_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_12_RISING (MXC_V_PWRSEQ_LPWKPOL2A_12_RISING << MXC_F_PWRSEQ_LPWKPOL2A_12_POS) /**< LPWKPOL2A_12_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2A_12_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2A_12_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_12_FALLING (MXC_V_PWRSEQ_LPWKPOL2A_12_FALLING << MXC_F_PWRSEQ_LPWKPOL2A_12_POS) /**< LPWKPOL2A_12_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL2A_13_POS 26 /**< LPWKPOL2A_13 Position */ +#define MXC_F_PWRSEQ_LPWKPOL2A_13 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2A_13_POS)) /**< LPWKPOL2A_13 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL2A_13_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2A_13_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_13_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2A_13_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2A_13_POS) /**< LPWKPOL2A_13_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2A_13_RISING ((uint32_t)0x1UL) /**< LPWKPOL2A_13_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_13_RISING (MXC_V_PWRSEQ_LPWKPOL2A_13_RISING << MXC_F_PWRSEQ_LPWKPOL2A_13_POS) /**< LPWKPOL2A_13_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2A_13_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2A_13_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_13_FALLING (MXC_V_PWRSEQ_LPWKPOL2A_13_FALLING << MXC_F_PWRSEQ_LPWKPOL2A_13_POS) /**< LPWKPOL2A_13_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL2A_14_POS 28 /**< LPWKPOL2A_14 Position */ +#define MXC_F_PWRSEQ_LPWKPOL2A_14 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2A_14_POS)) /**< LPWKPOL2A_14 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL2A_14_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2A_14_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_14_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2A_14_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2A_14_POS) /**< LPWKPOL2A_14_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2A_14_RISING ((uint32_t)0x1UL) /**< LPWKPOL2A_14_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_14_RISING (MXC_V_PWRSEQ_LPWKPOL2A_14_RISING << MXC_F_PWRSEQ_LPWKPOL2A_14_POS) /**< LPWKPOL2A_14_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2A_14_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2A_14_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_14_FALLING (MXC_V_PWRSEQ_LPWKPOL2A_14_FALLING << MXC_F_PWRSEQ_LPWKPOL2A_14_POS) /**< LPWKPOL2A_14_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL2A_15_POS 30 /**< LPWKPOL2A_15 Position */ +#define MXC_F_PWRSEQ_LPWKPOL2A_15 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2A_15_POS)) /**< LPWKPOL2A_15 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL2A_15_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2A_15_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_15_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2A_15_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2A_15_POS) /**< LPWKPOL2A_15_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2A_15_RISING ((uint32_t)0x1UL) /**< LPWKPOL2A_15_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_15_RISING (MXC_V_PWRSEQ_LPWKPOL2A_15_RISING << MXC_F_PWRSEQ_LPWKPOL2A_15_POS) /**< LPWKPOL2A_15_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2A_15_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2A_15_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2A_15_FALLING (MXC_V_PWRSEQ_LPWKPOL2A_15_FALLING << MXC_F_PWRSEQ_LPWKPOL2A_15_POS) /**< LPWKPOL2A_15_FALLING Setting */ + +/**@} end of group PWRSEQ_LPWKPOL2A_Register */ + +/** + * @ingroup pwrseq_registers + * @defgroup PWRSEQ_LPWKPOL2B PWRSEQ_LPWKPOL2B + * @brief Low Power Wakeup Polarity Select for GPIO2. + * @{ + */ +#define MXC_F_PWRSEQ_LPWKPOL2B_16_POS 0 /**< LPWKPOL2B_16 Position */ +#define MXC_F_PWRSEQ_LPWKPOL2B_16 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2B_16_POS)) /**< LPWKPOL2B_16 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL2B_16_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2B_16_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_16_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2B_16_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2B_16_POS) /**< LPWKPOL2B_16_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2B_16_RISING ((uint32_t)0x1UL) /**< LPWKPOL2B_16_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_16_RISING (MXC_V_PWRSEQ_LPWKPOL2B_16_RISING << MXC_F_PWRSEQ_LPWKPOL2B_16_POS) /**< LPWKPOL2B_16_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2B_16_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2B_16_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_16_FALLING (MXC_V_PWRSEQ_LPWKPOL2B_16_FALLING << MXC_F_PWRSEQ_LPWKPOL2B_16_POS) /**< LPWKPOL2B_16_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL2B_17_POS 2 /**< LPWKPOL2B_17 Position */ +#define MXC_F_PWRSEQ_LPWKPOL2B_17 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2B_17_POS)) /**< LPWKPOL2B_17 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL2B_17_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2B_17_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_17_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2B_17_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2B_17_POS) /**< LPWKPOL2B_17_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2B_17_RISING ((uint32_t)0x1UL) /**< LPWKPOL2B_17_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_17_RISING (MXC_V_PWRSEQ_LPWKPOL2B_17_RISING << MXC_F_PWRSEQ_LPWKPOL2B_17_POS) /**< LPWKPOL2B_17_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2B_17_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2B_17_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_17_FALLING (MXC_V_PWRSEQ_LPWKPOL2B_17_FALLING << MXC_F_PWRSEQ_LPWKPOL2B_17_POS) /**< LPWKPOL2B_17_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL2B_18_POS 4 /**< LPWKPOL2B_18 Position */ +#define MXC_F_PWRSEQ_LPWKPOL2B_18 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2B_18_POS)) /**< LPWKPOL2B_18 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL2B_18_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2B_18_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_18_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2B_18_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2B_18_POS) /**< LPWKPOL2B_18_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2B_18_RISING ((uint32_t)0x1UL) /**< LPWKPOL2B_18_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_18_RISING (MXC_V_PWRSEQ_LPWKPOL2B_18_RISING << MXC_F_PWRSEQ_LPWKPOL2B_18_POS) /**< LPWKPOL2B_18_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2B_18_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2B_18_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_18_FALLING (MXC_V_PWRSEQ_LPWKPOL2B_18_FALLING << MXC_F_PWRSEQ_LPWKPOL2B_18_POS) /**< LPWKPOL2B_18_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL2B_19_POS 6 /**< LPWKPOL2B_19 Position */ +#define MXC_F_PWRSEQ_LPWKPOL2B_19 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2B_19_POS)) /**< LPWKPOL2B_19 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL2B_19_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2B_19_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_19_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2B_19_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2B_19_POS) /**< LPWKPOL2B_19_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2B_19_RISING ((uint32_t)0x1UL) /**< LPWKPOL2B_19_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_19_RISING (MXC_V_PWRSEQ_LPWKPOL2B_19_RISING << MXC_F_PWRSEQ_LPWKPOL2B_19_POS) /**< LPWKPOL2B_19_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2B_19_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2B_19_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_19_FALLING (MXC_V_PWRSEQ_LPWKPOL2B_19_FALLING << MXC_F_PWRSEQ_LPWKPOL2B_19_POS) /**< LPWKPOL2B_19_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL2B_20_POS 8 /**< LPWKPOL2B_20 Position */ +#define MXC_F_PWRSEQ_LPWKPOL2B_20 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2B_20_POS)) /**< LPWKPOL2B_20 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL2B_20_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2B_20_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_20_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2B_20_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2B_20_POS) /**< LPWKPOL2B_20_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2B_20_RISING ((uint32_t)0x1UL) /**< LPWKPOL2B_20_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_20_RISING (MXC_V_PWRSEQ_LPWKPOL2B_20_RISING << MXC_F_PWRSEQ_LPWKPOL2B_20_POS) /**< LPWKPOL2B_20_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2B_20_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2B_20_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_20_FALLING (MXC_V_PWRSEQ_LPWKPOL2B_20_FALLING << MXC_F_PWRSEQ_LPWKPOL2B_20_POS) /**< LPWKPOL2B_20_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL2B_21_POS 10 /**< LPWKPOL2B_21 Position */ +#define MXC_F_PWRSEQ_LPWKPOL2B_21 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2B_21_POS)) /**< LPWKPOL2B_21 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL2B_21_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2B_21_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_21_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2B_21_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2B_21_POS) /**< LPWKPOL2B_21_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2B_21_RISING ((uint32_t)0x1UL) /**< LPWKPOL2B_21_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_21_RISING (MXC_V_PWRSEQ_LPWKPOL2B_21_RISING << MXC_F_PWRSEQ_LPWKPOL2B_21_POS) /**< LPWKPOL2B_21_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2B_21_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2B_21_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_21_FALLING (MXC_V_PWRSEQ_LPWKPOL2B_21_FALLING << MXC_F_PWRSEQ_LPWKPOL2B_21_POS) /**< LPWKPOL2B_21_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL2B_22_POS 12 /**< LPWKPOL2B_22 Position */ +#define MXC_F_PWRSEQ_LPWKPOL2B_22 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2B_22_POS)) /**< LPWKPOL2B_22 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL2B_22_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2B_22_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_22_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2B_22_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2B_22_POS) /**< LPWKPOL2B_22_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2B_22_RISING ((uint32_t)0x1UL) /**< LPWKPOL2B_22_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_22_RISING (MXC_V_PWRSEQ_LPWKPOL2B_22_RISING << MXC_F_PWRSEQ_LPWKPOL2B_22_POS) /**< LPWKPOL2B_22_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2B_22_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2B_22_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_22_FALLING (MXC_V_PWRSEQ_LPWKPOL2B_22_FALLING << MXC_F_PWRSEQ_LPWKPOL2B_22_POS) /**< LPWKPOL2B_22_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL2B_23_POS 14 /**< LPWKPOL2B_23 Position */ +#define MXC_F_PWRSEQ_LPWKPOL2B_23 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2B_23_POS)) /**< LPWKPOL2B_23 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL2B_23_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2B_23_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_23_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2B_23_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2B_23_POS) /**< LPWKPOL2B_23_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2B_23_RISING ((uint32_t)0x1UL) /**< LPWKPOL2B_23_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_23_RISING (MXC_V_PWRSEQ_LPWKPOL2B_23_RISING << MXC_F_PWRSEQ_LPWKPOL2B_23_POS) /**< LPWKPOL2B_23_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2B_23_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2B_23_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_23_FALLING (MXC_V_PWRSEQ_LPWKPOL2B_23_FALLING << MXC_F_PWRSEQ_LPWKPOL2B_23_POS) /**< LPWKPOL2B_23_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL2B_24_POS 16 /**< LPWKPOL2B_24 Position */ +#define MXC_F_PWRSEQ_LPWKPOL2B_24 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2B_24_POS)) /**< LPWKPOL2B_24 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL2B_24_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2B_24_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_24_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2B_24_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2B_24_POS) /**< LPWKPOL2B_24_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2B_24_RISING ((uint32_t)0x1UL) /**< LPWKPOL2B_24_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_24_RISING (MXC_V_PWRSEQ_LPWKPOL2B_24_RISING << MXC_F_PWRSEQ_LPWKPOL2B_24_POS) /**< LPWKPOL2B_24_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2B_24_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2B_24_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_24_FALLING (MXC_V_PWRSEQ_LPWKPOL2B_24_FALLING << MXC_F_PWRSEQ_LPWKPOL2B_24_POS) /**< LPWKPOL2B_24_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL2B_25_POS 18 /**< LPWKPOL2B_25 Position */ +#define MXC_F_PWRSEQ_LPWKPOL2B_25 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2B_25_POS)) /**< LPWKPOL2B_25 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL2B_25_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2B_25_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_25_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2B_25_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2B_25_POS) /**< LPWKPOL2B_25_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2B_25_RISING ((uint32_t)0x1UL) /**< LPWKPOL2B_25_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_25_RISING (MXC_V_PWRSEQ_LPWKPOL2B_25_RISING << MXC_F_PWRSEQ_LPWKPOL2B_25_POS) /**< LPWKPOL2B_25_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2B_25_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2B_25_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_25_FALLING (MXC_V_PWRSEQ_LPWKPOL2B_25_FALLING << MXC_F_PWRSEQ_LPWKPOL2B_25_POS) /**< LPWKPOL2B_25_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL2B_26_POS 20 /**< LPWKPOL2B_26 Position */ +#define MXC_F_PWRSEQ_LPWKPOL2B_26 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2B_26_POS)) /**< LPWKPOL2B_26 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL2B_26_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2B_26_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_26_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2B_26_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2B_26_POS) /**< LPWKPOL2B_26_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2B_26_RISING ((uint32_t)0x1UL) /**< LPWKPOL2B_26_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_26_RISING (MXC_V_PWRSEQ_LPWKPOL2B_26_RISING << MXC_F_PWRSEQ_LPWKPOL2B_26_POS) /**< LPWKPOL2B_26_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2B_26_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2B_26_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_26_FALLING (MXC_V_PWRSEQ_LPWKPOL2B_26_FALLING << MXC_F_PWRSEQ_LPWKPOL2B_26_POS) /**< LPWKPOL2B_26_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL2B_27_POS 22 /**< LPWKPOL2B_27 Position */ +#define MXC_F_PWRSEQ_LPWKPOL2B_27 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2B_27_POS)) /**< LPWKPOL2B_27 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL2B_27_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2B_27_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_27_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2B_27_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2B_27_POS) /**< LPWKPOL2B_27_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2B_27_RISING ((uint32_t)0x1UL) /**< LPWKPOL2B_27_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_27_RISING (MXC_V_PWRSEQ_LPWKPOL2B_27_RISING << MXC_F_PWRSEQ_LPWKPOL2B_27_POS) /**< LPWKPOL2B_27_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2B_27_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2B_27_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_27_FALLING (MXC_V_PWRSEQ_LPWKPOL2B_27_FALLING << MXC_F_PWRSEQ_LPWKPOL2B_27_POS) /**< LPWKPOL2B_27_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL2B_28_POS 24 /**< LPWKPOL2B_28 Position */ +#define MXC_F_PWRSEQ_LPWKPOL2B_28 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2B_28_POS)) /**< LPWKPOL2B_28 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL2B_28_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2B_28_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_28_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2B_28_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2B_28_POS) /**< LPWKPOL2B_28_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2B_28_RISING ((uint32_t)0x1UL) /**< LPWKPOL2B_28_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_28_RISING (MXC_V_PWRSEQ_LPWKPOL2B_28_RISING << MXC_F_PWRSEQ_LPWKPOL2B_28_POS) /**< LPWKPOL2B_28_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2B_28_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2B_28_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_28_FALLING (MXC_V_PWRSEQ_LPWKPOL2B_28_FALLING << MXC_F_PWRSEQ_LPWKPOL2B_28_POS) /**< LPWKPOL2B_28_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL2B_29_POS 26 /**< LPWKPOL2B_29 Position */ +#define MXC_F_PWRSEQ_LPWKPOL2B_29 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2B_29_POS)) /**< LPWKPOL2B_29 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL2B_29_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2B_29_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_29_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2B_29_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2B_29_POS) /**< LPWKPOL2B_29_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2B_29_RISING ((uint32_t)0x1UL) /**< LPWKPOL2B_29_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_29_RISING (MXC_V_PWRSEQ_LPWKPOL2B_29_RISING << MXC_F_PWRSEQ_LPWKPOL2B_29_POS) /**< LPWKPOL2B_29_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2B_29_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2B_29_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_29_FALLING (MXC_V_PWRSEQ_LPWKPOL2B_29_FALLING << MXC_F_PWRSEQ_LPWKPOL2B_29_POS) /**< LPWKPOL2B_29_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL2B_30_POS 28 /**< LPWKPOL2B_30 Position */ +#define MXC_F_PWRSEQ_LPWKPOL2B_30 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2B_30_POS)) /**< LPWKPOL2B_30 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL2B_30_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2B_30_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_30_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2B_30_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2B_30_POS) /**< LPWKPOL2B_30_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2B_30_RISING ((uint32_t)0x1UL) /**< LPWKPOL2B_30_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_30_RISING (MXC_V_PWRSEQ_LPWKPOL2B_30_RISING << MXC_F_PWRSEQ_LPWKPOL2B_30_POS) /**< LPWKPOL2B_30_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2B_30_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2B_30_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_30_FALLING (MXC_V_PWRSEQ_LPWKPOL2B_30_FALLING << MXC_F_PWRSEQ_LPWKPOL2B_30_POS) /**< LPWKPOL2B_30_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL2B_31_POS 30 /**< LPWKPOL2B_31 Position */ +#define MXC_F_PWRSEQ_LPWKPOL2B_31 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2B_31_POS)) /**< LPWKPOL2B_31 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL2B_31_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2B_31_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_31_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2B_31_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2B_31_POS) /**< LPWKPOL2B_31_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2B_31_RISING ((uint32_t)0x1UL) /**< LPWKPOL2B_31_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_31_RISING (MXC_V_PWRSEQ_LPWKPOL2B_31_RISING << MXC_F_PWRSEQ_LPWKPOL2B_31_POS) /**< LPWKPOL2B_31_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL2B_31_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2B_31_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL2B_31_FALLING (MXC_V_PWRSEQ_LPWKPOL2B_31_FALLING << MXC_F_PWRSEQ_LPWKPOL2B_31_POS) /**< LPWKPOL2B_31_FALLING Setting */ + +/**@} end of group PWRSEQ_LPWKPOL2B_Register */ + +/** + * @ingroup pwrseq_registers + * @defgroup PWRSEQ_LPWKPOL3 PWRSEQ_LPWKPOL3 + * @brief Low Power Wakeup Polarity Select for GPIO3. + * @{ + */ +#define MXC_F_PWRSEQ_LPWKPOL3_0_POS 0 /**< LPWKPOL3_0 Position */ +#define MXC_F_PWRSEQ_LPWKPOL3_0 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL3_0_POS)) /**< LPWKPOL3_0 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL3_0_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL3_0_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL3_0_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL3_0_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL3_0_POS) /**< LPWKPOL3_0_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL3_0_RISING ((uint32_t)0x1UL) /**< LPWKPOL3_0_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL3_0_RISING (MXC_V_PWRSEQ_LPWKPOL3_0_RISING << MXC_F_PWRSEQ_LPWKPOL3_0_POS) /**< LPWKPOL3_0_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL3_0_FALLING ((uint32_t)0x2UL) /**< LPWKPOL3_0_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL3_0_FALLING (MXC_V_PWRSEQ_LPWKPOL3_0_FALLING << MXC_F_PWRSEQ_LPWKPOL3_0_POS) /**< LPWKPOL3_0_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL3_1_POS 2 /**< LPWKPOL3_1 Position */ +#define MXC_F_PWRSEQ_LPWKPOL3_1 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL3_1_POS)) /**< LPWKPOL3_1 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL3_1_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL3_1_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL3_1_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL3_1_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL3_1_POS) /**< LPWKPOL3_1_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL3_1_RISING ((uint32_t)0x1UL) /**< LPWKPOL3_1_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL3_1_RISING (MXC_V_PWRSEQ_LPWKPOL3_1_RISING << MXC_F_PWRSEQ_LPWKPOL3_1_POS) /**< LPWKPOL3_1_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL3_1_FALLING ((uint32_t)0x2UL) /**< LPWKPOL3_1_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL3_1_FALLING (MXC_V_PWRSEQ_LPWKPOL3_1_FALLING << MXC_F_PWRSEQ_LPWKPOL3_1_POS) /**< LPWKPOL3_1_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL3_2_POS 4 /**< LPWKPOL3_2 Position */ +#define MXC_F_PWRSEQ_LPWKPOL3_2 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL3_2_POS)) /**< LPWKPOL3_2 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL3_2_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL3_2_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL3_2_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL3_2_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL3_2_POS) /**< LPWKPOL3_2_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL3_2_RISING ((uint32_t)0x1UL) /**< LPWKPOL3_2_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL3_2_RISING (MXC_V_PWRSEQ_LPWKPOL3_2_RISING << MXC_F_PWRSEQ_LPWKPOL3_2_POS) /**< LPWKPOL3_2_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL3_2_FALLING ((uint32_t)0x2UL) /**< LPWKPOL3_2_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL3_2_FALLING (MXC_V_PWRSEQ_LPWKPOL3_2_FALLING << MXC_F_PWRSEQ_LPWKPOL3_2_POS) /**< LPWKPOL3_2_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL3_3_POS 6 /**< LPWKPOL3_3 Position */ +#define MXC_F_PWRSEQ_LPWKPOL3_3 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL3_3_POS)) /**< LPWKPOL3_3 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL3_3_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL3_3_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL3_3_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL3_3_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL3_3_POS) /**< LPWKPOL3_3_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL3_3_RISING ((uint32_t)0x1UL) /**< LPWKPOL3_3_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL3_3_RISING (MXC_V_PWRSEQ_LPWKPOL3_3_RISING << MXC_F_PWRSEQ_LPWKPOL3_3_POS) /**< LPWKPOL3_3_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL3_3_FALLING ((uint32_t)0x2UL) /**< LPWKPOL3_3_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL3_3_FALLING (MXC_V_PWRSEQ_LPWKPOL3_3_FALLING << MXC_F_PWRSEQ_LPWKPOL3_3_POS) /**< LPWKPOL3_3_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL3_4_POS 8 /**< LPWKPOL3_4 Position */ +#define MXC_F_PWRSEQ_LPWKPOL3_4 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL3_4_POS)) /**< LPWKPOL3_4 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL3_4_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL3_4_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL3_4_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL3_4_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL3_4_POS) /**< LPWKPOL3_4_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL3_4_RISING ((uint32_t)0x1UL) /**< LPWKPOL3_4_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL3_4_RISING (MXC_V_PWRSEQ_LPWKPOL3_4_RISING << MXC_F_PWRSEQ_LPWKPOL3_4_POS) /**< LPWKPOL3_4_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL3_4_FALLING ((uint32_t)0x2UL) /**< LPWKPOL3_4_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL3_4_FALLING (MXC_V_PWRSEQ_LPWKPOL3_4_FALLING << MXC_F_PWRSEQ_LPWKPOL3_4_POS) /**< LPWKPOL3_4_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL3_5_POS 10 /**< LPWKPOL3_5 Position */ +#define MXC_F_PWRSEQ_LPWKPOL3_5 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL3_5_POS)) /**< LPWKPOL3_5 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL3_5_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL3_5_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL3_5_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL3_5_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL3_5_POS) /**< LPWKPOL3_5_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL3_5_RISING ((uint32_t)0x1UL) /**< LPWKPOL3_5_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL3_5_RISING (MXC_V_PWRSEQ_LPWKPOL3_5_RISING << MXC_F_PWRSEQ_LPWKPOL3_5_POS) /**< LPWKPOL3_5_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL3_5_FALLING ((uint32_t)0x2UL) /**< LPWKPOL3_5_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL3_5_FALLING (MXC_V_PWRSEQ_LPWKPOL3_5_FALLING << MXC_F_PWRSEQ_LPWKPOL3_5_POS) /**< LPWKPOL3_5_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL3_6_POS 12 /**< LPWKPOL3_6 Position */ +#define MXC_F_PWRSEQ_LPWKPOL3_6 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL3_6_POS)) /**< LPWKPOL3_6 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL3_6_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL3_6_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL3_6_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL3_6_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL3_6_POS) /**< LPWKPOL3_6_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL3_6_RISING ((uint32_t)0x1UL) /**< LPWKPOL3_6_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL3_6_RISING (MXC_V_PWRSEQ_LPWKPOL3_6_RISING << MXC_F_PWRSEQ_LPWKPOL3_6_POS) /**< LPWKPOL3_6_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL3_6_FALLING ((uint32_t)0x2UL) /**< LPWKPOL3_6_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL3_6_FALLING (MXC_V_PWRSEQ_LPWKPOL3_6_FALLING << MXC_F_PWRSEQ_LPWKPOL3_6_POS) /**< LPWKPOL3_6_FALLING Setting */ + +#define MXC_F_PWRSEQ_LPWKPOL3_7_POS 14 /**< LPWKPOL3_7 Position */ +#define MXC_F_PWRSEQ_LPWKPOL3_7 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL3_7_POS)) /**< LPWKPOL3_7 Mask */ +#define MXC_V_PWRSEQ_LPWKPOL3_7_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL3_7_BOTH_EDGES Value */ +#define MXC_S_PWRSEQ_LPWKPOL3_7_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL3_7_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL3_7_POS) /**< LPWKPOL3_7_BOTH_EDGES Setting */ +#define MXC_V_PWRSEQ_LPWKPOL3_7_RISING ((uint32_t)0x1UL) /**< LPWKPOL3_7_RISING Value */ +#define MXC_S_PWRSEQ_LPWKPOL3_7_RISING (MXC_V_PWRSEQ_LPWKPOL3_7_RISING << MXC_F_PWRSEQ_LPWKPOL3_7_POS) /**< LPWKPOL3_7_RISING Setting */ +#define MXC_V_PWRSEQ_LPWKPOL3_7_FALLING ((uint32_t)0x2UL) /**< LPWKPOL3_7_FALLING Value */ +#define MXC_S_PWRSEQ_LPWKPOL3_7_FALLING (MXC_V_PWRSEQ_LPWKPOL3_7_FALLING << MXC_F_PWRSEQ_LPWKPOL3_7_POS) /**< LPWKPOL3_7_FALLING Setting */ + +/**@} end of group PWRSEQ_LPWKPOL3_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_PWRSEQ_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/rtc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/rtc_regs.h new file mode 100644 index 00000000000..ea62c7fcf93 --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/rtc_regs.h @@ -0,0 +1,242 @@ +/** + * @file rtc_regs.h + * @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module. + * @note This file is @generated. + * @ingroup rtc_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_RTC_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_RTC_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup rtc + * @defgroup rtc_registers RTC_Registers + * @brief Registers, Bit Masks and Bit Positions for the RTC Peripheral Module. + * @details Real Time Clock and Alarm. + */ + +/** + * @ingroup rtc_registers + * Structure type to access the RTC Registers. + */ +typedef struct { + __IO uint32_t sec; /**< \b 0x00: RTC SEC Register */ + __IO uint32_t ssec; /**< \b 0x04: RTC SSEC Register */ + __IO uint32_t toda; /**< \b 0x08: RTC TODA Register */ + __IO uint32_t sseca; /**< \b 0x0C: RTC SSECA Register */ + __IO uint32_t ctrl; /**< \b 0x10: RTC CTRL Register */ + __IO uint32_t trim; /**< \b 0x14: RTC TRIM Register */ + __IO uint32_t oscctrl; /**< \b 0x18: RTC OSCCTRL Register */ +} mxc_rtc_regs_t; + +/* Register offsets for module RTC */ +/** + * @ingroup rtc_registers + * @defgroup RTC_Register_Offsets Register Offsets + * @brief RTC Peripheral Register Offsets from the RTC Base Peripheral Address. + * @{ + */ +#define MXC_R_RTC_SEC ((uint32_t)0x00000000UL) /**< Offset from RTC Base Address: 0x0000 */ +#define MXC_R_RTC_SSEC ((uint32_t)0x00000004UL) /**< Offset from RTC Base Address: 0x0004 */ +#define MXC_R_RTC_TODA ((uint32_t)0x00000008UL) /**< Offset from RTC Base Address: 0x0008 */ +#define MXC_R_RTC_SSECA ((uint32_t)0x0000000CUL) /**< Offset from RTC Base Address: 0x000C */ +#define MXC_R_RTC_CTRL ((uint32_t)0x00000010UL) /**< Offset from RTC Base Address: 0x0010 */ +#define MXC_R_RTC_TRIM ((uint32_t)0x00000014UL) /**< Offset from RTC Base Address: 0x0014 */ +#define MXC_R_RTC_OSCCTRL ((uint32_t)0x00000018UL) /**< Offset from RTC Base Address: 0x0018 */ +/**@} end of group rtc_registers */ + +/** + * @ingroup rtc_registers + * @defgroup RTC_SEC RTC_SEC + * @brief RTC Second Counter. This register contains the 32-bit second counter. + * @{ + */ +#define MXC_F_RTC_SEC_SEC_POS 0 /**< SEC_SEC Position */ +#define MXC_F_RTC_SEC_SEC ((uint32_t)(0xFFFFFFFFUL << MXC_F_RTC_SEC_SEC_POS)) /**< SEC_SEC Mask */ + +/**@} end of group RTC_SEC_Register */ + +/** + * @ingroup rtc_registers + * @defgroup RTC_SSEC RTC_SSEC + * @brief RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented + * when this register rolls over from 0xFF to 0x00. + * @{ + */ +#define MXC_F_RTC_SSEC_SSEC_POS 0 /**< SSEC_SSEC Position */ +#define MXC_F_RTC_SSEC_SSEC ((uint32_t)(0xFFFUL << MXC_F_RTC_SSEC_SSEC_POS)) /**< SSEC_SSEC Mask */ + +/**@} end of group RTC_SSEC_Register */ + +/** + * @ingroup rtc_registers + * @defgroup RTC_TODA RTC_TODA + * @brief Time-of-day Alarm. + * @{ + */ +#define MXC_F_RTC_TODA_TOD_ALARM_POS 0 /**< TODA_TOD_ALARM Position */ +#define MXC_F_RTC_TODA_TOD_ALARM ((uint32_t)(0xFFFFFUL << MXC_F_RTC_TODA_TOD_ALARM_POS)) /**< TODA_TOD_ALARM Mask */ + +/**@} end of group RTC_TODA_Register */ + +/** + * @ingroup rtc_registers + * @defgroup RTC_SSECA RTC_SSECA + * @brief RTC sub-second alarm. This register contains the reload value for the sub- + * second alarm. + * @{ + */ +#define MXC_F_RTC_SSECA_SSEC_ALARM_POS 0 /**< SSECA_SSEC_ALARM Position */ +#define MXC_F_RTC_SSECA_SSEC_ALARM ((uint32_t)(0xFFFFFFFFUL << MXC_F_RTC_SSECA_SSEC_ALARM_POS)) /**< SSECA_SSEC_ALARM Mask */ + +/**@} end of group RTC_SSECA_Register */ + +/** + * @ingroup rtc_registers + * @defgroup RTC_CTRL RTC_CTRL + * @brief RTC Control Register. + * @{ + */ +#define MXC_F_RTC_CTRL_EN_POS 0 /**< CTRL_EN Position */ +#define MXC_F_RTC_CTRL_EN ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_EN_POS)) /**< CTRL_EN Mask */ + +#define MXC_F_RTC_CTRL_TOD_ALARM_IE_POS 1 /**< CTRL_TOD_ALARM_IE Position */ +#define MXC_F_RTC_CTRL_TOD_ALARM_IE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_TOD_ALARM_IE_POS)) /**< CTRL_TOD_ALARM_IE Mask */ + +#define MXC_F_RTC_CTRL_SSEC_ALARM_IE_POS 2 /**< CTRL_SSEC_ALARM_IE Position */ +#define MXC_F_RTC_CTRL_SSEC_ALARM_IE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SSEC_ALARM_IE_POS)) /**< CTRL_SSEC_ALARM_IE Mask */ + +#define MXC_F_RTC_CTRL_BUSY_POS 3 /**< CTRL_BUSY Position */ +#define MXC_F_RTC_CTRL_BUSY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_BUSY_POS)) /**< CTRL_BUSY Mask */ + +#define MXC_F_RTC_CTRL_RDY_POS 4 /**< CTRL_RDY Position */ +#define MXC_F_RTC_CTRL_RDY ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDY_POS)) /**< CTRL_RDY Mask */ + +#define MXC_F_RTC_CTRL_RDY_IE_POS 5 /**< CTRL_RDY_IE Position */ +#define MXC_F_RTC_CTRL_RDY_IE ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RDY_IE_POS)) /**< CTRL_RDY_IE Mask */ + +#define MXC_F_RTC_CTRL_TOD_ALARM_IF_POS 6 /**< CTRL_TOD_ALARM_IF Position */ +#define MXC_F_RTC_CTRL_TOD_ALARM_IF ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_TOD_ALARM_IF_POS)) /**< CTRL_TOD_ALARM_IF Mask */ + +#define MXC_F_RTC_CTRL_SSEC_ALARM_IF_POS 7 /**< CTRL_SSEC_ALARM_IF Position */ +#define MXC_F_RTC_CTRL_SSEC_ALARM_IF ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SSEC_ALARM_IF_POS)) /**< CTRL_SSEC_ALARM_IF Mask */ + +#define MXC_F_RTC_CTRL_SQW_EN_POS 8 /**< CTRL_SQW_EN Position */ +#define MXC_F_RTC_CTRL_SQW_EN ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_SQW_EN_POS)) /**< CTRL_SQW_EN Mask */ + +#define MXC_F_RTC_CTRL_SQW_SEL_POS 9 /**< CTRL_SQW_SEL Position */ +#define MXC_F_RTC_CTRL_SQW_SEL ((uint32_t)(0x3UL << MXC_F_RTC_CTRL_SQW_SEL_POS)) /**< CTRL_SQW_SEL Mask */ +#define MXC_V_RTC_CTRL_SQW_SEL_FREQ1HZ ((uint32_t)0x0UL) /**< CTRL_SQW_SEL_FREQ1HZ Value */ +#define MXC_S_RTC_CTRL_SQW_SEL_FREQ1HZ (MXC_V_RTC_CTRL_SQW_SEL_FREQ1HZ << MXC_F_RTC_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_FREQ1HZ Setting */ +#define MXC_V_RTC_CTRL_SQW_SEL_FREQ512HZ ((uint32_t)0x1UL) /**< CTRL_SQW_SEL_FREQ512HZ Value */ +#define MXC_S_RTC_CTRL_SQW_SEL_FREQ512HZ (MXC_V_RTC_CTRL_SQW_SEL_FREQ512HZ << MXC_F_RTC_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_FREQ512HZ Setting */ +#define MXC_V_RTC_CTRL_SQW_SEL_FREQ4KHZ ((uint32_t)0x2UL) /**< CTRL_SQW_SEL_FREQ4KHZ Value */ +#define MXC_S_RTC_CTRL_SQW_SEL_FREQ4KHZ (MXC_V_RTC_CTRL_SQW_SEL_FREQ4KHZ << MXC_F_RTC_CTRL_SQW_SEL_POS) /**< CTRL_SQW_SEL_FREQ4KHZ Setting */ + +#define MXC_F_RTC_CTRL_RD_EN_POS 14 /**< CTRL_RD_EN Position */ +#define MXC_F_RTC_CTRL_RD_EN ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_RD_EN_POS)) /**< CTRL_RD_EN Mask */ + +#define MXC_F_RTC_CTRL_WR_EN_POS 15 /**< CTRL_WR_EN Position */ +#define MXC_F_RTC_CTRL_WR_EN ((uint32_t)(0x1UL << MXC_F_RTC_CTRL_WR_EN_POS)) /**< CTRL_WR_EN Mask */ + +/**@} end of group RTC_CTRL_Register */ + +/** + * @ingroup rtc_registers + * @defgroup RTC_TRIM RTC_TRIM + * @brief RTC Trim Register. + * @{ + */ +#define MXC_F_RTC_TRIM_TRIM_POS 0 /**< TRIM_TRIM Position */ +#define MXC_F_RTC_TRIM_TRIM ((uint32_t)(0xFFUL << MXC_F_RTC_TRIM_TRIM_POS)) /**< TRIM_TRIM Mask */ + +#define MXC_F_RTC_TRIM_VBAT_TMR_POS 8 /**< TRIM_VBAT_TMR Position */ +#define MXC_F_RTC_TRIM_VBAT_TMR ((uint32_t)(0xFFFFFFUL << MXC_F_RTC_TRIM_VBAT_TMR_POS)) /**< TRIM_VBAT_TMR Mask */ + +/**@} end of group RTC_TRIM_Register */ + +/** + * @ingroup rtc_registers + * @defgroup RTC_OSCCTRL RTC_OSCCTRL + * @brief RTC Oscillator Control Register. + * @{ + */ +#define MXC_F_RTC_OSCCTRL_FILTER_EN_POS 0 /**< OSCCTRL_FILTER_EN Position */ +#define MXC_F_RTC_OSCCTRL_FILTER_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_FILTER_EN_POS)) /**< OSCCTRL_FILTER_EN Mask */ + +#define MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS 1 /**< OSCCTRL_IBIAS_SEL Position */ +#define MXC_F_RTC_OSCCTRL_IBIAS_SEL ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_IBIAS_SEL_POS)) /**< OSCCTRL_IBIAS_SEL Mask */ + +#define MXC_F_RTC_OSCCTRL_HYST_EN_POS 2 /**< OSCCTRL_HYST_EN Position */ +#define MXC_F_RTC_OSCCTRL_HYST_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_HYST_EN_POS)) /**< OSCCTRL_HYST_EN Mask */ + +#define MXC_F_RTC_OSCCTRL_IBIAS_EN_POS 3 /**< OSCCTRL_IBIAS_EN Position */ +#define MXC_F_RTC_OSCCTRL_IBIAS_EN ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_IBIAS_EN_POS)) /**< OSCCTRL_IBIAS_EN Mask */ + +#define MXC_F_RTC_OSCCTRL_BYPASS_POS 4 /**< OSCCTRL_BYPASS Position */ +#define MXC_F_RTC_OSCCTRL_BYPASS ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_BYPASS_POS)) /**< OSCCTRL_BYPASS Mask */ + +#define MXC_F_RTC_OSCCTRL_SQW_32K_POS 5 /**< OSCCTRL_SQW_32K Position */ +#define MXC_F_RTC_OSCCTRL_SQW_32K ((uint32_t)(0x1UL << MXC_F_RTC_OSCCTRL_SQW_32K_POS)) /**< OSCCTRL_SQW_32K Mask */ + +/**@} end of group RTC_OSCCTRL_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_RTC_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sema_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sema_regs.h new file mode 100644 index 00000000000..66bc71ba2a6 --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sema_regs.h @@ -0,0 +1,203 @@ +/** + * @file sema_regs.h + * @brief Registers, Bit Masks and Bit Positions for the SEMA Peripheral Module. + * @note This file is @generated. + * @ingroup sema_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_SEMA_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_SEMA_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup sema + * @defgroup sema_registers SEMA_Registers + * @brief Registers, Bit Masks and Bit Positions for the SEMA Peripheral Module. + * @details The Semaphore peripheral allows multiple cores in a system to cooperate when accessing shred resources. + The peripheral contains eight semaphores that can be atomically set and cleared. It is left to the discretion of the software + architect to decide how and when the semaphores are used and how they are allocated. Existing hardware does not have to be + + modified for this type of cooperative sharing, and the use of semaphores is exclusively within the software domain. + */ + +/** + * @ingroup sema_registers + * Structure type to access the SEMA Registers. + */ +typedef struct { + __IO uint32_t semaphores[8]; /**< \b 0x00: SEMA SEMAPHORES Register */ + __R uint32_t rsv_0x20_0x3f[8]; + __IO uint32_t irq0; /**< \b 0x40: SEMA IRQ0 Register */ + __IO uint32_t mail0; /**< \b 0x44: SEMA MAIL0 Register */ + __IO uint32_t irq1; /**< \b 0x48: SEMA IRQ1 Register */ + __IO uint32_t mail1; /**< \b 0x4C: SEMA MAIL1 Register */ + __R uint32_t rsv_0x50_0xff[44]; + __IO uint32_t status; /**< \b 0x100: SEMA STATUS Register */ +} mxc_sema_regs_t; + +/* Register offsets for module SEMA */ +/** + * @ingroup sema_registers + * @defgroup SEMA_Register_Offsets Register Offsets + * @brief SEMA Peripheral Register Offsets from the SEMA Base Peripheral Address. + * @{ + */ +#define MXC_R_SEMA_SEMAPHORES ((uint32_t)0x00000000UL) /**< Offset from SEMA Base Address: 0x0000 */ +#define MXC_R_SEMA_IRQ0 ((uint32_t)0x00000040UL) /**< Offset from SEMA Base Address: 0x0040 */ +#define MXC_R_SEMA_MAIL0 ((uint32_t)0x00000044UL) /**< Offset from SEMA Base Address: 0x0044 */ +#define MXC_R_SEMA_IRQ1 ((uint32_t)0x00000048UL) /**< Offset from SEMA Base Address: 0x0048 */ +#define MXC_R_SEMA_MAIL1 ((uint32_t)0x0000004CUL) /**< Offset from SEMA Base Address: 0x004C */ +#define MXC_R_SEMA_STATUS ((uint32_t)0x00000100UL) /**< Offset from SEMA Base Address: 0x0100 */ +/**@} end of group sema_registers */ + +/** + * @ingroup sema_registers + * @defgroup SEMA_SEMAPHORES SEMA_SEMAPHORES + * @brief Read to test and set, returns prior value. Write 0 to clear semaphore. + * @{ + */ +#define MXC_F_SEMA_SEMAPHORES_SEMA_POS 0 /**< SEMAPHORES_SEMA Position */ +#define MXC_F_SEMA_SEMAPHORES_SEMA ((uint32_t)(0x1UL << MXC_F_SEMA_SEMAPHORES_SEMA_POS)) /**< SEMAPHORES_SEMA Mask */ + +/**@} end of group SEMA_SEMAPHORES_Register */ + +/** + * @ingroup sema_registers + * @defgroup SEMA_IRQ0 SEMA_IRQ0 + * @brief Semaphore IRQ0 register. + * @{ + */ +#define MXC_F_SEMA_IRQ0_EN_POS 0 /**< IRQ0_EN Position */ +#define MXC_F_SEMA_IRQ0_EN ((uint32_t)(0x1UL << MXC_F_SEMA_IRQ0_EN_POS)) /**< IRQ0_EN Mask */ + +#define MXC_F_SEMA_IRQ0_CM4_IRQ_POS 16 /**< IRQ0_CM4_IRQ Position */ +#define MXC_F_SEMA_IRQ0_CM4_IRQ ((uint32_t)(0x1UL << MXC_F_SEMA_IRQ0_CM4_IRQ_POS)) /**< IRQ0_CM4_IRQ Mask */ + +/**@} end of group SEMA_IRQ0_Register */ + +/** + * @ingroup sema_registers + * @defgroup SEMA_MAIL0 SEMA_MAIL0 + * @brief Semaphore Mailbox 0 register. + * @{ + */ +#define MXC_F_SEMA_MAIL0_DATA_POS 0 /**< MAIL0_DATA Position */ +#define MXC_F_SEMA_MAIL0_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SEMA_MAIL0_DATA_POS)) /**< MAIL0_DATA Mask */ + +/**@} end of group SEMA_MAIL0_Register */ + +/** + * @ingroup sema_registers + * @defgroup SEMA_IRQ1 SEMA_IRQ1 + * @brief Semaphore IRQ1 register. + * @{ + */ +#define MXC_F_SEMA_IRQ1_EN_POS 0 /**< IRQ1_EN Position */ +#define MXC_F_SEMA_IRQ1_EN ((uint32_t)(0x1UL << MXC_F_SEMA_IRQ1_EN_POS)) /**< IRQ1_EN Mask */ + +#define MXC_F_SEMA_IRQ1_RV32_IRQ_POS 16 /**< IRQ1_RV32_IRQ Position */ +#define MXC_F_SEMA_IRQ1_RV32_IRQ ((uint32_t)(0x1UL << MXC_F_SEMA_IRQ1_RV32_IRQ_POS)) /**< IRQ1_RV32_IRQ Mask */ + +/**@} end of group SEMA_IRQ1_Register */ + +/** + * @ingroup sema_registers + * @defgroup SEMA_MAIL1 SEMA_MAIL1 + * @brief Semaphore Mailbox 1 register. + * @{ + */ +#define MXC_F_SEMA_MAIL1_DATA_POS 0 /**< MAIL1_DATA Position */ +#define MXC_F_SEMA_MAIL1_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SEMA_MAIL1_DATA_POS)) /**< MAIL1_DATA Mask */ + +/**@} end of group SEMA_MAIL1_Register */ + +/** + * @ingroup sema_registers + * @defgroup SEMA_STATUS SEMA_STATUS + * @brief Semaphore status bits. 0 indicates the semaphore is free, 1 indicates taken. + * @{ + */ +#define MXC_F_SEMA_STATUS_STATUS0_POS 0 /**< STATUS_STATUS0 Position */ +#define MXC_F_SEMA_STATUS_STATUS0 ((uint32_t)(0x1UL << MXC_F_SEMA_STATUS_STATUS0_POS)) /**< STATUS_STATUS0 Mask */ + +#define MXC_F_SEMA_STATUS_STATUS1_POS 1 /**< STATUS_STATUS1 Position */ +#define MXC_F_SEMA_STATUS_STATUS1 ((uint32_t)(0x1UL << MXC_F_SEMA_STATUS_STATUS1_POS)) /**< STATUS_STATUS1 Mask */ + +#define MXC_F_SEMA_STATUS_STATUS2_POS 2 /**< STATUS_STATUS2 Position */ +#define MXC_F_SEMA_STATUS_STATUS2 ((uint32_t)(0x1UL << MXC_F_SEMA_STATUS_STATUS2_POS)) /**< STATUS_STATUS2 Mask */ + +#define MXC_F_SEMA_STATUS_STATUS3_POS 3 /**< STATUS_STATUS3 Position */ +#define MXC_F_SEMA_STATUS_STATUS3 ((uint32_t)(0x1UL << MXC_F_SEMA_STATUS_STATUS3_POS)) /**< STATUS_STATUS3 Mask */ + +#define MXC_F_SEMA_STATUS_STATUS4_POS 4 /**< STATUS_STATUS4 Position */ +#define MXC_F_SEMA_STATUS_STATUS4 ((uint32_t)(0x1UL << MXC_F_SEMA_STATUS_STATUS4_POS)) /**< STATUS_STATUS4 Mask */ + +#define MXC_F_SEMA_STATUS_STATUS5_POS 5 /**< STATUS_STATUS5 Position */ +#define MXC_F_SEMA_STATUS_STATUS5 ((uint32_t)(0x1UL << MXC_F_SEMA_STATUS_STATUS5_POS)) /**< STATUS_STATUS5 Mask */ + +#define MXC_F_SEMA_STATUS_STATUS6_POS 6 /**< STATUS_STATUS6 Position */ +#define MXC_F_SEMA_STATUS_STATUS6 ((uint32_t)(0x1UL << MXC_F_SEMA_STATUS_STATUS6_POS)) /**< STATUS_STATUS6 Mask */ + +#define MXC_F_SEMA_STATUS_STATUS7_POS 7 /**< STATUS_STATUS7 Position */ +#define MXC_F_SEMA_STATUS_STATUS7 ((uint32_t)(0x1UL << MXC_F_SEMA_STATUS_STATUS7_POS)) /**< STATUS_STATUS7 Mask */ + +/**@} end of group SEMA_STATUS_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_SEMA_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/simo_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/simo_regs.h new file mode 100644 index 00000000000..36b8ea3e8bc --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/simo_regs.h @@ -0,0 +1,380 @@ +/** + * @file simo_regs.h + * @brief Registers, Bit Masks and Bit Positions for the SIMO Peripheral Module. + * @note This file is @generated. + * @ingroup simo_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_SIMO_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_SIMO_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup simo + * @defgroup simo_registers SIMO_Registers + * @brief Registers, Bit Masks and Bit Positions for the SIMO Peripheral Module. + * @details Single Inductor Multiple Output Switching Converter + */ + +/** + * @ingroup simo_registers + * Structure type to access the SIMO Registers. + */ +typedef struct { + __R uint32_t rsv_0x0; + __IO uint32_t vrego_a; /**< \b 0x0004: SIMO VREGO_A Register */ + __IO uint32_t vrego_b; /**< \b 0x0008: SIMO VREGO_B Register */ + __IO uint32_t vrego_c; /**< \b 0x000C: SIMO VREGO_C Register */ + __IO uint32_t vrego_d; /**< \b 0x0010: SIMO VREGO_D Register */ + __IO uint32_t ipka; /**< \b 0x0014: SIMO IPKA Register */ + __IO uint32_t ipkb; /**< \b 0x0018: SIMO IPKB Register */ + __IO uint32_t maxton; /**< \b 0x001C: SIMO MAXTON Register */ + __I uint32_t iload_a; /**< \b 0x0020: SIMO ILOAD_A Register */ + __I uint32_t iload_b; /**< \b 0x0024: SIMO ILOAD_B Register */ + __I uint32_t iload_c; /**< \b 0x0028: SIMO ILOAD_C Register */ + __I uint32_t iload_d; /**< \b 0x002C: SIMO ILOAD_D Register */ + __IO uint32_t buck_alert_thr_a; /**< \b 0x0030: SIMO BUCK_ALERT_THR_A Register */ + __IO uint32_t buck_alert_thr_b; /**< \b 0x0034: SIMO BUCK_ALERT_THR_B Register */ + __IO uint32_t buck_alert_thr_c; /**< \b 0x0038: SIMO BUCK_ALERT_THR_C Register */ + __IO uint32_t buck_alert_thr_d; /**< \b 0x003C: SIMO BUCK_ALERT_THR_D Register */ + __I uint32_t buck_out_ready; /**< \b 0x0040: SIMO BUCK_OUT_READY Register */ + __I uint32_t zero_cross_cal_a; /**< \b 0x0044: SIMO ZERO_CROSS_CAL_A Register */ + __I uint32_t zero_cross_cal_b; /**< \b 0x0048: SIMO ZERO_CROSS_CAL_B Register */ + __I uint32_t zero_cross_cal_c; /**< \b 0x004C: SIMO ZERO_CROSS_CAL_C Register */ + __I uint32_t zero_cross_cal_d; /**< \b 0x0050: SIMO ZERO_CROSS_CAL_D Register */ +} mxc_simo_regs_t; + +/* Register offsets for module SIMO */ +/** + * @ingroup simo_registers + * @defgroup SIMO_Register_Offsets Register Offsets + * @brief SIMO Peripheral Register Offsets from the SIMO Base Peripheral Address. + * @{ + */ +#define MXC_R_SIMO_VREGO_A ((uint32_t)0x00000004UL) /**< Offset from SIMO Base Address: 0x0004 */ +#define MXC_R_SIMO_VREGO_B ((uint32_t)0x00000008UL) /**< Offset from SIMO Base Address: 0x0008 */ +#define MXC_R_SIMO_VREGO_C ((uint32_t)0x0000000CUL) /**< Offset from SIMO Base Address: 0x000C */ +#define MXC_R_SIMO_VREGO_D ((uint32_t)0x00000010UL) /**< Offset from SIMO Base Address: 0x0010 */ +#define MXC_R_SIMO_IPKA ((uint32_t)0x00000014UL) /**< Offset from SIMO Base Address: 0x0014 */ +#define MXC_R_SIMO_IPKB ((uint32_t)0x00000018UL) /**< Offset from SIMO Base Address: 0x0018 */ +#define MXC_R_SIMO_MAXTON ((uint32_t)0x0000001CUL) /**< Offset from SIMO Base Address: 0x001C */ +#define MXC_R_SIMO_ILOAD_A ((uint32_t)0x00000020UL) /**< Offset from SIMO Base Address: 0x0020 */ +#define MXC_R_SIMO_ILOAD_B ((uint32_t)0x00000024UL) /**< Offset from SIMO Base Address: 0x0024 */ +#define MXC_R_SIMO_ILOAD_C ((uint32_t)0x00000028UL) /**< Offset from SIMO Base Address: 0x0028 */ +#define MXC_R_SIMO_ILOAD_D ((uint32_t)0x0000002CUL) /**< Offset from SIMO Base Address: 0x002C */ +#define MXC_R_SIMO_BUCK_ALERT_THR_A ((uint32_t)0x00000030UL) /**< Offset from SIMO Base Address: 0x0030 */ +#define MXC_R_SIMO_BUCK_ALERT_THR_B ((uint32_t)0x00000034UL) /**< Offset from SIMO Base Address: 0x0034 */ +#define MXC_R_SIMO_BUCK_ALERT_THR_C ((uint32_t)0x00000038UL) /**< Offset from SIMO Base Address: 0x0038 */ +#define MXC_R_SIMO_BUCK_ALERT_THR_D ((uint32_t)0x0000003CUL) /**< Offset from SIMO Base Address: 0x003C */ +#define MXC_R_SIMO_BUCK_OUT_READY ((uint32_t)0x00000040UL) /**< Offset from SIMO Base Address: 0x0040 */ +#define MXC_R_SIMO_ZERO_CROSS_CAL_A ((uint32_t)0x00000044UL) /**< Offset from SIMO Base Address: 0x0044 */ +#define MXC_R_SIMO_ZERO_CROSS_CAL_B ((uint32_t)0x00000048UL) /**< Offset from SIMO Base Address: 0x0048 */ +#define MXC_R_SIMO_ZERO_CROSS_CAL_C ((uint32_t)0x0000004CUL) /**< Offset from SIMO Base Address: 0x004C */ +#define MXC_R_SIMO_ZERO_CROSS_CAL_D ((uint32_t)0x00000050UL) /**< Offset from SIMO Base Address: 0x0050 */ +/**@} end of group simo_registers */ + +/** + * @ingroup simo_registers + * @defgroup SIMO_VREGO_A SIMO_VREGO_A + * @brief Buck Voltage Regulator A Control Register + * @{ + */ +#define MXC_F_SIMO_VREGO_A_VSETA_POS 0 /**< VREGO_A_VSETA Position */ +#define MXC_F_SIMO_VREGO_A_VSETA ((uint32_t)(0x7FUL << MXC_F_SIMO_VREGO_A_VSETA_POS)) /**< VREGO_A_VSETA Mask */ + +#define MXC_F_SIMO_VREGO_A_RANGEA_POS 7 /**< VREGO_A_RANGEA Position */ +#define MXC_F_SIMO_VREGO_A_RANGEA ((uint32_t)(0x1UL << MXC_F_SIMO_VREGO_A_RANGEA_POS)) /**< VREGO_A_RANGEA Mask */ + +/**@} end of group SIMO_VREGO_A_Register */ + +/** + * @ingroup simo_registers + * @defgroup SIMO_VREGO_B SIMO_VREGO_B + * @brief Buck Voltage Regulator B Control Register + * @{ + */ +#define MXC_F_SIMO_VREGO_B_VSETB_POS 0 /**< VREGO_B_VSETB Position */ +#define MXC_F_SIMO_VREGO_B_VSETB ((uint32_t)(0x7FUL << MXC_F_SIMO_VREGO_B_VSETB_POS)) /**< VREGO_B_VSETB Mask */ + +#define MXC_F_SIMO_VREGO_B_RANGEB_POS 7 /**< VREGO_B_RANGEB Position */ +#define MXC_F_SIMO_VREGO_B_RANGEB ((uint32_t)(0x1UL << MXC_F_SIMO_VREGO_B_RANGEB_POS)) /**< VREGO_B_RANGEB Mask */ + +/**@} end of group SIMO_VREGO_B_Register */ + +/** + * @ingroup simo_registers + * @defgroup SIMO_VREGO_C SIMO_VREGO_C + * @brief Buck Voltage Regulator C Control Register + * @{ + */ +#define MXC_F_SIMO_VREGO_C_VSETC_POS 0 /**< VREGO_C_VSETC Position */ +#define MXC_F_SIMO_VREGO_C_VSETC ((uint32_t)(0x7FUL << MXC_F_SIMO_VREGO_C_VSETC_POS)) /**< VREGO_C_VSETC Mask */ + +#define MXC_F_SIMO_VREGO_C_RANGEC_POS 7 /**< VREGO_C_RANGEC Position */ +#define MXC_F_SIMO_VREGO_C_RANGEC ((uint32_t)(0x1UL << MXC_F_SIMO_VREGO_C_RANGEC_POS)) /**< VREGO_C_RANGEC Mask */ + +/**@} end of group SIMO_VREGO_C_Register */ + +/** + * @ingroup simo_registers + * @defgroup SIMO_VREGO_D SIMO_VREGO_D + * @brief Buck Voltage Regulator D Control Register + * @{ + */ +#define MXC_F_SIMO_VREGO_D_VSETD_POS 0 /**< VREGO_D_VSETD Position */ +#define MXC_F_SIMO_VREGO_D_VSETD ((uint32_t)(0x7FUL << MXC_F_SIMO_VREGO_D_VSETD_POS)) /**< VREGO_D_VSETD Mask */ + +#define MXC_F_SIMO_VREGO_D_RANGED_POS 7 /**< VREGO_D_RANGED Position */ +#define MXC_F_SIMO_VREGO_D_RANGED ((uint32_t)(0x1UL << MXC_F_SIMO_VREGO_D_RANGED_POS)) /**< VREGO_D_RANGED Mask */ + +/**@} end of group SIMO_VREGO_D_Register */ + +/** + * @ingroup simo_registers + * @defgroup SIMO_IPKA SIMO_IPKA + * @brief High Side FET Peak Current VREGO_A/VREGO_B Register + * @{ + */ +#define MXC_F_SIMO_IPKA_IPKSETA_POS 0 /**< IPKA_IPKSETA Position */ +#define MXC_F_SIMO_IPKA_IPKSETA ((uint32_t)(0xFUL << MXC_F_SIMO_IPKA_IPKSETA_POS)) /**< IPKA_IPKSETA Mask */ + +#define MXC_F_SIMO_IPKA_IPKSETB_POS 4 /**< IPKA_IPKSETB Position */ +#define MXC_F_SIMO_IPKA_IPKSETB ((uint32_t)(0xFUL << MXC_F_SIMO_IPKA_IPKSETB_POS)) /**< IPKA_IPKSETB Mask */ + +/**@} end of group SIMO_IPKA_Register */ + +/** + * @ingroup simo_registers + * @defgroup SIMO_IPKB SIMO_IPKB + * @brief High Side FET Peak Current VREGO_C/VREGO_D Register + * @{ + */ +#define MXC_F_SIMO_IPKB_IPKSETC_POS 0 /**< IPKB_IPKSETC Position */ +#define MXC_F_SIMO_IPKB_IPKSETC ((uint32_t)(0xFUL << MXC_F_SIMO_IPKB_IPKSETC_POS)) /**< IPKB_IPKSETC Mask */ + +#define MXC_F_SIMO_IPKB_IPKSETD_POS 4 /**< IPKB_IPKSETD Position */ +#define MXC_F_SIMO_IPKB_IPKSETD ((uint32_t)(0xFUL << MXC_F_SIMO_IPKB_IPKSETD_POS)) /**< IPKB_IPKSETD Mask */ + +/**@} end of group SIMO_IPKB_Register */ + +/** + * @ingroup simo_registers + * @defgroup SIMO_MAXTON SIMO_MAXTON + * @brief Maximum High Side FET Time On Register + * @{ + */ +#define MXC_F_SIMO_MAXTON_TONSET_POS 0 /**< MAXTON_TONSET Position */ +#define MXC_F_SIMO_MAXTON_TONSET ((uint32_t)(0xFUL << MXC_F_SIMO_MAXTON_TONSET_POS)) /**< MAXTON_TONSET Mask */ + +/**@} end of group SIMO_MAXTON_Register */ + +/** + * @ingroup simo_registers + * @defgroup SIMO_ILOAD_A SIMO_ILOAD_A + * @brief Buck Cycle Count VREGO_A Register + * @{ + */ +#define MXC_F_SIMO_ILOAD_A_ILOADA_POS 0 /**< ILOAD_A_ILOADA Position */ +#define MXC_F_SIMO_ILOAD_A_ILOADA ((uint32_t)(0xFFUL << MXC_F_SIMO_ILOAD_A_ILOADA_POS)) /**< ILOAD_A_ILOADA Mask */ + +/**@} end of group SIMO_ILOAD_A_Register */ + +/** + * @ingroup simo_registers + * @defgroup SIMO_ILOAD_B SIMO_ILOAD_B + * @brief Buck Cycle Count VREGO_B Register + * @{ + */ +#define MXC_F_SIMO_ILOAD_B_ILOADB_POS 0 /**< ILOAD_B_ILOADB Position */ +#define MXC_F_SIMO_ILOAD_B_ILOADB ((uint32_t)(0xFFUL << MXC_F_SIMO_ILOAD_B_ILOADB_POS)) /**< ILOAD_B_ILOADB Mask */ + +/**@} end of group SIMO_ILOAD_B_Register */ + +/** + * @ingroup simo_registers + * @defgroup SIMO_ILOAD_C SIMO_ILOAD_C + * @brief Buck Cycle Count VREGO_C Register + * @{ + */ +#define MXC_F_SIMO_ILOAD_C_ILOADC_POS 0 /**< ILOAD_C_ILOADC Position */ +#define MXC_F_SIMO_ILOAD_C_ILOADC ((uint32_t)(0xFFUL << MXC_F_SIMO_ILOAD_C_ILOADC_POS)) /**< ILOAD_C_ILOADC Mask */ + +/**@} end of group SIMO_ILOAD_C_Register */ + +/** + * @ingroup simo_registers + * @defgroup SIMO_ILOAD_D SIMO_ILOAD_D + * @brief Buck Cycle Count VREGO_D Register + * @{ + */ +#define MXC_F_SIMO_ILOAD_D_ILOADD_POS 0 /**< ILOAD_D_ILOADD Position */ +#define MXC_F_SIMO_ILOAD_D_ILOADD ((uint32_t)(0xFFUL << MXC_F_SIMO_ILOAD_D_ILOADD_POS)) /**< ILOAD_D_ILOADD Mask */ + +/**@} end of group SIMO_ILOAD_D_Register */ + +/** + * @ingroup simo_registers + * @defgroup SIMO_BUCK_ALERT_THR_A SIMO_BUCK_ALERT_THR_A + * @brief Buck Cycle Count Alert VERGO_A Register + * @{ + */ +#define MXC_F_SIMO_BUCK_ALERT_THR_A_BUCKTHRA_POS 0 /**< BUCK_ALERT_THR_A_BUCKTHRA Position */ +#define MXC_F_SIMO_BUCK_ALERT_THR_A_BUCKTHRA ((uint32_t)(0xFFUL << MXC_F_SIMO_BUCK_ALERT_THR_A_BUCKTHRA_POS)) /**< BUCK_ALERT_THR_A_BUCKTHRA Mask */ + +/**@} end of group SIMO_BUCK_ALERT_THR_A_Register */ + +/** + * @ingroup simo_registers + * @defgroup SIMO_BUCK_ALERT_THR_B SIMO_BUCK_ALERT_THR_B + * @brief Buck Cycle Count Alert VERGO_B Register + * @{ + */ +#define MXC_F_SIMO_BUCK_ALERT_THR_B_BUCKTHRB_POS 0 /**< BUCK_ALERT_THR_B_BUCKTHRB Position */ +#define MXC_F_SIMO_BUCK_ALERT_THR_B_BUCKTHRB ((uint32_t)(0xFFUL << MXC_F_SIMO_BUCK_ALERT_THR_B_BUCKTHRB_POS)) /**< BUCK_ALERT_THR_B_BUCKTHRB Mask */ + +/**@} end of group SIMO_BUCK_ALERT_THR_B_Register */ + +/** + * @ingroup simo_registers + * @defgroup SIMO_BUCK_ALERT_THR_C SIMO_BUCK_ALERT_THR_C + * @brief Buck Cycle Count Alert VERGO_C Register + * @{ + */ +#define MXC_F_SIMO_BUCK_ALERT_THR_C_BUCKTHRC_POS 0 /**< BUCK_ALERT_THR_C_BUCKTHRC Position */ +#define MXC_F_SIMO_BUCK_ALERT_THR_C_BUCKTHRC ((uint32_t)(0xFFUL << MXC_F_SIMO_BUCK_ALERT_THR_C_BUCKTHRC_POS)) /**< BUCK_ALERT_THR_C_BUCKTHRC Mask */ + +/**@} end of group SIMO_BUCK_ALERT_THR_C_Register */ + +/** + * @ingroup simo_registers + * @defgroup SIMO_BUCK_ALERT_THR_D SIMO_BUCK_ALERT_THR_D + * @brief Buck Cycle Count Alert VERGO_D Register + * @{ + */ +#define MXC_F_SIMO_BUCK_ALERT_THR_D_BUCKTHRD_POS 0 /**< BUCK_ALERT_THR_D_BUCKTHRD Position */ +#define MXC_F_SIMO_BUCK_ALERT_THR_D_BUCKTHRD ((uint32_t)(0xFFUL << MXC_F_SIMO_BUCK_ALERT_THR_D_BUCKTHRD_POS)) /**< BUCK_ALERT_THR_D_BUCKTHRD Mask */ + +/**@} end of group SIMO_BUCK_ALERT_THR_D_Register */ + +/** + * @ingroup simo_registers + * @defgroup SIMO_BUCK_OUT_READY SIMO_BUCK_OUT_READY + * @brief Buck Regulator Output Ready Register + * @{ + */ +#define MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYA_POS 0 /**< BUCK_OUT_READY_BUCKOUTRDYA Position */ +#define MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYA ((uint32_t)(0x1UL << MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYA_POS)) /**< BUCK_OUT_READY_BUCKOUTRDYA Mask */ + +#define MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYB_POS 1 /**< BUCK_OUT_READY_BUCKOUTRDYB Position */ +#define MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYB ((uint32_t)(0x1UL << MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYB_POS)) /**< BUCK_OUT_READY_BUCKOUTRDYB Mask */ + +#define MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYC_POS 2 /**< BUCK_OUT_READY_BUCKOUTRDYC Position */ +#define MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYC ((uint32_t)(0x1UL << MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYC_POS)) /**< BUCK_OUT_READY_BUCKOUTRDYC Mask */ + +#define MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYD_POS 3 /**< BUCK_OUT_READY_BUCKOUTRDYD Position */ +#define MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYD ((uint32_t)(0x1UL << MXC_F_SIMO_BUCK_OUT_READY_BUCKOUTRDYD_POS)) /**< BUCK_OUT_READY_BUCKOUTRDYD Mask */ + +/**@} end of group SIMO_BUCK_OUT_READY_Register */ + +/** + * @ingroup simo_registers + * @defgroup SIMO_ZERO_CROSS_CAL_A SIMO_ZERO_CROSS_CAL_A + * @brief Zero Cross Calibration VERGO_A Register + * @{ + */ +#define MXC_F_SIMO_ZERO_CROSS_CAL_A_ZXCALA_POS 0 /**< ZERO_CROSS_CAL_A_ZXCALA Position */ +#define MXC_F_SIMO_ZERO_CROSS_CAL_A_ZXCALA ((uint32_t)(0xFUL << MXC_F_SIMO_ZERO_CROSS_CAL_A_ZXCALA_POS)) /**< ZERO_CROSS_CAL_A_ZXCALA Mask */ + +/**@} end of group SIMO_ZERO_CROSS_CAL_A_Register */ + +/** + * @ingroup simo_registers + * @defgroup SIMO_ZERO_CROSS_CAL_B SIMO_ZERO_CROSS_CAL_B + * @brief Zero Cross Calibration VERGO_B Register + * @{ + */ +#define MXC_F_SIMO_ZERO_CROSS_CAL_B_ZXCALB_POS 0 /**< ZERO_CROSS_CAL_B_ZXCALB Position */ +#define MXC_F_SIMO_ZERO_CROSS_CAL_B_ZXCALB ((uint32_t)(0xFUL << MXC_F_SIMO_ZERO_CROSS_CAL_B_ZXCALB_POS)) /**< ZERO_CROSS_CAL_B_ZXCALB Mask */ + +/**@} end of group SIMO_ZERO_CROSS_CAL_B_Register */ + +/** + * @ingroup simo_registers + * @defgroup SIMO_ZERO_CROSS_CAL_C SIMO_ZERO_CROSS_CAL_C + * @brief Zero Cross Calibration VERGO_C Register + * @{ + */ +#define MXC_F_SIMO_ZERO_CROSS_CAL_C_ZXCALC_POS 0 /**< ZERO_CROSS_CAL_C_ZXCALC Position */ +#define MXC_F_SIMO_ZERO_CROSS_CAL_C_ZXCALC ((uint32_t)(0xFUL << MXC_F_SIMO_ZERO_CROSS_CAL_C_ZXCALC_POS)) /**< ZERO_CROSS_CAL_C_ZXCALC Mask */ + +/**@} end of group SIMO_ZERO_CROSS_CAL_C_Register */ + +/** + * @ingroup simo_registers + * @defgroup SIMO_ZERO_CROSS_CAL_D SIMO_ZERO_CROSS_CAL_D + * @brief Zero Cross Calibration VERGO_D Register + * @{ + */ +#define MXC_F_SIMO_ZERO_CROSS_CAL_D_ZXCALD_POS 0 /**< ZERO_CROSS_CAL_D_ZXCALD Position */ +#define MXC_F_SIMO_ZERO_CROSS_CAL_D_ZXCALD ((uint32_t)(0xFUL << MXC_F_SIMO_ZERO_CROSS_CAL_D_ZXCALD_POS)) /**< ZERO_CROSS_CAL_D_ZXCALD Mask */ + +/**@} end of group SIMO_ZERO_CROSS_CAL_D_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_SIMO_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sir_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sir_regs.h new file mode 100644 index 00000000000..d40d745b137 --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sir_regs.h @@ -0,0 +1,179 @@ +/** + * @file sir_regs.h + * @brief Registers, Bit Masks and Bit Positions for the SIR Peripheral Module. + * @note This file is @generated. + * @ingroup sir_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_SIR_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_SIR_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup sir + * @defgroup sir_registers SIR_Registers + * @brief Registers, Bit Masks and Bit Positions for the SIR Peripheral Module. + * @details System Initialization Registers. + */ + +/** + * @ingroup sir_registers + * Structure type to access the SIR Registers. + */ +typedef struct { + __I uint32_t sistat; /**< \b 0x00: SIR SISTAT Register */ + __I uint32_t addr; /**< \b 0x04: SIR ADDR Register */ + __R uint32_t rsv_0x8_0x47[16]; + __IO uint32_t btleldotrim; /**< \b 0x48: SIR BTLELDOTRIM Register */ + __R uint32_t rsv_0x4c_0xff[45]; + __I uint32_t fstat; /**< \b 0x100: SIR FSTAT Register */ + __I uint32_t sfstat; /**< \b 0x104: SIR SFSTAT Register */ +} mxc_sir_regs_t; + +/* Register offsets for module SIR */ +/** + * @ingroup sir_registers + * @defgroup SIR_Register_Offsets Register Offsets + * @brief SIR Peripheral Register Offsets from the SIR Base Peripheral Address. + * @{ + */ +#define MXC_R_SIR_SISTAT ((uint32_t)0x00000000UL) /**< Offset from SIR Base Address: 0x0000 */ +#define MXC_R_SIR_ADDR ((uint32_t)0x00000004UL) /**< Offset from SIR Base Address: 0x0004 */ +#define MXC_R_SIR_BTLELDOTRIM ((uint32_t)0x00000048UL) /**< Offset from SIR Base Address: 0x0048 */ +#define MXC_R_SIR_FSTAT ((uint32_t)0x00000100UL) /**< Offset from SIR Base Address: 0x0100 */ +#define MXC_R_SIR_SFSTAT ((uint32_t)0x00000104UL) /**< Offset from SIR Base Address: 0x0104 */ +/**@} end of group sir_registers */ + +/** + * @ingroup sir_registers + * @defgroup SIR_SISTAT SIR_SISTAT + * @brief System Initialization Status Register. + * @{ + */ +#define MXC_F_SIR_SISTAT_MAGIC_POS 0 /**< SISTAT_MAGIC Position */ +#define MXC_F_SIR_SISTAT_MAGIC ((uint32_t)(0x1UL << MXC_F_SIR_SISTAT_MAGIC_POS)) /**< SISTAT_MAGIC Mask */ + +#define MXC_F_SIR_SISTAT_CRCERR_POS 1 /**< SISTAT_CRCERR Position */ +#define MXC_F_SIR_SISTAT_CRCERR ((uint32_t)(0x1UL << MXC_F_SIR_SISTAT_CRCERR_POS)) /**< SISTAT_CRCERR Mask */ + +/**@} end of group SIR_SISTAT_Register */ + +/** + * @ingroup sir_registers + * @defgroup SIR_ADDR SIR_ADDR + * @brief Read-only field set by the SIB block if a CRC error occurs during the read of + * the OTP memory. Contains the failing address in OTP memory (when CRCERR equals + * 1). + * @{ + */ +#define MXC_F_SIR_ADDR_ERRADDR_POS 0 /**< ADDR_ERRADDR Position */ +#define MXC_F_SIR_ADDR_ERRADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_SIR_ADDR_ERRADDR_POS)) /**< ADDR_ERRADDR Mask */ + +/**@} end of group SIR_ADDR_Register */ + +/** + * @ingroup sir_registers + * @defgroup SIR_BTLELDOTRIM SIR_BTLELDOTRIM + * @brief BTLE LDO Trim register. + * @{ + */ +#define MXC_F_SIR_BTLELDOTRIM_TX_POS 0 /**< BTLELDOTRIM_TX Position */ +#define MXC_F_SIR_BTLELDOTRIM_TX ((uint32_t)(0x1FUL << MXC_F_SIR_BTLELDOTRIM_TX_POS)) /**< BTLELDOTRIM_TX Mask */ + +#define MXC_F_SIR_BTLELDOTRIM_RX_POS 8 /**< BTLELDOTRIM_RX Position */ +#define MXC_F_SIR_BTLELDOTRIM_RX ((uint32_t)(0x1FUL << MXC_F_SIR_BTLELDOTRIM_RX_POS)) /**< BTLELDOTRIM_RX Mask */ + +/**@} end of group SIR_BTLELDOTRIM_Register */ + +/** + * @ingroup sir_registers + * @defgroup SIR_FSTAT SIR_FSTAT + * @brief funcstat register. + * @{ + */ +#define MXC_F_SIR_FSTAT_FPU_POS 0 /**< FSTAT_FPU Position */ +#define MXC_F_SIR_FSTAT_FPU ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_FPU_POS)) /**< FSTAT_FPU Mask */ + +#define MXC_F_SIR_FSTAT_ADC_POS 2 /**< FSTAT_ADC Position */ +#define MXC_F_SIR_FSTAT_ADC ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_ADC_POS)) /**< FSTAT_ADC Mask */ + +#define MXC_F_SIR_FSTAT_SEMA_POS 7 /**< FSTAT_SEMA Position */ +#define MXC_F_SIR_FSTAT_SEMA ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_SEMA_POS)) /**< FSTAT_SEMA Mask */ + +/**@} end of group SIR_FSTAT_Register */ + +/** + * @ingroup sir_registers + * @defgroup SIR_SFSTAT SIR_SFSTAT + * @brief Security function status register. + * @{ + */ +#define MXC_F_SIR_SFSTAT_SECBOOT_POS 0 /**< SFSTAT_SECBOOT Position */ +#define MXC_F_SIR_SFSTAT_SECBOOT ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_SECBOOT_POS)) /**< SFSTAT_SECBOOT Mask */ + +#define MXC_F_SIR_SFSTAT_TRNG_POS 2 /**< SFSTAT_TRNG Position */ +#define MXC_F_SIR_SFSTAT_TRNG ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_TRNG_POS)) /**< SFSTAT_TRNG Mask */ + +#define MXC_F_SIR_SFSTAT_AES_POS 3 /**< SFSTAT_AES Position */ +#define MXC_F_SIR_SFSTAT_AES ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_AES_POS)) /**< SFSTAT_AES Mask */ + +/**@} end of group SIR_SFSTAT_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_SIR_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spi_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spi_regs.h new file mode 100644 index 00000000000..870c3678174 --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spi_regs.h @@ -0,0 +1,507 @@ +/** + * @file spi_regs.h + * @brief Registers, Bit Masks and Bit Positions for the SPI Peripheral Module. + * @note This file is @generated. + * @ingroup spi_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_SPI_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_SPI_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup spi + * @defgroup spi_registers SPI_Registers + * @brief Registers, Bit Masks and Bit Positions for the SPI Peripheral Module. + * @details SPI peripheral. + */ + +/** + * @ingroup spi_registers + * Structure type to access the SPI Registers. + */ +typedef struct { + union { + __IO uint32_t fifo32; /**< \b 0x00: SPI FIFO32 Register */ + __IO uint16_t fifo16[2]; /**< \b 0x00: SPI FIFO16 Register */ + __IO uint8_t fifo8[4]; /**< \b 0x00: SPI FIFO8 Register */ + }; + __IO uint32_t ctrl0; /**< \b 0x04: SPI CTRL0 Register */ + __IO uint32_t ctrl1; /**< \b 0x08: SPI CTRL1 Register */ + __IO uint32_t ctrl2; /**< \b 0x0C: SPI CTRL2 Register */ + __IO uint32_t sstime; /**< \b 0x10: SPI SSTIME Register */ + __IO uint32_t clkctrl; /**< \b 0x14: SPI CLKCTRL Register */ + __R uint32_t rsv_0x18; + __IO uint32_t dma; /**< \b 0x1C: SPI DMA Register */ + __IO uint32_t intfl; /**< \b 0x20: SPI INTFL Register */ + __IO uint32_t inten; /**< \b 0x24: SPI INTEN Register */ + __IO uint32_t wkfl; /**< \b 0x28: SPI WKFL Register */ + __IO uint32_t wken; /**< \b 0x2C: SPI WKEN Register */ + __I uint32_t status; /**< \b 0x30: SPI STATUS Register */ +} mxc_spi_regs_t; + +/* Register offsets for module SPI */ +/** + * @ingroup spi_registers + * @defgroup SPI_Register_Offsets Register Offsets + * @brief SPI Peripheral Register Offsets from the SPI Base Peripheral Address. + * @{ + */ +#define MXC_R_SPI_FIFO32 ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: 0x0000 */ +#define MXC_R_SPI_FIFO16 ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: 0x0000 */ +#define MXC_R_SPI_FIFO8 ((uint32_t)0x00000000UL) /**< Offset from SPI Base Address: 0x0000 */ +#define MXC_R_SPI_CTRL0 ((uint32_t)0x00000004UL) /**< Offset from SPI Base Address: 0x0004 */ +#define MXC_R_SPI_CTRL1 ((uint32_t)0x00000008UL) /**< Offset from SPI Base Address: 0x0008 */ +#define MXC_R_SPI_CTRL2 ((uint32_t)0x0000000CUL) /**< Offset from SPI Base Address: 0x000C */ +#define MXC_R_SPI_SSTIME ((uint32_t)0x00000010UL) /**< Offset from SPI Base Address: 0x0010 */ +#define MXC_R_SPI_CLKCTRL ((uint32_t)0x00000014UL) /**< Offset from SPI Base Address: 0x0014 */ +#define MXC_R_SPI_DMA ((uint32_t)0x0000001CUL) /**< Offset from SPI Base Address: 0x001C */ +#define MXC_R_SPI_INTFL ((uint32_t)0x00000020UL) /**< Offset from SPI Base Address: 0x0020 */ +#define MXC_R_SPI_INTEN ((uint32_t)0x00000024UL) /**< Offset from SPI Base Address: 0x0024 */ +#define MXC_R_SPI_WKFL ((uint32_t)0x00000028UL) /**< Offset from SPI Base Address: 0x0028 */ +#define MXC_R_SPI_WKEN ((uint32_t)0x0000002CUL) /**< Offset from SPI Base Address: 0x002C */ +#define MXC_R_SPI_STATUS ((uint32_t)0x00000030UL) /**< Offset from SPI Base Address: 0x0030 */ +/**@} end of group spi_registers */ + +/** + * @ingroup spi_registers + * @defgroup SPI_FIFO32 SPI_FIFO32 + * @brief Register for reading and writing the FIFO. + * @{ + */ +#define MXC_F_SPI_FIFO32_DATA_POS 0 /**< FIFO32_DATA Position */ +#define MXC_F_SPI_FIFO32_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_SPI_FIFO32_DATA_POS)) /**< FIFO32_DATA Mask */ + +/**@} end of group SPI_FIFO32_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_FIFO16 SPI_FIFO16 + * @brief Register for reading and writing the FIFO. + * @{ + */ +#define MXC_F_SPI_FIFO16_DATA_POS 0 /**< FIFO16_DATA Position */ +#define MXC_F_SPI_FIFO16_DATA ((uint16_t)(0xFFFFUL << MXC_F_SPI_FIFO16_DATA_POS)) /**< FIFO16_DATA Mask */ + +/**@} end of group SPI_FIFO16_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_FIFO8 SPI_FIFO8 + * @brief Register for reading and writing the FIFO. + * @{ + */ +#define MXC_F_SPI_FIFO8_DATA_POS 0 /**< FIFO8_DATA Position */ +#define MXC_F_SPI_FIFO8_DATA ((uint8_t)(0xFFUL << MXC_F_SPI_FIFO8_DATA_POS)) /**< FIFO8_DATA Mask */ + +/**@} end of group SPI_FIFO8_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_CTRL0 SPI_CTRL0 + * @brief Register for controlling SPI peripheral. + * @{ + */ +#define MXC_F_SPI_CTRL0_EN_POS 0 /**< CTRL0_EN Position */ +#define MXC_F_SPI_CTRL0_EN ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_EN_POS)) /**< CTRL0_EN Mask */ + +#define MXC_F_SPI_CTRL0_MST_MODE_POS 1 /**< CTRL0_MST_MODE Position */ +#define MXC_F_SPI_CTRL0_MST_MODE ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_MST_MODE_POS)) /**< CTRL0_MST_MODE Mask */ + +#define MXC_F_SPI_CTRL0_SS_IO_POS 4 /**< CTRL0_SS_IO Position */ +#define MXC_F_SPI_CTRL0_SS_IO ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_IO_POS)) /**< CTRL0_SS_IO Mask */ + +#define MXC_F_SPI_CTRL0_START_POS 5 /**< CTRL0_START Position */ +#define MXC_F_SPI_CTRL0_START ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_START_POS)) /**< CTRL0_START Mask */ + +#define MXC_F_SPI_CTRL0_SS_CTRL_POS 8 /**< CTRL0_SS_CTRL Position */ +#define MXC_F_SPI_CTRL0_SS_CTRL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_CTRL_POS)) /**< CTRL0_SS_CTRL Mask */ + +#define MXC_F_SPI_CTRL0_SS_ACTIVE_POS 16 /**< CTRL0_SS_ACTIVE Position */ +#define MXC_F_SPI_CTRL0_SS_ACTIVE ((uint32_t)(0xFUL << MXC_F_SPI_CTRL0_SS_ACTIVE_POS)) /**< CTRL0_SS_ACTIVE Mask */ +#define MXC_V_SPI_CTRL0_SS_ACTIVE_SS0 ((uint32_t)0x1UL) /**< CTRL0_SS_ACTIVE_SS0 Value */ +#define MXC_S_SPI_CTRL0_SS_ACTIVE_SS0 (MXC_V_SPI_CTRL0_SS_ACTIVE_SS0 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS0 Setting */ +#define MXC_V_SPI_CTRL0_SS_ACTIVE_SS1 ((uint32_t)0x2UL) /**< CTRL0_SS_ACTIVE_SS1 Value */ +#define MXC_S_SPI_CTRL0_SS_ACTIVE_SS1 (MXC_V_SPI_CTRL0_SS_ACTIVE_SS1 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS1 Setting */ +#define MXC_V_SPI_CTRL0_SS_ACTIVE_SS2 ((uint32_t)0x4UL) /**< CTRL0_SS_ACTIVE_SS2 Value */ +#define MXC_S_SPI_CTRL0_SS_ACTIVE_SS2 (MXC_V_SPI_CTRL0_SS_ACTIVE_SS2 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS2 Setting */ +#define MXC_V_SPI_CTRL0_SS_ACTIVE_SS3 ((uint32_t)0x8UL) /**< CTRL0_SS_ACTIVE_SS3 Value */ +#define MXC_S_SPI_CTRL0_SS_ACTIVE_SS3 (MXC_V_SPI_CTRL0_SS_ACTIVE_SS3 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS3 Setting */ + +/**@} end of group SPI_CTRL0_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_CTRL1 SPI_CTRL1 + * @brief Register for controlling SPI peripheral. + * @{ + */ +#define MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS 0 /**< CTRL1_TX_NUM_CHAR Position */ +#define MXC_F_SPI_CTRL1_TX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_TX_NUM_CHAR_POS)) /**< CTRL1_TX_NUM_CHAR Mask */ + +#define MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS 16 /**< CTRL1_RX_NUM_CHAR Position */ +#define MXC_F_SPI_CTRL1_RX_NUM_CHAR ((uint32_t)(0xFFFFUL << MXC_F_SPI_CTRL1_RX_NUM_CHAR_POS)) /**< CTRL1_RX_NUM_CHAR Mask */ + +/**@} end of group SPI_CTRL1_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_CTRL2 SPI_CTRL2 + * @brief Register for controlling SPI peripheral. + * @{ + */ +#define MXC_F_SPI_CTRL2_CLKPHA_POS 0 /**< CTRL2_CLKPHA Position */ +#define MXC_F_SPI_CTRL2_CLKPHA ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLKPHA_POS)) /**< CTRL2_CLKPHA Mask */ + +#define MXC_F_SPI_CTRL2_CLKPOL_POS 1 /**< CTRL2_CLKPOL Position */ +#define MXC_F_SPI_CTRL2_CLKPOL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_CLKPOL_POS)) /**< CTRL2_CLKPOL Mask */ + +#define MXC_F_SPI_CTRL2_SCLK_FB_INV_POS 4 /**< CTRL2_SCLK_FB_INV Position */ +#define MXC_F_SPI_CTRL2_SCLK_FB_INV ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_SCLK_FB_INV_POS)) /**< CTRL2_SCLK_FB_INV Mask */ + +#define MXC_F_SPI_CTRL2_NUMBITS_POS 8 /**< CTRL2_NUMBITS Position */ +#define MXC_F_SPI_CTRL2_NUMBITS ((uint32_t)(0xFUL << MXC_F_SPI_CTRL2_NUMBITS_POS)) /**< CTRL2_NUMBITS Mask */ +#define MXC_V_SPI_CTRL2_NUMBITS_16 ((uint32_t)0x0UL) /**< CTRL2_NUMBITS_16 Value */ +#define MXC_S_SPI_CTRL2_NUMBITS_16 (MXC_V_SPI_CTRL2_NUMBITS_16 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_16 Setting */ +#define MXC_V_SPI_CTRL2_NUMBITS_1 ((uint32_t)0x1UL) /**< CTRL2_NUMBITS_1 Value */ +#define MXC_S_SPI_CTRL2_NUMBITS_1 (MXC_V_SPI_CTRL2_NUMBITS_1 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_1 Setting */ +#define MXC_V_SPI_CTRL2_NUMBITS_2 ((uint32_t)0x2UL) /**< CTRL2_NUMBITS_2 Value */ +#define MXC_S_SPI_CTRL2_NUMBITS_2 (MXC_V_SPI_CTRL2_NUMBITS_2 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_2 Setting */ +#define MXC_V_SPI_CTRL2_NUMBITS_3 ((uint32_t)0x3UL) /**< CTRL2_NUMBITS_3 Value */ +#define MXC_S_SPI_CTRL2_NUMBITS_3 (MXC_V_SPI_CTRL2_NUMBITS_3 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_3 Setting */ +#define MXC_V_SPI_CTRL2_NUMBITS_4 ((uint32_t)0x4UL) /**< CTRL2_NUMBITS_4 Value */ +#define MXC_S_SPI_CTRL2_NUMBITS_4 (MXC_V_SPI_CTRL2_NUMBITS_4 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_4 Setting */ +#define MXC_V_SPI_CTRL2_NUMBITS_5 ((uint32_t)0x5UL) /**< CTRL2_NUMBITS_5 Value */ +#define MXC_S_SPI_CTRL2_NUMBITS_5 (MXC_V_SPI_CTRL2_NUMBITS_5 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_5 Setting */ +#define MXC_V_SPI_CTRL2_NUMBITS_6 ((uint32_t)0x6UL) /**< CTRL2_NUMBITS_6 Value */ +#define MXC_S_SPI_CTRL2_NUMBITS_6 (MXC_V_SPI_CTRL2_NUMBITS_6 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_6 Setting */ +#define MXC_V_SPI_CTRL2_NUMBITS_7 ((uint32_t)0x7UL) /**< CTRL2_NUMBITS_7 Value */ +#define MXC_S_SPI_CTRL2_NUMBITS_7 (MXC_V_SPI_CTRL2_NUMBITS_7 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_7 Setting */ +#define MXC_V_SPI_CTRL2_NUMBITS_8 ((uint32_t)0x8UL) /**< CTRL2_NUMBITS_8 Value */ +#define MXC_S_SPI_CTRL2_NUMBITS_8 (MXC_V_SPI_CTRL2_NUMBITS_8 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_8 Setting */ +#define MXC_V_SPI_CTRL2_NUMBITS_9 ((uint32_t)0x9UL) /**< CTRL2_NUMBITS_9 Value */ +#define MXC_S_SPI_CTRL2_NUMBITS_9 (MXC_V_SPI_CTRL2_NUMBITS_9 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_9 Setting */ +#define MXC_V_SPI_CTRL2_NUMBITS_10 ((uint32_t)0xAUL) /**< CTRL2_NUMBITS_10 Value */ +#define MXC_S_SPI_CTRL2_NUMBITS_10 (MXC_V_SPI_CTRL2_NUMBITS_10 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_10 Setting */ +#define MXC_V_SPI_CTRL2_NUMBITS_11 ((uint32_t)0xBUL) /**< CTRL2_NUMBITS_11 Value */ +#define MXC_S_SPI_CTRL2_NUMBITS_11 (MXC_V_SPI_CTRL2_NUMBITS_11 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_11 Setting */ +#define MXC_V_SPI_CTRL2_NUMBITS_12 ((uint32_t)0xCUL) /**< CTRL2_NUMBITS_12 Value */ +#define MXC_S_SPI_CTRL2_NUMBITS_12 (MXC_V_SPI_CTRL2_NUMBITS_12 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_12 Setting */ +#define MXC_V_SPI_CTRL2_NUMBITS_13 ((uint32_t)0xDUL) /**< CTRL2_NUMBITS_13 Value */ +#define MXC_S_SPI_CTRL2_NUMBITS_13 (MXC_V_SPI_CTRL2_NUMBITS_13 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_13 Setting */ +#define MXC_V_SPI_CTRL2_NUMBITS_14 ((uint32_t)0xEUL) /**< CTRL2_NUMBITS_14 Value */ +#define MXC_S_SPI_CTRL2_NUMBITS_14 (MXC_V_SPI_CTRL2_NUMBITS_14 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_14 Setting */ +#define MXC_V_SPI_CTRL2_NUMBITS_15 ((uint32_t)0xFUL) /**< CTRL2_NUMBITS_15 Value */ +#define MXC_S_SPI_CTRL2_NUMBITS_15 (MXC_V_SPI_CTRL2_NUMBITS_15 << MXC_F_SPI_CTRL2_NUMBITS_POS) /**< CTRL2_NUMBITS_15 Setting */ + +#define MXC_F_SPI_CTRL2_DATA_WIDTH_POS 12 /**< CTRL2_DATA_WIDTH Position */ +#define MXC_F_SPI_CTRL2_DATA_WIDTH ((uint32_t)(0x3UL << MXC_F_SPI_CTRL2_DATA_WIDTH_POS)) /**< CTRL2_DATA_WIDTH Mask */ +#define MXC_V_SPI_CTRL2_DATA_WIDTH_MONO ((uint32_t)0x0UL) /**< CTRL2_DATA_WIDTH_MONO Value */ +#define MXC_S_SPI_CTRL2_DATA_WIDTH_MONO (MXC_V_SPI_CTRL2_DATA_WIDTH_MONO << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_MONO Setting */ +#define MXC_V_SPI_CTRL2_DATA_WIDTH_DUAL ((uint32_t)0x1UL) /**< CTRL2_DATA_WIDTH_DUAL Value */ +#define MXC_S_SPI_CTRL2_DATA_WIDTH_DUAL (MXC_V_SPI_CTRL2_DATA_WIDTH_DUAL << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_DUAL Setting */ +#define MXC_V_SPI_CTRL2_DATA_WIDTH_QUAD ((uint32_t)0x2UL) /**< CTRL2_DATA_WIDTH_QUAD Value */ +#define MXC_S_SPI_CTRL2_DATA_WIDTH_QUAD (MXC_V_SPI_CTRL2_DATA_WIDTH_QUAD << MXC_F_SPI_CTRL2_DATA_WIDTH_POS) /**< CTRL2_DATA_WIDTH_QUAD Setting */ + +#define MXC_F_SPI_CTRL2_THREE_WIRE_POS 15 /**< CTRL2_THREE_WIRE Position */ +#define MXC_F_SPI_CTRL2_THREE_WIRE ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_THREE_WIRE_POS)) /**< CTRL2_THREE_WIRE Mask */ + +#define MXC_F_SPI_CTRL2_SSPOL_POS 16 /**< CTRL2_SSPOL Position */ +#define MXC_F_SPI_CTRL2_SSPOL ((uint32_t)(0xFUL << MXC_F_SPI_CTRL2_SSPOL_POS)) /**< CTRL2_SSPOL Mask */ +#define MXC_V_SPI_CTRL2_SSPOL_SS0_HIGH ((uint32_t)0x1UL) /**< CTRL2_SSPOL_SS0_HIGH Value */ +#define MXC_S_SPI_CTRL2_SSPOL_SS0_HIGH (MXC_V_SPI_CTRL2_SSPOL_SS0_HIGH << MXC_F_SPI_CTRL2_SSPOL_POS) /**< CTRL2_SSPOL_SS0_HIGH Setting */ +#define MXC_V_SPI_CTRL2_SSPOL_SS1_HIGH ((uint32_t)0x2UL) /**< CTRL2_SSPOL_SS1_HIGH Value */ +#define MXC_S_SPI_CTRL2_SSPOL_SS1_HIGH (MXC_V_SPI_CTRL2_SSPOL_SS1_HIGH << MXC_F_SPI_CTRL2_SSPOL_POS) /**< CTRL2_SSPOL_SS1_HIGH Setting */ +#define MXC_V_SPI_CTRL2_SSPOL_SS2_HIGH ((uint32_t)0x4UL) /**< CTRL2_SSPOL_SS2_HIGH Value */ +#define MXC_S_SPI_CTRL2_SSPOL_SS2_HIGH (MXC_V_SPI_CTRL2_SSPOL_SS2_HIGH << MXC_F_SPI_CTRL2_SSPOL_POS) /**< CTRL2_SSPOL_SS2_HIGH Setting */ +#define MXC_V_SPI_CTRL2_SSPOL_SS3_HIGH ((uint32_t)0x8UL) /**< CTRL2_SSPOL_SS3_HIGH Value */ +#define MXC_S_SPI_CTRL2_SSPOL_SS3_HIGH (MXC_V_SPI_CTRL2_SSPOL_SS3_HIGH << MXC_F_SPI_CTRL2_SSPOL_POS) /**< CTRL2_SSPOL_SS3_HIGH Setting */ + +/**@} end of group SPI_CTRL2_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_SSTIME SPI_SSTIME + * @brief Register for controlling SPI peripheral/Slave Select Timing. + * @{ + */ +#define MXC_F_SPI_SSTIME_PRE_POS 0 /**< SSTIME_PRE Position */ +#define MXC_F_SPI_SSTIME_PRE ((uint32_t)(0xFFUL << MXC_F_SPI_SSTIME_PRE_POS)) /**< SSTIME_PRE Mask */ +#define MXC_V_SPI_SSTIME_PRE_256 ((uint32_t)0x0UL) /**< SSTIME_PRE_256 Value */ +#define MXC_S_SPI_SSTIME_PRE_256 (MXC_V_SPI_SSTIME_PRE_256 << MXC_F_SPI_SSTIME_PRE_POS) /**< SSTIME_PRE_256 Setting */ + +#define MXC_F_SPI_SSTIME_POST_POS 8 /**< SSTIME_POST Position */ +#define MXC_F_SPI_SSTIME_POST ((uint32_t)(0xFFUL << MXC_F_SPI_SSTIME_POST_POS)) /**< SSTIME_POST Mask */ +#define MXC_V_SPI_SSTIME_POST_256 ((uint32_t)0x0UL) /**< SSTIME_POST_256 Value */ +#define MXC_S_SPI_SSTIME_POST_256 (MXC_V_SPI_SSTIME_POST_256 << MXC_F_SPI_SSTIME_POST_POS) /**< SSTIME_POST_256 Setting */ + +#define MXC_F_SPI_SSTIME_INACT_POS 16 /**< SSTIME_INACT Position */ +#define MXC_F_SPI_SSTIME_INACT ((uint32_t)(0xFFUL << MXC_F_SPI_SSTIME_INACT_POS)) /**< SSTIME_INACT Mask */ +#define MXC_V_SPI_SSTIME_INACT_256 ((uint32_t)0x0UL) /**< SSTIME_INACT_256 Value */ +#define MXC_S_SPI_SSTIME_INACT_256 (MXC_V_SPI_SSTIME_INACT_256 << MXC_F_SPI_SSTIME_INACT_POS) /**< SSTIME_INACT_256 Setting */ + +/**@} end of group SPI_SSTIME_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_CLKCTRL SPI_CLKCTRL + * @brief Register for controlling SPI clock rate. + * @{ + */ +#define MXC_F_SPI_CLKCTRL_LO_POS 0 /**< CLKCTRL_LO Position */ +#define MXC_F_SPI_CLKCTRL_LO ((uint32_t)(0xFFUL << MXC_F_SPI_CLKCTRL_LO_POS)) /**< CLKCTRL_LO Mask */ +#define MXC_V_SPI_CLKCTRL_LO_DIS ((uint32_t)0x0UL) /**< CLKCTRL_LO_DIS Value */ +#define MXC_S_SPI_CLKCTRL_LO_DIS (MXC_V_SPI_CLKCTRL_LO_DIS << MXC_F_SPI_CLKCTRL_LO_POS) /**< CLKCTRL_LO_DIS Setting */ + +#define MXC_F_SPI_CLKCTRL_HI_POS 8 /**< CLKCTRL_HI Position */ +#define MXC_F_SPI_CLKCTRL_HI ((uint32_t)(0xFFUL << MXC_F_SPI_CLKCTRL_HI_POS)) /**< CLKCTRL_HI Mask */ +#define MXC_V_SPI_CLKCTRL_HI_DIS ((uint32_t)0x0UL) /**< CLKCTRL_HI_DIS Value */ +#define MXC_S_SPI_CLKCTRL_HI_DIS (MXC_V_SPI_CLKCTRL_HI_DIS << MXC_F_SPI_CLKCTRL_HI_POS) /**< CLKCTRL_HI_DIS Setting */ + +#define MXC_F_SPI_CLKCTRL_CLKDIV_POS 16 /**< CLKCTRL_CLKDIV Position */ +#define MXC_F_SPI_CLKCTRL_CLKDIV ((uint32_t)(0xFUL << MXC_F_SPI_CLKCTRL_CLKDIV_POS)) /**< CLKCTRL_CLKDIV Mask */ + +/**@} end of group SPI_CLKCTRL_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_DMA SPI_DMA + * @brief Register for controlling DMA. + * @{ + */ +#define MXC_F_SPI_DMA_TX_THD_VAL_POS 0 /**< DMA_TX_THD_VAL Position */ +#define MXC_F_SPI_DMA_TX_THD_VAL ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_TX_THD_VAL_POS)) /**< DMA_TX_THD_VAL Mask */ + +#define MXC_F_SPI_DMA_TX_FIFO_EN_POS 6 /**< DMA_TX_FIFO_EN Position */ +#define MXC_F_SPI_DMA_TX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FIFO_EN_POS)) /**< DMA_TX_FIFO_EN Mask */ + +#define MXC_F_SPI_DMA_TX_FLUSH_POS 7 /**< DMA_TX_FLUSH Position */ +#define MXC_F_SPI_DMA_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_FLUSH_POS)) /**< DMA_TX_FLUSH Mask */ + +#define MXC_F_SPI_DMA_TX_LVL_POS 8 /**< DMA_TX_LVL Position */ +#define MXC_F_SPI_DMA_TX_LVL ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_TX_LVL_POS)) /**< DMA_TX_LVL Mask */ + +#define MXC_F_SPI_DMA_TX_EN_POS 15 /**< DMA_TX_EN Position */ +#define MXC_F_SPI_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */ + +#define MXC_F_SPI_DMA_RX_THD_VAL_POS 16 /**< DMA_RX_THD_VAL Position */ +#define MXC_F_SPI_DMA_RX_THD_VAL ((uint32_t)(0x1FUL << MXC_F_SPI_DMA_RX_THD_VAL_POS)) /**< DMA_RX_THD_VAL Mask */ + +#define MXC_F_SPI_DMA_RX_FIFO_EN_POS 22 /**< DMA_RX_FIFO_EN Position */ +#define MXC_F_SPI_DMA_RX_FIFO_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FIFO_EN_POS)) /**< DMA_RX_FIFO_EN Mask */ + +#define MXC_F_SPI_DMA_RX_FLUSH_POS 23 /**< DMA_RX_FLUSH Position */ +#define MXC_F_SPI_DMA_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_FLUSH_POS)) /**< DMA_RX_FLUSH Mask */ + +#define MXC_F_SPI_DMA_RX_LVL_POS 24 /**< DMA_RX_LVL Position */ +#define MXC_F_SPI_DMA_RX_LVL ((uint32_t)(0x3FUL << MXC_F_SPI_DMA_RX_LVL_POS)) /**< DMA_RX_LVL Mask */ + +#define MXC_F_SPI_DMA_RX_EN_POS 31 /**< DMA_RX_EN Position */ +#define MXC_F_SPI_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_SPI_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */ + +/**@} end of group SPI_DMA_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_INTFL SPI_INTFL + * @brief Register for reading and clearing interrupt flags. All bits are write 1 to + * clear. + * @{ + */ +#define MXC_F_SPI_INTFL_TX_THD_POS 0 /**< INTFL_TX_THD Position */ +#define MXC_F_SPI_INTFL_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_THD_POS)) /**< INTFL_TX_THD Mask */ + +#define MXC_F_SPI_INTFL_TX_EM_POS 1 /**< INTFL_TX_EM Position */ +#define MXC_F_SPI_INTFL_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_EM_POS)) /**< INTFL_TX_EM Mask */ + +#define MXC_F_SPI_INTFL_RX_THD_POS 2 /**< INTFL_RX_THD Position */ +#define MXC_F_SPI_INTFL_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_THD_POS)) /**< INTFL_RX_THD Mask */ + +#define MXC_F_SPI_INTFL_RX_FULL_POS 3 /**< INTFL_RX_FULL Position */ +#define MXC_F_SPI_INTFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_FULL_POS)) /**< INTFL_RX_FULL Mask */ + +#define MXC_F_SPI_INTFL_SSA_POS 4 /**< INTFL_SSA Position */ +#define MXC_F_SPI_INTFL_SSA ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_SSA_POS)) /**< INTFL_SSA Mask */ + +#define MXC_F_SPI_INTFL_SSD_POS 5 /**< INTFL_SSD Position */ +#define MXC_F_SPI_INTFL_SSD ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_SSD_POS)) /**< INTFL_SSD Mask */ + +#define MXC_F_SPI_INTFL_FAULT_POS 8 /**< INTFL_FAULT Position */ +#define MXC_F_SPI_INTFL_FAULT ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_FAULT_POS)) /**< INTFL_FAULT Mask */ + +#define MXC_F_SPI_INTFL_ABORT_POS 9 /**< INTFL_ABORT Position */ +#define MXC_F_SPI_INTFL_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_ABORT_POS)) /**< INTFL_ABORT Mask */ + +#define MXC_F_SPI_INTFL_MST_DONE_POS 11 /**< INTFL_MST_DONE Position */ +#define MXC_F_SPI_INTFL_MST_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_MST_DONE_POS)) /**< INTFL_MST_DONE Mask */ + +#define MXC_F_SPI_INTFL_TX_OV_POS 12 /**< INTFL_TX_OV Position */ +#define MXC_F_SPI_INTFL_TX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_OV_POS)) /**< INTFL_TX_OV Mask */ + +#define MXC_F_SPI_INTFL_TX_UN_POS 13 /**< INTFL_TX_UN Position */ +#define MXC_F_SPI_INTFL_TX_UN ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_UN_POS)) /**< INTFL_TX_UN Mask */ + +#define MXC_F_SPI_INTFL_RX_OV_POS 14 /**< INTFL_RX_OV Position */ +#define MXC_F_SPI_INTFL_RX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_OV_POS)) /**< INTFL_RX_OV Mask */ + +#define MXC_F_SPI_INTFL_RX_UN_POS 15 /**< INTFL_RX_UN Position */ +#define MXC_F_SPI_INTFL_RX_UN ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_UN_POS)) /**< INTFL_RX_UN Mask */ + +/**@} end of group SPI_INTFL_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_INTEN SPI_INTEN + * @brief Register for enabling interrupts. + * @{ + */ +#define MXC_F_SPI_INTEN_TX_THD_POS 0 /**< INTEN_TX_THD Position */ +#define MXC_F_SPI_INTEN_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_THD_POS)) /**< INTEN_TX_THD Mask */ + +#define MXC_F_SPI_INTEN_TX_EM_POS 1 /**< INTEN_TX_EM Position */ +#define MXC_F_SPI_INTEN_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_EM_POS)) /**< INTEN_TX_EM Mask */ + +#define MXC_F_SPI_INTEN_RX_THD_POS 2 /**< INTEN_RX_THD Position */ +#define MXC_F_SPI_INTEN_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_THD_POS)) /**< INTEN_RX_THD Mask */ + +#define MXC_F_SPI_INTEN_RX_FULL_POS 3 /**< INTEN_RX_FULL Position */ +#define MXC_F_SPI_INTEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_FULL_POS)) /**< INTEN_RX_FULL Mask */ + +#define MXC_F_SPI_INTEN_SSA_POS 4 /**< INTEN_SSA Position */ +#define MXC_F_SPI_INTEN_SSA ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_SSA_POS)) /**< INTEN_SSA Mask */ + +#define MXC_F_SPI_INTEN_SSD_POS 5 /**< INTEN_SSD Position */ +#define MXC_F_SPI_INTEN_SSD ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_SSD_POS)) /**< INTEN_SSD Mask */ + +#define MXC_F_SPI_INTEN_FAULT_POS 8 /**< INTEN_FAULT Position */ +#define MXC_F_SPI_INTEN_FAULT ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_FAULT_POS)) /**< INTEN_FAULT Mask */ + +#define MXC_F_SPI_INTEN_ABORT_POS 9 /**< INTEN_ABORT Position */ +#define MXC_F_SPI_INTEN_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_ABORT_POS)) /**< INTEN_ABORT Mask */ + +#define MXC_F_SPI_INTEN_MST_DONE_POS 11 /**< INTEN_MST_DONE Position */ +#define MXC_F_SPI_INTEN_MST_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_MST_DONE_POS)) /**< INTEN_MST_DONE Mask */ + +#define MXC_F_SPI_INTEN_TX_OV_POS 12 /**< INTEN_TX_OV Position */ +#define MXC_F_SPI_INTEN_TX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_OV_POS)) /**< INTEN_TX_OV Mask */ + +#define MXC_F_SPI_INTEN_TX_UN_POS 13 /**< INTEN_TX_UN Position */ +#define MXC_F_SPI_INTEN_TX_UN ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_UN_POS)) /**< INTEN_TX_UN Mask */ + +#define MXC_F_SPI_INTEN_RX_OV_POS 14 /**< INTEN_RX_OV Position */ +#define MXC_F_SPI_INTEN_RX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_OV_POS)) /**< INTEN_RX_OV Mask */ + +#define MXC_F_SPI_INTEN_RX_UN_POS 15 /**< INTEN_RX_UN Position */ +#define MXC_F_SPI_INTEN_RX_UN ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_UN_POS)) /**< INTEN_RX_UN Mask */ + +/**@} end of group SPI_INTEN_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_WKFL SPI_WKFL + * @brief Register for wake up flags. All bits in this register are write 1 to clear. + * @{ + */ +#define MXC_F_SPI_WKFL_TX_THD_POS 0 /**< WKFL_TX_THD Position */ +#define MXC_F_SPI_WKFL_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_WKFL_TX_THD_POS)) /**< WKFL_TX_THD Mask */ + +#define MXC_F_SPI_WKFL_TX_EM_POS 1 /**< WKFL_TX_EM Position */ +#define MXC_F_SPI_WKFL_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_WKFL_TX_EM_POS)) /**< WKFL_TX_EM Mask */ + +#define MXC_F_SPI_WKFL_RX_THD_POS 2 /**< WKFL_RX_THD Position */ +#define MXC_F_SPI_WKFL_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_WKFL_RX_THD_POS)) /**< WKFL_RX_THD Mask */ + +#define MXC_F_SPI_WKFL_RX_FULL_POS 3 /**< WKFL_RX_FULL Position */ +#define MXC_F_SPI_WKFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_WKFL_RX_FULL_POS)) /**< WKFL_RX_FULL Mask */ + +/**@} end of group SPI_WKFL_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_WKEN SPI_WKEN + * @brief Register for wake up enable. + * @{ + */ +#define MXC_F_SPI_WKEN_TX_THD_POS 0 /**< WKEN_TX_THD Position */ +#define MXC_F_SPI_WKEN_TX_THD ((uint32_t)(0x1UL << MXC_F_SPI_WKEN_TX_THD_POS)) /**< WKEN_TX_THD Mask */ + +#define MXC_F_SPI_WKEN_TX_EM_POS 1 /**< WKEN_TX_EM Position */ +#define MXC_F_SPI_WKEN_TX_EM ((uint32_t)(0x1UL << MXC_F_SPI_WKEN_TX_EM_POS)) /**< WKEN_TX_EM Mask */ + +#define MXC_F_SPI_WKEN_RX_THD_POS 2 /**< WKEN_RX_THD Position */ +#define MXC_F_SPI_WKEN_RX_THD ((uint32_t)(0x1UL << MXC_F_SPI_WKEN_RX_THD_POS)) /**< WKEN_RX_THD Mask */ + +#define MXC_F_SPI_WKEN_RX_FULL_POS 3 /**< WKEN_RX_FULL Position */ +#define MXC_F_SPI_WKEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_WKEN_RX_FULL_POS)) /**< WKEN_RX_FULL Mask */ + +/**@} end of group SPI_WKEN_Register */ + +/** + * @ingroup spi_registers + * @defgroup SPI_STATUS SPI_STATUS + * @brief SPI Status register. + * @{ + */ +#define MXC_F_SPI_STATUS_BUSY_POS 0 /**< STATUS_BUSY Position */ +#define MXC_F_SPI_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_SPI_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */ + +/**@} end of group SPI_STATUS_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_SPI_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h new file mode 100644 index 00000000000..fe34a75832e --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h @@ -0,0 +1,101 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_SYSTEM_MAX32657_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_SYSTEM_MAX32657_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + +/* NOTE: HIRC was previously named CRYPTO */ +#ifdef CRYPTO_FREQ +#warning WARNING: CRYPTO_FREQ does not exist in MAX78000, replace with HIRC_FREQ! +#define HIRC_FREQ CRYPTO_FREQ +#endif + +/* NOTE: EXTCLK needs to be defined by user based on the clock they supply */ +#ifndef EXTCLK_FREQ +#define EXTCLK_FREQ 75000000 +#endif + +/* NOTE: This is the nominal value for INRO. The actual value may vary from chip to chip. + Update if use of this oscillator requires precise timing.*/ +/* NOTE: INRO was previously named NANORING */ +#ifndef INRO_FREQ +#define INRO_FREQ 8000 +#endif + +#ifndef IPO_FREQ +#define IPO_FREQ 100000000 +#endif + +#ifndef ISO_FREQ +#define ISO_FREQ 60000000 +#endif + +#ifndef ERFO_FREQ +#define ERFO_FREQ 32000000 +#endif + +#ifndef IBRO_FREQ +#define IBRO_FREQ 7372800 +#endif + +#ifndef ERTCO_FREQ +#define ERTCO_FREQ 32768 +#endif + +#ifndef HIRC_FREQ +#define HIRC_FREQ IPO_FREQ +#endif + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +#ifdef PeripheralClock +#warning PeripheralClock define is being overidden. +#else +#define PeripheralClock (SystemCoreClock / 2) /*!< Peripheral Clock Frequency */ +#endif + +/* + * Initialize the system + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void); + +/* + * Update SystemCoreClock variable + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_SYSTEM_MAX32657_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/tmr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/tmr_regs.h new file mode 100644 index 00000000000..3847c923c3f --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/tmr_regs.h @@ -0,0 +1,232 @@ +/** + * @file tmr_regs.h + * @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module. + * @note This file is @generated. + * @ingroup tmr_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_TMR_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_TMR_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup tmr + * @defgroup tmr_registers TMR_Registers + * @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module. + * @details 32-bit reloadable timer that can be used for timing and event counting. + */ + +/** + * @ingroup tmr_registers + * Structure type to access the TMR Registers. + */ +typedef struct { + __IO uint32_t cnt; /**< \b 0x00: TMR CNT Register */ + __IO uint32_t cmp; /**< \b 0x04: TMR CMP Register */ + __IO uint32_t pwm; /**< \b 0x08: TMR PWM Register */ + __IO uint32_t intfl; /**< \b 0x0C: TMR INTFL Register */ + __IO uint32_t ctrl; /**< \b 0x10: TMR CTRL Register */ + __IO uint32_t nolcmp; /**< \b 0x14: TMR NOLCMP Register */ +} mxc_tmr_regs_t; + +/* Register offsets for module TMR */ +/** + * @ingroup tmr_registers + * @defgroup TMR_Register_Offsets Register Offsets + * @brief TMR Peripheral Register Offsets from the TMR Base Peripheral Address. + * @{ + */ +#define MXC_R_TMR_CNT ((uint32_t)0x00000000UL) /**< Offset from TMR Base Address: 0x0000 */ +#define MXC_R_TMR_CMP ((uint32_t)0x00000004UL) /**< Offset from TMR Base Address: 0x0004 */ +#define MXC_R_TMR_PWM ((uint32_t)0x00000008UL) /**< Offset from TMR Base Address: 0x0008 */ +#define MXC_R_TMR_INTFL ((uint32_t)0x0000000CUL) /**< Offset from TMR Base Address: 0x000C */ +#define MXC_R_TMR_CTRL ((uint32_t)0x00000010UL) /**< Offset from TMR Base Address: 0x0010 */ +#define MXC_R_TMR_NOLCMP ((uint32_t)0x00000014UL) /**< Offset from TMR Base Address: 0x0014 */ +/**@} end of group tmr_registers */ + +/** + * @ingroup tmr_registers + * @defgroup TMR_CNT TMR_CNT + * @brief Count. This register stores the current timer count. + * @{ + */ +#define MXC_F_TMR_CNT_COUNT_POS 0 /**< CNT_COUNT Position */ +#define MXC_F_TMR_CNT_COUNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_CNT_COUNT_POS)) /**< CNT_COUNT Mask */ + +/**@} end of group TMR_CNT_Register */ + +/** + * @ingroup tmr_registers + * @defgroup TMR_CMP TMR_CMP + * @brief Compare. This register stores the compare value, which is used to set the + * maximum count value to initiate a reload of the timer to 0x0001. + * @{ + */ +#define MXC_F_TMR_CMP_COMPARE_POS 0 /**< CMP_COMPARE Position */ +#define MXC_F_TMR_CMP_COMPARE ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_CMP_COMPARE_POS)) /**< CMP_COMPARE Mask */ + +/**@} end of group TMR_CMP_Register */ + +/** + * @ingroup tmr_registers + * @defgroup TMR_PWM TMR_PWM + * @brief PWM. This register stores the value that is compared to the current timer + * count. + * @{ + */ +#define MXC_F_TMR_PWM_PWM_POS 0 /**< PWM_PWM Position */ +#define MXC_F_TMR_PWM_PWM ((uint32_t)(0xFFFFFFFFUL << MXC_F_TMR_PWM_PWM_POS)) /**< PWM_PWM Mask */ + +/**@} end of group TMR_PWM_Register */ + +/** + * @ingroup tmr_registers + * @defgroup TMR_INTFL TMR_INTFL + * @brief Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the + * associated interrupt. + * @{ + */ +#define MXC_F_TMR_INTFL_IRQ_POS 0 /**< INTFL_IRQ Position */ +#define MXC_F_TMR_INTFL_IRQ ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_IRQ_POS)) /**< INTFL_IRQ Mask */ + +/**@} end of group TMR_INTFL_Register */ + +/** + * @ingroup tmr_registers + * @defgroup TMR_CTRL TMR_CTRL + * @brief Timer Control Register. + * @{ + */ +#define MXC_F_TMR_CTRL_MODE_POS 0 /**< CTRL_MODE Position */ +#define MXC_F_TMR_CTRL_MODE ((uint32_t)(0x7UL << MXC_F_TMR_CTRL_MODE_POS)) /**< CTRL_MODE Mask */ +#define MXC_V_TMR_CTRL_MODE_ONESHOT ((uint32_t)0x0UL) /**< CTRL_MODE_ONESHOT Value */ +#define MXC_S_TMR_CTRL_MODE_ONESHOT (MXC_V_TMR_CTRL_MODE_ONESHOT << MXC_F_TMR_CTRL_MODE_POS) /**< CTRL_MODE_ONESHOT Setting */ +#define MXC_V_TMR_CTRL_MODE_CONTINUOUS ((uint32_t)0x1UL) /**< CTRL_MODE_CONTINUOUS Value */ +#define MXC_S_TMR_CTRL_MODE_CONTINUOUS (MXC_V_TMR_CTRL_MODE_CONTINUOUS << MXC_F_TMR_CTRL_MODE_POS) /**< CTRL_MODE_CONTINUOUS Setting */ +#define MXC_V_TMR_CTRL_MODE_COUNTER ((uint32_t)0x2UL) /**< CTRL_MODE_COUNTER Value */ +#define MXC_S_TMR_CTRL_MODE_COUNTER (MXC_V_TMR_CTRL_MODE_COUNTER << MXC_F_TMR_CTRL_MODE_POS) /**< CTRL_MODE_COUNTER Setting */ +#define MXC_V_TMR_CTRL_MODE_PWM ((uint32_t)0x3UL) /**< CTRL_MODE_PWM Value */ +#define MXC_S_TMR_CTRL_MODE_PWM (MXC_V_TMR_CTRL_MODE_PWM << MXC_F_TMR_CTRL_MODE_POS) /**< CTRL_MODE_PWM Setting */ +#define MXC_V_TMR_CTRL_MODE_CAPTURE ((uint32_t)0x4UL) /**< CTRL_MODE_CAPTURE Value */ +#define MXC_S_TMR_CTRL_MODE_CAPTURE (MXC_V_TMR_CTRL_MODE_CAPTURE << MXC_F_TMR_CTRL_MODE_POS) /**< CTRL_MODE_CAPTURE Setting */ +#define MXC_V_TMR_CTRL_MODE_COMPARE ((uint32_t)0x5UL) /**< CTRL_MODE_COMPARE Value */ +#define MXC_S_TMR_CTRL_MODE_COMPARE (MXC_V_TMR_CTRL_MODE_COMPARE << MXC_F_TMR_CTRL_MODE_POS) /**< CTRL_MODE_COMPARE Setting */ +#define MXC_V_TMR_CTRL_MODE_GATED ((uint32_t)0x6UL) /**< CTRL_MODE_GATED Value */ +#define MXC_S_TMR_CTRL_MODE_GATED (MXC_V_TMR_CTRL_MODE_GATED << MXC_F_TMR_CTRL_MODE_POS) /**< CTRL_MODE_GATED Setting */ +#define MXC_V_TMR_CTRL_MODE_CAPTURECOMPARE ((uint32_t)0x7UL) /**< CTRL_MODE_CAPTURECOMPARE Value */ +#define MXC_S_TMR_CTRL_MODE_CAPTURECOMPARE (MXC_V_TMR_CTRL_MODE_CAPTURECOMPARE << MXC_F_TMR_CTRL_MODE_POS) /**< CTRL_MODE_CAPTURECOMPARE Setting */ + +#define MXC_F_TMR_CTRL_CLKDIV_POS 3 /**< CTRL_CLKDIV Position */ +#define MXC_F_TMR_CTRL_CLKDIV ((uint32_t)(0x7UL << MXC_F_TMR_CTRL_CLKDIV_POS)) /**< CTRL_CLKDIV Mask */ +#define MXC_V_TMR_CTRL_CLKDIV_DIV1 ((uint32_t)0x0UL) /**< CTRL_CLKDIV_DIV1 Value */ +#define MXC_S_TMR_CTRL_CLKDIV_DIV1 (MXC_V_TMR_CTRL_CLKDIV_DIV1 << MXC_F_TMR_CTRL_CLKDIV_POS) /**< CTRL_CLKDIV_DIV1 Setting */ +#define MXC_V_TMR_CTRL_CLKDIV_DIV2 ((uint32_t)0x1UL) /**< CTRL_CLKDIV_DIV2 Value */ +#define MXC_S_TMR_CTRL_CLKDIV_DIV2 (MXC_V_TMR_CTRL_CLKDIV_DIV2 << MXC_F_TMR_CTRL_CLKDIV_POS) /**< CTRL_CLKDIV_DIV2 Setting */ +#define MXC_V_TMR_CTRL_CLKDIV_DIV4 ((uint32_t)0x2UL) /**< CTRL_CLKDIV_DIV4 Value */ +#define MXC_S_TMR_CTRL_CLKDIV_DIV4 (MXC_V_TMR_CTRL_CLKDIV_DIV4 << MXC_F_TMR_CTRL_CLKDIV_POS) /**< CTRL_CLKDIV_DIV4 Setting */ +#define MXC_V_TMR_CTRL_CLKDIV_DIV8 ((uint32_t)0x3UL) /**< CTRL_CLKDIV_DIV8 Value */ +#define MXC_S_TMR_CTRL_CLKDIV_DIV8 (MXC_V_TMR_CTRL_CLKDIV_DIV8 << MXC_F_TMR_CTRL_CLKDIV_POS) /**< CTRL_CLKDIV_DIV8 Setting */ +#define MXC_V_TMR_CTRL_CLKDIV_DIV16 ((uint32_t)0x4UL) /**< CTRL_CLKDIV_DIV16 Value */ +#define MXC_S_TMR_CTRL_CLKDIV_DIV16 (MXC_V_TMR_CTRL_CLKDIV_DIV16 << MXC_F_TMR_CTRL_CLKDIV_POS) /**< CTRL_CLKDIV_DIV16 Setting */ +#define MXC_V_TMR_CTRL_CLKDIV_DIV32 ((uint32_t)0x5UL) /**< CTRL_CLKDIV_DIV32 Value */ +#define MXC_S_TMR_CTRL_CLKDIV_DIV32 (MXC_V_TMR_CTRL_CLKDIV_DIV32 << MXC_F_TMR_CTRL_CLKDIV_POS) /**< CTRL_CLKDIV_DIV32 Setting */ +#define MXC_V_TMR_CTRL_CLKDIV_DIV64 ((uint32_t)0x6UL) /**< CTRL_CLKDIV_DIV64 Value */ +#define MXC_S_TMR_CTRL_CLKDIV_DIV64 (MXC_V_TMR_CTRL_CLKDIV_DIV64 << MXC_F_TMR_CTRL_CLKDIV_POS) /**< CTRL_CLKDIV_DIV64 Setting */ +#define MXC_V_TMR_CTRL_CLKDIV_DIV128 ((uint32_t)0x7UL) /**< CTRL_CLKDIV_DIV128 Value */ +#define MXC_S_TMR_CTRL_CLKDIV_DIV128 (MXC_V_TMR_CTRL_CLKDIV_DIV128 << MXC_F_TMR_CTRL_CLKDIV_POS) /**< CTRL_CLKDIV_DIV128 Setting */ + +#define MXC_F_TMR_CTRL_POL_POS 6 /**< CTRL_POL Position */ +#define MXC_F_TMR_CTRL_POL ((uint32_t)(0x1UL << MXC_F_TMR_CTRL_POL_POS)) /**< CTRL_POL Mask */ + +#define MXC_F_TMR_CTRL_EN_POS 7 /**< CTRL_EN Position */ +#define MXC_F_TMR_CTRL_EN ((uint32_t)(0x1UL << MXC_F_TMR_CTRL_EN_POS)) /**< CTRL_EN Mask */ + +#define MXC_F_TMR_CTRL_CLKDIV3_POS 8 /**< CTRL_CLKDIV3 Position */ +#define MXC_F_TMR_CTRL_CLKDIV3 ((uint32_t)(0x1UL << MXC_F_TMR_CTRL_CLKDIV3_POS)) /**< CTRL_CLKDIV3 Mask */ + +#define MXC_F_TMR_CTRL_PWMSYNC_POS 9 /**< CTRL_PWMSYNC Position */ +#define MXC_F_TMR_CTRL_PWMSYNC ((uint32_t)(0x1UL << MXC_F_TMR_CTRL_PWMSYNC_POS)) /**< CTRL_PWMSYNC Mask */ + +#define MXC_F_TMR_CTRL_NOLHPOL_POS 10 /**< CTRL_NOLHPOL Position */ +#define MXC_F_TMR_CTRL_NOLHPOL ((uint32_t)(0x1UL << MXC_F_TMR_CTRL_NOLHPOL_POS)) /**< CTRL_NOLHPOL Mask */ + +#define MXC_F_TMR_CTRL_NOLLPOL_POS 11 /**< CTRL_NOLLPOL Position */ +#define MXC_F_TMR_CTRL_NOLLPOL ((uint32_t)(0x1UL << MXC_F_TMR_CTRL_NOLLPOL_POS)) /**< CTRL_NOLLPOL Mask */ + +#define MXC_F_TMR_CTRL_PWMCKBD_POS 12 /**< CTRL_PWMCKBD Position */ +#define MXC_F_TMR_CTRL_PWMCKBD ((uint32_t)(0x1UL << MXC_F_TMR_CTRL_PWMCKBD_POS)) /**< CTRL_PWMCKBD Mask */ + +/**@} end of group TMR_CTRL_Register */ + +/** + * @ingroup tmr_registers + * @defgroup TMR_NOLCMP TMR_NOLCMP + * @brief Timer Non-Overlapping Compare Register. + * @{ + */ +#define MXC_F_TMR_NOLCMP_LO_POS 0 /**< NOLCMP_LO Position */ +#define MXC_F_TMR_NOLCMP_LO ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_LO_POS)) /**< NOLCMP_LO Mask */ + +#define MXC_F_TMR_NOLCMP_HI_POS 8 /**< NOLCMP_HI Position */ +#define MXC_F_TMR_NOLCMP_HI ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_HI_POS)) /**< NOLCMP_HI Mask */ + +/**@} end of group TMR_NOLCMP_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_TMR_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trimsir_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trimsir_regs.h new file mode 100644 index 00000000000..ebbc38c19dc --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trimsir_regs.h @@ -0,0 +1,206 @@ +/** + * @file trimsir_regs.h + * @brief Registers, Bit Masks and Bit Positions for the TRIMSIR Peripheral Module. + * @note This file is @generated. + * @ingroup trimsir_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_TRIMSIR_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_TRIMSIR_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup trimsir + * @defgroup trimsir_registers TRIMSIR_Registers + * @brief Registers, Bit Masks and Bit Positions for the TRIMSIR Peripheral Module. + * @details Trim System Initilazation Registers + */ + +/** + * @ingroup trimsir_registers + * Structure type to access the TRIMSIR Registers. + */ +typedef struct { + __R uint32_t rsv_0x0_0x7[2]; + __IO uint32_t rtc; /**< \b 0x08: TRIMSIR RTC Register */ + __R uint32_t rsv_0xc_0x33[10]; + __I uint32_t simo; /**< \b 0x34: TRIMSIR SIMO Register */ + __R uint32_t rsv_0x38; + __I uint32_t ipolo; /**< \b 0x3C: TRIMSIR IPOLO Register */ + __IO uint32_t ctrl; /**< \b 0x40: TRIMSIR CTRL Register */ + __IO uint32_t inro; /**< \b 0x44: TRIMSIR INRO Register */ +} mxc_trimsir_regs_t; + +/* Register offsets for module TRIMSIR */ +/** + * @ingroup trimsir_registers + * @defgroup TRIMSIR_Register_Offsets Register Offsets + * @brief TRIMSIR Peripheral Register Offsets from the TRIMSIR Base Peripheral Address. + * @{ + */ +#define MXC_R_TRIMSIR_RTC ((uint32_t)0x00000008UL) /**< Offset from TRIMSIR Base Address: 0x0008 */ +#define MXC_R_TRIMSIR_SIMO ((uint32_t)0x00000034UL) /**< Offset from TRIMSIR Base Address: 0x0034 */ +#define MXC_R_TRIMSIR_IPOLO ((uint32_t)0x0000003CUL) /**< Offset from TRIMSIR Base Address: 0x003C */ +#define MXC_R_TRIMSIR_CTRL ((uint32_t)0x00000040UL) /**< Offset from TRIMSIR Base Address: 0x0040 */ +#define MXC_R_TRIMSIR_INRO ((uint32_t)0x00000044UL) /**< Offset from TRIMSIR Base Address: 0x0044 */ +/**@} end of group trimsir_registers */ + +/** + * @ingroup trimsir_registers + * @defgroup TRIMSIR_RTC TRIMSIR_RTC + * @brief RTC Trim System Initialization Register. + * @{ + */ +#define MXC_F_TRIMSIR_RTC_X1TRIM_POS 16 /**< RTC_X1TRIM Position */ +#define MXC_F_TRIMSIR_RTC_X1TRIM ((uint32_t)(0x1FUL << MXC_F_TRIMSIR_RTC_X1TRIM_POS)) /**< RTC_X1TRIM Mask */ + +#define MXC_F_TRIMSIR_RTC_X2TRIM_POS 21 /**< RTC_X2TRIM Position */ +#define MXC_F_TRIMSIR_RTC_X2TRIM ((uint32_t)(0x1FUL << MXC_F_TRIMSIR_RTC_X2TRIM_POS)) /**< RTC_X2TRIM Mask */ + +#define MXC_F_TRIMSIR_RTC_LOCK_POS 31 /**< RTC_LOCK Position */ +#define MXC_F_TRIMSIR_RTC_LOCK ((uint32_t)(0x1UL << MXC_F_TRIMSIR_RTC_LOCK_POS)) /**< RTC_LOCK Mask */ + +/**@} end of group TRIMSIR_RTC_Register */ + +/** + * @ingroup trimsir_registers + * @defgroup TRIMSIR_SIMO TRIMSIR_SIMO + * @brief SIMO Trim System Initialization Register. + * @{ + */ +#define MXC_F_TRIMSIR_SIMO_CLKDIV_POS 0 /**< SIMO_CLKDIV Position */ +#define MXC_F_TRIMSIR_SIMO_CLKDIV ((uint32_t)(0x7UL << MXC_F_TRIMSIR_SIMO_CLKDIV_POS)) /**< SIMO_CLKDIV Mask */ +#define MXC_V_TRIMSIR_SIMO_CLKDIV_DIV1 ((uint32_t)0x0UL) /**< SIMO_CLKDIV_DIV1 Value */ +#define MXC_S_TRIMSIR_SIMO_CLKDIV_DIV1 (MXC_V_TRIMSIR_SIMO_CLKDIV_DIV1 << MXC_F_TRIMSIR_SIMO_CLKDIV_POS) /**< SIMO_CLKDIV_DIV1 Setting */ +#define MXC_V_TRIMSIR_SIMO_CLKDIV_DIV16 ((uint32_t)0x1UL) /**< SIMO_CLKDIV_DIV16 Value */ +#define MXC_S_TRIMSIR_SIMO_CLKDIV_DIV16 (MXC_V_TRIMSIR_SIMO_CLKDIV_DIV16 << MXC_F_TRIMSIR_SIMO_CLKDIV_POS) /**< SIMO_CLKDIV_DIV16 Setting */ +#define MXC_V_TRIMSIR_SIMO_CLKDIV_DIV32 ((uint32_t)0x3UL) /**< SIMO_CLKDIV_DIV32 Value */ +#define MXC_S_TRIMSIR_SIMO_CLKDIV_DIV32 (MXC_V_TRIMSIR_SIMO_CLKDIV_DIV32 << MXC_F_TRIMSIR_SIMO_CLKDIV_POS) /**< SIMO_CLKDIV_DIV32 Setting */ +#define MXC_V_TRIMSIR_SIMO_CLKDIV_DIV64 ((uint32_t)0x5UL) /**< SIMO_CLKDIV_DIV64 Value */ +#define MXC_S_TRIMSIR_SIMO_CLKDIV_DIV64 (MXC_V_TRIMSIR_SIMO_CLKDIV_DIV64 << MXC_F_TRIMSIR_SIMO_CLKDIV_POS) /**< SIMO_CLKDIV_DIV64 Setting */ +#define MXC_V_TRIMSIR_SIMO_CLKDIV_DIV128 ((uint32_t)0x7UL) /**< SIMO_CLKDIV_DIV128 Value */ +#define MXC_S_TRIMSIR_SIMO_CLKDIV_DIV128 (MXC_V_TRIMSIR_SIMO_CLKDIV_DIV128 << MXC_F_TRIMSIR_SIMO_CLKDIV_POS) /**< SIMO_CLKDIV_DIV128 Setting */ + +/**@} end of group TRIMSIR_SIMO_Register */ + +/** + * @ingroup trimsir_registers + * @defgroup TRIMSIR_IPOLO TRIMSIR_IPOLO + * @brief IPO Low Trim System Initialization Register. + * @{ + */ +#define MXC_F_TRIMSIR_IPOLO_IPO_LIMITLO_POS 0 /**< IPOLO_IPO_LIMITLO Position */ +#define MXC_F_TRIMSIR_IPOLO_IPO_LIMITLO ((uint32_t)(0xFFUL << MXC_F_TRIMSIR_IPOLO_IPO_LIMITLO_POS)) /**< IPOLO_IPO_LIMITLO Mask */ + +/**@} end of group TRIMSIR_IPOLO_Register */ + +/** + * @ingroup trimsir_registers + * @defgroup TRIMSIR_CTRL TRIMSIR_CTRL + * @brief Control Trim System Initialization Register. + * @{ + */ +#define MXC_F_TRIMSIR_CTRL_VDDA_LIMITLO_POS 0 /**< CTRL_VDDA_LIMITLO Position */ +#define MXC_F_TRIMSIR_CTRL_VDDA_LIMITLO ((uint32_t)(0x7FUL << MXC_F_TRIMSIR_CTRL_VDDA_LIMITLO_POS)) /**< CTRL_VDDA_LIMITLO Mask */ + +#define MXC_F_TRIMSIR_CTRL_VDDA_LIMITHI_POS 8 /**< CTRL_VDDA_LIMITHI Position */ +#define MXC_F_TRIMSIR_CTRL_VDDA_LIMITHI ((uint32_t)(0x7FUL << MXC_F_TRIMSIR_CTRL_VDDA_LIMITHI_POS)) /**< CTRL_VDDA_LIMITHI Mask */ + +#define MXC_F_TRIMSIR_CTRL_IPO_LIMITHI_POS 15 /**< CTRL_IPO_LIMITHI Position */ +#define MXC_F_TRIMSIR_CTRL_IPO_LIMITHI ((uint32_t)(0x1FFUL << MXC_F_TRIMSIR_CTRL_IPO_LIMITHI_POS)) /**< CTRL_IPO_LIMITHI Mask */ + +#define MXC_F_TRIMSIR_CTRL_INRO_SEL_POS 24 /**< CTRL_INRO_SEL Position */ +#define MXC_F_TRIMSIR_CTRL_INRO_SEL ((uint32_t)(0x3UL << MXC_F_TRIMSIR_CTRL_INRO_SEL_POS)) /**< CTRL_INRO_SEL Mask */ +#define MXC_V_TRIMSIR_CTRL_INRO_SEL_8KHZ ((uint32_t)0x0UL) /**< CTRL_INRO_SEL_8KHZ Value */ +#define MXC_S_TRIMSIR_CTRL_INRO_SEL_8KHZ (MXC_V_TRIMSIR_CTRL_INRO_SEL_8KHZ << MXC_F_TRIMSIR_CTRL_INRO_SEL_POS) /**< CTRL_INRO_SEL_8KHZ Setting */ +#define MXC_V_TRIMSIR_CTRL_INRO_SEL_16KHZ ((uint32_t)0x1UL) /**< CTRL_INRO_SEL_16KHZ Value */ +#define MXC_S_TRIMSIR_CTRL_INRO_SEL_16KHZ (MXC_V_TRIMSIR_CTRL_INRO_SEL_16KHZ << MXC_F_TRIMSIR_CTRL_INRO_SEL_POS) /**< CTRL_INRO_SEL_16KHZ Setting */ +#define MXC_V_TRIMSIR_CTRL_INRO_SEL_30KHZ ((uint32_t)0x2UL) /**< CTRL_INRO_SEL_30KHZ Value */ +#define MXC_S_TRIMSIR_CTRL_INRO_SEL_30KHZ (MXC_V_TRIMSIR_CTRL_INRO_SEL_30KHZ << MXC_F_TRIMSIR_CTRL_INRO_SEL_POS) /**< CTRL_INRO_SEL_30KHZ Setting */ + +#define MXC_F_TRIMSIR_CTRL_INRO_TRIM_POS 29 /**< CTRL_INRO_TRIM Position */ +#define MXC_F_TRIMSIR_CTRL_INRO_TRIM ((uint32_t)(0x7UL << MXC_F_TRIMSIR_CTRL_INRO_TRIM_POS)) /**< CTRL_INRO_TRIM Mask */ + +/**@} end of group TRIMSIR_CTRL_Register */ + +/** + * @ingroup trimsir_registers + * @defgroup TRIMSIR_INRO TRIMSIR_INRO + * @brief RTC Trim System Initialization Register. + * @{ + */ +#define MXC_F_TRIMSIR_INRO_TRIM16K_POS 0 /**< INRO_TRIM16K Position */ +#define MXC_F_TRIMSIR_INRO_TRIM16K ((uint32_t)(0x7UL << MXC_F_TRIMSIR_INRO_TRIM16K_POS)) /**< INRO_TRIM16K Mask */ + +#define MXC_F_TRIMSIR_INRO_TRIM30K_POS 3 /**< INRO_TRIM30K Position */ +#define MXC_F_TRIMSIR_INRO_TRIM30K ((uint32_t)(0x7UL << MXC_F_TRIMSIR_INRO_TRIM30K_POS)) /**< INRO_TRIM30K Mask */ + +#define MXC_F_TRIMSIR_INRO_LPCLKSEL_POS 6 /**< INRO_LPCLKSEL Position */ +#define MXC_F_TRIMSIR_INRO_LPCLKSEL ((uint32_t)(0x3UL << MXC_F_TRIMSIR_INRO_LPCLKSEL_POS)) /**< INRO_LPCLKSEL Mask */ +#define MXC_V_TRIMSIR_INRO_LPCLKSEL_8KHZ ((uint32_t)0x0UL) /**< INRO_LPCLKSEL_8KHZ Value */ +#define MXC_S_TRIMSIR_INRO_LPCLKSEL_8KHZ (MXC_V_TRIMSIR_INRO_LPCLKSEL_8KHZ << MXC_F_TRIMSIR_INRO_LPCLKSEL_POS) /**< INRO_LPCLKSEL_8KHZ Setting */ +#define MXC_V_TRIMSIR_INRO_LPCLKSEL_16KHZ ((uint32_t)0x1UL) /**< INRO_LPCLKSEL_16KHZ Value */ +#define MXC_S_TRIMSIR_INRO_LPCLKSEL_16KHZ (MXC_V_TRIMSIR_INRO_LPCLKSEL_16KHZ << MXC_F_TRIMSIR_INRO_LPCLKSEL_POS) /**< INRO_LPCLKSEL_16KHZ Setting */ +#define MXC_V_TRIMSIR_INRO_LPCLKSEL_30KHZ ((uint32_t)0x2UL) /**< INRO_LPCLKSEL_30KHZ Value */ +#define MXC_S_TRIMSIR_INRO_LPCLKSEL_30KHZ (MXC_V_TRIMSIR_INRO_LPCLKSEL_30KHZ << MXC_F_TRIMSIR_INRO_LPCLKSEL_POS) /**< INRO_LPCLKSEL_30KHZ Setting */ + +/**@} end of group TRIMSIR_INRO_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_TRIMSIR_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trng_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trng_regs.h new file mode 100644 index 00000000000..ae81696390d --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trng_regs.h @@ -0,0 +1,267 @@ +/** + * @file trng_regs.h + * @brief Registers, Bit Masks and Bit Positions for the TRNG Peripheral Module. + * @note This file is @generated. + * @ingroup trng_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_TRNG_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_TRNG_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup trng + * @defgroup trng_registers TRNG_Registers + * @brief Registers, Bit Masks and Bit Positions for the TRNG Peripheral Module. + * @details Random Number Generator. + */ + +/** + * @ingroup trng_registers + * Structure type to access the TRNG Registers. + */ +typedef struct { + __IO uint32_t ctrl; /**< \b 0x00: TRNG CTRL Register */ + __IO uint32_t status; /**< \b 0x04: TRNG STATUS Register */ + __I uint32_t data; /**< \b 0x08: TRNG DATA Register */ + __R uint32_t rsv_0xc_0x37[11]; + __IO uint32_t data_nist; /**< \b 0x38: TRNG DATA_NIST Register */ +} mxc_trng_regs_t; + +/* Register offsets for module TRNG */ +/** + * @ingroup trng_registers + * @defgroup TRNG_Register_Offsets Register Offsets + * @brief TRNG Peripheral Register Offsets from the TRNG Base Peripheral Address. + * @{ + */ +#define MXC_R_TRNG_CTRL ((uint32_t)0x00000000UL) /**< Offset from TRNG Base Address: 0x0000 */ +#define MXC_R_TRNG_STATUS ((uint32_t)0x00000004UL) /**< Offset from TRNG Base Address: 0x0004 */ +#define MXC_R_TRNG_DATA ((uint32_t)0x00000008UL) /**< Offset from TRNG Base Address: 0x0008 */ +#define MXC_R_TRNG_DATA_NIST ((uint32_t)0x00000038UL) /**< Offset from TRNG Base Address: 0x0038 */ +/**@} end of group trng_registers */ + +/** + * @ingroup trng_registers + * @defgroup TRNG_CTRL TRNG_CTRL + * @brief TRNG Control Register. + * @{ + */ +#define MXC_F_TRNG_CTRL_OD_HEALTH_POS 0 /**< CTRL_OD_HEALTH Position */ +#define MXC_F_TRNG_CTRL_OD_HEALTH ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_OD_HEALTH_POS)) /**< CTRL_OD_HEALTH Mask */ + +#define MXC_F_TRNG_CTRL_RND_IE_POS 1 /**< CTRL_RND_IE Position */ +#define MXC_F_TRNG_CTRL_RND_IE ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_RND_IE_POS)) /**< CTRL_RND_IE Mask */ + +#define MXC_F_TRNG_CTRL_HEALTH_IE_POS 2 /**< CTRL_HEALTH_IE Position */ +#define MXC_F_TRNG_CTRL_HEALTH_IE ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_HEALTH_IE_POS)) /**< CTRL_HEALTH_IE Mask */ + +#define MXC_F_TRNG_CTRL_AESKG_MEU_POS 3 /**< CTRL_AESKG_MEU Position */ +#define MXC_F_TRNG_CTRL_AESKG_MEU ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_AESKG_MEU_POS)) /**< CTRL_AESKG_MEU Mask */ + +#define MXC_F_TRNG_CTRL_AESKG_MEMPROT_XIP_POS 4 /**< CTRL_AESKG_MEMPROT_XIP Position */ +#define MXC_F_TRNG_CTRL_AESKG_MEMPROT_XIP ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_AESKG_MEMPROT_XIP_POS)) /**< CTRL_AESKG_MEMPROT_XIP Mask */ + +#define MXC_F_TRNG_CTRL_AESKG_MEMPROT_DIP_POS 5 /**< CTRL_AESKG_MEMPROT_DIP Position */ +#define MXC_F_TRNG_CTRL_AESKG_MEMPROT_DIP ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_AESKG_MEMPROT_DIP_POS)) /**< CTRL_AESKG_MEMPROT_DIP Mask */ + +#define MXC_F_TRNG_CTRL_OD_ROMON_POS 6 /**< CTRL_OD_ROMON Position */ +#define MXC_F_TRNG_CTRL_OD_ROMON ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_OD_ROMON_POS)) /**< CTRL_OD_ROMON Mask */ + +#define MXC_F_TRNG_CTRL_OD_EE_POS 7 /**< CTRL_OD_EE Position */ +#define MXC_F_TRNG_CTRL_OD_EE ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_OD_EE_POS)) /**< CTRL_OD_EE Mask */ + +#define MXC_F_TRNG_CTRL_ROMON_EE_FOE_POS 8 /**< CTRL_ROMON_EE_FOE Position */ +#define MXC_F_TRNG_CTRL_ROMON_EE_FOE ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_ROMON_EE_FOE_POS)) /**< CTRL_ROMON_EE_FOE Mask */ + +#define MXC_F_TRNG_CTRL_ROMON_EE_FOD_POS 9 /**< CTRL_ROMON_EE_FOD Position */ +#define MXC_F_TRNG_CTRL_ROMON_EE_FOD ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_ROMON_EE_FOD_POS)) /**< CTRL_ROMON_EE_FOD Mask */ + +#define MXC_F_TRNG_CTRL_EBLS_POS 10 /**< CTRL_EBLS Position */ +#define MXC_F_TRNG_CTRL_EBLS ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_EBLS_POS)) /**< CTRL_EBLS Mask */ + +#define MXC_F_TRNG_CTRL_KEYWIPE_POS 15 /**< CTRL_KEYWIPE Position */ +#define MXC_F_TRNG_CTRL_KEYWIPE ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_KEYWIPE_POS)) /**< CTRL_KEYWIPE Mask */ + +#define MXC_F_TRNG_CTRL_GET_TERO_CNT_POS 16 /**< CTRL_GET_TERO_CNT Position */ +#define MXC_F_TRNG_CTRL_GET_TERO_CNT ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_GET_TERO_CNT_POS)) /**< CTRL_GET_TERO_CNT Mask */ + +#define MXC_F_TRNG_CTRL_EE_DONE_IE_POS 23 /**< CTRL_EE_DONE_IE Position */ +#define MXC_F_TRNG_CTRL_EE_DONE_IE ((uint32_t)(0x1UL << MXC_F_TRNG_CTRL_EE_DONE_IE_POS)) /**< CTRL_EE_DONE_IE Mask */ + +#define MXC_F_TRNG_CTRL_ROMON_DIS_POS 24 /**< CTRL_ROMON_DIS Position */ +#define MXC_F_TRNG_CTRL_ROMON_DIS ((uint32_t)(0x7UL << MXC_F_TRNG_CTRL_ROMON_DIS_POS)) /**< CTRL_ROMON_DIS Mask */ +#define MXC_V_TRNG_CTRL_ROMON_DIS_RO_0 ((uint32_t)0x1UL) /**< CTRL_ROMON_DIS_RO_0 Value */ +#define MXC_S_TRNG_CTRL_ROMON_DIS_RO_0 (MXC_V_TRNG_CTRL_ROMON_DIS_RO_0 << MXC_F_TRNG_CTRL_ROMON_DIS_POS) /**< CTRL_ROMON_DIS_RO_0 Setting */ +#define MXC_V_TRNG_CTRL_ROMON_DIS_RO_1 ((uint32_t)0x2UL) /**< CTRL_ROMON_DIS_RO_1 Value */ +#define MXC_S_TRNG_CTRL_ROMON_DIS_RO_1 (MXC_V_TRNG_CTRL_ROMON_DIS_RO_1 << MXC_F_TRNG_CTRL_ROMON_DIS_POS) /**< CTRL_ROMON_DIS_RO_1 Setting */ +#define MXC_V_TRNG_CTRL_ROMON_DIS_RO_2 ((uint32_t)0x4UL) /**< CTRL_ROMON_DIS_RO_2 Value */ +#define MXC_S_TRNG_CTRL_ROMON_DIS_RO_2 (MXC_V_TRNG_CTRL_ROMON_DIS_RO_2 << MXC_F_TRNG_CTRL_ROMON_DIS_POS) /**< CTRL_ROMON_DIS_RO_2 Setting */ + +#define MXC_F_TRNG_CTRL_ROMON_DIV2_POS 28 /**< CTRL_ROMON_DIV2 Position */ +#define MXC_F_TRNG_CTRL_ROMON_DIV2 ((uint32_t)(0x7UL << MXC_F_TRNG_CTRL_ROMON_DIV2_POS)) /**< CTRL_ROMON_DIV2 Mask */ +#define MXC_V_TRNG_CTRL_ROMON_DIV2_RO_0 ((uint32_t)0x0UL) /**< CTRL_ROMON_DIV2_RO_0 Value */ +#define MXC_S_TRNG_CTRL_ROMON_DIV2_RO_0 (MXC_V_TRNG_CTRL_ROMON_DIV2_RO_0 << MXC_F_TRNG_CTRL_ROMON_DIV2_POS) /**< CTRL_ROMON_DIV2_RO_0 Setting */ +#define MXC_V_TRNG_CTRL_ROMON_DIV2_RO_1 ((uint32_t)0x1UL) /**< CTRL_ROMON_DIV2_RO_1 Value */ +#define MXC_S_TRNG_CTRL_ROMON_DIV2_RO_1 (MXC_V_TRNG_CTRL_ROMON_DIV2_RO_1 << MXC_F_TRNG_CTRL_ROMON_DIV2_POS) /**< CTRL_ROMON_DIV2_RO_1 Setting */ +#define MXC_V_TRNG_CTRL_ROMON_DIV2_RO_2 ((uint32_t)0x2UL) /**< CTRL_ROMON_DIV2_RO_2 Value */ +#define MXC_S_TRNG_CTRL_ROMON_DIV2_RO_2 (MXC_V_TRNG_CTRL_ROMON_DIV2_RO_2 << MXC_F_TRNG_CTRL_ROMON_DIV2_POS) /**< CTRL_ROMON_DIV2_RO_2 Setting */ + +/**@} end of group TRNG_CTRL_Register */ + +/** + * @ingroup trng_registers + * @defgroup TRNG_STATUS TRNG_STATUS + * @brief Data. The content of this register is valid only when RNG_IS = 1. When TRNG is + * disabled, read returns 0x0000 0000. + * @{ + */ +#define MXC_F_TRNG_STATUS_RDY_POS 0 /**< STATUS_RDY Position */ +#define MXC_F_TRNG_STATUS_RDY ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_RDY_POS)) /**< STATUS_RDY Mask */ + +#define MXC_F_TRNG_STATUS_OD_HEALTH_POS 1 /**< STATUS_OD_HEALTH Position */ +#define MXC_F_TRNG_STATUS_OD_HEALTH ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_OD_HEALTH_POS)) /**< STATUS_OD_HEALTH Mask */ + +#define MXC_F_TRNG_STATUS_HEALTH_POS 2 /**< STATUS_HEALTH Position */ +#define MXC_F_TRNG_STATUS_HEALTH ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_HEALTH_POS)) /**< STATUS_HEALTH Mask */ + +#define MXC_F_TRNG_STATUS_SRCFAIL_POS 3 /**< STATUS_SRCFAIL Position */ +#define MXC_F_TRNG_STATUS_SRCFAIL ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_SRCFAIL_POS)) /**< STATUS_SRCFAIL Mask */ + +#define MXC_F_TRNG_STATUS_AES_KEYGEN_POS 4 /**< STATUS_AES_KEYGEN Position */ +#define MXC_F_TRNG_STATUS_AES_KEYGEN ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_AES_KEYGEN_POS)) /**< STATUS_AES_KEYGEN Mask */ + +#define MXC_F_TRNG_STATUS_OD_ROMON_POS 6 /**< STATUS_OD_ROMON Position */ +#define MXC_F_TRNG_STATUS_OD_ROMON ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_OD_ROMON_POS)) /**< STATUS_OD_ROMON Mask */ + +#define MXC_F_TRNG_STATUS_OD_EE_POS 7 /**< STATUS_OD_EE Position */ +#define MXC_F_TRNG_STATUS_OD_EE ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_OD_EE_POS)) /**< STATUS_OD_EE Mask */ + +#define MXC_F_TRNG_STATUS_PP_ERR_POS 8 /**< STATUS_PP_ERR Position */ +#define MXC_F_TRNG_STATUS_PP_ERR ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_PP_ERR_POS)) /**< STATUS_PP_ERR Mask */ + +#define MXC_F_TRNG_STATUS_ROMON_0_ERR_POS 9 /**< STATUS_ROMON_0_ERR Position */ +#define MXC_F_TRNG_STATUS_ROMON_0_ERR ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_ROMON_0_ERR_POS)) /**< STATUS_ROMON_0_ERR Mask */ + +#define MXC_F_TRNG_STATUS_ROMON_1_ERR_POS 10 /**< STATUS_ROMON_1_ERR Position */ +#define MXC_F_TRNG_STATUS_ROMON_1_ERR ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_ROMON_1_ERR_POS)) /**< STATUS_ROMON_1_ERR Mask */ + +#define MXC_F_TRNG_STATUS_ROMON_2_ERR_POS 11 /**< STATUS_ROMON_2_ERR Position */ +#define MXC_F_TRNG_STATUS_ROMON_2_ERR ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_ROMON_2_ERR_POS)) /**< STATUS_ROMON_2_ERR Mask */ + +#define MXC_F_TRNG_STATUS_EE_ERR_THR_POS 12 /**< STATUS_EE_ERR_THR Position */ +#define MXC_F_TRNG_STATUS_EE_ERR_THR ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_EE_ERR_THR_POS)) /**< STATUS_EE_ERR_THR Mask */ + +#define MXC_F_TRNG_STATUS_EE_ERR_OOB_POS 13 /**< STATUS_EE_ERR_OOB Position */ +#define MXC_F_TRNG_STATUS_EE_ERR_OOB ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_EE_ERR_OOB_POS)) /**< STATUS_EE_ERR_OOB Mask */ + +#define MXC_F_TRNG_STATUS_EE_ERR_LOCK_POS 14 /**< STATUS_EE_ERR_LOCK Position */ +#define MXC_F_TRNG_STATUS_EE_ERR_LOCK ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_EE_ERR_LOCK_POS)) /**< STATUS_EE_ERR_LOCK Mask */ + +#define MXC_F_TRNG_STATUS_TERO_CNT_RDY_POS 16 /**< STATUS_TERO_CNT_RDY Position */ +#define MXC_F_TRNG_STATUS_TERO_CNT_RDY ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_TERO_CNT_RDY_POS)) /**< STATUS_TERO_CNT_RDY Mask */ + +#define MXC_F_TRNG_STATUS_RC_ERR_POS 17 /**< STATUS_RC_ERR Position */ +#define MXC_F_TRNG_STATUS_RC_ERR ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_RC_ERR_POS)) /**< STATUS_RC_ERR Mask */ + +#define MXC_F_TRNG_STATUS_AP_ERR_POS 18 /**< STATUS_AP_ERR Position */ +#define MXC_F_TRNG_STATUS_AP_ERR ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_AP_ERR_POS)) /**< STATUS_AP_ERR Mask */ + +#define MXC_F_TRNG_STATUS_DATA_DONE_POS 19 /**< STATUS_DATA_DONE Position */ +#define MXC_F_TRNG_STATUS_DATA_DONE ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_DATA_DONE_POS)) /**< STATUS_DATA_DONE Mask */ + +#define MXC_F_TRNG_STATUS_DATA_NIST_DONE_POS 20 /**< STATUS_DATA_NIST_DONE Position */ +#define MXC_F_TRNG_STATUS_DATA_NIST_DONE ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_DATA_NIST_DONE_POS)) /**< STATUS_DATA_NIST_DONE Mask */ + +#define MXC_F_TRNG_STATUS_HEALTH_DONE_POS 21 /**< STATUS_HEALTH_DONE Position */ +#define MXC_F_TRNG_STATUS_HEALTH_DONE ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_HEALTH_DONE_POS)) /**< STATUS_HEALTH_DONE Mask */ + +#define MXC_F_TRNG_STATUS_ROMON_DONE_POS 22 /**< STATUS_ROMON_DONE Position */ +#define MXC_F_TRNG_STATUS_ROMON_DONE ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_ROMON_DONE_POS)) /**< STATUS_ROMON_DONE Mask */ + +#define MXC_F_TRNG_STATUS_EE_DONE_POS 23 /**< STATUS_EE_DONE Position */ +#define MXC_F_TRNG_STATUS_EE_DONE ((uint32_t)(0x1UL << MXC_F_TRNG_STATUS_EE_DONE_POS)) /**< STATUS_EE_DONE Mask */ + +/**@} end of group TRNG_STATUS_Register */ + +/** + * @ingroup trng_registers + * @defgroup TRNG_DATA TRNG_DATA + * @brief Data. The content of this register is valid only when RNG_IS = 1. When TRNG is + * disabled, read returns 0x0000 0000. + * @{ + */ +#define MXC_F_TRNG_DATA_DATA_POS 0 /**< DATA_DATA Position */ +#define MXC_F_TRNG_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_TRNG_DATA_DATA_POS)) /**< DATA_DATA Mask */ + +/**@} end of group TRNG_DATA_Register */ + +/** + * @ingroup trng_registers + * @defgroup TRNG_DATA_NIST TRNG_DATA_NIST + * @brief Data NIST Register. + * @{ + */ +#define MXC_F_TRNG_DATA_NIST_DATA_POS 0 /**< DATA_NIST_DATA Position */ +#define MXC_F_TRNG_DATA_NIST_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_TRNG_DATA_NIST_DATA_POS)) /**< DATA_NIST_DATA Mask */ + +/**@} end of group TRNG_DATA_NIST_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_TRNG_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/uart_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/uart_regs.h new file mode 100644 index 00000000000..b2d9d1c0114 --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/uart_regs.h @@ -0,0 +1,397 @@ +/** + * @file uart_regs.h + * @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module. + * @note This file is @generated. + * @ingroup uart_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_UART_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_UART_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup uart + * @defgroup uart_registers UART_Registers + * @brief Registers, Bit Masks and Bit Positions for the UART Peripheral Module. + * @details UART Low Power Registers + */ + +/** + * @ingroup uart_registers + * Structure type to access the UART Registers. + */ +typedef struct { + __IO uint32_t ctrl; /**< \b 0x0000: UART CTRL Register */ + __I uint32_t status; /**< \b 0x0004: UART STATUS Register */ + __IO uint32_t inten; /**< \b 0x0008: UART INTEN Register */ + __IO uint32_t intfl; /**< \b 0x000C: UART INTFL Register */ + __IO uint32_t clkdiv; /**< \b 0x0010: UART CLKDIV Register */ + __IO uint32_t osr; /**< \b 0x0014: UART OSR Register */ + __IO uint32_t txpeek; /**< \b 0x0018: UART TXPEEK Register */ + __IO uint32_t pin; /**< \b 0x001C: UART PIN Register */ + __IO uint32_t fifo; /**< \b 0x0020: UART FIFO Register */ + __R uint32_t rsv_0x24_0x2f[3]; + __IO uint32_t dma; /**< \b 0x0030: UART DMA Register */ + __IO uint32_t wken; /**< \b 0x0034: UART WKEN Register */ + __IO uint32_t wkfl; /**< \b 0x0038: UART WKFL Register */ +} mxc_uart_regs_t; + +/* Register offsets for module UART */ +/** + * @ingroup uart_registers + * @defgroup UART_Register_Offsets Register Offsets + * @brief UART Peripheral Register Offsets from the UART Base Peripheral Address. + * @{ + */ +#define MXC_R_UART_CTRL ((uint32_t)0x00000000UL) /**< Offset from UART Base Address: 0x0000 */ +#define MXC_R_UART_STATUS ((uint32_t)0x00000004UL) /**< Offset from UART Base Address: 0x0004 */ +#define MXC_R_UART_INTEN ((uint32_t)0x00000008UL) /**< Offset from UART Base Address: 0x0008 */ +#define MXC_R_UART_INTFL ((uint32_t)0x0000000CUL) /**< Offset from UART Base Address: 0x000C */ +#define MXC_R_UART_CLKDIV ((uint32_t)0x00000010UL) /**< Offset from UART Base Address: 0x0010 */ +#define MXC_R_UART_OSR ((uint32_t)0x00000014UL) /**< Offset from UART Base Address: 0x0014 */ +#define MXC_R_UART_TXPEEK ((uint32_t)0x00000018UL) /**< Offset from UART Base Address: 0x0018 */ +#define MXC_R_UART_PIN ((uint32_t)0x0000001CUL) /**< Offset from UART Base Address: 0x001C */ +#define MXC_R_UART_FIFO ((uint32_t)0x00000020UL) /**< Offset from UART Base Address: 0x0020 */ +#define MXC_R_UART_DMA ((uint32_t)0x00000030UL) /**< Offset from UART Base Address: 0x0030 */ +#define MXC_R_UART_WKEN ((uint32_t)0x00000034UL) /**< Offset from UART Base Address: 0x0034 */ +#define MXC_R_UART_WKFL ((uint32_t)0x00000038UL) /**< Offset from UART Base Address: 0x0038 */ +/**@} end of group uart_registers */ + +/** + * @ingroup uart_registers + * @defgroup UART_CTRL UART_CTRL + * @brief Control register + * @{ + */ +#define MXC_F_UART_CTRL_RX_THD_VAL_POS 0 /**< CTRL_RX_THD_VAL Position */ +#define MXC_F_UART_CTRL_RX_THD_VAL ((uint32_t)(0xFUL << MXC_F_UART_CTRL_RX_THD_VAL_POS)) /**< CTRL_RX_THD_VAL Mask */ + +#define MXC_F_UART_CTRL_PAR_EN_POS 4 /**< CTRL_PAR_EN Position */ +#define MXC_F_UART_CTRL_PAR_EN ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PAR_EN_POS)) /**< CTRL_PAR_EN Mask */ + +#define MXC_F_UART_CTRL_PAR_EO_POS 5 /**< CTRL_PAR_EO Position */ +#define MXC_F_UART_CTRL_PAR_EO ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PAR_EO_POS)) /**< CTRL_PAR_EO Mask */ + +#define MXC_F_UART_CTRL_PAR_MD_POS 6 /**< CTRL_PAR_MD Position */ +#define MXC_F_UART_CTRL_PAR_MD ((uint32_t)(0x1UL << MXC_F_UART_CTRL_PAR_MD_POS)) /**< CTRL_PAR_MD Mask */ + +#define MXC_F_UART_CTRL_CTS_DIS_POS 7 /**< CTRL_CTS_DIS Position */ +#define MXC_F_UART_CTRL_CTS_DIS ((uint32_t)(0x1UL << MXC_F_UART_CTRL_CTS_DIS_POS)) /**< CTRL_CTS_DIS Mask */ + +#define MXC_F_UART_CTRL_TX_FLUSH_POS 8 /**< CTRL_TX_FLUSH Position */ +#define MXC_F_UART_CTRL_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL_TX_FLUSH_POS)) /**< CTRL_TX_FLUSH Mask */ + +#define MXC_F_UART_CTRL_RX_FLUSH_POS 9 /**< CTRL_RX_FLUSH Position */ +#define MXC_F_UART_CTRL_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_UART_CTRL_RX_FLUSH_POS)) /**< CTRL_RX_FLUSH Mask */ + +#define MXC_F_UART_CTRL_CHAR_SIZE_POS 10 /**< CTRL_CHAR_SIZE Position */ +#define MXC_F_UART_CTRL_CHAR_SIZE ((uint32_t)(0x3UL << MXC_F_UART_CTRL_CHAR_SIZE_POS)) /**< CTRL_CHAR_SIZE Mask */ +#define MXC_V_UART_CTRL_CHAR_SIZE_5BITS ((uint32_t)0x0UL) /**< CTRL_CHAR_SIZE_5BITS Value */ +#define MXC_S_UART_CTRL_CHAR_SIZE_5BITS (MXC_V_UART_CTRL_CHAR_SIZE_5BITS << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_5BITS Setting */ +#define MXC_V_UART_CTRL_CHAR_SIZE_6BITS ((uint32_t)0x1UL) /**< CTRL_CHAR_SIZE_6BITS Value */ +#define MXC_S_UART_CTRL_CHAR_SIZE_6BITS (MXC_V_UART_CTRL_CHAR_SIZE_6BITS << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_6BITS Setting */ +#define MXC_V_UART_CTRL_CHAR_SIZE_7BITS ((uint32_t)0x2UL) /**< CTRL_CHAR_SIZE_7BITS Value */ +#define MXC_S_UART_CTRL_CHAR_SIZE_7BITS (MXC_V_UART_CTRL_CHAR_SIZE_7BITS << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_7BITS Setting */ +#define MXC_V_UART_CTRL_CHAR_SIZE_8BITS ((uint32_t)0x3UL) /**< CTRL_CHAR_SIZE_8BITS Value */ +#define MXC_S_UART_CTRL_CHAR_SIZE_8BITS (MXC_V_UART_CTRL_CHAR_SIZE_8BITS << MXC_F_UART_CTRL_CHAR_SIZE_POS) /**< CTRL_CHAR_SIZE_8BITS Setting */ + +#define MXC_F_UART_CTRL_STOPBITS_POS 12 /**< CTRL_STOPBITS Position */ +#define MXC_F_UART_CTRL_STOPBITS ((uint32_t)(0x1UL << MXC_F_UART_CTRL_STOPBITS_POS)) /**< CTRL_STOPBITS Mask */ + +#define MXC_F_UART_CTRL_HFC_EN_POS 13 /**< CTRL_HFC_EN Position */ +#define MXC_F_UART_CTRL_HFC_EN ((uint32_t)(0x1UL << MXC_F_UART_CTRL_HFC_EN_POS)) /**< CTRL_HFC_EN Mask */ + +#define MXC_F_UART_CTRL_RTS_NEG_POS 14 /**< CTRL_RTS_NEG Position */ +#define MXC_F_UART_CTRL_RTS_NEG ((uint32_t)(0x1UL << MXC_F_UART_CTRL_RTS_NEG_POS)) /**< CTRL_RTS_NEG Mask */ + +#define MXC_F_UART_CTRL_CLK_EN_POS 15 /**< CTRL_CLK_EN Position */ +#define MXC_F_UART_CTRL_CLK_EN ((uint32_t)(0x1UL << MXC_F_UART_CTRL_CLK_EN_POS)) /**< CTRL_CLK_EN Mask */ + +#define MXC_F_UART_CTRL_CLK_SEL_POS 16 /**< CTRL_CLK_SEL Position */ +#define MXC_F_UART_CTRL_CLK_SEL ((uint32_t)(0x3UL << MXC_F_UART_CTRL_CLK_SEL_POS)) /**< CTRL_CLK_SEL Mask */ +#define MXC_V_UART_CTRL_CLK_SEL_PERIPHERAL_CLOCK ((uint32_t)0x0UL) /**< CTRL_CLK_SEL_PERIPHERAL_CLOCK Value */ +#define MXC_S_UART_CTRL_CLK_SEL_PERIPHERAL_CLOCK (MXC_V_UART_CTRL_CLK_SEL_PERIPHERAL_CLOCK << MXC_F_UART_CTRL_CLK_SEL_POS) /**< CTRL_CLK_SEL_PERIPHERAL_CLOCK Setting */ +#define MXC_V_UART_CTRL_CLK_SEL_EXTERNAL_CLOCK ((uint32_t)0x1UL) /**< CTRL_CLK_SEL_EXTERNAL_CLOCK Value */ +#define MXC_S_UART_CTRL_CLK_SEL_EXTERNAL_CLOCK (MXC_V_UART_CTRL_CLK_SEL_EXTERNAL_CLOCK << MXC_F_UART_CTRL_CLK_SEL_POS) /**< CTRL_CLK_SEL_EXTERNAL_CLOCK Setting */ +#define MXC_V_UART_CTRL_CLK_SEL_CLK2 ((uint32_t)0x2UL) /**< CTRL_CLK_SEL_CLK2 Value */ +#define MXC_S_UART_CTRL_CLK_SEL_CLK2 (MXC_V_UART_CTRL_CLK_SEL_CLK2 << MXC_F_UART_CTRL_CLK_SEL_POS) /**< CTRL_CLK_SEL_CLK2 Setting */ +#define MXC_V_UART_CTRL_CLK_SEL_CLK3 ((uint32_t)0x3UL) /**< CTRL_CLK_SEL_CLK3 Value */ +#define MXC_S_UART_CTRL_CLK_SEL_CLK3 (MXC_V_UART_CTRL_CLK_SEL_CLK3 << MXC_F_UART_CTRL_CLK_SEL_POS) /**< CTRL_CLK_SEL_CLK3 Setting */ + +#define MXC_F_UART_CTRL_CLK_RDY_POS 19 /**< CTRL_CLK_RDY Position */ +#define MXC_F_UART_CTRL_CLK_RDY ((uint32_t)(0x1UL << MXC_F_UART_CTRL_CLK_RDY_POS)) /**< CTRL_CLK_RDY Mask */ + +#define MXC_F_UART_CTRL_CLK_GATE_POS 20 /**< CTRL_CLK_GATE Position */ +#define MXC_F_UART_CTRL_CLK_GATE ((uint32_t)(0x1UL << MXC_F_UART_CTRL_CLK_GATE_POS)) /**< CTRL_CLK_GATE Mask */ + +/**@} end of group UART_CTRL_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_STATUS UART_STATUS + * @brief Status register + * @{ + */ +#define MXC_F_UART_STATUS_TX_BUSY_POS 0 /**< STATUS_TX_BUSY Position */ +#define MXC_F_UART_STATUS_TX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_BUSY_POS)) /**< STATUS_TX_BUSY Mask */ + +#define MXC_F_UART_STATUS_RX_BUSY_POS 1 /**< STATUS_RX_BUSY Position */ +#define MXC_F_UART_STATUS_RX_BUSY ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_BUSY_POS)) /**< STATUS_RX_BUSY Mask */ + +#define MXC_F_UART_STATUS_RX_EM_POS 4 /**< STATUS_RX_EM Position */ +#define MXC_F_UART_STATUS_RX_EM ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_EM_POS)) /**< STATUS_RX_EM Mask */ + +#define MXC_F_UART_STATUS_RX_FULL_POS 5 /**< STATUS_RX_FULL Position */ +#define MXC_F_UART_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */ + +#define MXC_F_UART_STATUS_TX_EM_POS 6 /**< STATUS_TX_EM Position */ +#define MXC_F_UART_STATUS_TX_EM ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_EM_POS)) /**< STATUS_TX_EM Mask */ + +#define MXC_F_UART_STATUS_TX_FULL_POS 7 /**< STATUS_TX_FULL Position */ +#define MXC_F_UART_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_UART_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */ + +#define MXC_F_UART_STATUS_RX_LVL_POS 8 /**< STATUS_RX_LVL Position */ +#define MXC_F_UART_STATUS_RX_LVL ((uint32_t)(0xFUL << MXC_F_UART_STATUS_RX_LVL_POS)) /**< STATUS_RX_LVL Mask */ + +#define MXC_F_UART_STATUS_TX_LVL_POS 12 /**< STATUS_TX_LVL Position */ +#define MXC_F_UART_STATUS_TX_LVL ((uint32_t)(0xFUL << MXC_F_UART_STATUS_TX_LVL_POS)) /**< STATUS_TX_LVL Mask */ + +/**@} end of group UART_STATUS_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_INTEN UART_INTEN + * @brief Interrupt Enable control register + * @{ + */ +#define MXC_F_UART_INTEN_RX_FERR_POS 0 /**< INTEN_RX_FERR Position */ +#define MXC_F_UART_INTEN_RX_FERR ((uint32_t)(0x1UL << MXC_F_UART_INTEN_RX_FERR_POS)) /**< INTEN_RX_FERR Mask */ + +#define MXC_F_UART_INTEN_RX_PAR_POS 1 /**< INTEN_RX_PAR Position */ +#define MXC_F_UART_INTEN_RX_PAR ((uint32_t)(0x1UL << MXC_F_UART_INTEN_RX_PAR_POS)) /**< INTEN_RX_PAR Mask */ + +#define MXC_F_UART_INTEN_CTS_EV_POS 2 /**< INTEN_CTS_EV Position */ +#define MXC_F_UART_INTEN_CTS_EV ((uint32_t)(0x1UL << MXC_F_UART_INTEN_CTS_EV_POS)) /**< INTEN_CTS_EV Mask */ + +#define MXC_F_UART_INTEN_RX_OV_POS 3 /**< INTEN_RX_OV Position */ +#define MXC_F_UART_INTEN_RX_OV ((uint32_t)(0x1UL << MXC_F_UART_INTEN_RX_OV_POS)) /**< INTEN_RX_OV Mask */ + +#define MXC_F_UART_INTEN_RX_THD_POS 4 /**< INTEN_RX_THD Position */ +#define MXC_F_UART_INTEN_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_INTEN_RX_THD_POS)) /**< INTEN_RX_THD Mask */ + +#define MXC_F_UART_INTEN_TX_OB_POS 5 /**< INTEN_TX_OB Position */ +#define MXC_F_UART_INTEN_TX_OB ((uint32_t)(0x1UL << MXC_F_UART_INTEN_TX_OB_POS)) /**< INTEN_TX_OB Mask */ + +#define MXC_F_UART_INTEN_TX_HE_POS 6 /**< INTEN_TX_HE Position */ +#define MXC_F_UART_INTEN_TX_HE ((uint32_t)(0x1UL << MXC_F_UART_INTEN_TX_HE_POS)) /**< INTEN_TX_HE Mask */ + +#define MXC_F_UART_INTEN_RX_FULL_POS 7 /**< INTEN_RX_FULL Position */ +#define MXC_F_UART_INTEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_INTEN_RX_FULL_POS)) /**< INTEN_RX_FULL Mask */ + +/**@} end of group UART_INTEN_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_INTFL UART_INTFL + * @brief Interrupt status flags Control register + * @{ + */ +#define MXC_F_UART_INTFL_RX_FERR_POS 0 /**< INTFL_RX_FERR Position */ +#define MXC_F_UART_INTFL_RX_FERR ((uint32_t)(0x1UL << MXC_F_UART_INTFL_RX_FERR_POS)) /**< INTFL_RX_FERR Mask */ + +#define MXC_F_UART_INTFL_RX_PAR_POS 1 /**< INTFL_RX_PAR Position */ +#define MXC_F_UART_INTFL_RX_PAR ((uint32_t)(0x1UL << MXC_F_UART_INTFL_RX_PAR_POS)) /**< INTFL_RX_PAR Mask */ + +#define MXC_F_UART_INTFL_CTS_EV_POS 2 /**< INTFL_CTS_EV Position */ +#define MXC_F_UART_INTFL_CTS_EV ((uint32_t)(0x1UL << MXC_F_UART_INTFL_CTS_EV_POS)) /**< INTFL_CTS_EV Mask */ + +#define MXC_F_UART_INTFL_RX_OV_POS 3 /**< INTFL_RX_OV Position */ +#define MXC_F_UART_INTFL_RX_OV ((uint32_t)(0x1UL << MXC_F_UART_INTFL_RX_OV_POS)) /**< INTFL_RX_OV Mask */ + +#define MXC_F_UART_INTFL_RX_THD_POS 4 /**< INTFL_RX_THD Position */ +#define MXC_F_UART_INTFL_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_INTFL_RX_THD_POS)) /**< INTFL_RX_THD Mask */ + +#define MXC_F_UART_INTFL_TX_OB_POS 5 /**< INTFL_TX_OB Position */ +#define MXC_F_UART_INTFL_TX_OB ((uint32_t)(0x1UL << MXC_F_UART_INTFL_TX_OB_POS)) /**< INTFL_TX_OB Mask */ + +#define MXC_F_UART_INTFL_TX_HE_POS 6 /**< INTFL_TX_HE Position */ +#define MXC_F_UART_INTFL_TX_HE ((uint32_t)(0x1UL << MXC_F_UART_INTFL_TX_HE_POS)) /**< INTFL_TX_HE Mask */ + +#define MXC_F_UART_INTFL_RX_FULL_POS 7 /**< INTFL_RX_FULL Position */ +#define MXC_F_UART_INTFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_INTFL_RX_FULL_POS)) /**< INTFL_RX_FULL Mask */ + +/**@} end of group UART_INTFL_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_CLKDIV UART_CLKDIV + * @brief Clock Divider register + * @{ + */ +#define MXC_F_UART_CLKDIV_CLKDIV_POS 0 /**< CLKDIV_CLKDIV Position */ +#define MXC_F_UART_CLKDIV_CLKDIV ((uint32_t)(0xFFFFFUL << MXC_F_UART_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */ + +/**@} end of group UART_CLKDIV_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_OSR UART_OSR + * @brief Over Sampling Rate register + * @{ + */ +#define MXC_F_UART_OSR_OSR_POS 0 /**< OSR_OSR Position */ +#define MXC_F_UART_OSR_OSR ((uint32_t)(0x7UL << MXC_F_UART_OSR_OSR_POS)) /**< OSR_OSR Mask */ + +/**@} end of group UART_OSR_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_TXPEEK UART_TXPEEK + * @brief TX FIFO Output Peek register + * @{ + */ +#define MXC_F_UART_TXPEEK_DATA_POS 0 /**< TXPEEK_DATA Position */ +#define MXC_F_UART_TXPEEK_DATA ((uint32_t)(0xFFUL << MXC_F_UART_TXPEEK_DATA_POS)) /**< TXPEEK_DATA Mask */ + +/**@} end of group UART_TXPEEK_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_PIN UART_PIN + * @brief Pin register + * @{ + */ +#define MXC_F_UART_PIN_CTS_POS 0 /**< PIN_CTS Position */ +#define MXC_F_UART_PIN_CTS ((uint32_t)(0x1UL << MXC_F_UART_PIN_CTS_POS)) /**< PIN_CTS Mask */ + +#define MXC_F_UART_PIN_RTS_POS 1 /**< PIN_RTS Position */ +#define MXC_F_UART_PIN_RTS ((uint32_t)(0x1UL << MXC_F_UART_PIN_RTS_POS)) /**< PIN_RTS Mask */ + +/**@} end of group UART_PIN_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_FIFO UART_FIFO + * @brief FIFO Read/Write register + * @{ + */ +#define MXC_F_UART_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ +#define MXC_F_UART_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_UART_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ + +#define MXC_F_UART_FIFO_RX_PAR_POS 8 /**< FIFO_RX_PAR Position */ +#define MXC_F_UART_FIFO_RX_PAR ((uint32_t)(0x1UL << MXC_F_UART_FIFO_RX_PAR_POS)) /**< FIFO_RX_PAR Mask */ + +/**@} end of group UART_FIFO_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_DMA UART_DMA + * @brief DMA Configuration register + * @{ + */ +#define MXC_F_UART_DMA_TX_THD_VAL_POS 0 /**< DMA_TX_THD_VAL Position */ +#define MXC_F_UART_DMA_TX_THD_VAL ((uint32_t)(0xFUL << MXC_F_UART_DMA_TX_THD_VAL_POS)) /**< DMA_TX_THD_VAL Mask */ + +#define MXC_F_UART_DMA_TX_EN_POS 4 /**< DMA_TX_EN Position */ +#define MXC_F_UART_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */ + +#define MXC_F_UART_DMA_RX_THD_VAL_POS 5 /**< DMA_RX_THD_VAL Position */ +#define MXC_F_UART_DMA_RX_THD_VAL ((uint32_t)(0xFUL << MXC_F_UART_DMA_RX_THD_VAL_POS)) /**< DMA_RX_THD_VAL Mask */ + +#define MXC_F_UART_DMA_RX_EN_POS 9 /**< DMA_RX_EN Position */ +#define MXC_F_UART_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_UART_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */ + +/**@} end of group UART_DMA_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_WKEN UART_WKEN + * @brief Wake up enable Control register + * @{ + */ +#define MXC_F_UART_WKEN_RX_NE_POS 0 /**< WKEN_RX_NE Position */ +#define MXC_F_UART_WKEN_RX_NE ((uint32_t)(0x1UL << MXC_F_UART_WKEN_RX_NE_POS)) /**< WKEN_RX_NE Mask */ + +#define MXC_F_UART_WKEN_RX_FULL_POS 1 /**< WKEN_RX_FULL Position */ +#define MXC_F_UART_WKEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_WKEN_RX_FULL_POS)) /**< WKEN_RX_FULL Mask */ + +#define MXC_F_UART_WKEN_RX_THD_POS 2 /**< WKEN_RX_THD Position */ +#define MXC_F_UART_WKEN_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_WKEN_RX_THD_POS)) /**< WKEN_RX_THD Mask */ + +/**@} end of group UART_WKEN_Register */ + +/** + * @ingroup uart_registers + * @defgroup UART_WKFL UART_WKFL + * @brief Wake up Flags register + * @{ + */ +#define MXC_F_UART_WKFL_RX_NE_POS 0 /**< WKFL_RX_NE Position */ +#define MXC_F_UART_WKFL_RX_NE ((uint32_t)(0x1UL << MXC_F_UART_WKFL_RX_NE_POS)) /**< WKFL_RX_NE Mask */ + +#define MXC_F_UART_WKFL_RX_FULL_POS 1 /**< WKFL_RX_FULL Position */ +#define MXC_F_UART_WKFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_WKFL_RX_FULL_POS)) /**< WKFL_RX_FULL Mask */ + +#define MXC_F_UART_WKFL_RX_THD_POS 2 /**< WKFL_RX_THD Position */ +#define MXC_F_UART_WKFL_RX_THD ((uint32_t)(0x1UL << MXC_F_UART_WKFL_RX_THD_POS)) /**< WKFL_RX_THD Mask */ + +/**@} end of group UART_WKFL_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_UART_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/wdt_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/wdt_regs.h new file mode 100644 index 00000000000..5e9bceab6dd --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/wdt_regs.h @@ -0,0 +1,315 @@ +/** + * @file wdt_regs.h + * @brief Registers, Bit Masks and Bit Positions for the WDT Peripheral Module. + * @note This file is @generated. + * @ingroup wdt_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_WDT_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_WDT_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup wdt + * @defgroup wdt_registers WDT_Registers + * @brief Registers, Bit Masks and Bit Positions for the WDT Peripheral Module. + * @details Windowed Watchdog Timer + */ + +/** + * @ingroup wdt_registers + * Structure type to access the WDT Registers. + */ +typedef struct { + __IO uint32_t ctrl; /**< \b 0x00: WDT CTRL Register */ + __O uint32_t rst; /**< \b 0x04: WDT RST Register */ + __IO uint32_t clksel; /**< \b 0x08: WDT CLKSEL Register */ + __I uint32_t cnt; /**< \b 0x0C: WDT CNT Register */ +} mxc_wdt_regs_t; + +/* Register offsets for module WDT */ +/** + * @ingroup wdt_registers + * @defgroup WDT_Register_Offsets Register Offsets + * @brief WDT Peripheral Register Offsets from the WDT Base Peripheral Address. + * @{ + */ +#define MXC_R_WDT_CTRL ((uint32_t)0x00000000UL) /**< Offset from WDT Base Address: 0x0000 */ +#define MXC_R_WDT_RST ((uint32_t)0x00000004UL) /**< Offset from WDT Base Address: 0x0004 */ +#define MXC_R_WDT_CLKSEL ((uint32_t)0x00000008UL) /**< Offset from WDT Base Address: 0x0008 */ +#define MXC_R_WDT_CNT ((uint32_t)0x0000000CUL) /**< Offset from WDT Base Address: 0x000C */ +/**@} end of group wdt_registers */ + +/** + * @ingroup wdt_registers + * @defgroup WDT_CTRL WDT_CTRL + * @brief Watchdog Timer Control Register. + * @{ + */ +#define MXC_F_WDT_CTRL_INT_LATE_VAL_POS 0 /**< CTRL_INT_LATE_VAL Position */ +#define MXC_F_WDT_CTRL_INT_LATE_VAL ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_INT_LATE_VAL_POS)) /**< CTRL_INT_LATE_VAL Mask */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_INT_LATE_VAL_WDT2POW31 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW31 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW31 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW31 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_INT_LATE_VAL_WDT2POW30 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW30 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW30 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW30 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_INT_LATE_VAL_WDT2POW29 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW29 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW29 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW29 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_INT_LATE_VAL_WDT2POW28 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW28 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW28 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW28 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_INT_LATE_VAL_WDT2POW27 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW27 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW27 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW27 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_INT_LATE_VAL_WDT2POW26 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW26 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW26 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW26 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_INT_LATE_VAL_WDT2POW25 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW25 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW25 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW25 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_INT_LATE_VAL_WDT2POW24 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW24 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW24 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW24 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_INT_LATE_VAL_WDT2POW23 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW23 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW23 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW23 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_INT_LATE_VAL_WDT2POW22 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW22 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW22 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW22 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_INT_LATE_VAL_WDT2POW21 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW21 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW21 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW21 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_INT_LATE_VAL_WDT2POW20 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW20 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW20 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW20 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_INT_LATE_VAL_WDT2POW19 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW19 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW19 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW19 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_INT_LATE_VAL_WDT2POW18 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW18 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW18 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW18 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_INT_LATE_VAL_WDT2POW17 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW17 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW17 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW17 Setting */ +#define MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_INT_LATE_VAL_WDT2POW16 Value */ +#define MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW16 (MXC_V_WDT_CTRL_INT_LATE_VAL_WDT2POW16 << MXC_F_WDT_CTRL_INT_LATE_VAL_POS) /**< CTRL_INT_LATE_VAL_WDT2POW16 Setting */ + +#define MXC_F_WDT_CTRL_RST_LATE_VAL_POS 4 /**< CTRL_RST_LATE_VAL Position */ +#define MXC_F_WDT_CTRL_RST_LATE_VAL ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_RST_LATE_VAL_POS)) /**< CTRL_RST_LATE_VAL Mask */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_RST_LATE_VAL_WDT2POW31 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW31 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW31 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW31 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_RST_LATE_VAL_WDT2POW30 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW30 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW30 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW30 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_RST_LATE_VAL_WDT2POW29 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW29 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW29 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW29 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_RST_LATE_VAL_WDT2POW28 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW28 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW28 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW28 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_RST_LATE_VAL_WDT2POW27 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW27 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW27 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW27 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_RST_LATE_VAL_WDT2POW26 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW26 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW26 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW26 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_RST_LATE_VAL_WDT2POW25 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW25 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW25 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW25 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_RST_LATE_VAL_WDT2POW24 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW24 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW24 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW24 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_RST_LATE_VAL_WDT2POW23 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW23 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW23 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW23 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_RST_LATE_VAL_WDT2POW22 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW22 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW22 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW22 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_RST_LATE_VAL_WDT2POW21 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW21 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW21 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW21 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_RST_LATE_VAL_WDT2POW20 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW20 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW20 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW20 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_RST_LATE_VAL_WDT2POW19 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW19 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW19 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW19 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_RST_LATE_VAL_WDT2POW18 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW18 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW18 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW18 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_RST_LATE_VAL_WDT2POW17 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW17 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW17 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW17 Setting */ +#define MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_RST_LATE_VAL_WDT2POW16 Value */ +#define MXC_S_WDT_CTRL_RST_LATE_VAL_WDT2POW16 (MXC_V_WDT_CTRL_RST_LATE_VAL_WDT2POW16 << MXC_F_WDT_CTRL_RST_LATE_VAL_POS) /**< CTRL_RST_LATE_VAL_WDT2POW16 Setting */ + +#define MXC_F_WDT_CTRL_EN_POS 8 /**< CTRL_EN Position */ +#define MXC_F_WDT_CTRL_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_EN_POS)) /**< CTRL_EN Mask */ + +#define MXC_F_WDT_CTRL_INT_LATE_POS 9 /**< CTRL_INT_LATE Position */ +#define MXC_F_WDT_CTRL_INT_LATE ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_LATE_POS)) /**< CTRL_INT_LATE Mask */ + +#define MXC_F_WDT_CTRL_WDT_INT_EN_POS 10 /**< CTRL_WDT_INT_EN Position */ +#define MXC_F_WDT_CTRL_WDT_INT_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_WDT_INT_EN_POS)) /**< CTRL_WDT_INT_EN Mask */ + +#define MXC_F_WDT_CTRL_WDT_RST_EN_POS 11 /**< CTRL_WDT_RST_EN Position */ +#define MXC_F_WDT_CTRL_WDT_RST_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_WDT_RST_EN_POS)) /**< CTRL_WDT_RST_EN Mask */ + +#define MXC_F_WDT_CTRL_INT_EARLY_POS 12 /**< CTRL_INT_EARLY Position */ +#define MXC_F_WDT_CTRL_INT_EARLY ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_INT_EARLY_POS)) /**< CTRL_INT_EARLY Mask */ + +#define MXC_F_WDT_CTRL_INT_EARLY_VAL_POS 16 /**< CTRL_INT_EARLY_VAL Position */ +#define MXC_F_WDT_CTRL_INT_EARLY_VAL ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS)) /**< CTRL_INT_EARLY_VAL Mask */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_INT_EARLY_VAL_WDT2POW31 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW31 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW31 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW31 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_INT_EARLY_VAL_WDT2POW30 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW30 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW30 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW30 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_INT_EARLY_VAL_WDT2POW29 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW29 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW29 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW29 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_INT_EARLY_VAL_WDT2POW28 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW28 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW28 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW28 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_INT_EARLY_VAL_WDT2POW27 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW27 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW27 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW27 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_INT_EARLY_VAL_WDT2POW26 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW26 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW26 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW26 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_INT_EARLY_VAL_WDT2POW25 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW25 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW25 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW25 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_INT_EARLY_VAL_WDT2POW24 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW24 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW24 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW24 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_INT_EARLY_VAL_WDT2POW23 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW23 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW23 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW23 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_INT_EARLY_VAL_WDT2POW22 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW22 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW22 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW22 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_INT_EARLY_VAL_WDT2POW21 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW21 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW21 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW21 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_INT_EARLY_VAL_WDT2POW20 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW20 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW20 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW20 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_INT_EARLY_VAL_WDT2POW19 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW19 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW19 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW19 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_INT_EARLY_VAL_WDT2POW18 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW18 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW18 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW18 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_INT_EARLY_VAL_WDT2POW17 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW17 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW17 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW17 Setting */ +#define MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_INT_EARLY_VAL_WDT2POW16 Value */ +#define MXC_S_WDT_CTRL_INT_EARLY_VAL_WDT2POW16 (MXC_V_WDT_CTRL_INT_EARLY_VAL_WDT2POW16 << MXC_F_WDT_CTRL_INT_EARLY_VAL_POS) /**< CTRL_INT_EARLY_VAL_WDT2POW16 Setting */ + +#define MXC_F_WDT_CTRL_RST_EARLY_VAL_POS 20 /**< CTRL_RST_EARLY_VAL Position */ +#define MXC_F_WDT_CTRL_RST_EARLY_VAL ((uint32_t)(0xFUL << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS)) /**< CTRL_RST_EARLY_VAL Mask */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW31 ((uint32_t)0x0UL) /**< CTRL_RST_EARLY_VAL_WDT2POW31 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW31 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW31 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW31 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW30 ((uint32_t)0x1UL) /**< CTRL_RST_EARLY_VAL_WDT2POW30 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW30 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW30 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW30 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW29 ((uint32_t)0x2UL) /**< CTRL_RST_EARLY_VAL_WDT2POW29 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW29 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW29 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW29 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW28 ((uint32_t)0x3UL) /**< CTRL_RST_EARLY_VAL_WDT2POW28 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW28 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW28 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW28 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW27 ((uint32_t)0x4UL) /**< CTRL_RST_EARLY_VAL_WDT2POW27 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW27 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW27 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW27 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW26 ((uint32_t)0x5UL) /**< CTRL_RST_EARLY_VAL_WDT2POW26 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW26 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW26 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW26 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW25 ((uint32_t)0x6UL) /**< CTRL_RST_EARLY_VAL_WDT2POW25 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW25 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW25 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW25 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW24 ((uint32_t)0x7UL) /**< CTRL_RST_EARLY_VAL_WDT2POW24 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW24 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW24 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW24 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW23 ((uint32_t)0x8UL) /**< CTRL_RST_EARLY_VAL_WDT2POW23 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW23 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW23 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW23 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW22 ((uint32_t)0x9UL) /**< CTRL_RST_EARLY_VAL_WDT2POW22 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW22 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW22 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW22 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW21 ((uint32_t)0xAUL) /**< CTRL_RST_EARLY_VAL_WDT2POW21 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW21 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW21 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW21 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW20 ((uint32_t)0xBUL) /**< CTRL_RST_EARLY_VAL_WDT2POW20 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW20 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW20 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW20 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW19 ((uint32_t)0xCUL) /**< CTRL_RST_EARLY_VAL_WDT2POW19 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW19 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW19 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW19 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW18 ((uint32_t)0xDUL) /**< CTRL_RST_EARLY_VAL_WDT2POW18 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW18 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW18 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW18 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW17 ((uint32_t)0xEUL) /**< CTRL_RST_EARLY_VAL_WDT2POW17 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW17 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW17 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW17 Setting */ +#define MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW16 ((uint32_t)0xFUL) /**< CTRL_RST_EARLY_VAL_WDT2POW16 Value */ +#define MXC_S_WDT_CTRL_RST_EARLY_VAL_WDT2POW16 (MXC_V_WDT_CTRL_RST_EARLY_VAL_WDT2POW16 << MXC_F_WDT_CTRL_RST_EARLY_VAL_POS) /**< CTRL_RST_EARLY_VAL_WDT2POW16 Setting */ + +#define MXC_F_WDT_CTRL_CLKRDY_IE_POS 27 /**< CTRL_CLKRDY_IE Position */ +#define MXC_F_WDT_CTRL_CLKRDY_IE ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_CLKRDY_IE_POS)) /**< CTRL_CLKRDY_IE Mask */ + +#define MXC_F_WDT_CTRL_CLKRDY_POS 28 /**< CTRL_CLKRDY Position */ +#define MXC_F_WDT_CTRL_CLKRDY ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_CLKRDY_POS)) /**< CTRL_CLKRDY Mask */ + +#define MXC_F_WDT_CTRL_WIN_EN_POS 29 /**< CTRL_WIN_EN Position */ +#define MXC_F_WDT_CTRL_WIN_EN ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_WIN_EN_POS)) /**< CTRL_WIN_EN Mask */ + +#define MXC_F_WDT_CTRL_RST_EARLY_POS 30 /**< CTRL_RST_EARLY Position */ +#define MXC_F_WDT_CTRL_RST_EARLY ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_EARLY_POS)) /**< CTRL_RST_EARLY Mask */ + +#define MXC_F_WDT_CTRL_RST_LATE_POS 31 /**< CTRL_RST_LATE Position */ +#define MXC_F_WDT_CTRL_RST_LATE ((uint32_t)(0x1UL << MXC_F_WDT_CTRL_RST_LATE_POS)) /**< CTRL_RST_LATE Mask */ + +/**@} end of group WDT_CTRL_Register */ + +/** + * @ingroup wdt_registers + * @defgroup WDT_RST WDT_RST + * @brief Windowed Watchdog Timer Reset Register. + * @{ + */ +#define MXC_F_WDT_RST_RESET_POS 0 /**< RST_RESET Position */ +#define MXC_F_WDT_RST_RESET ((uint32_t)(0xFFUL << MXC_F_WDT_RST_RESET_POS)) /**< RST_RESET Mask */ +#define MXC_V_WDT_RST_RESET_SEQ0 ((uint32_t)0xA5UL) /**< RST_RESET_SEQ0 Value */ +#define MXC_S_WDT_RST_RESET_SEQ0 (MXC_V_WDT_RST_RESET_SEQ0 << MXC_F_WDT_RST_RESET_POS) /**< RST_RESET_SEQ0 Setting */ +#define MXC_V_WDT_RST_RESET_SEQ1 ((uint32_t)0x5AUL) /**< RST_RESET_SEQ1 Value */ +#define MXC_S_WDT_RST_RESET_SEQ1 (MXC_V_WDT_RST_RESET_SEQ1 << MXC_F_WDT_RST_RESET_POS) /**< RST_RESET_SEQ1 Setting */ + +/**@} end of group WDT_RST_Register */ + +/** + * @ingroup wdt_registers + * @defgroup WDT_CLKSEL WDT_CLKSEL + * @brief Windowed Watchdog Timer Clock Select Register. + * @{ + */ +#define MXC_F_WDT_CLKSEL_SOURCE_POS 0 /**< CLKSEL_SOURCE Position */ +#define MXC_F_WDT_CLKSEL_SOURCE ((uint32_t)(0x7UL << MXC_F_WDT_CLKSEL_SOURCE_POS)) /**< CLKSEL_SOURCE Mask */ + +/**@} end of group WDT_CLKSEL_Register */ + +/** + * @ingroup wdt_registers + * @defgroup WDT_CNT WDT_CNT + * @brief Windowed Watchdog Timer Count Register. + * @{ + */ +#define MXC_F_WDT_CNT_COUNT_POS 0 /**< CNT_COUNT Position */ +#define MXC_F_WDT_CNT_COUNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_WDT_CNT_COUNT_POS)) /**< CNT_COUNT Mask */ + +/**@} end of group WDT_CNT_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_WDT_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/wut_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/wut_regs.h new file mode 100644 index 00000000000..e9f2a5f84bd --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/wut_regs.h @@ -0,0 +1,244 @@ +/** + * @file wut_regs.h + * @brief Registers, Bit Masks and Bit Positions for the WUT Peripheral Module. + * @note This file is @generated. + * @ingroup wut_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_WUT_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_WUT_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup wut + * @defgroup wut_registers WUT_Registers + * @brief Registers, Bit Masks and Bit Positions for the WUT Peripheral Module. + * @details 32-bit reloadable timer that can be used for timing and wakeup. + */ + +/** + * @ingroup wut_registers + * Structure type to access the WUT Registers. + */ +typedef struct { + __IO uint32_t cnt; /**< \b 0x00: WUT CNT Register */ + __IO uint32_t cmp; /**< \b 0x04: WUT CMP Register */ + __R uint32_t rsv_0x8; + __IO uint32_t intr; /**< \b 0x0C: WUT INTR Register */ + __IO uint32_t ctrl; /**< \b 0x10: WUT CTRL Register */ + __IO uint32_t nolcmp; /**< \b 0x14: WUT NOLCMP Register */ + __IO uint32_t preset; /**< \b 0x18: WUT PRESET Register */ + __IO uint32_t reload; /**< \b 0x1C: WUT RELOAD Register */ + __IO uint32_t snapshot; /**< \b 0x20: WUT SNAPSHOT Register */ +} mxc_wut_regs_t; + +/* Register offsets for module WUT */ +/** + * @ingroup wut_registers + * @defgroup WUT_Register_Offsets Register Offsets + * @brief WUT Peripheral Register Offsets from the WUT Base Peripheral Address. + * @{ + */ +#define MXC_R_WUT_CNT ((uint32_t)0x00000000UL) /**< Offset from WUT Base Address: 0x0000 */ +#define MXC_R_WUT_CMP ((uint32_t)0x00000004UL) /**< Offset from WUT Base Address: 0x0004 */ +#define MXC_R_WUT_INTR ((uint32_t)0x0000000CUL) /**< Offset from WUT Base Address: 0x000C */ +#define MXC_R_WUT_CTRL ((uint32_t)0x00000010UL) /**< Offset from WUT Base Address: 0x0010 */ +#define MXC_R_WUT_NOLCMP ((uint32_t)0x00000014UL) /**< Offset from WUT Base Address: 0x0014 */ +#define MXC_R_WUT_PRESET ((uint32_t)0x00000018UL) /**< Offset from WUT Base Address: 0x0018 */ +#define MXC_R_WUT_RELOAD ((uint32_t)0x0000001CUL) /**< Offset from WUT Base Address: 0x001C */ +#define MXC_R_WUT_SNAPSHOT ((uint32_t)0x00000020UL) /**< Offset from WUT Base Address: 0x0020 */ +/**@} end of group wut_registers */ + +/** + * @ingroup wut_registers + * @defgroup WUT_CNT WUT_CNT + * @brief Count. This register stores the current timer count. + * @{ + */ +#define MXC_F_WUT_CNT_COUNT_POS 0 /**< CNT_COUNT Position */ +#define MXC_F_WUT_CNT_COUNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_WUT_CNT_COUNT_POS)) /**< CNT_COUNT Mask */ + +/**@} end of group WUT_CNT_Register */ + +/** + * @ingroup wut_registers + * @defgroup WUT_CMP WUT_CMP + * @brief Compare. This register stores the compare value, which is used to set the + * maximum count value to initiate a reload of the timer to 0x0001. + * @{ + */ +#define MXC_F_WUT_CMP_COMPARE_POS 0 /**< CMP_COMPARE Position */ +#define MXC_F_WUT_CMP_COMPARE ((uint32_t)(0xFFFFFFFFUL << MXC_F_WUT_CMP_COMPARE_POS)) /**< CMP_COMPARE Mask */ + +/**@} end of group WUT_CMP_Register */ + +/** + * @ingroup wut_registers + * @defgroup WUT_INTR WUT_INTR + * @brief Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the + * associated interrupt. + * @{ + */ +#define MXC_F_WUT_INTR_IF_CLR_POS 0 /**< INTR_IF_CLR Position */ +#define MXC_F_WUT_INTR_IF_CLR ((uint32_t)(0x1UL << MXC_F_WUT_INTR_IF_CLR_POS)) /**< INTR_IF_CLR Mask */ + +/**@} end of group WUT_INTR_Register */ + +/** + * @ingroup wut_registers + * @defgroup WUT_CTRL WUT_CTRL + * @brief Timer Control Register. + * @{ + */ +#define MXC_F_WUT_CTRL_TMODE_POS 0 /**< CTRL_TMODE Position */ +#define MXC_F_WUT_CTRL_TMODE ((uint32_t)(0x7UL << MXC_F_WUT_CTRL_TMODE_POS)) /**< CTRL_TMODE Mask */ +#define MXC_V_WUT_CTRL_TMODE_ONESHOT ((uint32_t)0x0UL) /**< CTRL_TMODE_ONESHOT Value */ +#define MXC_S_WUT_CTRL_TMODE_ONESHOT (MXC_V_WUT_CTRL_TMODE_ONESHOT << MXC_F_WUT_CTRL_TMODE_POS) /**< CTRL_TMODE_ONESHOT Setting */ +#define MXC_V_WUT_CTRL_TMODE_CONTINUOUS ((uint32_t)0x1UL) /**< CTRL_TMODE_CONTINUOUS Value */ +#define MXC_S_WUT_CTRL_TMODE_CONTINUOUS (MXC_V_WUT_CTRL_TMODE_CONTINUOUS << MXC_F_WUT_CTRL_TMODE_POS) /**< CTRL_TMODE_CONTINUOUS Setting */ +#define MXC_V_WUT_CTRL_TMODE_COUNTER ((uint32_t)0x2UL) /**< CTRL_TMODE_COUNTER Value */ +#define MXC_S_WUT_CTRL_TMODE_COUNTER (MXC_V_WUT_CTRL_TMODE_COUNTER << MXC_F_WUT_CTRL_TMODE_POS) /**< CTRL_TMODE_COUNTER Setting */ +#define MXC_V_WUT_CTRL_TMODE_CAPTURE ((uint32_t)0x4UL) /**< CTRL_TMODE_CAPTURE Value */ +#define MXC_S_WUT_CTRL_TMODE_CAPTURE (MXC_V_WUT_CTRL_TMODE_CAPTURE << MXC_F_WUT_CTRL_TMODE_POS) /**< CTRL_TMODE_CAPTURE Setting */ +#define MXC_V_WUT_CTRL_TMODE_COMPARE ((uint32_t)0x5UL) /**< CTRL_TMODE_COMPARE Value */ +#define MXC_S_WUT_CTRL_TMODE_COMPARE (MXC_V_WUT_CTRL_TMODE_COMPARE << MXC_F_WUT_CTRL_TMODE_POS) /**< CTRL_TMODE_COMPARE Setting */ +#define MXC_V_WUT_CTRL_TMODE_GATED ((uint32_t)0x6UL) /**< CTRL_TMODE_GATED Value */ +#define MXC_S_WUT_CTRL_TMODE_GATED (MXC_V_WUT_CTRL_TMODE_GATED << MXC_F_WUT_CTRL_TMODE_POS) /**< CTRL_TMODE_GATED Setting */ +#define MXC_V_WUT_CTRL_TMODE_CAPTURECOMPARE ((uint32_t)0x7UL) /**< CTRL_TMODE_CAPTURECOMPARE Value */ +#define MXC_S_WUT_CTRL_TMODE_CAPTURECOMPARE (MXC_V_WUT_CTRL_TMODE_CAPTURECOMPARE << MXC_F_WUT_CTRL_TMODE_POS) /**< CTRL_TMODE_CAPTURECOMPARE Setting */ + +#define MXC_F_WUT_CTRL_PRES_POS 3 /**< CTRL_PRES Position */ +#define MXC_F_WUT_CTRL_PRES ((uint32_t)(0x7UL << MXC_F_WUT_CTRL_PRES_POS)) /**< CTRL_PRES Mask */ +#define MXC_V_WUT_CTRL_PRES_DIV1 ((uint32_t)0x0UL) /**< CTRL_PRES_DIV1 Value */ +#define MXC_S_WUT_CTRL_PRES_DIV1 (MXC_V_WUT_CTRL_PRES_DIV1 << MXC_F_WUT_CTRL_PRES_POS) /**< CTRL_PRES_DIV1 Setting */ +#define MXC_V_WUT_CTRL_PRES_DIV2 ((uint32_t)0x1UL) /**< CTRL_PRES_DIV2 Value */ +#define MXC_S_WUT_CTRL_PRES_DIV2 (MXC_V_WUT_CTRL_PRES_DIV2 << MXC_F_WUT_CTRL_PRES_POS) /**< CTRL_PRES_DIV2 Setting */ +#define MXC_V_WUT_CTRL_PRES_DIV4 ((uint32_t)0x2UL) /**< CTRL_PRES_DIV4 Value */ +#define MXC_S_WUT_CTRL_PRES_DIV4 (MXC_V_WUT_CTRL_PRES_DIV4 << MXC_F_WUT_CTRL_PRES_POS) /**< CTRL_PRES_DIV4 Setting */ +#define MXC_V_WUT_CTRL_PRES_DIV8 ((uint32_t)0x3UL) /**< CTRL_PRES_DIV8 Value */ +#define MXC_S_WUT_CTRL_PRES_DIV8 (MXC_V_WUT_CTRL_PRES_DIV8 << MXC_F_WUT_CTRL_PRES_POS) /**< CTRL_PRES_DIV8 Setting */ +#define MXC_V_WUT_CTRL_PRES_DIV16 ((uint32_t)0x4UL) /**< CTRL_PRES_DIV16 Value */ +#define MXC_S_WUT_CTRL_PRES_DIV16 (MXC_V_WUT_CTRL_PRES_DIV16 << MXC_F_WUT_CTRL_PRES_POS) /**< CTRL_PRES_DIV16 Setting */ +#define MXC_V_WUT_CTRL_PRES_DIV32 ((uint32_t)0x5UL) /**< CTRL_PRES_DIV32 Value */ +#define MXC_S_WUT_CTRL_PRES_DIV32 (MXC_V_WUT_CTRL_PRES_DIV32 << MXC_F_WUT_CTRL_PRES_POS) /**< CTRL_PRES_DIV32 Setting */ +#define MXC_V_WUT_CTRL_PRES_DIV64 ((uint32_t)0x6UL) /**< CTRL_PRES_DIV64 Value */ +#define MXC_S_WUT_CTRL_PRES_DIV64 (MXC_V_WUT_CTRL_PRES_DIV64 << MXC_F_WUT_CTRL_PRES_POS) /**< CTRL_PRES_DIV64 Setting */ +#define MXC_V_WUT_CTRL_PRES_DIV128 ((uint32_t)0x7UL) /**< CTRL_PRES_DIV128 Value */ +#define MXC_S_WUT_CTRL_PRES_DIV128 (MXC_V_WUT_CTRL_PRES_DIV128 << MXC_F_WUT_CTRL_PRES_POS) /**< CTRL_PRES_DIV128 Setting */ + +#define MXC_F_WUT_CTRL_TPOL_POS 6 /**< CTRL_TPOL Position */ +#define MXC_F_WUT_CTRL_TPOL ((uint32_t)(0x1UL << MXC_F_WUT_CTRL_TPOL_POS)) /**< CTRL_TPOL Mask */ + +#define MXC_F_WUT_CTRL_TEN_POS 7 /**< CTRL_TEN Position */ +#define MXC_F_WUT_CTRL_TEN ((uint32_t)(0x1UL << MXC_F_WUT_CTRL_TEN_POS)) /**< CTRL_TEN Mask */ + +#define MXC_F_WUT_CTRL_PRES3_POS 8 /**< CTRL_PRES3 Position */ +#define MXC_F_WUT_CTRL_PRES3 ((uint32_t)(0x1UL << MXC_F_WUT_CTRL_PRES3_POS)) /**< CTRL_PRES3 Mask */ + +/**@} end of group WUT_CTRL_Register */ + +/** + * @ingroup wut_registers + * @defgroup WUT_NOLCMP WUT_NOLCMP + * @brief Timer Non-Overlapping Compare Register. + * @{ + */ +#define MXC_F_WUT_NOLCMP_NOL_LO_POS 0 /**< NOLCMP_NOL_LO Position */ +#define MXC_F_WUT_NOLCMP_NOL_LO ((uint32_t)(0xFFUL << MXC_F_WUT_NOLCMP_NOL_LO_POS)) /**< NOLCMP_NOL_LO Mask */ + +#define MXC_F_WUT_NOLCMP_NOL_HI_POS 8 /**< NOLCMP_NOL_HI Position */ +#define MXC_F_WUT_NOLCMP_NOL_HI ((uint32_t)(0xFFUL << MXC_F_WUT_NOLCMP_NOL_HI_POS)) /**< NOLCMP_NOL_HI Mask */ + +/**@} end of group WUT_NOLCMP_Register */ + +/** + * @ingroup wut_registers + * @defgroup WUT_PRESET WUT_PRESET + * @brief Preset register. + * @{ + */ +#define MXC_F_WUT_PRESET_PRESET_POS 0 /**< PRESET_PRESET Position */ +#define MXC_F_WUT_PRESET_PRESET ((uint32_t)(0xFFFFFFFFUL << MXC_F_WUT_PRESET_PRESET_POS)) /**< PRESET_PRESET Mask */ + +/**@} end of group WUT_PRESET_Register */ + +/** + * @ingroup wut_registers + * @defgroup WUT_RELOAD WUT_RELOAD + * @brief Reload register. + * @{ + */ +#define MXC_F_WUT_RELOAD_RELOAD_POS 0 /**< RELOAD_RELOAD Position */ +#define MXC_F_WUT_RELOAD_RELOAD ((uint32_t)(0xFFFFFFFFUL << MXC_F_WUT_RELOAD_RELOAD_POS)) /**< RELOAD_RELOAD Mask */ + +/**@} end of group WUT_RELOAD_Register */ + +/** + * @ingroup wut_registers + * @defgroup WUT_SNAPSHOT WUT_SNAPSHOT + * @brief Snapshot register. + * @{ + */ +#define MXC_F_WUT_SNAPSHOT_SNAPSHOT_POS 0 /**< SNAPSHOT_SNAPSHOT Position */ +#define MXC_F_WUT_SNAPSHOT_SNAPSHOT ((uint32_t)(0xFFFFFFFFUL << MXC_F_WUT_SNAPSHOT_SNAPSHOT_POS)) /**< SNAPSHOT_SNAPSHOT Mask */ + +/**@} end of group WUT_SNAPSHOT_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_WUT_REGS_H_ diff --git a/Libraries/PeriphDrivers/Source/ADC/adc_reva_me30.svd b/Libraries/PeriphDrivers/Source/ADC/adc_reva_me30.svd new file mode 100644 index 00000000000..50b90f0ff63 --- /dev/null +++ b/Libraries/PeriphDrivers/Source/ADC/adc_reva_me30.svd @@ -0,0 +1,362 @@ + + + + ADC + 10-bit Analog to Digital Converter + + 0x40034000 + 32 + read-write + + 0 + 0x1000 + registers + + + ADC + ADC IRQ + 20 + + + + + CTRL + ADC Control + 0x0000 + read-write + + + START + Start ADC Conversion + [0:0] + read-write + + + PWR + ADC Power Up + [1:1] + read-write + + + REBUF_PWR + ADC Reference Buffer Power Up + [3:3] + read-write + + + CHGPUMP_PWR + ADC Charge Pump Power Up + [4:4] + read-write + + + REF_SCALE + ADC Reference Scale + [8:8] + read-write + + + SCALE + ADC Scale + [9:9] + read-write + + + CLK_EN + ADC Clock Enable + [11:11] + read-write + + + CH_SEL + ADC Channel Select + [16:12] + read-write + + + AIN0 + 0 + + + AIN1 + 1 + + + AIN2 + 2 + + + AIN3 + 3 + + + AIN4 + 4 + + + AIN5 + 5 + + + AIN6 + 6 + + + AIN7 + 7 + + + VcoreA + 8 + + + VcoreB + 9 + + + Vrxout + 10 + + + Vtxout + 11 + + + VddA + 12 + + + VddB + VddB/4 + 13 + + + Vddio + Vddio/4 + 14 + + + Vddioh + Vddioh/4 + 15 + + + VregI + VregI/4 + 16 + + + + + DIVSEL + Scales the external inputs, all inputs are scaled the same + [18:17] + read-write + + + DIV1 + 0 + + + DIV2 + 1 + + + DIV3 + 2 + + + DIV4 + 3 + + + + + DATA_ALIGN + ADC Data Alignment Select + [20:20] + read-write + + + + + + STATUS + ADC Status + 0x0004 + read-write + + + ACTIVE + ADC Conversion In Progress + [0:0] + read-only + + + AFE_PWR_UP_ACTIVE + AFE Power Up Delay Active + [2:2] + read-only + + + OVERFLOW + ADC Overflow + [3:3] + read-only + + + + + + DATA + ADC Output Data + 0x0008 + read-write + + + DATA + ADC Converted Sample Data Output + [15:0] + read-only + + + + + + INTR + ADC Interrupt Control Register + 0x000C + read-write + + + DONE_IE + ADC Done Interrupt Enable + [0:0] + read-write + + + REF_READY_IE + ADC Reference Ready Interrupt Enable + [1:1] + read-write + + + HI_LIMIT_IE + ADC Hi Limit Monitor Interrupt Enable + [2:2] + read-write + + + LO_LIMIT_IE + ADC Lo Limit Monitor Interrupt Enable + [3:3] + read-write + + + OVERFLOW_IE + ADC Overflow Interrupt Enable + [4:4] + read-write + + + DONE_IF + ADC Done Interrupt Flag + [16:16] + read-write + oneToClear + + + REF_READY_IF + ADC Reference Ready Interrupt Flag + [17:17] + read-write + oneToClear + + + HI_LIMIT_IF + ADC Hi Limit Monitor Interrupt Flag + [18:18] + read-write + oneToClear + + + LO_LIMIT_IF + ADC Lo Limit Monitor Interrupt Flag + [19:19] + read-write + oneToClear + + + OVERFLOW_IF + ADC Overflow Interrupt Flag + [20:20] + read-write + oneToClear + + + PENDING + ADC Interrupt Pending Status + [22:22] + read-only + + + + + + 4 + 4 + LIMIT[%s] + ADC Limit + 0x0010 + read-write + + + CH_LO_LIMIT + Low Limit Threshold + [9:0] + read-write + + + CH_HI_LIMIT + High Limit Threshold + [21:12] + read-write + + + CH_SEL + ADC Channel Select + [27:24] + read-write + + + CH_LO_LIMIT_EN + Low Limit Monitoring Enable + [28:28] + read-write + + + CH_HI_LIMIT_EN + High Limit Monitoring Enable + [29:29] + read-write + + + + + DECCNT + ADC Decimation Count. + 0x0020 + read-write + + + DELAY + Delay. + [31:0] + read-write + + + + + + + \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/DMA/dma_reva_me30.svd b/Libraries/PeriphDrivers/Source/DMA/dma_reva_me30.svd new file mode 100644 index 00000000000..2e190249a34 --- /dev/null +++ b/Libraries/PeriphDrivers/Source/DMA/dma_reva_me30.svd @@ -0,0 +1,715 @@ + + + + DMA + DMA Controller Fully programmable, chaining capable DMA channels. + 0x40028000 + 32 + + 0x00 + 0x1000 + registers + + + DMA0 + 28 + + + DMA1 + 29 + + + DMA2 + 30 + + + DMA3 + 31 + + + + INTEN + DMA Control Register. + 0x000 + + + CH0 + Channel 0 Interrupt Enable. + 0 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + CH1 + Channel 1 Interrupt Enable. + 1 + 1 + + + CH2 + Channel 2 Interrupt Enable. + 2 + 1 + + + CH3 + Channel 3 Interrupt Enable. + 3 + 1 + + + + + INTFL + DMA Interrupt Register. + 0x004 + read-only + + + CH0 + Channel Interrupt. To clear an interrupt, all active interrupt bits of the DMA_ST must be cleared. The interrupt bits are set only if their corresponding interrupt enable bits are set in DMA_CN. + 0 + 1 + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + CH1 + 1 + 1 + + + CH2 + 2 + 1 + + + CH3 + 3 + 1 + + + + + 4 + 0x20 + CH[%s] + DMA Channel registers. + dma_ch + 0x100 + read-write + + CTRL + DMA Channel Control Register. + 0x000 + + + EN + Channel Enable. This bit is automatically cleared when DMA_ST.CH_ST changes from 1 to 0. + 0 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + RLDEN + Reload Enable. Setting this bit to 1 enables DMA_SRC, DMA_DST and DMA_CNT to be reloaded with their corresponding reload registers upon count-to-zero. This bit is also writeable in the Count Reload Register. Refer to the description on Buffer Chaining for use of this bit. If buffer chaining is not used this bit must be written with a 0. This bit should be set after the reload registers have been programmed. + 1 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + PRI + DMA Priority. + 2 + 2 + + + high + Highest Priority. + 0 + + + medHigh + Medium High Priority. + 1 + + + medLow + Medium Low Priority. + 2 + + + low + Lowest Priority. + 3 + + + + + REQUEST + Request Select. Select DMA request line for this channel. If memory-to-memory is selected, the channel operates as if the request is always active. + 4 + 6 + + + MEMTOMEM + Memory To Memory + 0x00 + + + SPI1RX + SPI1 RX + 0x01 + + + UART0RX + UART0 RX + 0x04 + + + UART1RX + UART1 RX + 0x05 + + + I2C0RX + I2C0 RX + 0x07 + + + I2C1RX + I2C1 RX + 0x08 + + + ADC + ADC + 0x09 + + + I2C2RX + I2C2 RX + 0x0A + + + UART2RX + UART2 RX + 0x0E + + + SPI0RX + SPI0 RX + 0x0F + + + AESRX + AES RX + 0x10 + + + UART3RX + UART3 RX + 0x1C + + + I2SRX + I2S RX + 0x1E + + + SPI1TX + SPI1 TX + 0x21 + + + UART0TX + UART0 TX + 0x24 + + + UART1TX + UART1 TX + 0x25 + + + I2C0TX + I2C0 TX + 0x27 + + + I2C1TX + I2C1 TX + 0x28 + + + I2C2TX + I2C2 TX + 0x2A + + + CRCTX + CRC TX + 0x2C + + + UART2TX + UART2 TX + 0x2E + + + SPI0TX + SPI0 TX + 0x2F + + + AESTX + AES TX + 0x30 + + + UART3TX + UART3 TX + 0x3C + + + I2STX + I2S TX + 0x3E + + + + + TO_WAIT + Request Wait Enable. When enabled, delay timer start until DMA request transitions from active to inactive. + 10 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + TO_PER + Timeout Period Select. + 11 + 3 + + + to4 + Timeout of 3 to 4 prescale clocks. + 0 + + + to8 + Timeout of 7 to 8 prescale clocks. + 1 + + + to16 + Timeout of 15 to 16 prescale clocks. + 2 + + + to32 + Timeout of 31 to 32 prescale clocks. + 3 + + + to64 + Timeout of 63 to 64 prescale clocks. + 4 + + + to128 + Timeout of 127 to 128 prescale clocks. + 5 + + + to256 + Timeout of 255 to 256 prescale clocks. + 6 + + + to512 + Timeout of 511 to 512 prescale clocks. + 7 + + + + + TO_CLKDIV + Pre-Scale Select. Selects the Pre-Scale divider for timer clock input. + 14 + 2 + + + dis + Disable timer. + 0 + + + div256 + hclk / 256. + 1 + + + div64k + hclk / 64k. + 2 + + + div16M + hclk / 16M. + 3 + + + + + SRCWD + Source Width. In most cases, this will be the data width of each AHB transactions. However, the width will be reduced in the cases where DMA_CNT indicates a smaller value. + 16 + 2 + + + byte + Byte. + 0 + + + halfWord + Halfword. + 1 + + + word + Word. + 2 + + + + + SRCINC + Source Increment Enable. This bit enables DMA_SRC increment upon every AHB transaction. This bit is forced to 0 for DMA receive from peripherals. + 18 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + DSTWD + Destination Width. Indicates the width of the each AHB transactions to the destination peripheral or memory. (The actual width may be less than this if there are insufficient bytes in the DMA FIFO for the full width). + 20 + 2 + + + byte + Byte. + 0 + + + halfWord + Halfword. + 1 + + + word + Word. + 2 + + + + + DSTINC + Destination Increment Enable. This bit enables DMA_DST increment upon every AHB transaction. This bit is forced to 0 for DMA transmit to peripherals. + 22 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + BURST_SIZE + Burst Size. The number of bytes to be transferred into and out of the DMA FIFO in a single burst. Burst size equals 1 + value stored in this field. + 24 + 5 + + + DIS_IE + Channel Disable Interrupt Enable. When enabled, the IPEND will be set to 1 whenever CH_ST changes from 1 to 0. + 30 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + CTZ_IE + Count-to-zero Interrupts Enable. When enabled, the IPEND will be set to 1 whenever a count-to-zero event occurs. + 31 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + + + STATUS + DMA Channel Status Register. + 0x004 + + + STATUS + Channel Status. This bit is used to indicate to the programmer when it is safe to change the configuration, address, and count registers for the channel. Whenever this bit is cleared by hardware, the DMA_CFG.CHEN bit is also cleared (if not cleared already). + 0 + 1 + read-only + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + IPEND + Channel Interrupt. + 1 + 1 + read-only + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + CTZ_IF + Count-to-Zero (CTZ) Interrupt Flag + 2 + 1 + oneToClear + + + RLD_IF + Reload Event Interrupt Flag. + 3 + 1 + oneToClear + + + BUS_ERR + Bus Error. Indicates that an AHB abort was received and the channel has been disabled. + 4 + 1 + oneToClear + + + TO_IF + Time-Out Event Interrupt Flag. + 6 + 1 + oneToClear + + + + + SRC + Source Device Address. If SRCINC=1, the counter bits are incremented by 1,2, or 4, depending on the data width of each AHB cycle. For peripheral transfers, some or all of the actual address bits are fixed. If SRCINC=0, this register remains constant. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with the contents of DMA_SRC_RLD. + 0x008 + + + ADDR + 0 + 32 + + + + + DST + Destination Device Address. For peripheral transfers, some or all of the actual address bits are fixed. If DSTINC=1, this register is incremented on every AHB write out of the DMA FIFO. They are incremented by 1, 2, or 4, depending on the data width of each AHB cycle. In the case where a count-to-zero condition occurs while RLDEN=1, the register is reloaded with DMA_DST_RLD. + 0x00C + + + ADDR + 0 + 32 + + + + + CNT + DMA Counter. The user loads this register with the number of bytes to transfer. This counter decreases on every AHB cycle into the DMA FIFO. The decrement will be 1, 2, or 4 depending on the data width of each AHB cycle. When the counter reaches 0, a count-to-zero condition is triggered. + 0x010 + + + CNT + DMA Counter. + 0 + 24 + + + + + SRCRLD + Source Address Reload Value. The value of this register is loaded into DMA0_SRC upon a count-to-zero condition. + 0x014 + + + ADDR + Source Address Reload Value. + 0 + 31 + + + + + DSTRLD + Destination Address Reload Value. The value of this register is loaded into DMA0_DST upon a count-to-zero condition. + 0x018 + + + ADDR + Destination Address Reload Value. + 0 + 31 + + + + + CNTRLD + DMA Channel Count Reload Register. + 0x01C + + + CNT + Count Reload Value. The value of this register is loaded into DMA0_CNT upon a count-to-zero condition. + 0 + 24 + + + EN + Reload Enable. This bit should be set after the address reload registers have been programmed. This bit is automatically cleared to 0 when reload occurs. + 31 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + + + + + + \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/FLC/flc_revb_me30.svd b/Libraries/PeriphDrivers/Source/FLC/flc_revb_me30.svd new file mode 100644 index 00000000000..2b177533f80 --- /dev/null +++ b/Libraries/PeriphDrivers/Source/FLC/flc_revb_me30.svd @@ -0,0 +1,321 @@ + + + + FLC + Flash Memory Control. + FLSH_ + 0x40029000 + + 0x00 + 0x400 + registers + + + Flash_Controller + Flash Controller interrupt. + 23 + + + + ADDR + Flash Write Address. + 0x00 + + + ADDR + Address for next operation. + 0 + 32 + + + + + CLKDIV + Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller. + 0x04 + 0x00000064 + + + CLKDIV + Flash Clock Divide. The clock is divided by this value to generate a 1MHz clock for flash controller. + 0 + 8 + + + + + CTRL + Flash Control Register. + 0x08 + + + WR + Write. This bit is automatically cleared after the operation. + 0 + 1 + + + complete + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + ME + Mass Erase. This bit is automatically cleared after the operation. + 1 + 1 + + + PGE + Page Erase. This bit is automatically cleared after the operation. + 2 + 1 + + + ERASE_CODE + Erase Code. The ERASE_CODE must be set up property before erase operation can be initiated. These bits are automatically cleared after the operation is complete. + 8 + 8 + + + nop + No operation. + 0 + + + erasePage + Enable Page Erase. + 0x55 + + + eraseAll + Enable Mass Erase. The debug port must be enabled. + 0xAA + + + + + PEND + Flash Pending. When Flash operation is in progress (busy), Flash reads and writes will fail. When PEND is set, write to all Flash registers, with exception of the Flash interrupt register, are ignored. + 24 + 1 + read-only + + + idle + Idle. + 0 + + + busy + Busy. + 1 + + + + + LVE + Low Voltage enable. + 25 + 1 + + + UNLOCK + Flash Unlock. The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed. + 28 + 4 + + + unlocked + Flash Unlocked. + 2 + + + locked + Flash Locked. + 3 + + + + + + + INTR + Flash Interrupt Register. + 0x024 + + + DONE_IF + Flash Done Interrupt. This bit is set to 1 upon Flash write or erase completion. + 0 + 1 + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + AF_IF + Flash Access Fail. This bit is set when an attempt is made to write the flash while the flash is busy or the flash is locked. This bit can only be set to 1 by hardware. + 1 + 1 + + + noError + No Failure. + 0 + + + error + Failure occurs. + 1 + + + + + DONE_IE + Flash Done Interrupt Enable. + 8 + 1 + + + disable + Disable. + 0 + + + enable + Enable. + 1 + + + + + AF_IE + 9 + 1 + + + + + ECCDATA + ECC Data Register. + 0x2C + + + EVEN + Error Correction Code Odd Data. + 0 + 9 + + + ODD + Error Correction Code Even Data. + 16 + 9 + + + + + 4 + 4 + DATA[%s] + Flash Write Data. + 0x30 + + + DATA + Data next operation. + 0 + 32 + + + + + ACTRL + Access Control Register. Writing the ACTRL register with the following values in the order shown, allows read and write access to the system and user Information block: + pflc-actrl = 0x3a7f5ca3; + pflc-actrl = 0xa1e34f20; + pflc-actrl = 0x9608b2c1. When unlocked, a write of any word will disable access to system and user information block. Readback of this register is always zero. + 0x40 + write-only + + + ACTRL + Access control. + 0 + 32 + + + + + WELR0 + WELR0 + 0x80 + + + WELR0 + Access control. + 0 + 32 + + + + + WELR1 + WELR1 + 0x88 + + + WELR1 + Access control. + 0 + 32 + + + + + RLR0 + RLR0 + 0x90 + + + RLR0 + Access control. + 0 + 32 + + + + + RLR1 + RLR1 + 0x98 + + + RLR1 + Access control. + 0 + 32 + + + + + + + \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/GPIO/gpio_reva_me30.svd b/Libraries/PeriphDrivers/Source/GPIO/gpio_reva_me30.svd new file mode 100644 index 00000000000..2020a611e38 --- /dev/null +++ b/Libraries/PeriphDrivers/Source/GPIO/gpio_reva_me30.svd @@ -0,0 +1,712 @@ + + + + GPIO0 + Individual I/O for each GPIO + GPIO + 0x40008000 + + 0x00 + 0x1000 + registers + + + GPIO0 + GPIO0 interrupt. + 24 + + + + EN0 + GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port. + 0x00 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + ALTERNATE + Alternate function enabled. + 0 + + + GPIO + GPIO function is enabled. + 1 + + + + + + + EN0_SET + GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1, without affecting other bits in that register. + 0x04 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN0_CLR + GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register. + 0x08 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + OUTEN + GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port. + 0x0C + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + dis + GPIO Output Disable + 0 + + + en + GPIO Output Enable + 1 + + + + + + + OUTEN_SET + GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1, without affecting other bits in that register. + 0x10 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + OUTEN_CLR + GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, without affecting other bits in that register. + 0x14 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + OUT + GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers. + 0x18 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + low + Drive Logic 0 (low) on GPIO output. + 0 + + + high + Drive logic 1 (high) on GPIO output. + 1 + + + + + + + OUT_SET + GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1, without affecting other bits in that register. + 0x1C + write-only + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + no + No Effect. + 0 + + + set + Set GPIO_OUT bit in this position to '1' + 1 + + + + + + + OUT_CLR + GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0, without affecting other bits in that register. + 0x20 + write-only + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + IN + GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port. + 0x24 + read-only + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + INTMODE + GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port. + 0x28 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + level + Interrupts for this pin are level triggered. + 0 + + + edge + Interrupts for this pin are edge triggered. + 1 + + + + + + + INTPOL + GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port. + 0x2C + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + falling + Interrupts are latched on a falling edge or low level condition for this pin. + 0 + + + rising + Interrupts are latched on a rising edge or high condition for this pin. + 1 + + + + + + + INEN + GPIO Input Enable + 0x30 + + + INTEN + GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port. + 0x34 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + dis + Interrupts are disabled for this GPIO pin. + 0 + + + en + Interrupts are enabled for this GPIO pin. + 1 + + + + + + + INTEN_SET + GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits in that register. + 0x38 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + no + No effect. + 0 + + + set + Set GPIO_INT_EN bit in this position to '1' + 1 + + + + + + + INTEN_CLR + GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0, without affecting other bits in that register. + 0x3C + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + no + No Effect. + 0 + + + clear + Clear GPIO_INT_EN bit in this position to '0' + 1 + + + + + + + INTFL + GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port. + 0x40 + read-only + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + no + No Interrupt is pending on this GPIO pin. + 0 + + + pending + An Interrupt is pending on this GPIO pin. + 1 + + + + + + + INTFL_CLR + GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits in that register. + 0x48 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + WKEN + GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port. + 0x4C + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + dis + PMU wakeup for this GPIO is disabled. + 0 + + + en + PMU wakeup for this GPIO is enabled. + 1 + + + + + + + WKEN_SET + GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in that register. + 0x50 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + WKEN_CLR + GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other bits in that register. + 0x54 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + DUALEDGE + GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port. + 0x5C + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + no + No Effect. + 0 + + + en + Dual Edge mode is enabled. If edge-triggered interrupts are enabled on this GPIO pin, then both rising and falling edges will trigger interrupts regardless of the GPIO_INT_POL setting. + 1 + + + + + + + PADCTRL0 + GPIO Input Mode Config 0. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port. + 0x60 + + + ALL + The two bits in GPIO_PADCTRL0 and GPIO_PADCTRL1 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. + 0 + 32 + + + impedance + High Impedance. + 0 + + + pu + Weak pull-up mode. + 1 + + + pd + weak pull-down mode. + 2 + + + + + + + PADCTRL1 + GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port. + 0x64 + + + ALL + The two bits in GPIO_PADCTRL0 and GPIO_PADCTRL1 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. + 0 + 32 + + + impedance + High Impedance. + 0 + + + pu + Weak pull-up mode. + 1 + + + pd + weak pull-down mode. + 2 + + + + + + + EN1 + GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. + 0x68 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + primary + Primary function selected. + 0 + + + secondary + Secondary function selected. + 1 + + + + + + + EN1_SET + GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register. + 0x6C + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN1_CLR + GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register. + 0x70 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN2 + GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. + 0x74 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + primary + Primary function selected. + 0 + + + secondary + Secondary function selected. + 1 + + + + + + + EN2_SET + GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1, without affecting other bits in that register. + 0x78 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN2_CLR + GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0, without affecting other bits in that register. + 0x7C + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + HYSEN + GPIO Input Hysteresis Enable. + 0xA8 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + SRSEL + GPIO Slew Rate Enable Register. + 0xAC + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + FAST + Fast Slew Rate selected. + 0 + + + SLOW + Slow Slew Rate selected. + 1 + + + + + + + DS0 + GPIO Drive Strength 0 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. + 0xB0 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + ld + GPIO port pin is in low-drive mode. + 0 + + + hd + GPIO port pin is in high-drive mode. + 1 + + + + + + + DS1 + GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. + 0xB4 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + PSSEL + GPIO Pull Select Mode. + 0xB8 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + VSSEL + GPIO Voltage Select. + 0xC0 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + + + \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/I2C/i2c_reva_me30.svd b/Libraries/PeriphDrivers/Source/I2C/i2c_reva_me30.svd new file mode 100644 index 00000000000..b49bf1fe78e --- /dev/null +++ b/Libraries/PeriphDrivers/Source/I2C/i2c_reva_me30.svd @@ -0,0 +1,1480 @@ + + + + I2C0 + Inter-Integrated Circuit. + I2C + 0x4001D000 + 32 + + 0x00 + 0x1000 + registers + + + I2C0 + I2C0 IRQ + 13 + + + + CTRL + Control Register0. + 0x00 + + + + EN + I2C Enable. + [0:0] + read-write + + + dis + Disable I2C. + 0 + + + en + enable I2C. + 1 + + + + + + MST_MODE + Master Mode Enable. + [1:1] + read-write + + + slave_mode + Slave Mode. + 0 + + + master_mode + Master Mode. + 1 + + + + + + GC_ADDR_EN + General Call Address Enable. + [2:2] + read-write + + + dis + Ignore Gneral Call Address. + 0 + + + en + Acknowledge general call address. + 1 + + + + + + IRXM_EN + Interactive Receive Mode. + [3:3] + read-write + + + dis + Disable Interactive Receive Mode. + 0 + + + en + Enable Interactive Receive Mode. + 1 + + + + + + IRXM_ACK + Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0. + [4:4] + read-write + + + ack + return ACK (pulling SDA LOW). + 0 + + + nack + return NACK (leaving SDA HIGH). + 1 + + + + + + SCL_OUT + SCL Output. This bits control SCL output when SWOE =1. + [6:6] + read-write + + + drive_scl_low + Drive SCL low. + 0 + + + release_scl + Release SCL. + 1 + + + + + + SDA_OUT + SDA Output. This bits control SDA output when SWOE = 1. + [7:7] + read-write + + + drive_sda_low + Drive SDA low. + 0 + + + release_sda + Release SDA. + 1 + + + + + + SCL + SCL status. This bit reflects the logic gate of SCL signal. + [8:8] + read-only + + + + SDA + SDA status. THis bit reflects the logic gate of SDA signal. + [9:9] + read-only + + + + BB_EN + Software Output Enable. + [10:10] + read-write + + + outputs_disable + I2C Outputs SCLO and SDAO disabled. + 0 + + + outputs_enable + I2C Outputs SCLO and SDAO enabled. + 1 + + + + + + READ + Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match (GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set. + [11:11] + read-only + + + write + Write. + 0 + + + read + Read. + 1 + + + + + + CLKSTR_DIS + This bit will disable slave clock stretching when set. + [12:12] + read-write + + + en + Slave clock stretching enabled. + 0 + + + dis + Slave clock stretching disabled. + 1 + + + + + + ONE_MST_MODE + SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low. + [13:13] + read-write + + + dis + Standard open-drain operation: + drive low for 0, Hi-Z for 1 + 0 + + + en + Non-standard push-pull operation: + drive low for 0, drive high for 1 + 1 + + + + + + HS_EN + High speed mode enable + [15:15] + read-write + + + + + STATUS + Status Register. + 0x04 + + + BUSY + Bus Status. + [0:0] + read-only + + + idle + I2C Bus Idle. + 0 + + + busy + I2C Bus Busy. + 1 + + + + + RX_EM + RX empty. + [1:1] + read-only + + + not_empty + Not Empty. + 0 + + + empty + Empty. + 1 + + + + + RX_FULL + RX Full. + [2:2] + read-only + + + not_full + Not Full. + 0 + + + full + Full. + 1 + + + + + TX_EM + TX Empty. + [3:3] + + + not_empty + Not Empty. + 0 + + + empty + Empty. + 1 + + + + + TX_FULL + TX Full. + [4:4] + + + not_empty + Not Empty. + 0 + + + empty + Empty. + 1 + + + + + MST_BUSY + Clock Mode. + [5:5] + read-only + + + not_actively_driving_scl_clock + Device not actively driving SCL clock cycles. + 0 + + + actively_driving_scl_clock + Device operating as master and actively driving SCL clock cycles. + 1 + + + + + + + INTFL0 + Interrupt Status Register. + 0x08 + + + DONE + Transfer Done Interrupt. + [0:0] + + INT_FL0_Done + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + IRXM + Interactive Receive Interrupt. + [1:1] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + GC_ADDR_MATCH + Slave General Call Address Match Interrupt. + [2:2] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + ADDR_MATCH + Slave Address Match Interrupt. + [3:3] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + RX_THD + Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level. + [4:4] + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. RX_FIFO equal or more bytes than the threshold. + 1 + + + + + TX_THD + Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level. + [5:5] + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. + 1 + + + + + STOP + STOP Interrupt. + [6:6] + + + inactive + No interrupt is pending. + 0 + + + pending + An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. + 1 + + + + + ADDR_ACK + Address Acknowledge Interrupt. + [7:7] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + ARB_ERR + Arbritation error Interrupt. + [8:8] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + TO_ERR + timeout Error Interrupt. + [9:9] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + ADDR_NACK_ERR + Address NACK Error Interrupt. + [10:10] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + DATA_ERR + Data NACK Error Interrupt. + [11:11] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + DNR_ERR + Do Not Respond Error Interrupt. + [12:12] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + START_ERR + Start Error Interrupt. + [13:13] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + STOP_ERR + Stop Error Interrupt. + [14:14] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + TX_LOCKOUT + Transmit Lock Out Interrupt. + [15:15] + + + MAMI + Multiple Address Match Interrupt + [21:16] + + + RD_ADDR_MATCH + Slave Read Address Match Interrupt + [22:22] + + + WR_ADDR_MATCH + Slave Write Address Match Interrupt + [23:23] + + + + + INTEN0 + Interrupt Enable Register. + 0x0C + read-write + + + DONE + Transfer Done Interrupt Enable. + [0:0] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when DONE = 1. + 1 + + + + + IRXM + Description not available. + [1:1] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when RX_MODE = 1. + 1 + + + + + GC_ADDR_MATCH + Slave mode general call address match received input enable. + [2:2] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when GEN_CTRL_ADDR = 1. + 1 + + + + + ADDR_MATCH + Slave mode incoming address match interrupt. + [3:3] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when ADDR_MATCH = 1. + 1 + + + + + RX_THD + RX FIFO Above Treshold Level Interrupt Enable. + [4:4] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + TX_THD + TX FIFO Below Treshold Level Interrupt Enable. + [5:5] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + STOP + Stop Interrupt Enable + [6:6] + read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when STOP = 1. + 1 + + + + + ADDR_ACK + Received Address ACK from Slave Interrupt. + [7:7] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + ARB_ERR + Master Mode Arbitration Lost Interrupt. + [8:8] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + TO_ERR + Timeout Error Interrupt Enable. + [9:9] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + ADDR_NACK_ERR + Master Mode Address NACK Received Interrupt. + [10:10] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + DATA_ERR + Master Mode Data NACK Received Interrupt. + [11:11] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + DNR_ERR + Slave Mode Do Not Respond Interrupt. + [12:12] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + START_ERR + Out of Sequence START condition detected interrupt. + [13:13] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + STOP_ERR + Out of Sequence STOP condition detected interrupt. + [14:14] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + + + TX_LOCKOUT + TX FIFO Locked Out Interrupt. + [15:15] + + + MAMI + Multiple Address Match Interrupt + [21:16] + + + RD_ADDR_MATCH + Slave Read Address Match Interrupt + [22:22] + + + WR_ADDR_MATCH + Slave Write Address Match Interrupt + [23:23] + + + + + INTFL1 + Interrupt Status Register 1. + 0x10 + + + RX_OV + Receiver Overflow Interrupt. When operating as a slave receiver, this bit is set when you reach the first data bit and the RX FIFO and shift register are both full. + [0:0] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + TX_UN + Transmit Underflow Interrupt. When operating as a slave transmitter, this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet). + [1:1] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + + + + START + START Condition Status Flag. + [2:2] + + + + + INTEN1 + Interrupt Staus Register 1. + 0x14 + read-write + + + RX_OV + Receiver Overflow Interrupt Enable. + [0:0] + + + dis + No Interrupt is Pending. + 0 + + + en + An interrupt is pending. + 1 + + + + + TX_UN + Transmit Underflow Interrupt Enable. + [1:1] + + + dis + No Interrupt is Pending. + 0 + + + en + An interrupt is pending. + 1 + + + + + START + START Condition Interrupt Enable. + [2:2] + + + + + FIFOLEN + FIFO Configuration Register. + 0x18 + + + RX_DEPTH + Receive FIFO Length. + [7:0] + read-only + + + TX_DEPTH + Transmit FIFO Length. + [15:8] + read-only + + + + + RXCTRL0 + Receive Control Register 0. + 0x1C + + + DNR + Do Not Respond. + [0:0] + + + respond + Always respond to address match. + 0 + + + not_respond_rx_fifo_empty + Do not respond to address match when RX_FIFO is not empty. + 1 + + + + + FLUSH + Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status. + [7:7] + + + not_flushed + FIFO not flushed. + 0 + + + flush + Flush RX_FIFO. + 1 + + + + + THD_LVL + Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold. + [11:8] + + + + + RXCTRL1 + Receive Control Register 1. + 0x20 + + + CNT + Receive Count Bits. These bits define the number of bytes to be received in a transaction, except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction. + [7:0] + + + LVL + Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0. + [11:8] + read-only + + + + + TXCTRL0 + Transmit Control Register 0. + 0x24 + + + PRELOAD_MODE + Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match. + [0:0] + + + TX_READY_MODE + Transmit FIFO Ready Manual Mode. + [1:1] + + + en + HW control of I2CTXRDY enabled. + 0 + + + dis + HW control of I2CTXRDY disabled. + 1 + + + + + GC_ADDR_FLUSH_DIS + TX FIFO General Call Address Match Auto Flush Disable. + [2:2] + + + en + Enabled. + 0 + + + dis + Disabled. + 1 + + + + + WR_ADDR_FLUSH_DIS + TX FIFO Slave Address Match Write Auto Flush Disable. + [3:3] + + + en + Enabled. + 0 + + + dis + Disabled. + 1 + + + + + RD_ADDR_FLUSH_DIS + TX FIFO Slave Address Match Read Auto Flush Disable. + [4:4] + + + en + Enabled. + 0 + + + dis + Disabled. + 1 + + + + + NACK_FLUSH_DIS + TX FIFO received NACK Auto Flush Disable. + [5:5] + + + en + Enabled. + 0 + + + dis + Disabled. + 1 + + + + + FLUSH + Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation. + [7:7] + + + not_flushed + FIFO not flushed. + 0 + + + flush + Flush TX_FIFO. + 1 + + + + + THD_VAL + Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold. + [11:8] + + + + + TXCTRL1 + Transmit Control Register 1. + 0x28 + + + PRELOAD_RDY + Transmit FIFO Preload Ready. + [0:0] + + + LAST + Transmit Last. + [1:1] + + + LVL + Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO. + [11:8] + read-only + + + + + FIFO + Data Register. + 0x2C + + + DATA + Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location. + 0 + 8 + + + + + MSTCTRL + Master Control Register. + 0x30 + + + START + Setting this bit to 1 will start a master transfer. + [0:0] + + + RESTART + Setting this bit to 1 will generate a repeated START. + [1:1] + + + STOP + Setting this bit to 1 will generate a STOP condition. + [2:2] + + + EX_ADDR_EN + Slave Extend Address Select. + [7:7] + + + 7_bits_address + 7-bit address. + 0 + + + 10_bits_address + 10-bit address. + 1 + + + + + CODE + Master Code. + [10:8] + + + IGN_ACK + Master Ignore Acknowledge. + [12:12] + + + + + CLKLO + Clock Low Register. + 0x34 + + + LO + Clock low. In master mode, these bits define the SCL low period. In slave mode, these bits define the time SCL will be held low after data is outputted. + [8:0] + + + + + CLKHI + Clock high Register. + 0x38 + + + HI + Clock High. In master mode, these bits define the SCL high period. + [8:0] + + + + + HSCLK + Clock high Register. + 0x3C + + + LO + Clock Low. This field sets the Hs-Mode clock low count. In Slave mode, this is the time SCL is held low after data is output on SDA. + [7:0] + + + HI + Clock High. This field sets the Hs-Mode clock high count. In Slave mode, this is the time SCL is held high after data is output on SDA + [15:8] + + + + + TIMEOUT + Timeout Register + 0x40 + + + SCL_TO_VAL + Timeout + [15:0] + + + + + DMA + DMA Register. + 0x48 + + + TX_EN + TX channel enable. + [0:0] + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + RX_EN + RX channel enable. + [1:1] + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + + + 4 + 4 + SLAVE_MULTI[%s] + Slave Address Register. + SLAVE0 + 0x4C + 32 + read-write + + + ADDR + Slave Address. + [9:0] + + + DIS + Slave Disable. + [10:10] + + + EXT_ADDR_EN + Extended Address Select. + [15:15] + + + 7_bits_address + 7-bit address. + 0 + + + 10_bits_address + 10-bit address. + 1 + + + + + + + SLAVE0 + Slave Address Register. + 0x4C + + + SLAVE1 + Slave Address Register. + 0x50 + + + SLAVE2 + Slave Address Register. + 0x54 + + + SLAVE3 + Slave Address Register. + 0x58 + + + + + \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/I2S/i2s_reva_me30.svd b/Libraries/PeriphDrivers/Source/I2S/i2s_reva_me30.svd new file mode 100644 index 00000000000..941e6e7cc82 --- /dev/null +++ b/Libraries/PeriphDrivers/Source/I2S/i2s_reva_me30.svd @@ -0,0 +1,327 @@ + + + + I2S + Inter-IC Sound Interface. + I2S + 0x40060000 + 32 + + 0x00 + 0x1000 + registers + + + I2S + I2S IRQ + 99 + + + + CTRL0CH0 + Global mode channel. + 0x00 + + + LSB_FIRST + LSB Transmit Receive First. + [1:1] + read-write + + + PDM_FILT + PDM Filter. + [2:2] + read-write + + + PDM_EN + PDM Enable. + [3:3] + read-write + + + USEDDR + DDR. + [4:4] + read-write + + + PDM_INV + Invert PDM. + [5:5] + read-write + + + CH_MODE + SCK Select. + [7:6] + read-write + + + WS_POL + WS polarity select. + [8:8] + read-write + + + MSB_LOC + MSB location. + [9:9] + read-only + + + ALIGN + Align to MSB or LSB. + [10:10] + read-only + + + EXT_SEL + External SCK/WS selection. + [11:11] + read-write + + + STEREO + Stereo mode of I2S. + [13:12] + read-only + + + WSIZE + Data size when write to FIFO. + [15:14] + read-write + + + TX_EN + TX channel enable. + [16:16] + read-write + + + RX_EN + RX channel enable. + [17:17] + read-write + + + FLUSH + Flushes the TX/RX FIFO buffer. + [18:18] + read-write + + + RST + Write 1 to reset channel. + [19:19] + read-write + + + FIFO_LSB + Bit Field Control. + [20:20] + read-write + + + RX_THD_VAL + depth of receive FIFO for threshold interrupt generation. + [31:24] + read-write + + + + + CTRL1CH0 + Local channel Setup. + 0x10 + + + BITS_WORD + I2S word length. + [4:0] + read-write + + + EN + I2S clock enable. + [8:8] + read-write + + + SMP_SIZE + I2S sample size length. + [13:9] + read-write + + + CLKSEL + Select source clock for internal SCK mode. + [14:14] + read-write + + + ADJUST + LSB/MSB Justify. + [15:15] + read-write + + + CLKDIV + I2S clock frequency divisor. + [31:16] + read-write + + + + + FILTCH0 + Filter. + 0x20 + + + DMACH0 + DMA Control. + 0x30 + + + DMA_TX_THD_VAL + TX FIFO Level DMA Trigger. + [6:0] + read-write + + + DMA_TX_EN + TX DMA channel enable. + [7:7] + read-write + + + DMA_RX_THD_VAL + RX FIFO Level DMA Trigger. + [14:8] + read-write + + + DMA_RX_EN + RX DMA channel enable. + [15:15] + read-write + + + TX_LVL + Number of data word in the TX FIFO. + [23:16] + read-write + + + RX_LVL + Number of data word in the RX FIFO. + [31:24] + read-write + + + + + FIFOCH0 + I2S Fifo. + 0x40 + + + DATA + Load/unload location for TX and RX FIFO buffers. + [31:0] + read-write + + + + + INTFL + ISR Status. + 0x50 + + + RX_OV_CH0 + Status for RX FIFO Overrun interrupt. + [0:0] + read-write + + + RX_THD_CH0 + Status for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field. + [1:1] + read-write + + + TX_OB_CH0 + Status for interrupt when TX FIFO has only one byte remaining. + [2:2] + read-write + + + TX_HE_CH0 + Status for interrupt when TX FIFO is half empty. + [3:3] + read-write + + + + + INTEN + Interrupt Enable. + 0x54 + + + RX_OV_CH0 + Enable for RX FIFO Overrun interrupt. + [0:0] + read-write + + + RX_THD_CH0 + Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field. + [1:1] + read-write + + + TX_OB_CH0 + Enable for interrupt when TX FIFO has only one byte remaining. + [2:2] + read-write + + + TX_HE_CH0 + Enable for interrupt when TX FIFO is half empty. + [3:3] + read-write + + + + + EXTSETUP + Ext Control. + 0x58 + + + EXT_BITS_WORD + Word Length for ch_mode. + [4:0] + read-write + + + + + WKEN + Wakeup Enable. + 0x5C + + + WKFL + Wakeup Flags. + 0x60 + + + + + \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/LP/pwrseq_me30.svd b/Libraries/PeriphDrivers/Source/LP/pwrseq_me30.svd new file mode 100644 index 00000000000..3f6b4a158fa --- /dev/null +++ b/Libraries/PeriphDrivers/Source/LP/pwrseq_me30.svd @@ -0,0 +1,3165 @@ + + + + PWRSEQ + Power Sequencer / Low Power Control Register. + 0x40006800 + + 0x00 + 0x400 + registers + + + + LPCTRL + Low Power Control Register. + 0x00 + + + RAMRET_EN + System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. + 0 + 4 + + + OVR + Operating Voltage Range + 4 + 2 + + + 1_1V + 1.1V + 2 + + + + + RETREG_EN + Retention Regulator Enable. This bit controls the retention regulator in BACKUP mode. + 8 + 1 + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + FASTWK_EN + Fast Wake-Up Mode. This bit enables fast wake-up from DeepSleep mode. (5uS typical). + 10 + 1 + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + BG_DIS + Bandgap OFF. This controls the System Bandgap in DeepSleep mode. + 11 + 1 + + + on + Bandgap is always ON. + 0 + + + off + Bandgap is OFF in DeepSleep mode (default). + 1 + + + + + PORVDDCMON_DIS + VDDC (VCore) Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDC supply in DeepSleep and BACKUP mode. + 12 + 1 + + + VDDIOHHVMON_DIS + VDDIOH High Voltage Monitor Disable. This bit controls the power monitor on VDDIOH supply in all operating modes. + 17 + 1 + + + VDDIOHVMON_DIS + VDDIO High Voltage Monitor Disable. This bit controls the power monitor on VDDIO supply in all operating modes. + 18 + 1 + + + VCOREHVMON_DIS + VCORE High Voltage Monitor Disable. This bit controls the power monitor on VCORE supply in all operating modes. + 19 + 1 + + + VDDCMON_DIS + VDDC (Vcore) Monitor Disable. This bit controls the power monitor on the VCore supply in all operating modes. + 20 + 1 + + + en + Enable if Bandgap is ON (default) + 0 + + + dis + Disabled. + 1 + + + + + VRTCMON_DIS + VRTC Monitor Disable. This bit controls the power monitor on the Always-On Supply in all operating modes. + 21 + 1 + + + en + Enable if Bandgap is ON (default) + 0 + + + dis + Disabled. + 1 + + + + + VDDAMON_DIS + VDDA Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes. + 22 + 1 + + + en + Enable if Bandgap is ON (default) + 0 + + + dis + Disabled. + 1 + + + + + VDDIOMON_DIS + VDDIO Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes. + 23 + 1 + + + en + Enable if Bandgap is ON (default) + 0 + + + dis + Disabled. + 1 + + + + + VDDIOHMON_DIS + VDDIOH Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes. + 24 + 1 + + + en + Enable if Bandgap is ON (default) + 0 + + + dis + Disabled. + 1 + + + + + VDDBMON_DIS + VDDB Monitor Disable. This bit controls the Power-On Reset monitor on VDDB supply in all operating mods. + 27 + 1 + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + + + LPWKFL0 + Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO0. + 0x04 + + + ALL + Wakeup Flags. + 0 + 31 + + + + + LPWKEN0 + Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0. + 0x08 + + + ALL + Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. + 0 + 31 + + + + + LPWKFL1 + Low Power I/O Wakeup Status Register 1. This register indicates the low power wakeup status for GPIO1. + 0x0C + + + LPWKEN1 + Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup functionality for GPIO1. + 0x10 + + + LPWKFL2 + Low Power I/O Wakeup Status Register 2. This register indicates the low power wakeup status for GPIO2. + 0x14 + + + LPWKEN2 + Low Power I/O Wakeup Enable Register 2. This register enables low power wakeup functionality for GPIO2. + 0x18 + + + LPWKFL3 + Low Power I/O Wakeup Status Register 3. This register indicates the low power wakeup status for GPIO3. + 0x1C + + + LPWKEN3 + Low Power I/O Wakeup Enable Register 3. This register enables low power wakeup functionality for GPIO3. + 0x20 + + + LPPWKFL + Low Power Peripheral Wakeup Status Register. + 0x30 + + + USBLS + USB UTMI Linestate Detect Wakeup Flag (write one to clear). One or both of these bits will be set when the USB bus activity causes the linestate to change and the device to wake while USB wakeup is enabled using PMLUSBWKEN. + 0 + 2 + + + AINCOMP0 + Analog Input Comparator Wakeup Flag. + 4 + 1 + + + USBVBUS + USB VBUS Detect Wakeup Flag (write one to clear). This bit will be set when the USB power supply is powered on or powered off. + 2 + 1 + + + BACKUP + Battery Back Wakeup Flag (write one to clear). This bit will be set when exiting Battery Backup Mode. + 16 + 1 + + + RSTDET + Reset Detect Wakeup Flag (write one to clear). This bit will be set when the external reset causes wakeup + 17 + 1 + + + + + LPPWKEN + Low Power Peripheral Wakeup Enable Register. + 0x34 + + + USBLS + USB UTMI Linestate Detect Wakeup Enable. These bits allow wakeup from the corresponding USB linestate signal (s) on transition (s) from low to high or high to low when PM.USBWKEN is set. + 0 + 2 + + + USBVBUS + USB VBUS Detect Wakeup Enable. This bit allows wakeup from the USB power supply on or off status. + 2 + 1 + + + AINCOMP0 + AINCOMP0 Wakeup Enable. This bit allows wakeup from the AINCOMP0. + 4 + 1 + + + WDT0 + WDT0 Wakeup Enable. This bit allows wakeup from the WDT0. + 8 + 1 + + + WDT1 + WDT1 Wakeup Enable. This bit allows wakeup from the WDT1. + 9 + 1 + + + CPU1 + CPU1 Wakeup Enable. This bit allows wakeup from the CPU1. + 10 + 1 + + + TMR0 + TMR0 Wakeup Enable. This bit allows wakeup from the TMR0. + 11 + 1 + + + TMR1 + TMR1 Wakeup Enable. This bit allows wakeup from the TMR1. + 12 + 1 + + + TMR2 + TMR2 Wakeup Enable. This bit allows wakeup from the TMR2. + 13 + 1 + + + TMR3 + TMR3 Wakeup Enable. This bit allows wakeup from the TMR3. + 14 + 1 + + + TMR4 + TMR4 Wakeup Enable. This bit allows wakeup from the TMR4. + 15 + 1 + + + TMR5 + TMR5 Wakeup Enable. This bit allows wakeup from the TMR5. + 16 + 1 + + + UART0 + UART0 Wakeup Enable. This bit allows wakeup from the UART0. + 17 + 1 + + + UART1 + UART1 Wakeup Enable. This bit allows wakeup from the UART1. + 18 + 1 + + + UART2 + UART2 Wakeup Enable. This bit allows wakeup from the UART2. + 19 + 1 + + + UART3 + UART3 Wakeup Enable. This bit allows wakeup from the UART3. + 20 + 1 + + + I2C0 + I2C0 Wakeup Enable. This bit allows wakeup from the I2C0. + 21 + 1 + + + I2C1 + I2C1 Wakeup Enable. This bit allows wakeup from the I2C1. + 22 + 1 + + + I2C2 + I2C2 Wakeup Enable. This bit allows wakeup from the I2C2. + 23 + 1 + + + I2S + I2S Wakeup Enable. This bit allows wakeup from the I2S. + 24 + 1 + + + SPI1 + SPI1 Wakeup Enable. This bit allows wakeup from the SPI1. + 25 + 1 + + + LPCMP + LPCMP Wakeup Enable. This bit allows wakeup from the LPCMP. + 26 + 1 + + + + + LPMEMSD + Low Power Memory Shutdown Control. + 0x40 + + + RAM0 + System RAM block 0 Shut Down. + 0 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + RAM1 + System RAM block 1 Shut Down. + 1 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + RAM2 + System RAM block 2 Shut Down. + 2 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + RAM3 + System RAM block 3 Shut Down. + 3 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + RAM4 + System RAM block 4 Shut Down. + 4 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + RAM5 + System RAM block 5 Shut Down. + 5 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + ICC + Instruction Cache RAM Shut Down. + 7 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + ICCXIP + XiP Instruction Cache RAM Shut Down. + 8 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + SRCC + System Cache RAM Shut Down. + 9 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + USBFIFO + USB FIFO Shut Down. + 11 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + ROM0 + ROM0 Shut Down. (CPU0 ROM) + 12 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + MEU + MEU MEM Shut Down. + 13 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + ROM1 + ROM1 Shut Down. + 15 + 1 + + + normal + Normal Operating Mode. + 0 + + + shutdown + Shutdown Mode. + 1 + + + + + + + LPVDDPD + Low Power VDD Domain Power Down Control. + 0x44 + + + BTLE + Power Down. + 1 + 1 + + + + + GP0 + General Purpose Register 0 + 0x48 + + + GP1 + General Purpose Register 1 + 0x4C + + + LPWKPOL0A + Low Power Wakeup Polarity Select for GPIO0. + 0x50 + + + 0 + Polarity Select for Wakeup Events for Pin 0. + 0 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 1 + Polarity Select for Wakeup Events for Pin 1. + 2 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 2 + Polarity Select for Wakeup Events for Pin 2. + 4 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 3 + Polarity Select for Wakeup Events for Pin 3. + 6 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 4 + Polarity Select for Wakeup Events for Pin 4. + 8 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 5 + Polarity Select for Wakeup Events for Pin 5. + 10 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 6 + Polarity Select for Wakeup Events for Pin 6. + 12 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 7 + Polarity Select for Wakeup Events for Pin 7. + 14 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 8 + Polarity Select for Wakeup Events for Pin 8. + 16 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 9 + Polarity Select for Wakeup Events for Pin 9. + 18 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 10 + Polarity Select for Wakeup Events for Pin 10. + 20 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 11 + Polarity Select for Wakeup Events for Pin 11. + 22 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 12 + Polarity Select for Wakeup Events for Pin 12. + 24 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 13 + Polarity Select for Wakeup Events for Pin 13. + 26 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 14 + Polarity Select for Wakeup Events for Pin 14. + 28 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 15 + Polarity Select for Wakeup Events for Pin 15. + 30 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + + + LPWKPOL0B + Low Power Wakeup Polarity Select for GPIO0. + 0x54 + + + 16 + Polarity Select for Wakeup Events for Pin 16. + 0 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 17 + Polarity Select for Wakeup Events for Pin 17. + 2 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 18 + Polarity Select for Wakeup Events for Pin 18. + 4 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 19 + Polarity Select for Wakeup Events for Pin 19. + 6 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 20 + Polarity Select for Wakeup Events for Pin 20. + 8 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 21 + Polarity Select for Wakeup Events for Pin 21. + 10 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 22 + Polarity Select for Wakeup Events for Pin 22. + 12 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 23 + Polarity Select for Wakeup Events for Pin 23. + 14 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 24 + Polarity Select for Wakeup Events for Pin 24. + 16 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 25 + Polarity Select for Wakeup Events for Pin 25. + 18 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 26 + Polarity Select for Wakeup Events for Pin 26. + 20 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 27 + Polarity Select for Wakeup Events for Pin 27. + 22 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 28 + Polarity Select for Wakeup Events for Pin 28. + 24 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 29 + Polarity Select for Wakeup Events for Pin 29. + 26 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 30 + Polarity Select for Wakeup Events for Pin 30. + 28 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 31 + Polarity Select for Wakeup Events for Pin 31. + 30 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + + + LPWKPOL1A + Low Power Wakeup Polarity Select for GPIO1. + 0x58 + + + 0 + Polarity Select for Wakeup Events for Pin 0. + 0 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 1 + Polarity Select for Wakeup Events for Pin 1. + 2 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 2 + Polarity Select for Wakeup Events for Pin 2. + 4 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 3 + Polarity Select for Wakeup Events for Pin 3. + 6 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 4 + Polarity Select for Wakeup Events for Pin 4. + 8 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 5 + Polarity Select for Wakeup Events for Pin 5. + 10 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 6 + Polarity Select for Wakeup Events for Pin 6. + 12 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 7 + Polarity Select for Wakeup Events for Pin 7. + 14 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 8 + Polarity Select for Wakeup Events for Pin 8. + 16 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 9 + Polarity Select for Wakeup Events for Pin 9. + 18 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 10 + Polarity Select for Wakeup Events for Pin 10. + 20 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 11 + Polarity Select for Wakeup Events for Pin 11. + 22 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 12 + Polarity Select for Wakeup Events for Pin 12. + 24 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 13 + Polarity Select for Wakeup Events for Pin 13. + 26 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 14 + Polarity Select for Wakeup Events for Pin 14. + 28 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 15 + Polarity Select for Wakeup Events for Pin 15. + 30 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + + + LPWKPOL1B + Low Power Wakeup Polarity Select for GPIO1. + 0x5C + + + 16 + Polarity Select for Wakeup Events for Pin 16. + 0 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 17 + Polarity Select for Wakeup Events for Pin 17. + 2 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 18 + Polarity Select for Wakeup Events for Pin 18. + 4 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 19 + Polarity Select for Wakeup Events for Pin 19. + 6 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 20 + Polarity Select for Wakeup Events for Pin 20. + 8 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 21 + Polarity Select for Wakeup Events for Pin 21. + 10 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 22 + Polarity Select for Wakeup Events for Pin 22. + 12 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 23 + Polarity Select for Wakeup Events for Pin 23. + 14 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 24 + Polarity Select for Wakeup Events for Pin 24. + 16 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 25 + Polarity Select for Wakeup Events for Pin 25. + 18 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 26 + Polarity Select for Wakeup Events for Pin 26. + 20 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 27 + Polarity Select for Wakeup Events for Pin 27. + 22 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 28 + Polarity Select for Wakeup Events for Pin 28. + 24 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 29 + Polarity Select for Wakeup Events for Pin 29. + 26 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 30 + Polarity Select for Wakeup Events for Pin 30. + 28 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 31 + Polarity Select for Wakeup Events for Pin 31. + 30 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + + + LPWKPOL2A + Low Power Wakeup Polarity Select for GPIO2. + 0x60 + + + 0 + Polarity Select for Wakeup Events for Pin 0. + 0 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 1 + Polarity Select for Wakeup Events for Pin 1. + 2 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 2 + Polarity Select for Wakeup Events for Pin 2. + 4 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 3 + Polarity Select for Wakeup Events for Pin 3. + 6 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 4 + Polarity Select for Wakeup Events for Pin 4. + 8 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 5 + Polarity Select for Wakeup Events for Pin 5. + 10 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 6 + Polarity Select for Wakeup Events for Pin 6. + 12 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 7 + Polarity Select for Wakeup Events for Pin 7. + 14 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 8 + Polarity Select for Wakeup Events for Pin 8. + 16 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 9 + Polarity Select for Wakeup Events for Pin 9. + 18 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 10 + Polarity Select for Wakeup Events for Pin 10. + 20 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 11 + Polarity Select for Wakeup Events for Pin 11. + 22 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 12 + Polarity Select for Wakeup Events for Pin 12. + 24 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 13 + Polarity Select for Wakeup Events for Pin 13. + 26 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 14 + Polarity Select for Wakeup Events for Pin 14. + 28 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 15 + Polarity Select for Wakeup Events for Pin 15. + 30 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + + + LPWKPOL2B + Low Power Wakeup Polarity Select for GPIO2. + 0x64 + + + 16 + Polarity Select for Wakeup Events for Pin 16. + 0 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 17 + Polarity Select for Wakeup Events for Pin 17. + 2 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 18 + Polarity Select for Wakeup Events for Pin 18. + 4 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 19 + Polarity Select for Wakeup Events for Pin 19. + 6 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 20 + Polarity Select for Wakeup Events for Pin 20. + 8 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 21 + Polarity Select for Wakeup Events for Pin 21. + 10 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 22 + Polarity Select for Wakeup Events for Pin 22. + 12 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 23 + Polarity Select for Wakeup Events for Pin 23. + 14 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 24 + Polarity Select for Wakeup Events for Pin 24. + 16 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 25 + Polarity Select for Wakeup Events for Pin 25. + 18 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 26 + Polarity Select for Wakeup Events for Pin 26. + 20 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 27 + Polarity Select for Wakeup Events for Pin 27. + 22 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 28 + Polarity Select for Wakeup Events for Pin 28. + 24 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 29 + Polarity Select for Wakeup Events for Pin 29. + 26 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 30 + Polarity Select for Wakeup Events for Pin 30. + 28 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 31 + Polarity Select for Wakeup Events for Pin 31. + 30 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + + + LPWKPOL3 + Low Power Wakeup Polarity Select for GPIO3. + 0x68 + + + 0 + Polarity Select for Wakeup Events for Pin 0. + 0 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 1 + Polarity Select for Wakeup Events for Pin 1. + 2 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 2 + Polarity Select for Wakeup Events for Pin 2. + 4 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 3 + Polarity Select for Wakeup Events for Pin 3. + 6 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 4 + Polarity Select for Wakeup Events for Pin 4. + 8 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 5 + Polarity Select for Wakeup Events for Pin 5. + 10 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 6 + Polarity Select for Wakeup Events for Pin 6. + 12 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + 7 + Polarity Select for Wakeup Events for Pin 7. + 14 + 2 + + + BOTH_EDGES + Both Edges. + 0 + + + RISING + Rising Edge. + 1 + + + FALLING + Falling Edge. + 2 + + + + + + + + + \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/LPCMP/lpcmp_reva.svd b/Libraries/PeriphDrivers/Source/LPCMP/lpcmp_reva.svd index 9cbabd3bed5..0e0856063bb 100644 --- a/Libraries/PeriphDrivers/Source/LPCMP/lpcmp_reva.svd +++ b/Libraries/PeriphDrivers/Source/LPCMP/lpcmp_reva.svd @@ -35,7 +35,7 @@ 1 - INT_EN + INTEN IRQ Enable. 6 1 @@ -47,7 +47,7 @@ 1 - INT_FL + INTFL IRQ Flag 15 1 diff --git a/Libraries/PeriphDrivers/Source/LPCMP/lpcmp_reva_me30.svd b/Libraries/PeriphDrivers/Source/LPCMP/lpcmp_reva_me30.svd new file mode 100644 index 00000000000..9cbabd3bed5 --- /dev/null +++ b/Libraries/PeriphDrivers/Source/LPCMP/lpcmp_reva_me30.svd @@ -0,0 +1,59 @@ + + + + LPCMP + Low Power Comparator + 0x40088000 + + 0x00 + 0x400 + registers + + + LPCMP + Low Power Comparato + 103 + + + + 3 + 4 + CTRL[%s] + Comparator Control Register. + 0x00 + + + EN + Comparator Enable. + 0 + 1 + + + POL + Polarity Select + 5 + 1 + + + INT_EN + IRQ Enable. + 6 + 1 + + + OUT + Raw Compartor Input. + 14 + 1 + + + INT_FL + IRQ Flag + 15 + 1 + + + + + + \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/OWM/owm_reva_me30.svd b/Libraries/PeriphDrivers/Source/OWM/owm_reva_me30.svd new file mode 100644 index 00000000000..8506606fbd7 --- /dev/null +++ b/Libraries/PeriphDrivers/Source/OWM/owm_reva_me30.svd @@ -0,0 +1,237 @@ + + + + OWM + 1-Wire Master Interface. + 0x4003D000 + 32 + read-write + + 0 + 0x1000 + registers + + + OneWire + 67 + + + + + CTRL0 + 1-Wire Master Control Register. + 0x0000 + read-write + + + LL_EN + Enable Long Line Mode. + [0:0] + read-write + + + FPRESDET + Force Line During Presence Detect. + [1:1] + read-write + + + BB_EN + Bit Bang Enable. + [2:2] + read-write + + + EXT_PU_MODE + Provide an extra output control to control an external pullup. + [3:3] + read-write + + + EXT_PU_EN + Enable External Pullup. + [4:4] + read-write + + + SB_EN + Enable Single Bit TX/RX Mode. + [5:5] + read-write + + + OD + Enables overdrive speed for 1-Wire operations. + [6:6] + read-write + + + INT_PU_EN + Enable intenral pullup. + [7:7] + read-write + + + + + + CLKDIV + 1-Wire Master Clock Divisor. + 0x0004 + read-write + + + DIVISOR + Clock Divisor for 1Mhz. + [7:0] + read-write + + + + + + CTRL1 + 1-Wire Master Control/Status. + 0x0008 + read-write + + + RST + Start OW Reset. + [0:0] + read-write + + + SRA_EN + Enable SRA Mode. + [1:1] + read-write + + + BB_OUT_EN + Bit Bang Output Enable. + [2:2] + read-write + + + INPUT_ST + OW Input State. + [3:3] + read-only + + + OD_SPEC_ST + Overdrive Spec Mode. + [4:4] + read-only + + + PRESDET_ST + Presence Pulse Detected. + [7:7] + read-only + + + + + + DATA + 1-Wire Master Data Buffer. + 0x000C + read-write + + + DATA + TX/RX Buffer. + [7:0] + read-write + + + + + + INTFL + 1-Wire Master Interrupt Flags. + 0x0010 + read-write + + + RST_DONE + OW Reset Sequence Completed. + [0:0] + read-write + + + TX_EM + TX Data Empty Interrupt Flag. + [1:1] + read-write + + + RX_RDY + RX Data Ready Interrupt Flag + [2:2] + read-write + + + LINE_SHORT + OW Line Short Detected Interrupt Flag. + [3:3] + read-write + + + LINE_LOW + OW Line Low Detected Interrupt Flag. + [4:4] + read-write + + + + + + INTEN + 1-Wire Master Interrupt Enables. + 0x0014 + read-write + + + RST_DONE + OW Reset Sequence Completed. + [0:0] + read-write + oneToClear + + + TX_EM + Tx Data Empty Interrupt Enable. + [1:1] + read-write + oneToClear + + + RX_RDY + Rx Data Ready Interrupt Enable. + [2:2] + read-write + oneToClear + + + LINE_SHORT + OW Line Short Detected Interrupt Enable. + [3:3] + read-write + oneToClear + + + LINE_LOW + OW Line Low Detected Interrupt Enable. + [4:4] + read-write + oneToClear + + + + + + + \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/RTC/rtc_reva_me30.svd b/Libraries/PeriphDrivers/Source/RTC/rtc_reva_me30.svd new file mode 100644 index 00000000000..bc42bc5c0f1 --- /dev/null +++ b/Libraries/PeriphDrivers/Source/RTC/rtc_reva_me30.svd @@ -0,0 +1,410 @@ + + + + RTC + Real Time Clock and Alarm. + 0x40006000 + + 0x00 + 0x400 + registers + + + RTC + RTC interrupt. + 3 + + + + SEC + RTC Second Counter. This register contains the 32-bit second counter. + 0x00 + 0x00000000 + + + SEC + Seconds Counter. + 0 + 32 + + + + + SSEC + RTC Sub-second Counter. This counter increments at 256Hz. RTC_SEC is incremented when this register rolls over from 0xFF to 0x00. + 0x04 + 0x00000000 + + + SSEC + Sub-Seconds Counter (12-bit). + 0 + 12 + + + + + TODA + Time-of-day Alarm. + 0x08 + 0x00000000 + + + TOD_ALARM + Time-of-day Alarm. + 0 + 20 + + + + + SSECA + RTC sub-second alarm. This register contains the reload value for the sub-second alarm. + 0x0C + 0x00000000 + + + SSEC_ALARM + This register contains the reload value for the sub-second alarm. + 0 + 32 + + + + + CTRL + RTC Control Register. + 0x10 + 0x00000008 + 0xFFFFFF38 + + + EN + Real Time Clock Enable. This bit enables the Real Time Clock. This bit can only be written when WE=1 and BUSY =0. Change to this bit is effective only after BUSY is cleared from 1 to 0. + 0 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + TOD_ALARM_IE + Alarm Time-of-Day Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. + 1 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + SSEC_ALARM_IE + Alarm Sub-second Interrupt Enable. Change to this bit is effective only after BUSY is cleared from 1 to 0. + 2 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + BUSY + RTC Busy. This bit is set to 1 by hardware when changes to RTC registers required a synchronized version of the register to be in place. This bit is automatically cleared by hardware. + 3 + 1 + read-only + + + idle + Idle. + 0 + + + busy + Busy. + 1 + + + + + RDY + RTC Ready. This bit is set to 1 by hardware when the RTC count registers update. It can be cleared to 0 by software at any time. It will also be cleared to 0 by hardware just prior to an update of the RTC count register. + 4 + 1 + + + busy + Register has not updated. + 0 + + + ready + Ready. + 1 + + + + + RDY_IE + RTC Ready Interrupt Enable. + 5 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + TOD_ALARM_IF + Time-of-Day Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. + 6 + 1 + read-only + + + inactive + Not active. + 0 + + + pending + Active. + 1 + + + + + SSEC_ALARM_IF + Sub-second Alarm Interrupt Flag. This alarm is qualified as wake-up source to the processor. + 7 + 1 + read-only + + + inactive + Not active. + 0 + + + pending + Active. + 1 + + + + + SQW_EN + Square Wave Output Enable. + 8 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + SQW_SEL + Frequency Output Selection. When SQE=1, these bits specify the output frequency on the SQW pin. + 9 + 2 + + + freq1Hz + 1 Hz (Compensated). + 0 + + + freq512Hz + 512 Hz (Compensated). + 1 + + + freq4KHz + 4 KHz. + 2 + + + + + RD_EN + Asynchronous Counter Read Enable. + 14 + 1 + + + sync + Synchronous. + 0 + + + async + Asynchronous. + 1 + + + + + WR_EN + Write Enable. This register bit serves as a protection mechanism against unintentional writes to critical RTC bits. + 15 + 1 + + + ignore + Ignored. + 0 + + + allow + Allowed. + 1 + + + + + + + TRIM + RTC Trim Register. + 0x14 + 0x00000000 + + + TRIM + RTC Trim. This register contains the 2's complement value that specifies the trim resolution. Each increment or decrement of the bit adds or subtracts 1ppm at each 4KHz clock value, with a maximum correction of +/- 127ppm. + 0 + 8 + + + VBAT_TMR + VBAT Timer Value. When RTC is running off of VBAT, this field is incremented every 32 seconds. + 8 + 24 + + + + + OSCCTRL + RTC Oscillator Control Register. + 0x18 + 0x00000000 + + + FILTER_EN + Enable Filter. + 0 + 1 + + + IBIAS_SEL + IBIAS Select. + 1 + 1 + + + 2x + 2x + 0 + + + 4x + 4x + 1 + + + + + HYST_EN + RTC Hysteresis Enable. + 2 + 1 + + + IBIAS_EN + RTC IBIAS Enable. + 3 + 1 + + + BYPASS + RTC Crystal Bypass + 4 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + SQW_32K + RTC 32kHz Square Wave Output + 5 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + + + + + \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/SPI/spi_reva_me30.svd b/Libraries/PeriphDrivers/Source/SPI/spi_reva_me30.svd new file mode 100644 index 00000000000..f91d21497cc --- /dev/null +++ b/Libraries/PeriphDrivers/Source/SPI/spi_reva_me30.svd @@ -0,0 +1,1237 @@ + + + + SPI + SPI peripheral. + 0x400BE000 + + 0x00 + 0x1000 + registers + + + SPI0 + 16 + + + + FIFO32 + Register for reading and writing the FIFO. + 0x00 + 32 + read-write + + + DATA + Read to pull from RX FIFO, write to put into TX FIFO. + 0 + 32 + + + + + 2 + 2 + FIFO16[%s] + Register for reading and writing the FIFO. + FIFO32 + 0x00 + 16 + read-write + + + DATA + Read to pull from RX FIFO, write to put into TX FIFO. + 0 + 16 + + + + + 4 + 1 + FIFO8[%s] + Register for reading and writing the FIFO. + FIFO32 + 0x00 + 8 + read-write + + + DATA + Read to pull from RX FIFO, write to put into TX FIFO. + 0 + 8 + + + + + CTRL0 + Register for controlling SPI peripheral. + 0x04 + read-write + + + EN + SPI Enable. + 0 + 1 + + + dis + SPI is disabled. + 0 + + + en + SPI is enabled. + 1 + + + + + MST_MODE + Master Mode Enable. + 1 + 1 + + + dis + SPI is Slave mode. + 0 + + + en + SPI is Master mode. + 1 + + + + + SS_IO + Slave Select 0, IO direction, to support Multi-Master mode,Slave Select 0 can be input in Master mode. This bit has no effect in slave mode. + 4 + 1 + + + output + Slave select 0 is output. + 0 + + + input + Slave Select 0 is input, only valid if MMEN=1. + 1 + + + + + START + Start Transmit. + 5 + 1 + + + start + Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction. + 1 + + + + + SS_CTRL + Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction. + 8 + 1 + + + DEASSERT + SPI De-asserts Slave Select at the end of a transaction. + 0 + + + ASSERT + SPI leaves Slave Select asserted at the end of a transaction. + 1 + + + + + SS_ACTIVE + Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected. + 16 + 4 + + + SS0 + SS0 is selected. + 0x1 + + + SS1 + SS1 is selected. + 0x2 + + + SS2 + SS2 is selected. + 0x4 + + + SS3 + SS3 is selected. + 0x8 + + + + + + + CTRL1 + Register for controlling SPI peripheral. + 0x08 + read-write + + + TX_NUM_CHAR + Nubmer of Characters to transmit. + 0 + 16 + + + RX_NUM_CHAR + Nubmer of Characters to receive. + 16 + 16 + + + + + CTRL2 + Register for controlling SPI peripheral. + 0x0C + read-write + + + CLKPHA + Clock Phase. + 0 + 1 + + + Rising_Edge + Data Sampled on clock rising edge. Use when in SPI Mode 0 and Mode 2 + 0 + + + Falling_Edge + Data Sampled on clock falling edge. Use when in SPI Mode 1 and Mode 3 + 1 + + + + + CLKPOL + Clock Polarity. + 1 + 1 + + + Normal + Normal Clock. Use when in SPI Mode 0 and Mode 1 + 0 + + + Inverted + Inverted Clock. Use when in SPI Mode 2 and Mode 3 + 1 + + + + + SCLK_FB_INV + Clock Polarity. + 4 + 1 + + + Normal + Normal Clock. Use when in SPI Mode 0 and Mode 1 + 0 + + + Inverted + Inverted Clock. Use when in SPI Mode 2 and Mode 3 + 1 + + + + + NUMBITS + Number of Bits per character. + 8 + 4 + + + 16 + 16 bits per character. + 0 + + + 1 + 1 bits per character. + 1 + + + 2 + 2 bits per character. + 2 + + + 3 + 3 bits per character. + 3 + + + 4 + 4 bits per character. + 4 + + + 5 + 5 bits per character. + 5 + + + 6 + 6 bits per character. + 6 + + + 7 + 7 bits per character. + 7 + + + 8 + 8 bits per character. + 8 + + + 9 + 9 bits per character. + 9 + + + 10 + 10 bits per character. + 10 + + + 11 + 11 bits per character. + 11 + + + 12 + 12 bits per character. + 12 + + + 13 + 13 bits per character. + 13 + + + 14 + 14 bits per character. + 14 + + + 15 + 15 bits per character. + 15 + + + + + DATA_WIDTH + SPI Data width. + 12 + 2 + + + Mono + 1 data pin. + 0 + + + Dual + 2 data pins. + 1 + + + Quad + 4 data pins. + 2 + + + + + THREE_WIRE + Three Wire mode. MOSI/MISO pin(s) shared. Only Mono mode suports Four-Wire. + 15 + 1 + + + dis + Use four wire mode (Mono only). + 0 + + + en + Use three wire mode. + 1 + + + + + SSPOL + Slave Select Polarity, each Slave Select can have unique polarity. + 16 + 4 + + + SS0_high + SS0 active high. + 0x1 + + + SS1_high + SS1 active high. + 0x2 + + + SS2_high + SS2 active high. + 0x4 + + + SS3_high + SS3 active high. + 0x8 + + + + + + + SSTIME + Register for controlling SPI peripheral/Slave Select Timing. + 0x10 + read-write + + + PRE + Slave Select Pre delay 1. + 0 + 8 + + + 256 + 256 system clocks between SS active and first serial clock edge. + 0 + + + + + POST + Slave Select Post delay 2. + 8 + 8 + + + 256 + 256 system clocks between last serial clock edge and SS inactive. + 0 + + + + + INACT + Slave Select Inactive delay. + 16 + 8 + + + 256 + 256 system clocks between transactions. + 0 + + + + + + + CLKCTRL + Register for controlling SPI clock rate. + 0x14 + read-write + + + LO + Low duty cycle control. In timer mode, reload[7:0]. + 0 + 8 + + + Dis + Duty cycle control of serial clock generation is disabled. + 0 + + + + + HI + High duty cycle control. In timer mode, reload[15:8]. + 8 + 8 + + + Dis + Duty cycle control of serial clock generation is disabled. + 0 + + + + + CLKDIV + System Clock scale factor. Scales the AMBA clock by 2^SCALE before generating serial clock. + 16 + 4 + + + + + DMA + Register for controlling DMA. + 0x1C + read-write + + + TX_THD_VAL + Transmit FIFO level that will trigger a DMA request, also level for threshold status. When TX FIFO has fewer than this many bytes, the associated events and conditions are triggered. + 0 + 5 + + + TX_FIFO_EN + Transmit FIFO enabled for SPI transactions. + 6 + 1 + + + dis + Transmit FIFO is not enabled. + 0 + + + en + Transmit FIFO is enabled. + 1 + + + + + TX_FLUSH + Clear TX FIFO, clear is accomplished by resetting the read and write + pointers. This should be done when FIFO is not being accessed on the SPI side. + . + 7 + 1 + + + CLEAR + Clear the Transmit FIFO, clears any pending TX FIFO status. + 1 + + + + + TX_LVL + Count of entries in TX FIFO. + 8 + 6 + read-only + + + TX_EN + TX DMA Enable. + 15 + 1 + + + DIS + TX DMA requests are disabled, andy pending DMA requests are cleared. + 0 + + + en + TX DMA requests are enabled. + 1 + + + + + RX_THD_VAL + Receive FIFO level that will trigger a DMA request, also level for threshold status. When RX FIFO has more than this many bytes, the associated events and conditions are triggered. + 16 + 5 + + + RX_FIFO_EN + Receive FIFO enabled for SPI transactions. + 22 + 1 + + + DIS + Receive FIFO is not enabled. + 0 + + + en + Receive FIFO is enabled. + 1 + + + + + RX_FLUSH + Clear RX FIFO, clear is accomplished by resetting the read and write pointers. This should be done when FIFO is not being accessed on the SPI side. + 23 + 1 + + + CLEAR + Clear the Receive FIFO, clears any pending RX FIFO status. + 1 + + + + + RX_LVL + Count of entries in RX FIFO. + 24 + 6 + read-only + + + RX_EN + RX DMA Enable. + 31 + 1 + + + dis + RX DMA requests are disabled, any pending DMA requests are cleared. + 0 + + + en + RX DMA requests are enabled. + 1 + + + + + + + INTFL + Register for reading and clearing interrupt flags. All bits are write 1 to clear. + 0x20 + read-write + + + TX_THD + TX FIFO Threshold Crossed. + 0 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TX_EM + TX FIFO Empty. + 1 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_THD + RX FIFO Threshold Crossed. + 2 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_FULL + RX FIFO FULL. + 3 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + SSA + Slave Select Asserted. + 4 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + SSD + Slave Select Deasserted. + 5 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + FAULT + Multi-Master Mode Fault. + 8 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + ABORT + Slave Abort Detected. + 9 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + MST_DONE + Master Done, set when SPI Master has completed any transactions. + 11 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TX_OV + Transmit FIFO Overrun, set when the AMBA side attempts to write data to a full transmit FIFO. + 12 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TX_UN + Transmit FIFO Underrun, set when the SPI side attempts to read data from an empty transmit FIFO. + 13 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_OV + Receive FIFO Overrun, set when the SPI side attempts to write to a full receive FIFO. + 14 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_UN + Receive FIFO Underrun, set when the AMBA side attempts to read data from an empty receive FIFO. + 15 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + + + INTEN + Register for enabling interrupts. + 0x24 + read-write + + + TX_THD + TX FIFO Threshold interrupt enable. + 0 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + TX_EM + TX FIFO Empty interrupt enable. + 1 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + RX_THD + RX FIFO Threshold Crossed interrupt enable. + 2 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + RX_FULL + RX FIFO FULL interrupt enable. + 3 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + SSA + Slave Select Asserted interrupt enable. + 4 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + SSD + Slave Select Deasserted interrupt enable. + 5 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + FAULT + Multi-Master Mode Fault interrupt enable. + 8 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + ABORT + Slave Abort Detected interrupt enable. + 9 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + MST_DONE + Master Done interrupt enable. + 11 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + TX_OV + Transmit FIFO Overrun interrupt enable. + 12 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + TX_UN + Transmit FIFO Underrun interrupt enable. + 13 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + RX_OV + Receive FIFO Overrun interrupt enable. + 14 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + RX_UN + Receive FIFO Underrun interrupt enable. + 15 + 1 + + + dis + Interrupt is disabled. + 0 + + + en + Interrupt is enabled. + 1 + + + + + + + WKFL + Register for wake up flags. All bits in this register are write 1 to clear. + 0x28 + read-write + + + TX_THD + Wake on TX FIFO Threshold Crossed. + 0 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + TX_EM + Wake on TX FIFO Empty. + 1 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_THD + Wake on RX FIFO Threshold Crossed. + 2 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + RX_FULL + Wake on RX FIFO Full. + 3 + 1 + + + clear + Flag is set when value read is 1. Write 1 to clear this flag. + 1 + + + + + + + WKEN + Register for wake up enable. + 0x2C + read-write + + + TX_THD + Wake on TX FIFO Threshold Crossed Enable. + 0 + 1 + + + dis + Wakeup source disabled. + 0 + + + en + Wakeup source enabled. + 1 + + + + + TX_EM + Wake on TX FIFO Empty Enable. + 1 + 1 + + + dis + Wakeup source disabled. + 0 + + + en + Wakeup source enabled. + 1 + + + + + RX_THD + Wake on RX FIFO Threshold Crossed Enable. + 2 + 1 + + + dis + Wakeup source disabled. + 0 + + + en + Wakeup source enabled. + 1 + + + + + RX_FULL + Wake on RX FIFO Full Enable. + 3 + 1 + + + dis + Wakeup source disabled. + 0 + + + en + Wakeup source enabled. + 1 + + + + + + + STATUS + SPI Status register. + 0x30 + read-only + + + BUSY + SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. + 0 + 1 + + + not + SPI not active. + 0 + + + active + SPI active. + 1 + + + + + + + + + \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/SYS/SVD/fcr_me30.svd b/Libraries/PeriphDrivers/Source/SYS/SVD/fcr_me30.svd new file mode 100644 index 00000000000..eab7c51a325 --- /dev/null +++ b/Libraries/PeriphDrivers/Source/SYS/SVD/fcr_me30.svd @@ -0,0 +1,456 @@ + + + + FCR + Function Control Register. + 0x40000800 + + 0x00 + 0x400 + registers + + + + FCTRL0 + Register 0. + 0x00 + read-write + + + USBCLKSEL + USB External Core Clock Select. + 16 + 1 + + + sys + Generated clock from system clock. + 0 + + + dig + Digital clock from a GPIO. + 1 + + + + + I2C0DGEN0 + I2C0 SDA Glitch Filter Enable. + 20 + 1 + + + dis + Filter disabled. + 0 + + + en + Filter enabled. + 1 + + + + + I2C0DGEN1 + I2C0 SCL Glitch Filter Enable. + 21 + 1 + + + dis + Filter disabled. + 0 + + + en + Filter enabled. + 1 + + + + + I2C1DGEN0 + I2C1 SDA Glitch Filter Enable. + 22 + 1 + + + dis + Filter disabled. + 0 + + + en + Filter enabled. + 1 + + + + + I2C1DGEN1 + I2C1 SCL Glitch Filter Enable. + 23 + 1 + + + dis + Filter disabled. + 0 + + + en + Filter enabled. + 1 + + + + + I2C2ADGEN0 + I2C2 AF2 SDA Glitch Filter Enable. + 24 + 1 + + + dis + Filter disabled. + 0 + + + en + Filter enabled. + 1 + + + + + I2C2ADGEN1 + I2C2 AF2 SCL Glitch Filter Enable. + 25 + 1 + + + dis + Filter disabled. + 0 + + + en + Filter enabled. + 1 + + + + + I2C2BDGEN0 + I2C2 AF3 SDA Glitch Filter Enable. + 26 + 1 + + + dis + Filter disabled. + 0 + + + en + Filter enabled. + 1 + + + + + I2C2BDGEN1 + I2C2 AF3 SCL Glitch Filter Enable. + 27 + 1 + + + dis + Filter disabled. + 0 + + + en + Filter enabled. + 1 + + + + + I2C2CDGEN0 + I2C2 AF4 SDA Glitch Filter Enable + 28 + 1 + + + dis + Filter disabled. + 0 + + + en + Filter enabled. + 1 + + + + + I2C2CDGEN1 + I2C2 AF4 SCL Glitch Filter Enable + 29 + 1 + + + dis + Filter disabled. + 0 + + + en + Filter enabled. + 1 + + + + + + + FCTRL1 + Register 1. + 0x04 + read-write + + + AC_EN + Auto-calibration Enable. + 0 + 1 + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + + + + AC_RUN + Autocalibration Run. + 1 + 1 + + + not + Not Running. + 0 + + + run + Running. + 1 + + + + + LOAD_TRIM + Load Trim. + 2 + 1 + + + GAIN_INV + Invert Gain. + 3 + 1 + + + not + Not Running. + 0 + + + run + Running. + 1 + + + + + ATOMIC + Atomic mode. + 4 + 1 + + + not + Not Running. + 0 + + + run + Running. + 1 + + + + + MU + MU value. + 8 + 12 + + + AC_TRIM + 150MHz HFIO Auto Calibration Trim + 23 + 9 + + + + + FCTRL2 + Register 2. + 0x08 + read-write + + + NFC_FWD_EN + Enabled FWD mode for NFC block + 0 + 1 + + + NFC_CLK_EN + Enabled the NFC blocks clock divider in Analog + 1 + 1 + + + NFC_FWD_TX_DATA_OVR + FWD input for NFC block + 2 + 1 + + + XO_EN_DGL + TBD + 3 + 1 + + + RX_BIAS_PD + Power down enable for NFC receiver analog block + 4 + 1 + + + RX_BIAS_EN + Enable the NFC receiver analog blocks + 5 + 1 + + + RX_TM_VBG_VABUS + TBD + 6 + 1 + + + RX_TM_BIAS + TBD + 7 + 1 + + + NFC_FWD_DOUT + FWD output from FNC block + 8 + 1 + + + + + FCTRL3 + Register 3. + 0x0C + read-write + + + DONECNT + Auto-calibration Done Counter Setting. + 0 + 8 + + + + + GP + General Purpose Register. + 0x1C + read-write + + + GP + General Purpose. + 0 + 32 + + + + + MSRTRIM + MSR Trim Register. + 0x20 + read-write + + + R1 + MSR Trim R1. + 0 + 2 + + + R2 + MSR Trim R2. + 2 + 3 + + + + + FLVFILT + Flash Low Voltage Filter Control Register. + 0x24 + read-write + + + NUM + Defines the number of consecutive samples of FLV status that must be good for ROM to continue. + 0 + 8 + + + RATE + Defines the rate for ROM sampling of the FLV status. + 8 + 8 + + + DELAY + Defines the delay from change in system clock divider until ROM begins filtering process of the FLV status. + 16 + 8 + + + + + + + \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/SYS/SVD/gcfr_me30.svd b/Libraries/PeriphDrivers/Source/SYS/SVD/gcfr_me30.svd new file mode 100644 index 00000000000..884a52161b4 --- /dev/null +++ b/Libraries/PeriphDrivers/Source/SYS/SVD/gcfr_me30.svd @@ -0,0 +1,55 @@ + + + + GCFR + Global Control Function Register. + 0x40005800 + + 0x00 + 0x400 + registers + + + + REG0 + Register 0. + 0x00 + read-write + + + ISO_WUP + ISO Warm Up Value. + 0 + 9 + + + IPO_WUP + IPO Warm Up Value. + 16 + 11 + + + + + REG1 + Register 1. + 0x04 + read-write + + + ERFO_WUP + ERFO Warm Up Value. + 0 + 14 + + + IBRO_WUP + IBRO Warm Up Value. + 16 + 6 + + + + + + \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me30.svd b/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me30.svd new file mode 100644 index 00000000000..56fe920d300 --- /dev/null +++ b/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me30.svd @@ -0,0 +1,2011 @@ + + + + GCR + Global Control Registers. + 0x40000000 + + 0 + 0x400 + registers + + + + SYSCTRL + System Control. + 0x00 + 0xFFFFFFFE + + + BSTAP_EN + Boundary Scan TAP enable. When enabled, the JTAG port is connected to the Boundary Scan TAP. Otherwise, the port is connected to the ARM ICE function. This bit is reset by the POR. Reset value and access depend on the part number. + 0 + 1 + + + dis + Boundary Scan TAP port disabled. + 0 + + + en + Boundary Scan TAP port enabled. + 1 + + + + + SBUSARB + System bus abritration scheme. These bits are used to select between Fixed-burst abritration and Round-Robin scheme. The Round-Robin scheme is selected by default. These bits are reset by the system reset. + 1 + 2 + + + fix + Fixed Burst abritration. + 0 + + + round + Round-robin scheme. + 1 + + + + + FLASH_PAGE_FLIP + Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer. + 4 + 1 + + + normal + Physical layout matches logical layout. + 0 + + + swapped + Bottom half mapped to logical top half and vice versa. + 1 + + + + + FPU_DIS + Cortex M4 Floating Point Disable This bit is used to disable the floating-point unit of the Cortex-M4. + 5 + 1 + + + ICC_FLUSH + Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. + 6 + 1 + + + normal + Normal Code Cache Operation + 0 + + + flush + Code Caches and CPU instruction buffer are flushed + 1 + + + + + SRCC_FLUSH + Data Cache Flush. The system cache (s) will be flushed when this bit is set. + 7 + 1 + + + normal + Normal System Cache Operation + 0 + + + flush + System Cache is flushed + 1 + + + + + SRCC_DIS + Data Cache Disable. The system cache (s) will be completely disabled when this bit is set. + 9 + 1 + + + en + Is enabled. + 0 + + + dis + Is Disabled. + 1 + + + + + CHKRES1 + ROM1 Checksum Result. This bit is only valid when the checksum is done and CCHK1 bit is cleared.. + 11 + 1 + + + complete + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + CCHK1 + Compute ROM1 Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. + 12 + 1 + + + complete + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + CCHK0 + Compute ROM0 Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. + 13 + 1 + + + complete + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + CHKRES0 + ROM0 Checksum Result. This bit is only valid when the checksum is done and CCHK0 bit is cleared.. + 15 + 1 + + + pass + ROM Checksum Correct. + 0 + + + fail + ROM Checksum Fail. + 1 + + + + + OVR + Operating Voltage Range. + 16 + 2 + + + + + RST0 + Reset. + 0x04 + + + DMA + DMA Reset. + 0 + 1 + + + WDT0 + Watchdog Timer Reset. + 1 + 1 + + + GPIO0 + GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states. + 2 + 1 + + + GPIO1 + GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states. + 3 + 1 + + + TMR0 + Timer0 Reset. Setting this bit to 1 resets Timer 0 blocks. + 5 + 1 + + + TMR1 + Timer1 Reset. Setting this bit to 1 resets Timer 1 blocks. + 6 + 1 + + + TMR2 + Timer2 Reset. Setting this bit to 1 resets Timer 2 blocks. + 7 + 1 + + + TMR3 + Timer3 Reset. Setting this bit to 1 resets Timer 3 blocks. + 8 + 1 + + + TMR4 + Timer4 Reset. Setting this bit to 1 resets Timer 4 blocks. + 9 + 1 + + + TMR5 + Timer5 Reset. Setting this bit to 1 resets Timer 5 blocks. + 10 + 1 + + + UART0 + UART0 Reset. Setting this bit to 1 resets all UART 0 blocks. + 11 + 1 + + + UART1 + UART1 Reset. Setting this bit to 1 resets all UART 1 blocks. + 12 + 1 + + + SPI0 + SPI0 Reset. Setting this bit to 1 resets all SPI 0 blocks. + 13 + 1 + + + SPI1 + SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks. + 14 + 1 + + + SPI2 + SPI2 Reset. Setting this bit to 1 resets all SPI 2 blocks. + 15 + 1 + + + I2C0 + I2C0 Reset. + 16 + 1 + + + RTC + Real Time Clock Reset. + 17 + 1 + + + TMR6 + Timer6 Reset. Setting this bit to 1 resets Timer 6 blocks. + 20 + 1 + + + TMR7 + Timer7 Reset. Setting this bit to 1 resets Timer 7 blocks. + 21 + 1 + + + SEMA + Semaphore Reset. + 22 + 1 + + + TRNG + TODO(5-2-2023): Remove this bit before release. TRNG Reset. Setting this bit resets the TRNG block. + 24 + 1 + + + ADC + Analog to Digital Reset. + 26 + 1 + + + UART2 + UART2 Reset. Setting this bit to 1 resets all UART 2 blocks. + 28 + 1 + + + SOFT + Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer. + 29 + 1 + + + PERIPH + Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset. + 30 + 1 + + + SYS + System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer. + 31 + 1 + + + + + CLKCTRL + Clock Control. + 0x08 + 0x00000008 + + + PCLK_DIV + PCLK Divider. + 3 + 3 + + + div1 + Divide by 1. + 0 + + + div2 + Divide by 2. + 1 + + + div4 + Divide by 4. + 2 + + + div8 + Divide by 8. + 3 + + + + + SYSCLK_DIV + Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0. + 6 + 3 + + + div1 + Divide by 1. + 0 + + + div2 + Divide by 2. + 1 + + + div4 + Divide by 4. + 2 + + + div8 + Divide by 8. + 3 + + + div16 + Divide by 16. + 4 + + + div32 + Divide by 32. + 5 + + + div64 + Divide by 64. + 6 + + + div128 + Divide by 128. + 7 + + + + + SYSCLK_SEL + Clock Source Select. This 3 bit field selects the source for the system clock. + 9 + 3 + + + ISO + Internal Secondary Oscilatior Clock + 0 + + + ERFO + 27MHz Crystal is used for the system clock. + 2 + + + INRO + 8kHz Internal Nano Ring Oscillator is used for the system clock. + 3 + + + IPO + The internal Primary oscillator is used for the system clock. + 4 + + + IBRO + The internal Baud Rate oscillator is used for the system clock. + 5 + + + ERTCO + 32kHz is used for the system clock. + 6 + + + + + SYSCLK_RDY + Clock Ready. This read only bit reflects whether the currently selected system clock source is running. + 13 + 1 + read-only + + + busy + Switchover to the new clock source (as selected by CLKSEL) has not yet occurred. + 0 + + + ready + System clock running from CLKSEL clock source. + 1 + + + + + IPO_DIV + IPO clock divider + 14 + 2 + + + DIV1 + Divide 1. + 0 + + + DIV2 + Divide 2. + 1 + + + DIV4 + Divide 4. + 2 + + + DIV8 + Divide 8. + 3 + + + + + ERFO_EN + 27MHz Crystal Oscillator Enable. + 16 + 1 + + + dis + Is Disabled. + 0 + + + en + Is Enabled. + 1 + + + + + ERTCO_EN + 32kHz Crystal Oscillator Enable. + 17 + 1 + + + ISO_EN + 60MHz High Frequency Internal Reference Clock Enable. + 18 + 1 + + + IPO_EN + 96MHz High Frequency Internal Reference Clock Enable. + 19 + 1 + + + IBRO_EN + 8MHz High Frequency Internal Reference Clock Enable. + 20 + 1 + + + IBRO_VS + 7.3728MHz Internal Oscillator Voltage Source Select + 21 + 1 + + + ERFO_RDY + 27MHz Crystal Oscillator Ready + 24 + 1 + read-only + + + not + Is not Ready. + 0 + + + ready + Is Ready. + 1 + + + + + ERTCO_RDY + 32kHz Crystal Oscillator Ready + 25 + 1 + + + ISO_RDY + 60MHz ISO Ready. + 26 + 1 + + + IPO_RDY + Internal Primary Oscillator Ready. + 27 + 1 + + + IBRO_RDY + Internal Baud Rate Oscillator Ready. + 28 + 1 + + + INRO_RDY + Internal Nano Ring Oscillator Low Frequency Reference Clock Ready. + 29 + 1 + + + + + PM + Power Management. + 0x0C + + + MODE + Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode. + 0 + 3 + + + active + Active Mode. + 0 + + + deepsleep + DeepSleep Mode. + 2 + + + shutdown + Shutdown Mode. + 3 + + + backup + Backup Mode. + 4 + + + + + GPIO_WE + GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set. + 4 + 1 + + + RTC_WE + RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers. + 5 + 1 + + + USB_WE + USB Wake Up Enable. This bit enables USB activity as wakeup source. + 6 + 1 + + + ERFO_PD + Radio Frequency oscilator Crystal Power Down. This bit selects the power state in DEEPSLEEP mode. + 12 + 1 + + + active + Mode is Active. + 0 + + + deepsleep + Powered down in DEEPSLEEP. + 1 + + + + + ISO_PD + Internal Secondary Oscilator Power Down. This bit selects the power state in DEEPSLEEP mode. + 15 + 1 + + + active + Mode is Active. + 0 + + + deepsleep + Powered down in DEEPSLEEP. + 1 + + + + + IPO_PD + Internal Primary Oscilatory power down. This bit selects the power state in DEEPSLEEP mode. + 16 + 1 + + + active + Mode is Active. + 0 + + + deepsleep + Powered down in DEEPSLEEP. + 1 + + + + + IBRO_PD + Internal Baud Rate Oscillator power down. This bit selects the power state in DEEPSLEEP mode. + 17 + 1 + + + active + Mode is Active. + 0 + + + deepsleep + Powered down in DEEPSLEEP. + 1 + + + + + ERFO_BP + XTAL Bypass + 20 + 1 + + + normal + Normal + 0 + + + bypass + Bypass + 1 + + + + + + + PCLKDIV + Peripheral Clock Divider. + 0x18 + 0x00000001 + + + ADCFRQ + ADC clock Frequency. These bits define the ADC clock frequency. FADC = FPCLK / (ADCFRQ). + 10 + 4 + + + AONCLKDIV + Always-ON (AON) domain Clock Divider. These bits define the AON domain clock divider. + 14 + 2 + + + DIV4 + PCLK divide by 4. + 0 + + + DIV8 + PCLK divide by 8. + 1 + + + DIV16 + PCLK divide by 16. + 2 + + + DIV32 + PCLK divide by 32. + 3 + + + + + + + PCLKDIS0 + Peripheral Clock Disable. + 0x24 + + + GPIO0 + GPIO0 Clock Disable. + 0 + 1 + + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + GPIO1 + GPIO1 Disable. + 1 + 1 + + + DMA + DMA Disable. + 5 + 1 + + + SPI0 + SPI 0 Disable. + 6 + 1 + + + SPI1 + SPI 1 Disable. + 7 + 1 + + + SPI2 + SPI 2 Disable. + 8 + 1 + + + UART0 + UART 0 Disable. + 9 + 1 + + + UART1 + UART 1 Disable. + 10 + 1 + + + I2C0 + I2C 0 Disable. + 13 + 1 + + + TMR0 + Timer 0 Disable. + 15 + 1 + + + TMR1 + Timer 1 Disable. + 16 + 1 + + + TMR2 + Timer 2 Disable. + 17 + 1 + + + TMR3 + Timer 3 Disable. + 18 + 1 + + + TMR4 + Timer 4 Disable. + 19 + 1 + + + TMR5 + Timer 5 Disable. + 20 + 1 + + + ADC + ADC Disable. + 23 + 1 + + + TMR6 + Timer 6 Disable. + 24 + 1 + + + TMR7 + Timer 7 Disable. + 25 + 1 + + + I2C1 + I2C 1 Disable. + 28 + 1 + + + PT + PT Clock Disable. + 29 + 1 + + + + + MEMCTRL + Memory Clock Control Register. + 0x28 + + + FWS + Flash Wait State. These bits define the number of wait-state cycles per Flash data read access. Minimum wait state is 2. + 0 + 3 + + + SRAM_WS + SRAM Wait State Enable + 4 + 1 + + + ROM1_WS + ROM1 Wait State Enable + 7 + 1 + + + RAM0_WS + System RAM 0 Wait State Enable + 8 + 1 + + + RAM1_WS + System RAM 1 Wait State Enable + 9 + 1 + + + RAM2_WS + System RAM 2 Wait State Enable + 10 + 1 + + + RAM3_WS + System RAM 3 Wait State Enable + 11 + 1 + + + RAM4_WS + System RAM 4 Wait State Enable + 12 + 1 + + + RAM5_WS + System RAM 5 Wait State Enable + 13 + 1 + + + RAM0LS_EN + System RAM 0 Light Sleep Mode. + 16 + 1 + + + active + RAM is active. + 0 + + + light_sleep + RAM is in Light Sleep mode. + 1 + + + + + RAM1LS_EN + System RAM 1 Light Sleep Mode. + 17 + 1 + + + RAM2LS_EN + System RAM 2 Light Sleep Mode. + 18 + 1 + + + RAM3LS_EN + System RAM 3 Light Sleep Mode. + 19 + 1 + + + RAM4LS_EN + System RAM 4 Light Sleep Mode. + 20 + 1 + + + RAM5LS_EN + System RAM 5 Light Sleep Mode. + 21 + 1 + + + ICCLS_EN + ICache RAM Light Sleep Mode. + 24 + 1 + + + ICCXIPLS_EN + ICACHE-XIP RAM Light Sleep Mode. + 25 + 1 + + + SRCCLS_EN + SysCache RAM Light Sleep Mode. + 26 + 1 + + + USBLS_EN + USB FIFO Light Sleep Mode. + 28 + 1 + + + ROM0LS_EN + ROM0 Light Sleep Mode. + 29 + 1 + + + ROM1LS_EN + ROM1 Light Sleep Mode. + 30 + 1 + + + + + MEMZ + Memory Zeroize Control. + 0x2C + + + RAM0 + System RAM Block 0. + 0 + 1 + + + nop + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + RAM1 + System RAM Block 1. + 1 + 1 + + + RAM2 + System RAM Block 2. + 2 + 1 + + + RAM3 + System RAM Block 3. + 3 + 1 + + + RAM4 + System RAM Block 4. + 4 + 1 + + + RAM5 + System RAM Block 5. + 5 + 1 + + + RAM6 + System RAM Block 6. + 6 + 1 + + + ICC + Instruction Cache. + 8 + 1 + + + ICCXIP + Instruction Cache XIP Data and Tag Ram zeroizatoin. + 9 + 1 + + + SRCCDATA + System Cache Data Ram Zeroization. + 10 + 1 + + + SRCCTAG + System Cache Tag Zeroization. + 11 + 1 + + + USBFIFO + USB FIFO Zeroization. + 13 + 1 + + + + + SYSST + System Status Register. + 0x40 + + + ICELOCK + ARM ICE Lock Status. + 0 + 1 + + + unlocked + ICE is unlocked. + 0 + + + locked + ICE is locked. + 1 + + + + + CODEAUTHERR + Code Authentication Error Flag. This bit indicates a code authentication error has occured in XiP interface. + 1 + 1 + + + norm + Normal Operating Condition. + 0 + + + code + Code Integrity Error. + 1 + + + + + DATAAUTHERR + Data Authentication Error Flag. This bit indicates a data authentication error has occured in XiP interface. + 2 + 1 + + + norm + Normal Operating Condition. + 0 + + + code + Code Integrity Error. + 1 + + + + + SCMEMF + System Cache Memory Fault Flag. This bit indicates a memory fault has occured in the System Cache while receiving data from the Hyperbus Interface. + 5 + 1 + + + norm + Normal Operating Condition. + 0 + + + memory + Memory Fault. + 1 + + + + + + + RST1 + Reset 1. + 0x44 + + + I2C1 + I2C1 Reset. + 0 + 1 + + + PT + PT Reset. + 1 + 1 + + + OWIRE + OWIRE Reset. + 7 + 1 + + + WDT1 + WDT1 Reset. + 8 + 1 + + + CRC + CRC Reset. + 9 + 1 + + + AES + AES Reset. + 10 + 1 + + + I2S + I2S Reset. + 13 + 1 + + + AC + AC Reset. + 14 + 1 + + + SEMA + Semaphore Reset. + 16 + 1 + + + I2C2 + I2C2 Reset. + 17 + 1 + + + UART3 + UART3 Reset. + 18 + 1 + + + UART4 + UART4 Reset. + 19 + 1 + + + UART5 + UART5 Reset. + 20 + 1 + + + + + PCLKDIS1 + Peripheral Clock Disable. + 0x48 + + + BTLE + Bluetooth Clock Disable. + 0 + 1 + + + en + Enable. + 0 + + + dis + Disable. + 1 + + + + + UART2 + UART2 Disable. + 1 + 1 + + + en + Enable. + 0 + + + dis + Disable. + 1 + + + + + TRNG + TRNG Disable. + 2 + 1 + + + WDT0 + WDT0 Clock Disable + 4 + 1 + + + WDT1 + WDT1 Clock Disable + 5 + 1 + + + SRCC + System Cache Clock Disable. + 7 + 1 + + + SEMA + Semaphore Clock Disable. + 9 + 1 + + + OWIRE + One-Wire Clock Disable. + 13 + 1 + + + CRC + CRC Clock Disable. + 14 + 1 + + + AES + AES Clock Disable. + 15 + 1 + + + I2S + I2S Clock Disable. + 16 + 1 + + + I2C2 + I2C2 Clock Disable + 21 + 1 + + + UART3 + UART3 Clock Disable + 22 + 1 + + + UART4 + UART4 Clock Disable + 23 + 1 + + + UART5 + UART5 Clock Disable + 24 + 1 + + + + + EVENTEN + Event Enable Register. + 0x4C + + + DMA + Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode. + 0 + 1 + + + RX + Enable RXEV pin event. When this bit is set, a logic high of GPIO0[24] will cause an RXEV event to wake the CPU from WFE sleep mode. + 1 + 1 + + + TX + Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO[25]. + 2 + 1 + + + + + REVISION + Revision Register. + 0x50 + read-only + + + REVISION + Manufacturer Chip Revision. + 0 + 16 + + + + + SYSINTEN + System Status Interrupt Enable Register. + 0x54 + + + ICEUNLOCK + ARM ICE Unlock Interrupt Enable. + 0 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + CIE + Code Integrity Error Interrupt Enable. + 1 + 1 + + + SCMF + System Cache Memory Fault Interrupt Enable. + 5 + 1 + + + + + IPOCNT + IPO Warmup Count Register. + 0x58 + + + WMUPCNT + TBD + 0 + 10 + + + + + ECCERR + ECC Error Register + 0x64 + + + RAM0 + ECC System RAM0 Error Flag. Write 1 to clear. + 0 + 1 + + + RAM1 + ECC System RAM1 Error Flag. Write 1 to clear. + 1 + 1 + + + RAM2 + ECC System RAM2 Error Flag. Write 1 to clear. + 2 + 1 + + + RAM3 + ECC System RAM3 Error Flag. Write 1 to clear. + 3 + 1 + + + RAM4 + ECC System RAM4 Error Flag. Write 1 to clear. + 4 + 1 + + + RAM5 + ECC System RAM5 Error Flag. Write 1 to clear. + 5 + 1 + + + ICC + ECC Icache0 Error Flag. Write 1 to clear. + 8 + 1 + + + ICCXIP + ECC SFCC Instruction Cache Error Flag. Write 1 to clear. + 10 + 1 + + + FLASH + ECC Flash0 Error Flag. Write 1 to clear. + 11 + 1 + + + + + ECCCED + ECC Not Double Error Detect Register + 0x68 + + + RAM0 + ECC System RAM0 Error Flag. Write 1 to clear. + 0 + 1 + + + RAM1 + ECC System RAM1 Not Double Error Detect. Write 1 to clear. + 1 + 1 + + + RAM2 + ECC System RAM2 Not Double Error Detect. Write 1 to clear. + 2 + 1 + + + RAM3 + ECC System RAM3 Not Double Error Detect. Write 1 to clear. + 3 + 1 + + + RAM4 + ECC System RAM4 Not Double Error Detect. Write 1 to clear. + 4 + 1 + + + RAM5 + ECC System RAM5 Not Double Error Detect. Write 1 to clear. + 5 + 1 + + + ICC + ECC Icache0 Not Double Error Detect. Write 1 to clear. + 8 + 1 + + + ICCXIP + ECC IcacheXIP Not Double Error Detect. Write 1 to clear. + 10 + 1 + + + FLASH + ECC Flash0 Not Double Error Detect. Write 1 to clear. + 11 + 1 + + + + + ECCINTEN + ECC Interrupt Enable Register + 0x6C + + + RAM0 + ECC System RAM0 Interrupt Enable. + 0 + 1 + + + RAM1 + ECC System RAM1 Interrupt Enable. + 1 + 1 + + + RAM2 + ECC System RAM2 Interrupt Enable. + 2 + 1 + + + RAM3 + ECC System RAM3 Interrupt Enable. + 3 + 1 + + + RAM4 + ECC System RAM4 Interrupt Enable. + 4 + 1 + + + RAM5 + ECC System RAM5 Interrupt Enable. + 5 + 1 + + + ICC + ECC Icache0 Interrupt Enable. + 8 + 1 + + + ICCXIP + ECC IcacheXIP Interrupt Enable. + 10 + 1 + + + FLASH + ECC Flash0 Interrupt Enable. + 11 + 1 + + + + + ECCADDR + ECC Error Address Register + 0x70 + + + DADDR + Address of Error in Data RAM. + 0 + 14 + + + DB + Data Bank, + 14 + 1 + + + DE + Data Error Flag. + 15 + 1 + + + TADDR + Address of Error in Tag RAM. + 16 + 14 + + + TB + Tag Bank. + 30 + 1 + + + TE + Tag Error Flag. + 31 + 1 + + + + + BTLELDOCTRL + BTLE LDO Control Register + 0x74 + + + TX_EN + LDOTX enable. + 0 + 1 + + + TX_PD_EN + LDOTX Pull Down. + 1 + 1 + + + TX_VSEL + Voltage Selection for NFC LDO + 2 + 2 + + + RX_EN + LDORX enable. + 4 + 1 + + + RX_PD_EN + LDORX Pull DOwn. + 5 + 1 + + + RX_VSEL + LDORX Voltage Setting. + 6 + 2 + + + RX_BP_EN + LDORX Bypass Enable. + 8 + 1 + + + RX_DISCH + LDORX Discharge. + 9 + 1 + + + TX_BP_EN + LDOTX Bypass Enable. + 10 + 1 + + + TX_DISCH + LDOTX Discharge. + 11 + 1 + + + TX_EN_DLY + LDOTX Enable Delay. + 12 + 1 + + + RX_EN_DLY + LDORX Enable Delay. + 13 + 1 + + + RX_BP_EN_DLY + LDORX Bypass Enable Delay. + 14 + 1 + + + TX_BP_EN_DLY + LDOTX Bypass Enable Delay. + 15 + 1 + + + + + BTLELDODLY + BTLE LDO Delay Register + 0x78 + + + BP_CNT + Bypass delay count. + 0 + 8 + + + RX_CNT + RX delay count. + 8 + 9 + + + TX_CNT + TX delay count. + 20 + 9 + + + + + FLVRST + Flash Low Voltage Reset Control Register + 0x80 + + + EN + Flash Low Voltage Reset Enable. + 0 + 1 + + + + + FLVCLKCTRL + Flash Low Voltage Clock Control Register + 0x84 + + + DIV + Flash Low Voltage Clock Divider Select. + 0 + 2 + + + 512 + Divide 512. + 0 + + + 256 + Divide 256 + 1 + + + 128 + Divide 128 + 2 + + + 64 + Divide 64 + 3 + + + + + + + FLVSTAT + Flash Low Voltage Status Register + 0x88 + + + FLV + Live Flash Low Voltage Detect Status. + 0 + 1 + + + ONES + FLV Buffer contains all ones if supply is above safe operating range. + 6 + 1 + + + ZEROS + FLV Buffer contains all zeros if supply is below safe operating voltage. + 7 + 1 + + + ONES_FL + Sticky version of ONES status. Write 1 to clear. + 14 + 1 + + + ZEROS_FL + Sticky version of ZEROS status. Write 1 to clear. + 15 + 1 + + + BUF + 10 Sample History of FLV status. + 16 + 10 + + + + + + \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/SYS/SVD/lpgcr_me30.svd b/Libraries/PeriphDrivers/Source/SYS/SVD/lpgcr_me30.svd new file mode 100644 index 00000000000..d7305e020bc --- /dev/null +++ b/Libraries/PeriphDrivers/Source/SYS/SVD/lpgcr_me30.svd @@ -0,0 +1,127 @@ + + + + LPGCR + Low Power Global Control. + 0x40080000 + + 0x00 + 0x400 + registers + + + + RST + Low Power Reset Register. + 0x08 + + + GPIO2 + Low Power GPIO 2 Reset. + 0 + 1 + + reset + read-write + + reset_done + Reset complete. + 0 + + + busy + Starts Reset or indicates reset in progress. + 1 + + + + + WDT1 + Low Power Watchdog Timer 1 Reset. + 1 + 1 + + + TMR4 + Low Power Timer 4 Reset. + 2 + 1 + + + TMR5 + Low Power Timer 5 Reset. + 3 + 1 + + + UART3 + Low Power UART 3 Reset. + 4 + 1 + + + LPCOMP + Low Power Comparator Reset. + 6 + 1 + + + + + PCLKDIS + Low Power Peripheral Clock Disable Register. + 0x0C + + + GPIO2 + Low Power GPIO 2 Clock Disable. + 0 + 1 + + + en + enable it. + 0 + + + dis + disable it. + 1 + + + + + WDT1 + Low Power Watchdog 1 Clock Disable. + 1 + 1 + + + TMR4 + Low Power Timer 4 Clock Disable. + 2 + 1 + + + TMR5 + Low Power Timer 5 Clock Disable. + 3 + 1 + + + UART3 + Low Power UART 3 Clock Disable. + 4 + 1 + + + LPCOMP + Low Power Comparator Clock Disable. + 6 + 1 + + + + + + diff --git a/Libraries/PeriphDrivers/Source/SYS/SVD/mcr_me30.svd b/Libraries/PeriphDrivers/Source/SYS/SVD/mcr_me30.svd new file mode 100644 index 00000000000..070e1b59547 --- /dev/null +++ b/Libraries/PeriphDrivers/Source/SYS/SVD/mcr_me30.svd @@ -0,0 +1,410 @@ + + + + MCR + Misc Control. + 0x40006C00 + + 0x00 + 0x400 + registers + + + + ECCEN + ECC Enable Register + 0x00 + + + RAM0 + ECC System RAM0 Enable. + 0 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + + + IPOTRIM + IPO Manual Trim Register + 0x04 + + + VAL + Manual Trim Value. + 0 + 8 + + + RANGE + Trim Range Select. + 8 + 1 + + + + + OUTEN + Output Enable Register. + 0x08 + + + SQWOUT_EN + Square Wave Output Enable. + 0 + 1 + + + PDOWN_EN + Power Down Output Enable. + 1 + 1 + + + + + CMP_CTRL + Comparator Control Register. + 0x0C + + + EN + Comparator Enable. + 0 + 1 + + + POL + Polarity Select + 5 + 1 + + + INTR_EN + IRQ Enable. + 6 + 1 + + + OUT + Comparator Output State. + 14 + 1 + + + INTR_FL + IRQ Flag + 15 + 1 + + + + + CTRL + Control Register + 0x10 + + + CMP_HYST + Comparator hysteresis control. + 0 + 2 + + + INRO_EN + INRO Enable. + 2 + 1 + + + ERTCO_EN + ERTCO Enable. + 3 + 1 + + + IBRO_EN + IBRO Enable. + 4 + 1 + + + ERTCO_LP_EN + Enable 32K Oscillator input. + 5 + 1 + + + PADPUP_RST + Enable the Reset Pad Pull Up Resistors + 9 + 1 + + + 1m + 1MOhm Pullup + 0 + + + 25k + 25kOhm Pullup. + 1 + + + + + PADVDDIOHSEL_RST + Reset VIDDIOH Select. + 10 + 1 + + + + + RTCRST + Reset Register. + 0x18 + + + RTC + RTC Reset. + 0 + 1 + + + + + RTCTRIM + RTC Trim Register. + 0x1C + + + X1 + RTC Trim X1. + 0 + 5 + + + X2 + RTC Trim X2. + 8 + 5 + + + + + GPIO3_CTRL + GPIO3 Pin Control Register. + 0x20 + + + P30_OUT + GPIO3 Pin 0 Data Output. + 0 + 1 + + + P30_OUTEN + GPIO3 Pin 0 Output Enable. + 1 + 1 + + + P30_PUPEN + GPIO3 Pin 0 Pull-up Enable. + 2 + 1 + + + P30_IN + GPIO3 Pin 0 Input Status. + 3 + 1 + + + P31_OUT + GPIO3 Pin 1 Data Output. + 4 + 1 + + + P31_OUTEN + GPIO3 Pin 1 Output Enable. + 5 + 1 + + + P31_PUPEN + GPIO3 Pin 1 Pull-up Enable. + 6 + 1 + + + P31_IN + GPIO3 Pin 1 Input Status. + 7 + 1 + + + + + LDOCTRL + LDO Control Register. + 0x60 + + + 0P9V_EN + LDO 0.9V Enable. + 0 + 1 + + + + + PWRMONST + LDO Control Register. + 0x64 + + + PORZ_VLOSS + Sticky bit indicating power-on status of core power domains of VDDIO, VDDIOH, VCOR + 0 + 1 + + + PORZ_VBAT + Sticky bit indicating power-on status of the battery. + 1 + 1 + + + PORZ_VBB + Sticky bit indicating power-on status of the VBB. + 2 + 1 + + + PORZ_VDDCA + Sticky bit indicating power-on status of VAON_SW supply. + 4 + 1 + + + PORZ_VDDCB + Sticky bit indicating power-on status of VCORE_PAD supply. + 5 + 1 + + + PORZ_VDDA + Sticky bit indicating power-on status of VDDA (for analog) supply. + 6 + 1 + + + PORZ_VDDB + Sticky bit indicating power-on status of VDDB (for USB) supply. + 7 + 1 + + + RSTZ_VDDCB + Sticky bit indicating reset condition on VCORE supply. + 9 + 1 + + + RSTZ_VDDA + Sticky bit indicating reset condition on VDDA (analog) supply. + 10 + 1 + + + RSTZ_VDDB + Sticky bit indicating reset condition on VDDB (USB) supply. + 11 + 1 + + + RSTZ_VDDIO + Sticky bit indicating reset condition on VDDIO supply. + 12 + 1 + + + RSTZ_VDDIOH + Sticky bit indicating reset condition on VDDIOH supply. + 13 + 1 + + + RSTZ_VBB + Sticky bit indicating reset condition on VBB supply. + 14 + 1 + + + RSTZ_LDO0P9V + Sticky bit indicating reset condition on 0.9V USB supply. + 16 + 1 + + + RSTZ_VDDCA + Sticky bit indicating reset condition on VCORE in Analog supply. + 17 + 1 + + + RSTZ_VCOREHV + Sticky bit indicating high voltage reset condition on VCORE supply. + 18 + 1 + + + RSTZ_VDDIOHV + Sticky bit indicating high voltage reset condition on VDDIO supply. + 19 + 1 + + + RSTZ_VDDIOHHV + Sticky bit indicating high voltage reset condition on VDDIOH supply. + 20 + 1 + + + RSTZ_VNFCRX + Sticky bit indicating reset condition on VNFCRX supply. + 21 + 1 + + + RSTZ_VNFCTX + Sticky bit indicating reset condition on VNFCTX supply. + 22 + 1 + + + RSTZ_VNFC1V + Sticky bit indicating reset condition on VNFC1V supply. + 23 + 1 + + + + + + + \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me30.svd b/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me30.svd new file mode 100644 index 00000000000..ea62f38cbb2 --- /dev/null +++ b/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me30.svd @@ -0,0 +1,202 @@ + + + + SIR + System Initialization Registers. + 0x40000400 + read-only + + 0x00 + 0x400 + registers + + + + SISTAT + System Initialization Status Register. + 0x00 + read-only + + + MAGIC + Magic Word Validation. This bit is set by the system initialization block following power-up. + 0 + 1 + read-only + + read + + magicNotSet + Magic word was not set (OTP has not been initialized properly). + 0 + + + magicSet + Magic word was set (OTP contains valid settings). + 1 + + + + + CRCERR + CRC Error Status. This bit is set by the system initialization block following power-up. + 1 + 1 + read-only + + read + + noError + No CRC errors occurred during the read of the OTP memory block. + 0 + + + error + A CRC error occurred while reading the OTP. The address of the failure location in the OTP memory is stored in the ERRADDR register. + 1 + + + + + + + ADDR + Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1). + 0x04 + read-only + + + ERRADDR + 0 + 32 + + + + + BTLELDOTRIM + BTLE LDO Trim register. + 0x48 + read-write + + + TX + TX LDO trim value. + 0 + 5 + read-write + + + RX + RX LDO trim value. + 8 + 5 + read-write + + + + + FSTAT + funcstat register. + 0x100 + read-only + + + FPU + FPU Function. + 0 + 1 + + + no + 0 + + + yes + 1 + + + + + ADC + 10-bit Sigma Delta ADC. + 2 + 1 + + + no + 0 + + + yes + 1 + + + + + SEMA + Semaphore function. + 7 + 1 + + + no + 0 + + + yes + 1 + + + + + + + SFSTAT + Security function status register. + 0x104 + read-only + + + SECBOOT + Security Boot. + 0 + 1 + + + TRNG + TRNG Function. + 2 + 1 + + + no + 0 + + + yes + 1 + + + + + AES + AES Block. + 3 + 1 + + + no + 0 + + + yes + 1 + + + + + + + + + \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/SYS/SVD/trimsir_me30.svd b/Libraries/PeriphDrivers/Source/SYS/SVD/trimsir_me30.svd new file mode 100644 index 00000000000..570df3a73d5 --- /dev/null +++ b/Libraries/PeriphDrivers/Source/SYS/SVD/trimsir_me30.svd @@ -0,0 +1,181 @@ + + + + TRIMSIR + Trim System Initilazation Registers + 0x40005400 + + 0x00 + 0x400 + registers + + + + RTC + RTC Trim System Initialization Register. + 0x08 + + + X1TRIM + RTC X1 Trim. + 16 + 5 + + + X2TRIM + RTC X2 Trim. + 21 + 5 + + + LOCK + Lock. + 31 + 1 + + + + + SIMO + SIMO Trim System Initialization Register. + 0x34 + read-only + + + CLKDIV + SIMO Clock Divide. + 0 + 3 + + + DIV1 + 0 + + + DIV16 + 1 + + + DIV32 + 3 + + + DIV64 + 5 + + + DIV128 + 7 + + + + + + + IPOLO + IPO Low Trim System Initialization Register. + 0x3C + read-only + + + IPO_LIMITLO + IPO Low Limit Trim. + 0 + 8 + + + + + CTRL + Control Trim System Initialization Register. + 0x40 + + + VDDA_LIMITLO + VDDA Low Trim Limit. + 0 + 7 + + + VDDA_LIMITHI + VDDA High Trim Limit. + 8 + 7 + + + IPO_LIMITHI + IPO High Trim Limit. + 15 + 9 + + + INRO_SEL + INRO Clock Select. + 24 + 2 + + + 8KHZ + 0 + + + 16KHZ + 1 + + + 30KHZ + 2 + + + + + INRO_TRIM + INRO Clock Trim. + 29 + 3 + + + + + INRO + RTC Trim System Initialization Register. + 0x44 + + + TRIM16K + INRO 16KHz Trim. + 0 + 3 + + + TRIM30K + INRO 30KHz Trim. + 3 + 3 + + + LPCLKSEL + INRO Low Power Mode Clock Select. + 6 + 2 + + + 8KHZ + 0 + + + 16KHZ + 1 + + + 30KHZ + 2 + + + + + + + + + \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/TMR/tmr_reva_me30.svd b/Libraries/PeriphDrivers/Source/TMR/tmr_reva_me30.svd new file mode 100644 index 00000000000..9a0fe80a4a6 --- /dev/null +++ b/Libraries/PeriphDrivers/Source/TMR/tmr_reva_me30.svd @@ -0,0 +1,313 @@ + + + + TMR0 + 32-bit reloadable timer that can be used for timing and event counting. + Timers + 0x40010000 + + 0x00 + 0x1000 + registers + + + TMR0 + TMR0 IRQ + 5 + + + + CNT + Count. This register stores the current timer count. + 0x00 + 0x00000001 + + + COUNT + Count. + 0 + 32 + + + + + CMP + Compare. This register stores the compare value, which is used to set the maximum count value to initiate a reload of the timer to 0x0001. + 0x04 + 0x0000FFFF + + + COMPARE + Compare. + 0 + 32 + + + + + PWM + PWM. This register stores the value that is compared to the current timer count. + 0x08 + + + PWM + PWM + 0 + 32 + + + + + INTFL + Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt. + 0x0C + oneToClear + + + IRQ + Clear Interrupt. + 0 + 1 + + + + + CTRL + Timer Control Register. + 0x10 + + + MODE + Timer Mode. + 0 + 3 + + + oneShot + One Shot Mode. + 0 + + + continuous + Continuous Mode. + 1 + + + counter + Counter Mode. + 2 + + + pwm + PWM Mode. + 3 + + + capture + Capture Mode. + 4 + + + compare + Compare Mode. + 5 + + + gated + Gated Mode. + 6 + + + captureCompare + Capture/Compare Mode. + 7 + + + + + CLKDIV + Prescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock, F_CNT_CLK = PCLK (HZ) /prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres[2:0]. + 3 + 3 + + + div1 + Divide by 1. + 0 + + + div2 + Divide by 2. + 1 + + + div4 + Divide by 4. + 2 + + + div8 + Divide by 8. + 3 + + + div16 + Divide by 16. + 4 + + + div32 + Divide by 32. + 5 + + + div64 + Divide by 64. + 6 + + + div128 + Divide by 128. + 7 + + + + + POL + Timer input/output polarity bit. + 6 + 1 + + + activeHi + Active High. + 0 + + + activeLo + Active Low. + 1 + + + + + EN + Timer Enable. + 7 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + CLKDIV3 + MSB of prescaler value. + 8 + 1 + + + PWMSYNC + Timer PWM Synchronization Mode Enable. + 9 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + NOLHPOL + Timer PWM output 0A polarity bit. + 10 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + NOLLPOL + Timer PWM output 0A' polarity bit. + 11 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + PWMCKBD + Timer PWM output 0A Mode Disable. + 12 + 1 + + + dis + Disable. + 1 + + + en + Enable. + 0 + + + + + + + NOLCMP + Timer Non-Overlapping Compare Register. + 0x14 + + + LO + Non-overlapping Low Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A and next rising edge of PWM output 0A'. + 0 + 8 + + + HI + Non-overlapping High Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A' and next rising edge of PWM output 0A. + 8 + 8 + + + + + + + \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/TRNG/trng_revc_me30.svd b/Libraries/PeriphDrivers/Source/TRNG/trng_revc_me30.svd new file mode 100644 index 00000000000..e7184d78a60 --- /dev/null +++ b/Libraries/PeriphDrivers/Source/TRNG/trng_revc_me30.svd @@ -0,0 +1,349 @@ + + + + TRNG + Random Number Generator. + 0x4004D000 + + 0x00 + 0x1000 + registers + + + TRNG + TRNG interrupt. + 4 + + + + CTRL + TRNG Control Register. + 0x00 + 0x00000003 + + + OD_HEALTH + Start On-Demand health test. + 0 + 1 + + + RND_IE + To enable IRQ generation when a new 32-bit Random number is ready. + 1 + 1 + + + disable + Disable + 0 + + + enable + Enable + 1 + + + + + HEALTH_IE + Enable IRQ generation when a health test fails. + 2 + 1 + + + AESKG_MEU + Generate and transfer 256 bit MEU key to AES Key storage. + 3 + 1 + + + AESKG_MEMPROT_XIP + Generate and transfer 128 bit MEMPROT_XIP key to AES key storage. + 4 + 1 + + + AESKG_MEMPROT_DIP + Generate and transfer 128 bit MEMPROT_DIP key to AES key storage. + 5 + 1 + + + OD_ROMON + Start ring oscillator monitor on demand test. + 6 + 1 + + + OD_EE + Start entropy estimator on demand test. + 7 + 1 + + + ROMON_EE_FOE + Ring Oscillator Monitors and Entropy Estimator Freeze on Error. + 8 + 1 + + + ROMON_EE_FOD + Ring Oscillator Monitors and Entropy Estimator Freeze on Done. + 9 + 1 + + + EBLS + Entropy Bit Load Select. + 10 + 1 + + + KEYWIPE + To wipe the Battery Backed key. + 15 + 1 + + + GET_TERO_CNT + Get Tero Count. + 16 + 1 + + + EE_DONE_IE + Entropy Estimator Done Interrupt Enable. + 23 + 1 + + + ROMON_DIS + Ring Oscillator Disable. + 24 + 3 + + + RO_0 + Ring Oscillator 0. + 1 + + + RO_1 + Ring Oscillator 1. + 2 + + + RO_2 + Ring Oscillator 2. + 4 + + + + + ROMON_DIV2 + Divide ring by 2. + 28 + 3 + + + RO_0 + Ring Oscillator 0. + 0 + + + RO_1 + Ring Oscillator 1. + 1 + + + RO_2 + Ring Oscillator 2. + 2 + + + + + + + STATUS + Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000. + 0x04 + + + RDY + 32-bit random data is ready to read from TRNG_DATA register. Reading TRNG_DATA when RND_RDY=0 will return all 0's. IRQ is generated when RND_RDY=1 if TRNG_CN.RND_IRQ_EN=1. + 0 + 1 + + + Busy + TRNG Busy + 0 + + + Ready + 32 bit random data is ready + 1 + + + + + OD_HEALTH + On-Demand health test status. + 1 + 1 + + + HEALTH + Health test status. + 2 + 1 + + + SRCFAIL + Entropy source has failed. + 3 + 1 + + + AES_KEYGEN + AESKGD. + 4 + 1 + + + OD_ROMON + On demand ring oscillator test status. + 6 + 1 + + + OD_EE + On demand entropy estimator status. + 7 + 1 + + + PP_ERR + Post process error. + 8 + 1 + + + ROMON_0_ERR + Ring Oscillator 0 Monitor Error. + 9 + 1 + + + ROMON_1_ERR + Ring Oscillator 1 Monitor Error. + 10 + 1 + + + ROMON_2_ERR + Ring Oscillator 2 Monitor Error. + 11 + 1 + + + EE_ERR_THR + Entropy Estimator Threshold Error. + 12 + 1 + + + EE_ERR_OOB + Entropy Estimator Out of Bounds Error.. + 13 + 1 + + + EE_ERR_LOCK + Entropy Estimator Lock Error. + 14 + 1 + + + TERO_CNT_RDY + TERO Count Ready. + 16 + 1 + + + RC_ERR + Repetition Count Error. + 17 + 1 + + + AP_ERR + Adaptive Proportion Error. + 18 + 1 + + + DATA_DONE + Data register has been loaded with at least 32 new entropy bits. + 19 + 1 + + + DATA_NIST_DONE + Data NIST register has been loaded with at least 32 new entropy bits. + 20 + 1 + + + HEALTH_DONE + Health Test Done. + 21 + 1 + + + ROMON_DONE + Ring Oscillator Monitor Test Done. + 22 + 1 + + + EE_DONE + Entropy Estimator Test Done. + 23 + 1 + + + + + DATA + Data. The content of this register is valid only when RNG_IS = 1. When TRNG is disabled, read returns 0x0000 0000. + 0x08 + read-only + + + DATA + Data. The content of this register is valid only when RNG_IS =1. When TNRG is disabled, read returns 0x0000 0000. + 0 + 32 + + + + + DATA_NIST + Data NIST Register. + 0x38 + + + DATA + Ring Oscillator 1 Monitor Last Ring Oscillator Count. + 0 + 32 + + + + + + + \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/UART/uart_revb_me30.svd b/Libraries/PeriphDrivers/Source/UART/uart_revb_me30.svd new file mode 100644 index 00000000000..12971e73f4a --- /dev/null +++ b/Libraries/PeriphDrivers/Source/UART/uart_revb_me30.svd @@ -0,0 +1,482 @@ + + + + UART + UART Low Power Registers + 0x40042000 + + 0x00 + 0x1000 + registers + + + + CTRL + Control register + 0x0000 + + + RX_THD_VAL + This field specifies the depth of receive FIFO for interrupt generation (value 0 and > 16 are ignored) + 0 + 4 + + + PAR_EN + Parity Enable + 4 + 1 + + + PAR_EO + when PAREN=1 selects odd or even parity odd is 1 even is 0 + 5 + 1 + + + PAR_MD + Selects parity based on 1s or 0s count (when PAREN=1) + 6 + 1 + + + CTS_DIS + CTS Sampling Disable + 7 + 1 + + + TX_FLUSH + Flushes the TX FIFO buffer. This bit is automatically cleared by hardware when flush is completed. + 8 + 1 + + + RX_FLUSH + Flushes the RX FIFO buffer. This bit is automatically cleared by hardware when flush is completed. + 9 + 1 + + + CHAR_SIZE + Selects UART character size + 10 + 2 + + + 5bits + 5 bits + 0 + + + 6bits + 6 bits + 1 + + + 7bits + 7 bits + 2 + + + 8bits + 8 bits + 3 + + + + + STOPBITS + Selects the number of stop bits that will be generated + 12 + 1 + + + HFC_EN + Enables/disables hardware flow control + 13 + 1 + + + RTS_NEG + The condition to negate RTS in HFC mode. + 14 + 1 + + + CLK_EN + Baud clock enable + 15 + 1 + + + CLK_SEL + To select the UART clock source for the UART engine (except APB registers). Secondary clock (used for baud rate generator) can be asynchronous from APB clock. + 16 + 2 + + + Peripheral_Clock + apb clock + 0 + + + External_Clock + Clock 1 + 1 + + + CLK2 + Clock 2 + 2 + + + CLK3 + Clock 3 + 3 + + + + + CLK_RDY + Baud clock Ready read only bit + 19 + 1 + + + CLK_GATE + UART Clock Auto Gating mode + 20 + 1 + + + + + STATUS + Status register + 0x0004 + read-only + + + TX_BUSY + Read-only flag indicating the UART transmit status + 0 + 1 + + + RX_BUSY + Read-only flag indicating the UART receiver status + 1 + 1 + + + RX_EM + Read-only flag indicating the RX FIFO state + 4 + 1 + + + RX_FULL + Read-only flag indicating the RX FIFO state + 5 + 1 + + + TX_EM + Read-only flag indicating the TX FIFO state + 6 + 1 + + + TX_FULL + Read-only flag indicating the TX FIFO state + 7 + 1 + + + RX_LVL + Indicates the number of bytes currently in the RX FIFO (0-RX FIFO_ELTS) + 8 + 4 + + + TX_LVL + Indicates the number of bytes currently in the TX FIFO (0-TX FIFO_ELTS) + 12 + 4 + + + + + INTEN + Interrupt Enable control register + 0x0008 + + + RX_FERR + Enable Interrupt For RX Frame Error + 0 + 1 + + + RX_PAR + Enable Interrupt For RX Parity Error + 1 + 1 + + + CTS_EV + Enable Interrupt For CTS signal change Error + 2 + 1 + + + RX_OV + Enable Interrupt For RX FIFO Overrun Error + 3 + 1 + + + RX_THD + Enable Interrupt For RX FIFO reaches the number of bytes configured by RXTHD + 4 + 1 + + + TX_OB + Enable Interrupt For TX FIFO when only one byte is remaining. + 5 + 1 + + + TX_HE + Enable Interrupt For TX FIFO has half empty + 6 + 1 + + + RX_FULL + Enable for RX FIFO Full interrupt. + 7 + 1 + + + + + INTFL + Interrupt status flags Control register + 0x000C + + + RX_FERR + Flag for RX Frame Error Interrupt. + 0 + 1 + + + RX_PAR + Flag for RX Parity Error interrupt + 1 + 1 + + + CTS_EV + Flag for CTS signal change interrupt (hardware flow control disabled) + 2 + 1 + + + RX_OV + Flag for RX FIFO Overrun interrupt + 3 + 1 + + + RX_THD + Flag for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field + 4 + 1 + + + TX_OB + Flag for interrupt when TX FIFO has only one byte is remaining. + 5 + 1 + + + TX_HE + Flag for interrupt when TX FIFO is half empty + 6 + 1 + + + RX_FULL + Flag for full RX FIFO. + 7 + 1 + + + + + CLKDIV + Clock Divider register + 0x0010 + + + CLKDIV + Baud rate divisor value + 0 + 20 + + + + + OSR + Over Sampling Rate register + 0x0014 + + + OSR + OSR + 0 + 3 + + + + + TXPEEK + TX FIFO Output Peek register + 0x0018 + + + DATA + Read TX FIFO next data. Reading from this field does not affect the contents of TX FIFO. Note that the parity bit is available from this field. + 0 + 8 + + + + + PIN + Pin register + 0x001C + + + CTS + Current sampled value of CTS IO + 0 + 1 + read-only + + + RTS + This bit controls the value to apply on the RTS IO. If set to 1, the RTS IO is set to high level. If set to 0, the RTS IO is set to low level. + 1 + 1 + + + + + FIFO + FIFO Read/Write register + 0x0020 + + + DATA + Load/unload location for TX and RX FIFO buffers. + 0 + 8 + + + RX_PAR + Parity error flag for next byte to be read from FIFO. + 8 + 1 + + + + + DMA + DMA Configuration register + 0x0030 + + + TX_THD_VAL + TX FIFO Level DMA Trigger If the TX FIFO level is less than this value, then the TX FIFO DMA interface will send a signal to system DMA to notify that TX FIFO is ready to receive data from memory. + 0 + 4 + + + TX_EN + TX DMA channel enable + 4 + 1 + + + RX_THD_VAL + Rx FIFO Level DMA Trigger If the RX FIFO level is greater than this value, then the RX FIFO DMA interface will send a signal to the system DMA to notify that RX FIFO has characters to transfer to memory. + 5 + 4 + + + RX_EN + RX DMA channel enable + 9 + 1 + + + + + WKEN + Wake up enable Control register + 0x0034 + + + RX_NE + Wake-Up Enable for RX FIFO Not Empty + 0 + 1 + + + RX_FULL + Wake-Up Enable for RX FIFO Full + 1 + 1 + + + RX_THD + Wake-Up Enable for RX FIFO Threshold Met + 2 + 1 + + + + + WKFL + Wake up Flags register + 0x0038 + + + RX_NE + Wake-Up Flag for RX FIFO Not Empty + 0 + 1 + + + RX_FULL + Wake-Up Flag for RX FIFO Full + 1 + 1 + + + RX_THD + Wake-Up Flag for RX FIFO Threshold Met + 2 + 1 + + + + + + + \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/WUT/wut_reva_me30.svd b/Libraries/PeriphDrivers/Source/WUT/wut_reva_me30.svd new file mode 100644 index 00000000000..e9c590e8b98 --- /dev/null +++ b/Libraries/PeriphDrivers/Source/WUT/wut_reva_me30.svd @@ -0,0 +1,261 @@ + + + + WUT + 32-bit reloadable timer that can be used for timing and wakeup. + 0x40006400 + + 0x00 + 0x400 + registers + + + WUT + WUT IRQ + 1 + + + + CNT + Count. This register stores the current timer count. + 0x00 + 0x00000001 + + + COUNT + Timer Count Value. + 0 + 32 + + + + + CMP + Compare. This register stores the compare value, which is used to set the maximum count value to initiate a reload of the timer to 0x0001. + 0x04 + 0x0000FFFF + + + COMPARE + Timer Compare Value. + 0 + 32 + + + + + INTR + Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt. + 0x0C + oneToClear + + + IF_CLR + Clear Interrupt. + 0 + 1 + + + + + CTRL + Timer Control Register. + 0x10 + + + TMODE + Timer Mode. + 0 + 3 + + + oneShot + One Shot Mode. + 0 + + + continuous + Continuous Mode. + 1 + + + counter + Counter Mode. + 2 + + + capture + Capture Mode. + 4 + + + compare + Compare Mode. + 5 + + + gated + Gated Mode. + 6 + + + captureCompare + Capture/Compare Mode. + 7 + + + + + PRES + Prescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock, F_CNT_CLK = PCLK(HZ)/prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres[2:0]. + 3 + 3 + + + div1 + Divide by 1. + 0 + + + div2 + Divide by 2. + 1 + + + div4 + Divide by 4. + 2 + + + div8 + Divide by 8. + 3 + + + div16 + Divide by 16. + 4 + + + div32 + Divide by 32. + 5 + + + div64 + Divide by 64. + 6 + + + div128 + Divide by 128. + 7 + + + + + TPOL + Timer input/output polarity bit. + 6 + 1 + + + activeHi + Active High. + 0 + + + activeLo + Active Low. + 1 + + + + + TEN + Timer Enable. + 7 + 1 + + + dis + Disable. + 0 + + + en + Enable. + 1 + + + + + PRES3 + MSB of prescaler value. + 8 + 1 + + + + + NOLCMP + Timer Non-Overlapping Compare Register. + 0x14 + + + NOL_LO + Non-overlapping Low Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A and next rising edge of PWM output 0A'. + 0 + 8 + + + NOL_HI + Non-overlapping High Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A' and next rising edge of PWM output 0A. + 8 + 8 + + + + + PRESET + Preset register. + 0x18 + + + PRESET + Preset Value. + 0 + 32 + + + + + RELOAD + Reload register. + 0x1C + + + RELOAD + Rerload Value. + 0 + 32 + + + + + SNAPSHOT + Snapshot register. + 0x20 + + + SNAPSHOT + Snapshot Value. + 0 + 32 + + + + + + + \ No newline at end of file From 3befb1374bbe3809144632870820f023ef1be5f3 Mon Sep 17 00:00:00 2001 From: Woo Date: Thu, 18 Apr 2024 18:19:02 -0500 Subject: [PATCH 04/93] Update copyrights --- Libraries/CMSIS/Device/Maxim/MAX32657/Include/adc_regs.h | 3 +-- Libraries/CMSIS/Device/Maxim/MAX32657/Include/aes_regs.h | 3 +-- Libraries/CMSIS/Device/Maxim/MAX32657/Include/aeskeys_regs.h | 3 +-- Libraries/CMSIS/Device/Maxim/MAX32657/Include/crc_regs.h | 3 +-- Libraries/CMSIS/Device/Maxim/MAX32657/Include/dma_regs.h | 3 +-- Libraries/CMSIS/Device/Maxim/MAX32657/Include/dvs_regs.h | 3 +-- Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h | 3 +-- Libraries/CMSIS/Device/Maxim/MAX32657/Include/flc_regs.h | 3 +-- Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcfr_regs.h | 3 +-- Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h | 3 +-- Libraries/CMSIS/Device/Maxim/MAX32657/Include/gpio_regs.h | 3 +-- Libraries/CMSIS/Device/Maxim/MAX32657/Include/i2c_regs.h | 3 +-- Libraries/CMSIS/Device/Maxim/MAX32657/Include/i2s_regs.h | 3 +-- Libraries/CMSIS/Device/Maxim/MAX32657/Include/icc_regs.h | 3 +-- Libraries/CMSIS/Device/Maxim/MAX32657/Include/lpcmp_regs.h | 3 +-- Libraries/CMSIS/Device/Maxim/MAX32657/Include/lpgcr_regs.h | 3 +-- Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h | 3 +-- Libraries/CMSIS/Device/Maxim/MAX32657/Include/mcr_regs.h | 3 +-- Libraries/CMSIS/Device/Maxim/MAX32657/Include/owm_regs.h | 3 +-- Libraries/CMSIS/Device/Maxim/MAX32657/Include/pt_regs.h | 3 +-- Libraries/CMSIS/Device/Maxim/MAX32657/Include/ptg_regs.h | 3 +-- Libraries/CMSIS/Device/Maxim/MAX32657/Include/pwrseq_regs.h | 3 +-- Libraries/CMSIS/Device/Maxim/MAX32657/Include/rtc_regs.h | 3 +-- Libraries/CMSIS/Device/Maxim/MAX32657/Include/sema_regs.h | 3 +-- Libraries/CMSIS/Device/Maxim/MAX32657/Include/simo_regs.h | 3 +-- Libraries/CMSIS/Device/Maxim/MAX32657/Include/sir_regs.h | 3 +-- Libraries/CMSIS/Device/Maxim/MAX32657/Include/spi_regs.h | 3 +-- Libraries/CMSIS/Device/Maxim/MAX32657/Include/tmr_regs.h | 3 +-- Libraries/CMSIS/Device/Maxim/MAX32657/Include/trimsir_regs.h | 3 +-- Libraries/CMSIS/Device/Maxim/MAX32657/Include/trng_regs.h | 3 +-- Libraries/CMSIS/Device/Maxim/MAX32657/Include/uart_regs.h | 3 +-- Libraries/CMSIS/Device/Maxim/MAX32657/Include/wdt_regs.h | 3 +-- Libraries/CMSIS/Device/Maxim/MAX32657/Include/wut_regs.h | 3 +-- 33 files changed, 33 insertions(+), 66 deletions(-) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/adc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/adc_regs.h index 6d6cdedabdf..5aca6094603 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/adc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/adc_regs.h @@ -7,9 +7,8 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/aes_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/aes_regs.h index 36a59717548..a962a06aa33 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/aes_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/aes_regs.h @@ -7,9 +7,8 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/aeskeys_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/aeskeys_regs.h index d028c716491..b6aad12ae7f 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/aeskeys_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/aeskeys_regs.h @@ -7,9 +7,8 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/crc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/crc_regs.h index 55311ca4a68..ccc0b8580ec 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/crc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/crc_regs.h @@ -7,9 +7,8 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/dma_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/dma_regs.h index 5517794c3af..5b0da7826bd 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/dma_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/dma_regs.h @@ -7,9 +7,8 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/dvs_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/dvs_regs.h index 42bfde14fd3..e5ba963cb40 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/dvs_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/dvs_regs.h @@ -7,9 +7,8 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h index 42eead07591..4056241705b 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h @@ -7,9 +7,8 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/flc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/flc_regs.h index fff8fabef3a..8d836a20ebb 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/flc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/flc_regs.h @@ -7,9 +7,8 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcfr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcfr_regs.h index 41c304907d5..f236a45c322 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcfr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcfr_regs.h @@ -7,9 +7,8 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h index efd1e4aa891..c97e6f8a1ff 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h @@ -7,9 +7,8 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gpio_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gpio_regs.h index f7f759f9ed1..ef90a433d21 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gpio_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gpio_regs.h @@ -7,9 +7,8 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/i2c_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/i2c_regs.h index aa4ae41c411..f7ffa96e1d0 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/i2c_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/i2c_regs.h @@ -7,9 +7,8 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/i2s_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/i2s_regs.h index c211a8e56e0..a7fedc7b89c 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/i2s_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/i2s_regs.h @@ -7,9 +7,8 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/icc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/icc_regs.h index 9ed18f4a4ef..f0a8875caa5 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/icc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/icc_regs.h @@ -7,9 +7,8 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/lpcmp_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/lpcmp_regs.h index fd1c04b8994..36c3ebe616c 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/lpcmp_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/lpcmp_regs.h @@ -7,9 +7,8 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/lpgcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/lpgcr_regs.h index 44381a1e7e3..3c2208e5125 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/lpgcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/lpgcr_regs.h @@ -7,9 +7,8 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h index eb008889d52..5b0b5aac2f1 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h @@ -5,9 +5,8 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mcr_regs.h index 0fb91c5f55b..940b3a29cc9 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mcr_regs.h @@ -7,9 +7,8 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/owm_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/owm_regs.h index 99c5b7e3ea8..4255e2b88fa 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/owm_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/owm_regs.h @@ -7,9 +7,8 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/pt_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/pt_regs.h index 1ad7f8b27bd..7ad2723ef21 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/pt_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/pt_regs.h @@ -7,9 +7,8 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/ptg_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/ptg_regs.h index 7510105d626..1ec3278293e 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/ptg_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/ptg_regs.h @@ -7,9 +7,8 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/pwrseq_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/pwrseq_regs.h index 31e6bfe4f4f..dde66e8e51f 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/pwrseq_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/pwrseq_regs.h @@ -7,9 +7,8 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/rtc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/rtc_regs.h index ea62c7fcf93..25aa4e768f7 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/rtc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/rtc_regs.h @@ -7,9 +7,8 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sema_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sema_regs.h index 66bc71ba2a6..7f287a2aa3e 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sema_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sema_regs.h @@ -7,9 +7,8 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/simo_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/simo_regs.h index 36b8ea3e8bc..b074a335739 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/simo_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/simo_regs.h @@ -7,9 +7,8 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sir_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sir_regs.h index d40d745b137..2ac0507b884 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sir_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sir_regs.h @@ -7,9 +7,8 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spi_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spi_regs.h index 870c3678174..9b102e01b95 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spi_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spi_regs.h @@ -7,9 +7,8 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/tmr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/tmr_regs.h index 3847c923c3f..a8284bef628 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/tmr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/tmr_regs.h @@ -7,9 +7,8 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trimsir_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trimsir_regs.h index ebbc38c19dc..e2e0d459f58 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trimsir_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trimsir_regs.h @@ -7,9 +7,8 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trng_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trng_regs.h index ae81696390d..dd27efe9605 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trng_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trng_regs.h @@ -7,9 +7,8 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/uart_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/uart_regs.h index b2d9d1c0114..ac3b2350dfa 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/uart_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/uart_regs.h @@ -7,9 +7,8 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/wdt_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/wdt_regs.h index 5e9bceab6dd..78193302071 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/wdt_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/wdt_regs.h @@ -7,9 +7,8 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/wut_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/wut_regs.h index e9f2a5f84bd..a3aef1ef3c2 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/wut_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/wut_regs.h @@ -7,9 +7,8 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. From 319d6dc1f95777df0c53f35cdb1e4f7e834ef27e Mon Sep 17 00:00:00 2001 From: Woo Date: Thu, 18 Apr 2024 18:22:25 -0500 Subject: [PATCH 05/93] Update LPCMP names --- .../CMSIS/Device/Maxim/MAX32657/Include/lpcmp_regs.h | 9 ++++----- .../CMSIS/Device/Maxim/MAX32657/Include/max32657.svd | 4 ++-- Libraries/PeriphDrivers/Source/LPCMP/lpcmp_reva_me30.svd | 4 ++-- 3 files changed, 8 insertions(+), 9 deletions(-) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/lpcmp_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/lpcmp_regs.h index 36c3ebe616c..209995cb182 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/lpcmp_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/lpcmp_regs.h @@ -7,7 +7,6 @@ /****************************************************************************** * - * Analog Devices, Inc.), * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -98,14 +97,14 @@ typedef struct { #define MXC_F_LPCMP_CTRL_POL_POS 5 /**< CTRL_POL Position */ #define MXC_F_LPCMP_CTRL_POL ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_POL_POS)) /**< CTRL_POL Mask */ -#define MXC_F_LPCMP_CTRL_INT_EN_POS 6 /**< CTRL_INT_EN Position */ -#define MXC_F_LPCMP_CTRL_INT_EN ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_INT_EN_POS)) /**< CTRL_INT_EN Mask */ +#define MXC_F_LPCMP_CTRL_INTR_EN_POS 6 /**< CTRL_INTR_EN Position */ +#define MXC_F_LPCMP_CTRL_INTR_EN ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_INTR_EN_POS)) /**< CTRL_INTR_EN Mask */ #define MXC_F_LPCMP_CTRL_OUT_POS 14 /**< CTRL_OUT Position */ #define MXC_F_LPCMP_CTRL_OUT ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_OUT_POS)) /**< CTRL_OUT Mask */ -#define MXC_F_LPCMP_CTRL_INT_FL_POS 15 /**< CTRL_INT_FL Position */ -#define MXC_F_LPCMP_CTRL_INT_FL ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_INT_FL_POS)) /**< CTRL_INT_FL Mask */ +#define MXC_F_LPCMP_CTRL_INTR_FL_POS 15 /**< CTRL_INTR_FL Position */ +#define MXC_F_LPCMP_CTRL_INTR_FL ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_INTR_FL_POS)) /**< CTRL_INTR_FL Mask */ /**@} end of group LPCMP_CTRL_Register */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd index 6278f7f4a3a..1c1771d0ff7 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd @@ -7460,7 +7460,7 @@ 1 - INT_EN + INTR_EN IRQ Enable. 6 1 @@ -7472,7 +7472,7 @@ 1 - INT_FL + INTR_FL IRQ Flag 15 1 diff --git a/Libraries/PeriphDrivers/Source/LPCMP/lpcmp_reva_me30.svd b/Libraries/PeriphDrivers/Source/LPCMP/lpcmp_reva_me30.svd index 9cbabd3bed5..c6d4b776bd3 100644 --- a/Libraries/PeriphDrivers/Source/LPCMP/lpcmp_reva_me30.svd +++ b/Libraries/PeriphDrivers/Source/LPCMP/lpcmp_reva_me30.svd @@ -35,7 +35,7 @@ 1 - INT_EN + INTR_EN IRQ Enable. 6 1 @@ -47,7 +47,7 @@ 1 - INT_FL + INTR_FL IRQ Flag 15 1 From b2d3100f7362afc66511c706b96a9a47f129d396 Mon Sep 17 00:00:00 2001 From: Woo Date: Wed, 24 Apr 2024 15:31:03 -0500 Subject: [PATCH 06/93] Initial passthrough for max32657.h --- .../Device/Maxim/MAX32657/Include/max32657.h | 792 +++++++++++++++++- 1 file changed, 787 insertions(+), 5 deletions(-) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h index 5b0b5aac2f1..1f467259de5 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h @@ -22,10 +22,792 @@ * ******************************************************************************/ -#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_MAX32657_H_ -#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_MAX32657_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_MAX32657_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_MAX32657_H_ -// TODO(ME30): Top-level device header file -// TODO(ME30): Place max32657.svd file next to this one +#ifndef TARGET_NUM +#define TARGET_NUM 32657 +#endif -#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32660_INCLUDE_MAX32660_H_ +#define MXC_NUMCORES 1 + +#include + +#ifndef FALSE +#define FALSE (0) +#endif + +#ifndef TRUE +#define TRUE (1) +#endif + +/* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */ +#if defined(__GNUC__) +#ifndef __weak +#define __weak __attribute__((weak)) +#endif + +#elif defined(__CC_ARM) + +#define inline __inline +#pragma anon_unions + +#endif + +/* ================================================================================ */ +/* ================== Interrupt Number Table Section ================== */ +/* ================================================================================ */ + +// clang-format off +typedef enum { + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + MemoryManagement_IRQn = -12, + BusFault_IRQn = -11, + UsageFault_IRQn = -10, + SVCall_IRQn = -5, + DebugMonitor_IRQn = -4, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + + /* Device-specific interrupt sources (external to ARM core) */ + /* table entry number */ + /* |||| */ + /* |||| table offset address */ + /* vvvv vvvvvv */ + + MSP_IRQn = 0, /* 0x10 0x0040 16: MSP Initial Value */ + Reset_IRQn, /* 0x11 0x0044 17: Reset */ + RSV02_IRQn, /* 0x12 0x0048 18: Reserved */ + RTC_IRQn, /* 0x13 0x004C 19: RTC */ + TRNG_IRQn, /* 0x14 0x0050 20: True Random Number Generator */ + TMR0_IRQn, /* 0x15 0x0054 21: Timer 0 */ + TMR1_IRQn, /* 0x16 0x0058 22: Timer 1 */ + TMR2_IRQn, /* 0x17 0x005C 23: Timer 2 */ + TMR3_IRQn, /* 0x18 0x0060 24: Timer 3 */ + TMR4_IRQn, /* 0x19 0x0064 25: Timer 4 (LP) */ + TMR5_IRQn, /* 0x1A 0x0068 26: Timer 5 (LP) */ + RSV11_IRQn, /* 0x1B 0x006C 27: Reserved */ + RSV12_IRQn, /* 0x1C 0x0070 28: Reserved */ + I3C_IRQn, /* 0x1D 0x0074 29: I3C */ + UART_IRQn, /* 0x1E 0x0078 30: UART */ + RSV15_IRQn, /* 0x1F 0x007C 31: Reserved */ + RSV16_IRQn, /* 0x20 0x0080 32: Reserved */ + RSV17_IRQn, /* 0x21 0x0084 33: Reserved */ + RSV18_IRQn, /* 0x22 0x0088 34: Reserved */ + RSV19_IRQn, /* 0x23 0x008C 35: Reserved */ + RSV20_IRQn, /* 0x24 0x0090 36: Reserved */ + RSV21_IRQn, /* 0x25 0x0094 37: Reserved */ + RSV22_IRQn, /* 0x26 0x0098 38: Reserved */ + FLC_IRQn, /* 0x27 0x009C 39: Flash Controller */ + GPIO0_IRQn, /* 0x28 0x00A0 40: GPIO0 */ + RSV25_IRQn, /* 0x29 0x00A4 41: Reserved */ + RSV26_IRQn, /* 0x2A 0x00A8 42: Reserved */ + RSV27_IRQn, /* 0x2B 0x00AC 43: Reserved */ + DMA0_IRQn, /* 0x2C 0x00B0 44: DMA0 */ + DMA1_IRQn, /* 0x2D 0x00B4 45: DMA1 */ + DMA2_IRQn, /* 0x2E 0x00B8 46: DMA2 */ + DMA3_IRQn, /* 0x2F 0x00BC 47: DMA3 */ + RSV32_IRQn, /* 0x30 0x00C0 48: Reserved */ + RSV33_IRQn, /* 0x31 0x00C4 49: Reserved */ + RSV34_IRQn, /* 0x32 0x00C8 50: Reserved */ + RSV35_IRQn, /* 0x33 0x00CC 51: Reserved */ + RSV36_IRQn, /* 0x34 0x00D0 52: Reserved */ + RSV37_IRQn, /* 0x35 0x00D4 53: Reserved */ + RSV38_IRQn, /* 0x36 0x00D8 54: Reserved */ + BTLE_TX_DONE_IRQn, /* 0x37 0x00DC 55: BTLE TX Done */ + BTLE_RX_RCVD_IRQn, /* 0x38 0x00E0 56: BTLE RX Received */ + BTLE_RX_ENG_DET_IRQn, /* 0x39 0x00E4 57: BTLE RX Energy Detected */ + BTLE_SFD_DET_IRQn, /* 0x3A 0x00E8 58: BTLE SFD Detected */ + BTLE_SFD_TO_IRQn, /* 0x3B 0x00EC 59: BTLE SFD Timeout*/ + BTLE_GP_EVENT_IRQn, /* 0x3C 0x00F0 60: BTLE Timestamp*/ + BTLE_CFO_IRQn, /* 0x3D 0x00F4 61: BTLE CFO Done */ + BTLE_SIG_DET_IRQn, /* 0x3E 0x00F8 62: BTLE Signal Detected */ + BTLE_AGC_EVENT_IRQn, /* 0x3F 0x00FC 63: BTLE AGC Event */ + BTLE_RFFE_SPIM_IRQn, /* 0x40 0x0100 64: BTLE RFFE SPIM Done */ + BTLE_TX_AES_IRQn, /* 0x41 0x0104 65: BTLE TX AES Done */ + BTLE_RX_AES_IRQn, /* 0x42 0x0108 66: BTLE RX AES Done */ + BTLE_INV_APB_ADDR_IRQn, /* 0x43 0x010C 67: BTLE Invalid APB Address*/ + BTLE_IQ_DATA_VALID_IRQn, /* 0x44 0x0110 68: BTLE IQ Data Valid */ + WUT0_IRQn, /* 0x45 0x0114 69: Wakeup Timer 0 */ + GPIOWAKE_IRQn, /* 0x46 0x0118 70: GPIO Wakeup */ + RSV55_IRQn, /* 0x47 0x011C 71: Reserved */ + SPI_IRQn, /* 0x48 0x0120 72: SPI */ + RSV57_IRQn, /* 0x49 0x0124 73: Reserved */ + RSV58_IRQn, /* 0x4A 0x0128 74: Reserved */ + RSV59_IRQn, /* 0x4B 0x012C 75: Reserved */ + RSV60_IRQn, /* 0x4C 0x0130 76: Reserved */ + RSV61_IRQn, /* 0x4D 0x0134 77: Reserved */ + RSV62_IRQn, /* 0x4E 0x0138 78: Reserved */ + RSV63_IRQn, /* 0x4F 0x013C 79: Reserved */ + RSV64_IRQn, /* 0x50 0x0140 80: Reserved */ + RSV65_IRQn, /* 0x51 0x0144 81: Reserved */ + RSV66_IRQn, /* 0x52 0x0148 82: Reserved */ + RSV67_IRQn, /* 0x53 0x014C 83: Reserved */ + RSV68_IRQn, /* 0x54 0x0150 84: Reserved */ + RSV69_IRQn, /* 0x55 0x0154 85: Reserved */ + RSV70_IRQn, /* 0x56 0x0158 86: Reserved */ + RSV71_IRQn, /* 0x57 0x015C 87: Reserved */ + RSV72_IRQn, /* 0x58 0x0160 88: Reserved */ + RSV73_IRQn, /* 0x59 0x0164 89: Reserved */ + RSV74_IRQn, /* 0x5A 0x0168 90: Reserved */ + RSV75_IRQn, /* 0x5B 0x016C 91: Reserved */ + RSV76_IRQn, /* 0x5C 0x0170 92: Reserved */ + RSV77_IRQn, /* 0x5D 0x0174 93: Reserved */ + RSV78_IRQn, /* 0x5E 0x0178 94: Reserved */ + RSV79_IRQn, /* 0x5F 0x017C 95: Reserved */ + RSV80_IRQn, /* 0x60 0x0180 96: Reserved */ + RSV81_IRQn, /* 0x61 0x0184 97: Reserved */ + RSV82_IRQn, /* 0x62 0x0188 98: Reserved */ + RSV83_IRQn, /* 0x63 0x018C 99: Reserved */ + RSV84_IRQn, /* 0x64 0x0190 100: Reserved */ + RSV85_IRQn, /* 0x65 0x0194 101: Reserved */ + RSV86_IRQn, /* 0x66 0x0198 102: Reserved */ + RSV87_IRQn, /* 0x67 0x019C 103: Reserved */ + RSV88_IRQn, /* 0x68 0x01A0 104: Reserved */ + RSV89_IRQn, /* 0x69 0x01A4 105: Reserved */ + RSV90_IRQn, /* 0x6A 0x01A8 106: Reserved */ + RSV91_IRQn, /* 0x6B 0x01AC 107: Reserved */ + RSV92_IRQn, /* 0x6C 0x01B0 108: Reserved */ + RSV93_IRQn, /* 0x6D 0x01B4 109: Reserved */ + RSV94_IRQn, /* 0x6E 0x01B8 110: Reserved */ + RSV95_IRQn, /* 0x6F 0x01BC 111: Reserved */ + RSV96_IRQn, /* 0x70 0x01C0 112: Reserved */ + AES_IRQn, /* 0x71 0x01C4 113: AES */ + RSV98_IRQn, /* 0x72 0x01C8 114: Reserved */ + RSV99_IRQn, /* 0x73 0x01CC 115: Reserved */ + RSV100_IRQn, /* 0x74 0x01D0 116: Reserved */ + RSV101_IRQn, /* 0x75 0x01D4 117: Reserved */ + RSV102_IRQn, /* 0x76 0x01D8 118: Reserved */ + RSV103_IRQn, /* 0x77 0x01Dc 119: Reserved */ + RSV104_IRQn, /* 0x78 0x01E0 120: Reserved */ + RSV105_IRQn, /* 0x79 0x01E4 121: Reserved */ + RSV106_IRQn, /* 0x7A 0x01E8 122: Reserved */ + RSV107_IRQn, /* 0x7B 0x01EC 123: Reserved */ + RSV108_IRQn, /* 0x7C 0x01F0 124: Reserved */ + WUT1_IRQn, /* 0x7D 0x01F4 125: ERFO Ready/WUT 1 */ + MXC_IRQ_EXT_COUNT, +} IRQn_Type; +// clang-format on + +#define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16) + +/* ================================================================================ */ +/* ================== Processor Section ================== */ +/* ================================================================================ */ + +#define __CM33_REV 0x0000U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/* ================================================================================ */ +/* ================== Device Specific Memory Section ================== */ +/* ================================================================================ */ + +/* Non-secure Regions */ +#define MXC_FLASH_NS_MEM_BASE 0x01000000UL +#define MXC_FLASH_NS_PAGE_SIZE 0x00002000UL +#define MXC_FLASH_NS_MEM_SIZE 0x00100000UL +#define MXC_SRAM_NS_MEM_BASE 0x20000000UL +#define MXC_SRAM_NS_MEM_SIZE 0x00040000UL + +/* Secure Regions */ +/* ROM is always in secure region. */ +#define MXC_ROM_MEM_BASE 0x00000000UL +#define MXC_ROM_MEM_SIZE 0x00010000UL +#define MXC_FLASH_S_MEM_BASE 0x11000000UL +#define MXC_FLASH_S_PAGE_SIZE 0x00002000UL +#define MXC_FLASH_S_MEM_SIZE 0x00100000UL +#define MXC_INFO_S_MEM_BASE 0x12000000UL +#define MXC_INFO_S_MEM_SIZE 0x00004000UL +#define MXC_SRAM_S_MEM_BASE 0x30000000UL +#define MXC_SRAM_S_MEM_SIZE 0x00040000UL + +/* Secure Region name redefinitions for explicit use */ +#define MXC_FLASH_MEM_BASE MXC_FLASH_S_MEM_BASE +#define MXC_FLASH_PAGE_SIZE MXC_FLASH_S_PAGE_SIZE +#define MXC_FLASH_MEM_SIZE MXC_FLASH_S_MEM_SIZE +#define MXC_INFO_MEM_BASE MXC_INFO_S_MEM_BASE +#define MXC_INFO_MEM_SIZE MXC_INFO_S_MEM_SIZE +#define MXC_SRAM_MEM_BASE MXC_SRAM_S_MEM_BASE +#define MXC_SRAM_MEM_SIZE MXC_SRAM_S_MEM_SIZE + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ + +/* + Base addresses and configuration settings for all MAX78000 peripheral modules. +*/ + +/******************************************************************************/ +/* Global control */ + +/* Non-secure Mapping */ +#define MXC_BASE_GCR_NS ((uint32_t)0x40000000UL) +#define MXC_GCR_NS ((mxc_gcr_regs_t *)MXC_BASE_GCR_NS) + +/* Secure Mapping */ +#define MXC_BASE_GCR_S ((uint32_t)0x50000000UL) +#define MXC_GCR_S ((mxc_gcr_regs_t *)MXC_BASE_GCR_S) + +#define MXC_BASE_GCR MXC_BASE_GCR_S +#define MXC_GCR MXC_GCR_S + +/******************************************************************************/ +/* Non-battery backed SI Registers */ + +/* Non-secure Mapping */ +#define MXC_BASE_SIR_NS ((uint32_t)0x40000400UL) +#define MXC_SIR_NS ((mxc_sir_regs_t *)MXC_BASE_SIR_NS) + +/* Secure Mapping */ +#define MXC_BASE_SIR_S ((uint32_t)0x50000400UL) +#define MXC_SIR_S ((mxc_sir_regs_t *)MXC_BASE_SIR_S) + +#define MXC_BASE_SIR MXC_BASE_SIR_S +#define MXC_SIR MXC_SIR_S + +/******************************************************************************/ +/* Non-Battery Backed Function Control */ + +/* Non-secure Mapping */ +#define MXC_BASE_FCR_NS ((uint32_t)0x40000800UL) +#define MXC_FCR_NS ((mxc_fcr_regs_t *)MXC_BASE_FCR_NS) + +/* Secure Mapping */ +#define MXC_BASE_FCR_S ((uint32_t)0x50000800UL) +#define MXC_FCR_S ((mxc_fcr_regs_t *)MXC_BASE_FCR_S) + +/******************************************************************************/ +/* Windowed Watchdog Timer */ +#define MXC_CFG_WDT_INSTANCES (1) + +/* Non-secure Mapping */ +#define MXC_BASE_WDT_NS ((uint32_t)0x40003000UL) +#define MXC_WDT_NS ((mxc_wdt_regs_t *)MXC_BASE_WDT_NS) + +/* Secure Mapping */ +#define MXC_BASE_WDT_S ((uint32_t)0x50003000UL) +#define MXC_WDT_S ((mxc_wdt_regs_t *)MXC_BASE_WDT_S) + +#define MXC_BASE_WDT MXC_BASE_WDT_S +#define MXC_WDT MXC_WDT_S + +/******************************************************************************/ +/* SVM Controller */ + +/* Non-secure Mapping */ +#define MXC_BASE_SVM_NS ((uint32_t)0x40004800UL) +#define MXC_SVM_NS //TODO(ME30): Add SVM controller registers. + +/* Secure Mapping */ +#define MXC_BASE_SVM_S ((uint32_t)0x50004800UL) +#define MXC_SVM_S //TODO(ME30): Add SVM controller registers. + +#define MXC_BASE_SVM MXC_BASE_SVM_S +#define MXC_SVM //TODO(ME30): Add SVM controller registers. + +/******************************************************************************/ +/* Boost Controller */ + +/* Non-secure Mapping */ +#define MXC_BASE_BOOST_NS ((uint32_t)0x40004C00UL) +#define MXC_BOOST_NS //TODO(ME30): Add Boost controller registers. + +/* Secure Mapping */ +#define MXC_BASE_BOOST_S ((uint32_t)0x50004C00UL) +#define MXC_BOOST_S //TODO(ME30): Add Boost controller registers. + +#define MXC_BASE_BOOST MXC_BASE_BOOST_S +#define MXC_BOOST //TODO(ME30): Add Boost controller registers. + +/******************************************************************************/ +/* Trim System Initalization Register */ + +/* Non-secure Mapping */ +#define MXC_BASE_TRIMSIR_NS ((uint32_t)0x40005400UL) +#define MXC_TRIMSIR_NS ((mxc_trimsir_regs_t *)MXC_BASE_TRIMSIR_NS) + +/* Secure Mapping */ +#define MXC_BASE_TRIMSIR_S ((uint32_t)0x50005400UL) +#define MXC_TRIMSIR_S ((mxc_trimsir_regs_t *)MXC_BASE_TRIMSIR_S) + +#define MXC_BASE_TRIMSIR MXC_BASE_TRIMSIR_S +#define MXC_TRIMSIR MXC_TRIMSIR_S + +/******************************************************************************/ +/* Real Time Clock */ + +/* Non-secure Mapping */ +#define MXC_BASE_RTC_NS ((uint32_t)0x40006000UL) +#define MXC_RTC_NS ((mxc_rtc_regs_t *)MXC_BASE_RTC_NS) + +/* Secure Mapping */ +#define MXC_BASE_RTC_S ((uint32_t)0x50006000UL) +#define MXC_RTC_S ((mxc_rtc_regs_t *)MXC_BASE_RTC_S) + +#define MXC_BASE_RTC MXC_BASE_RTC_S +#define MXC_RTC MXC_RTC_S + +/******************************************************************************/ +/* Wake-Up Timer (WUT) */ +#define MXC_CFG_WUT_INSTANCES (2) + +/* Non-secure Mapping */ +#define MXC_BASE_WUT0_NS ((uint32_t)0x40006400UL) +#define MXC_WUT0_NS ((mxc_wut_regs_t *)MXC_BASE_WUT0_NS) +#define MXC_BASE_WUT1_NS ((uint32_t)0x40006600UL) +#define MXC_WUT1_NS ((mxc_wut_regs_t *)MXC_BASE_WUT1_NS) + +/* Secure Mapping */ +#define MXC_BASE_WUT0_S ((uint32_t)0x50006400UL) +#define MXC_WUT0_S ((mxc_wut_regs_t *)MXC_BASE_WUT0_S) +#define MXC_BASE_WUT1_S ((uint32_t)0x50006600UL) +#define MXC_WUT1_S ((mxc_wut_regs_t *)MXC_BASE_WUT1_S) + +#define MXC_BASE_WUT0 MXC_BASE_WUT0_S +#define MXC_WUT0 MXC_WUT0_S +#define MXC_BASE_WUT1 MXC_BASE_WUT1_S +#define MXC_WUT1 MXC_WUT1_S + +/******************************************************************************/ +/* Power Sequencer */ + +/* Non-secure Mapping */ +#define MXC_BASE_PWRSEQ_NS ((uint32_t)0x40006800UL) +#define MXC_PWRSEQ_NS ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ_NS) + +/* Secure Mapping */ +#define MXC_BASE_PWRSEQ_S ((uint32_t)0x50006800UL) +#define MXC_PWRSEQ_S ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ_S) + +#define MXC_BASE_PWRSEQ MXC_BASE_PWRSEQ_S +#define MXC_PWRSEQ MXC_PWRSEQ_S + +/******************************************************************************/ +/* Misc Control */ + +/* Non-secure Mapping */ +#define MXC_BASE_MCR_NS ((uint32_t)0x40006C00UL) +#define MXC_MCR_NS ((mxc_mcr_regs_t *)MXC_BASE_MCR_NS) + +/* Secure Mapping */ +#define MXC_BASE_MCR_S ((uint32_t)0x50006C00UL) +#define MXC_MCR_S ((mxc_mcr_regs_t *)MXC_BASE_MCR_S) + +#define MXC_BASE_MCR MXC_BASE_MCR_S +#define MXC_MCR MXC_MCR_S + +/******************************************************************************/ +/* AES */ + +/* Non-secure Mapping */ +#define MXC_BASE_AES_NS ((uint32_t)0x40007400UL) +#define MXC_AES_NS ((mxc_aes_regs_t *)MXC_BASE_AES_NS) + +/* Secure Mapping */ +#define MXC_BASE_AES_S ((uint32_t)0x50007400UL) +#define MXC_AES_S ((mxc_aes_regs_t *)MXC_BASE_AES_NS) + +#define MXC_BASE_AES MXC_BASE_AES_S +#define MXC_AES MXC_AES_S + +/******************************************************************************/ +/* AES Keys */ + +/* Non-secure Mapping */ +#define MXC_BASE_AESKEYS_NS ((uint32_t)0x40007800UL) +#define MXC_AESKEYS_NS ((mxc_aeskeys_regs_t *)MXC_BASE_AESKEYS_NS) + +/* Secure Mapping */ +#define MXC_BASE_AESKEYS_S ((uint32_t)0x50007800UL) +#define MXC_AESKEYS_S ((mxc_aeskeys_regs_t *)MXC_BASE_AESKEYS_S) + +#define MXC_BASE_AESKEYS MXC_BASE_AESKEYS_S +#define MXC_AESKEYS MXC_AESKEYS_S + +/******************************************************************************/ +/* GPIO */ +#define MXC_CFG_GPIO_INSTANCES (1) +#define MXC_CFG_GPIO_PINS_PORT (32) + +/* Non-secure Mapping */ +#define MXC_BASE_GPIO0_NS ((uint32_t)0x40008000UL) +#define MXC_GPIO0_NS ((mxc_gpio_regs_t *)MXC_BASE_GPIO0_NS) + +#define MXC_GPIO_NS_GET_IDX(p) ((p) == MXC_GPIO0_NS ? 0 : -1) +#define MXC_GPIO_NS_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0_NS : 0) + +/* Secure Mapping */ +#define MXC_BASE_GPIO0_S ((uint32_t)0x50008000UL) +#define MXC_GPIO0_S ((mxc_gpio_regs_t *)MXC_BASE_GPIO0_S) + +#define MXC_BASE_GPIO0 MXC_BASE_GPIO0_S +#define MXC_GPIO0 MXC_GPIO0_S + +/******************************************************************************/ +/* CRC */ + +/* Non-secure Mapping */ +#define MXC_BASE_CRC_NS ((uint32_t)0x4000F000UL) +#define MXC_CRC_NS ((mxc_crc_regs_t *)MXC_BASE_CRC_NS) + +/* Secure Mapping */ +#define MXC_BASE_CRC_S ((uint32_t)0x5000F000UL) +#define MXC_CRC_S ((mxc_crc_regs_t *)MXC_BASE_CRC_S) + +#define MXC_BASE_CRC MXC_BASE_CRC_S +#define MXC_CRC MXC_CRC_S + +/******************************************************************************/ +/* Timer */ +#define SEC(s) (((uint32_t)s) * 1000000UL) +#define MSEC(ms) (ms * 1000UL) +#define USEC(us) (us) + +#define MXC_CFG_TMR_INSTANCES (6) + +/* Non-secure Mapping */ +#define MXC_BASE_TMR0_NS ((uint32_t)0x40010000UL) +#define MXC_TMR0_NS ((mxc_tmr_regs_t *)MXC_BASE_TMR0_NS) +#define MXC_BASE_TMR1_NS ((uint32_t)0x40011000UL) +#define MXC_TMR1_NS ((mxc_tmr_regs_t *)MXC_BASE_TMR1_NS) +#define MXC_BASE_TMR2_NS ((uint32_t)0x40012000UL) +#define MXC_TMR2_NS ((mxc_tmr_regs_t *)MXC_BASE_TMR2_NS) +#define MXC_BASE_TMR3_NS ((uint32_t)0x40013000UL) +#define MXC_TMR3_NS ((mxc_tmr_regs_t *)MXC_BASE_TMR3_NS) +#define MXC_BASE_TMR4_NS ((uint32_t)0x40080C00UL) +#define MXC_TMR4_NS ((mxc_tmr_regs_t *)MXC_BASE_TMR4_NS) +#define MXC_BASE_TMR5_NS ((uint32_t)0x40081000UL) +#define MXC_TMR5_NS ((mxc_tmr_regs_t *)MXC_BASE_TMR5_NS) + +#define MXC_TMR_NS_GET_BASE(i) \ + ((i) == 0 ? MXC_BASE_TMR0_NS : \ + (i) == 1 ? MXC_BASE_TMR1_NS : \ + (i) == 2 ? MXC_BASE_TMR2_NS : \ + (i) == 3 ? MXC_BASE_TMR3_NS : \ + (i) == 4 ? MXC_BASE_TMR4_NS : \ + (i) == 5 ? MXC_BASE_TMR5_NS : \ + 0) + +#define MXC_TMR_NS_GET_TMR(i) \ + ((i) == 0 ? MXC_TMR0_NS : \ + (i) == 1 ? MXC_TMR1_NS : \ + (i) == 2 ? MXC_TMR2_NS : \ + (i) == 3 ? MXC_TMR3_NS : \ + (i) == 4 ? MXC_TMR4_NS : \ + (i) == 5 ? MXC_TMR5_NS : \ + 0) + +/* Secure Mapping */ +#define MXC_BASE_TMR0_S ((uint32_t)0x50010000UL) +#define MXC_TMR0_S ((mxc_tmr_regs_t *)MXC_BASE_TMR0_S) +#define MXC_BASE_TMR1_S ((uint32_t)0x50011000UL) +#define MXC_TMR1_S ((mxc_tmr_regs_t *)MXC_BASE_TMR1_S) +#define MXC_BASE_TMR2_S ((uint32_t)0x50012000UL) +#define MXC_TMR2_S ((mxc_tmr_regs_t *)MXC_BASE_TMR2_S) +#define MXC_BASE_TMR3_S ((uint32_t)0x50013000UL) +#define MXC_TMR3_S ((mxc_tmr_regs_t *)MXC_BASE_TMR3_S) +#define MXC_BASE_TMR4_S ((uint32_t)0x50080C00UL) +#define MXC_TMR4_S ((mxc_tmr_regs_t *)MXC_BASE_TMR4_S) +#define MXC_BASE_TMR5_S ((uint32_t)0x50081000UL) +#define MXC_TMR5_S ((mxc_tmr_regs_t *)MXC_BASE_TMR5_S) + +#define MXC_BASE_TMR0 MXC_BASE_TMR0_S +#define MXC_TMR0 MXC_TMR0_S +#define MXC_BASE_TMR1 MXC_BASE_TMR1_S +#define MXC_TMR1 MXC_TMR1_S +#define MXC_BASE_TMR2 MXC_BASE_TMR2_S +#define MXC_TMR2 MXC_TMR2_S +#define MXC_BASE_TMR3 MXC_BASE_TMR3_S +#define MXC_TMR3 MXC_TMR3_S +#define MXC_BASE_TMR4 MXC_BASE_TMR4_S +#define MXC_TMR4 MXC_TMR4_S +#define MXC_BASE_TMR5 MXC_BASE_TMR5_S +#define MXC_TMR5 MXC_TMR5_S + +#define MXC_TMR_S_GET_BASE(i) \ + ((i) == 0 ? MXC_BASE_TMR0_S : \ + (i) == 1 ? MXC_BASE_TMR1_S : \ + (i) == 2 ? MXC_BASE_TMR2_S : \ + (i) == 3 ? MXC_BASE_TMR3_S : \ + (i) == 4 ? MXC_BASE_TMR4_S : \ + (i) == 5 ? MXC_BASE_TMR5_S : \ + 0) + +#define MXC_TMR_S_GET_TMR(i) \ + ((i) == 0 ? MXC_TMR0_S : \ + (i) == 1 ? MXC_TMR1_S : \ + (i) == 2 ? MXC_TMR2_S : \ + (i) == 3 ? MXC_TMR3_S : \ + (i) == 4 ? MXC_TMR4_S : \ + (i) == 5 ? MXC_TMR5_S : \ + 0) + +#define MXC_TMR_GET_IRQ(i) \ + (IRQn_Type)((i) == 0 ? TMR0_IRQn : \ + (i) == 1 ? TMR1_IRQn : \ + (i) == 2 ? TMR2_IRQn : \ + (i) == 3 ? TMR3_IRQn : \ + (i) == 4 ? TMR4_IRQn : \ + (i) == 5 ? TMR5_IRQn : \ + 0) + +#define MXC_TMR_GET_IDX(p) \ + ((p) == MXC_TMR0_NS ? 0 : \ + (p) == MXC_TMR1_NS ? 1 : \ + (p) == MXC_TMR2_NS ? 2 : \ + (p) == MXC_TMR3_NS ? 3 : \ + (p) == MXC_TMR4_NS ? 4 : \ + (p) == MXC_TMR5_NS ? 5 : \ + (p) == MXC_TMR0_S ? 0 : \ + (p) == MXC_TMR1_S ? 1 : \ + (p) == MXC_TMR2_S ? 2 : \ + (p) == MXC_TMR3_S ? 3 : \ + (p) == MXC_TMR4_S ? 4 : \ + (p) == MXC_TMR5_S ? 5 : \ + -1) + +/******************************************************************************/ +/* I3C */ +/* Non-secure Mapping */ +#define MXC_BASE_I3C_NS ((uint32_t)0x4001D000UL) +#define MXC_I3C_NS ((mxc_i2c_regs_t *)MXC_BASE_I3C_NS) + +/* Secure Mapping */ +#define MXC_BASE_I3C_S ((uint32_t)0x5001D000UL) +#define MXC_I3C_S ((mxc_i2c_regs_t *)MXC_BASE_I3C_S) + +#define MXC_BASE_I3C MXC_BASE_I2C_S +#define MXC_I3C MXC_I3C_S + +#define MXC_I3C_FIFO_DEPTH (8) // TODO(ME30): Confirm this is correct. + +/******************************************************************************/ +/* DMA */ +#define MXC_DMA_CHANNELS (4) +#define MXC_DMA_INSTANCES (2) + +/* Non-secure Mapping */ +#define MXC_BASE_DMA0_NS ((uint32_t)0x40028000UL) +#define MXC_DMA0_NS ((mxc_dma_regs_t *)MXC_BASE_DMA0_NS) +/* DMA1 instance only for secure mode. */ + +/* Secure Mapping */ +#define MXC_BASE_DMA0_S ((uint32_t)0x50028000UL) +#define MXC_DMA0_S ((mxc_dma_regs_t *)MXC_BASE_DMA0_S) +#define MXC_BASE_DMA1_S ((uint32_t)0x50035000UL) +#define MXC_DMA1_S ((mxc_dma_regs_t *)MXC_BASE_DMA1_S) + +#define MXC_BASE_DMA0 MXC_BASE_DMA0_S +#define MXC_DMA0 MXC_DMA0_S +#define MXC_BASE_DMA1 MXC_BASE_DMA1_S +#define MXC_DMA1 MXC_DMA1_S + +#define MXC_DMA_CH_GET_IRQ(i) \ + ((IRQn_Type)(((i) == 0) ? DMA0_IRQn : \ + ((i) == 1) ? DMA1_IRQn : \ + ((i) == 2) ? DMA2_IRQn : \ + ((i) == 3) ? DMA3_IRQn : \ + 0)) + +/******************************************************************************/ +/* Flash Controller */ +#define MXC_FLC_INSTANCES (1) + +/* Secure Mapping Only */ +#define MXC_BASE_FLC ((uint32_t)0x50029000UL) +#define MXC_FLC ((mxc_flc_regs_t *)MXC_BASE_FLC) + +/* Added for consistency and explicitness */ +#define MXC_BASE_FLC_S MXC_BASE_FLC +#define MXC_FLC_S MXC_FLC + +/******************************************************************************/ +/* Internal Cache Controller */ +#define MXC_ICC_INSTANCES (1) + +/* Secure Mapping Only */ +#define MXC_BASE_ICC ((uint32_t)0x5002A000UL) +#define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC_S) + +/* Added for consistency and explicitness */ +#define MXC_BASE_ICC_S MXC_BASE_ICC +#define MXC_ICC_S MXC_ICC + +/******************************************************************************/ +/* UART / Serial Port Interface */ +#define MXC_UART_INSTANCES (1) +#define MXC_UART_FIFO_DEPTH (8) // TOD(ME30): Check this is correct. + +/* Non-secure Mapping */ +#define MXC_BASE_UART_NS ((uint32_t)0x40042000UL) +#define MXC_UART_NS ((mxc_uart_regs_t *)MXC_BASE_UART_NS) + +#define MXC_UART_NS_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0_NS : 0) +#define MXC_UART_NS_GET_UART(i) ((i) == 0 ? MXC_UART_NS : 0) + +/* Secure Mapping */ +#define MXC_BASE_UART_S ((uint32_t)0x50042000UL) +#define MXC_UART_S ((mxc_uart_regs_t *)MXC_BASE_UART_S) + +#define MXC_BASE_UART MXC_BASE_UART_S +#define MXC_UART MXC_UART_S + +#define MXC_UART_S_GET_UART(i) ((i) == 0 ? MXC_UART_S : 0) +#define MXC_UART_S_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0_S : 0) + +#define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : 0) +#define MXC_UART_GET_IDX(p) ((p) == MXC_UART_NS ? 0 : (p) == MXC_UART_S ? 0 : -1) + +/******************************************************************************/ +/* SPI */ +#define MXC_SPI_INSTANCES (1) +#define MXC_SPI_SS_INSTANCES (4) +#define MXC_SPI_FIFO_DEPTH (32) + +/* Non-secure Mapping */ +#define MXC_BASE_SPI_NS ((uint32_t)0x40046000UL) +#define MXC_SPI_NS ((mxc_spi_regs_t *)MXC_BASE_SPI_NS) + +#define MXC_SPI_NS_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI_NS : 0) +#define MXC_SPI_NS_GET_SPI(i) ((i) == 0 ? MXC_SPI_NS : 0) + +/* Secure Mapping */ +#define MXC_BASE_SPI_S ((uint32_t)0x50046000UL) +#define MXC_SPI_S ((mxc_spi_regs_t *)MXC_BASE_SPI_S) + +#define MXC_BASE_SPI MXC_BASE_SPI_S +#define MXC_SPI MXC_SPI_S + +#define MXC_SPI_S_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI_S : 0) +#define MXC_SPI_S_GET_SPI(i) ((i) == 0 ? MXC_SPI_S : 0) + +#define MXC_SPI_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SPI_IRQn : 0) +#define MXC_SPI_GET_IDX(p) ((p) == MXC_SPI_NS ? 0 : (p) == MXC_SPI_S ? 0 : -1) + +/******************************************************************************/ +/* TRNG */ + +/* Non-secure Mapping */ +#define MXC_BASE_TRNG_NS ((uint32_t)0x4004D000UL) +#define MXC_TRNG_NS ((mxc_trng_regs_t *)MXC_BASE_TRNG_NS) + +/* Secure Mapping */ +#define MXC_BASE_TRNG_S ((uint32_t)0x5004D000UL) +#define MXC_TRNG_S ((mxc_trng_regs_t *)MXC_BASE_TRNG_S) + +#define MXC_BASE_TRNG MXC_BASE_TRNG_S +#define MXC_TRNG MXC_TRNG_S + +/******************************************************************************/ +/* BTLE */ +// TODO(ME30): Verify with bluetooth team. This section does not exist in our prev +// bluetooth-supported parts. +/* Non-secure Mapping */ +#define MXC_BASE_BTLE_NS ((uint32_t)0x40050000UL) +#define MXC_BTLE_NS // TODO(ME30): Add BTLE related registers? This section doesn't exist for ME17. + +/* Secure Mapping */ +#define MXC_BASE_BTLE_S ((uint32_t)0x50050000UL) +#define MXC_BTLE_S // TODO(ME30): Add BTLE related registers? This section doesn't exist for ME17. + +#define MXC_BASE_BTLE MXC_BASE_BTLE_S +#define MXC_BTLE // TODO(ME30): Does this have registers? + +/******************************************************************************/ +/* Secure Privilege Control (SPC TZ) */ + +/* Secure Mapping Only */ +#define MXC_BASE_SPC ((uint32_t)0x50090000UL) +#define MXC_SPC // TODO(ME30): Does this have registers? + +#define MXC_BASE_SPC_S MXC_BASE_SPC +#define MXC_SPC_S // TODO(ME30): Does this have registers? + +/******************************************************************************/ +/* MPC */ + +/* Secure Mapping Only */ +#define MXC_BASE_MPC_SRAM0 ((uint32_t)0x50091000UL) +#define MXC_MPC_SRAM0 // TODO(ME30): Does this have registers? +#define MXC_BASE_MPC_SRAM1 ((uint32_t)0x50092000UL) +#define MXC_MPC_SRAM1 // TODO(ME30): Does this have registers? +#define MXC_BASE_MPC_SRAM2 ((uint32_t)0x50093000UL) +#define MXC_MPC_SRAM2 // TODO(ME30): Does this have registers? +#define MXC_BASE_MPC_SRAM3 ((uint32_t)0x50094000UL) +#define MXC_MPC_SRAM3 // TODO(ME30): Does this have registers? +#define MXC_BASE_MPC_SRAM4 ((uint32_t)0x50095000UL) +#define MXC_MPC_SRAM4 // TODO(ME30): Does this have registers? +#define MXC_BASE_MPC_FLASH ((uint32_t)0x50096000UL) +#define MXC_MPC_FLASH // TODO(ME30): Does this have registers? + +/* Added for consistency and explicitness */ +#define MXC_BASE_MPC_SRAM0_S MXC_BASE_MPC_SRAM0 +#define MXC_MPC_SRAM0_S // TODO(ME30): Does this have registers? +#define MXC_BASE_MPC_SRAM1_S MXC_BASE_MPC_SRAM1 +#define MXC_MPC_SRAM1_S // TODO(ME30): Does this have registers? +#define MXC_BASE_MPC_SRAM2_S MXC_BASE_MPC_SRAM2 +#define MXC_MPC_SRAM2_S // TODO(ME30): Does this have registers? +#define MXC_BASE_MPC_SRAM3_S MXC_BASE_MPC_SRAM3 +#define MXC_MPC_SRAM3_S // TODO(ME30): Does this have registers? +#define MXC_BASE_MPC_SRAM4_S MXC_BASE_MPC_SRAM4 +#define MXC_MPC_SRAM4_S // TODO(ME30): Does this have registers? +#define MXC_BASE_MPC_FLASH_S MXC_BASE_MPC_FLASH +#define MXC_MPC_FLASH_S // TODO(ME30): Does this have registers? + +/******************************************************************************/ +/* Bit Shifting */ +#define MXC_F_BIT_0 (1 << 0) +#define MXC_F_BIT_1 (1 << 1) +#define MXC_F_BIT_2 (1 << 2) +#define MXC_F_BIT_3 (1 << 3) +#define MXC_F_BIT_4 (1 << 4) +#define MXC_F_BIT_5 (1 << 5) +#define MXC_F_BIT_6 (1 << 6) +#define MXC_F_BIT_7 (1 << 7) +#define MXC_F_BIT_8 (1 << 8) +#define MXC_F_BIT_9 (1 << 9) +#define MXC_F_BIT_10 (1 << 10) +#define MXC_F_BIT_11 (1 << 11) +#define MXC_F_BIT_12 (1 << 12) +#define MXC_F_BIT_13 (1 << 13) +#define MXC_F_BIT_14 (1 << 14) +#define MXC_F_BIT_15 (1 << 15) +#define MXC_F_BIT_16 (1 << 16) +#define MXC_F_BIT_17 (1 << 17) +#define MXC_F_BIT_18 (1 << 18) +#define MXC_F_BIT_19 (1 << 19) +#define MXC_F_BIT_20 (1 << 20) +#define MXC_F_BIT_21 (1 << 21) +#define MXC_F_BIT_22 (1 << 22) +#define MXC_F_BIT_23 (1 << 23) +#define MXC_F_BIT_24 (1 << 24) +#define MXC_F_BIT_25 (1 << 25) +#define MXC_F_BIT_26 (1 << 26) +#define MXC_F_BIT_27 (1 << 27) +#define MXC_F_BIT_28 (1 << 28) +#define MXC_F_BIT_29 (1 << 29) +#define MXC_F_BIT_30 (1 << 30) +#define MXC_F_BIT_31 (1 << 31) + +/******************************************************************************/ +/* Bit Banding */ +#define BITBAND(reg, bit) \ + ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg)&0x0fffffff) << 5) + \ + ((bit) << 2)) + +#define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0) +#define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1) +#define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit)) + +#define MXC_SETFIELD(reg, mask, setting) ((reg) = ((reg) & ~(mask)) | ((setting) & (mask))) + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX326657_INCLUDE_MAX32657_H_ From 2cd2bb9ed67f36bdacb86b3588e1bc4395afc5ea Mon Sep 17 00:00:00 2001 From: Woo Date: Thu, 25 Apr 2024 12:57:19 -0500 Subject: [PATCH 07/93] Update IVT for max32657.h --- .../Device/Maxim/MAX32657/Include/max32657.h | 162 ++++++------------ 1 file changed, 53 insertions(+), 109 deletions(-) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h index 1f467259de5..c6c60785f1e 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h @@ -76,116 +76,60 @@ typedef enum { /* |||| table offset address */ /* vvvv vvvvvv */ - MSP_IRQn = 0, /* 0x10 0x0040 16: MSP Initial Value */ - Reset_IRQn, /* 0x11 0x0044 17: Reset */ - RSV02_IRQn, /* 0x12 0x0048 18: Reserved */ - RTC_IRQn, /* 0x13 0x004C 19: RTC */ - TRNG_IRQn, /* 0x14 0x0050 20: True Random Number Generator */ - TMR0_IRQn, /* 0x15 0x0054 21: Timer 0 */ - TMR1_IRQn, /* 0x16 0x0058 22: Timer 1 */ - TMR2_IRQn, /* 0x17 0x005C 23: Timer 2 */ - TMR3_IRQn, /* 0x18 0x0060 24: Timer 3 */ - TMR4_IRQn, /* 0x19 0x0064 25: Timer 4 (LP) */ - TMR5_IRQn, /* 0x1A 0x0068 26: Timer 5 (LP) */ - RSV11_IRQn, /* 0x1B 0x006C 27: Reserved */ - RSV12_IRQn, /* 0x1C 0x0070 28: Reserved */ - I3C_IRQn, /* 0x1D 0x0074 29: I3C */ - UART_IRQn, /* 0x1E 0x0078 30: UART */ + ICE_IRQn = 0, /* 0x10 0x0040 16: ICE Unlock */ + WDT_IRQn, /* 0x11 0x0044 17: Watchdog Timer */ + RTC_IRQn, /* 0x12 0x0048 18: RTC */ + TRNG_IRQn, /* 0x13 0x004C 19: True Random Number Generator */ + TMR0_IRQn, /* 0x14 0x0050 20: Timer 0 */ + TMR1_IRQn, /* 0x15 0x0054 21: Timer 1 */ + TMR2_IRQn, /* 0x16 0x0058 22: Timer 2 */ + TMR3_IRQn, /* 0x17 0x005C 23: Timer 3 */ + TMR4_IRQn, /* 0x18 0x0060 24: Timer 4 */ + TMR5_IRQn, /* 0x19 0x0064 25: Timer 5 */ + I3C_IRQn, /* 0x1A 0x0068 26: I3C */ + UART_IRQn, /* 0x1B 0x006C 27: UART */ + SPI_IRQn, /* 0x1C 0x0070 28: SPI */ + FLC_IRQn, /* 0x1D 0x0074 29: FLC */ + GPIO0_IRQn, /* 0x1E 0x0078 30: GPIO0 */ RSV15_IRQn, /* 0x1F 0x007C 31: Reserved */ - RSV16_IRQn, /* 0x20 0x0080 32: Reserved */ - RSV17_IRQn, /* 0x21 0x0084 33: Reserved */ - RSV18_IRQn, /* 0x22 0x0088 34: Reserved */ - RSV19_IRQn, /* 0x23 0x008C 35: Reserved */ - RSV20_IRQn, /* 0x24 0x0090 36: Reserved */ - RSV21_IRQn, /* 0x25 0x0094 37: Reserved */ - RSV22_IRQn, /* 0x26 0x0098 38: Reserved */ - FLC_IRQn, /* 0x27 0x009C 39: Flash Controller */ - GPIO0_IRQn, /* 0x28 0x00A0 40: GPIO0 */ - RSV25_IRQn, /* 0x29 0x00A4 41: Reserved */ - RSV26_IRQn, /* 0x2A 0x00A8 42: Reserved */ - RSV27_IRQn, /* 0x2B 0x00AC 43: Reserved */ - DMA0_IRQn, /* 0x2C 0x00B0 44: DMA0 */ - DMA1_IRQn, /* 0x2D 0x00B4 45: DMA1 */ - DMA2_IRQn, /* 0x2E 0x00B8 46: DMA2 */ - DMA3_IRQn, /* 0x2F 0x00BC 47: DMA3 */ - RSV32_IRQn, /* 0x30 0x00C0 48: Reserved */ - RSV33_IRQn, /* 0x31 0x00C4 49: Reserved */ - RSV34_IRQn, /* 0x32 0x00C8 50: Reserved */ - RSV35_IRQn, /* 0x33 0x00CC 51: Reserved */ - RSV36_IRQn, /* 0x34 0x00D0 52: Reserved */ - RSV37_IRQn, /* 0x35 0x00D4 53: Reserved */ - RSV38_IRQn, /* 0x36 0x00D8 54: Reserved */ - BTLE_TX_DONE_IRQn, /* 0x37 0x00DC 55: BTLE TX Done */ - BTLE_RX_RCVD_IRQn, /* 0x38 0x00E0 56: BTLE RX Received */ - BTLE_RX_ENG_DET_IRQn, /* 0x39 0x00E4 57: BTLE RX Energy Detected */ - BTLE_SFD_DET_IRQn, /* 0x3A 0x00E8 58: BTLE SFD Detected */ - BTLE_SFD_TO_IRQn, /* 0x3B 0x00EC 59: BTLE SFD Timeout*/ - BTLE_GP_EVENT_IRQn, /* 0x3C 0x00F0 60: BTLE Timestamp*/ - BTLE_CFO_IRQn, /* 0x3D 0x00F4 61: BTLE CFO Done */ - BTLE_SIG_DET_IRQn, /* 0x3E 0x00F8 62: BTLE Signal Detected */ - BTLE_AGC_EVENT_IRQn, /* 0x3F 0x00FC 63: BTLE AGC Event */ - BTLE_RFFE_SPIM_IRQn, /* 0x40 0x0100 64: BTLE RFFE SPIM Done */ - BTLE_TX_AES_IRQn, /* 0x41 0x0104 65: BTLE TX AES Done */ - BTLE_RX_AES_IRQn, /* 0x42 0x0108 66: BTLE RX AES Done */ - BTLE_INV_APB_ADDR_IRQn, /* 0x43 0x010C 67: BTLE Invalid APB Address*/ - BTLE_IQ_DATA_VALID_IRQn, /* 0x44 0x0110 68: BTLE IQ Data Valid */ - WUT0_IRQn, /* 0x45 0x0114 69: Wakeup Timer 0 */ - GPIOWAKE_IRQn, /* 0x46 0x0118 70: GPIO Wakeup */ - RSV55_IRQn, /* 0x47 0x011C 71: Reserved */ - SPI_IRQn, /* 0x48 0x0120 72: SPI */ - RSV57_IRQn, /* 0x49 0x0124 73: Reserved */ - RSV58_IRQn, /* 0x4A 0x0128 74: Reserved */ - RSV59_IRQn, /* 0x4B 0x012C 75: Reserved */ - RSV60_IRQn, /* 0x4C 0x0130 76: Reserved */ - RSV61_IRQn, /* 0x4D 0x0134 77: Reserved */ - RSV62_IRQn, /* 0x4E 0x0138 78: Reserved */ - RSV63_IRQn, /* 0x4F 0x013C 79: Reserved */ - RSV64_IRQn, /* 0x50 0x0140 80: Reserved */ - RSV65_IRQn, /* 0x51 0x0144 81: Reserved */ - RSV66_IRQn, /* 0x52 0x0148 82: Reserved */ - RSV67_IRQn, /* 0x53 0x014C 83: Reserved */ - RSV68_IRQn, /* 0x54 0x0150 84: Reserved */ - RSV69_IRQn, /* 0x55 0x0154 85: Reserved */ - RSV70_IRQn, /* 0x56 0x0158 86: Reserved */ - RSV71_IRQn, /* 0x57 0x015C 87: Reserved */ - RSV72_IRQn, /* 0x58 0x0160 88: Reserved */ - RSV73_IRQn, /* 0x59 0x0164 89: Reserved */ - RSV74_IRQn, /* 0x5A 0x0168 90: Reserved */ - RSV75_IRQn, /* 0x5B 0x016C 91: Reserved */ - RSV76_IRQn, /* 0x5C 0x0170 92: Reserved */ - RSV77_IRQn, /* 0x5D 0x0174 93: Reserved */ - RSV78_IRQn, /* 0x5E 0x0178 94: Reserved */ - RSV79_IRQn, /* 0x5F 0x017C 95: Reserved */ - RSV80_IRQn, /* 0x60 0x0180 96: Reserved */ - RSV81_IRQn, /* 0x61 0x0184 97: Reserved */ - RSV82_IRQn, /* 0x62 0x0188 98: Reserved */ - RSV83_IRQn, /* 0x63 0x018C 99: Reserved */ - RSV84_IRQn, /* 0x64 0x0190 100: Reserved */ - RSV85_IRQn, /* 0x65 0x0194 101: Reserved */ - RSV86_IRQn, /* 0x66 0x0198 102: Reserved */ - RSV87_IRQn, /* 0x67 0x019C 103: Reserved */ - RSV88_IRQn, /* 0x68 0x01A0 104: Reserved */ - RSV89_IRQn, /* 0x69 0x01A4 105: Reserved */ - RSV90_IRQn, /* 0x6A 0x01A8 106: Reserved */ - RSV91_IRQn, /* 0x6B 0x01AC 107: Reserved */ - RSV92_IRQn, /* 0x6C 0x01B0 108: Reserved */ - RSV93_IRQn, /* 0x6D 0x01B4 109: Reserved */ - RSV94_IRQn, /* 0x6E 0x01B8 110: Reserved */ - RSV95_IRQn, /* 0x6F 0x01BC 111: Reserved */ - RSV96_IRQn, /* 0x70 0x01C0 112: Reserved */ - AES_IRQn, /* 0x71 0x01C4 113: AES */ - RSV98_IRQn, /* 0x72 0x01C8 114: Reserved */ - RSV99_IRQn, /* 0x73 0x01CC 115: Reserved */ - RSV100_IRQn, /* 0x74 0x01D0 116: Reserved */ - RSV101_IRQn, /* 0x75 0x01D4 117: Reserved */ - RSV102_IRQn, /* 0x76 0x01D8 118: Reserved */ - RSV103_IRQn, /* 0x77 0x01Dc 119: Reserved */ - RSV104_IRQn, /* 0x78 0x01E0 120: Reserved */ - RSV105_IRQn, /* 0x79 0x01E4 121: Reserved */ - RSV106_IRQn, /* 0x7A 0x01E8 122: Reserved */ - RSV107_IRQn, /* 0x7B 0x01EC 123: Reserved */ - RSV108_IRQn, /* 0x7C 0x01F0 124: Reserved */ - WUT1_IRQn, /* 0x7D 0x01F4 125: ERFO Ready/WUT 1 */ + DMA0_CH0_IRQn, /* 0x20 0x0080 32: DMA0 Channel 0 */ + DMA0_CH1_IRQn, /* 0x21 0x0084 33: DMA0 Channel 1 */ + DMA0_CH2_IRQn, /* 0x22 0x0088 34: DMA0 Channel 2 */ + DMA0_CH3_IRQn, /* 0x23 0x008C 35: DMA0 Channel 3 */ + DMA1_CH0_IRQn, /* 0x24 0x0090 36: DMA1 Channel 0 */ + DMA1_CH1_IRQn, /* 0x25 0x0094 37: DMA1 Channel 1 */ + DMA1_CH2_IRQn, /* 0x26 0x0098 38: DMA1 CHannel 2 */ + DMA1_CH3_IRQn, /* 0x27 0x009C 39: DMA1 Channel 3 */ + WUT0_IRQn, /* 0x28 0x00A0 40: Wakeup Timer 0 */ + WUT1_IRQn, /* 0x29 0x00A4 41: Wakeup TImer 1 */ + GPIOWAKE_IRQn, /* 0x2A 0x00A8 42: GPIO Wakeup */ + CRC_IRQn, /* 0x2B 0x00AC 43: CRC */ + AES_IRQn, /* 0x2C 0x00B0 44: AES */ + ERFO_IRQn, /* 0x2D 0x00B4 45: ERFO Ready */ + BOOST_IRQn, /* 0x2E 0x00B8 46: Boost Controller */ + ECC_IRQn, /* 0x2F 0x00BC 47: ECC */ + BTLE_TX_DONE_IRQn, /* 0x30 0x00C0 48: BTLE TX Done */ + BTLE_RX_RCVD_IRQn, /* 0x31 0x00C4 49: BTLE RX Received */ + BTLE_RX_ENG_DET_IRQn, /* 0x32 0x00C8 50: BTLE RX Energy Detected */ + BTLE_SFD_DET_IRQn, /* 0x33 0x00CC 51: BTLE SFD Detected */ + BTLE_SFD_TO_IRQn, /* 0x34 0x00D0 52: BTLE SFD Timeout */ + BTLE_GP_EVENT_IRQn, /* 0x35 0x00D4 53: BTLE BTLE Timestamp */ + BTLE_CFO_IRQn, /* 0x36 0x00D8 54: BTLE CFO Done */ + BTLE_SIG_DET_IRQn, /* 0x37 0x00DC 55: BTLE Signal Detected */ + BTLE_AGC_EVENT_IRQn, /* 0x38 0x00E0 56: BTLE AGC Event */ + BTLE_RFFE_SPIM_IRQn, /* 0x39 0x00E4 57: BTLE RFFE SPIM Done */ + BTLE_TX_AES_IRQn, /* 0x3A 0x00E8 58: BTLE TX AES Done */ + BTLE_RX_AES_IRQn, /* 0x3B 0x00EC 59: BTLE RX AES Done */ + BTLE_INV_APB_ADDR_IRQn, /* 0x3C 0x00F0 60: BTLE Invalid APB Address */ + BTLE_IQ_DATA_VALID_IRQn, /* 0x3D 0x00F4 61:BTLE IQ Data Valid */ + BTLE_XXXX_IRQn, /* 0x3E 0x00F8 62: BTLE XXXX TODO(ME30): Verify BTLE IRQs */ + RSV47_IRQn, /* 0x3F 0x00FC 63: Reserved */ + MPC_IRQn, /* 0x40 0x0100 64: MPC Combined (Secure) */ + PPC_IRQn, /* 0x41 0x0104 65: PPC Combined (Secure) */ + RSV50_IRQn, /* 0x42 0x0108 66: Reserved */ + RSV51_IRQn, /* 0x43 0x010C 67: Reserved */ + RSV52_IRQn, /* 0x44 0x0110 68: Reserved */ + RSV53_IRQn, /* 0x45 0x0114 69: Reserved */ MXC_IRQ_EXT_COUNT, } IRQn_Type; // clang-format on From 4b813579883d228f0d49e37b9c9ea578c2dd65be Mon Sep 17 00:00:00 2001 From: Woo Date: Fri, 26 Apr 2024 13:51:23 -0500 Subject: [PATCH 08/93] Fix TMR registers --- .../Maxim/MAX32657/Include/max32657.svd | 8632 +++++++---------- .../Device/Maxim/MAX32657/Include/tmr_regs.h | 357 +- .../Source/TMR/tmr_reva_me30.svd | 313 - .../Source/TMR/tmr_revb_me30.svd | 662 ++ 4 files changed, 4336 insertions(+), 5628 deletions(-) delete mode 100644 Libraries/PeriphDrivers/Source/TMR/tmr_reva_me30.svd create mode 100644 Libraries/PeriphDrivers/Source/TMR/tmr_revb_me30.svd diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd index 1c1771d0ff7..5d65d8caf66 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd @@ -22,359 +22,6 @@ 0x00000000 0xFFFFFFFF - - ADC - 10-bit Analog to Digital Converter - 0x40034000 - 32 - read-write - - 0 - 0x1000 - registers - - - ADC - ADC IRQ - 20 - - - - CTRL - ADC Control - 0x0000 - read-write - - - START - Start ADC Conversion - [0:0] - read-write - - - PWR - ADC Power Up - [1:1] - read-write - - - REBUF_PWR - ADC Reference Buffer Power Up - [3:3] - read-write - - - CHGPUMP_PWR - ADC Charge Pump Power Up - [4:4] - read-write - - - REF_SCALE - ADC Reference Scale - [8:8] - read-write - - - SCALE - ADC Scale - [9:9] - read-write - - - CLK_EN - ADC Clock Enable - [11:11] - read-write - - - CH_SEL - ADC Channel Select - [16:12] - read-write - - - AIN0 - 0 - - - AIN1 - 1 - - - AIN2 - 2 - - - AIN3 - 3 - - - AIN4 - 4 - - - AIN5 - 5 - - - AIN6 - 6 - - - AIN7 - 7 - - - VcoreA - 8 - - - VcoreB - 9 - - - Vrxout - 10 - - - Vtxout - 11 - - - VddA - 12 - - - VddB - VddB/4 - 13 - - - Vddio - Vddio/4 - 14 - - - Vddioh - Vddioh/4 - 15 - - - VregI - VregI/4 - 16 - - - - - DIVSEL - Scales the external inputs, all inputs are scaled the same - [18:17] - read-write - - - DIV1 - 0 - - - DIV2 - 1 - - - DIV3 - 2 - - - DIV4 - 3 - - - - - DATA_ALIGN - ADC Data Alignment Select - [20:20] - read-write - - - - - STATUS - ADC Status - 0x0004 - read-write - - - ACTIVE - ADC Conversion In Progress - [0:0] - read-only - - - AFE_PWR_UP_ACTIVE - AFE Power Up Delay Active - [2:2] - read-only - - - OVERFLOW - ADC Overflow - [3:3] - read-only - - - - - DATA - ADC Output Data - 0x0008 - read-write - - - DATA - ADC Converted Sample Data Output - [15:0] - read-only - - - - - INTR - ADC Interrupt Control Register - 0x000C - read-write - - - DONE_IE - ADC Done Interrupt Enable - [0:0] - read-write - - - REF_READY_IE - ADC Reference Ready Interrupt Enable - [1:1] - read-write - - - HI_LIMIT_IE - ADC Hi Limit Monitor Interrupt Enable - [2:2] - read-write - - - LO_LIMIT_IE - ADC Lo Limit Monitor Interrupt Enable - [3:3] - read-write - - - OVERFLOW_IE - ADC Overflow Interrupt Enable - [4:4] - read-write - - - DONE_IF - ADC Done Interrupt Flag - [16:16] - read-write - oneToClear - - - REF_READY_IF - ADC Reference Ready Interrupt Flag - [17:17] - read-write - oneToClear - - - HI_LIMIT_IF - ADC Hi Limit Monitor Interrupt Flag - [18:18] - read-write - oneToClear - - - LO_LIMIT_IF - ADC Lo Limit Monitor Interrupt Flag - [19:19] - read-write - oneToClear - - - OVERFLOW_IF - ADC Overflow Interrupt Flag - [20:20] - read-write - oneToClear - - - PENDING - ADC Interrupt Pending Status - [22:22] - read-only - - - - - 4 - 4 - LIMIT[%s] - ADC Limit - 0x0010 - read-write - - - CH_LO_LIMIT - Low Limit Threshold - [9:0] - read-write - - - CH_HI_LIMIT - High Limit Threshold - [21:12] - read-write - - - CH_SEL - ADC Channel Select - [27:24] - read-write - - - CH_LO_LIMIT_EN - Low Limit Monitoring Enable - [28:28] - read-write - - - CH_HI_LIMIT_EN - High Limit Monitoring Enable - [29:29] - read-write - - - - - DECCNT - ADC Decimation Count. - 0x0020 - read-write - - - DELAY - Delay. - [31:0] - read-write - - - - - - AESKEYS AES Key Registers. @@ -1491,1991 +1138,1547 @@ - DVS - Dynamic Voltage Scaling - DVS_ - 0x40003C00 + FCR + Function Control Register. + 0x40000800 0x00 - 0x0030 + 0x400 registers - - DVS - Dynamic Voltage Scaling Interrupt - 83 - - CTL - Control Register + FCTRL0 + Register 0. 0x00 + read-write - MON_ENA - Enable the DVS monitoring circuit - 0 - 1 - - - ADJ_ENA - Enable the power supply adjustment based on measurements - 1 - 1 - - - PS_FB_DIS - Power Supply Feedback Disable - 2 - 1 - - - CTRL_TAP_ENA - Use the TAP Select for automatic adjustment or monitoring - 3 - 1 - - - PROP_DLY - Additional delay to monitor lines - 4 - 2 - - - MON_ONESHOT - Measure delay once - 6 - 1 - - - GO_DIRECT - Operate in automatic mode or move directly - 7 - 1 - - - DIRECT_REG - Step incrementally to target voltage - 8 + USBCLKSEL + USB External Core Clock Select. + 16 1 + + + sys + Generated clock from system clock. + 0 + + + dig + Digital clock from a GPIO. + 1 + + - PRIME_ENA - Include a delay line priming signal before monitoring - 9 + I2C0DGEN0 + I2C0 SDA Glitch Filter Enable. + 20 1 + + + dis + Filter disabled. + 0 + + + en + Filter enabled. + 1 + + - LIMIT_IE - Enable Limit Error Interrupt - 10 + I2C0DGEN1 + I2C0 SCL Glitch Filter Enable. + 21 1 + + + dis + Filter disabled. + 0 + + + en + Filter enabled. + 1 + + - RANGE_IE - Enable Range Error Interrupt - 11 + I2C1DGEN0 + I2C1 SDA Glitch Filter Enable. + 22 1 + + + dis + Filter disabled. + 0 + + + en + Filter enabled. + 1 + + - ADJ_IE - Enable Adjustment Error Interrupt - 12 + I2C1DGEN1 + I2C1 SCL Glitch Filter Enable. + 23 1 + + + dis + Filter disabled. + 0 + + + en + Filter enabled. + 1 + + - REF_SEL - Select TAP used for voltage adjustment - 13 - 4 - - - INC_VAL - Step size to increment voltage when in automatic mode - 17 - 3 - - - DVS_PS_APB_DIS - Prevent the application code from adjusting Vcore - 20 + I2C2ADGEN0 + I2C2 AF2 SDA Glitch Filter Enable. + 24 1 + + + dis + Filter disabled. + 0 + + + en + Filter enabled. + 1 + + - DVS_HI_RANGE_ANY - Any high range signal from a delay line will cause a voltage adjustment - 21 + I2C2ADGEN1 + I2C2 AF2 SCL Glitch Filter Enable. + 25 1 + + + dis + Filter disabled. + 0 + + + en + Filter enabled. + 1 + + - FB_TO_IE - Enable Voltage Adjustment Timeout Interrupt - 22 + I2C2BDGEN0 + I2C2 AF3 SDA Glitch Filter Enable. + 26 1 + + + dis + Filter disabled. + 0 + + + en + Filter enabled. + 1 + + - FC_LV_IE - Enable Low Voltage Interrupt - 23 + I2C2BDGEN1 + I2C2 AF3 SCL Glitch Filter Enable. + 27 1 + + + dis + Filter disabled. + 0 + + + en + Filter enabled. + 1 + + - PD_ACK_ENA - Prevent DVS from ack'ing a request to enter a low power mode until in the idle state - 24 + I2C2CDGEN0 + I2C2 AF4 SDA Glitch Filter Enable + 28 1 + + + dis + Filter disabled. + 0 + + + en + Filter enabled. + 1 + + - ADJ_ABORT - Causes the DVS to enter the idle state immediately on a request to enter a low power mode - 25 + I2C2CDGEN1 + I2C2 AF4 SCL Glitch Filter Enable + 29 1 + + + dis + Filter disabled. + 0 + + + en + Filter enabled. + 1 + + - STAT - Status Fields + FCTRL1 + Register 1. 0x04 - 0x00000000 + read-write - DVS_STATE - State machine state + AC_EN + Auto-calibration Enable. 0 - 4 - - - ADJ_UP_ENA - DVS Raising voltage - 4 1 + + + dis + Disabled. + 0 + + + en + Enabled. + 1 + + - ADJ_DWN_ENA - DVS Lowering voltage - 5 + AC_RUN + Autocalibration Run. + 1 1 + + + not + Not Running. + 0 + + + run + Running. + 1 + + - ADJ_ACTIVE - Adjustment to a Direct Voltage - 6 + LOAD_TRIM + Load Trim. + 2 1 - CTR_TAP_OK - Tap Enabled and the Tap is withing Hi/Low limits - 7 - 1 - - - CTR_TAP_SEL - Status of selected center tap delay line detect output - 8 - 1 - - - SLOW_TRIP_DET - Provides the current combined status of all selected Low Range delay lines - 9 - 1 - - - FAST_TRIP_DET - Provides the current combined status of all selected High Range delay lines - 10 - 1 - - - PS_IN_RANGE - Indicates if the power supply is in range - 11 - 1 - - - PS_VCNTR - Voltage Count value sent to the power supply - 12 - 7 - - - MON_DLY_OK - Indicates the monitor delay count is at 0 - 19 + GAIN_INV + Invert Gain. + 3 1 + + + not + Not Running. + 0 + + + run + Running. + 1 + + - ADJ_DLY_OK - Indicates the adjustment delay count is at 0 - 20 + ATOMIC + Atomic mode. + 4 1 + + + not + Not Running. + 0 + + + run + Running. + 1 + + - LO_LIMIT_DET - Power supply voltage counter is at low limit - 21 - 1 + MU + MU value. + 8 + 12 - HI_LIMIT_DET - Power supply voltage counter is at high limit - 22 - 1 + AC_TRIM + 150MHz HFIO Auto Calibration Trim + 23 + 9 + + + + FCTRL2 + Register 2. + 0x08 + read-write + - VALID_TAP - At least one delay line has been enabled - 23 + NFC_FWD_EN + Enabled FWD mode for NFC block + 0 1 - LIMIT_ERR - Interrupt flag that indicates a voltage count is at/beyond manufacturer limits - 24 + NFC_CLK_EN + Enabled the NFC blocks clock divider in Analog + 1 1 - RANGE_ERR - Interrupt flag that indicates a tap has an invalid value - 25 + NFC_FWD_TX_DATA_OVR + FWD input for NFC block + 2 1 - ADJ_ERR - Interrupt flag that indicates up and down adjustment requested simultaneously - 26 + XO_EN_DGL + TBD + 3 1 - REF_SEL_ERR - Indicates the ref select register bit is out of range - 27 + RX_BIAS_PD + Power down enable for NFC receiver analog block + 4 1 - FB_TO_ERR - Interrupt flag that indicates a timeout while adjusting the voltage - 28 + RX_BIAS_EN + Enable the NFC receiver analog blocks + 5 1 - FB_TO_ERR_S - Interrupt flag that mirror FB_TO_ERR and is write one clear - 29 + RX_TM_VBG_VABUS + TBD + 6 1 - FC_LV_DET_INT - Interrupt flag that indicates the power supply voltage requested is below the low threshold - 30 + RX_TM_BIAS + TBD + 7 1 - FC_LV_DET_S - Interrupt flag that mirrors FC_LV_DET_INT - 31 + NFC_FWD_DOUT + FWD output from FNC block + 8 1 - DIRECT - Direct control of target voltage - 0x08 + FCTRL3 + Register 3. + 0x0C + read-write - VOLTAGE - Sets the target power supply value + DONECNT + Auto-calibration Done Counter Setting. 0 - 7 + 8 - MON - Monitor Delay - 0x00C + GP + General Purpose Register. + 0x1C + read-write - DLY - Number of prescaled clocks between delay line samples + GP + General Purpose. 0 - 24 - - - PRE - Number of clocks before DVS_MON_DLY is decremented - 24 - 8 + 32 - ADJ_UP - Up Delay Register - 0x010 + MSRTRIM + MSR Trim Register. + 0x20 + read-write - DLY - Number of prescaled clocks between updates of the adjustment delay counter + R1 + MSR Trim R1. 0 - 16 + 2 - PRE - Number of clocks before DVS_ADJ_UP_DLY is decremented - 16 - 8 + R2 + MSR Trim R2. + 2 + 3 - ADJ_DWN - Down Delay Register - 0x014 + FLVFILT + Flash Low Voltage Filter Control Register. + 0x24 + read-write - DLY - Number of prescaled clocks between updates of the adjustment delay counter + NUM + Defines the number of consecutive samples of FLV status that must be good for ROM to continue. 0 - 16 + 8 - PRE - Number of clocks before DVS_ADJ_DWN_DLY is decremented + RATE + Defines the rate for ROM sampling of the FLV status. + 8 + 8 + + + DELAY + Defines the delay from change in system clock divider until ROM begins filtering process of the FLV status. 16 8 + + + + + FLC + Flash Memory Control. + FLSH_ + 0x40029000 + + 0x00 + 0x400 + registers + + + Flash_Controller + Flash Controller interrupt. + 23 + + - THRES_CMP - Up Delay Register - 0x018 + ADDR + Flash Write Address. + 0x00 - VCNTR_THRES_CNT - Value used to determine 'low voltage' range + ADDR + Address for next operation. 0 - 7 - - - VCNTR_THRES_MASK - Mask applied to threshold and vcount to determine if the device is in a low voltage range - 8 - 7 + 32 - 5 - 4 - TAP_SEL[%s] - DVS Tap Select Register - 0x1C + CLKDIV + Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller. + 0x04 + 0x00000064 - LO - Select delay line tap for lower bound of auto adjustment + CLKDIV + Flash Clock Divide. The clock is divided by this value to generate a 1MHz clock for flash controller. 0 - 5 + 8 + + + + CTRL + Flash Control Register. + 0x08 + - LO_TAP_STAT - Returns last delay line tap value - 5 + WR + Write. This bit is automatically cleared after the operation. + 0 1 + + + complete + No operation/complete. + 0 + + + start + Start operation. + 1 + + - - CTR_TAP_STAT - Returns last delay line tap value - 6 + + ME + Mass Erase. This bit is automatically cleared after the operation. + 1 1 - - HI_TAP_STAT - Returns last delay line tap value - 7 + + PGE + Page Erase. This bit is automatically cleared after the operation. + 2 1 - HI - Selects delay line tap for high point of auto adjustment + ERASE_CODE + Erase Code. The ERASE_CODE must be set up property before erase operation can be initiated. These bits are automatically cleared after the operation is complete. 8 - 5 - - - CTR - Selects delay line tap for center point of auto adjustment - 16 - 5 - - - COARSE - Selects delay line tap for coarse or fixed delay portion of the line - 24 - 3 - - - DET_DLY - Number of HCLK between delay line launch and sampling - 29 - 2 - - - DELAY_ACT - Set if the delay is active - 31 - 1 - - - - - - - - FCR - Function Control Register. - 0x40000800 - - 0x00 - 0x400 - registers - - - - FCTRL0 - Register 0. - 0x00 - read-write - - - USBCLKSEL - USB External Core Clock Select. - 16 - 1 + 8 - sys - Generated clock from system clock. + nop + No operation. 0 - dig - Digital clock from a GPIO. - 1 - - - - - I2C0DGEN0 - I2C0 SDA Glitch Filter Enable. - 20 - 1 - - - dis - Filter disabled. - 0 + erasePage + Enable Page Erase. + 0x55 - en - Filter enabled. - 1 + eraseAll + Enable Mass Erase. The debug port must be enabled. + 0xAA - I2C0DGEN1 - I2C0 SCL Glitch Filter Enable. - 21 + PEND + Flash Pending. When Flash operation is in progress (busy), Flash reads and writes will fail. When PEND is set, write to all Flash registers, with exception of the Flash interrupt register, are ignored. + 24 1 + read-only - dis - Filter disabled. + idle + Idle. 0 - en - Filter enabled. + busy + Busy. 1 - I2C1DGEN0 - I2C1 SDA Glitch Filter Enable. - 22 + LVE + Low Voltage enable. + 25 1 - - - dis - Filter disabled. - 0 - - - en - Filter enabled. - 1 - - - I2C1DGEN1 - I2C1 SCL Glitch Filter Enable. - 23 - 1 + UNLOCK + Flash Unlock. The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed. + 28 + 4 - dis - Filter disabled. - 0 + unlocked + Flash Unlocked. + 2 - en - Filter enabled. - 1 + locked + Flash Locked. + 3 + + + + INTR + Flash Interrupt Register. + 0x024 + - I2C2ADGEN0 - I2C2 AF2 SDA Glitch Filter Enable. - 24 + DONE_IF + Flash Done Interrupt. This bit is set to 1 upon Flash write or erase completion. + 0 1 - dis - Filter disabled. + inactive + No interrupt is pending. 0 - en - Filter enabled. + pending + An interrupt is pending. 1 - I2C2ADGEN1 - I2C2 AF2 SCL Glitch Filter Enable. - 25 + AF_IF + Flash Access Fail. This bit is set when an attempt is made to write the flash while the flash is busy or the flash is locked. This bit can only be set to 1 by hardware. + 1 1 - dis - Filter disabled. + noError + No Failure. 0 - en - Filter enabled. + error + Failure occurs. 1 - I2C2BDGEN0 - I2C2 AF3 SDA Glitch Filter Enable. - 26 + DONE_IE + Flash Done Interrupt Enable. + 8 1 - dis - Filter disabled. + disable + Disable. 0 - en - Filter enabled. + enable + Enable. 1 - - I2C2BDGEN1 - I2C2 AF3 SCL Glitch Filter Enable. - 27 + + AF_IE + 9 1 - - - dis - Filter disabled. - 0 - - - en - Filter enabled. - 1 - - + + + + ECCDATA + ECC Data Register. + 0x2C + - I2C2CDGEN0 - I2C2 AF4 SDA Glitch Filter Enable - 28 - 1 - - - dis - Filter disabled. - 0 - - - en - Filter enabled. - 1 - - + EVEN + Error Correction Code Odd Data. + 0 + 9 - I2C2CDGEN1 - I2C2 AF4 SCL Glitch Filter Enable - 29 - 1 - - - dis - Filter disabled. - 0 - - - en - Filter enabled. - 1 - - + ODD + Error Correction Code Even Data. + 16 + 9 - FCTRL1 - Register 1. - 0x04 - read-write + 4 + 4 + DATA[%s] + Flash Write Data. + 0x30 - AC_EN - Auto-calibration Enable. + DATA + Data next operation. 0 - 1 - - - dis - Disabled. - 0 - - - en - Enabled. - 1 - - - - - AC_RUN - Autocalibration Run. - 1 - 1 - - - not - Not Running. - 0 - - - run - Running. - 1 - - - - - LOAD_TRIM - Load Trim. - 2 - 1 - - - GAIN_INV - Invert Gain. - 3 - 1 - - - not - Not Running. - 0 - - - run - Running. - 1 - - - - - ATOMIC - Atomic mode. - 4 - 1 - - - not - Not Running. - 0 - - - run - Running. - 1 - - - - - MU - MU value. - 8 - 12 - - - AC_TRIM - 150MHz HFIO Auto Calibration Trim - 23 - 9 + 32 - FCTRL2 - Register 2. - 0x08 - read-write + ACTRL + Access Control Register. Writing the ACTRL register with the following values in the order shown, allows read and write access to the system and user Information block: + pflc-actrl = 0x3a7f5ca3; + pflc-actrl = 0xa1e34f20; + pflc-actrl = 0x9608b2c1. When unlocked, a write of any word will disable access to system and user information block. Readback of this register is always zero. + 0x40 + write-only - NFC_FWD_EN - Enabled FWD mode for NFC block + ACTRL + Access control. 0 - 1 - - - NFC_CLK_EN - Enabled the NFC blocks clock divider in Analog - 1 - 1 - - - NFC_FWD_TX_DATA_OVR - FWD input for NFC block - 2 - 1 - - - XO_EN_DGL - TBD - 3 - 1 - - - RX_BIAS_PD - Power down enable for NFC receiver analog block - 4 - 1 - - - RX_BIAS_EN - Enable the NFC receiver analog blocks - 5 - 1 - - - RX_TM_VBG_VABUS - TBD - 6 - 1 - - - RX_TM_BIAS - TBD - 7 - 1 - - - NFC_FWD_DOUT - FWD output from FNC block - 8 - 1 + 32 - FCTRL3 - Register 3. - 0x0C - read-write + WELR0 + WELR0 + 0x80 - DONECNT - Auto-calibration Done Counter Setting. + WELR0 + Access control. 0 - 8 + 32 - GP - General Purpose Register. - 0x1C - read-write + WELR1 + WELR1 + 0x88 - GP - General Purpose. + WELR1 + Access control. 0 32 - MSRTRIM - MSR Trim Register. - 0x20 - read-write + RLR0 + RLR0 + 0x90 - R1 - MSR Trim R1. + RLR0 + Access control. 0 - 2 - - - R2 - MSR Trim R2. - 2 - 3 + 32 - FLVFILT - Flash Low Voltage Filter Control Register. - 0x24 - read-write + RLR1 + RLR1 + 0x98 - NUM - Defines the number of consecutive samples of FLV status that must be good for ROM to continue. + RLR1 + Access control. 0 - 8 - - - RATE - Defines the rate for ROM sampling of the FLV status. - 8 - 8 - - - DELAY - Defines the delay from change in system clock divider until ROM begins filtering process of the FLV status. - 16 - 8 + 32 - + - FLC - Flash Memory Control. - FLSH_ - 0x40029000 + GCR + Global Control Registers. + 0x40000000 - 0x00 + 0 0x400 registers - - Flash_Controller - Flash Controller interrupt. - 23 - - ADDR - Flash Write Address. + SYSCTRL + System Control. 0x00 + 0xFFFFFFFE - ADDR - Address for next operation. - 0 - 32 - - - - - CLKDIV - Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1 MHz clock for Flash controller. - 0x04 - 0x00000064 - - - CLKDIV - Flash Clock Divide. The clock is divided by this value to generate a 1MHz clock for flash controller. - 0 - 8 - - - - - CTRL - Flash Control Register. - 0x08 - - - WR - Write. This bit is automatically cleared after the operation. + BSTAP_EN + Boundary Scan TAP enable. When enabled, the JTAG port is connected to the Boundary Scan TAP. Otherwise, the port is connected to the ARM ICE function. This bit is reset by the POR. Reset value and access depend on the part number. 0 1 - complete - No operation/complete. + dis + Boundary Scan TAP port disabled. 0 - start - Start operation. + en + Boundary Scan TAP port enabled. 1 - - ME - Mass Erase. This bit is automatically cleared after the operation. + + SBUSARB + System bus abritration scheme. These bits are used to select between Fixed-burst abritration and Round-Robin scheme. The Round-Robin scheme is selected by default. These bits are reset by the system reset. 1 + 2 + + + fix + Fixed Burst abritration. + 0 + + + round + Round-robin scheme. + 1 + + + + + FLASH_PAGE_FLIP + Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer. + 4 1 + + + normal + Physical layout matches logical layout. + 0 + + + swapped + Bottom half mapped to logical top half and vice versa. + 1 + + - - PGE - Page Erase. This bit is automatically cleared after the operation. - 2 + + FPU_DIS + Cortex M4 Floating Point Disable This bit is used to disable the floating-point unit of the Cortex-M4. + 5 1 - ERASE_CODE - Erase Code. The ERASE_CODE must be set up property before erase operation can be initiated. These bits are automatically cleared after the operation is complete. - 8 - 8 + ICC_FLUSH + Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. + 6 + 1 - nop - No operation. + normal + Normal Code Cache Operation 0 - erasePage - Enable Page Erase. - 0x55 - - - eraseAll - Enable Mass Erase. The debug port must be enabled. - 0xAA + flush + Code Caches and CPU instruction buffer are flushed + 1 - PEND - Flash Pending. When Flash operation is in progress (busy), Flash reads and writes will fail. When PEND is set, write to all Flash registers, with exception of the Flash interrupt register, are ignored. - 24 + SRCC_FLUSH + Data Cache Flush. The system cache (s) will be flushed when this bit is set. + 7 1 - read-only - idle - Idle. + normal + Normal System Cache Operation 0 - busy - Busy. + flush + System Cache is flushed 1 - LVE - Low Voltage enable. - 25 + SRCC_DIS + Data Cache Disable. The system cache (s) will be completely disabled when this bit is set. + 9 1 - - - UNLOCK - Flash Unlock. The correct unlock code must be written to these four bits before any Flash write or erase operation is allowed. - 28 - 4 - unlocked - Flash Unlocked. - 2 + en + Is enabled. + 0 - locked - Flash Locked. - 3 + dis + Is Disabled. + 1 - - - - INTR - Flash Interrupt Register. - 0x024 - - DONE_IF - Flash Done Interrupt. This bit is set to 1 upon Flash write or erase completion. - 0 + CHKRES1 + ROM1 Checksum Result. This bit is only valid when the checksum is done and CCHK1 bit is cleared.. + 11 1 - inactive - No interrupt is pending. + complete + No operation/complete. 0 - pending - An interrupt is pending. + start + Start operation. 1 - AF_IF - Flash Access Fail. This bit is set when an attempt is made to write the flash while the flash is busy or the flash is locked. This bit can only be set to 1 by hardware. - 1 + CCHK1 + Compute ROM1 Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. + 12 1 - noError - No Failure. + complete + No operation/complete. 0 - error - Failure occurs. + start + Start operation. 1 - DONE_IE - Flash Done Interrupt Enable. - 8 + CCHK0 + Compute ROM0 Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. + 13 1 - disable - Disable. + complete + No operation/complete. 0 - enable - Enable. + start + Start operation. 1 - - AF_IE - 9 - 1 - - - - - ECCDATA - ECC Data Register. - 0x2C - - EVEN - Error Correction Code Odd Data. - 0 - 9 + CHKRES0 + ROM0 Checksum Result. This bit is only valid when the checksum is done and CCHK0 bit is cleared.. + 15 + 1 + + + pass + ROM Checksum Correct. + 0 + + + fail + ROM Checksum Fail. + 1 + + - ODD - Error Correction Code Even Data. + OVR + Operating Voltage Range. 16 - 9 + 2 - 4 - 4 - DATA[%s] - Flash Write Data. - 0x30 + RST0 + Reset. + 0x04 - DATA - Data next operation. + DMA + DMA Reset. 0 - 32 + 1 - - - - ACTRL - Access Control Register. Writing the ACTRL register with the following values in the order shown, allows read and write access to the system and user Information block: - pflc-actrl = 0x3a7f5ca3; - pflc-actrl = 0xa1e34f20; - pflc-actrl = 0x9608b2c1. When unlocked, a write of any word will disable access to system and user information block. Readback of this register is always zero. - 0x40 - write-only - - - ACTRL - Access control. - 0 - 32 + + WDT0 + Watchdog Timer Reset. + 1 + 1 - - - - WELR0 - WELR0 - 0x80 - - - WELR0 - Access control. - 0 - 32 + + GPIO0 + GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states. + 2 + 1 - - - - WELR1 - WELR1 - 0x88 - - - WELR1 - Access control. - 0 - 32 + + GPIO1 + GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states. + 3 + 1 - - - - RLR0 - RLR0 - 0x90 - - - RLR0 - Access control. - 0 - 32 + + TMR0 + Timer0 Reset. Setting this bit to 1 resets Timer 0 blocks. + 5 + 1 - - - - RLR1 - RLR1 - 0x98 - - - RLR1 - Access control. - 0 - 32 + + TMR1 + Timer1 Reset. Setting this bit to 1 resets Timer 1 blocks. + 6 + 1 + + + TMR2 + Timer2 Reset. Setting this bit to 1 resets Timer 2 blocks. + 7 + 1 + + + TMR3 + Timer3 Reset. Setting this bit to 1 resets Timer 3 blocks. + 8 + 1 + + + TMR4 + Timer4 Reset. Setting this bit to 1 resets Timer 4 blocks. + 9 + 1 + + + TMR5 + Timer5 Reset. Setting this bit to 1 resets Timer 5 blocks. + 10 + 1 + + + UART0 + UART0 Reset. Setting this bit to 1 resets all UART 0 blocks. + 11 + 1 + + + UART1 + UART1 Reset. Setting this bit to 1 resets all UART 1 blocks. + 12 + 1 + + + SPI0 + SPI0 Reset. Setting this bit to 1 resets all SPI 0 blocks. + 13 + 1 + + + SPI1 + SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks. + 14 + 1 + + + SPI2 + SPI2 Reset. Setting this bit to 1 resets all SPI 2 blocks. + 15 + 1 + + + I2C0 + I2C0 Reset. + 16 + 1 + + + RTC + Real Time Clock Reset. + 17 + 1 + + + TMR6 + Timer6 Reset. Setting this bit to 1 resets Timer 6 blocks. + 20 + 1 + + + TMR7 + Timer7 Reset. Setting this bit to 1 resets Timer 7 blocks. + 21 + 1 + + + SEMA + Semaphore Reset. + 22 + 1 + + + TRNG + TODO(5-2-2023): Remove this bit before release. TRNG Reset. Setting this bit resets the TRNG block. + 24 + 1 + + + ADC + Analog to Digital Reset. + 26 + 1 + + + UART2 + UART2 Reset. Setting this bit to 1 resets all UART 2 blocks. + 28 + 1 + + + SOFT + Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer. + 29 + 1 + + + PERIPH + Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset. + 30 + 1 + + + SYS + System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer. + 31 + 1 - - - - - GCR - Global Control Registers. - 0x40000000 - - 0 - 0x400 - registers - - - SYSCTRL - System Control. - 0x00 - 0xFFFFFFFE + CLKCTRL + Clock Control. + 0x08 + 0x00000008 - BSTAP_EN - Boundary Scan TAP enable. When enabled, the JTAG port is connected to the Boundary Scan TAP. Otherwise, the port is connected to the ARM ICE function. This bit is reset by the POR. Reset value and access depend on the part number. - 0 - 1 + PCLK_DIV + PCLK Divider. + 3 + 3 - dis - Boundary Scan TAP port disabled. + div1 + Divide by 1. 0 - en - Boundary Scan TAP port enabled. + div2 + Divide by 2. 1 - - - - SBUSARB - System bus abritration scheme. These bits are used to select between Fixed-burst abritration and Round-Robin scheme. The Round-Robin scheme is selected by default. These bits are reset by the system reset. - 1 - 2 - - fix - Fixed Burst abritration. - 0 + div4 + Divide by 4. + 2 - round - Round-robin scheme. - 1 + div8 + Divide by 8. + 3 - FLASH_PAGE_FLIP - Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer. - 4 - 1 + SYSCLK_DIV + Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0. + 6 + 3 - normal - Physical layout matches logical layout. + div1 + Divide by 1. 0 - swapped - Bottom half mapped to logical top half and vice versa. + div2 + Divide by 2. 1 - - - - FPU_DIS - Cortex M4 Floating Point Disable This bit is used to disable the floating-point unit of the Cortex-M4. - 5 - 1 - - - ICC_FLUSH - Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. - 6 - 1 - - normal - Normal Code Cache Operation - 0 + div4 + Divide by 4. + 2 - flush - Code Caches and CPU instruction buffer are flushed - 1 + div8 + Divide by 8. + 3 - - - - SRCC_FLUSH - Data Cache Flush. The system cache (s) will be flushed when this bit is set. - 7 - 1 - - normal - Normal System Cache Operation - 0 + div16 + Divide by 16. + 4 - flush - System Cache is flushed - 1 + div32 + Divide by 32. + 5 + + + div64 + Divide by 64. + 6 + + + div128 + Divide by 128. + 7 - SRCC_DIS - Data Cache Disable. The system cache (s) will be completely disabled when this bit is set. + SYSCLK_SEL + Clock Source Select. This 3 bit field selects the source for the system clock. 9 - 1 + 3 - en - Is enabled. + ISO + Internal Secondary Oscilatior Clock 0 - dis - Is Disabled. - 1 + ERFO + 27MHz Crystal is used for the system clock. + 2 - - - - CHKRES1 - ROM1 Checksum Result. This bit is only valid when the checksum is done and CCHK1 bit is cleared.. - 11 - 1 - - complete - No operation/complete. - 0 + INRO + 8kHz Internal Nano Ring Oscillator is used for the system clock. + 3 - start - Start operation. - 1 + IPO + The internal Primary oscillator is used for the system clock. + 4 + + + IBRO + The internal Baud Rate oscillator is used for the system clock. + 5 + + + ERTCO + 32kHz is used for the system clock. + 6 - CCHK1 - Compute ROM1 Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. - 12 + SYSCLK_RDY + Clock Ready. This read only bit reflects whether the currently selected system clock source is running. + 13 1 + read-only - complete - No operation/complete. + busy + Switchover to the new clock source (as selected by CLKSEL) has not yet occurred. 0 - start - Start operation. + ready + System clock running from CLKSEL clock source. 1 - CCHK0 - Compute ROM0 Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. - 13 - 1 + IPO_DIV + IPO clock divider + 14 + 2 - complete - No operation/complete. + DIV1 + Divide 1. 0 - start - Start operation. + DIV2 + Divide 2. 1 + + DIV4 + Divide 4. + 2 + + + DIV8 + Divide 8. + 3 + - CHKRES0 - ROM0 Checksum Result. This bit is only valid when the checksum is done and CCHK0 bit is cleared.. - 15 + ERFO_EN + 27MHz Crystal Oscillator Enable. + 16 1 - pass - ROM Checksum Correct. + dis + Is Disabled. 0 - fail - ROM Checksum Fail. + en + Is Enabled. 1 - OVR - Operating Voltage Range. - 16 - 2 - - - - - RST0 - Reset. - 0x04 - - - DMA - DMA Reset. - 0 - 1 - - - WDT0 - Watchdog Timer Reset. - 1 + ERTCO_EN + 32kHz Crystal Oscillator Enable. + 17 1 - - GPIO0 - GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states. - 2 + + ISO_EN + 60MHz High Frequency Internal Reference Clock Enable. + 18 1 - - GPIO1 - GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states. - 3 + + IPO_EN + 96MHz High Frequency Internal Reference Clock Enable. + 19 1 - - TMR0 - Timer0 Reset. Setting this bit to 1 resets Timer 0 blocks. - 5 + + IBRO_EN + 8MHz High Frequency Internal Reference Clock Enable. + 20 1 - - TMR1 - Timer1 Reset. Setting this bit to 1 resets Timer 1 blocks. - 6 + + IBRO_VS + 7.3728MHz Internal Oscillator Voltage Source Select + 21 1 - - TMR2 - Timer2 Reset. Setting this bit to 1 resets Timer 2 blocks. - 7 + + ERFO_RDY + 27MHz Crystal Oscillator Ready + 24 1 + read-only + + + not + Is not Ready. + 0 + + + ready + Is Ready. + 1 + + - - TMR3 - Timer3 Reset. Setting this bit to 1 resets Timer 3 blocks. - 8 + + ERTCO_RDY + 32kHz Crystal Oscillator Ready + 25 1 - - TMR4 - Timer4 Reset. Setting this bit to 1 resets Timer 4 blocks. - 9 + + ISO_RDY + 60MHz ISO Ready. + 26 1 - - TMR5 - Timer5 Reset. Setting this bit to 1 resets Timer 5 blocks. - 10 + + IPO_RDY + Internal Primary Oscillator Ready. + 27 1 - - UART0 - UART0 Reset. Setting this bit to 1 resets all UART 0 blocks. - 11 + + IBRO_RDY + Internal Baud Rate Oscillator Ready. + 28 1 - - UART1 - UART1 Reset. Setting this bit to 1 resets all UART 1 blocks. - 12 - 1 - - - SPI0 - SPI0 Reset. Setting this bit to 1 resets all SPI 0 blocks. - 13 - 1 - - - SPI1 - SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks. - 14 - 1 - - - SPI2 - SPI2 Reset. Setting this bit to 1 resets all SPI 2 blocks. - 15 - 1 - - - I2C0 - I2C0 Reset. - 16 - 1 - - - RTC - Real Time Clock Reset. - 17 - 1 - - - TMR6 - Timer6 Reset. Setting this bit to 1 resets Timer 6 blocks. - 20 - 1 - - - TMR7 - Timer7 Reset. Setting this bit to 1 resets Timer 7 blocks. - 21 - 1 - - - SEMA - Semaphore Reset. - 22 - 1 - - - TRNG - TODO(5-2-2023): Remove this bit before release. TRNG Reset. Setting this bit resets the TRNG block. - 24 - 1 - - - ADC - Analog to Digital Reset. - 26 - 1 - - - UART2 - UART2 Reset. Setting this bit to 1 resets all UART 2 blocks. - 28 - 1 - - - SOFT - Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer. - 29 - 1 - - - PERIPH - Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset. - 30 - 1 - - - SYS - System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer. - 31 + + INRO_RDY + Internal Nano Ring Oscillator Low Frequency Reference Clock Ready. + 29 1 - CLKCTRL - Clock Control. - 0x08 - 0x00000008 + PM + Power Management. + 0x0C - PCLK_DIV - PCLK Divider. - 3 + MODE + Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode. + 0 3 - div1 - Divide by 1. + active + Active Mode. 0 - div2 - Divide by 2. - 1 - - - div4 - Divide by 4. + deepsleep + DeepSleep Mode. 2 - div8 - Divide by 8. + shutdown + Shutdown Mode. 3 + + backup + Backup Mode. + 4 + - SYSCLK_DIV - Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0. + GPIO_WE + GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set. + 4 + 1 + + + RTC_WE + RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers. + 5 + 1 + + + USB_WE + USB Wake Up Enable. This bit enables USB activity as wakeup source. 6 - 3 + 1 + + + ERFO_PD + Radio Frequency oscilator Crystal Power Down. This bit selects the power state in DEEPSLEEP mode. + 12 + 1 - div1 - Divide by 1. + active + Mode is Active. 0 - div2 - Divide by 2. + deepsleep + Powered down in DEEPSLEEP. 1 - - div4 - Divide by 4. - 2 - - - div8 - Divide by 8. - 3 - - - div16 - Divide by 16. - 4 - - - div32 - Divide by 32. - 5 - - - div64 - Divide by 64. - 6 - - - div128 - Divide by 128. - 7 - - SYSCLK_SEL - Clock Source Select. This 3 bit field selects the source for the system clock. - 9 - 3 + ISO_PD + Internal Secondary Oscilator Power Down. This bit selects the power state in DEEPSLEEP mode. + 15 + 1 - ISO - Internal Secondary Oscilatior Clock + active + Mode is Active. 0 - ERFO - 27MHz Crystal is used for the system clock. - 2 - - - INRO - 8kHz Internal Nano Ring Oscillator is used for the system clock. - 3 - - - IPO - The internal Primary oscillator is used for the system clock. - 4 + deepsleep + Powered down in DEEPSLEEP. + 1 + + + + IPO_PD + Internal Primary Oscilatory power down. This bit selects the power state in DEEPSLEEP mode. + 16 + 1 + - IBRO - The internal Baud Rate oscillator is used for the system clock. - 5 + active + Mode is Active. + 0 - ERTCO - 32kHz is used for the system clock. - 6 + deepsleep + Powered down in DEEPSLEEP. + 1 - SYSCLK_RDY - Clock Ready. This read only bit reflects whether the currently selected system clock source is running. - 13 + IBRO_PD + Internal Baud Rate Oscillator power down. This bit selects the power state in DEEPSLEEP mode. + 17 1 - read-only - busy - Switchover to the new clock source (as selected by CLKSEL) has not yet occurred. + active + Mode is Active. 0 - ready - System clock running from CLKSEL clock source. + deepsleep + Powered down in DEEPSLEEP. 1 - IPO_DIV - IPO clock divider - 14 - 2 + ERFO_BP + XTAL Bypass + 20 + 1 - DIV1 - Divide 1. - 0 - - - DIV2 - Divide 2. - 1 - - - DIV4 - Divide 4. - 2 - - - DIV8 - Divide 8. - 3 - - - - - ERFO_EN - 27MHz Crystal Oscillator Enable. - 16 - 1 - - - dis - Is Disabled. - 0 - - - en - Is Enabled. - 1 - - - - - ERTCO_EN - 32kHz Crystal Oscillator Enable. - 17 - 1 - - - ISO_EN - 60MHz High Frequency Internal Reference Clock Enable. - 18 - 1 - - - IPO_EN - 96MHz High Frequency Internal Reference Clock Enable. - 19 - 1 - - - IBRO_EN - 8MHz High Frequency Internal Reference Clock Enable. - 20 - 1 - - - IBRO_VS - 7.3728MHz Internal Oscillator Voltage Source Select - 21 - 1 - - - ERFO_RDY - 27MHz Crystal Oscillator Ready - 24 - 1 - read-only - - - not - Is not Ready. - 0 - - - ready - Is Ready. - 1 - - - - - ERTCO_RDY - 32kHz Crystal Oscillator Ready - 25 - 1 - - - ISO_RDY - 60MHz ISO Ready. - 26 - 1 - - - IPO_RDY - Internal Primary Oscillator Ready. - 27 - 1 - - - IBRO_RDY - Internal Baud Rate Oscillator Ready. - 28 - 1 - - - INRO_RDY - Internal Nano Ring Oscillator Low Frequency Reference Clock Ready. - 29 - 1 - - - - - PM - Power Management. - 0x0C - - - MODE - Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode. - 0 - 3 - - - active - Active Mode. - 0 - - - deepsleep - DeepSleep Mode. - 2 - - - shutdown - Shutdown Mode. - 3 - - - backup - Backup Mode. - 4 - - - - - GPIO_WE - GPIO Wake Up Enable. This bit enables all GPIO pins as potential wakeup sources. Any GPIO configured for wakeup is capable of causing an exit from IDLE or STANDBY modes when this bit is set. - 4 - 1 - - - RTC_WE - RTC Alarm Wake Up Enable. This bit enables RTC alarm as wakeup source. If enabled, the desired RTC alarm must be configured via the RTC control registers. - 5 - 1 - - - USB_WE - USB Wake Up Enable. This bit enables USB activity as wakeup source. - 6 - 1 - - - ERFO_PD - Radio Frequency oscilator Crystal Power Down. This bit selects the power state in DEEPSLEEP mode. - 12 - 1 - - - active - Mode is Active. - 0 - - - deepsleep - Powered down in DEEPSLEEP. - 1 - - - - - ISO_PD - Internal Secondary Oscilator Power Down. This bit selects the power state in DEEPSLEEP mode. - 15 - 1 - - - active - Mode is Active. - 0 - - - deepsleep - Powered down in DEEPSLEEP. - 1 - - - - - IPO_PD - Internal Primary Oscilatory power down. This bit selects the power state in DEEPSLEEP mode. - 16 - 1 - - - active - Mode is Active. - 0 - - - deepsleep - Powered down in DEEPSLEEP. - 1 - - - - - IBRO_PD - Internal Baud Rate Oscillator power down. This bit selects the power state in DEEPSLEEP mode. - 17 - 1 - - - active - Mode is Active. - 0 - - - deepsleep - Powered down in DEEPSLEEP. - 1 - - - - - ERFO_BP - XTAL Bypass - 20 - 1 - - - normal - Normal + normal + Normal 0 @@ -4607,1246 +3810,250 @@ 8 - RX_CNT - RX delay count. - 8 - 9 - - - TX_CNT - TX delay count. - 20 - 9 - - - - - FLVRST - Flash Low Voltage Reset Control Register - 0x80 - - - EN - Flash Low Voltage Reset Enable. - 0 - 1 - - - - - FLVCLKCTRL - Flash Low Voltage Clock Control Register - 0x84 - - - DIV - Flash Low Voltage Clock Divider Select. - 0 - 2 - - - 512 - Divide 512. - 0 - - - 256 - Divide 256 - 1 - - - 128 - Divide 128 - 2 - - - 64 - Divide 64 - 3 - - - - - - - FLVSTAT - Flash Low Voltage Status Register - 0x88 - - - FLV - Live Flash Low Voltage Detect Status. - 0 - 1 - - - ONES - FLV Buffer contains all ones if supply is above safe operating range. - 6 - 1 - - - ZEROS - FLV Buffer contains all zeros if supply is below safe operating voltage. - 7 - 1 - - - ONES_FL - Sticky version of ONES status. Write 1 to clear. - 14 - 1 - - - ZEROS_FL - Sticky version of ZEROS status. Write 1 to clear. - 15 - 1 - - - BUF - 10 Sample History of FLV status. - 16 - 10 - - - - - - - - GCFR - Global Control Function Register. - 0x40005800 - - 0x00 - 0x400 - registers - - - - REG0 - Register 0. - 0x00 - read-write - - - ISO_WUP - ISO Warm Up Value. - 0 - 9 - - - IPO_WUP - IPO Warm Up Value. - 16 - 11 - - - - - REG1 - Register 1. - 0x04 - read-write - - - ERFO_WUP - ERFO Warm Up Value. - 0 - 14 - - - IBRO_WUP - IBRO Warm Up Value. - 16 - 6 - - - - - - - - GPIO0 - Individual I/O for each GPIO - GPIO - 0x40008000 - - 0x00 - 0x1000 - registers - - - GPIO0 - GPIO0 interrupt. - 24 - - - - EN0 - GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port. - 0x00 - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - ALTERNATE - Alternate function enabled. - 0 - - - GPIO - GPIO function is enabled. - 1 - - - - - - - EN0_SET - GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1, without affecting other bits in that register. - 0x04 - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - - - EN0_CLR - GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register. - 0x08 - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - - - OUTEN - GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port. - 0x0C - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - dis - GPIO Output Disable - 0 - - - en - GPIO Output Enable - 1 - - - - - - - OUTEN_SET - GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1, without affecting other bits in that register. - 0x10 - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - - - OUTEN_CLR - GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, without affecting other bits in that register. - 0x14 - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - - - OUT - GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers. - 0x18 - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - low - Drive Logic 0 (low) on GPIO output. - 0 - - - high - Drive logic 1 (high) on GPIO output. - 1 - - - - - - - OUT_SET - GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1, without affecting other bits in that register. - 0x1C - write-only - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - no - No Effect. - 0 - - - set - Set GPIO_OUT bit in this position to '1' - 1 - - - - - - - OUT_CLR - GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0, without affecting other bits in that register. - 0x20 - write-only - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - - - IN - GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port. - 0x24 - read-only - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - - - INTMODE - GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port. - 0x28 - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - level - Interrupts for this pin are level triggered. - 0 - - - edge - Interrupts for this pin are edge triggered. - 1 - - - - - - - INTPOL - GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port. - 0x2C - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - falling - Interrupts are latched on a falling edge or low level condition for this pin. - 0 - - - rising - Interrupts are latched on a rising edge or high condition for this pin. - 1 - - - - - - - INEN - GPIO Input Enable - 0x30 - - - INTEN - GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port. - 0x34 - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - dis - Interrupts are disabled for this GPIO pin. - 0 - - - en - Interrupts are enabled for this GPIO pin. - 1 - - - - - - - INTEN_SET - GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits in that register. - 0x38 - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - no - No effect. - 0 - - - set - Set GPIO_INT_EN bit in this position to '1' - 1 - - - - - - - INTEN_CLR - GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0, without affecting other bits in that register. - 0x3C - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - no - No Effect. - 0 - - - clear - Clear GPIO_INT_EN bit in this position to '0' - 1 - - - - - - - INTFL - GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port. - 0x40 - read-only - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - no - No Interrupt is pending on this GPIO pin. - 0 - - - pending - An Interrupt is pending on this GPIO pin. - 1 - - - - - - - INTFL_CLR - GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits in that register. - 0x48 - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - - - WKEN - GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port. - 0x4C - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - dis - PMU wakeup for this GPIO is disabled. - 0 - - - en - PMU wakeup for this GPIO is enabled. - 1 - - - - - - - WKEN_SET - GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in that register. - 0x50 - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - - - WKEN_CLR - GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other bits in that register. - 0x54 - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - - - DUALEDGE - GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port. - 0x5C - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - no - No Effect. - 0 - - - en - Dual Edge mode is enabled. If edge-triggered interrupts are enabled on this GPIO pin, then both rising and falling edges will trigger interrupts regardless of the GPIO_INT_POL setting. - 1 - - - - - - - PADCTRL0 - GPIO Input Mode Config 0. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port. - 0x60 - - - ALL - The two bits in GPIO_PADCTRL0 and GPIO_PADCTRL1 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. - 0 - 32 - - - impedance - High Impedance. - 0 - - - pu - Weak pull-up mode. - 1 - - - pd - weak pull-down mode. - 2 - - - - - - - PADCTRL1 - GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port. - 0x64 - - - ALL - The two bits in GPIO_PADCTRL0 and GPIO_PADCTRL1 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. - 0 - 32 - - - impedance - High Impedance. - 0 - - - pu - Weak pull-up mode. - 1 - - - pd - weak pull-down mode. - 2 - - - - - - - EN1 - GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. - 0x68 - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - primary - Primary function selected. - 0 - - - secondary - Secondary function selected. - 1 - - - - - - - EN1_SET - GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register. - 0x6C - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - - - EN1_CLR - GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register. - 0x70 - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - - - EN2 - GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. - 0x74 - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - primary - Primary function selected. - 0 - - - secondary - Secondary function selected. - 1 - - - - - - - EN2_SET - GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1, without affecting other bits in that register. - 0x78 - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - - - EN2_CLR - GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0, without affecting other bits in that register. - 0x7C - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - - - HYSEN - GPIO Input Hysteresis Enable. - 0xA8 - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - - - SRSEL - GPIO Slew Rate Enable Register. - 0xAC - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - FAST - Fast Slew Rate selected. - 0 - - - SLOW - Slow Slew Rate selected. - 1 - - - - - - - DS0 - GPIO Drive Strength 0 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. - 0xB0 - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - ld - GPIO port pin is in low-drive mode. - 0 - - - hd - GPIO port pin is in high-drive mode. - 1 - - - - - - - DS1 - GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. - 0xB4 - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - - - PSSEL - GPIO Pull Select Mode. - 0xB8 - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - - - VSSEL - GPIO Voltage Select. - 0xC0 - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - - - - - - GPIO1 - Individual I/O for each GPIO 1 - 0x40009000 - - GPIO1 - GPIO1 IRQ - 25 - - - - - GPIO2 - Individual I/O for each GPIO 2 - 0x40080400 - - GPIO2 - GPIO2 IRQ - 26 - - - - - I2C0 - Inter-Integrated Circuit. - I2C - 0x4001D000 - 32 - - 0x00 - 0x1000 - registers - - - I2C0 - I2C0 IRQ - 13 - - - - CTRL - Control Register0. - 0x00 - - - EN - I2C Enable. - [0:0] - read-write - - - dis - Disable I2C. - 0 - - - en - enable I2C. - 1 - - - - - MST_MODE - Master Mode Enable. - [1:1] - read-write - - - slave_mode - Slave Mode. - 0 - - - master_mode - Master Mode. - 1 - - - - - GC_ADDR_EN - General Call Address Enable. - [2:2] - read-write - - - dis - Ignore Gneral Call Address. - 0 - - - en - Acknowledge general call address. - 1 - - - - - IRXM_EN - Interactive Receive Mode. - [3:3] - read-write - - - dis - Disable Interactive Receive Mode. - 0 - - - en - Enable Interactive Receive Mode. - 1 - - - - - IRXM_ACK - Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0. - [4:4] - read-write - - - ack - return ACK (pulling SDA LOW). - 0 - - - nack - return NACK (leaving SDA HIGH). - 1 - - - - - SCL_OUT - SCL Output. This bits control SCL output when SWOE =1. - [6:6] - read-write - - - drive_scl_low - Drive SCL low. - 0 - - - release_scl - Release SCL. - 1 - - - - - SDA_OUT - SDA Output. This bits control SDA output when SWOE = 1. - [7:7] - read-write - - - drive_sda_low - Drive SDA low. - 0 - - - release_sda - Release SDA. - 1 - - + RX_CNT + RX delay count. + 8 + 9 - SCL - SCL status. This bit reflects the logic gate of SCL signal. - [8:8] - read-only + TX_CNT + TX delay count. + 20 + 9 + + + + FLVRST + Flash Low Voltage Reset Control Register + 0x80 + - SDA - SDA status. THis bit reflects the logic gate of SDA signal. - [9:9] - read-only + EN + Flash Low Voltage Reset Enable. + 0 + 1 + + + + FLVCLKCTRL + Flash Low Voltage Clock Control Register + 0x84 + - BB_EN - Software Output Enable. - [10:10] - read-write + DIV + Flash Low Voltage Clock Divider Select. + 0 + 2 - outputs_disable - I2C Outputs SCLO and SDAO disabled. + 512 + Divide 512. 0 - outputs_enable - I2C Outputs SCLO and SDAO enabled. + 256 + Divide 256 1 - - - - READ - Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match (GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set. - [11:11] - read-only - - write - Write. - 0 + 128 + Divide 128 + 2 - read - Read. - 1 + 64 + Divide 64 + 3 + + + + FLVSTAT + Flash Low Voltage Status Register + 0x88 + - CLKSTR_DIS - This bit will disable slave clock stretching when set. - [12:12] - read-write - - - en - Slave clock stretching enabled. - 0 - - - dis - Slave clock stretching disabled. - 1 - - + FLV + Live Flash Low Voltage Detect Status. + 0 + 1 - ONE_MST_MODE - SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low. - [13:13] - read-write - - - dis - Standard open-drain operation: - drive low for 0, Hi-Z for 1 - 0 - - - en - Non-standard push-pull operation: - drive low for 0, drive high for 1 - 1 - - + ONES + FLV Buffer contains all ones if supply is above safe operating range. + 6 + 1 - HS_EN - High speed mode enable - [15:15] - read-write + ZEROS + FLV Buffer contains all zeros if supply is below safe operating voltage. + 7 + 1 + + + ONES_FL + Sticky version of ONES status. Write 1 to clear. + 14 + 1 + + + ZEROS_FL + Sticky version of ZEROS status. Write 1 to clear. + 15 + 1 + + + BUF + 10 Sample History of FLV status. + 16 + 10 + + + + + GPIO0 + Individual I/O for each GPIO + GPIO + 0x40008000 + + 0x00 + 0x1000 + registers + + + GPIO0 + GPIO0 interrupt. + 24 + + - STATUS - Status Register. - 0x04 + EN0 + GPIO Function Enable Register. Each bit controls the GPIO_EN setting for one GPIO pin on the associated port. + 0x00 - BUSY - Bus Status. - [0:0] - read-only + ALL + Mask of all of the pins on the port. + 0 + 32 - idle - I2C Bus Idle. + ALTERNATE + Alternate function enabled. 0 - busy - I2C Bus Busy. + GPIO + GPIO function is enabled. 1 + + + + EN0_SET + GPIO Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN to 1, without affecting other bits in that register. + 0x04 + - RX_EM - RX empty. - [1:1] - read-only - - - not_empty - Not Empty. - 0 - - - empty - Empty. - 1 - - + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + EN0_CLR + GPIO Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN to 0, without affecting other bits in that register. + 0x08 + - RX_FULL - RX Full. - [2:2] - read-only - - - not_full - Not Full. - 0 - - - full - Full. - 1 - - + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + OUTEN + GPIO Output Enable Register. Each bit controls the GPIO_OUT_EN setting for one GPIO pin in the associated port. + 0x0C + - TX_EM - TX Empty. - [3:3] + ALL + Mask of all of the pins on the port. + 0 + 32 - not_empty - Not Empty. + dis + GPIO Output Disable 0 - empty - Empty. + en + GPIO Output Enable 1 + + + + OUTEN_SET + GPIO Output Enable Set Function Enable Register. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT_EN to 1, without affecting other bits in that register. + 0x10 + - TX_FULL - TX Full. - [4:4] - - - not_empty - Not Empty. - 0 - - - empty - Empty. - 1 - - + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + OUTEN_CLR + GPIO Output Enable Clear Function Enable Register. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT_EN to 0, without affecting other bits in that register. + 0x14 + - MST_BUSY - Clock Mode. - [5:5] - read-only + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + OUT + GPIO Output Register. Each bit controls the GPIO_OUT setting for one pin in the associated port. This register can be written either directly, or by using the GPIO_OUT_SET and GPIO_OUT_CLR registers. + 0x18 + + + ALL + Mask of all of the pins on the port. + 0 + 32 - not_actively_driving_scl_clock - Device not actively driving SCL clock cycles. + low + Drive Logic 0 (low) on GPIO output. 0 - actively_driving_scl_clock - Device operating as master and actively driving SCL clock cycles. + high + Drive logic 1 (high) on GPIO output. 1 @@ -5854,2977 +4061,2581 @@ - INTFL0 - Interrupt Status Register. - 0x08 + OUT_SET + GPIO Output Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_OUT to 1, without affecting other bits in that register. + 0x1C + write-only - DONE - Transfer Done Interrupt. - [0:0] + ALL + Mask of all of the pins on the port. + 0 + 32 - INT_FL0_Done - inactive - No Interrupt is Pending. + no + No Effect. 0 - pending - An interrupt is pending. + set + Set GPIO_OUT bit in this position to '1' 1 + + + + OUT_CLR + GPIO Output Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_OUT to 0, without affecting other bits in that register. + 0x20 + write-only + - IRXM - Interactive Receive Interrupt. - [1:1] + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + IN + GPIO Input Register. Read-only register to read from the logic states of the GPIO pins on this port. + 0x24 + read-only + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + INTMODE + GPIO Interrupt Mode Register. Each bit in this register controls the interrupt mode setting for the associated GPIO pin on this port. + 0x28 + + + ALL + Mask of all of the pins on the port. + 0 + 32 - inactive - No Interrupt is Pending. + level + Interrupts for this pin are level triggered. 0 - pending - An interrupt is pending. + edge + Interrupts for this pin are edge triggered. 1 + + + + INTPOL + GPIO Interrupt Polarity Register. Each bit in this register controls the interrupt polarity setting for one GPIO pin in the associated port. + 0x2C + - GC_ADDR_MATCH - Slave General Call Address Match Interrupt. - [2:2] + ALL + Mask of all of the pins on the port. + 0 + 32 - inactive - No Interrupt is Pending. + falling + Interrupts are latched on a falling edge or low level condition for this pin. 0 - pending - An interrupt is pending. + rising + Interrupts are latched on a rising edge or high condition for this pin. 1 + + + + INEN + GPIO Input Enable + 0x30 + + + INTEN + GPIO Interrupt Enable Register. Each bit in this register controls the GPIO interrupt enable for the associated pin on the GPIO port. + 0x34 + - ADDR_MATCH - Slave Address Match Interrupt. - [3:3] + ALL + Mask of all of the pins on the port. + 0 + 32 - inactive - No Interrupt is Pending. + dis + Interrupts are disabled for this GPIO pin. 0 - pending - An interrupt is pending. + en + Interrupts are enabled for this GPIO pin. 1 + + + + INTEN_SET + GPIO Interrupt Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_INT_EN to 1, without affecting other bits in that register. + 0x38 + - RX_THD - Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level. - [4:4] + ALL + Mask of all of the pins on the port. + 0 + 32 - inactive - No interrupt is pending. + no + No effect. 0 - pending - An interrupt is pending. RX_FIFO equal or more bytes than the threshold. + set + Set GPIO_INT_EN bit in this position to '1' 1 + + + + INTEN_CLR + GPIO Interrupt Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_EN to 0, without affecting other bits in that register. + 0x3C + - TX_THD - Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level. - [5:5] + ALL + Mask of all of the pins on the port. + 0 + 32 - inactive - No interrupt is pending. + no + No Effect. 0 - pending - An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. + clear + Clear GPIO_INT_EN bit in this position to '0' 1 + + + + INTFL + GPIO Interrupt Status Register. Each bit in this register contains the pending interrupt status for the associated GPIO pin in this port. + 0x40 + read-only + - STOP - STOP Interrupt. - [6:6] + ALL + Mask of all of the pins on the port. + 0 + 32 - inactive - No interrupt is pending. + no + No Interrupt is pending on this GPIO pin. 0 pending - An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. + An Interrupt is pending on this GPIO pin. 1 + + + + INTFL_CLR + GPIO Status Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_INT_STAT to 0, without affecting other bits in that register. + 0x48 + - ADDR_ACK - Address Acknowledge Interrupt. - [7:7] + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + WKEN + GPIO Wake Enable Register. Each bit in this register controls the PMU wakeup enable for the associated GPIO pin in this port. + 0x4C + + + ALL + Mask of all of the pins on the port. + 0 + 32 - inactive - No Interrupt is Pending. + dis + PMU wakeup for this GPIO is disabled. 0 - pending - An interrupt is pending. + en + PMU wakeup for this GPIO is enabled. 1 + + + + WKEN_SET + GPIO Wake Enable Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_WAKE_EN to 1, without affecting other bits in that register. + 0x50 + - ARB_ERR - Arbritation error Interrupt. - [8:8] + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + WKEN_CLR + GPIO Wake Enable Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_WAKE_EN to 0, without affecting other bits in that register. + 0x54 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + DUALEDGE + GPIO Interrupt Dual Edge Mode Register. Each bit in this register selects dual edge mode for the associated GPIO pin in this port. + 0x5C + + + ALL + Mask of all of the pins on the port. + 0 + 32 - inactive - No Interrupt is Pending. + no + No Effect. 0 - pending - An interrupt is pending. + en + Dual Edge mode is enabled. If edge-triggered interrupts are enabled on this GPIO pin, then both rising and falling edges will trigger interrupts regardless of the GPIO_INT_POL setting. 1 + + + + PADCTRL0 + GPIO Input Mode Config 0. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port. + 0x60 + - TO_ERR - timeout Error Interrupt. - [9:9] + ALL + The two bits in GPIO_PADCTRL0 and GPIO_PADCTRL1 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. + 0 + 32 - inactive - No Interrupt is Pending. + impedance + High Impedance. 0 - pending - An interrupt is pending. + pu + Weak pull-up mode. 1 + + pd + weak pull-down mode. + 2 + + + + + PADCTRL1 + GPIO Input Mode Config 1. Each bit in this register enables the weak pull-up for the associated GPIO pin in this port. + 0x64 + - ADDR_NACK_ERR - Address NACK Error Interrupt. - [10:10] + ALL + The two bits in GPIO_PADCTRL0 and GPIO_PADCTRL1 for each GPIO pin work together to determine the pad mode when the GPIO is set to input mode. + 0 + 32 - inactive - No Interrupt is Pending. + impedance + High Impedance. 0 - pending - An interrupt is pending. + pu + Weak pull-up mode. 1 + + pd + weak pull-down mode. + 2 + + + + + EN1 + GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. + 0x68 + - DATA_ERR - Data NACK Error Interrupt. - [11:11] + ALL + Mask of all of the pins on the port. + 0 + 32 - inactive - No Interrupt is Pending. + primary + Primary function selected. 0 - pending - An interrupt is pending. + secondary + Secondary function selected. 1 + + + + EN1_SET + GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register. + 0x6C + - DNR_ERR - Do Not Respond Error Interrupt. - [12:12] + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN1_CLR + GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register. + 0x70 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN2 + GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. + 0x74 + + + ALL + Mask of all of the pins on the port. + 0 + 32 - inactive - No Interrupt is Pending. + primary + Primary function selected. 0 - pending - An interrupt is pending. + secondary + Secondary function selected. 1 + + + + EN2_SET + GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1, without affecting other bits in that register. + 0x78 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + EN2_CLR + GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0, without affecting other bits in that register. + 0x7C + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + HYSEN + GPIO Input Hysteresis Enable. + 0xA8 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + SRSEL + GPIO Slew Rate Enable Register. + 0xAC + - START_ERR - Start Error Interrupt. - [13:13] + ALL + Mask of all of the pins on the port. + 0 + 32 - inactive - No Interrupt is Pending. + FAST + Fast Slew Rate selected. 0 - pending - An interrupt is pending. + SLOW + Slow Slew Rate selected. 1 + + + + DS0 + GPIO Drive Strength 0 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. + 0xB0 + - STOP_ERR - Stop Error Interrupt. - [14:14] + ALL + Mask of all of the pins on the port. + 0 + 32 - inactive - No Interrupt is Pending. + ld + GPIO port pin is in low-drive mode. 0 - pending - An interrupt is pending. + hd + GPIO port pin is in high-drive mode. 1 + + + + DS1 + GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. + 0xB4 + - TX_LOCKOUT - Transmit Lock Out Interrupt. - [15:15] - - - MAMI - Multiple Address Match Interrupt - [21:16] + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + PSSEL + GPIO Pull Select Mode. + 0xB8 + - RD_ADDR_MATCH - Slave Read Address Match Interrupt - [22:22] + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + VSSEL + GPIO Voltage Select. + 0xC0 + - WR_ADDR_MATCH - Slave Write Address Match Interrupt - [23:23] + ALL + Mask of all of the pins on the port. + 0 + 32 + + + + + I2C0 + Inter-Integrated Circuit. + I2C + 0x4001D000 + 32 + + 0x00 + 0x1000 + registers + + + I2C0 + I2C0 IRQ + 13 + + - INTEN0 - Interrupt Enable Register. - 0x0C - read-write + CTRL + Control Register0. + 0x00 - DONE - Transfer Done Interrupt Enable. + EN + I2C Enable. [0:0] read-write dis - Interrupt disabled. + Disable I2C. 0 en - Interrupt enabled when DONE = 1. + enable I2C. 1 - IRXM - Description not available. + MST_MODE + Master Mode Enable. [1:1] read-write - dis - Interrupt disabled. + slave_mode + Slave Mode. 0 - en - Interrupt enabled when RX_MODE = 1. + master_mode + Master Mode. 1 - GC_ADDR_MATCH - Slave mode general call address match received input enable. + GC_ADDR_EN + General Call Address Enable. [2:2] read-write dis - Interrupt disabled. + Ignore Gneral Call Address. 0 en - Interrupt enabled when GEN_CTRL_ADDR = 1. + Acknowledge general call address. 1 - ADDR_MATCH - Slave mode incoming address match interrupt. + IRXM_EN + Interactive Receive Mode. [3:3] read-write dis - Interrupt disabled. + Disable Interactive Receive Mode. 0 en - Interrupt enabled when ADDR_MATCH = 1. + Enable Interactive Receive Mode. 1 - RX_THD - RX FIFO Above Treshold Level Interrupt Enable. + IRXM_ACK + Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0. [4:4] read-write - dis - Interrupt disabled. - 0 - - - en - Interrupt enabled. - 1 - - - - - TX_THD - TX FIFO Below Treshold Level Interrupt Enable. - [5:5] - - - dis - Interrupt disabled. + ack + return ACK (pulling SDA LOW). 0 - en - Interrupt enabled. + nack + return NACK (leaving SDA HIGH). 1 - STOP - Stop Interrupt Enable + SCL_OUT + SCL Output. This bits control SCL output when SWOE =1. [6:6] read-write - dis - Interrupt disabled. + drive_scl_low + Drive SCL low. 0 - en - Interrupt enabled when STOP = 1. + release_scl + Release SCL. 1 - ADDR_ACK - Received Address ACK from Slave Interrupt. + SDA_OUT + SDA Output. This bits control SDA output when SWOE = 1. [7:7] + read-write - dis - Interrupt disabled. - 0 - - - en - Interrupt enabled. - 1 - - - - - ARB_ERR - Master Mode Arbitration Lost Interrupt. - [8:8] - - - dis - Interrupt disabled. - 0 - - - en - Interrupt enabled. - 1 - - - - - TO_ERR - Timeout Error Interrupt Enable. - [9:9] - - - dis - Interrupt disabled. - 0 - - - en - Interrupt enabled. - 1 - - - - - ADDR_NACK_ERR - Master Mode Address NACK Received Interrupt. - [10:10] - - - dis - Interrupt disabled. + drive_sda_low + Drive SDA low. 0 - en - Interrupt enabled. + release_sda + Release SDA. 1 - DATA_ERR - Master Mode Data NACK Received Interrupt. - [11:11] + SCL + SCL status. This bit reflects the logic gate of SCL signal. + [8:8] + read-only + + + SDA + SDA status. THis bit reflects the logic gate of SDA signal. + [9:9] + read-only + + + BB_EN + Software Output Enable. + [10:10] + read-write - dis - Interrupt disabled. + outputs_disable + I2C Outputs SCLO and SDAO disabled. 0 - en - Interrupt enabled. + outputs_enable + I2C Outputs SCLO and SDAO enabled. 1 - DNR_ERR - Slave Mode Do Not Respond Interrupt. - [12:12] + READ + Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match (GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set. + [11:11] + read-only - dis - Interrupt disabled. + write + Write. 0 - en - Interrupt enabled. + read + Read. 1 - START_ERR - Out of Sequence START condition detected interrupt. - [13:13] + CLKSTR_DIS + This bit will disable slave clock stretching when set. + [12:12] + read-write - dis - Interrupt disabled. + en + Slave clock stretching enabled. 0 - en - Interrupt enabled. + dis + Slave clock stretching disabled. 1 - STOP_ERR - Out of Sequence STOP condition detected interrupt. - [14:14] + ONE_MST_MODE + SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low. + [13:13] + read-write dis - Interrupt disabled. + Standard open-drain operation: + drive low for 0, Hi-Z for 1 0 en - Interrupt enabled. + Non-standard push-pull operation: + drive low for 0, drive high for 1 1 - TX_LOCKOUT - TX FIFO Locked Out Interrupt. + HS_EN + High speed mode enable [15:15] - - - MAMI - Multiple Address Match Interrupt - [21:16] - - - RD_ADDR_MATCH - Slave Read Address Match Interrupt - [22:22] - - - WR_ADDR_MATCH - Slave Write Address Match Interrupt - [23:23] + read-write - INTFL1 - Interrupt Status Register 1. - 0x10 + STATUS + Status Register. + 0x04 - RX_OV - Receiver Overflow Interrupt. When operating as a slave receiver, this bit is set when you reach the first data bit and the RX FIFO and shift register are both full. + BUSY + Bus Status. [0:0] + read-only - inactive - No Interrupt is Pending. + idle + I2C Bus Idle. 0 - pending - An interrupt is pending. + busy + I2C Bus Busy. 1 - TX_UN - Transmit Underflow Interrupt. When operating as a slave transmitter, this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet). + RX_EM + RX empty. [1:1] + read-only - inactive - No Interrupt is Pending. + not_empty + Not Empty. 0 - pending - An interrupt is pending. + empty + Empty. 1 - START - START Condition Status Flag. + RX_FULL + RX Full. [2:2] - - - - - INTEN1 - Interrupt Staus Register 1. - 0x14 - read-write - - - RX_OV - Receiver Overflow Interrupt Enable. - [0:0] - - - dis - No Interrupt is Pending. - 0 - - - en - An interrupt is pending. - 1 - - - - - TX_UN - Transmit Underflow Interrupt Enable. - [1:1] + read-only - dis - No Interrupt is Pending. + not_full + Not Full. 0 - en - An interrupt is pending. + full + Full. 1 - START - START Condition Interrupt Enable. - [2:2] - - - - - FIFOLEN - FIFO Configuration Register. - 0x18 - - - RX_DEPTH - Receive FIFO Length. - [7:0] - read-only - - - TX_DEPTH - Transmit FIFO Length. - [15:8] - read-only - - - - - RXCTRL0 - Receive Control Register 0. - 0x1C - - - DNR - Do Not Respond. - [0:0] + TX_EM + TX Empty. + [3:3] - respond - Always respond to address match. + not_empty + Not Empty. 0 - not_respond_rx_fifo_empty - Do not respond to address match when RX_FIFO is not empty. + empty + Empty. 1 - FLUSH - Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status. - [7:7] + TX_FULL + TX Full. + [4:4] - not_flushed - FIFO not flushed. + not_empty + Not Empty. 0 - flush - Flush RX_FIFO. + empty + Empty. 1 - THD_LVL - Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold. - [11:8] - - - - - RXCTRL1 - Receive Control Register 1. - 0x20 - - - CNT - Receive Count Bits. These bits define the number of bytes to be received in a transaction, except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction. - [7:0] - - - LVL - Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0. - [11:8] + MST_BUSY + Clock Mode. + [5:5] read-only + + + not_actively_driving_scl_clock + Device not actively driving SCL clock cycles. + 0 + + + actively_driving_scl_clock + Device operating as master and actively driving SCL clock cycles. + 1 + + - TXCTRL0 - Transmit Control Register 0. - 0x24 + INTFL0 + Interrupt Status Register. + 0x08 - PRELOAD_MODE - Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match. + DONE + Transfer Done Interrupt. [0:0] - - - TX_READY_MODE - Transmit FIFO Ready Manual Mode. - [1:1] + INT_FL0_Done - en - HW control of I2CTXRDY enabled. + inactive + No Interrupt is Pending. 0 - dis - HW control of I2CTXRDY disabled. + pending + An interrupt is pending. 1 - GC_ADDR_FLUSH_DIS - TX FIFO General Call Address Match Auto Flush Disable. - [2:2] + IRXM + Interactive Receive Interrupt. + [1:1] - en - Enabled. + inactive + No Interrupt is Pending. 0 - dis - Disabled. + pending + An interrupt is pending. 1 - WR_ADDR_FLUSH_DIS - TX FIFO Slave Address Match Write Auto Flush Disable. - [3:3] + GC_ADDR_MATCH + Slave General Call Address Match Interrupt. + [2:2] - en - Enabled. + inactive + No Interrupt is Pending. 0 - dis - Disabled. + pending + An interrupt is pending. 1 - RD_ADDR_FLUSH_DIS - TX FIFO Slave Address Match Read Auto Flush Disable. - [4:4] + ADDR_MATCH + Slave Address Match Interrupt. + [3:3] - en - Enabled. + inactive + No Interrupt is Pending. 0 - dis - Disabled. + pending + An interrupt is pending. 1 - NACK_FLUSH_DIS - TX FIFO received NACK Auto Flush Disable. - [5:5] + RX_THD + Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level. + [4:4] - en - Enabled. + inactive + No interrupt is pending. 0 - dis - Disabled. + pending + An interrupt is pending. RX_FIFO equal or more bytes than the threshold. 1 - FLUSH - Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation. - [7:7] + TX_THD + Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level. + [5:5] - not_flushed - FIFO not flushed. + inactive + No interrupt is pending. 0 - flush - Flush TX_FIFO. + pending + An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. 1 - - THD_VAL - Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold. - [11:8] - - - - - TXCTRL1 - Transmit Control Register 1. - 0x28 - - - PRELOAD_RDY - Transmit FIFO Preload Ready. - [0:0] - - - LAST - Transmit Last. - [1:1] - - - LVL - Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO. - [11:8] - read-only - - - - - FIFO - Data Register. - 0x2C - - - DATA - Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location. - 0 - 8 - - - - - MSTCTRL - Master Control Register. - 0x30 - - - START - Setting this bit to 1 will start a master transfer. - [0:0] - - - RESTART - Setting this bit to 1 will generate a repeated START. - [1:1] - STOP - Setting this bit to 1 will generate a STOP condition. - [2:2] - - - EX_ADDR_EN - Slave Extend Address Select. - [7:7] + STOP Interrupt. + [6:6] - 7_bits_address - 7-bit address. + inactive + No interrupt is pending. 0 - 10_bits_address - 10-bit address. + pending + An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. 1 - CODE - Master Code. - [10:8] - - - IGN_ACK - Master Ignore Acknowledge. - [12:12] - - - - - CLKLO - Clock Low Register. - 0x34 - - - LO - Clock low. In master mode, these bits define the SCL low period. In slave mode, these bits define the time SCL will be held low after data is outputted. - [8:0] - - - - - CLKHI - Clock high Register. - 0x38 - - - HI - Clock High. In master mode, these bits define the SCL high period. - [8:0] - - - - - HSCLK - Clock high Register. - 0x3C - - - LO - Clock Low. This field sets the Hs-Mode clock low count. In Slave mode, this is the time SCL is held low after data is output on SDA. - [7:0] - - - HI - Clock High. This field sets the Hs-Mode clock high count. In Slave mode, this is the time SCL is held high after data is output on SDA - [15:8] - - - - - TIMEOUT - Timeout Register - 0x40 - - - SCL_TO_VAL - Timeout - [15:0] - - - - - DMA - DMA Register. - 0x48 - - - TX_EN - TX channel enable. - [0:0] + ADDR_ACK + Address Acknowledge Interrupt. + [7:7] - dis - Disable. + inactive + No Interrupt is Pending. 0 - en - Enable. + pending + An interrupt is pending. 1 - RX_EN - RX channel enable. - [1:1] + ARB_ERR + Arbritation error Interrupt. + [8:8] - dis - Disable. + inactive + No Interrupt is Pending. 0 - en - Enable. + pending + An interrupt is pending. 1 - - - - 4 - 4 - SLAVE_MULTI[%s] - Slave Address Register. - SLAVE0 - 0x4C - 32 - read-write - - - ADDR - Slave Address. - [9:0] - - - DIS - Slave Disable. - [10:10] - - EXT_ADDR_EN - Extended Address Select. - [15:15] + TO_ERR + timeout Error Interrupt. + [9:9] - 7_bits_address - 7-bit address. + inactive + No Interrupt is Pending. 0 - 10_bits_address - 10-bit address. + pending + An interrupt is pending. 1 - - - - SLAVE0 - Slave Address Register. - 0x4C - - - SLAVE1 - Slave Address Register. - 0x50 - - - SLAVE2 - Slave Address Register. - 0x54 - - - SLAVE3 - Slave Address Register. - 0x58 - - - - - - I2C1 - Inter-Integrated Circuit. 1 - 0x4001E000 - - I2C1 - I2C1 IRQ - 36 - - - - - I2C2 - Inter-Integrated Circuit. 2 - 0x4001F000 - - I2C2 - I2C2 IRQ - 62 - - - - - I2S - Inter-IC Sound Interface. - I2S - 0x40060000 - 32 - - 0x00 - 0x1000 - registers - - - I2S - I2S IRQ - 99 - - - - CTRL0CH0 - Global mode channel. - 0x00 - - - LSB_FIRST - LSB Transmit Receive First. - [1:1] - read-write - - - PDM_FILT - PDM Filter. - [2:2] - read-write - - - PDM_EN - PDM Enable. - [3:3] - read-write - - - USEDDR - DDR. - [4:4] - read-write - - - PDM_INV - Invert PDM. - [5:5] - read-write - - - CH_MODE - SCK Select. - [7:6] - read-write - - - WS_POL - WS polarity select. - [8:8] - read-write - - - MSB_LOC - MSB location. - [9:9] - read-only - - ALIGN - Align to MSB or LSB. + ADDR_NACK_ERR + Address NACK Error Interrupt. [10:10] - read-only + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + - EXT_SEL - External SCK/WS selection. + DATA_ERR + Data NACK Error Interrupt. [11:11] - read-write - - - STEREO - Stereo mode of I2S. - [13:12] - read-only - - - WSIZE - Data size when write to FIFO. - [15:14] - read-write - - - TX_EN - TX channel enable. - [16:16] - read-write - - - RX_EN - RX channel enable. - [17:17] - read-write - - - FLUSH - Flushes the TX/RX FIFO buffer. - [18:18] - read-write - - - RST - Write 1 to reset channel. - [19:19] - read-write - - - FIFO_LSB - Bit Field Control. - [20:20] - read-write - - - RX_THD_VAL - depth of receive FIFO for threshold interrupt generation. - [31:24] - read-write - - - - - CTRL1CH0 - Local channel Setup. - 0x10 - - - BITS_WORD - I2S word length. - [4:0] - read-write - - - EN - I2S clock enable. - [8:8] - read-write - - - SMP_SIZE - I2S sample size length. - [13:9] - read-write - - - CLKSEL - Select source clock for internal SCK mode. - [14:14] - read-write - - - ADJUST - LSB/MSB Justify. - [15:15] - read-write - - - CLKDIV - I2S clock frequency divisor. - [31:16] - read-write - - - - - FILTCH0 - Filter. - 0x20 - - - DMACH0 - DMA Control. - 0x30 - - - DMA_TX_THD_VAL - TX FIFO Level DMA Trigger. - [6:0] - read-write - - - DMA_TX_EN - TX DMA channel enable. - [7:7] - read-write - - - DMA_RX_THD_VAL - RX FIFO Level DMA Trigger. - [14:8] - read-write - - - DMA_RX_EN - RX DMA channel enable. - [15:15] - read-write + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + - TX_LVL - Number of data word in the TX FIFO. - [23:16] - read-write + DNR_ERR + Do Not Respond Error Interrupt. + [12:12] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + - RX_LVL - Number of data word in the RX FIFO. - [31:24] - read-write + START_ERR + Start Error Interrupt. + [13:13] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + - - - - FIFOCH0 - I2S Fifo. - 0x40 - - DATA - Load/unload location for TX and RX FIFO buffers. - [31:0] - read-write + STOP_ERR + Stop Error Interrupt. + [14:14] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + - - - - INTFL - ISR Status. - 0x50 - - RX_OV_CH0 - Status for RX FIFO Overrun interrupt. - [0:0] - read-write + TX_LOCKOUT + Transmit Lock Out Interrupt. + [15:15] - RX_THD_CH0 - Status for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field. - [1:1] - read-write + MAMI + Multiple Address Match Interrupt + [21:16] - TX_OB_CH0 - Status for interrupt when TX FIFO has only one byte remaining. - [2:2] - read-write + RD_ADDR_MATCH + Slave Read Address Match Interrupt + [22:22] - TX_HE_CH0 - Status for interrupt when TX FIFO is half empty. - [3:3] - read-write + WR_ADDR_MATCH + Slave Write Address Match Interrupt + [23:23] - INTEN - Interrupt Enable. - 0x54 + INTEN0 + Interrupt Enable Register. + 0x0C + read-write - RX_OV_CH0 - Enable for RX FIFO Overrun interrupt. + DONE + Transfer Done Interrupt Enable. [0:0] read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when DONE = 1. + 1 + + - RX_THD_CH0 - Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field. + IRXM + Description not available. [1:1] read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when RX_MODE = 1. + 1 + + - TX_OB_CH0 - Enable for interrupt when TX FIFO has only one byte remaining. + GC_ADDR_MATCH + Slave mode general call address match received input enable. [2:2] read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when GEN_CTRL_ADDR = 1. + 1 + + - TX_HE_CH0 - Enable for interrupt when TX FIFO is half empty. + ADDR_MATCH + Slave mode incoming address match interrupt. [3:3] read-write + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled when ADDR_MATCH = 1. + 1 + + - - - - EXTSETUP - Ext Control. - 0x58 - - EXT_BITS_WORD - Word Length for ch_mode. - [4:0] + RX_THD + RX FIFO Above Treshold Level Interrupt Enable. + [4:4] read-write - - - - - WKEN - Wakeup Enable. - 0x5C - - - WKFL - Wakeup Flags. - 0x60 - - - - - - ICC0 - Instruction Cache Controller Registers - 0x4002A000 - - 0x00 - 0x800 - registers - - - - INFO - Cache ID Register. - 0x0000 - read-only - - - RELNUM - Release Number. Identifies the RTL release version. - 0 - 6 - - - PARTNUM - Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter. - 6 - 4 - - - ID - Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter. - 10 - 6 - - - - - SZ - Memory Configuration Register. - 0x0004 - read-only - 0x00080008 - - - CCH - Cache Size. Indicates total size in Kbytes of cache. - 0 - 16 + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + - MEM - Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller. - 16 - 16 - - - - - CTRL - Cache Control and Status Register. - 0x0100 - + TX_THD + TX FIFO Below Treshold Level Interrupt Enable. + [5:5] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + + - EN - Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated. - 0 - 1 + STOP + Stop Interrupt Enable + [6:6] + read-write dis - Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array. + Interrupt disabled. 0 en - Cache Enabled. + Interrupt enabled when STOP = 1. 1 - RDY - Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready. - 16 - 1 - read-only + ADDR_ACK + Received Address ACK from Slave Interrupt. + [7:7] - notReady - Not Ready. + dis + Interrupt disabled. 0 - ready - Ready. + en + Interrupt enabled. 1 - - - - INVALIDATE - Invalidate All Registers. - 0x0700 - read-write - - - INVALID - Invalidate. - 0 - 32 - - - - - - - - LPCMP - Low Power Comparator - 0x40088000 - - 0x00 - 0x400 - registers - - - LPCMP - Low Power Comparato - 103 - - - - 3 - 4 - CTRL[%s] - Comparator Control Register. - 0x00 - - - EN - Comparator Enable. - 0 - 1 - - POL - Polarity Select - 5 - 1 + ARB_ERR + Master Mode Arbitration Lost Interrupt. + [8:8] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + - INTR_EN - IRQ Enable. - 6 - 1 + TO_ERR + Timeout Error Interrupt Enable. + [9:9] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + - OUT - Raw Compartor Input. - 14 - 1 + ADDR_NACK_ERR + Master Mode Address NACK Received Interrupt. + [10:10] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + - INTR_FL - IRQ Flag - 15 - 1 + DATA_ERR + Master Mode Data NACK Received Interrupt. + [11:11] + + + dis + Interrupt disabled. + 0 + + + en + Interrupt enabled. + 1 + + - - - - - - - LPGCR - Low Power Global Control. - 0x40080000 - - 0x00 - 0x400 - registers - - - - RST - Low Power Reset Register. - 0x08 - - GPIO2 - Low Power GPIO 2 Reset. - 0 - 1 + DNR_ERR + Slave Mode Do Not Respond Interrupt. + [12:12] - reset - read-write - reset_done - Reset complete. + dis + Interrupt disabled. 0 - busy - Starts Reset or indicates reset in progress. + en + Interrupt enabled. 1 - - WDT1 - Low Power Watchdog Timer 1 Reset. - 1 - 1 - - - TMR4 - Low Power Timer 4 Reset. - 2 - 1 - - - TMR5 - Low Power Timer 5 Reset. - 3 - 1 - - - UART3 - Low Power UART 3 Reset. - 4 - 1 - - - LPCOMP - Low Power Comparator Reset. - 6 - 1 - - - - - PCLKDIS - Low Power Peripheral Clock Disable Register. - 0x0C - - GPIO2 - Low Power GPIO 2 Clock Disable. - 0 - 1 + START_ERR + Out of Sequence START condition detected interrupt. + [13:13] - en - enable it. + dis + Interrupt disabled. 0 - dis - disable it. + en + Interrupt enabled. 1 - - WDT1 - Low Power Watchdog 1 Clock Disable. - 1 - 1 - - - TMR4 - Low Power Timer 4 Clock Disable. - 2 - 1 - - - TMR5 - Low Power Timer 5 Clock Disable. - 3 - 1 - - - UART3 - Low Power UART 3 Clock Disable. - 4 - 1 - - - LPCOMP - Low Power Comparator Clock Disable. - 6 - 1 - - - - - - - - MCR - Misc Control. - 0x40006C00 - - 0x00 - 0x400 - registers - - - - ECCEN - ECC Enable Register - 0x00 - - RAM0 - ECC System RAM0 Enable. - 0 - 1 + STOP_ERR + Out of Sequence STOP condition detected interrupt. + [14:14] dis - disabled. + Interrupt disabled. 0 en - enabled. + Interrupt enabled. 1 - - - - IPOTRIM - IPO Manual Trim Register - 0x04 - - - VAL - Manual Trim Value. - 0 - 8 - - - RANGE - Trim Range Select. - 8 - 1 - - - - - OUTEN - Output Enable Register. - 0x08 - - - SQWOUT_EN - Square Wave Output Enable. - 0 - 1 - - - PDOWN_EN - Power Down Output Enable. - 1 - 1 - - - - - CMP_CTRL - Comparator Control Register. - 0x0C - - - EN - Comparator Enable. - 0 - 1 - - POL - Polarity Select - 5 - 1 + TX_LOCKOUT + TX FIFO Locked Out Interrupt. + [15:15] - INTR_EN - IRQ Enable. - 6 - 1 + MAMI + Multiple Address Match Interrupt + [21:16] - OUT - Comparator Output State. - 14 - 1 + RD_ADDR_MATCH + Slave Read Address Match Interrupt + [22:22] - INTR_FL - IRQ Flag - 15 - 1 + WR_ADDR_MATCH + Slave Write Address Match Interrupt + [23:23] - CTRL - Control Register + INTFL1 + Interrupt Status Register 1. 0x10 - CMP_HYST - Comparator hysteresis control. - 0 - 2 - - - INRO_EN - INRO Enable. - 2 - 1 - - - ERTCO_EN - ERTCO Enable. - 3 - 1 - - - IBRO_EN - IBRO Enable. - 4 - 1 - - - ERTCO_LP_EN - Enable 32K Oscillator input. - 5 - 1 + RX_OV + Receiver Overflow Interrupt. When operating as a slave receiver, this bit is set when you reach the first data bit and the RX FIFO and shift register are both full. + [0:0] + + + inactive + No Interrupt is Pending. + 0 + + + pending + An interrupt is pending. + 1 + + - PADPUP_RST - Enable the Reset Pad Pull Up Resistors - 9 - 1 + TX_UN + Transmit Underflow Interrupt. When operating as a slave transmitter, this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet). + [1:1] - 1m - 1MOhm Pullup + inactive + No Interrupt is Pending. 0 - 25k - 25kOhm Pullup. + pending + An interrupt is pending. 1 - PADVDDIOHSEL_RST - Reset VIDDIOH Select. - 10 - 1 + START + START Condition Status Flag. + [2:2] - RTCRST - Reset Register. - 0x18 + INTEN1 + Interrupt Staus Register 1. + 0x14 + read-write - RTC - RTC Reset. - 0 - 1 + RX_OV + Receiver Overflow Interrupt Enable. + [0:0] + + + dis + No Interrupt is Pending. + 0 + + + en + An interrupt is pending. + 1 + + - - - - RTCTRIM - RTC Trim Register. - 0x1C - - X1 - RTC Trim X1. - 0 - 5 + TX_UN + Transmit Underflow Interrupt Enable. + [1:1] + + + dis + No Interrupt is Pending. + 0 + + + en + An interrupt is pending. + 1 + + - X2 - RTC Trim X2. - 8 - 5 + START + START Condition Interrupt Enable. + [2:2] - GPIO3_CTRL - GPIO3 Pin Control Register. - 0x20 + FIFOLEN + FIFO Configuration Register. + 0x18 - P30_OUT - GPIO3 Pin 0 Data Output. - 0 - 1 - - - P30_OUTEN - GPIO3 Pin 0 Output Enable. - 1 - 1 - - - P30_PUPEN - GPIO3 Pin 0 Pull-up Enable. - 2 - 1 - - - P30_IN - GPIO3 Pin 0 Input Status. - 3 - 1 - - - P31_OUT - GPIO3 Pin 1 Data Output. - 4 - 1 - - - P31_OUTEN - GPIO3 Pin 1 Output Enable. - 5 - 1 - - - P31_PUPEN - GPIO3 Pin 1 Pull-up Enable. - 6 - 1 + RX_DEPTH + Receive FIFO Length. + [7:0] + read-only - P31_IN - GPIO3 Pin 1 Input Status. - 7 - 1 + TX_DEPTH + Transmit FIFO Length. + [15:8] + read-only - LDOCTRL - LDO Control Register. - 0x60 + RXCTRL0 + Receive Control Register 0. + 0x1C - 0P9V_EN - LDO 0.9V Enable. - 0 - 1 + DNR + Do Not Respond. + [0:0] + + + respond + Always respond to address match. + 0 + + + not_respond_rx_fifo_empty + Do not respond to address match when RX_FIFO is not empty. + 1 + + + + + FLUSH + Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status. + [7:7] + + + not_flushed + FIFO not flushed. + 0 + + + flush + Flush RX_FIFO. + 1 + + + + + THD_LVL + Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold. + [11:8] - PWRMONST - LDO Control Register. - 0x64 + RXCTRL1 + Receive Control Register 1. + 0x20 - PORZ_VLOSS - Sticky bit indicating power-on status of core power domains of VDDIO, VDDIOH, VCOR - 0 - 1 - - - PORZ_VBAT - Sticky bit indicating power-on status of the battery. - 1 - 1 + CNT + Receive Count Bits. These bits define the number of bytes to be received in a transaction, except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction. + [7:0] - PORZ_VBB - Sticky bit indicating power-on status of the VBB. - 2 - 1 + LVL + Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0. + [11:8] + read-only + + + + TXCTRL0 + Transmit Control Register 0. + 0x24 + - PORZ_VDDCA - Sticky bit indicating power-on status of VAON_SW supply. - 4 - 1 + PRELOAD_MODE + Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match. + [0:0] - PORZ_VDDCB - Sticky bit indicating power-on status of VCORE_PAD supply. - 5 - 1 + TX_READY_MODE + Transmit FIFO Ready Manual Mode. + [1:1] + + + en + HW control of I2CTXRDY enabled. + 0 + + + dis + HW control of I2CTXRDY disabled. + 1 + + - PORZ_VDDA - Sticky bit indicating power-on status of VDDA (for analog) supply. - 6 - 1 + GC_ADDR_FLUSH_DIS + TX FIFO General Call Address Match Auto Flush Disable. + [2:2] + + + en + Enabled. + 0 + + + dis + Disabled. + 1 + + - PORZ_VDDB - Sticky bit indicating power-on status of VDDB (for USB) supply. - 7 - 1 + WR_ADDR_FLUSH_DIS + TX FIFO Slave Address Match Write Auto Flush Disable. + [3:3] + + + en + Enabled. + 0 + + + dis + Disabled. + 1 + + - RSTZ_VDDCB - Sticky bit indicating reset condition on VCORE supply. - 9 - 1 + RD_ADDR_FLUSH_DIS + TX FIFO Slave Address Match Read Auto Flush Disable. + [4:4] + + + en + Enabled. + 0 + + + dis + Disabled. + 1 + + - RSTZ_VDDA - Sticky bit indicating reset condition on VDDA (analog) supply. - 10 - 1 + NACK_FLUSH_DIS + TX FIFO received NACK Auto Flush Disable. + [5:5] + + + en + Enabled. + 0 + + + dis + Disabled. + 1 + + - RSTZ_VDDB - Sticky bit indicating reset condition on VDDB (USB) supply. - 11 - 1 + FLUSH + Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation. + [7:7] + + + not_flushed + FIFO not flushed. + 0 + + + flush + Flush TX_FIFO. + 1 + + - RSTZ_VDDIO - Sticky bit indicating reset condition on VDDIO supply. - 12 - 1 + THD_VAL + Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold. + [11:8] + + + + TXCTRL1 + Transmit Control Register 1. + 0x28 + - RSTZ_VDDIOH - Sticky bit indicating reset condition on VDDIOH supply. - 13 - 1 + PRELOAD_RDY + Transmit FIFO Preload Ready. + [0:0] - RSTZ_VBB - Sticky bit indicating reset condition on VBB supply. - 14 - 1 + LAST + Transmit Last. + [1:1] - RSTZ_LDO0P9V - Sticky bit indicating reset condition on 0.9V USB supply. - 16 - 1 + LVL + Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO. + [11:8] + read-only + + + + FIFO + Data Register. + 0x2C + - RSTZ_VDDCA - Sticky bit indicating reset condition on VCORE in Analog supply. - 17 - 1 + DATA + Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location. + 0 + 8 + + + + MSTCTRL + Master Control Register. + 0x30 + - RSTZ_VCOREHV - Sticky bit indicating high voltage reset condition on VCORE supply. - 18 - 1 + START + Setting this bit to 1 will start a master transfer. + [0:0] - RSTZ_VDDIOHV - Sticky bit indicating high voltage reset condition on VDDIO supply. - 19 - 1 + RESTART + Setting this bit to 1 will generate a repeated START. + [1:1] - RSTZ_VDDIOHHV - Sticky bit indicating high voltage reset condition on VDDIOH supply. - 20 - 1 + STOP + Setting this bit to 1 will generate a STOP condition. + [2:2] - RSTZ_VNFCRX - Sticky bit indicating reset condition on VNFCRX supply. - 21 - 1 + EX_ADDR_EN + Slave Extend Address Select. + [7:7] + + + 7_bits_address + 7-bit address. + 0 + + + 10_bits_address + 10-bit address. + 1 + + - RSTZ_VNFCTX - Sticky bit indicating reset condition on VNFCTX supply. - 22 - 1 + CODE + Master Code. + [10:8] - RSTZ_VNFC1V - Sticky bit indicating reset condition on VNFC1V supply. - 23 - 1 + IGN_ACK + Master Ignore Acknowledge. + [12:12] - - - - - OWM - 1-Wire Master Interface. - 0x4003D000 - 32 - read-write - - 0 - 0x1000 - registers - - - OneWire - 67 - - - CTRL0 - 1-Wire Master Control Register. - 0x0000 - read-write + CLKLO + Clock Low Register. + 0x34 - LL_EN - Enable Long Line Mode. - [0:0] - read-write - - - FPRESDET - Force Line During Presence Detect. - [1:1] - read-write + LO + Clock low. In master mode, these bits define the SCL low period. In slave mode, these bits define the time SCL will be held low after data is outputted. + [8:0] + + + + CLKHI + Clock high Register. + 0x38 + - BB_EN - Bit Bang Enable. - [2:2] - read-write + HI + Clock High. In master mode, these bits define the SCL high period. + [8:0] + + + + HSCLK + Clock high Register. + 0x3C + - EXT_PU_MODE - Provide an extra output control to control an external pullup. - [3:3] - read-write + LO + Clock Low. This field sets the Hs-Mode clock low count. In Slave mode, this is the time SCL is held low after data is output on SDA. + [7:0] - EXT_PU_EN - Enable External Pullup. - [4:4] - read-write + HI + Clock High. This field sets the Hs-Mode clock high count. In Slave mode, this is the time SCL is held high after data is output on SDA + [15:8] + + + + TIMEOUT + Timeout Register + 0x40 + - SB_EN - Enable Single Bit TX/RX Mode. - [5:5] - read-write + SCL_TO_VAL + Timeout + [15:0] + + + + DMA + DMA Register. + 0x48 + - OD - Enables overdrive speed for 1-Wire operations. - [6:6] - read-write + TX_EN + TX channel enable. + [0:0] + + + dis + Disable. + 0 + + + en + Enable. + 1 + + - INT_PU_EN - Enable intenral pullup. - [7:7] - read-write + RX_EN + RX channel enable. + [1:1] + + + dis + Disable. + 0 + + + en + Enable. + 1 + + - CLKDIV - 1-Wire Master Clock Divisor. - 0x0004 + 4 + 4 + SLAVE_MULTI[%s] + Slave Address Register. + SLAVE0 + 0x4C + 32 read-write - DIVISOR - Clock Divisor for 1Mhz. - [7:0] - read-write + ADDR + Slave Address. + [9:0] + + + DIS + Slave Disable. + [10:10] + + + EXT_ADDR_EN + Extended Address Select. + [15:15] + + + 7_bits_address + 7-bit address. + 0 + + + 10_bits_address + 10-bit address. + 1 + + - CTRL1 - 1-Wire Master Control/Status. - 0x0008 - read-write + SLAVE0 + Slave Address Register. + 0x4C + + + SLAVE1 + Slave Address Register. + 0x50 + + + SLAVE2 + Slave Address Register. + 0x54 + + + SLAVE3 + Slave Address Register. + 0x58 + + + + + + I2C1 + Inter-Integrated Circuit. 1 + 0x4001E000 + + I2C1 + I2C1 IRQ + 36 + + + + + I2C2 + Inter-Integrated Circuit. 2 + 0x4001F000 + + I2C2 + I2C2 IRQ + 62 + + + + + ICC0 + Instruction Cache Controller Registers + 0x4002A000 + + 0x00 + 0x800 + registers + + + + INFO + Cache ID Register. + 0x0000 + read-only - RST - Start OW Reset. - [0:0] - read-write - - - SRA_EN - Enable SRA Mode. - [1:1] - read-write - - - BB_OUT_EN - Bit Bang Output Enable. - [2:2] - read-write - - - INPUT_ST - OW Input State. - [3:3] - read-only + RELNUM + Release Number. Identifies the RTL release version. + 0 + 6 - OD_SPEC_ST - Overdrive Spec Mode. - [4:4] - read-only + PARTNUM + Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter. + 6 + 4 - PRESDET_ST - Presence Pulse Detected. - [7:7] - read-only + ID + Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter. + 10 + 6 - DATA - 1-Wire Master Data Buffer. - 0x000C - read-write + SZ + Memory Configuration Register. + 0x0004 + read-only + 0x00080008 - DATA - TX/RX Buffer. - [7:0] - read-write + CCH + Cache Size. Indicates total size in Kbytes of cache. + 0 + 16 + + + MEM + Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller. + 16 + 16 - INTFL - 1-Wire Master Interrupt Flags. - 0x0010 - read-write + CTRL + Cache Control and Status Register. + 0x0100 - RST_DONE - OW Reset Sequence Completed. - [0:0] - read-write - - - TX_EM - TX Data Empty Interrupt Flag. - [1:1] - read-write - - - RX_RDY - RX Data Ready Interrupt Flag - [2:2] - read-write - - - LINE_SHORT - OW Line Short Detected Interrupt Flag. - [3:3] - read-write + EN + Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated. + 0 + 1 + + + dis + Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array. + 0 + + + en + Cache Enabled. + 1 + + - LINE_LOW - OW Line Low Detected Interrupt Flag. - [4:4] - read-write + RDY + Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready. + 16 + 1 + read-only + + + notReady + Not Ready. + 0 + + + ready + Ready. + 1 + + - INTEN - 1-Wire Master Interrupt Enables. - 0x0014 + INVALIDATE + Invalidate All Registers. + 0x0700 read-write - RST_DONE - OW Reset Sequence Completed. - [0:0] - read-write - oneToClear - - - TX_EM - Tx Data Empty Interrupt Enable. - [1:1] - read-write - oneToClear - - - RX_RDY - Rx Data Ready Interrupt Enable. - [2:2] - read-write - oneToClear - - - LINE_SHORT - OW Line Short Detected Interrupt Enable. - [3:3] - read-write - oneToClear - - - LINE_LOW - OW Line Low Detected Interrupt Enable. - [4:4] - read-write - oneToClear + INVALID + Invalidate. + 0 + 32 - + - PT - Pulse Train - Pulse_Train - 0x4003C020 - 32 - read-write + MCR + Misc Control. + 0x40006C00 - 0 - 0x0010 + 0x00 + 0x400 registers - RATE_LENGTH - Pulse Train Configuration - 0x0000 - read-write + ECCEN + ECC Enable Register + 0x00 - rate_control - Pulse Train Enable and Rate Control. Set to 0 to disable the Pulse Train. + RAM0 + ECC System RAM0 Enable. 0 - 27 - read-write - - - mode - Pulse Train Output Mode/Train Length - 27 - 5 - read-write - - - 32_BIT - Pulse train, 32 bit pattern. - 0 - - - SQUARE_WAVE - Square wave mode. - 1 - - - 2_BIT - Pulse train, 2 bit pattern. - 2 - - - 3_BIT - Pulse train, 3 bit pattern. - 3 - - - 4_BIT - Pulse train, 4 bit pattern. - 4 - - - 5_BIT - Pulse train, 5 bit pattern. - 5 - - - 6_BIT - Pulse train, 6 bit pattern. - 6 - - - 7_BIT - Pulse train, 7 bit pattern. - 7 - - - 8_BIT - Pulse train, 8 bit pattern. - 8 - - - 9_BIT - Pulse train, 9 bit pattern. - 9 - - - 10_BIT - Pulse train, 10 bit pattern. - 10 - - - 11_BIT - Pulse train, 11 bit pattern. - 11 - - - 12_BIT - Pulse train, 12 bit pattern. - 12 - - - 13_BIT - Pulse train, 13 bit pattern. - 13 - - - 14_BIT - Pulse train, 14 bit pattern. - 14 - - - 15_BIT - Pulse train, 15 bit pattern. - 15 - - - 16_BIT - Pulse train, 16 bit pattern. - 16 - - - 17_BIT - Pulse train, 17 bit pattern. - 17 - - - 18_BIT - Pulse train, 18 bit pattern. - 18 - - - 19_BIT - Pulse train, 19 bit pattern. - 19 - - - 20_BIT - Pulse train, 20 bit pattern. - 20 - - - 21_BIT - Pulse train, 21 bit pattern. - 21 - - - 22_BIT - Pulse train, 22 bit pattern. - 22 - - - 23_BIT - Pulse train, 23 bit pattern. - 23 - - - 24_BIT - Pulse train, 24 bit pattern. - 24 - - - 25_BIT - Pulse train, 25 bit pattern. - 25 - - - 26_BIT - Pulse train, 26 bit pattern. - 26 - - - 27_BIT - Pulse train, 27 bit pattern. - 27 - - - 28_BIT - Pulse train, 28 bit pattern. - 28 - - - 29_BIT - Pulse train, 29 bit pattern. - 29 - + 1 + - 30_BIT - Pulse train, 30 bit pattern. - 30 + dis + disabled. + 0 - 31_BIT - Pulse train, 31 bit pattern. - 31 + en + enabled. + 1 - TRAIN - Write the repeating bit pattern that is shifted out, LSB first, when configured in Pulse Train mode. See PT_RATE_LENGTH.mode for setting the length. - 0x0004 - read-write + IPOTRIM + IPO Manual Trim Register + 0x04 + + + VAL + Manual Trim Value. + 0 + 8 + + + RANGE + Trim Range Select. + 8 + 1 + + - LOOP - Pulse Train Loop Count - 0x0008 - read-write + OUTEN + Output Enable Register. + 0x08 - count - Number of loops for this pulse train to repeat. + SQWOUT_EN + Square Wave Output Enable. 0 - 16 - read-write + 1 - delay - Delay between loops of the Pulse Train in PT Peripheral Clock cycles - 16 - 12 - read-write + PDOWN_EN + Power Down Output Enable. + 1 + 1 - RESTART - Pulse Train Auto-Restart Configuration. - 0x000C - read-write + CMP_CTRL + Comparator Control Register. + 0x0C - pt_x_select - Auto-Restart PT X Select + EN + Comparator Enable. 0 - 5 - read-write + 1 - on_pt_x_loop_exit - Enable Auto-Restart on PT X Loop Exit - 7 + POL + Polarity Select + 5 1 - read-write - pt_y_select - Auto-Restart PT Y Select - 8 - 5 - read-write + INTR_EN + IRQ Enable. + 6 + 1 + + + OUT + Comparator Output State. + 14 + 1 - on_pt_y_loop_exit - Enable Auto-Restart on PT Y Loop Exit + INTR_FL + IRQ Flag 15 1 - read-write - - - - - PT1 - Pulse Train 1 - 0x4003C030 - - - - PT2 - Pulse Train 2 - 0x4003C040 - - - - PT3 - Pulse Train 3 - 0x4003C050 - - - - PTG - Pulse Train Generation - Pulse_Train - 0x4003C000 - 32 - read-write - - 0 - 0x0018 - registers - - - PT - Pulse Train IRQ - 59 - - - ENABLE - Global Enable/Disable Controls for All Pulse Trains - 0x0000 - read-write + CTRL + Control Register + 0x10 - pt0 - Enable/Disable control for PT0 + CMP_HYST + Comparator hysteresis control. 0 + 2 + + + INRO_EN + INRO Enable. + 2 1 - read-write - pt1 - Enable/Disable control for PT1 - 1 + ERTCO_EN + ERTCO Enable. + 3 1 - read-write - pt2 - Enable/Disable control for PT2 - 2 + IBRO_EN + IBRO Enable. + 4 1 - read-write - pt3 - Enable/Disable control for PT3 - 3 + ERTCO_LP_EN + Enable 32K Oscillator input. + 5 + 1 + + + PADPUP_RST + Enable the Reset Pad Pull Up Resistors + 9 + 1 + + + 1m + 1MOhm Pullup + 0 + + + 25k + 25kOhm Pullup. + 1 + + + + + PADVDDIOHSEL_RST + Reset VIDDIOH Select. + 10 1 - read-write - RESYNC - Global Resync (All Pulse Trains) Control - 0x0004 - read-write + RTCRST + Reset Register. + 0x18 - pt0 - Resync control for PT0 + RTC + RTC Reset. 0 1 - read-write - - - pt1 - Resync control for PT1 - 1 - 1 - read-write + + + + RTCTRIM + RTC Trim Register. + 0x1C + - pt2 - Resync control for PT2 - 2 - 1 - read-write + X1 + RTC Trim X1. + 0 + 5 - pt3 - Resync control for PT3 - 3 - 1 - read-write + X2 + RTC Trim X2. + 8 + 5 - STOP_INTFL - Pulse Train Stop Interrupt Flags - 0x0008 - read-write + GPIO3_CTRL + GPIO3 Pin Control Register. + 0x20 - pt0 - Pulse Train 0 Stopped Interrupt Flag + P30_OUT + GPIO3 Pin 0 Data Output. 0 1 - read-write - pt1 - Pulse Train 1 Stopped Interrupt Flag + P30_OUTEN + GPIO3 Pin 0 Output Enable. 1 1 - read-write - pt2 - Pulse Train 2 Stopped Interrupt Flag + P30_PUPEN + GPIO3 Pin 0 Pull-up Enable. 2 1 - read-write - pt3 - Pulse Train 3 Stopped Interrupt Flag + P30_IN + GPIO3 Pin 0 Input Status. 3 1 - read-write + + + P31_OUT + GPIO3 Pin 1 Data Output. + 4 + 1 + + + P31_OUTEN + GPIO3 Pin 1 Output Enable. + 5 + 1 + + + P31_PUPEN + GPIO3 Pin 1 Pull-up Enable. + 6 + 1 + + + P31_IN + GPIO3 Pin 1 Input Status. + 7 + 1 - STOP_INTEN - Pulse Train Stop Interrupt Enable/Disable - 0x000C - read-write + LDOCTRL + LDO Control Register. + 0x60 - pt0 - Pulse Train 0 Stopped Interrupt Enable/Disable + 0P9V_EN + LDO 0.9V Enable. + 0 + 1 + + + + + PWRMONST + LDO Control Register. + 0x64 + + + PORZ_VLOSS + Sticky bit indicating power-on status of core power domains of VDDIO, VDDIOH, VCOR 0 1 - read-write - pt1 - Pulse Train 1 Stopped Interrupt Enable/Disable + PORZ_VBAT + Sticky bit indicating power-on status of the battery. 1 1 - read-write - pt2 - Pulse Train 2 Stopped Interrupt Enable/Disable + PORZ_VBB + Sticky bit indicating power-on status of the VBB. 2 1 - read-write - pt3 - Pulse Train 3 Stopped Interrupt Enable/Disable - 3 + PORZ_VDDCA + Sticky bit indicating power-on status of VAON_SW supply. + 4 + 1 + + + PORZ_VDDCB + Sticky bit indicating power-on status of VCORE_PAD supply. + 5 1 - read-write - - - - SAFE_EN - Pulse Train Global Safe Enable. - 0x0010 - write-only - - PT0 - 0 + PORZ_VDDA + Sticky bit indicating power-on status of VDDA (for analog) supply. + 6 1 - write-only - PT1 - 1 + PORZ_VDDB + Sticky bit indicating power-on status of VDDB (for USB) supply. + 7 1 - write-only - PT2 - 2 + RSTZ_VDDCB + Sticky bit indicating reset condition on VCORE supply. + 9 1 - write-only - PT3 - 3 + RSTZ_VDDA + Sticky bit indicating reset condition on VDDA (analog) supply. + 10 1 - write-only - - - - SAFE_DIS - Pulse Train Global Safe Disable. - 0x0014 - write-only - - PT0 - 0 + RSTZ_VDDB + Sticky bit indicating reset condition on VDDB (USB) supply. + 11 1 - write-only - PT1 - 1 + RSTZ_VDDIO + Sticky bit indicating reset condition on VDDIO supply. + 12 1 - write-only - PT2 - 2 + RSTZ_VDDIOH + Sticky bit indicating reset condition on VDDIOH supply. + 13 1 - write-only - PT3 - 3 + RSTZ_VBB + Sticky bit indicating reset condition on VBB supply. + 14 1 - write-only - - - - READY_INTFL - Pulse Train Ready Interrupt Flags - 0x0018 - read-write - - pt0 - Pulse Train 0 Ready Interrupt Flag - 0 + RSTZ_LDO0P9V + Sticky bit indicating reset condition on 0.9V USB supply. + 16 1 - read-write - pt1 - Pulse Train 1 Ready Interrupt Flag - 1 + RSTZ_VDDCA + Sticky bit indicating reset condition on VCORE in Analog supply. + 17 1 - read-write - pt2 - Pulse Train 2 Ready Interrupt Flag - 2 + RSTZ_VCOREHV + Sticky bit indicating high voltage reset condition on VCORE supply. + 18 1 - read-write - pt3 - Pulse Train 3 Ready Interrupt Flag - 3 + RSTZ_VDDIOHV + Sticky bit indicating high voltage reset condition on VDDIO supply. + 19 1 - read-write - - - - READY_INTEN - Pulse Train Ready Interrupt Enable/Disable - 0x001C - read-write - - pt0 - Pulse Train 0 Ready Interrupt Enable/Disable - 0 + RSTZ_VDDIOHHV + Sticky bit indicating high voltage reset condition on VDDIOH supply. + 20 1 - read-write - pt1 - Pulse Train 1 Ready Interrupt Enable/Disable - 1 + RSTZ_VNFCRX + Sticky bit indicating reset condition on VNFCRX supply. + 21 1 - read-write - pt2 - Pulse Train 2 Ready Interrupt Enable/Disable - 2 + RSTZ_VNFCTX + Sticky bit indicating reset condition on VNFCTX supply. + 22 1 - read-write - pt3 - Pulse Train 3 Ready Interrupt Enable/Disable - 3 + RSTZ_VNFC1V + Sticky bit indicating reset condition on VNFC1V supply. + 23 1 - read-write - + PWRSEQ Power Sequencer / Low Power Control Register. @@ -14392,9 +12203,8 @@ - TMR0 - 32-bit reloadable timer that can be used for timing and event counting. - Timers + TMR + Low-Power Configurable Timer 0x40010000 0x00 @@ -14402,20 +12212,19 @@ registers - TMR0 - TMR0 IRQ + TMR 5 CNT - Count. This register stores the current timer count. + Timer Counter Register. 0x00 - 0x00000001 + read-write COUNT - Count. + The current count value for the timer. This field increments as the timer counts. 0 32 @@ -14423,13 +12232,13 @@ CMP - Compare. This register stores the compare value, which is used to set the maximum count value to initiate a reload of the timer to 0x0001. + Timer Compare Register. 0x04 - 0x0000FFFF + read-write COMPARE - Compare. + The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer. 0 32 @@ -14437,12 +12246,15 @@ PWM - PWM. This register stores the value that is compared to the current timer count. + Timer PWM Register. 0x08 + read-write PWM - PWM + Timer PWM Match: + In PWM Mode, this field sets the count value for the first transition period of the PWM cycle. At the end of the cycle where CNT equals PWM, the PWM output transitions to the second period of the PWM cycle. The second PWM period count is stored in the CMP register. The value set for PWM must me less than the value set in CMP for PWM mode operation. Timer Capture Value: + In Capture, Compare, and Capture/Compare modes, this field is used to store the CNT value when a Capture, Compare, or Capture/Compare event occurs. 0 32 @@ -14450,232 +12262,411 @@ INTFL - Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt. + Timer Interrupt Status Register. 0x0C - oneToClear + read-write - IRQ - Clear Interrupt. + IRQ_A + Interrupt Flag for Timer A. 0 1 + + WRDONE_A + Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain. + 8 + 1 + + + WR_DIS_A + Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration. + 9 + 1 + + + IRQ_B + Interrupt Flag for Timer B. + 16 + 1 + + + WRDONE_B + Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain. + 24 + 1 + + + WR_DIS_B + Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration. + 25 + 1 + - CTRL + CTRL0 Timer Control Register. 0x10 + read-write - MODE - Timer Mode. + MODE_A + Mode Select for Timer A 0 - 3 + 4 - oneShot - One Shot Mode. + ONE_SHOT + One-Shot Mode 0 - continuous - Continuous Mode. + CONTINUOUS + Continuous Mode 1 - counter - Counter Mode. + COUNTER + Counter Mode 2 - pwm - PWM Mode. + PWM + PWM Mode 3 - capture - Capture Mode. + CAPTURE + Capture Mode 4 - compare - Compare Mode. + COMPARE + Compare Mode + 5 + + + GATED + Gated Mode + 6 + + + CAPCOMP + Capture/Compare Mode + 7 + + + DUAL_EDGE + Dual Edge Capture Mode + 8 + + + IGATED + Inactive Gated Mode + 14 + + + + + CLKDIV_A + Clock Divider Select for Timer A + 4 + 4 + + + DIV_BY_1 + Prescaler Divide-By-1 + 0 + + + DIV_BY_2 + Prescaler Divide-By-2 + 1 + + + DIV_BY_4 + Prescaler Divide-By-4 + 2 + + + DIV_BY_8 + Prescaler Divide-By-8 + 3 + + + DIV_BY_16 + Prescaler Divide-By-16 + 4 + + + DIV_BY_32 + Prescaler Divide-By-32 + 5 + + + DIV_BY_64 + Prescaler Divide-By-64 + 6 + + + DIV_BY_128 + Prescaler Divide-By-128 + 7 + + + DIV_BY_256 + Prescaler Divide-By-256 + 8 + + + DIV_BY_512 + Prescaler Divide-By-512 + 9 + + + DIV_BY_1024 + Prescaler Divide-By-1024 + 10 + + + DIV_BY_2048 + Prescaler Divide-By-2048 + 11 + + + DIV_BY_4096 + TBD + 12 + + + + + POL_A + Timer Polarity for Timer A + 8 + 1 + + + PWMSYNC_A + PWM Synchronization Mode for Timer A + 9 + 1 + + + NOLHPOL_A + PWM Phase A (Non-Overlapping High) Polarity for Timer A + 10 + 1 + + + NOLLPOL_A + PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A + 11 + 1 + + + PWMCKBD_A + PWM Phase A-Prime Output Disable for Timer A + 12 + 1 + + + RST_A + Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears. + 13 + 1 + + + CLKEN_A + Write 1 to Enable CLK_TMR for Timer A + 14 + 1 + + + EN_A + Enable for Timer A + 15 + 1 + + + MODE_B + Mode Select for Timer B + 16 + 4 + + + ONE_SHOT + One-Shot Mode + 0 + + + CONTINUOUS + Continuous Mode + 1 + + + COUNTER + Counter Mode + 2 + + + PWM + PWM Mode + 3 + + + CAPTURE + Capture Mode + 4 + + + COMPARE + Compare Mode 5 - gated - Gated Mode. + GATED + Gated Mode 6 - captureCompare - Capture/Compare Mode. + CAPCOMP + Capture/Compare Mode 7 + + DUAL_EDGE + Dual Edge Capture Mode + 8 + + + IGATED + Inactive Gated Mode + 14 + - CLKDIV - Prescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock, F_CNT_CLK = PCLK (HZ) /prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres[2:0]. - 3 - 3 + CLKDIV_B + Clock Divider Select for Timer B + 20 + 4 - div1 - Divide by 1. + DIV_BY_1 + Prescaler Divide-By-1 0 - div2 - Divide by 2. + DIV_BY_2 + Prescaler Divide-By-2 1 - div4 - Divide by 4. + DIV_BY_4 + Prescaler Divide-By-4 2 - div8 - Divide by 8. + DIV_BY_8 + Prescaler Divide-By-8 3 - div16 - Divide by 16. + DIV_BY_16 + Prescaler Divide-By-16 4 - div32 - Divide by 32. + DIV_BY_32 + Prescaler Divide-By-32 5 - div64 - Divide by 64. + DIV_BY_64 + Prescaler Divide-By-64 6 - div128 - Divide by 128. + DIV_BY_128 + Prescaler Divide-By-128 7 - - - - POL - Timer input/output polarity bit. - 6 - 1 - - activeHi - Active High. - 0 + DIV_BY_256 + Prescaler Divide-By-256 + 8 - activeLo - Active Low. - 1 + DIV_BY_512 + Prescaler Divide-By-512 + 9 - - - - EN - Timer Enable. - 7 - 1 - - dis - Disable. - 0 + DIV_BY_1024 + Prescaler Divide-By-1024 + 10 - en - Enable. - 1 + DIV_BY_2048 + Prescaler Divide-By-2048 + 11 + + + DIV_BY_4096 + TBD + 12 - CLKDIV3 - MSB of prescaler value. - 8 + POL_B + Timer Polarity for Timer B + 24 1 - PWMSYNC - Timer PWM Synchronization Mode Enable. - 9 + PWMSYNC_B + PWM Synchronization Mode for Timer B + 25 1 - - - dis - Disable. - 0 - - - en - Enable. - 1 - - - NOLHPOL - Timer PWM output 0A polarity bit. - 10 + NOLHPOL_B + PWM Phase A (Non-Overlapping High) Polarity for Timer B + 26 1 - - - dis - Disable. - 0 - - - en - Enable. - 1 - - - NOLLPOL - Timer PWM output 0A' polarity bit. - 11 + NOLLPOL_B + PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B + 27 1 - - - dis - Disable. - 0 - - - en - Enable. - 1 - - - PWMCKBD - Timer PWM output 0A Mode Disable. - 12 + PWMCKBD_B + PWM Phase A-Prime Output Disable for Timer B + 28 + 1 + + + RST_B + Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears. + 29 + 1 + + + CLKEN_B + Write 1 to Enable CLK_TMR for Timer B + 30 + 1 + + + EN_B + Enable for Timer B + 31 1 - - - dis - Disable. - 1 - - - en - Enable. - 0 - - @@ -14683,27 +12674,194 @@ NOLCMP Timer Non-Overlapping Compare Register. 0x14 + read-write - LO - Non-overlapping Low Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A and next rising edge of PWM output 0A'. + LO_A + Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime. 0 8 - HI - Non-overlapping High Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A' and next rising edge of PWM output 0A. + HI_A + Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A. 8 8 + + LO_B + Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime. + 16 + 8 + + + HI_B + Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A. + 24 + 8 + + + + + CTRL1 + Timer Configuration Register. + 0x18 + read-write + + + CLKSEL_A + Timer Clock Select for Timer A + 0 + 2 + + + CLKEN_A + Timer A Enable Status + 2 + 1 + + + CLKRDY_A + CLK_TMR Ready Flag for Timer A + 3 + 1 + + + EVENT_SEL_A + Event Select for Timer A + 4 + 3 + + + NEGTRIG_A + Negative Edge Trigger for Event for Timer A + 7 + 1 + + + IE_A + Interrupt Enable for Timer A + 8 + 1 + + + CAPEVENT_SEL_A + Capture Event Select for Timer A + 9 + 2 + + + SW_CAPEVENT_A + Software Capture Event for Timer A + 11 + 1 + + + WE_A + Wake-Up Enable for Timer A + 12 + 1 + + + OUTEN_A + OUT_OE_O Enable for Modes 0, 1,and 5 for Timer A + 13 + 1 + + + OUTBEN_A + PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A + 14 + 1 + + + CLKSEL_B + Timer Clock Select for Timer B + 16 + 2 + + + CLKEN_B + Timer B Enable Status + 18 + 1 + + + CLKRDY_B + CLK_TMR Ready Flag for Timer B + 19 + 1 + + + EVENT_SEL_B + Event Select for Timer B + 20 + 3 + + + NEGTRIG_B + Negative Edge Trigger for Event for Timer B + 23 + 1 + + + IE_B + Interrupt Enable for Timer B + 24 + 1 + + + CAPEVENT_SEL_B + Capture Event Select for Timer B + 25 + 2 + + + SW_CAPEVENT_B + Software Capture Event for Timer B + 27 + 1 + + + WE_B + Wake-Up Enable for Timer B + 28 + 1 + + + CASCADE + Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1. + 31 + 1 + + + + + WKFL + Timer Wakeup Status Register. + 0x1C + read-write + + + A + Wake-Up Flag for Timer A + 0 + 1 + + + B + Wake-Up Flag for Timer B + 16 + 1 + - - + + TMR1 - 32-bit reloadable timer that can be used for timing and event counting. 1 + Low-Power Configurable Timer 1 0x40011000 TMR1 @@ -14711,10 +12869,10 @@ 6 - - + + TMR2 - 32-bit reloadable timer that can be used for timing and event counting. 2 + Low-Power Configurable Timer 2 0x40012000 TMR2 @@ -14722,10 +12880,10 @@ 7 - - + + TMR3 - 32-bit reloadable timer that can be used for timing and event counting. 3 + Low-Power Configurable Timer 3 0x40013000 TMR3 @@ -14733,10 +12891,10 @@ 8 - - + + TMR4 - 32-bit reloadable timer that can be used for timing and event counting. 4 + Low-Power Configurable Timer 4 0x40080C00 TMR4 @@ -14744,10 +12902,10 @@ 9 - - + + TMR5 - 32-bit reloadable timer that can be used for timing and event counting. 5 + Low-Power Configurable Timer 5 0x40081000 TMR5 @@ -14755,7 +12913,7 @@ 10 - + TRIMSIR Trim System Initilazation Registers diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/tmr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/tmr_regs.h index a8284bef628..57f0be3dfcb 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/tmr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/tmr_regs.h @@ -7,8 +7,9 @@ /****************************************************************************** * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by * Analog Devices, Inc.), - * Copyright (C) 2024 Analog Devices, Inc. + * Copyright (C) 2023-2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -65,7 +66,7 @@ extern "C" { * @ingroup tmr * @defgroup tmr_registers TMR_Registers * @brief Registers, Bit Masks and Bit Positions for the TMR Peripheral Module. - * @details 32-bit reloadable timer that can be used for timing and event counting. + * @details Low-Power Configurable Timer */ /** @@ -77,8 +78,10 @@ typedef struct { __IO uint32_t cmp; /**< \b 0x04: TMR CMP Register */ __IO uint32_t pwm; /**< \b 0x08: TMR PWM Register */ __IO uint32_t intfl; /**< \b 0x0C: TMR INTFL Register */ - __IO uint32_t ctrl; /**< \b 0x10: TMR CTRL Register */ + __IO uint32_t ctrl0; /**< \b 0x10: TMR CTRL0 Register */ __IO uint32_t nolcmp; /**< \b 0x14: TMR NOLCMP Register */ + __IO uint32_t ctrl1; /**< \b 0x18: TMR CTRL1 Register */ + __IO uint32_t wkfl; /**< \b 0x1C: TMR WKFL Register */ } mxc_tmr_regs_t; /* Register offsets for module TMR */ @@ -92,14 +95,16 @@ typedef struct { #define MXC_R_TMR_CMP ((uint32_t)0x00000004UL) /**< Offset from TMR Base Address: 0x0004 */ #define MXC_R_TMR_PWM ((uint32_t)0x00000008UL) /**< Offset from TMR Base Address: 0x0008 */ #define MXC_R_TMR_INTFL ((uint32_t)0x0000000CUL) /**< Offset from TMR Base Address: 0x000C */ -#define MXC_R_TMR_CTRL ((uint32_t)0x00000010UL) /**< Offset from TMR Base Address: 0x0010 */ +#define MXC_R_TMR_CTRL0 ((uint32_t)0x00000010UL) /**< Offset from TMR Base Address: 0x0010 */ #define MXC_R_TMR_NOLCMP ((uint32_t)0x00000014UL) /**< Offset from TMR Base Address: 0x0014 */ +#define MXC_R_TMR_CTRL1 ((uint32_t)0x00000018UL) /**< Offset from TMR Base Address: 0x0018 */ +#define MXC_R_TMR_WKFL ((uint32_t)0x0000001CUL) /**< Offset from TMR Base Address: 0x001C */ /**@} end of group tmr_registers */ /** * @ingroup tmr_registers * @defgroup TMR_CNT TMR_CNT - * @brief Count. This register stores the current timer count. + * @brief Timer Counter Register. * @{ */ #define MXC_F_TMR_CNT_COUNT_POS 0 /**< CNT_COUNT Position */ @@ -110,8 +115,7 @@ typedef struct { /** * @ingroup tmr_registers * @defgroup TMR_CMP TMR_CMP - * @brief Compare. This register stores the compare value, which is used to set the - * maximum count value to initiate a reload of the timer to 0x0001. + * @brief Timer Compare Register. * @{ */ #define MXC_F_TMR_CMP_COMPARE_POS 0 /**< CMP_COMPARE Position */ @@ -122,8 +126,7 @@ typedef struct { /** * @ingroup tmr_registers * @defgroup TMR_PWM TMR_PWM - * @brief PWM. This register stores the value that is compared to the current timer - * count. + * @brief Timer PWM Register. * @{ */ #define MXC_F_TMR_PWM_PWM_POS 0 /**< PWM_PWM Position */ @@ -134,81 +137,188 @@ typedef struct { /** * @ingroup tmr_registers * @defgroup TMR_INTFL TMR_INTFL - * @brief Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the - * associated interrupt. + * @brief Timer Interrupt Status Register. * @{ */ -#define MXC_F_TMR_INTFL_IRQ_POS 0 /**< INTFL_IRQ Position */ -#define MXC_F_TMR_INTFL_IRQ ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_IRQ_POS)) /**< INTFL_IRQ Mask */ +#define MXC_F_TMR_INTFL_IRQ_A_POS 0 /**< INTFL_IRQ_A Position */ +#define MXC_F_TMR_INTFL_IRQ_A ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_IRQ_A_POS)) /**< INTFL_IRQ_A Mask */ + +#define MXC_F_TMR_INTFL_WRDONE_A_POS 8 /**< INTFL_WRDONE_A Position */ +#define MXC_F_TMR_INTFL_WRDONE_A ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WRDONE_A_POS)) /**< INTFL_WRDONE_A Mask */ + +#define MXC_F_TMR_INTFL_WR_DIS_A_POS 9 /**< INTFL_WR_DIS_A Position */ +#define MXC_F_TMR_INTFL_WR_DIS_A ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WR_DIS_A_POS)) /**< INTFL_WR_DIS_A Mask */ + +#define MXC_F_TMR_INTFL_IRQ_B_POS 16 /**< INTFL_IRQ_B Position */ +#define MXC_F_TMR_INTFL_IRQ_B ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_IRQ_B_POS)) /**< INTFL_IRQ_B Mask */ + +#define MXC_F_TMR_INTFL_WRDONE_B_POS 24 /**< INTFL_WRDONE_B Position */ +#define MXC_F_TMR_INTFL_WRDONE_B ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WRDONE_B_POS)) /**< INTFL_WRDONE_B Mask */ + +#define MXC_F_TMR_INTFL_WR_DIS_B_POS 25 /**< INTFL_WR_DIS_B Position */ +#define MXC_F_TMR_INTFL_WR_DIS_B ((uint32_t)(0x1UL << MXC_F_TMR_INTFL_WR_DIS_B_POS)) /**< INTFL_WR_DIS_B Mask */ /**@} end of group TMR_INTFL_Register */ /** * @ingroup tmr_registers - * @defgroup TMR_CTRL TMR_CTRL + * @defgroup TMR_CTRL0 TMR_CTRL0 * @brief Timer Control Register. * @{ */ -#define MXC_F_TMR_CTRL_MODE_POS 0 /**< CTRL_MODE Position */ -#define MXC_F_TMR_CTRL_MODE ((uint32_t)(0x7UL << MXC_F_TMR_CTRL_MODE_POS)) /**< CTRL_MODE Mask */ -#define MXC_V_TMR_CTRL_MODE_ONESHOT ((uint32_t)0x0UL) /**< CTRL_MODE_ONESHOT Value */ -#define MXC_S_TMR_CTRL_MODE_ONESHOT (MXC_V_TMR_CTRL_MODE_ONESHOT << MXC_F_TMR_CTRL_MODE_POS) /**< CTRL_MODE_ONESHOT Setting */ -#define MXC_V_TMR_CTRL_MODE_CONTINUOUS ((uint32_t)0x1UL) /**< CTRL_MODE_CONTINUOUS Value */ -#define MXC_S_TMR_CTRL_MODE_CONTINUOUS (MXC_V_TMR_CTRL_MODE_CONTINUOUS << MXC_F_TMR_CTRL_MODE_POS) /**< CTRL_MODE_CONTINUOUS Setting */ -#define MXC_V_TMR_CTRL_MODE_COUNTER ((uint32_t)0x2UL) /**< CTRL_MODE_COUNTER Value */ -#define MXC_S_TMR_CTRL_MODE_COUNTER (MXC_V_TMR_CTRL_MODE_COUNTER << MXC_F_TMR_CTRL_MODE_POS) /**< CTRL_MODE_COUNTER Setting */ -#define MXC_V_TMR_CTRL_MODE_PWM ((uint32_t)0x3UL) /**< CTRL_MODE_PWM Value */ -#define MXC_S_TMR_CTRL_MODE_PWM (MXC_V_TMR_CTRL_MODE_PWM << MXC_F_TMR_CTRL_MODE_POS) /**< CTRL_MODE_PWM Setting */ -#define MXC_V_TMR_CTRL_MODE_CAPTURE ((uint32_t)0x4UL) /**< CTRL_MODE_CAPTURE Value */ -#define MXC_S_TMR_CTRL_MODE_CAPTURE (MXC_V_TMR_CTRL_MODE_CAPTURE << MXC_F_TMR_CTRL_MODE_POS) /**< CTRL_MODE_CAPTURE Setting */ -#define MXC_V_TMR_CTRL_MODE_COMPARE ((uint32_t)0x5UL) /**< CTRL_MODE_COMPARE Value */ -#define MXC_S_TMR_CTRL_MODE_COMPARE (MXC_V_TMR_CTRL_MODE_COMPARE << MXC_F_TMR_CTRL_MODE_POS) /**< CTRL_MODE_COMPARE Setting */ -#define MXC_V_TMR_CTRL_MODE_GATED ((uint32_t)0x6UL) /**< CTRL_MODE_GATED Value */ -#define MXC_S_TMR_CTRL_MODE_GATED (MXC_V_TMR_CTRL_MODE_GATED << MXC_F_TMR_CTRL_MODE_POS) /**< CTRL_MODE_GATED Setting */ -#define MXC_V_TMR_CTRL_MODE_CAPTURECOMPARE ((uint32_t)0x7UL) /**< CTRL_MODE_CAPTURECOMPARE Value */ -#define MXC_S_TMR_CTRL_MODE_CAPTURECOMPARE (MXC_V_TMR_CTRL_MODE_CAPTURECOMPARE << MXC_F_TMR_CTRL_MODE_POS) /**< CTRL_MODE_CAPTURECOMPARE Setting */ - -#define MXC_F_TMR_CTRL_CLKDIV_POS 3 /**< CTRL_CLKDIV Position */ -#define MXC_F_TMR_CTRL_CLKDIV ((uint32_t)(0x7UL << MXC_F_TMR_CTRL_CLKDIV_POS)) /**< CTRL_CLKDIV Mask */ -#define MXC_V_TMR_CTRL_CLKDIV_DIV1 ((uint32_t)0x0UL) /**< CTRL_CLKDIV_DIV1 Value */ -#define MXC_S_TMR_CTRL_CLKDIV_DIV1 (MXC_V_TMR_CTRL_CLKDIV_DIV1 << MXC_F_TMR_CTRL_CLKDIV_POS) /**< CTRL_CLKDIV_DIV1 Setting */ -#define MXC_V_TMR_CTRL_CLKDIV_DIV2 ((uint32_t)0x1UL) /**< CTRL_CLKDIV_DIV2 Value */ -#define MXC_S_TMR_CTRL_CLKDIV_DIV2 (MXC_V_TMR_CTRL_CLKDIV_DIV2 << MXC_F_TMR_CTRL_CLKDIV_POS) /**< CTRL_CLKDIV_DIV2 Setting */ -#define MXC_V_TMR_CTRL_CLKDIV_DIV4 ((uint32_t)0x2UL) /**< CTRL_CLKDIV_DIV4 Value */ -#define MXC_S_TMR_CTRL_CLKDIV_DIV4 (MXC_V_TMR_CTRL_CLKDIV_DIV4 << MXC_F_TMR_CTRL_CLKDIV_POS) /**< CTRL_CLKDIV_DIV4 Setting */ -#define MXC_V_TMR_CTRL_CLKDIV_DIV8 ((uint32_t)0x3UL) /**< CTRL_CLKDIV_DIV8 Value */ -#define MXC_S_TMR_CTRL_CLKDIV_DIV8 (MXC_V_TMR_CTRL_CLKDIV_DIV8 << MXC_F_TMR_CTRL_CLKDIV_POS) /**< CTRL_CLKDIV_DIV8 Setting */ -#define MXC_V_TMR_CTRL_CLKDIV_DIV16 ((uint32_t)0x4UL) /**< CTRL_CLKDIV_DIV16 Value */ -#define MXC_S_TMR_CTRL_CLKDIV_DIV16 (MXC_V_TMR_CTRL_CLKDIV_DIV16 << MXC_F_TMR_CTRL_CLKDIV_POS) /**< CTRL_CLKDIV_DIV16 Setting */ -#define MXC_V_TMR_CTRL_CLKDIV_DIV32 ((uint32_t)0x5UL) /**< CTRL_CLKDIV_DIV32 Value */ -#define MXC_S_TMR_CTRL_CLKDIV_DIV32 (MXC_V_TMR_CTRL_CLKDIV_DIV32 << MXC_F_TMR_CTRL_CLKDIV_POS) /**< CTRL_CLKDIV_DIV32 Setting */ -#define MXC_V_TMR_CTRL_CLKDIV_DIV64 ((uint32_t)0x6UL) /**< CTRL_CLKDIV_DIV64 Value */ -#define MXC_S_TMR_CTRL_CLKDIV_DIV64 (MXC_V_TMR_CTRL_CLKDIV_DIV64 << MXC_F_TMR_CTRL_CLKDIV_POS) /**< CTRL_CLKDIV_DIV64 Setting */ -#define MXC_V_TMR_CTRL_CLKDIV_DIV128 ((uint32_t)0x7UL) /**< CTRL_CLKDIV_DIV128 Value */ -#define MXC_S_TMR_CTRL_CLKDIV_DIV128 (MXC_V_TMR_CTRL_CLKDIV_DIV128 << MXC_F_TMR_CTRL_CLKDIV_POS) /**< CTRL_CLKDIV_DIV128 Setting */ - -#define MXC_F_TMR_CTRL_POL_POS 6 /**< CTRL_POL Position */ -#define MXC_F_TMR_CTRL_POL ((uint32_t)(0x1UL << MXC_F_TMR_CTRL_POL_POS)) /**< CTRL_POL Mask */ - -#define MXC_F_TMR_CTRL_EN_POS 7 /**< CTRL_EN Position */ -#define MXC_F_TMR_CTRL_EN ((uint32_t)(0x1UL << MXC_F_TMR_CTRL_EN_POS)) /**< CTRL_EN Mask */ - -#define MXC_F_TMR_CTRL_CLKDIV3_POS 8 /**< CTRL_CLKDIV3 Position */ -#define MXC_F_TMR_CTRL_CLKDIV3 ((uint32_t)(0x1UL << MXC_F_TMR_CTRL_CLKDIV3_POS)) /**< CTRL_CLKDIV3 Mask */ - -#define MXC_F_TMR_CTRL_PWMSYNC_POS 9 /**< CTRL_PWMSYNC Position */ -#define MXC_F_TMR_CTRL_PWMSYNC ((uint32_t)(0x1UL << MXC_F_TMR_CTRL_PWMSYNC_POS)) /**< CTRL_PWMSYNC Mask */ - -#define MXC_F_TMR_CTRL_NOLHPOL_POS 10 /**< CTRL_NOLHPOL Position */ -#define MXC_F_TMR_CTRL_NOLHPOL ((uint32_t)(0x1UL << MXC_F_TMR_CTRL_NOLHPOL_POS)) /**< CTRL_NOLHPOL Mask */ - -#define MXC_F_TMR_CTRL_NOLLPOL_POS 11 /**< CTRL_NOLLPOL Position */ -#define MXC_F_TMR_CTRL_NOLLPOL ((uint32_t)(0x1UL << MXC_F_TMR_CTRL_NOLLPOL_POS)) /**< CTRL_NOLLPOL Mask */ - -#define MXC_F_TMR_CTRL_PWMCKBD_POS 12 /**< CTRL_PWMCKBD Position */ -#define MXC_F_TMR_CTRL_PWMCKBD ((uint32_t)(0x1UL << MXC_F_TMR_CTRL_PWMCKBD_POS)) /**< CTRL_PWMCKBD Mask */ - -/**@} end of group TMR_CTRL_Register */ +#define MXC_F_TMR_CTRL0_MODE_A_POS 0 /**< CTRL0_MODE_A Position */ +#define MXC_F_TMR_CTRL0_MODE_A ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_MODE_A_POS)) /**< CTRL0_MODE_A Mask */ +#define MXC_V_TMR_CTRL0_MODE_A_ONE_SHOT ((uint32_t)0x0UL) /**< CTRL0_MODE_A_ONE_SHOT Value */ +#define MXC_S_TMR_CTRL0_MODE_A_ONE_SHOT (MXC_V_TMR_CTRL0_MODE_A_ONE_SHOT << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_ONE_SHOT Setting */ +#define MXC_V_TMR_CTRL0_MODE_A_CONTINUOUS ((uint32_t)0x1UL) /**< CTRL0_MODE_A_CONTINUOUS Value */ +#define MXC_S_TMR_CTRL0_MODE_A_CONTINUOUS (MXC_V_TMR_CTRL0_MODE_A_CONTINUOUS << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_CONTINUOUS Setting */ +#define MXC_V_TMR_CTRL0_MODE_A_COUNTER ((uint32_t)0x2UL) /**< CTRL0_MODE_A_COUNTER Value */ +#define MXC_S_TMR_CTRL0_MODE_A_COUNTER (MXC_V_TMR_CTRL0_MODE_A_COUNTER << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_COUNTER Setting */ +#define MXC_V_TMR_CTRL0_MODE_A_PWM ((uint32_t)0x3UL) /**< CTRL0_MODE_A_PWM Value */ +#define MXC_S_TMR_CTRL0_MODE_A_PWM (MXC_V_TMR_CTRL0_MODE_A_PWM << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_PWM Setting */ +#define MXC_V_TMR_CTRL0_MODE_A_CAPTURE ((uint32_t)0x4UL) /**< CTRL0_MODE_A_CAPTURE Value */ +#define MXC_S_TMR_CTRL0_MODE_A_CAPTURE (MXC_V_TMR_CTRL0_MODE_A_CAPTURE << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_CAPTURE Setting */ +#define MXC_V_TMR_CTRL0_MODE_A_COMPARE ((uint32_t)0x5UL) /**< CTRL0_MODE_A_COMPARE Value */ +#define MXC_S_TMR_CTRL0_MODE_A_COMPARE (MXC_V_TMR_CTRL0_MODE_A_COMPARE << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_COMPARE Setting */ +#define MXC_V_TMR_CTRL0_MODE_A_GATED ((uint32_t)0x6UL) /**< CTRL0_MODE_A_GATED Value */ +#define MXC_S_TMR_CTRL0_MODE_A_GATED (MXC_V_TMR_CTRL0_MODE_A_GATED << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_GATED Setting */ +#define MXC_V_TMR_CTRL0_MODE_A_CAPCOMP ((uint32_t)0x7UL) /**< CTRL0_MODE_A_CAPCOMP Value */ +#define MXC_S_TMR_CTRL0_MODE_A_CAPCOMP (MXC_V_TMR_CTRL0_MODE_A_CAPCOMP << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_CAPCOMP Setting */ +#define MXC_V_TMR_CTRL0_MODE_A_DUAL_EDGE ((uint32_t)0x8UL) /**< CTRL0_MODE_A_DUAL_EDGE Value */ +#define MXC_S_TMR_CTRL0_MODE_A_DUAL_EDGE (MXC_V_TMR_CTRL0_MODE_A_DUAL_EDGE << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_DUAL_EDGE Setting */ +#define MXC_V_TMR_CTRL0_MODE_A_IGATED ((uint32_t)0xEUL) /**< CTRL0_MODE_A_IGATED Value */ +#define MXC_S_TMR_CTRL0_MODE_A_IGATED (MXC_V_TMR_CTRL0_MODE_A_IGATED << MXC_F_TMR_CTRL0_MODE_A_POS) /**< CTRL0_MODE_A_IGATED Setting */ + +#define MXC_F_TMR_CTRL0_CLKDIV_A_POS 4 /**< CTRL0_CLKDIV_A Position */ +#define MXC_F_TMR_CTRL0_CLKDIV_A ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_CLKDIV_A_POS)) /**< CTRL0_CLKDIV_A Mask */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1 ((uint32_t)0x0UL) /**< CTRL0_CLKDIV_A_DIV_BY_1 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_1 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2 ((uint32_t)0x1UL) /**< CTRL0_CLKDIV_A_DIV_BY_2 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_2 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4 ((uint32_t)0x2UL) /**< CTRL0_CLKDIV_A_DIV_BY_4 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_4 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_8 ((uint32_t)0x3UL) /**< CTRL0_CLKDIV_A_DIV_BY_8 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_8 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_8 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_8 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_16 ((uint32_t)0x4UL) /**< CTRL0_CLKDIV_A_DIV_BY_16 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_16 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_16 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_16 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_32 ((uint32_t)0x5UL) /**< CTRL0_CLKDIV_A_DIV_BY_32 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_32 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_32 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_32 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_64 ((uint32_t)0x6UL) /**< CTRL0_CLKDIV_A_DIV_BY_64 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_64 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_64 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_64 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_128 ((uint32_t)0x7UL) /**< CTRL0_CLKDIV_A_DIV_BY_128 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_128 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_128 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_128 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_256 ((uint32_t)0x8UL) /**< CTRL0_CLKDIV_A_DIV_BY_256 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_256 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_256 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_256 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_512 ((uint32_t)0x9UL) /**< CTRL0_CLKDIV_A_DIV_BY_512 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_512 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_512 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_512 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1024 ((uint32_t)0xAUL) /**< CTRL0_CLKDIV_A_DIV_BY_1024 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1024 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_1024 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_1024 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2048 ((uint32_t)0xBUL) /**< CTRL0_CLKDIV_A_DIV_BY_2048 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2048 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_2048 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_2048 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4096 ((uint32_t)0xCUL) /**< CTRL0_CLKDIV_A_DIV_BY_4096 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4096 (MXC_V_TMR_CTRL0_CLKDIV_A_DIV_BY_4096 << MXC_F_TMR_CTRL0_CLKDIV_A_POS) /**< CTRL0_CLKDIV_A_DIV_BY_4096 Setting */ + +#define MXC_F_TMR_CTRL0_POL_A_POS 8 /**< CTRL0_POL_A Position */ +#define MXC_F_TMR_CTRL0_POL_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_POL_A_POS)) /**< CTRL0_POL_A Mask */ + +#define MXC_F_TMR_CTRL0_PWMSYNC_A_POS 9 /**< CTRL0_PWMSYNC_A Position */ +#define MXC_F_TMR_CTRL0_PWMSYNC_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMSYNC_A_POS)) /**< CTRL0_PWMSYNC_A Mask */ + +#define MXC_F_TMR_CTRL0_NOLHPOL_A_POS 10 /**< CTRL0_NOLHPOL_A Position */ +#define MXC_F_TMR_CTRL0_NOLHPOL_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLHPOL_A_POS)) /**< CTRL0_NOLHPOL_A Mask */ + +#define MXC_F_TMR_CTRL0_NOLLPOL_A_POS 11 /**< CTRL0_NOLLPOL_A Position */ +#define MXC_F_TMR_CTRL0_NOLLPOL_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLLPOL_A_POS)) /**< CTRL0_NOLLPOL_A Mask */ + +#define MXC_F_TMR_CTRL0_PWMCKBD_A_POS 12 /**< CTRL0_PWMCKBD_A Position */ +#define MXC_F_TMR_CTRL0_PWMCKBD_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMCKBD_A_POS)) /**< CTRL0_PWMCKBD_A Mask */ + +#define MXC_F_TMR_CTRL0_RST_A_POS 13 /**< CTRL0_RST_A Position */ +#define MXC_F_TMR_CTRL0_RST_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_RST_A_POS)) /**< CTRL0_RST_A Mask */ + +#define MXC_F_TMR_CTRL0_CLKEN_A_POS 14 /**< CTRL0_CLKEN_A Position */ +#define MXC_F_TMR_CTRL0_CLKEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_CLKEN_A_POS)) /**< CTRL0_CLKEN_A Mask */ + +#define MXC_F_TMR_CTRL0_EN_A_POS 15 /**< CTRL0_EN_A Position */ +#define MXC_F_TMR_CTRL0_EN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_EN_A_POS)) /**< CTRL0_EN_A Mask */ + +#define MXC_F_TMR_CTRL0_MODE_B_POS 16 /**< CTRL0_MODE_B Position */ +#define MXC_F_TMR_CTRL0_MODE_B ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_MODE_B_POS)) /**< CTRL0_MODE_B Mask */ +#define MXC_V_TMR_CTRL0_MODE_B_ONE_SHOT ((uint32_t)0x0UL) /**< CTRL0_MODE_B_ONE_SHOT Value */ +#define MXC_S_TMR_CTRL0_MODE_B_ONE_SHOT (MXC_V_TMR_CTRL0_MODE_B_ONE_SHOT << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_ONE_SHOT Setting */ +#define MXC_V_TMR_CTRL0_MODE_B_CONTINUOUS ((uint32_t)0x1UL) /**< CTRL0_MODE_B_CONTINUOUS Value */ +#define MXC_S_TMR_CTRL0_MODE_B_CONTINUOUS (MXC_V_TMR_CTRL0_MODE_B_CONTINUOUS << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_CONTINUOUS Setting */ +#define MXC_V_TMR_CTRL0_MODE_B_COUNTER ((uint32_t)0x2UL) /**< CTRL0_MODE_B_COUNTER Value */ +#define MXC_S_TMR_CTRL0_MODE_B_COUNTER (MXC_V_TMR_CTRL0_MODE_B_COUNTER << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_COUNTER Setting */ +#define MXC_V_TMR_CTRL0_MODE_B_PWM ((uint32_t)0x3UL) /**< CTRL0_MODE_B_PWM Value */ +#define MXC_S_TMR_CTRL0_MODE_B_PWM (MXC_V_TMR_CTRL0_MODE_B_PWM << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_PWM Setting */ +#define MXC_V_TMR_CTRL0_MODE_B_CAPTURE ((uint32_t)0x4UL) /**< CTRL0_MODE_B_CAPTURE Value */ +#define MXC_S_TMR_CTRL0_MODE_B_CAPTURE (MXC_V_TMR_CTRL0_MODE_B_CAPTURE << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_CAPTURE Setting */ +#define MXC_V_TMR_CTRL0_MODE_B_COMPARE ((uint32_t)0x5UL) /**< CTRL0_MODE_B_COMPARE Value */ +#define MXC_S_TMR_CTRL0_MODE_B_COMPARE (MXC_V_TMR_CTRL0_MODE_B_COMPARE << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_COMPARE Setting */ +#define MXC_V_TMR_CTRL0_MODE_B_GATED ((uint32_t)0x6UL) /**< CTRL0_MODE_B_GATED Value */ +#define MXC_S_TMR_CTRL0_MODE_B_GATED (MXC_V_TMR_CTRL0_MODE_B_GATED << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_GATED Setting */ +#define MXC_V_TMR_CTRL0_MODE_B_CAPCOMP ((uint32_t)0x7UL) /**< CTRL0_MODE_B_CAPCOMP Value */ +#define MXC_S_TMR_CTRL0_MODE_B_CAPCOMP (MXC_V_TMR_CTRL0_MODE_B_CAPCOMP << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_CAPCOMP Setting */ +#define MXC_V_TMR_CTRL0_MODE_B_DUAL_EDGE ((uint32_t)0x8UL) /**< CTRL0_MODE_B_DUAL_EDGE Value */ +#define MXC_S_TMR_CTRL0_MODE_B_DUAL_EDGE (MXC_V_TMR_CTRL0_MODE_B_DUAL_EDGE << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_DUAL_EDGE Setting */ +#define MXC_V_TMR_CTRL0_MODE_B_IGATED ((uint32_t)0xEUL) /**< CTRL0_MODE_B_IGATED Value */ +#define MXC_S_TMR_CTRL0_MODE_B_IGATED (MXC_V_TMR_CTRL0_MODE_B_IGATED << MXC_F_TMR_CTRL0_MODE_B_POS) /**< CTRL0_MODE_B_IGATED Setting */ + +#define MXC_F_TMR_CTRL0_CLKDIV_B_POS 20 /**< CTRL0_CLKDIV_B Position */ +#define MXC_F_TMR_CTRL0_CLKDIV_B ((uint32_t)(0xFUL << MXC_F_TMR_CTRL0_CLKDIV_B_POS)) /**< CTRL0_CLKDIV_B Mask */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1 ((uint32_t)0x0UL) /**< CTRL0_CLKDIV_B_DIV_BY_1 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_1 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_1 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2 ((uint32_t)0x1UL) /**< CTRL0_CLKDIV_B_DIV_BY_2 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_2 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_2 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4 ((uint32_t)0x2UL) /**< CTRL0_CLKDIV_B_DIV_BY_4 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_4 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_4 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_8 ((uint32_t)0x3UL) /**< CTRL0_CLKDIV_B_DIV_BY_8 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_8 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_8 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_8 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_16 ((uint32_t)0x4UL) /**< CTRL0_CLKDIV_B_DIV_BY_16 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_16 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_16 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_16 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_32 ((uint32_t)0x5UL) /**< CTRL0_CLKDIV_B_DIV_BY_32 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_32 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_32 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_32 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_64 ((uint32_t)0x6UL) /**< CTRL0_CLKDIV_B_DIV_BY_64 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_64 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_64 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_64 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_128 ((uint32_t)0x7UL) /**< CTRL0_CLKDIV_B_DIV_BY_128 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_128 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_128 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_128 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_256 ((uint32_t)0x8UL) /**< CTRL0_CLKDIV_B_DIV_BY_256 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_256 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_256 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_256 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_512 ((uint32_t)0x9UL) /**< CTRL0_CLKDIV_B_DIV_BY_512 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_512 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_512 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_512 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1024 ((uint32_t)0xAUL) /**< CTRL0_CLKDIV_B_DIV_BY_1024 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_1024 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_1024 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_1024 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2048 ((uint32_t)0xBUL) /**< CTRL0_CLKDIV_B_DIV_BY_2048 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_2048 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_2048 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_2048 Setting */ +#define MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4096 ((uint32_t)0xCUL) /**< CTRL0_CLKDIV_B_DIV_BY_4096 Value */ +#define MXC_S_TMR_CTRL0_CLKDIV_B_DIV_BY_4096 (MXC_V_TMR_CTRL0_CLKDIV_B_DIV_BY_4096 << MXC_F_TMR_CTRL0_CLKDIV_B_POS) /**< CTRL0_CLKDIV_B_DIV_BY_4096 Setting */ + +#define MXC_F_TMR_CTRL0_POL_B_POS 24 /**< CTRL0_POL_B Position */ +#define MXC_F_TMR_CTRL0_POL_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_POL_B_POS)) /**< CTRL0_POL_B Mask */ + +#define MXC_F_TMR_CTRL0_PWMSYNC_B_POS 25 /**< CTRL0_PWMSYNC_B Position */ +#define MXC_F_TMR_CTRL0_PWMSYNC_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMSYNC_B_POS)) /**< CTRL0_PWMSYNC_B Mask */ + +#define MXC_F_TMR_CTRL0_NOLHPOL_B_POS 26 /**< CTRL0_NOLHPOL_B Position */ +#define MXC_F_TMR_CTRL0_NOLHPOL_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLHPOL_B_POS)) /**< CTRL0_NOLHPOL_B Mask */ + +#define MXC_F_TMR_CTRL0_NOLLPOL_B_POS 27 /**< CTRL0_NOLLPOL_B Position */ +#define MXC_F_TMR_CTRL0_NOLLPOL_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_NOLLPOL_B_POS)) /**< CTRL0_NOLLPOL_B Mask */ + +#define MXC_F_TMR_CTRL0_PWMCKBD_B_POS 28 /**< CTRL0_PWMCKBD_B Position */ +#define MXC_F_TMR_CTRL0_PWMCKBD_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_PWMCKBD_B_POS)) /**< CTRL0_PWMCKBD_B Mask */ + +#define MXC_F_TMR_CTRL0_RST_B_POS 29 /**< CTRL0_RST_B Position */ +#define MXC_F_TMR_CTRL0_RST_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_RST_B_POS)) /**< CTRL0_RST_B Mask */ + +#define MXC_F_TMR_CTRL0_CLKEN_B_POS 30 /**< CTRL0_CLKEN_B Position */ +#define MXC_F_TMR_CTRL0_CLKEN_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_CLKEN_B_POS)) /**< CTRL0_CLKEN_B Mask */ + +#define MXC_F_TMR_CTRL0_EN_B_POS 31 /**< CTRL0_EN_B Position */ +#define MXC_F_TMR_CTRL0_EN_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL0_EN_B_POS)) /**< CTRL0_EN_B Mask */ + +/**@} end of group TMR_CTRL0_Register */ /** * @ingroup tmr_registers @@ -216,14 +326,105 @@ typedef struct { * @brief Timer Non-Overlapping Compare Register. * @{ */ -#define MXC_F_TMR_NOLCMP_LO_POS 0 /**< NOLCMP_LO Position */ -#define MXC_F_TMR_NOLCMP_LO ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_LO_POS)) /**< NOLCMP_LO Mask */ +#define MXC_F_TMR_NOLCMP_LO_A_POS 0 /**< NOLCMP_LO_A Position */ +#define MXC_F_TMR_NOLCMP_LO_A ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_LO_A_POS)) /**< NOLCMP_LO_A Mask */ -#define MXC_F_TMR_NOLCMP_HI_POS 8 /**< NOLCMP_HI Position */ -#define MXC_F_TMR_NOLCMP_HI ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_HI_POS)) /**< NOLCMP_HI Mask */ +#define MXC_F_TMR_NOLCMP_HI_A_POS 8 /**< NOLCMP_HI_A Position */ +#define MXC_F_TMR_NOLCMP_HI_A ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_HI_A_POS)) /**< NOLCMP_HI_A Mask */ + +#define MXC_F_TMR_NOLCMP_LO_B_POS 16 /**< NOLCMP_LO_B Position */ +#define MXC_F_TMR_NOLCMP_LO_B ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_LO_B_POS)) /**< NOLCMP_LO_B Mask */ + +#define MXC_F_TMR_NOLCMP_HI_B_POS 24 /**< NOLCMP_HI_B Position */ +#define MXC_F_TMR_NOLCMP_HI_B ((uint32_t)(0xFFUL << MXC_F_TMR_NOLCMP_HI_B_POS)) /**< NOLCMP_HI_B Mask */ /**@} end of group TMR_NOLCMP_Register */ +/** + * @ingroup tmr_registers + * @defgroup TMR_CTRL1 TMR_CTRL1 + * @brief Timer Configuration Register. + * @{ + */ +#define MXC_F_TMR_CTRL1_CLKSEL_A_POS 0 /**< CTRL1_CLKSEL_A Position */ +#define MXC_F_TMR_CTRL1_CLKSEL_A ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_A_POS)) /**< CTRL1_CLKSEL_A Mask */ + +#define MXC_F_TMR_CTRL1_CLKEN_A_POS 2 /**< CTRL1_CLKEN_A Position */ +#define MXC_F_TMR_CTRL1_CLKEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKEN_A_POS)) /**< CTRL1_CLKEN_A Mask */ + +#define MXC_F_TMR_CTRL1_CLKRDY_A_POS 3 /**< CTRL1_CLKRDY_A Position */ +#define MXC_F_TMR_CTRL1_CLKRDY_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKRDY_A_POS)) /**< CTRL1_CLKRDY_A Mask */ + +#define MXC_F_TMR_CTRL1_EVENT_SEL_A_POS 4 /**< CTRL1_EVENT_SEL_A Position */ +#define MXC_F_TMR_CTRL1_EVENT_SEL_A ((uint32_t)(0x7UL << MXC_F_TMR_CTRL1_EVENT_SEL_A_POS)) /**< CTRL1_EVENT_SEL_A Mask */ + +#define MXC_F_TMR_CTRL1_NEGTRIG_A_POS 7 /**< CTRL1_NEGTRIG_A Position */ +#define MXC_F_TMR_CTRL1_NEGTRIG_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_NEGTRIG_A_POS)) /**< CTRL1_NEGTRIG_A Mask */ + +#define MXC_F_TMR_CTRL1_IE_A_POS 8 /**< CTRL1_IE_A Position */ +#define MXC_F_TMR_CTRL1_IE_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_IE_A_POS)) /**< CTRL1_IE_A Mask */ + +#define MXC_F_TMR_CTRL1_CAPEVENT_SEL_A_POS 9 /**< CTRL1_CAPEVENT_SEL_A Position */ +#define MXC_F_TMR_CTRL1_CAPEVENT_SEL_A ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CAPEVENT_SEL_A_POS)) /**< CTRL1_CAPEVENT_SEL_A Mask */ + +#define MXC_F_TMR_CTRL1_SW_CAPEVENT_A_POS 11 /**< CTRL1_SW_CAPEVENT_A Position */ +#define MXC_F_TMR_CTRL1_SW_CAPEVENT_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_SW_CAPEVENT_A_POS)) /**< CTRL1_SW_CAPEVENT_A Mask */ + +#define MXC_F_TMR_CTRL1_WE_A_POS 12 /**< CTRL1_WE_A Position */ +#define MXC_F_TMR_CTRL1_WE_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_WE_A_POS)) /**< CTRL1_WE_A Mask */ + +#define MXC_F_TMR_CTRL1_OUTEN_A_POS 13 /**< CTRL1_OUTEN_A Position */ +#define MXC_F_TMR_CTRL1_OUTEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTEN_A_POS)) /**< CTRL1_OUTEN_A Mask */ + +#define MXC_F_TMR_CTRL1_OUTBEN_A_POS 14 /**< CTRL1_OUTBEN_A Position */ +#define MXC_F_TMR_CTRL1_OUTBEN_A ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_OUTBEN_A_POS)) /**< CTRL1_OUTBEN_A Mask */ + +#define MXC_F_TMR_CTRL1_CLKSEL_B_POS 16 /**< CTRL1_CLKSEL_B Position */ +#define MXC_F_TMR_CTRL1_CLKSEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CLKSEL_B_POS)) /**< CTRL1_CLKSEL_B Mask */ + +#define MXC_F_TMR_CTRL1_CLKEN_B_POS 18 /**< CTRL1_CLKEN_B Position */ +#define MXC_F_TMR_CTRL1_CLKEN_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKEN_B_POS)) /**< CTRL1_CLKEN_B Mask */ + +#define MXC_F_TMR_CTRL1_CLKRDY_B_POS 19 /**< CTRL1_CLKRDY_B Position */ +#define MXC_F_TMR_CTRL1_CLKRDY_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CLKRDY_B_POS)) /**< CTRL1_CLKRDY_B Mask */ + +#define MXC_F_TMR_CTRL1_EVENT_SEL_B_POS 20 /**< CTRL1_EVENT_SEL_B Position */ +#define MXC_F_TMR_CTRL1_EVENT_SEL_B ((uint32_t)(0x7UL << MXC_F_TMR_CTRL1_EVENT_SEL_B_POS)) /**< CTRL1_EVENT_SEL_B Mask */ + +#define MXC_F_TMR_CTRL1_NEGTRIG_B_POS 23 /**< CTRL1_NEGTRIG_B Position */ +#define MXC_F_TMR_CTRL1_NEGTRIG_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_NEGTRIG_B_POS)) /**< CTRL1_NEGTRIG_B Mask */ + +#define MXC_F_TMR_CTRL1_IE_B_POS 24 /**< CTRL1_IE_B Position */ +#define MXC_F_TMR_CTRL1_IE_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_IE_B_POS)) /**< CTRL1_IE_B Mask */ + +#define MXC_F_TMR_CTRL1_CAPEVENT_SEL_B_POS 25 /**< CTRL1_CAPEVENT_SEL_B Position */ +#define MXC_F_TMR_CTRL1_CAPEVENT_SEL_B ((uint32_t)(0x3UL << MXC_F_TMR_CTRL1_CAPEVENT_SEL_B_POS)) /**< CTRL1_CAPEVENT_SEL_B Mask */ + +#define MXC_F_TMR_CTRL1_SW_CAPEVENT_B_POS 27 /**< CTRL1_SW_CAPEVENT_B Position */ +#define MXC_F_TMR_CTRL1_SW_CAPEVENT_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_SW_CAPEVENT_B_POS)) /**< CTRL1_SW_CAPEVENT_B Mask */ + +#define MXC_F_TMR_CTRL1_WE_B_POS 28 /**< CTRL1_WE_B Position */ +#define MXC_F_TMR_CTRL1_WE_B ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_WE_B_POS)) /**< CTRL1_WE_B Mask */ + +#define MXC_F_TMR_CTRL1_CASCADE_POS 31 /**< CTRL1_CASCADE Position */ +#define MXC_F_TMR_CTRL1_CASCADE ((uint32_t)(0x1UL << MXC_F_TMR_CTRL1_CASCADE_POS)) /**< CTRL1_CASCADE Mask */ + +/**@} end of group TMR_CTRL1_Register */ + +/** + * @ingroup tmr_registers + * @defgroup TMR_WKFL TMR_WKFL + * @brief Timer Wakeup Status Register. + * @{ + */ +#define MXC_F_TMR_WKFL_A_POS 0 /**< WKFL_A Position */ +#define MXC_F_TMR_WKFL_A ((uint32_t)(0x1UL << MXC_F_TMR_WKFL_A_POS)) /**< WKFL_A Mask */ + +#define MXC_F_TMR_WKFL_B_POS 16 /**< WKFL_B Position */ +#define MXC_F_TMR_WKFL_B ((uint32_t)(0x1UL << MXC_F_TMR_WKFL_B_POS)) /**< WKFL_B Mask */ + +/**@} end of group TMR_WKFL_Register */ + #ifdef __cplusplus } #endif diff --git a/Libraries/PeriphDrivers/Source/TMR/tmr_reva_me30.svd b/Libraries/PeriphDrivers/Source/TMR/tmr_reva_me30.svd deleted file mode 100644 index 9a0fe80a4a6..00000000000 --- a/Libraries/PeriphDrivers/Source/TMR/tmr_reva_me30.svd +++ /dev/null @@ -1,313 +0,0 @@ - - - - TMR0 - 32-bit reloadable timer that can be used for timing and event counting. - Timers - 0x40010000 - - 0x00 - 0x1000 - registers - - - TMR0 - TMR0 IRQ - 5 - - - - CNT - Count. This register stores the current timer count. - 0x00 - 0x00000001 - - - COUNT - Count. - 0 - 32 - - - - - CMP - Compare. This register stores the compare value, which is used to set the maximum count value to initiate a reload of the timer to 0x0001. - 0x04 - 0x0000FFFF - - - COMPARE - Compare. - 0 - 32 - - - - - PWM - PWM. This register stores the value that is compared to the current timer count. - 0x08 - - - PWM - PWM - 0 - 32 - - - - - INTFL - Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt. - 0x0C - oneToClear - - - IRQ - Clear Interrupt. - 0 - 1 - - - - - CTRL - Timer Control Register. - 0x10 - - - MODE - Timer Mode. - 0 - 3 - - - oneShot - One Shot Mode. - 0 - - - continuous - Continuous Mode. - 1 - - - counter - Counter Mode. - 2 - - - pwm - PWM Mode. - 3 - - - capture - Capture Mode. - 4 - - - compare - Compare Mode. - 5 - - - gated - Gated Mode. - 6 - - - captureCompare - Capture/Compare Mode. - 7 - - - - - CLKDIV - Prescaler. Set the Timer's prescaler value. The prescaler divides the PCLK input to the timer and sets the Timer's Count Clock, F_CNT_CLK = PCLK (HZ) /prescaler. The Timer's prescaler setting is a 4-bit value with pres3:pres[2:0]. - 3 - 3 - - - div1 - Divide by 1. - 0 - - - div2 - Divide by 2. - 1 - - - div4 - Divide by 4. - 2 - - - div8 - Divide by 8. - 3 - - - div16 - Divide by 16. - 4 - - - div32 - Divide by 32. - 5 - - - div64 - Divide by 64. - 6 - - - div128 - Divide by 128. - 7 - - - - - POL - Timer input/output polarity bit. - 6 - 1 - - - activeHi - Active High. - 0 - - - activeLo - Active Low. - 1 - - - - - EN - Timer Enable. - 7 - 1 - - - dis - Disable. - 0 - - - en - Enable. - 1 - - - - - CLKDIV3 - MSB of prescaler value. - 8 - 1 - - - PWMSYNC - Timer PWM Synchronization Mode Enable. - 9 - 1 - - - dis - Disable. - 0 - - - en - Enable. - 1 - - - - - NOLHPOL - Timer PWM output 0A polarity bit. - 10 - 1 - - - dis - Disable. - 0 - - - en - Enable. - 1 - - - - - NOLLPOL - Timer PWM output 0A' polarity bit. - 11 - 1 - - - dis - Disable. - 0 - - - en - Enable. - 1 - - - - - PWMCKBD - Timer PWM output 0A Mode Disable. - 12 - 1 - - - dis - Disable. - 1 - - - en - Enable. - 0 - - - - - - - NOLCMP - Timer Non-Overlapping Compare Register. - 0x14 - - - LO - Non-overlapping Low Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A and next rising edge of PWM output 0A'. - 0 - 8 - - - HI - Non-overlapping High Compare. The 8-bit timer count value of non-overlapping time between falling edge of PWM output 0A' and next rising edge of PWM output 0A. - 8 - 8 - - - - - - - \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/TMR/tmr_revb_me30.svd b/Libraries/PeriphDrivers/Source/TMR/tmr_revb_me30.svd new file mode 100644 index 00000000000..5bb17764a0d --- /dev/null +++ b/Libraries/PeriphDrivers/Source/TMR/tmr_revb_me30.svd @@ -0,0 +1,662 @@ + + + + TMR + Low-Power Configurable Timer + 0x40010000 + + 0x00 + 0x1000 + registers + + + TMR + + 1 + + + + + CNT + Timer Counter Register. + 0x00 + read-write + + + COUNT + The current count value for the timer. This field increments as the timer counts. + 0 + 32 + + + + + CMP + Timer Compare Register. + 0x04 + read-write + + + COMPARE + The value in this register is used as the compare value for the timer's count value. The compare field meaning is determined by the specific mode of the timer. + 0 + 32 + + + + + PWM + Timer PWM Register. + 0x08 + read-write + + + PWM + Timer PWM Match: + In PWM Mode, this field sets the count value for the first transition period of the PWM cycle. At the end of the cycle where CNT equals PWM, the PWM output transitions to the second period of the PWM cycle. The second PWM period count is stored in the CMP register. The value set for PWM must me less than the value set in CMP for PWM mode operation. Timer Capture Value: + In Capture, Compare, and Capture/Compare modes, this field is used to store the CNT value when a Capture, Compare, or Capture/Compare event occurs. + 0 + 32 + + + + + INTFL + Timer Interrupt Status Register. + 0x0C + read-write + + + IRQ_A + Interrupt Flag for Timer A. + 0 + 1 + + + WRDONE_A + Write Done Flag for Timer A indicating the write is complete from APB to CLK_TMR domain. + 8 + 1 + + + WR_DIS_A + Write Disable to CNT/PWM for Timer A in the non-cascaded dual timer configuration. + 9 + 1 + + + IRQ_B + Interrupt Flag for Timer B. + 16 + 1 + + + WRDONE_B + Write Done Flag for Timer B indicating the write is complete from APB to CLK_TMR domain. + 24 + 1 + + + WR_DIS_B + Write Disable to CNT/PWM for Timer B in the non-cascaded dual timer configuration. + 25 + 1 + + + + + CTRL0 + Timer Control Register. + 0x10 + read-write + + + MODE_A + Mode Select for Timer A + 0 + 4 + + + ONE_SHOT + One-Shot Mode + 0 + + + CONTINUOUS + Continuous Mode + 1 + + + COUNTER + Counter Mode + 2 + + + PWM + PWM Mode + 3 + + + CAPTURE + Capture Mode + 4 + + + COMPARE + Compare Mode + 5 + + + GATED + Gated Mode + 6 + + + CAPCOMP + Capture/Compare Mode + 7 + + + DUAL_EDGE + Dual Edge Capture Mode + 8 + + + IGATED + Inactive Gated Mode + 14 + + + + + CLKDIV_A + Clock Divider Select for Timer A + 4 + 4 + + + DIV_BY_1 + Prescaler Divide-By-1 + 0 + + + DIV_BY_2 + Prescaler Divide-By-2 + 1 + + + DIV_BY_4 + Prescaler Divide-By-4 + 2 + + + DIV_BY_8 + Prescaler Divide-By-8 + 3 + + + DIV_BY_16 + Prescaler Divide-By-16 + 4 + + + DIV_BY_32 + Prescaler Divide-By-32 + 5 + + + DIV_BY_64 + Prescaler Divide-By-64 + 6 + + + DIV_BY_128 + Prescaler Divide-By-128 + 7 + + + DIV_BY_256 + Prescaler Divide-By-256 + 8 + + + DIV_BY_512 + Prescaler Divide-By-512 + 9 + + + DIV_BY_1024 + Prescaler Divide-By-1024 + 10 + + + DIV_BY_2048 + Prescaler Divide-By-2048 + 11 + + + DIV_BY_4096 + TBD + 12 + + + + + POL_A + Timer Polarity for Timer A + 8 + 1 + + + PWMSYNC_A + PWM Synchronization Mode for Timer A + 9 + 1 + + + NOLHPOL_A + PWM Phase A (Non-Overlapping High) Polarity for Timer A + 10 + 1 + + + NOLLPOL_A + PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer A + 11 + 1 + + + PWMCKBD_A + PWM Phase A-Prime Output Disable for Timer A + 12 + 1 + + + RST_A + Resets all flip flops in the CLK_TMR domain for Timer A. Self-clears. + 13 + 1 + + + CLKEN_A + Write 1 to Enable CLK_TMR for Timer A + 14 + 1 + + + EN_A + Enable for Timer A + 15 + 1 + + + MODE_B + Mode Select for Timer B + 16 + 4 + + + ONE_SHOT + One-Shot Mode + 0 + + + CONTINUOUS + Continuous Mode + 1 + + + COUNTER + Counter Mode + 2 + + + PWM + PWM Mode + 3 + + + CAPTURE + Capture Mode + 4 + + + COMPARE + Compare Mode + 5 + + + GATED + Gated Mode + 6 + + + CAPCOMP + Capture/Compare Mode + 7 + + + DUAL_EDGE + Dual Edge Capture Mode + 8 + + + IGATED + Inactive Gated Mode + 14 + + + + + CLKDIV_B + Clock Divider Select for Timer B + 20 + 4 + + + DIV_BY_1 + Prescaler Divide-By-1 + 0 + + + DIV_BY_2 + Prescaler Divide-By-2 + 1 + + + DIV_BY_4 + Prescaler Divide-By-4 + 2 + + + DIV_BY_8 + Prescaler Divide-By-8 + 3 + + + DIV_BY_16 + Prescaler Divide-By-16 + 4 + + + DIV_BY_32 + Prescaler Divide-By-32 + 5 + + + DIV_BY_64 + Prescaler Divide-By-64 + 6 + + + DIV_BY_128 + Prescaler Divide-By-128 + 7 + + + DIV_BY_256 + Prescaler Divide-By-256 + 8 + + + DIV_BY_512 + Prescaler Divide-By-512 + 9 + + + DIV_BY_1024 + Prescaler Divide-By-1024 + 10 + + + DIV_BY_2048 + Prescaler Divide-By-2048 + 11 + + + DIV_BY_4096 + TBD + 12 + + + + + POL_B + Timer Polarity for Timer B + 24 + 1 + + + PWMSYNC_B + PWM Synchronization Mode for Timer B + 25 + 1 + + + NOLHPOL_B + PWM Phase A (Non-Overlapping High) Polarity for Timer B + 26 + 1 + + + NOLLPOL_B + PWM Phase A-Prime (Non-Overlapping Low) Polarity for Timer B + 27 + 1 + + + PWMCKBD_B + PWM Phase A-Prime Output Disable for Timer B + 28 + 1 + + + RST_B + Resets all flip flops in the CLK_TMR domain for Timer B. Self-clears. + 29 + 1 + + + CLKEN_B + Write 1 to Enable CLK_TMR for Timer B + 30 + 1 + + + EN_B + Enable for Timer B + 31 + 1 + + + + + NOLCMP + Timer Non-Overlapping Compare Register. + 0x14 + read-write + + + LO_A + Non-Overlapping Low Compare value for Timer A controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime. + 0 + 8 + + + HI_A + Non-Overlapping High Compare value for Timer A controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A. + 8 + 8 + + + LO_B + Non-Overlapping Low Compare value for Timer B controls the time between the falling edge of PWM Phase A and the next rising edge of PWM Phase A-Prime. + 16 + 8 + + + HI_B + Non-Overlapping High Compare value for Timer B controls the time between the falling edge of PWM Phase A-Prime and the next rising edge of PWM Phase A. + 24 + 8 + + + + + CTRL1 + Timer Configuration Register. + 0x18 + read-write + + + CLKSEL_A + Timer Clock Select for Timer A + 0 + 2 + + + CLKEN_A + Timer A Enable Status + 2 + 1 + + + CLKRDY_A + CLK_TMR Ready Flag for Timer A + 3 + 1 + + + EVENT_SEL_A + Event Select for Timer A + 4 + 3 + + + NEGTRIG_A + Negative Edge Trigger for Event for Timer A + 7 + 1 + + + IE_A + Interrupt Enable for Timer A + 8 + 1 + + + CAPEVENT_SEL_A + Capture Event Select for Timer A + 9 + 2 + + + SW_CAPEVENT_A + Software Capture Event for Timer A + 11 + 1 + + + WE_A + Wake-Up Enable for Timer A + 12 + 1 + + + OUTEN_A + OUT_OE_O Enable for Modes 0, 1,and 5 for Timer A + 13 + 1 + + + OUTBEN_A + PWM_CKB_EN_O Enable for Modes other than Mode 3 for Timer A + 14 + 1 + + + CLKSEL_B + Timer Clock Select for Timer B + 16 + 2 + + + CLKEN_B + Timer B Enable Status + 18 + 1 + + + CLKRDY_B + CLK_TMR Ready Flag for Timer B + 19 + 1 + + + EVENT_SEL_B + Event Select for Timer B + 20 + 3 + + + NEGTRIG_B + Negative Edge Trigger for Event for Timer B + 23 + 1 + + + IE_B + Interrupt Enable for Timer B + 24 + 1 + + + CAPEVENT_SEL_B + Capture Event Select for Timer B + 25 + 2 + + + SW_CAPEVENT_B + Software Capture Event for Timer B + 27 + 1 + + + WE_B + Wake-Up Enable for Timer B + 28 + 1 + + + CASCADE + Cascade two 16-bit timers into one 32-bit timer. Only available when C_TMR16=0 adn C_DUALTMR16=1. + 31 + 1 + + + + + WKFL + Timer Wakeup Status Register. + 0x1C + read-write + + + A + Wake-Up Flag for Timer A + 0 + 1 + + + B + Wake-Up Flag for Timer B + 16 + 1 + + + + + + + From 64f15d3d510c3ff5841ef6e215289751216f821e Mon Sep 17 00:00:00 2001 From: Woo Date: Mon, 29 Apr 2024 14:31:03 -0500 Subject: [PATCH 09/93] Fix copyright names and add SPC --- .../Device/Maxim/MAX32657/Include/aes_regs.h | 1 - .../Maxim/MAX32657/Include/aeskeys_regs.h | 1 - .../Device/Maxim/MAX32657/Include/crc_regs.h | 1 - .../Device/Maxim/MAX32657/Include/dma_regs.h | 1 - .../Device/Maxim/MAX32657/Include/fcr_regs.h | 1 - .../Device/Maxim/MAX32657/Include/flc_regs.h | 1 - .../Device/Maxim/MAX32657/Include/gcr_regs.h | 1 - .../Device/Maxim/MAX32657/Include/gpio_regs.h | 1 - .../Device/Maxim/MAX32657/Include/i2c_regs.h | 1 - .../Device/Maxim/MAX32657/Include/icc_regs.h | 1 - .../Maxim/MAX32657/Include/max32657.svd | 290 ++++++++++++++++ .../Device/Maxim/MAX32657/Include/mcr_regs.h | 1 - .../Maxim/MAX32657/Include/pwrseq_regs.h | 1 - .../Device/Maxim/MAX32657/Include/rtc_regs.h | 1 - .../Device/Maxim/MAX32657/Include/sema_regs.h | 1 - .../Device/Maxim/MAX32657/Include/simo_regs.h | 1 - .../Device/Maxim/MAX32657/Include/sir_regs.h | 1 - .../Device/Maxim/MAX32657/Include/spc_regs.h | 313 ++++++++++++++++++ .../Device/Maxim/MAX32657/Include/spi_regs.h | 1 - .../Device/Maxim/MAX32657/Include/tmr_regs.h | 4 +- .../Maxim/MAX32657/Include/trimsir_regs.h | 1 - .../Device/Maxim/MAX32657/Include/trng_regs.h | 1 - .../Device/Maxim/MAX32657/Include/uart_regs.h | 1 - .../Device/Maxim/MAX32657/Include/wdt_regs.h | 1 - .../Device/Maxim/MAX32657/Include/wut_regs.h | 1 - .../PeriphDrivers/Source/SPC/spc_reva.svd | 293 ++++++++++++++++ 26 files changed, 897 insertions(+), 25 deletions(-) create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/spc_regs.h create mode 100644 Libraries/PeriphDrivers/Source/SPC/spc_reva.svd diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/aes_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/aes_regs.h index a962a06aa33..d76e19f69ad 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/aes_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/aes_regs.h @@ -7,7 +7,6 @@ /****************************************************************************** * - * Analog Devices, Inc.), * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/aeskeys_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/aeskeys_regs.h index b6aad12ae7f..3e030d4cceb 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/aeskeys_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/aeskeys_regs.h @@ -7,7 +7,6 @@ /****************************************************************************** * - * Analog Devices, Inc.), * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/crc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/crc_regs.h index ccc0b8580ec..fe26a3df145 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/crc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/crc_regs.h @@ -7,7 +7,6 @@ /****************************************************************************** * - * Analog Devices, Inc.), * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/dma_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/dma_regs.h index 5b0da7826bd..ed564122112 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/dma_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/dma_regs.h @@ -7,7 +7,6 @@ /****************************************************************************** * - * Analog Devices, Inc.), * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h index 4056241705b..53dd1268f50 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h @@ -7,7 +7,6 @@ /****************************************************************************** * - * Analog Devices, Inc.), * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/flc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/flc_regs.h index 8d836a20ebb..0027d3c335b 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/flc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/flc_regs.h @@ -7,7 +7,6 @@ /****************************************************************************** * - * Analog Devices, Inc.), * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h index c97e6f8a1ff..16a0777d191 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h @@ -7,7 +7,6 @@ /****************************************************************************** * - * Analog Devices, Inc.), * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gpio_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gpio_regs.h index ef90a433d21..3b9ad89a961 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gpio_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gpio_regs.h @@ -7,7 +7,6 @@ /****************************************************************************** * - * Analog Devices, Inc.), * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/i2c_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/i2c_regs.h index f7ffa96e1d0..f45b5c18180 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/i2c_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/i2c_regs.h @@ -7,7 +7,6 @@ /****************************************************************************** * - * Analog Devices, Inc.), * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/icc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/icc_regs.h index f0a8875caa5..566417e782f 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/icc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/icc_regs.h @@ -7,7 +7,6 @@ /****************************************************************************** * - * Analog Devices, Inc.), * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd index 5d65d8caf66..b1c96806256 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd @@ -10957,6 +10957,296 @@ + + SPC + Secure Privilege Controller. + 0x50090000 + + 0x00 + 0x1000 + registers + + + + CTRL + SPC Secure Configuration Control Register. + 0x0000 + 32 + + + LOCK + Write 1 to set, disables writes to security-related control registers in the SPC. Once set, the locked registers cannot be modified nor can this bit be cleared to 0 except through a reset. + 0 + 1 + + + + + RESP + Security Violation Response Configuration Register. + 0x0008 + 32 + + + VIOLCFG + This field configures the target response in case of a secuirty violation. + 0 + 1 + + + + + MPC_STATUS + Secure MPC Status Register. + 0x0020 + 8 + read-only + + + SRAM0 + Interrupt status for SRAM 0 Memory Protection Controller. + 0 + 1 + + + SRAM1 + Interrupt status for SRAM1 Memory Protection Controllers. + 1 + 1 + + + SRAM2 + Interrupt status for SRAM2 Memory Protection Controllers. + 2 + 1 + + + SRAM3 + Interrupt status for SRAM3 Memory Protection Controllers. + 3 + 1 + + + SRAM4 + Interrupt status for SRAM4 Memory Protection Controllers. + 4 + 1 + + + FLASH + Interrupt status for Flash Memory Protection Controllers. + 5 + 1 + + + + + MPC_INTEN + Secure MPC Interrupt Enable Register. + 0x0024 + + + SRAM0 + Interrupt enable for SRAM 0 Memory Protection Controller. + 0 + 1 + + + SRAM1 + Interrupt enable for SRAM1 Memory Protection Controllers. + 1 + 1 + + + SRAM2 + Interrupt enable for SRAM2 Memory Protection Controllers. + 2 + 1 + + + SRAM3 + Interrupt enable for SRAM3 Memory Protection Controllers. + 3 + 1 + + + SRAM4 + Interrupt enable for SRAM4 Memory Protection Controllers. + 4 + 1 + + + FLASH + Interrupt enable for Flash Memory Protection Controllers. + 5 + 1 + + + + + PPC_STATUS + Secure PPC Interrupt Status Register. + 0x0030 + read-only + + + APBPPC + Interrupt Status of APB PPC for targets on APB bus. Each bit ties to an individual PPC in the system. + 0 + 2 + + + + + PPC_INTCLR + Secure PPC Interrupt Clear Register. + 0x0034 + write-only + + + APBPPC + Interrupt Clear of APB PPC for targets on the APB bus. Each bit ties to an individual PPC in the system. + 0 + 2 + + + + + PPC_INTEN + Secure PPC Interrupt Enable Register. + 0x0038 + + + APBPPC + Interrupt Enable for APB PPC for targets on the APB bus. Each bit ties to an individual PPC in the system. + 0 + 2 + + + + + NSCIDAU + Non-Secure Callabale IDAU Configuration Register. + 0x0080 + + + CODE + Configures whether the CODE region is Non-secure Callable. + 0 + 1 + + + SRAM + Configures whether the RAM region is Non-secure Callable. + 1 + 1 + + + + + M33LOCK + M33 Core Register Lock Configuratrion Register. + 0x0090 + + + AIRCR_VTOR_S + Lock VTOR_S, AIRCR.PRIS, and AIRCR.BFHFNMINS. + 0 + 1 + + + VTOR_NS + Lock VTOR_NS register. + 1 + 1 + + + MPU_S + Lock secure MPU registers. + 2 + 1 + + + MPU_NS + Lock non-secure MPU registers. + 3 + 1 + + + SAU + Lock Security Attribution Unit (SAU). + 4 + 1 + + + DIS + TX DMA requests are disabled, andy pending DMA requests are cleared. + 0 + + + en + TX DMA requests are enabled. + 1 + + + + + + + APBSEC + APB Target Secure/Non-secure PPC Access Register. + 0x0120 + + + PERIPH + Each bit configures the APB PPC to enforce the security access allowed for an individual peripheral. + 0 + 32 + + + + + APBPRIV + APB Tartet Privileged/Non-privileged PPC Access Register. + 0x0160 + + + PERIPH + Each bit configures the APB PPC to enforce the security access allowed for an individual peripheral. + 0 + 32 + + + + + GPIO0 + Secure GPIO0 Configuration Register. + 0x0180 + + + PINS + Each bit configures a GPIO pin as secore or non-secure on GPIO Port 0. Secure GPIO pins prevent software from reading GPIO Data In pin states. + 0 + 12 + + + + + GPIO1 + Secure GPIO1 Configuration Register. + 0x0184 + + + PINS + Each bit configures a GPIO pin as secore or non-secure on GPIO Port 0. Secure GPIO pins prevent software from reading GPIO Data In pin states. + 0 + 2 + + + + + + SPI SPI peripheral. diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mcr_regs.h index 940b3a29cc9..30a97da0147 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mcr_regs.h @@ -7,7 +7,6 @@ /****************************************************************************** * - * Analog Devices, Inc.), * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/pwrseq_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/pwrseq_regs.h index dde66e8e51f..77b5a1a141d 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/pwrseq_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/pwrseq_regs.h @@ -7,7 +7,6 @@ /****************************************************************************** * - * Analog Devices, Inc.), * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/rtc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/rtc_regs.h index 25aa4e768f7..f54cf7b4c25 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/rtc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/rtc_regs.h @@ -7,7 +7,6 @@ /****************************************************************************** * - * Analog Devices, Inc.), * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sema_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sema_regs.h index 7f287a2aa3e..e9b763a0c1e 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sema_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sema_regs.h @@ -7,7 +7,6 @@ /****************************************************************************** * - * Analog Devices, Inc.), * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/simo_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/simo_regs.h index b074a335739..d6cfc8ccd04 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/simo_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/simo_regs.h @@ -7,7 +7,6 @@ /****************************************************************************** * - * Analog Devices, Inc.), * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sir_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sir_regs.h index 2ac0507b884..7b9be1b01bb 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sir_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sir_regs.h @@ -7,7 +7,6 @@ /****************************************************************************** * - * Analog Devices, Inc.), * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spc_regs.h new file mode 100644 index 00000000000..0ad6d991de8 --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spc_regs.h @@ -0,0 +1,313 @@ +/** + * @file spc_regs.h + * @brief Registers, Bit Masks and Bit Positions for the SPC Peripheral Module. + * @note This file is @generated. + * @ingroup spc_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_SPC_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_SPC_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup spc + * @defgroup spc_registers SPC_Registers + * @brief Registers, Bit Masks and Bit Positions for the SPC Peripheral Module. + * @details Secure Privilege Controller. + */ + +/** + * @ingroup spc_registers + * Structure type to access the SPC Registers. + */ +typedef struct { + __IO uint32_t ctrl; /**< \b 0x0000: SPC CTRL Register */ + __R uint32_t rsv_0x4; + __IO uint32_t resp; /**< \b 0x0008: SPC RESP Register */ + __R uint32_t rsv_0xc_0x1f[5]; + __I uint8_t mpc_status; /**< \b 0x0020: SPC MPC_STATUS Register */ + __R uint8_t rsv_0x21_0x23[3]; + __IO uint32_t mpc_inten; /**< \b 0x0024: SPC MPC_INTEN Register */ + __R uint32_t rsv_0x28_0x2f[2]; + __I uint32_t ppc_status; /**< \b 0x0030: SPC PPC_STATUS Register */ + __O uint32_t ppc_intclr; /**< \b 0x0034: SPC PPC_INTCLR Register */ + __IO uint32_t ppc_inten; /**< \b 0x0038: SPC PPC_INTEN Register */ + __R uint32_t rsv_0x3c_0x7f[17]; + __IO uint32_t nscidau; /**< \b 0x0080: SPC NSCIDAU Register */ + __R uint32_t rsv_0x84_0x8f[3]; + __IO uint32_t m33lock; /**< \b 0x0090: SPC M33LOCK Register */ + __R uint32_t rsv_0x94_0x11f[35]; + __IO uint32_t apbsec; /**< \b 0x0120: SPC APBSEC Register */ + __R uint32_t rsv_0x124_0x15f[15]; + __IO uint32_t apbpriv; /**< \b 0x0160: SPC APBPRIV Register */ + __R uint32_t rsv_0x164_0x17f[7]; + __IO uint32_t gpio0; /**< \b 0x0180: SPC GPIO0 Register */ + __IO uint32_t gpio1; /**< \b 0x0184: SPC GPIO1 Register */ +} mxc_spc_regs_t; + +/* Register offsets for module SPC */ +/** + * @ingroup spc_registers + * @defgroup SPC_Register_Offsets Register Offsets + * @brief SPC Peripheral Register Offsets from the SPC Base Peripheral Address. + * @{ + */ +#define MXC_R_SPC_CTRL ((uint32_t)0x00000000UL) /**< Offset from SPC Base Address: 0x0000 */ +#define MXC_R_SPC_RESP ((uint32_t)0x00000008UL) /**< Offset from SPC Base Address: 0x0008 */ +#define MXC_R_SPC_MPC_STATUS ((uint32_t)0x00000020UL) /**< Offset from SPC Base Address: 0x0020 */ +#define MXC_R_SPC_MPC_INTEN ((uint32_t)0x00000024UL) /**< Offset from SPC Base Address: 0x0024 */ +#define MXC_R_SPC_PPC_STATUS ((uint32_t)0x00000030UL) /**< Offset from SPC Base Address: 0x0030 */ +#define MXC_R_SPC_PPC_INTCLR ((uint32_t)0x00000034UL) /**< Offset from SPC Base Address: 0x0034 */ +#define MXC_R_SPC_PPC_INTEN ((uint32_t)0x00000038UL) /**< Offset from SPC Base Address: 0x0038 */ +#define MXC_R_SPC_NSCIDAU ((uint32_t)0x00000080UL) /**< Offset from SPC Base Address: 0x0080 */ +#define MXC_R_SPC_M33LOCK ((uint32_t)0x00000090UL) /**< Offset from SPC Base Address: 0x0090 */ +#define MXC_R_SPC_APBSEC ((uint32_t)0x00000120UL) /**< Offset from SPC Base Address: 0x0120 */ +#define MXC_R_SPC_APBPRIV ((uint32_t)0x00000160UL) /**< Offset from SPC Base Address: 0x0160 */ +#define MXC_R_SPC_GPIO0 ((uint32_t)0x00000180UL) /**< Offset from SPC Base Address: 0x0180 */ +#define MXC_R_SPC_GPIO1 ((uint32_t)0x00000184UL) /**< Offset from SPC Base Address: 0x0184 */ +/**@} end of group spc_registers */ + +/** + * @ingroup spc_registers + * @defgroup SPC_CTRL SPC_CTRL + * @brief SPC Secure Configuration Control Register. + * @{ + */ +#define MXC_F_SPC_CTRL_LOCK_POS 0 /**< CTRL_LOCK Position */ +#define MXC_F_SPC_CTRL_LOCK ((uint32_t)(0x1UL << MXC_F_SPC_CTRL_LOCK_POS)) /**< CTRL_LOCK Mask */ + +/**@} end of group SPC_CTRL_Register */ + +/** + * @ingroup spc_registers + * @defgroup SPC_RESP SPC_RESP + * @brief Security Violation Response Configuration Register. + * @{ + */ +#define MXC_F_SPC_RESP_VIOLCFG_POS 0 /**< RESP_VIOLCFG Position */ +#define MXC_F_SPC_RESP_VIOLCFG ((uint32_t)(0x1UL << MXC_F_SPC_RESP_VIOLCFG_POS)) /**< RESP_VIOLCFG Mask */ + +/**@} end of group SPC_RESP_Register */ + +/** + * @ingroup spc_registers + * @defgroup SPC_MPC_STATUS SPC_MPC_STATUS + * @brief Secure MPC Status Register. + * @{ + */ +#define MXC_F_SPC_MPC_STATUS_SRAM0_POS 0 /**< MPC_STATUS_SRAM0 Position */ +#define MXC_F_SPC_MPC_STATUS_SRAM0 ((uint8_t)(0x1UL << MXC_F_SPC_MPC_STATUS_SRAM0_POS)) /**< MPC_STATUS_SRAM0 Mask */ + +#define MXC_F_SPC_MPC_STATUS_SRAM1_POS 1 /**< MPC_STATUS_SRAM1 Position */ +#define MXC_F_SPC_MPC_STATUS_SRAM1 ((uint8_t)(0x1UL << MXC_F_SPC_MPC_STATUS_SRAM1_POS)) /**< MPC_STATUS_SRAM1 Mask */ + +#define MXC_F_SPC_MPC_STATUS_SRAM2_POS 2 /**< MPC_STATUS_SRAM2 Position */ +#define MXC_F_SPC_MPC_STATUS_SRAM2 ((uint8_t)(0x1UL << MXC_F_SPC_MPC_STATUS_SRAM2_POS)) /**< MPC_STATUS_SRAM2 Mask */ + +#define MXC_F_SPC_MPC_STATUS_SRAM3_POS 3 /**< MPC_STATUS_SRAM3 Position */ +#define MXC_F_SPC_MPC_STATUS_SRAM3 ((uint8_t)(0x1UL << MXC_F_SPC_MPC_STATUS_SRAM3_POS)) /**< MPC_STATUS_SRAM3 Mask */ + +#define MXC_F_SPC_MPC_STATUS_SRAM4_POS 4 /**< MPC_STATUS_SRAM4 Position */ +#define MXC_F_SPC_MPC_STATUS_SRAM4 ((uint8_t)(0x1UL << MXC_F_SPC_MPC_STATUS_SRAM4_POS)) /**< MPC_STATUS_SRAM4 Mask */ + +#define MXC_F_SPC_MPC_STATUS_FLASH_POS 5 /**< MPC_STATUS_FLASH Position */ +#define MXC_F_SPC_MPC_STATUS_FLASH ((uint8_t)(0x1UL << MXC_F_SPC_MPC_STATUS_FLASH_POS)) /**< MPC_STATUS_FLASH Mask */ + +/**@} end of group SPC_MPC_STATUS_Register */ + +/** + * @ingroup spc_registers + * @defgroup SPC_MPC_INTEN SPC_MPC_INTEN + * @brief Secure MPC Interrupt Enable Register. + * @{ + */ +#define MXC_F_SPC_MPC_INTEN_SRAM0_POS 0 /**< MPC_INTEN_SRAM0 Position */ +#define MXC_F_SPC_MPC_INTEN_SRAM0 ((uint32_t)(0x1UL << MXC_F_SPC_MPC_INTEN_SRAM0_POS)) /**< MPC_INTEN_SRAM0 Mask */ + +#define MXC_F_SPC_MPC_INTEN_SRAM1_POS 1 /**< MPC_INTEN_SRAM1 Position */ +#define MXC_F_SPC_MPC_INTEN_SRAM1 ((uint32_t)(0x1UL << MXC_F_SPC_MPC_INTEN_SRAM1_POS)) /**< MPC_INTEN_SRAM1 Mask */ + +#define MXC_F_SPC_MPC_INTEN_SRAM2_POS 2 /**< MPC_INTEN_SRAM2 Position */ +#define MXC_F_SPC_MPC_INTEN_SRAM2 ((uint32_t)(0x1UL << MXC_F_SPC_MPC_INTEN_SRAM2_POS)) /**< MPC_INTEN_SRAM2 Mask */ + +#define MXC_F_SPC_MPC_INTEN_SRAM3_POS 3 /**< MPC_INTEN_SRAM3 Position */ +#define MXC_F_SPC_MPC_INTEN_SRAM3 ((uint32_t)(0x1UL << MXC_F_SPC_MPC_INTEN_SRAM3_POS)) /**< MPC_INTEN_SRAM3 Mask */ + +#define MXC_F_SPC_MPC_INTEN_SRAM4_POS 4 /**< MPC_INTEN_SRAM4 Position */ +#define MXC_F_SPC_MPC_INTEN_SRAM4 ((uint32_t)(0x1UL << MXC_F_SPC_MPC_INTEN_SRAM4_POS)) /**< MPC_INTEN_SRAM4 Mask */ + +#define MXC_F_SPC_MPC_INTEN_FLASH_POS 5 /**< MPC_INTEN_FLASH Position */ +#define MXC_F_SPC_MPC_INTEN_FLASH ((uint32_t)(0x1UL << MXC_F_SPC_MPC_INTEN_FLASH_POS)) /**< MPC_INTEN_FLASH Mask */ + +/**@} end of group SPC_MPC_INTEN_Register */ + +/** + * @ingroup spc_registers + * @defgroup SPC_PPC_STATUS SPC_PPC_STATUS + * @brief Secure PPC Interrupt Status Register. + * @{ + */ +#define MXC_F_SPC_PPC_STATUS_APBPPC_POS 0 /**< PPC_STATUS_APBPPC Position */ +#define MXC_F_SPC_PPC_STATUS_APBPPC ((uint32_t)(0x3UL << MXC_F_SPC_PPC_STATUS_APBPPC_POS)) /**< PPC_STATUS_APBPPC Mask */ + +/**@} end of group SPC_PPC_STATUS_Register */ + +/** + * @ingroup spc_registers + * @defgroup SPC_PPC_INTCLR SPC_PPC_INTCLR + * @brief Secure PPC Interrupt Clear Register. + * @{ + */ +#define MXC_F_SPC_PPC_INTCLR_APBPPC_POS 0 /**< PPC_INTCLR_APBPPC Position */ +#define MXC_F_SPC_PPC_INTCLR_APBPPC ((uint32_t)(0x3UL << MXC_F_SPC_PPC_INTCLR_APBPPC_POS)) /**< PPC_INTCLR_APBPPC Mask */ + +/**@} end of group SPC_PPC_INTCLR_Register */ + +/** + * @ingroup spc_registers + * @defgroup SPC_PPC_INTEN SPC_PPC_INTEN + * @brief Secure PPC Interrupt Enable Register. + * @{ + */ +#define MXC_F_SPC_PPC_INTEN_APBPPC_POS 0 /**< PPC_INTEN_APBPPC Position */ +#define MXC_F_SPC_PPC_INTEN_APBPPC ((uint32_t)(0x3UL << MXC_F_SPC_PPC_INTEN_APBPPC_POS)) /**< PPC_INTEN_APBPPC Mask */ + +/**@} end of group SPC_PPC_INTEN_Register */ + +/** + * @ingroup spc_registers + * @defgroup SPC_NSCIDAU SPC_NSCIDAU + * @brief Non-Secure Callabale IDAU Configuration Register. + * @{ + */ +#define MXC_F_SPC_NSCIDAU_CODE_POS 0 /**< NSCIDAU_CODE Position */ +#define MXC_F_SPC_NSCIDAU_CODE ((uint32_t)(0x1UL << MXC_F_SPC_NSCIDAU_CODE_POS)) /**< NSCIDAU_CODE Mask */ + +#define MXC_F_SPC_NSCIDAU_SRAM_POS 1 /**< NSCIDAU_SRAM Position */ +#define MXC_F_SPC_NSCIDAU_SRAM ((uint32_t)(0x1UL << MXC_F_SPC_NSCIDAU_SRAM_POS)) /**< NSCIDAU_SRAM Mask */ + +/**@} end of group SPC_NSCIDAU_Register */ + +/** + * @ingroup spc_registers + * @defgroup SPC_M33LOCK SPC_M33LOCK + * @brief M33 Core Register Lock Configuratrion Register. + * @{ + */ +#define MXC_F_SPC_M33LOCK_AIRCR_VTOR_S_POS 0 /**< M33LOCK_AIRCR_VTOR_S Position */ +#define MXC_F_SPC_M33LOCK_AIRCR_VTOR_S ((uint32_t)(0x1UL << MXC_F_SPC_M33LOCK_AIRCR_VTOR_S_POS)) /**< M33LOCK_AIRCR_VTOR_S Mask */ + +#define MXC_F_SPC_M33LOCK_VTOR_NS_POS 1 /**< M33LOCK_VTOR_NS Position */ +#define MXC_F_SPC_M33LOCK_VTOR_NS ((uint32_t)(0x1UL << MXC_F_SPC_M33LOCK_VTOR_NS_POS)) /**< M33LOCK_VTOR_NS Mask */ + +#define MXC_F_SPC_M33LOCK_MPU_S_POS 2 /**< M33LOCK_MPU_S Position */ +#define MXC_F_SPC_M33LOCK_MPU_S ((uint32_t)(0x1UL << MXC_F_SPC_M33LOCK_MPU_S_POS)) /**< M33LOCK_MPU_S Mask */ + +#define MXC_F_SPC_M33LOCK_MPU_NS_POS 3 /**< M33LOCK_MPU_NS Position */ +#define MXC_F_SPC_M33LOCK_MPU_NS ((uint32_t)(0x1UL << MXC_F_SPC_M33LOCK_MPU_NS_POS)) /**< M33LOCK_MPU_NS Mask */ + +#define MXC_F_SPC_M33LOCK_SAU_POS 4 /**< M33LOCK_SAU Position */ +#define MXC_F_SPC_M33LOCK_SAU ((uint32_t)(0x1UL << MXC_F_SPC_M33LOCK_SAU_POS)) /**< M33LOCK_SAU Mask */ + +/**@} end of group SPC_M33LOCK_Register */ + +/** + * @ingroup spc_registers + * @defgroup SPC_APBSEC SPC_APBSEC + * @brief APB Target Secure/Non-secure PPC Access Register. + * @{ + */ +#define MXC_F_SPC_APBSEC_PERIPH_POS 0 /**< APBSEC_PERIPH Position */ +#define MXC_F_SPC_APBSEC_PERIPH ((uint32_t)(0xFFFFFFFFUL << MXC_F_SPC_APBSEC_PERIPH_POS)) /**< APBSEC_PERIPH Mask */ + +/**@} end of group SPC_APBSEC_Register */ + +/** + * @ingroup spc_registers + * @defgroup SPC_APBPRIV SPC_APBPRIV + * @brief APB Tartet Privileged/Non-privileged PPC Access Register. + * @{ + */ +#define MXC_F_SPC_APBPRIV_PERIPH_POS 0 /**< APBPRIV_PERIPH Position */ +#define MXC_F_SPC_APBPRIV_PERIPH ((uint32_t)(0xFFFFFFFFUL << MXC_F_SPC_APBPRIV_PERIPH_POS)) /**< APBPRIV_PERIPH Mask */ + +/**@} end of group SPC_APBPRIV_Register */ + +/** + * @ingroup spc_registers + * @defgroup SPC_GPIO0 SPC_GPIO0 + * @brief Secure GPIO0 Configuration Register. + * @{ + */ +#define MXC_F_SPC_GPIO0_PINS_POS 0 /**< GPIO0_PINS Position */ +#define MXC_F_SPC_GPIO0_PINS ((uint32_t)(0xFFFUL << MXC_F_SPC_GPIO0_PINS_POS)) /**< GPIO0_PINS Mask */ + +/**@} end of group SPC_GPIO0_Register */ + +/** + * @ingroup spc_registers + * @defgroup SPC_GPIO1 SPC_GPIO1 + * @brief Secure GPIO1 Configuration Register. + * @{ + */ +#define MXC_F_SPC_GPIO1_PINS_POS 0 /**< GPIO1_PINS Position */ +#define MXC_F_SPC_GPIO1_PINS ((uint32_t)(0x3UL << MXC_F_SPC_GPIO1_PINS_POS)) /**< GPIO1_PINS Mask */ + +/**@} end of group SPC_GPIO1_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_SPC_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spi_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spi_regs.h index 9b102e01b95..4935a745e1c 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spi_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spi_regs.h @@ -7,7 +7,6 @@ /****************************************************************************** * - * Analog Devices, Inc.), * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/tmr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/tmr_regs.h index 57f0be3dfcb..61b8e57c73e 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/tmr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/tmr_regs.h @@ -7,9 +7,7 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trimsir_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trimsir_regs.h index e2e0d459f58..701e00c7bae 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trimsir_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trimsir_regs.h @@ -7,7 +7,6 @@ /****************************************************************************** * - * Analog Devices, Inc.), * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trng_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trng_regs.h index dd27efe9605..362dd3551ef 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trng_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/trng_regs.h @@ -7,7 +7,6 @@ /****************************************************************************** * - * Analog Devices, Inc.), * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/uart_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/uart_regs.h index ac3b2350dfa..e2506102de8 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/uart_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/uart_regs.h @@ -7,7 +7,6 @@ /****************************************************************************** * - * Analog Devices, Inc.), * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/wdt_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/wdt_regs.h index 78193302071..1e62996109f 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/wdt_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/wdt_regs.h @@ -7,7 +7,6 @@ /****************************************************************************** * - * Analog Devices, Inc.), * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/wut_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/wut_regs.h index a3aef1ef3c2..6f7a078ee0f 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/wut_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/wut_regs.h @@ -7,7 +7,6 @@ /****************************************************************************** * - * Analog Devices, Inc.), * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/Libraries/PeriphDrivers/Source/SPC/spc_reva.svd b/Libraries/PeriphDrivers/Source/SPC/spc_reva.svd new file mode 100644 index 00000000000..a290bd93dca --- /dev/null +++ b/Libraries/PeriphDrivers/Source/SPC/spc_reva.svd @@ -0,0 +1,293 @@ + + + + SPC + Secure Privilege Controller. + 0x50090000 + + 0x00 + 0x1000 + registers + + + + CTRL + SPC Secure Configuration Control Register. + 0x0000 + 32 + + + LOCK + Write 1 to set, disables writes to security-related control registers in the SPC. Once set, the locked registers cannot be modified nor can this bit be cleared to 0 except through a reset. + 0 + 1 + + + + + RESP + Security Violation Response Configuration Register. + 0x0008 + 32 + + + VIOLCFG + This field configures the target response in case of a secuirty violation. + 0 + 1 + + + + + MPC_STATUS + Secure MPC Status Register. + 0x0020 + 8 + read-only + + + SRAM0 + Interrupt status for SRAM 0 Memory Protection Controller. + 0 + 1 + + + SRAM1 + Interrupt status for SRAM1 Memory Protection Controllers. + 1 + 1 + + + SRAM2 + Interrupt status for SRAM2 Memory Protection Controllers. + 2 + 1 + + + SRAM3 + Interrupt status for SRAM3 Memory Protection Controllers. + 3 + 1 + + + SRAM4 + Interrupt status for SRAM4 Memory Protection Controllers. + 4 + 1 + + + FLASH + Interrupt status for Flash Memory Protection Controllers. + 5 + 1 + + + + + MPC_INTEN + Secure MPC Interrupt Enable Register. + 0x0024 + + + SRAM0 + Interrupt enable for SRAM 0 Memory Protection Controller. + 0 + 1 + + + SRAM1 + Interrupt enable for SRAM1 Memory Protection Controllers. + 1 + 1 + + + SRAM2 + Interrupt enable for SRAM2 Memory Protection Controllers. + 2 + 1 + + + SRAM3 + Interrupt enable for SRAM3 Memory Protection Controllers. + 3 + 1 + + + SRAM4 + Interrupt enable for SRAM4 Memory Protection Controllers. + 4 + 1 + + + FLASH + Interrupt enable for Flash Memory Protection Controllers. + 5 + 1 + + + + + PPC_STATUS + Secure PPC Interrupt Status Register. + 0x0030 + read-only + + + APBPPC + Interrupt Status of APB PPC for targets on APB bus. Each bit ties to an individual PPC in the system. + 0 + 2 + + + + + PPC_INTCLR + Secure PPC Interrupt Clear Register. + 0x0034 + write-only + + + APBPPC + Interrupt Clear of APB PPC for targets on the APB bus. Each bit ties to an individual PPC in the system. + 0 + 2 + + + + + PPC_INTEN + Secure PPC Interrupt Enable Register. + 0x0038 + + + APBPPC + Interrupt Enable for APB PPC for targets on the APB bus. Each bit ties to an individual PPC in the system. + 0 + 2 + + + + + NSCIDAU + Non-Secure Callabale IDAU Configuration Register. + 0x0080 + + + CODE + Configures whether the CODE region is Non-secure Callable. + 0 + 1 + + + SRAM + Configures whether the RAM region is Non-secure Callable. + 1 + 1 + + + + + M33LOCK + M33 Core Register Lock Configuratrion Register. + 0x0090 + + + AIRCR_VTOR_S + Lock VTOR_S, AIRCR.PRIS, and AIRCR.BFHFNMINS. + 0 + 1 + + + VTOR_NS + Lock VTOR_NS register. + 1 + 1 + + + MPU_S + Lock secure MPU registers. + 2 + 1 + + + MPU_NS + Lock non-secure MPU registers. + 3 + 1 + + + SAU + Lock Security Attribution Unit (SAU). + 4 + 1 + + + DIS + TX DMA requests are disabled, andy pending DMA requests are cleared. + 0 + + + en + TX DMA requests are enabled. + 1 + + + + + + + APBSEC + APB Target Secure/Non-secure PPC Access Register. + 0x0120 + + + PERIPH + Each bit configures the APB PPC to enforce the security access allowed for an individual peripheral. + 0 + 32 + + + + + APBPRIV + APB Tartet Privileged/Non-privileged PPC Access Register. + 0x0160 + + + PERIPH + Each bit configures the APB PPC to enforce the security access allowed for an individual peripheral. + 0 + 32 + + + + + GPIO0 + Secure GPIO0 Configuration Register. + 0x0180 + + + PINS + Each bit configures a GPIO pin as secore or non-secure on GPIO Port 0. Secure GPIO pins prevent software from reading GPIO Data In pin states. + 0 + 12 + + + + + GPIO1 + Secure GPIO1 Configuration Register. + 0x0184 + + + PINS + Each bit configures a GPIO pin as secore or non-secure on GPIO Port 0. Secure GPIO pins prevent software from reading GPIO Data In pin states. + 0 + 2 + + + + + + + \ No newline at end of file From 9417f4ed70b29f4c3ee15fdb2fbaf9572e9ca61f Mon Sep 17 00:00:00 2001 From: Woo Date: Mon, 29 Apr 2024 14:32:52 -0500 Subject: [PATCH 10/93] Remove unsuppored peripherals from CMSIS --- .../Device/Maxim/MAX32657/Include/adc_regs.h | 286 --------- .../Device/Maxim/MAX32657/Include/dvs_regs.h | 354 ----------- .../Device/Maxim/MAX32657/Include/gcfr_regs.h | 123 ---- .../Device/Maxim/MAX32657/Include/i2c_regs.h | 590 ------------------ .../Device/Maxim/MAX32657/Include/i2s_regs.h | 292 --------- .../Maxim/MAX32657/Include/lpcmp_regs.h | 115 ---- .../Maxim/MAX32657/Include/lpgcr_regs.h | 148 ----- .../Device/Maxim/MAX32657/Include/owm_regs.h | 229 ------- .../Device/Maxim/MAX32657/Include/pt_regs.h | 211 ------- .../Device/Maxim/MAX32657/Include/ptg_regs.h | 267 -------- 10 files changed, 2615 deletions(-) delete mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/adc_regs.h delete mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/dvs_regs.h delete mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcfr_regs.h delete mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/i2c_regs.h delete mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/i2s_regs.h delete mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/lpcmp_regs.h delete mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/lpgcr_regs.h delete mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/owm_regs.h delete mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/pt_regs.h delete mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/ptg_regs.h diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/adc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/adc_regs.h deleted file mode 100644 index 5aca6094603..00000000000 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/adc_regs.h +++ /dev/null @@ -1,286 +0,0 @@ -/** - * @file adc_regs.h - * @brief Registers, Bit Masks and Bit Positions for the ADC Peripheral Module. - * @note This file is @generated. - * @ingroup adc_registers - */ - -/****************************************************************************** - * - * Analog Devices, Inc.), - * Copyright (C) 2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ******************************************************************************/ - -#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_ADC_REGS_H_ -#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_ADC_REGS_H_ - -/* **** Includes **** */ -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined (__ICCARM__) - #pragma system_include -#endif - -#if defined (__CC_ARM) - #pragma anon_unions -#endif -/// @cond -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif -#ifndef __R -#define __R volatile const -#endif -/// @endcond - -/* **** Definitions **** */ - -/** - * @ingroup adc - * @defgroup adc_registers ADC_Registers - * @brief Registers, Bit Masks and Bit Positions for the ADC Peripheral Module. - * @details 10-bit Analog to Digital Converter - */ - -/** - * @ingroup adc_registers - * Structure type to access the ADC Registers. - */ -typedef struct { - __IO uint32_t ctrl; /**< \b 0x0000: ADC CTRL Register */ - __IO uint32_t status; /**< \b 0x0004: ADC STATUS Register */ - __IO uint32_t data; /**< \b 0x0008: ADC DATA Register */ - __IO uint32_t intr; /**< \b 0x000C: ADC INTR Register */ - __IO uint32_t limit[4]; /**< \b 0x0010: ADC LIMIT Register */ - __IO uint32_t deccnt; /**< \b 0x0020: ADC DECCNT Register */ -} mxc_adc_regs_t; - -/* Register offsets for module ADC */ -/** - * @ingroup adc_registers - * @defgroup ADC_Register_Offsets Register Offsets - * @brief ADC Peripheral Register Offsets from the ADC Base Peripheral Address. - * @{ - */ -#define MXC_R_ADC_CTRL ((uint32_t)0x00000000UL) /**< Offset from ADC Base Address: 0x0000 */ -#define MXC_R_ADC_STATUS ((uint32_t)0x00000004UL) /**< Offset from ADC Base Address: 0x0004 */ -#define MXC_R_ADC_DATA ((uint32_t)0x00000008UL) /**< Offset from ADC Base Address: 0x0008 */ -#define MXC_R_ADC_INTR ((uint32_t)0x0000000CUL) /**< Offset from ADC Base Address: 0x000C */ -#define MXC_R_ADC_LIMIT ((uint32_t)0x00000010UL) /**< Offset from ADC Base Address: 0x0010 */ -#define MXC_R_ADC_DECCNT ((uint32_t)0x00000020UL) /**< Offset from ADC Base Address: 0x0020 */ -/**@} end of group adc_registers */ - -/** - * @ingroup adc_registers - * @defgroup ADC_CTRL ADC_CTRL - * @brief ADC Control - * @{ - */ -#define MXC_F_ADC_CTRL_START_POS 0 /**< CTRL_START Position */ -#define MXC_F_ADC_CTRL_START ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_START_POS)) /**< CTRL_START Mask */ - -#define MXC_F_ADC_CTRL_PWR_POS 1 /**< CTRL_PWR Position */ -#define MXC_F_ADC_CTRL_PWR ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_PWR_POS)) /**< CTRL_PWR Mask */ - -#define MXC_F_ADC_CTRL_REBUF_PWR_POS 3 /**< CTRL_REBUF_PWR Position */ -#define MXC_F_ADC_CTRL_REBUF_PWR ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_REBUF_PWR_POS)) /**< CTRL_REBUF_PWR Mask */ - -#define MXC_F_ADC_CTRL_CHGPUMP_PWR_POS 4 /**< CTRL_CHGPUMP_PWR Position */ -#define MXC_F_ADC_CTRL_CHGPUMP_PWR ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_CHGPUMP_PWR_POS)) /**< CTRL_CHGPUMP_PWR Mask */ - -#define MXC_F_ADC_CTRL_REF_SCALE_POS 8 /**< CTRL_REF_SCALE Position */ -#define MXC_F_ADC_CTRL_REF_SCALE ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_REF_SCALE_POS)) /**< CTRL_REF_SCALE Mask */ - -#define MXC_F_ADC_CTRL_SCALE_POS 9 /**< CTRL_SCALE Position */ -#define MXC_F_ADC_CTRL_SCALE ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_SCALE_POS)) /**< CTRL_SCALE Mask */ - -#define MXC_F_ADC_CTRL_CLK_EN_POS 11 /**< CTRL_CLK_EN Position */ -#define MXC_F_ADC_CTRL_CLK_EN ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_CLK_EN_POS)) /**< CTRL_CLK_EN Mask */ - -#define MXC_F_ADC_CTRL_CH_SEL_POS 12 /**< CTRL_CH_SEL Position */ -#define MXC_F_ADC_CTRL_CH_SEL ((uint32_t)(0x1FUL << MXC_F_ADC_CTRL_CH_SEL_POS)) /**< CTRL_CH_SEL Mask */ -#define MXC_V_ADC_CTRL_CH_SEL_AIN0 ((uint32_t)0x0UL) /**< CTRL_CH_SEL_AIN0 Value */ -#define MXC_S_ADC_CTRL_CH_SEL_AIN0 (MXC_V_ADC_CTRL_CH_SEL_AIN0 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN0 Setting */ -#define MXC_V_ADC_CTRL_CH_SEL_AIN1 ((uint32_t)0x1UL) /**< CTRL_CH_SEL_AIN1 Value */ -#define MXC_S_ADC_CTRL_CH_SEL_AIN1 (MXC_V_ADC_CTRL_CH_SEL_AIN1 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN1 Setting */ -#define MXC_V_ADC_CTRL_CH_SEL_AIN2 ((uint32_t)0x2UL) /**< CTRL_CH_SEL_AIN2 Value */ -#define MXC_S_ADC_CTRL_CH_SEL_AIN2 (MXC_V_ADC_CTRL_CH_SEL_AIN2 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN2 Setting */ -#define MXC_V_ADC_CTRL_CH_SEL_AIN3 ((uint32_t)0x3UL) /**< CTRL_CH_SEL_AIN3 Value */ -#define MXC_S_ADC_CTRL_CH_SEL_AIN3 (MXC_V_ADC_CTRL_CH_SEL_AIN3 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN3 Setting */ -#define MXC_V_ADC_CTRL_CH_SEL_AIN4 ((uint32_t)0x4UL) /**< CTRL_CH_SEL_AIN4 Value */ -#define MXC_S_ADC_CTRL_CH_SEL_AIN4 (MXC_V_ADC_CTRL_CH_SEL_AIN4 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN4 Setting */ -#define MXC_V_ADC_CTRL_CH_SEL_AIN5 ((uint32_t)0x5UL) /**< CTRL_CH_SEL_AIN5 Value */ -#define MXC_S_ADC_CTRL_CH_SEL_AIN5 (MXC_V_ADC_CTRL_CH_SEL_AIN5 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN5 Setting */ -#define MXC_V_ADC_CTRL_CH_SEL_AIN6 ((uint32_t)0x6UL) /**< CTRL_CH_SEL_AIN6 Value */ -#define MXC_S_ADC_CTRL_CH_SEL_AIN6 (MXC_V_ADC_CTRL_CH_SEL_AIN6 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN6 Setting */ -#define MXC_V_ADC_CTRL_CH_SEL_AIN7 ((uint32_t)0x7UL) /**< CTRL_CH_SEL_AIN7 Value */ -#define MXC_S_ADC_CTRL_CH_SEL_AIN7 (MXC_V_ADC_CTRL_CH_SEL_AIN7 << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_AIN7 Setting */ -#define MXC_V_ADC_CTRL_CH_SEL_VCOREA ((uint32_t)0x8UL) /**< CTRL_CH_SEL_VCOREA Value */ -#define MXC_S_ADC_CTRL_CH_SEL_VCOREA (MXC_V_ADC_CTRL_CH_SEL_VCOREA << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VCOREA Setting */ -#define MXC_V_ADC_CTRL_CH_SEL_VCOREB ((uint32_t)0x9UL) /**< CTRL_CH_SEL_VCOREB Value */ -#define MXC_S_ADC_CTRL_CH_SEL_VCOREB (MXC_V_ADC_CTRL_CH_SEL_VCOREB << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VCOREB Setting */ -#define MXC_V_ADC_CTRL_CH_SEL_VRXOUT ((uint32_t)0xAUL) /**< CTRL_CH_SEL_VRXOUT Value */ -#define MXC_S_ADC_CTRL_CH_SEL_VRXOUT (MXC_V_ADC_CTRL_CH_SEL_VRXOUT << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VRXOUT Setting */ -#define MXC_V_ADC_CTRL_CH_SEL_VTXOUT ((uint32_t)0xBUL) /**< CTRL_CH_SEL_VTXOUT Value */ -#define MXC_S_ADC_CTRL_CH_SEL_VTXOUT (MXC_V_ADC_CTRL_CH_SEL_VTXOUT << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VTXOUT Setting */ -#define MXC_V_ADC_CTRL_CH_SEL_VDDA ((uint32_t)0xCUL) /**< CTRL_CH_SEL_VDDA Value */ -#define MXC_S_ADC_CTRL_CH_SEL_VDDA (MXC_V_ADC_CTRL_CH_SEL_VDDA << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VDDA Setting */ -#define MXC_V_ADC_CTRL_CH_SEL_VDDB ((uint32_t)0xDUL) /**< CTRL_CH_SEL_VDDB Value */ -#define MXC_S_ADC_CTRL_CH_SEL_VDDB (MXC_V_ADC_CTRL_CH_SEL_VDDB << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VDDB Setting */ -#define MXC_V_ADC_CTRL_CH_SEL_VDDIO ((uint32_t)0xEUL) /**< CTRL_CH_SEL_VDDIO Value */ -#define MXC_S_ADC_CTRL_CH_SEL_VDDIO (MXC_V_ADC_CTRL_CH_SEL_VDDIO << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VDDIO Setting */ -#define MXC_V_ADC_CTRL_CH_SEL_VDDIOH ((uint32_t)0xFUL) /**< CTRL_CH_SEL_VDDIOH Value */ -#define MXC_S_ADC_CTRL_CH_SEL_VDDIOH (MXC_V_ADC_CTRL_CH_SEL_VDDIOH << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VDDIOH Setting */ -#define MXC_V_ADC_CTRL_CH_SEL_VREGI ((uint32_t)0x10UL) /**< CTRL_CH_SEL_VREGI Value */ -#define MXC_S_ADC_CTRL_CH_SEL_VREGI (MXC_V_ADC_CTRL_CH_SEL_VREGI << MXC_F_ADC_CTRL_CH_SEL_POS) /**< CTRL_CH_SEL_VREGI Setting */ - -#define MXC_F_ADC_CTRL_DIVSEL_POS 17 /**< CTRL_DIVSEL Position */ -#define MXC_F_ADC_CTRL_DIVSEL ((uint32_t)(0x3UL << MXC_F_ADC_CTRL_DIVSEL_POS)) /**< CTRL_DIVSEL Mask */ -#define MXC_V_ADC_CTRL_DIVSEL_DIV1 ((uint32_t)0x0UL) /**< CTRL_DIVSEL_DIV1 Value */ -#define MXC_S_ADC_CTRL_DIVSEL_DIV1 (MXC_V_ADC_CTRL_DIVSEL_DIV1 << MXC_F_ADC_CTRL_DIVSEL_POS) /**< CTRL_DIVSEL_DIV1 Setting */ -#define MXC_V_ADC_CTRL_DIVSEL_DIV2 ((uint32_t)0x1UL) /**< CTRL_DIVSEL_DIV2 Value */ -#define MXC_S_ADC_CTRL_DIVSEL_DIV2 (MXC_V_ADC_CTRL_DIVSEL_DIV2 << MXC_F_ADC_CTRL_DIVSEL_POS) /**< CTRL_DIVSEL_DIV2 Setting */ -#define MXC_V_ADC_CTRL_DIVSEL_DIV3 ((uint32_t)0x2UL) /**< CTRL_DIVSEL_DIV3 Value */ -#define MXC_S_ADC_CTRL_DIVSEL_DIV3 (MXC_V_ADC_CTRL_DIVSEL_DIV3 << MXC_F_ADC_CTRL_DIVSEL_POS) /**< CTRL_DIVSEL_DIV3 Setting */ -#define MXC_V_ADC_CTRL_DIVSEL_DIV4 ((uint32_t)0x3UL) /**< CTRL_DIVSEL_DIV4 Value */ -#define MXC_S_ADC_CTRL_DIVSEL_DIV4 (MXC_V_ADC_CTRL_DIVSEL_DIV4 << MXC_F_ADC_CTRL_DIVSEL_POS) /**< CTRL_DIVSEL_DIV4 Setting */ - -#define MXC_F_ADC_CTRL_DATA_ALIGN_POS 20 /**< CTRL_DATA_ALIGN Position */ -#define MXC_F_ADC_CTRL_DATA_ALIGN ((uint32_t)(0x1UL << MXC_F_ADC_CTRL_DATA_ALIGN_POS)) /**< CTRL_DATA_ALIGN Mask */ - -/**@} end of group ADC_CTRL_Register */ - -/** - * @ingroup adc_registers - * @defgroup ADC_STATUS ADC_STATUS - * @brief ADC Status - * @{ - */ -#define MXC_F_ADC_STATUS_ACTIVE_POS 0 /**< STATUS_ACTIVE Position */ -#define MXC_F_ADC_STATUS_ACTIVE ((uint32_t)(0x1UL << MXC_F_ADC_STATUS_ACTIVE_POS)) /**< STATUS_ACTIVE Mask */ - -#define MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE_POS 2 /**< STATUS_AFE_PWR_UP_ACTIVE Position */ -#define MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE ((uint32_t)(0x1UL << MXC_F_ADC_STATUS_AFE_PWR_UP_ACTIVE_POS)) /**< STATUS_AFE_PWR_UP_ACTIVE Mask */ - -#define MXC_F_ADC_STATUS_OVERFLOW_POS 3 /**< STATUS_OVERFLOW Position */ -#define MXC_F_ADC_STATUS_OVERFLOW ((uint32_t)(0x1UL << MXC_F_ADC_STATUS_OVERFLOW_POS)) /**< STATUS_OVERFLOW Mask */ - -/**@} end of group ADC_STATUS_Register */ - -/** - * @ingroup adc_registers - * @defgroup ADC_DATA ADC_DATA - * @brief ADC Output Data - * @{ - */ -#define MXC_F_ADC_DATA_DATA_POS 0 /**< DATA_DATA Position */ -#define MXC_F_ADC_DATA_DATA ((uint32_t)(0xFFFFUL << MXC_F_ADC_DATA_DATA_POS)) /**< DATA_DATA Mask */ - -/**@} end of group ADC_DATA_Register */ - -/** - * @ingroup adc_registers - * @defgroup ADC_INTR ADC_INTR - * @brief ADC Interrupt Control Register - * @{ - */ -#define MXC_F_ADC_INTR_DONE_IE_POS 0 /**< INTR_DONE_IE Position */ -#define MXC_F_ADC_INTR_DONE_IE ((uint32_t)(0x1UL << MXC_F_ADC_INTR_DONE_IE_POS)) /**< INTR_DONE_IE Mask */ - -#define MXC_F_ADC_INTR_REF_READY_IE_POS 1 /**< INTR_REF_READY_IE Position */ -#define MXC_F_ADC_INTR_REF_READY_IE ((uint32_t)(0x1UL << MXC_F_ADC_INTR_REF_READY_IE_POS)) /**< INTR_REF_READY_IE Mask */ - -#define MXC_F_ADC_INTR_HI_LIMIT_IE_POS 2 /**< INTR_HI_LIMIT_IE Position */ -#define MXC_F_ADC_INTR_HI_LIMIT_IE ((uint32_t)(0x1UL << MXC_F_ADC_INTR_HI_LIMIT_IE_POS)) /**< INTR_HI_LIMIT_IE Mask */ - -#define MXC_F_ADC_INTR_LO_LIMIT_IE_POS 3 /**< INTR_LO_LIMIT_IE Position */ -#define MXC_F_ADC_INTR_LO_LIMIT_IE ((uint32_t)(0x1UL << MXC_F_ADC_INTR_LO_LIMIT_IE_POS)) /**< INTR_LO_LIMIT_IE Mask */ - -#define MXC_F_ADC_INTR_OVERFLOW_IE_POS 4 /**< INTR_OVERFLOW_IE Position */ -#define MXC_F_ADC_INTR_OVERFLOW_IE ((uint32_t)(0x1UL << MXC_F_ADC_INTR_OVERFLOW_IE_POS)) /**< INTR_OVERFLOW_IE Mask */ - -#define MXC_F_ADC_INTR_DONE_IF_POS 16 /**< INTR_DONE_IF Position */ -#define MXC_F_ADC_INTR_DONE_IF ((uint32_t)(0x1UL << MXC_F_ADC_INTR_DONE_IF_POS)) /**< INTR_DONE_IF Mask */ - -#define MXC_F_ADC_INTR_REF_READY_IF_POS 17 /**< INTR_REF_READY_IF Position */ -#define MXC_F_ADC_INTR_REF_READY_IF ((uint32_t)(0x1UL << MXC_F_ADC_INTR_REF_READY_IF_POS)) /**< INTR_REF_READY_IF Mask */ - -#define MXC_F_ADC_INTR_HI_LIMIT_IF_POS 18 /**< INTR_HI_LIMIT_IF Position */ -#define MXC_F_ADC_INTR_HI_LIMIT_IF ((uint32_t)(0x1UL << MXC_F_ADC_INTR_HI_LIMIT_IF_POS)) /**< INTR_HI_LIMIT_IF Mask */ - -#define MXC_F_ADC_INTR_LO_LIMIT_IF_POS 19 /**< INTR_LO_LIMIT_IF Position */ -#define MXC_F_ADC_INTR_LO_LIMIT_IF ((uint32_t)(0x1UL << MXC_F_ADC_INTR_LO_LIMIT_IF_POS)) /**< INTR_LO_LIMIT_IF Mask */ - -#define MXC_F_ADC_INTR_OVERFLOW_IF_POS 20 /**< INTR_OVERFLOW_IF Position */ -#define MXC_F_ADC_INTR_OVERFLOW_IF ((uint32_t)(0x1UL << MXC_F_ADC_INTR_OVERFLOW_IF_POS)) /**< INTR_OVERFLOW_IF Mask */ - -#define MXC_F_ADC_INTR_PENDING_POS 22 /**< INTR_PENDING Position */ -#define MXC_F_ADC_INTR_PENDING ((uint32_t)(0x1UL << MXC_F_ADC_INTR_PENDING_POS)) /**< INTR_PENDING Mask */ - -/**@} end of group ADC_INTR_Register */ - -/** - * @ingroup adc_registers - * @defgroup ADC_LIMIT ADC_LIMIT - * @brief ADC Limit - * @{ - */ -#define MXC_F_ADC_LIMIT_CH_LO_LIMIT_POS 0 /**< LIMIT_CH_LO_LIMIT Position */ -#define MXC_F_ADC_LIMIT_CH_LO_LIMIT ((uint32_t)(0x3FFUL << MXC_F_ADC_LIMIT_CH_LO_LIMIT_POS)) /**< LIMIT_CH_LO_LIMIT Mask */ - -#define MXC_F_ADC_LIMIT_CH_HI_LIMIT_POS 12 /**< LIMIT_CH_HI_LIMIT Position */ -#define MXC_F_ADC_LIMIT_CH_HI_LIMIT ((uint32_t)(0x3FFUL << MXC_F_ADC_LIMIT_CH_HI_LIMIT_POS)) /**< LIMIT_CH_HI_LIMIT Mask */ - -#define MXC_F_ADC_LIMIT_CH_SEL_POS 24 /**< LIMIT_CH_SEL Position */ -#define MXC_F_ADC_LIMIT_CH_SEL ((uint32_t)(0xFUL << MXC_F_ADC_LIMIT_CH_SEL_POS)) /**< LIMIT_CH_SEL Mask */ - -#define MXC_F_ADC_LIMIT_CH_LO_LIMIT_EN_POS 28 /**< LIMIT_CH_LO_LIMIT_EN Position */ -#define MXC_F_ADC_LIMIT_CH_LO_LIMIT_EN ((uint32_t)(0x1UL << MXC_F_ADC_LIMIT_CH_LO_LIMIT_EN_POS)) /**< LIMIT_CH_LO_LIMIT_EN Mask */ - -#define MXC_F_ADC_LIMIT_CH_HI_LIMIT_EN_POS 29 /**< LIMIT_CH_HI_LIMIT_EN Position */ -#define MXC_F_ADC_LIMIT_CH_HI_LIMIT_EN ((uint32_t)(0x1UL << MXC_F_ADC_LIMIT_CH_HI_LIMIT_EN_POS)) /**< LIMIT_CH_HI_LIMIT_EN Mask */ - -/**@} end of group ADC_LIMIT_Register */ - -/** - * @ingroup adc_registers - * @defgroup ADC_DECCNT ADC_DECCNT - * @brief ADC Decimation Count. - * @{ - */ -#define MXC_F_ADC_DECCNT_DELAY_POS 0 /**< DECCNT_DELAY Position */ -#define MXC_F_ADC_DECCNT_DELAY ((uint32_t)(0xFFFFFFFFUL << MXC_F_ADC_DECCNT_DELAY_POS)) /**< DECCNT_DELAY Mask */ - -/**@} end of group ADC_DECCNT_Register */ - -#ifdef __cplusplus -} -#endif - -#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_ADC_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/dvs_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/dvs_regs.h deleted file mode 100644 index e5ba963cb40..00000000000 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/dvs_regs.h +++ /dev/null @@ -1,354 +0,0 @@ -/** - * @file dvs_regs.h - * @brief Registers, Bit Masks and Bit Positions for the DVS Peripheral Module. - * @note This file is @generated. - * @ingroup dvs_registers - */ - -/****************************************************************************** - * - * Analog Devices, Inc.), - * Copyright (C) 2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ******************************************************************************/ - -#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_DVS_REGS_H_ -#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_DVS_REGS_H_ - -/* **** Includes **** */ -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined (__ICCARM__) - #pragma system_include -#endif - -#if defined (__CC_ARM) - #pragma anon_unions -#endif -/// @cond -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif -#ifndef __R -#define __R volatile const -#endif -/// @endcond - -/* **** Definitions **** */ - -/** - * @ingroup dvs - * @defgroup dvs_registers DVS_Registers - * @brief Registers, Bit Masks and Bit Positions for the DVS Peripheral Module. - * @details Dynamic Voltage Scaling - */ - -/** - * @ingroup dvs_registers - * Structure type to access the DVS Registers. - */ -typedef struct { - __IO uint32_t ctl; /**< \b 0x00: DVS CTL Register */ - __IO uint32_t stat; /**< \b 0x04: DVS STAT Register */ - __IO uint32_t direct; /**< \b 0x08: DVS DIRECT Register */ - __IO uint32_t mon; /**< \b 0x00C: DVS MON Register */ - __IO uint32_t adj_up; /**< \b 0x010: DVS ADJ_UP Register */ - __IO uint32_t adj_dwn; /**< \b 0x014: DVS ADJ_DWN Register */ - __IO uint32_t thres_cmp; /**< \b 0x018: DVS THRES_CMP Register */ - __IO uint32_t tap_sel[5]; /**< \b 0x1C: DVS TAP_SEL Register */ -} mxc_dvs_regs_t; - -/* Register offsets for module DVS */ -/** - * @ingroup dvs_registers - * @defgroup DVS_Register_Offsets Register Offsets - * @brief DVS Peripheral Register Offsets from the DVS Base Peripheral Address. - * @{ - */ -#define MXC_R_DVS_CTL ((uint32_t)0x00000000UL) /**< Offset from DVS Base Address: 0x0000 */ -#define MXC_R_DVS_STAT ((uint32_t)0x00000004UL) /**< Offset from DVS Base Address: 0x0004 */ -#define MXC_R_DVS_DIRECT ((uint32_t)0x00000008UL) /**< Offset from DVS Base Address: 0x0008 */ -#define MXC_R_DVS_MON ((uint32_t)0x0000000CUL) /**< Offset from DVS Base Address: 0x000C */ -#define MXC_R_DVS_ADJ_UP ((uint32_t)0x00000010UL) /**< Offset from DVS Base Address: 0x0010 */ -#define MXC_R_DVS_ADJ_DWN ((uint32_t)0x00000014UL) /**< Offset from DVS Base Address: 0x0014 */ -#define MXC_R_DVS_THRES_CMP ((uint32_t)0x00000018UL) /**< Offset from DVS Base Address: 0x0018 */ -#define MXC_R_DVS_TAP_SEL ((uint32_t)0x0000001CUL) /**< Offset from DVS Base Address: 0x001C */ -/**@} end of group dvs_registers */ - -/** - * @ingroup dvs_registers - * @defgroup DVS_CTL DVS_CTL - * @brief Control Register - * @{ - */ -#define MXC_F_DVS_CTL_MON_ENA_POS 0 /**< CTL_MON_ENA Position */ -#define MXC_F_DVS_CTL_MON_ENA ((uint32_t)(0x1UL << MXC_F_DVS_CTL_MON_ENA_POS)) /**< CTL_MON_ENA Mask */ - -#define MXC_F_DVS_CTL_ADJ_ENA_POS 1 /**< CTL_ADJ_ENA Position */ -#define MXC_F_DVS_CTL_ADJ_ENA ((uint32_t)(0x1UL << MXC_F_DVS_CTL_ADJ_ENA_POS)) /**< CTL_ADJ_ENA Mask */ - -#define MXC_F_DVS_CTL_PS_FB_DIS_POS 2 /**< CTL_PS_FB_DIS Position */ -#define MXC_F_DVS_CTL_PS_FB_DIS ((uint32_t)(0x1UL << MXC_F_DVS_CTL_PS_FB_DIS_POS)) /**< CTL_PS_FB_DIS Mask */ - -#define MXC_F_DVS_CTL_CTRL_TAP_ENA_POS 3 /**< CTL_CTRL_TAP_ENA Position */ -#define MXC_F_DVS_CTL_CTRL_TAP_ENA ((uint32_t)(0x1UL << MXC_F_DVS_CTL_CTRL_TAP_ENA_POS)) /**< CTL_CTRL_TAP_ENA Mask */ - -#define MXC_F_DVS_CTL_PROP_DLY_POS 4 /**< CTL_PROP_DLY Position */ -#define MXC_F_DVS_CTL_PROP_DLY ((uint32_t)(0x3UL << MXC_F_DVS_CTL_PROP_DLY_POS)) /**< CTL_PROP_DLY Mask */ - -#define MXC_F_DVS_CTL_MON_ONESHOT_POS 6 /**< CTL_MON_ONESHOT Position */ -#define MXC_F_DVS_CTL_MON_ONESHOT ((uint32_t)(0x1UL << MXC_F_DVS_CTL_MON_ONESHOT_POS)) /**< CTL_MON_ONESHOT Mask */ - -#define MXC_F_DVS_CTL_GO_DIRECT_POS 7 /**< CTL_GO_DIRECT Position */ -#define MXC_F_DVS_CTL_GO_DIRECT ((uint32_t)(0x1UL << MXC_F_DVS_CTL_GO_DIRECT_POS)) /**< CTL_GO_DIRECT Mask */ - -#define MXC_F_DVS_CTL_DIRECT_REG_POS 8 /**< CTL_DIRECT_REG Position */ -#define MXC_F_DVS_CTL_DIRECT_REG ((uint32_t)(0x1UL << MXC_F_DVS_CTL_DIRECT_REG_POS)) /**< CTL_DIRECT_REG Mask */ - -#define MXC_F_DVS_CTL_PRIME_ENA_POS 9 /**< CTL_PRIME_ENA Position */ -#define MXC_F_DVS_CTL_PRIME_ENA ((uint32_t)(0x1UL << MXC_F_DVS_CTL_PRIME_ENA_POS)) /**< CTL_PRIME_ENA Mask */ - -#define MXC_F_DVS_CTL_LIMIT_IE_POS 10 /**< CTL_LIMIT_IE Position */ -#define MXC_F_DVS_CTL_LIMIT_IE ((uint32_t)(0x1UL << MXC_F_DVS_CTL_LIMIT_IE_POS)) /**< CTL_LIMIT_IE Mask */ - -#define MXC_F_DVS_CTL_RANGE_IE_POS 11 /**< CTL_RANGE_IE Position */ -#define MXC_F_DVS_CTL_RANGE_IE ((uint32_t)(0x1UL << MXC_F_DVS_CTL_RANGE_IE_POS)) /**< CTL_RANGE_IE Mask */ - -#define MXC_F_DVS_CTL_ADJ_IE_POS 12 /**< CTL_ADJ_IE Position */ -#define MXC_F_DVS_CTL_ADJ_IE ((uint32_t)(0x1UL << MXC_F_DVS_CTL_ADJ_IE_POS)) /**< CTL_ADJ_IE Mask */ - -#define MXC_F_DVS_CTL_REF_SEL_POS 13 /**< CTL_REF_SEL Position */ -#define MXC_F_DVS_CTL_REF_SEL ((uint32_t)(0xFUL << MXC_F_DVS_CTL_REF_SEL_POS)) /**< CTL_REF_SEL Mask */ - -#define MXC_F_DVS_CTL_INC_VAL_POS 17 /**< CTL_INC_VAL Position */ -#define MXC_F_DVS_CTL_INC_VAL ((uint32_t)(0x7UL << MXC_F_DVS_CTL_INC_VAL_POS)) /**< CTL_INC_VAL Mask */ - -#define MXC_F_DVS_CTL_DVS_PS_APB_DIS_POS 20 /**< CTL_DVS_PS_APB_DIS Position */ -#define MXC_F_DVS_CTL_DVS_PS_APB_DIS ((uint32_t)(0x1UL << MXC_F_DVS_CTL_DVS_PS_APB_DIS_POS)) /**< CTL_DVS_PS_APB_DIS Mask */ - -#define MXC_F_DVS_CTL_DVS_HI_RANGE_ANY_POS 21 /**< CTL_DVS_HI_RANGE_ANY Position */ -#define MXC_F_DVS_CTL_DVS_HI_RANGE_ANY ((uint32_t)(0x1UL << MXC_F_DVS_CTL_DVS_HI_RANGE_ANY_POS)) /**< CTL_DVS_HI_RANGE_ANY Mask */ - -#define MXC_F_DVS_CTL_FB_TO_IE_POS 22 /**< CTL_FB_TO_IE Position */ -#define MXC_F_DVS_CTL_FB_TO_IE ((uint32_t)(0x1UL << MXC_F_DVS_CTL_FB_TO_IE_POS)) /**< CTL_FB_TO_IE Mask */ - -#define MXC_F_DVS_CTL_FC_LV_IE_POS 23 /**< CTL_FC_LV_IE Position */ -#define MXC_F_DVS_CTL_FC_LV_IE ((uint32_t)(0x1UL << MXC_F_DVS_CTL_FC_LV_IE_POS)) /**< CTL_FC_LV_IE Mask */ - -#define MXC_F_DVS_CTL_PD_ACK_ENA_POS 24 /**< CTL_PD_ACK_ENA Position */ -#define MXC_F_DVS_CTL_PD_ACK_ENA ((uint32_t)(0x1UL << MXC_F_DVS_CTL_PD_ACK_ENA_POS)) /**< CTL_PD_ACK_ENA Mask */ - -#define MXC_F_DVS_CTL_ADJ_ABORT_POS 25 /**< CTL_ADJ_ABORT Position */ -#define MXC_F_DVS_CTL_ADJ_ABORT ((uint32_t)(0x1UL << MXC_F_DVS_CTL_ADJ_ABORT_POS)) /**< CTL_ADJ_ABORT Mask */ - -/**@} end of group DVS_CTL_Register */ - -/** - * @ingroup dvs_registers - * @defgroup DVS_STAT DVS_STAT - * @brief Status Fields - * @{ - */ -#define MXC_F_DVS_STAT_DVS_STATE_POS 0 /**< STAT_DVS_STATE Position */ -#define MXC_F_DVS_STAT_DVS_STATE ((uint32_t)(0xFUL << MXC_F_DVS_STAT_DVS_STATE_POS)) /**< STAT_DVS_STATE Mask */ - -#define MXC_F_DVS_STAT_ADJ_UP_ENA_POS 4 /**< STAT_ADJ_UP_ENA Position */ -#define MXC_F_DVS_STAT_ADJ_UP_ENA ((uint32_t)(0x1UL << MXC_F_DVS_STAT_ADJ_UP_ENA_POS)) /**< STAT_ADJ_UP_ENA Mask */ - -#define MXC_F_DVS_STAT_ADJ_DWN_ENA_POS 5 /**< STAT_ADJ_DWN_ENA Position */ -#define MXC_F_DVS_STAT_ADJ_DWN_ENA ((uint32_t)(0x1UL << MXC_F_DVS_STAT_ADJ_DWN_ENA_POS)) /**< STAT_ADJ_DWN_ENA Mask */ - -#define MXC_F_DVS_STAT_ADJ_ACTIVE_POS 6 /**< STAT_ADJ_ACTIVE Position */ -#define MXC_F_DVS_STAT_ADJ_ACTIVE ((uint32_t)(0x1UL << MXC_F_DVS_STAT_ADJ_ACTIVE_POS)) /**< STAT_ADJ_ACTIVE Mask */ - -#define MXC_F_DVS_STAT_CTR_TAP_OK_POS 7 /**< STAT_CTR_TAP_OK Position */ -#define MXC_F_DVS_STAT_CTR_TAP_OK ((uint32_t)(0x1UL << MXC_F_DVS_STAT_CTR_TAP_OK_POS)) /**< STAT_CTR_TAP_OK Mask */ - -#define MXC_F_DVS_STAT_CTR_TAP_SEL_POS 8 /**< STAT_CTR_TAP_SEL Position */ -#define MXC_F_DVS_STAT_CTR_TAP_SEL ((uint32_t)(0x1UL << MXC_F_DVS_STAT_CTR_TAP_SEL_POS)) /**< STAT_CTR_TAP_SEL Mask */ - -#define MXC_F_DVS_STAT_SLOW_TRIP_DET_POS 9 /**< STAT_SLOW_TRIP_DET Position */ -#define MXC_F_DVS_STAT_SLOW_TRIP_DET ((uint32_t)(0x1UL << MXC_F_DVS_STAT_SLOW_TRIP_DET_POS)) /**< STAT_SLOW_TRIP_DET Mask */ - -#define MXC_F_DVS_STAT_FAST_TRIP_DET_POS 10 /**< STAT_FAST_TRIP_DET Position */ -#define MXC_F_DVS_STAT_FAST_TRIP_DET ((uint32_t)(0x1UL << MXC_F_DVS_STAT_FAST_TRIP_DET_POS)) /**< STAT_FAST_TRIP_DET Mask */ - -#define MXC_F_DVS_STAT_PS_IN_RANGE_POS 11 /**< STAT_PS_IN_RANGE Position */ -#define MXC_F_DVS_STAT_PS_IN_RANGE ((uint32_t)(0x1UL << MXC_F_DVS_STAT_PS_IN_RANGE_POS)) /**< STAT_PS_IN_RANGE Mask */ - -#define MXC_F_DVS_STAT_PS_VCNTR_POS 12 /**< STAT_PS_VCNTR Position */ -#define MXC_F_DVS_STAT_PS_VCNTR ((uint32_t)(0x7FUL << MXC_F_DVS_STAT_PS_VCNTR_POS)) /**< STAT_PS_VCNTR Mask */ - -#define MXC_F_DVS_STAT_MON_DLY_OK_POS 19 /**< STAT_MON_DLY_OK Position */ -#define MXC_F_DVS_STAT_MON_DLY_OK ((uint32_t)(0x1UL << MXC_F_DVS_STAT_MON_DLY_OK_POS)) /**< STAT_MON_DLY_OK Mask */ - -#define MXC_F_DVS_STAT_ADJ_DLY_OK_POS 20 /**< STAT_ADJ_DLY_OK Position */ -#define MXC_F_DVS_STAT_ADJ_DLY_OK ((uint32_t)(0x1UL << MXC_F_DVS_STAT_ADJ_DLY_OK_POS)) /**< STAT_ADJ_DLY_OK Mask */ - -#define MXC_F_DVS_STAT_LO_LIMIT_DET_POS 21 /**< STAT_LO_LIMIT_DET Position */ -#define MXC_F_DVS_STAT_LO_LIMIT_DET ((uint32_t)(0x1UL << MXC_F_DVS_STAT_LO_LIMIT_DET_POS)) /**< STAT_LO_LIMIT_DET Mask */ - -#define MXC_F_DVS_STAT_HI_LIMIT_DET_POS 22 /**< STAT_HI_LIMIT_DET Position */ -#define MXC_F_DVS_STAT_HI_LIMIT_DET ((uint32_t)(0x1UL << MXC_F_DVS_STAT_HI_LIMIT_DET_POS)) /**< STAT_HI_LIMIT_DET Mask */ - -#define MXC_F_DVS_STAT_VALID_TAP_POS 23 /**< STAT_VALID_TAP Position */ -#define MXC_F_DVS_STAT_VALID_TAP ((uint32_t)(0x1UL << MXC_F_DVS_STAT_VALID_TAP_POS)) /**< STAT_VALID_TAP Mask */ - -#define MXC_F_DVS_STAT_LIMIT_ERR_POS 24 /**< STAT_LIMIT_ERR Position */ -#define MXC_F_DVS_STAT_LIMIT_ERR ((uint32_t)(0x1UL << MXC_F_DVS_STAT_LIMIT_ERR_POS)) /**< STAT_LIMIT_ERR Mask */ - -#define MXC_F_DVS_STAT_RANGE_ERR_POS 25 /**< STAT_RANGE_ERR Position */ -#define MXC_F_DVS_STAT_RANGE_ERR ((uint32_t)(0x1UL << MXC_F_DVS_STAT_RANGE_ERR_POS)) /**< STAT_RANGE_ERR Mask */ - -#define MXC_F_DVS_STAT_ADJ_ERR_POS 26 /**< STAT_ADJ_ERR Position */ -#define MXC_F_DVS_STAT_ADJ_ERR ((uint32_t)(0x1UL << MXC_F_DVS_STAT_ADJ_ERR_POS)) /**< STAT_ADJ_ERR Mask */ - -#define MXC_F_DVS_STAT_REF_SEL_ERR_POS 27 /**< STAT_REF_SEL_ERR Position */ -#define MXC_F_DVS_STAT_REF_SEL_ERR ((uint32_t)(0x1UL << MXC_F_DVS_STAT_REF_SEL_ERR_POS)) /**< STAT_REF_SEL_ERR Mask */ - -#define MXC_F_DVS_STAT_FB_TO_ERR_POS 28 /**< STAT_FB_TO_ERR Position */ -#define MXC_F_DVS_STAT_FB_TO_ERR ((uint32_t)(0x1UL << MXC_F_DVS_STAT_FB_TO_ERR_POS)) /**< STAT_FB_TO_ERR Mask */ - -#define MXC_F_DVS_STAT_FB_TO_ERR_S_POS 29 /**< STAT_FB_TO_ERR_S Position */ -#define MXC_F_DVS_STAT_FB_TO_ERR_S ((uint32_t)(0x1UL << MXC_F_DVS_STAT_FB_TO_ERR_S_POS)) /**< STAT_FB_TO_ERR_S Mask */ - -#define MXC_F_DVS_STAT_FC_LV_DET_INT_POS 30 /**< STAT_FC_LV_DET_INT Position */ -#define MXC_F_DVS_STAT_FC_LV_DET_INT ((uint32_t)(0x1UL << MXC_F_DVS_STAT_FC_LV_DET_INT_POS)) /**< STAT_FC_LV_DET_INT Mask */ - -#define MXC_F_DVS_STAT_FC_LV_DET_S_POS 31 /**< STAT_FC_LV_DET_S Position */ -#define MXC_F_DVS_STAT_FC_LV_DET_S ((uint32_t)(0x1UL << MXC_F_DVS_STAT_FC_LV_DET_S_POS)) /**< STAT_FC_LV_DET_S Mask */ - -/**@} end of group DVS_STAT_Register */ - -/** - * @ingroup dvs_registers - * @defgroup DVS_DIRECT DVS_DIRECT - * @brief Direct control of target voltage - * @{ - */ -#define MXC_F_DVS_DIRECT_VOLTAGE_POS 0 /**< DIRECT_VOLTAGE Position */ -#define MXC_F_DVS_DIRECT_VOLTAGE ((uint32_t)(0x7FUL << MXC_F_DVS_DIRECT_VOLTAGE_POS)) /**< DIRECT_VOLTAGE Mask */ - -/**@} end of group DVS_DIRECT_Register */ - -/** - * @ingroup dvs_registers - * @defgroup DVS_MON DVS_MON - * @brief Monitor Delay - * @{ - */ -#define MXC_F_DVS_MON_DLY_POS 0 /**< MON_DLY Position */ -#define MXC_F_DVS_MON_DLY ((uint32_t)(0xFFFFFFUL << MXC_F_DVS_MON_DLY_POS)) /**< MON_DLY Mask */ - -#define MXC_F_DVS_MON_PRE_POS 24 /**< MON_PRE Position */ -#define MXC_F_DVS_MON_PRE ((uint32_t)(0xFFUL << MXC_F_DVS_MON_PRE_POS)) /**< MON_PRE Mask */ - -/**@} end of group DVS_MON_Register */ - -/** - * @ingroup dvs_registers - * @defgroup DVS_ADJ_UP DVS_ADJ_UP - * @brief Up Delay Register - * @{ - */ -#define MXC_F_DVS_ADJ_UP_DLY_POS 0 /**< ADJ_UP_DLY Position */ -#define MXC_F_DVS_ADJ_UP_DLY ((uint32_t)(0xFFFFUL << MXC_F_DVS_ADJ_UP_DLY_POS)) /**< ADJ_UP_DLY Mask */ - -#define MXC_F_DVS_ADJ_UP_PRE_POS 16 /**< ADJ_UP_PRE Position */ -#define MXC_F_DVS_ADJ_UP_PRE ((uint32_t)(0xFFUL << MXC_F_DVS_ADJ_UP_PRE_POS)) /**< ADJ_UP_PRE Mask */ - -/**@} end of group DVS_ADJ_UP_Register */ - -/** - * @ingroup dvs_registers - * @defgroup DVS_ADJ_DWN DVS_ADJ_DWN - * @brief Down Delay Register - * @{ - */ -#define MXC_F_DVS_ADJ_DWN_DLY_POS 0 /**< ADJ_DWN_DLY Position */ -#define MXC_F_DVS_ADJ_DWN_DLY ((uint32_t)(0xFFFFUL << MXC_F_DVS_ADJ_DWN_DLY_POS)) /**< ADJ_DWN_DLY Mask */ - -#define MXC_F_DVS_ADJ_DWN_PRE_POS 16 /**< ADJ_DWN_PRE Position */ -#define MXC_F_DVS_ADJ_DWN_PRE ((uint32_t)(0xFFUL << MXC_F_DVS_ADJ_DWN_PRE_POS)) /**< ADJ_DWN_PRE Mask */ - -/**@} end of group DVS_ADJ_DWN_Register */ - -/** - * @ingroup dvs_registers - * @defgroup DVS_THRES_CMP DVS_THRES_CMP - * @brief Up Delay Register - * @{ - */ -#define MXC_F_DVS_THRES_CMP_VCNTR_THRES_CNT_POS 0 /**< THRES_CMP_VCNTR_THRES_CNT Position */ -#define MXC_F_DVS_THRES_CMP_VCNTR_THRES_CNT ((uint32_t)(0x7FUL << MXC_F_DVS_THRES_CMP_VCNTR_THRES_CNT_POS)) /**< THRES_CMP_VCNTR_THRES_CNT Mask */ - -#define MXC_F_DVS_THRES_CMP_VCNTR_THRES_MASK_POS 8 /**< THRES_CMP_VCNTR_THRES_MASK Position */ -#define MXC_F_DVS_THRES_CMP_VCNTR_THRES_MASK ((uint32_t)(0x7FUL << MXC_F_DVS_THRES_CMP_VCNTR_THRES_MASK_POS)) /**< THRES_CMP_VCNTR_THRES_MASK Mask */ - -/**@} end of group DVS_THRES_CMP_Register */ - -/** - * @ingroup dvs_registers - * @defgroup DVS_TAP_SEL DVS_TAP_SEL - * @brief DVS Tap Select Register - * @{ - */ -#define MXC_F_DVS_TAP_SEL_LO_POS 0 /**< TAP_SEL_LO Position */ -#define MXC_F_DVS_TAP_SEL_LO ((uint32_t)(0x1FUL << MXC_F_DVS_TAP_SEL_LO_POS)) /**< TAP_SEL_LO Mask */ - -#define MXC_F_DVS_TAP_SEL_LO_TAP_STAT_POS 5 /**< TAP_SEL_LO_TAP_STAT Position */ -#define MXC_F_DVS_TAP_SEL_LO_TAP_STAT ((uint32_t)(0x1UL << MXC_F_DVS_TAP_SEL_LO_TAP_STAT_POS)) /**< TAP_SEL_LO_TAP_STAT Mask */ - -#define MXC_F_DVS_TAP_SEL_CTR_TAP_STAT_POS 6 /**< TAP_SEL_CTR_TAP_STAT Position */ -#define MXC_F_DVS_TAP_SEL_CTR_TAP_STAT ((uint32_t)(0x1UL << MXC_F_DVS_TAP_SEL_CTR_TAP_STAT_POS)) /**< TAP_SEL_CTR_TAP_STAT Mask */ - -#define MXC_F_DVS_TAP_SEL_HI_TAP_STAT_POS 7 /**< TAP_SEL_HI_TAP_STAT Position */ -#define MXC_F_DVS_TAP_SEL_HI_TAP_STAT ((uint32_t)(0x1UL << MXC_F_DVS_TAP_SEL_HI_TAP_STAT_POS)) /**< TAP_SEL_HI_TAP_STAT Mask */ - -#define MXC_F_DVS_TAP_SEL_HI_POS 8 /**< TAP_SEL_HI Position */ -#define MXC_F_DVS_TAP_SEL_HI ((uint32_t)(0x1FUL << MXC_F_DVS_TAP_SEL_HI_POS)) /**< TAP_SEL_HI Mask */ - -#define MXC_F_DVS_TAP_SEL_CTR_POS 16 /**< TAP_SEL_CTR Position */ -#define MXC_F_DVS_TAP_SEL_CTR ((uint32_t)(0x1FUL << MXC_F_DVS_TAP_SEL_CTR_POS)) /**< TAP_SEL_CTR Mask */ - -#define MXC_F_DVS_TAP_SEL_COARSE_POS 24 /**< TAP_SEL_COARSE Position */ -#define MXC_F_DVS_TAP_SEL_COARSE ((uint32_t)(0x7UL << MXC_F_DVS_TAP_SEL_COARSE_POS)) /**< TAP_SEL_COARSE Mask */ - -#define MXC_F_DVS_TAP_SEL_DET_DLY_POS 29 /**< TAP_SEL_DET_DLY Position */ -#define MXC_F_DVS_TAP_SEL_DET_DLY ((uint32_t)(0x3UL << MXC_F_DVS_TAP_SEL_DET_DLY_POS)) /**< TAP_SEL_DET_DLY Mask */ - -#define MXC_F_DVS_TAP_SEL_DELAY_ACT_POS 31 /**< TAP_SEL_DELAY_ACT Position */ -#define MXC_F_DVS_TAP_SEL_DELAY_ACT ((uint32_t)(0x1UL << MXC_F_DVS_TAP_SEL_DELAY_ACT_POS)) /**< TAP_SEL_DELAY_ACT Mask */ - -/**@} end of group DVS_TAP_SEL_Register */ - -#ifdef __cplusplus -} -#endif - -#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_DVS_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcfr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcfr_regs.h deleted file mode 100644 index f236a45c322..00000000000 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcfr_regs.h +++ /dev/null @@ -1,123 +0,0 @@ -/** - * @file gcfr_regs.h - * @brief Registers, Bit Masks and Bit Positions for the GCFR Peripheral Module. - * @note This file is @generated. - * @ingroup gcfr_registers - */ - -/****************************************************************************** - * - * Analog Devices, Inc.), - * Copyright (C) 2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ******************************************************************************/ - -#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_GCFR_REGS_H_ -#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_GCFR_REGS_H_ - -/* **** Includes **** */ -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined (__ICCARM__) - #pragma system_include -#endif - -#if defined (__CC_ARM) - #pragma anon_unions -#endif -/// @cond -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif -#ifndef __R -#define __R volatile const -#endif -/// @endcond - -/* **** Definitions **** */ - -/** - * @ingroup gcfr - * @defgroup gcfr_registers GCFR_Registers - * @brief Registers, Bit Masks and Bit Positions for the GCFR Peripheral Module. - * @details Global Control Function Register. - */ - -/** - * @ingroup gcfr_registers - * Structure type to access the GCFR Registers. - */ -typedef struct { - __IO uint32_t reg0; /**< \b 0x00: GCFR REG0 Register */ - __IO uint32_t reg1; /**< \b 0x04: GCFR REG1 Register */ -} mxc_gcfr_regs_t; - -/* Register offsets for module GCFR */ -/** - * @ingroup gcfr_registers - * @defgroup GCFR_Register_Offsets Register Offsets - * @brief GCFR Peripheral Register Offsets from the GCFR Base Peripheral Address. - * @{ - */ -#define MXC_R_GCFR_REG0 ((uint32_t)0x00000000UL) /**< Offset from GCFR Base Address: 0x0000 */ -#define MXC_R_GCFR_REG1 ((uint32_t)0x00000004UL) /**< Offset from GCFR Base Address: 0x0004 */ -/**@} end of group gcfr_registers */ - -/** - * @ingroup gcfr_registers - * @defgroup GCFR_REG0 GCFR_REG0 - * @brief Register 0. - * @{ - */ -#define MXC_F_GCFR_REG0_ISO_WUP_POS 0 /**< REG0_ISO_WUP Position */ -#define MXC_F_GCFR_REG0_ISO_WUP ((uint32_t)(0x1FFUL << MXC_F_GCFR_REG0_ISO_WUP_POS)) /**< REG0_ISO_WUP Mask */ - -#define MXC_F_GCFR_REG0_IPO_WUP_POS 16 /**< REG0_IPO_WUP Position */ -#define MXC_F_GCFR_REG0_IPO_WUP ((uint32_t)(0x7FFUL << MXC_F_GCFR_REG0_IPO_WUP_POS)) /**< REG0_IPO_WUP Mask */ - -/**@} end of group GCFR_REG0_Register */ - -/** - * @ingroup gcfr_registers - * @defgroup GCFR_REG1 GCFR_REG1 - * @brief Register 1. - * @{ - */ -#define MXC_F_GCFR_REG1_ERFO_WUP_POS 0 /**< REG1_ERFO_WUP Position */ -#define MXC_F_GCFR_REG1_ERFO_WUP ((uint32_t)(0x3FFFUL << MXC_F_GCFR_REG1_ERFO_WUP_POS)) /**< REG1_ERFO_WUP Mask */ - -#define MXC_F_GCFR_REG1_IBRO_WUP_POS 16 /**< REG1_IBRO_WUP Position */ -#define MXC_F_GCFR_REG1_IBRO_WUP ((uint32_t)(0x3FUL << MXC_F_GCFR_REG1_IBRO_WUP_POS)) /**< REG1_IBRO_WUP Mask */ - -/**@} end of group GCFR_REG1_Register */ - -#ifdef __cplusplus -} -#endif - -#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_GCFR_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/i2c_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/i2c_regs.h deleted file mode 100644 index f45b5c18180..00000000000 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/i2c_regs.h +++ /dev/null @@ -1,590 +0,0 @@ -/** - * @file i2c_regs.h - * @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module. - * @note This file is @generated. - * @ingroup i2c_registers - */ - -/****************************************************************************** - * - * Copyright (C) 2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ******************************************************************************/ - -#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_I2C_REGS_H_ -#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_I2C_REGS_H_ - -/* **** Includes **** */ -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined (__ICCARM__) - #pragma system_include -#endif - -#if defined (__CC_ARM) - #pragma anon_unions -#endif -/// @cond -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif -#ifndef __R -#define __R volatile const -#endif -/// @endcond - -/* **** Definitions **** */ - -/** - * @ingroup i2c - * @defgroup i2c_registers I2C_Registers - * @brief Registers, Bit Masks and Bit Positions for the I2C Peripheral Module. - * @details Inter-Integrated Circuit. - */ - -/** - * @ingroup i2c_registers - * Structure type to access the I2C Registers. - */ -typedef struct { - __IO uint32_t ctrl; /**< \b 0x00: I2C CTRL Register */ - __IO uint32_t status; /**< \b 0x04: I2C STATUS Register */ - __IO uint32_t intfl0; /**< \b 0x08: I2C INTFL0 Register */ - __IO uint32_t inten0; /**< \b 0x0C: I2C INTEN0 Register */ - __IO uint32_t intfl1; /**< \b 0x10: I2C INTFL1 Register */ - __IO uint32_t inten1; /**< \b 0x14: I2C INTEN1 Register */ - __IO uint32_t fifolen; /**< \b 0x18: I2C FIFOLEN Register */ - __IO uint32_t rxctrl0; /**< \b 0x1C: I2C RXCTRL0 Register */ - __IO uint32_t rxctrl1; /**< \b 0x20: I2C RXCTRL1 Register */ - __IO uint32_t txctrl0; /**< \b 0x24: I2C TXCTRL0 Register */ - __IO uint32_t txctrl1; /**< \b 0x28: I2C TXCTRL1 Register */ - __IO uint32_t fifo; /**< \b 0x2C: I2C FIFO Register */ - __IO uint32_t mstctrl; /**< \b 0x30: I2C MSTCTRL Register */ - __IO uint32_t clklo; /**< \b 0x34: I2C CLKLO Register */ - __IO uint32_t clkhi; /**< \b 0x38: I2C CLKHI Register */ - __IO uint32_t hsclk; /**< \b 0x3C: I2C HSCLK Register */ - __IO uint32_t timeout; /**< \b 0x40: I2C TIMEOUT Register */ - __R uint32_t rsv_0x44; - __IO uint32_t dma; /**< \b 0x48: I2C DMA Register */ - union { - __IO uint32_t slave_multi[4]; /**< \b 0x4C: I2C SLAVE_MULTI Register */ - struct { - __IO uint32_t slave0; /**< \b 0x4C: I2C SLAVE0 Register */ - __IO uint32_t slave1; /**< \b 0x50: I2C SLAVE1 Register */ - __IO uint32_t slave2; /**< \b 0x54: I2C SLAVE2 Register */ - __IO uint32_t slave3; /**< \b 0x58: I2C SLAVE3 Register */ - }; - }; -} mxc_i2c_regs_t; - -/* Register offsets for module I2C */ -/** - * @ingroup i2c_registers - * @defgroup I2C_Register_Offsets Register Offsets - * @brief I2C Peripheral Register Offsets from the I2C Base Peripheral Address. - * @{ - */ -#define MXC_R_I2C_CTRL ((uint32_t)0x00000000UL) /**< Offset from I2C Base Address: 0x0000 */ -#define MXC_R_I2C_STATUS ((uint32_t)0x00000004UL) /**< Offset from I2C Base Address: 0x0004 */ -#define MXC_R_I2C_INTFL0 ((uint32_t)0x00000008UL) /**< Offset from I2C Base Address: 0x0008 */ -#define MXC_R_I2C_INTEN0 ((uint32_t)0x0000000CUL) /**< Offset from I2C Base Address: 0x000C */ -#define MXC_R_I2C_INTFL1 ((uint32_t)0x00000010UL) /**< Offset from I2C Base Address: 0x0010 */ -#define MXC_R_I2C_INTEN1 ((uint32_t)0x00000014UL) /**< Offset from I2C Base Address: 0x0014 */ -#define MXC_R_I2C_FIFOLEN ((uint32_t)0x00000018UL) /**< Offset from I2C Base Address: 0x0018 */ -#define MXC_R_I2C_RXCTRL0 ((uint32_t)0x0000001CUL) /**< Offset from I2C Base Address: 0x001C */ -#define MXC_R_I2C_RXCTRL1 ((uint32_t)0x00000020UL) /**< Offset from I2C Base Address: 0x0020 */ -#define MXC_R_I2C_TXCTRL0 ((uint32_t)0x00000024UL) /**< Offset from I2C Base Address: 0x0024 */ -#define MXC_R_I2C_TXCTRL1 ((uint32_t)0x00000028UL) /**< Offset from I2C Base Address: 0x0028 */ -#define MXC_R_I2C_FIFO ((uint32_t)0x0000002CUL) /**< Offset from I2C Base Address: 0x002C */ -#define MXC_R_I2C_MSTCTRL ((uint32_t)0x00000030UL) /**< Offset from I2C Base Address: 0x0030 */ -#define MXC_R_I2C_CLKLO ((uint32_t)0x00000034UL) /**< Offset from I2C Base Address: 0x0034 */ -#define MXC_R_I2C_CLKHI ((uint32_t)0x00000038UL) /**< Offset from I2C Base Address: 0x0038 */ -#define MXC_R_I2C_HSCLK ((uint32_t)0x0000003CUL) /**< Offset from I2C Base Address: 0x003C */ -#define MXC_R_I2C_TIMEOUT ((uint32_t)0x00000040UL) /**< Offset from I2C Base Address: 0x0040 */ -#define MXC_R_I2C_DMA ((uint32_t)0x00000048UL) /**< Offset from I2C Base Address: 0x0048 */ -#define MXC_R_I2C_SLAVE_MULTI ((uint32_t)0x0000004CUL) /**< Offset from I2C Base Address: 0x004C */ -#define MXC_R_I2C_SLAVE0 ((uint32_t)0x0000004CUL) /**< Offset from I2C Base Address: 0x004C */ -#define MXC_R_I2C_SLAVE1 ((uint32_t)0x00000050UL) /**< Offset from I2C Base Address: 0x0050 */ -#define MXC_R_I2C_SLAVE2 ((uint32_t)0x00000054UL) /**< Offset from I2C Base Address: 0x0054 */ -#define MXC_R_I2C_SLAVE3 ((uint32_t)0x00000058UL) /**< Offset from I2C Base Address: 0x0058 */ -/**@} end of group i2c_registers */ - -/** - * @ingroup i2c_registers - * @defgroup I2C_CTRL I2C_CTRL - * @brief Control Register0. - * @{ - */ -#define MXC_F_I2C_CTRL_EN_POS 0 /**< CTRL_EN Position */ -#define MXC_F_I2C_CTRL_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_EN_POS)) /**< CTRL_EN Mask */ - -#define MXC_F_I2C_CTRL_MST_MODE_POS 1 /**< CTRL_MST_MODE Position */ -#define MXC_F_I2C_CTRL_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_MST_MODE_POS)) /**< CTRL_MST_MODE Mask */ - -#define MXC_F_I2C_CTRL_GC_ADDR_EN_POS 2 /**< CTRL_GC_ADDR_EN Position */ -#define MXC_F_I2C_CTRL_GC_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_GC_ADDR_EN_POS)) /**< CTRL_GC_ADDR_EN Mask */ - -#define MXC_F_I2C_CTRL_IRXM_EN_POS 3 /**< CTRL_IRXM_EN Position */ -#define MXC_F_I2C_CTRL_IRXM_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_IRXM_EN_POS)) /**< CTRL_IRXM_EN Mask */ - -#define MXC_F_I2C_CTRL_IRXM_ACK_POS 4 /**< CTRL_IRXM_ACK Position */ -#define MXC_F_I2C_CTRL_IRXM_ACK ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_IRXM_ACK_POS)) /**< CTRL_IRXM_ACK Mask */ - -#define MXC_F_I2C_CTRL_SCL_OUT_POS 6 /**< CTRL_SCL_OUT Position */ -#define MXC_F_I2C_CTRL_SCL_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_OUT_POS)) /**< CTRL_SCL_OUT Mask */ - -#define MXC_F_I2C_CTRL_SDA_OUT_POS 7 /**< CTRL_SDA_OUT Position */ -#define MXC_F_I2C_CTRL_SDA_OUT ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_OUT_POS)) /**< CTRL_SDA_OUT Mask */ - -#define MXC_F_I2C_CTRL_SCL_POS 8 /**< CTRL_SCL Position */ -#define MXC_F_I2C_CTRL_SCL ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SCL_POS)) /**< CTRL_SCL Mask */ - -#define MXC_F_I2C_CTRL_SDA_POS 9 /**< CTRL_SDA Position */ -#define MXC_F_I2C_CTRL_SDA ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_SDA_POS)) /**< CTRL_SDA Mask */ - -#define MXC_F_I2C_CTRL_BB_EN_POS 10 /**< CTRL_BB_EN Position */ -#define MXC_F_I2C_CTRL_BB_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_BB_EN_POS)) /**< CTRL_BB_EN Mask */ - -#define MXC_F_I2C_CTRL_READ_POS 11 /**< CTRL_READ Position */ -#define MXC_F_I2C_CTRL_READ ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_READ_POS)) /**< CTRL_READ Mask */ - -#define MXC_F_I2C_CTRL_CLKSTR_DIS_POS 12 /**< CTRL_CLKSTR_DIS Position */ -#define MXC_F_I2C_CTRL_CLKSTR_DIS ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_CLKSTR_DIS_POS)) /**< CTRL_CLKSTR_DIS Mask */ - -#define MXC_F_I2C_CTRL_ONE_MST_MODE_POS 13 /**< CTRL_ONE_MST_MODE Position */ -#define MXC_F_I2C_CTRL_ONE_MST_MODE ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_ONE_MST_MODE_POS)) /**< CTRL_ONE_MST_MODE Mask */ - -#define MXC_F_I2C_CTRL_HS_EN_POS 15 /**< CTRL_HS_EN Position */ -#define MXC_F_I2C_CTRL_HS_EN ((uint32_t)(0x1UL << MXC_F_I2C_CTRL_HS_EN_POS)) /**< CTRL_HS_EN Mask */ - -/**@} end of group I2C_CTRL_Register */ - -/** - * @ingroup i2c_registers - * @defgroup I2C_STATUS I2C_STATUS - * @brief Status Register. - * @{ - */ -#define MXC_F_I2C_STATUS_BUSY_POS 0 /**< STATUS_BUSY Position */ -#define MXC_F_I2C_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_BUSY_POS)) /**< STATUS_BUSY Mask */ - -#define MXC_F_I2C_STATUS_RX_EM_POS 1 /**< STATUS_RX_EM Position */ -#define MXC_F_I2C_STATUS_RX_EM ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_EM_POS)) /**< STATUS_RX_EM Mask */ - -#define MXC_F_I2C_STATUS_RX_FULL_POS 2 /**< STATUS_RX_FULL Position */ -#define MXC_F_I2C_STATUS_RX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_RX_FULL_POS)) /**< STATUS_RX_FULL Mask */ - -#define MXC_F_I2C_STATUS_TX_EM_POS 3 /**< STATUS_TX_EM Position */ -#define MXC_F_I2C_STATUS_TX_EM ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_EM_POS)) /**< STATUS_TX_EM Mask */ - -#define MXC_F_I2C_STATUS_TX_FULL_POS 4 /**< STATUS_TX_FULL Position */ -#define MXC_F_I2C_STATUS_TX_FULL ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_TX_FULL_POS)) /**< STATUS_TX_FULL Mask */ - -#define MXC_F_I2C_STATUS_MST_BUSY_POS 5 /**< STATUS_MST_BUSY Position */ -#define MXC_F_I2C_STATUS_MST_BUSY ((uint32_t)(0x1UL << MXC_F_I2C_STATUS_MST_BUSY_POS)) /**< STATUS_MST_BUSY Mask */ - -/**@} end of group I2C_STATUS_Register */ - -/** - * @ingroup i2c_registers - * @defgroup I2C_INTFL0 I2C_INTFL0 - * @brief Interrupt Status Register. - * @{ - */ -#define MXC_F_I2C_INTFL0_DONE_POS 0 /**< INTFL0_DONE Position */ -#define MXC_F_I2C_INTFL0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DONE_POS)) /**< INTFL0_DONE Mask */ - -#define MXC_F_I2C_INTFL0_IRXM_POS 1 /**< INTFL0_IRXM Position */ -#define MXC_F_I2C_INTFL0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_IRXM_POS)) /**< INTFL0_IRXM Mask */ - -#define MXC_F_I2C_INTFL0_GC_ADDR_MATCH_POS 2 /**< INTFL0_GC_ADDR_MATCH Position */ -#define MXC_F_I2C_INTFL0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_GC_ADDR_MATCH_POS)) /**< INTFL0_GC_ADDR_MATCH Mask */ - -#define MXC_F_I2C_INTFL0_ADDR_MATCH_POS 3 /**< INTFL0_ADDR_MATCH Position */ -#define MXC_F_I2C_INTFL0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADDR_MATCH_POS)) /**< INTFL0_ADDR_MATCH Mask */ - -#define MXC_F_I2C_INTFL0_RX_THD_POS 4 /**< INTFL0_RX_THD Position */ -#define MXC_F_I2C_INTFL0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_RX_THD_POS)) /**< INTFL0_RX_THD Mask */ - -#define MXC_F_I2C_INTFL0_TX_THD_POS 5 /**< INTFL0_TX_THD Position */ -#define MXC_F_I2C_INTFL0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TX_THD_POS)) /**< INTFL0_TX_THD Mask */ - -#define MXC_F_I2C_INTFL0_STOP_POS 6 /**< INTFL0_STOP Position */ -#define MXC_F_I2C_INTFL0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STOP_POS)) /**< INTFL0_STOP Mask */ - -#define MXC_F_I2C_INTFL0_ADDR_ACK_POS 7 /**< INTFL0_ADDR_ACK Position */ -#define MXC_F_I2C_INTFL0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADDR_ACK_POS)) /**< INTFL0_ADDR_ACK Mask */ - -#define MXC_F_I2C_INTFL0_ARB_ERR_POS 8 /**< INTFL0_ARB_ERR Position */ -#define MXC_F_I2C_INTFL0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ARB_ERR_POS)) /**< INTFL0_ARB_ERR Mask */ - -#define MXC_F_I2C_INTFL0_TO_ERR_POS 9 /**< INTFL0_TO_ERR Position */ -#define MXC_F_I2C_INTFL0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TO_ERR_POS)) /**< INTFL0_TO_ERR Mask */ - -#define MXC_F_I2C_INTFL0_ADDR_NACK_ERR_POS 10 /**< INTFL0_ADDR_NACK_ERR Position */ -#define MXC_F_I2C_INTFL0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_ADDR_NACK_ERR_POS)) /**< INTFL0_ADDR_NACK_ERR Mask */ - -#define MXC_F_I2C_INTFL0_DATA_ERR_POS 11 /**< INTFL0_DATA_ERR Position */ -#define MXC_F_I2C_INTFL0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DATA_ERR_POS)) /**< INTFL0_DATA_ERR Mask */ - -#define MXC_F_I2C_INTFL0_DNR_ERR_POS 12 /**< INTFL0_DNR_ERR Position */ -#define MXC_F_I2C_INTFL0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_DNR_ERR_POS)) /**< INTFL0_DNR_ERR Mask */ - -#define MXC_F_I2C_INTFL0_START_ERR_POS 13 /**< INTFL0_START_ERR Position */ -#define MXC_F_I2C_INTFL0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_START_ERR_POS)) /**< INTFL0_START_ERR Mask */ - -#define MXC_F_I2C_INTFL0_STOP_ERR_POS 14 /**< INTFL0_STOP_ERR Position */ -#define MXC_F_I2C_INTFL0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_STOP_ERR_POS)) /**< INTFL0_STOP_ERR Mask */ - -#define MXC_F_I2C_INTFL0_TX_LOCKOUT_POS 15 /**< INTFL0_TX_LOCKOUT Position */ -#define MXC_F_I2C_INTFL0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_TX_LOCKOUT_POS)) /**< INTFL0_TX_LOCKOUT Mask */ - -#define MXC_F_I2C_INTFL0_MAMI_POS 16 /**< INTFL0_MAMI Position */ -#define MXC_F_I2C_INTFL0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_INTFL0_MAMI_POS)) /**< INTFL0_MAMI Mask */ - -#define MXC_F_I2C_INTFL0_RD_ADDR_MATCH_POS 22 /**< INTFL0_RD_ADDR_MATCH Position */ -#define MXC_F_I2C_INTFL0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_RD_ADDR_MATCH_POS)) /**< INTFL0_RD_ADDR_MATCH Mask */ - -#define MXC_F_I2C_INTFL0_WR_ADDR_MATCH_POS 23 /**< INTFL0_WR_ADDR_MATCH Position */ -#define MXC_F_I2C_INTFL0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTFL0_WR_ADDR_MATCH_POS)) /**< INTFL0_WR_ADDR_MATCH Mask */ - -/**@} end of group I2C_INTFL0_Register */ - -/** - * @ingroup i2c_registers - * @defgroup I2C_INTEN0 I2C_INTEN0 - * @brief Interrupt Enable Register. - * @{ - */ -#define MXC_F_I2C_INTEN0_DONE_POS 0 /**< INTEN0_DONE Position */ -#define MXC_F_I2C_INTEN0_DONE ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DONE_POS)) /**< INTEN0_DONE Mask */ - -#define MXC_F_I2C_INTEN0_IRXM_POS 1 /**< INTEN0_IRXM Position */ -#define MXC_F_I2C_INTEN0_IRXM ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_IRXM_POS)) /**< INTEN0_IRXM Mask */ - -#define MXC_F_I2C_INTEN0_GC_ADDR_MATCH_POS 2 /**< INTEN0_GC_ADDR_MATCH Position */ -#define MXC_F_I2C_INTEN0_GC_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_GC_ADDR_MATCH_POS)) /**< INTEN0_GC_ADDR_MATCH Mask */ - -#define MXC_F_I2C_INTEN0_ADDR_MATCH_POS 3 /**< INTEN0_ADDR_MATCH Position */ -#define MXC_F_I2C_INTEN0_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADDR_MATCH_POS)) /**< INTEN0_ADDR_MATCH Mask */ - -#define MXC_F_I2C_INTEN0_RX_THD_POS 4 /**< INTEN0_RX_THD Position */ -#define MXC_F_I2C_INTEN0_RX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_RX_THD_POS)) /**< INTEN0_RX_THD Mask */ - -#define MXC_F_I2C_INTEN0_TX_THD_POS 5 /**< INTEN0_TX_THD Position */ -#define MXC_F_I2C_INTEN0_TX_THD ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TX_THD_POS)) /**< INTEN0_TX_THD Mask */ - -#define MXC_F_I2C_INTEN0_STOP_POS 6 /**< INTEN0_STOP Position */ -#define MXC_F_I2C_INTEN0_STOP ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOP_POS)) /**< INTEN0_STOP Mask */ - -#define MXC_F_I2C_INTEN0_ADDR_ACK_POS 7 /**< INTEN0_ADDR_ACK Position */ -#define MXC_F_I2C_INTEN0_ADDR_ACK ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADDR_ACK_POS)) /**< INTEN0_ADDR_ACK Mask */ - -#define MXC_F_I2C_INTEN0_ARB_ERR_POS 8 /**< INTEN0_ARB_ERR Position */ -#define MXC_F_I2C_INTEN0_ARB_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ARB_ERR_POS)) /**< INTEN0_ARB_ERR Mask */ - -#define MXC_F_I2C_INTEN0_TO_ERR_POS 9 /**< INTEN0_TO_ERR Position */ -#define MXC_F_I2C_INTEN0_TO_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TO_ERR_POS)) /**< INTEN0_TO_ERR Mask */ - -#define MXC_F_I2C_INTEN0_ADDR_NACK_ERR_POS 10 /**< INTEN0_ADDR_NACK_ERR Position */ -#define MXC_F_I2C_INTEN0_ADDR_NACK_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_ADDR_NACK_ERR_POS)) /**< INTEN0_ADDR_NACK_ERR Mask */ - -#define MXC_F_I2C_INTEN0_DATA_ERR_POS 11 /**< INTEN0_DATA_ERR Position */ -#define MXC_F_I2C_INTEN0_DATA_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DATA_ERR_POS)) /**< INTEN0_DATA_ERR Mask */ - -#define MXC_F_I2C_INTEN0_DNR_ERR_POS 12 /**< INTEN0_DNR_ERR Position */ -#define MXC_F_I2C_INTEN0_DNR_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_DNR_ERR_POS)) /**< INTEN0_DNR_ERR Mask */ - -#define MXC_F_I2C_INTEN0_START_ERR_POS 13 /**< INTEN0_START_ERR Position */ -#define MXC_F_I2C_INTEN0_START_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_START_ERR_POS)) /**< INTEN0_START_ERR Mask */ - -#define MXC_F_I2C_INTEN0_STOP_ERR_POS 14 /**< INTEN0_STOP_ERR Position */ -#define MXC_F_I2C_INTEN0_STOP_ERR ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_STOP_ERR_POS)) /**< INTEN0_STOP_ERR Mask */ - -#define MXC_F_I2C_INTEN0_TX_LOCKOUT_POS 15 /**< INTEN0_TX_LOCKOUT Position */ -#define MXC_F_I2C_INTEN0_TX_LOCKOUT ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_TX_LOCKOUT_POS)) /**< INTEN0_TX_LOCKOUT Mask */ - -#define MXC_F_I2C_INTEN0_MAMI_POS 16 /**< INTEN0_MAMI Position */ -#define MXC_F_I2C_INTEN0_MAMI ((uint32_t)(0x3FUL << MXC_F_I2C_INTEN0_MAMI_POS)) /**< INTEN0_MAMI Mask */ - -#define MXC_F_I2C_INTEN0_RD_ADDR_MATCH_POS 22 /**< INTEN0_RD_ADDR_MATCH Position */ -#define MXC_F_I2C_INTEN0_RD_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_RD_ADDR_MATCH_POS)) /**< INTEN0_RD_ADDR_MATCH Mask */ - -#define MXC_F_I2C_INTEN0_WR_ADDR_MATCH_POS 23 /**< INTEN0_WR_ADDR_MATCH Position */ -#define MXC_F_I2C_INTEN0_WR_ADDR_MATCH ((uint32_t)(0x1UL << MXC_F_I2C_INTEN0_WR_ADDR_MATCH_POS)) /**< INTEN0_WR_ADDR_MATCH Mask */ - -/**@} end of group I2C_INTEN0_Register */ - -/** - * @ingroup i2c_registers - * @defgroup I2C_INTFL1 I2C_INTFL1 - * @brief Interrupt Status Register 1. - * @{ - */ -#define MXC_F_I2C_INTFL1_RX_OV_POS 0 /**< INTFL1_RX_OV Position */ -#define MXC_F_I2C_INTFL1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_RX_OV_POS)) /**< INTFL1_RX_OV Mask */ - -#define MXC_F_I2C_INTFL1_TX_UN_POS 1 /**< INTFL1_TX_UN Position */ -#define MXC_F_I2C_INTFL1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_TX_UN_POS)) /**< INTFL1_TX_UN Mask */ - -#define MXC_F_I2C_INTFL1_START_POS 2 /**< INTFL1_START Position */ -#define MXC_F_I2C_INTFL1_START ((uint32_t)(0x1UL << MXC_F_I2C_INTFL1_START_POS)) /**< INTFL1_START Mask */ - -/**@} end of group I2C_INTFL1_Register */ - -/** - * @ingroup i2c_registers - * @defgroup I2C_INTEN1 I2C_INTEN1 - * @brief Interrupt Staus Register 1. - * @{ - */ -#define MXC_F_I2C_INTEN1_RX_OV_POS 0 /**< INTEN1_RX_OV Position */ -#define MXC_F_I2C_INTEN1_RX_OV ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_RX_OV_POS)) /**< INTEN1_RX_OV Mask */ - -#define MXC_F_I2C_INTEN1_TX_UN_POS 1 /**< INTEN1_TX_UN Position */ -#define MXC_F_I2C_INTEN1_TX_UN ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_TX_UN_POS)) /**< INTEN1_TX_UN Mask */ - -#define MXC_F_I2C_INTEN1_START_POS 2 /**< INTEN1_START Position */ -#define MXC_F_I2C_INTEN1_START ((uint32_t)(0x1UL << MXC_F_I2C_INTEN1_START_POS)) /**< INTEN1_START Mask */ - -/**@} end of group I2C_INTEN1_Register */ - -/** - * @ingroup i2c_registers - * @defgroup I2C_FIFOLEN I2C_FIFOLEN - * @brief FIFO Configuration Register. - * @{ - */ -#define MXC_F_I2C_FIFOLEN_RX_DEPTH_POS 0 /**< FIFOLEN_RX_DEPTH Position */ -#define MXC_F_I2C_FIFOLEN_RX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_FIFOLEN_RX_DEPTH_POS)) /**< FIFOLEN_RX_DEPTH Mask */ - -#define MXC_F_I2C_FIFOLEN_TX_DEPTH_POS 8 /**< FIFOLEN_TX_DEPTH Position */ -#define MXC_F_I2C_FIFOLEN_TX_DEPTH ((uint32_t)(0xFFUL << MXC_F_I2C_FIFOLEN_TX_DEPTH_POS)) /**< FIFOLEN_TX_DEPTH Mask */ - -/**@} end of group I2C_FIFOLEN_Register */ - -/** - * @ingroup i2c_registers - * @defgroup I2C_RXCTRL0 I2C_RXCTRL0 - * @brief Receive Control Register 0. - * @{ - */ -#define MXC_F_I2C_RXCTRL0_DNR_POS 0 /**< RXCTRL0_DNR Position */ -#define MXC_F_I2C_RXCTRL0_DNR ((uint32_t)(0x1UL << MXC_F_I2C_RXCTRL0_DNR_POS)) /**< RXCTRL0_DNR Mask */ - -#define MXC_F_I2C_RXCTRL0_FLUSH_POS 7 /**< RXCTRL0_FLUSH Position */ -#define MXC_F_I2C_RXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_RXCTRL0_FLUSH_POS)) /**< RXCTRL0_FLUSH Mask */ - -#define MXC_F_I2C_RXCTRL0_THD_LVL_POS 8 /**< RXCTRL0_THD_LVL Position */ -#define MXC_F_I2C_RXCTRL0_THD_LVL ((uint32_t)(0xFUL << MXC_F_I2C_RXCTRL0_THD_LVL_POS)) /**< RXCTRL0_THD_LVL Mask */ - -/**@} end of group I2C_RXCTRL0_Register */ - -/** - * @ingroup i2c_registers - * @defgroup I2C_RXCTRL1 I2C_RXCTRL1 - * @brief Receive Control Register 1. - * @{ - */ -#define MXC_F_I2C_RXCTRL1_CNT_POS 0 /**< RXCTRL1_CNT Position */ -#define MXC_F_I2C_RXCTRL1_CNT ((uint32_t)(0xFFUL << MXC_F_I2C_RXCTRL1_CNT_POS)) /**< RXCTRL1_CNT Mask */ - -#define MXC_F_I2C_RXCTRL1_LVL_POS 8 /**< RXCTRL1_LVL Position */ -#define MXC_F_I2C_RXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_RXCTRL1_LVL_POS)) /**< RXCTRL1_LVL Mask */ - -/**@} end of group I2C_RXCTRL1_Register */ - -/** - * @ingroup i2c_registers - * @defgroup I2C_TXCTRL0 I2C_TXCTRL0 - * @brief Transmit Control Register 0. - * @{ - */ -#define MXC_F_I2C_TXCTRL0_PRELOAD_MODE_POS 0 /**< TXCTRL0_PRELOAD_MODE Position */ -#define MXC_F_I2C_TXCTRL0_PRELOAD_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_PRELOAD_MODE_POS)) /**< TXCTRL0_PRELOAD_MODE Mask */ - -#define MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS 1 /**< TXCTRL0_TX_READY_MODE Position */ -#define MXC_F_I2C_TXCTRL0_TX_READY_MODE ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_TX_READY_MODE_POS)) /**< TXCTRL0_TX_READY_MODE Mask */ - -#define MXC_F_I2C_TXCTRL0_GC_ADDR_FLUSH_DIS_POS 2 /**< TXCTRL0_GC_ADDR_FLUSH_DIS Position */ -#define MXC_F_I2C_TXCTRL0_GC_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_GC_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_GC_ADDR_FLUSH_DIS Mask */ - -#define MXC_F_I2C_TXCTRL0_WR_ADDR_FLUSH_DIS_POS 3 /**< TXCTRL0_WR_ADDR_FLUSH_DIS Position */ -#define MXC_F_I2C_TXCTRL0_WR_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_WR_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_WR_ADDR_FLUSH_DIS Mask */ - -#define MXC_F_I2C_TXCTRL0_RD_ADDR_FLUSH_DIS_POS 4 /**< TXCTRL0_RD_ADDR_FLUSH_DIS Position */ -#define MXC_F_I2C_TXCTRL0_RD_ADDR_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_RD_ADDR_FLUSH_DIS_POS)) /**< TXCTRL0_RD_ADDR_FLUSH_DIS Mask */ - -#define MXC_F_I2C_TXCTRL0_NACK_FLUSH_DIS_POS 5 /**< TXCTRL0_NACK_FLUSH_DIS Position */ -#define MXC_F_I2C_TXCTRL0_NACK_FLUSH_DIS ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_NACK_FLUSH_DIS_POS)) /**< TXCTRL0_NACK_FLUSH_DIS Mask */ - -#define MXC_F_I2C_TXCTRL0_FLUSH_POS 7 /**< TXCTRL0_FLUSH Position */ -#define MXC_F_I2C_TXCTRL0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL0_FLUSH_POS)) /**< TXCTRL0_FLUSH Mask */ - -#define MXC_F_I2C_TXCTRL0_THD_VAL_POS 8 /**< TXCTRL0_THD_VAL Position */ -#define MXC_F_I2C_TXCTRL0_THD_VAL ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL0_THD_VAL_POS)) /**< TXCTRL0_THD_VAL Mask */ - -/**@} end of group I2C_TXCTRL0_Register */ - -/** - * @ingroup i2c_registers - * @defgroup I2C_TXCTRL1 I2C_TXCTRL1 - * @brief Transmit Control Register 1. - * @{ - */ -#define MXC_F_I2C_TXCTRL1_PRELOAD_RDY_POS 0 /**< TXCTRL1_PRELOAD_RDY Position */ -#define MXC_F_I2C_TXCTRL1_PRELOAD_RDY ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_PRELOAD_RDY_POS)) /**< TXCTRL1_PRELOAD_RDY Mask */ - -#define MXC_F_I2C_TXCTRL1_LAST_POS 1 /**< TXCTRL1_LAST Position */ -#define MXC_F_I2C_TXCTRL1_LAST ((uint32_t)(0x1UL << MXC_F_I2C_TXCTRL1_LAST_POS)) /**< TXCTRL1_LAST Mask */ - -#define MXC_F_I2C_TXCTRL1_LVL_POS 8 /**< TXCTRL1_LVL Position */ -#define MXC_F_I2C_TXCTRL1_LVL ((uint32_t)(0xFUL << MXC_F_I2C_TXCTRL1_LVL_POS)) /**< TXCTRL1_LVL Mask */ - -/**@} end of group I2C_TXCTRL1_Register */ - -/** - * @ingroup i2c_registers - * @defgroup I2C_FIFO I2C_FIFO - * @brief Data Register. - * @{ - */ -#define MXC_F_I2C_FIFO_DATA_POS 0 /**< FIFO_DATA Position */ -#define MXC_F_I2C_FIFO_DATA ((uint32_t)(0xFFUL << MXC_F_I2C_FIFO_DATA_POS)) /**< FIFO_DATA Mask */ - -/**@} end of group I2C_FIFO_Register */ - -/** - * @ingroup i2c_registers - * @defgroup I2C_MSTCTRL I2C_MSTCTRL - * @brief Master Control Register. - * @{ - */ -#define MXC_F_I2C_MSTCTRL_START_POS 0 /**< MSTCTRL_START Position */ -#define MXC_F_I2C_MSTCTRL_START ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_START_POS)) /**< MSTCTRL_START Mask */ - -#define MXC_F_I2C_MSTCTRL_RESTART_POS 1 /**< MSTCTRL_RESTART Position */ -#define MXC_F_I2C_MSTCTRL_RESTART ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_RESTART_POS)) /**< MSTCTRL_RESTART Mask */ - -#define MXC_F_I2C_MSTCTRL_STOP_POS 2 /**< MSTCTRL_STOP Position */ -#define MXC_F_I2C_MSTCTRL_STOP ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_STOP_POS)) /**< MSTCTRL_STOP Mask */ - -#define MXC_F_I2C_MSTCTRL_EX_ADDR_EN_POS 7 /**< MSTCTRL_EX_ADDR_EN Position */ -#define MXC_F_I2C_MSTCTRL_EX_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_EX_ADDR_EN_POS)) /**< MSTCTRL_EX_ADDR_EN Mask */ - -#define MXC_F_I2C_MSTCTRL_CODE_POS 8 /**< MSTCTRL_CODE Position */ -#define MXC_F_I2C_MSTCTRL_CODE ((uint32_t)(0x7UL << MXC_F_I2C_MSTCTRL_CODE_POS)) /**< MSTCTRL_CODE Mask */ - -#define MXC_F_I2C_MSTCTRL_IGN_ACK_POS 12 /**< MSTCTRL_IGN_ACK Position */ -#define MXC_F_I2C_MSTCTRL_IGN_ACK ((uint32_t)(0x1UL << MXC_F_I2C_MSTCTRL_IGN_ACK_POS)) /**< MSTCTRL_IGN_ACK Mask */ - -/**@} end of group I2C_MSTCTRL_Register */ - -/** - * @ingroup i2c_registers - * @defgroup I2C_CLKLO I2C_CLKLO - * @brief Clock Low Register. - * @{ - */ -#define MXC_F_I2C_CLKLO_LO_POS 0 /**< CLKLO_LO Position */ -#define MXC_F_I2C_CLKLO_LO ((uint32_t)(0x1FFUL << MXC_F_I2C_CLKLO_LO_POS)) /**< CLKLO_LO Mask */ - -/**@} end of group I2C_CLKLO_Register */ - -/** - * @ingroup i2c_registers - * @defgroup I2C_CLKHI I2C_CLKHI - * @brief Clock high Register. - * @{ - */ -#define MXC_F_I2C_CLKHI_HI_POS 0 /**< CLKHI_HI Position */ -#define MXC_F_I2C_CLKHI_HI ((uint32_t)(0x1FFUL << MXC_F_I2C_CLKHI_HI_POS)) /**< CLKHI_HI Mask */ - -/**@} end of group I2C_CLKHI_Register */ - -/** - * @ingroup i2c_registers - * @defgroup I2C_HSCLK I2C_HSCLK - * @brief Clock high Register. - * @{ - */ -#define MXC_F_I2C_HSCLK_LO_POS 0 /**< HSCLK_LO Position */ -#define MXC_F_I2C_HSCLK_LO ((uint32_t)(0xFFUL << MXC_F_I2C_HSCLK_LO_POS)) /**< HSCLK_LO Mask */ - -#define MXC_F_I2C_HSCLK_HI_POS 8 /**< HSCLK_HI Position */ -#define MXC_F_I2C_HSCLK_HI ((uint32_t)(0xFFUL << MXC_F_I2C_HSCLK_HI_POS)) /**< HSCLK_HI Mask */ - -/**@} end of group I2C_HSCLK_Register */ - -/** - * @ingroup i2c_registers - * @defgroup I2C_TIMEOUT I2C_TIMEOUT - * @brief Timeout Register - * @{ - */ -#define MXC_F_I2C_TIMEOUT_SCL_TO_VAL_POS 0 /**< TIMEOUT_SCL_TO_VAL Position */ -#define MXC_F_I2C_TIMEOUT_SCL_TO_VAL ((uint32_t)(0xFFFFUL << MXC_F_I2C_TIMEOUT_SCL_TO_VAL_POS)) /**< TIMEOUT_SCL_TO_VAL Mask */ - -/**@} end of group I2C_TIMEOUT_Register */ - -/** - * @ingroup i2c_registers - * @defgroup I2C_DMA I2C_DMA - * @brief DMA Register. - * @{ - */ -#define MXC_F_I2C_DMA_TX_EN_POS 0 /**< DMA_TX_EN Position */ -#define MXC_F_I2C_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_TX_EN_POS)) /**< DMA_TX_EN Mask */ - -#define MXC_F_I2C_DMA_RX_EN_POS 1 /**< DMA_RX_EN Position */ -#define MXC_F_I2C_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_I2C_DMA_RX_EN_POS)) /**< DMA_RX_EN Mask */ - -/**@} end of group I2C_DMA_Register */ - -/** - * @ingroup i2c_registers - * @defgroup I2C_SLAVE_MULTI I2C_SLAVE_MULTI - * @brief Slave Address Register. - * @{ - */ -#define MXC_F_I2C_SLAVE_MULTI_ADDR_POS 0 /**< SLAVE_MULTI_ADDR Position */ -#define MXC_F_I2C_SLAVE_MULTI_ADDR ((uint32_t)(0x3FFUL << MXC_F_I2C_SLAVE_MULTI_ADDR_POS)) /**< SLAVE_MULTI_ADDR Mask */ - -#define MXC_F_I2C_SLAVE_MULTI_DIS_POS 10 /**< SLAVE_MULTI_DIS Position */ -#define MXC_F_I2C_SLAVE_MULTI_DIS ((uint32_t)(0x1UL << MXC_F_I2C_SLAVE_MULTI_DIS_POS)) /**< SLAVE_MULTI_DIS Mask */ - -#define MXC_F_I2C_SLAVE_MULTI_EXT_ADDR_EN_POS 15 /**< SLAVE_MULTI_EXT_ADDR_EN Position */ -#define MXC_F_I2C_SLAVE_MULTI_EXT_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I2C_SLAVE_MULTI_EXT_ADDR_EN_POS)) /**< SLAVE_MULTI_EXT_ADDR_EN Mask */ - -/**@} end of group I2C_SLAVE_MULTI_Register */ - -#ifdef __cplusplus -} -#endif - -#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_I2C_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/i2s_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/i2s_regs.h deleted file mode 100644 index a7fedc7b89c..00000000000 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/i2s_regs.h +++ /dev/null @@ -1,292 +0,0 @@ -/** - * @file i2s_regs.h - * @brief Registers, Bit Masks and Bit Positions for the I2S Peripheral Module. - * @note This file is @generated. - * @ingroup i2s_registers - */ - -/****************************************************************************** - * - * Analog Devices, Inc.), - * Copyright (C) 2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ******************************************************************************/ - -#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_I2S_REGS_H_ -#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_I2S_REGS_H_ - -/* **** Includes **** */ -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined (__ICCARM__) - #pragma system_include -#endif - -#if defined (__CC_ARM) - #pragma anon_unions -#endif -/// @cond -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif -#ifndef __R -#define __R volatile const -#endif -/// @endcond - -/* **** Definitions **** */ - -/** - * @ingroup i2s - * @defgroup i2s_registers I2S_Registers - * @brief Registers, Bit Masks and Bit Positions for the I2S Peripheral Module. - * @details Inter-IC Sound Interface. - */ - -/** - * @ingroup i2s_registers - * Structure type to access the I2S Registers. - */ -typedef struct { - __IO uint32_t ctrl0ch0; /**< \b 0x00: I2S CTRL0CH0 Register */ - __R uint32_t rsv_0x4_0xf[3]; - __IO uint32_t ctrl1ch0; /**< \b 0x10: I2S CTRL1CH0 Register */ - __R uint32_t rsv_0x14_0x1f[3]; - __IO uint32_t filtch0; /**< \b 0x20: I2S FILTCH0 Register */ - __R uint32_t rsv_0x24_0x2f[3]; - __IO uint32_t dmach0; /**< \b 0x30: I2S DMACH0 Register */ - __R uint32_t rsv_0x34_0x3f[3]; - __IO uint32_t fifoch0; /**< \b 0x40: I2S FIFOCH0 Register */ - __R uint32_t rsv_0x44_0x4f[3]; - __IO uint32_t intfl; /**< \b 0x50: I2S INTFL Register */ - __IO uint32_t inten; /**< \b 0x54: I2S INTEN Register */ - __IO uint32_t extsetup; /**< \b 0x58: I2S EXTSETUP Register */ - __IO uint32_t wken; /**< \b 0x5C: I2S WKEN Register */ - __IO uint32_t wkfl; /**< \b 0x60: I2S WKFL Register */ -} mxc_i2s_regs_t; - -/* Register offsets for module I2S */ -/** - * @ingroup i2s_registers - * @defgroup I2S_Register_Offsets Register Offsets - * @brief I2S Peripheral Register Offsets from the I2S Base Peripheral Address. - * @{ - */ -#define MXC_R_I2S_CTRL0CH0 ((uint32_t)0x00000000UL) /**< Offset from I2S Base Address: 0x0000 */ -#define MXC_R_I2S_CTRL1CH0 ((uint32_t)0x00000010UL) /**< Offset from I2S Base Address: 0x0010 */ -#define MXC_R_I2S_FILTCH0 ((uint32_t)0x00000020UL) /**< Offset from I2S Base Address: 0x0020 */ -#define MXC_R_I2S_DMACH0 ((uint32_t)0x00000030UL) /**< Offset from I2S Base Address: 0x0030 */ -#define MXC_R_I2S_FIFOCH0 ((uint32_t)0x00000040UL) /**< Offset from I2S Base Address: 0x0040 */ -#define MXC_R_I2S_INTFL ((uint32_t)0x00000050UL) /**< Offset from I2S Base Address: 0x0050 */ -#define MXC_R_I2S_INTEN ((uint32_t)0x00000054UL) /**< Offset from I2S Base Address: 0x0054 */ -#define MXC_R_I2S_EXTSETUP ((uint32_t)0x00000058UL) /**< Offset from I2S Base Address: 0x0058 */ -#define MXC_R_I2S_WKEN ((uint32_t)0x0000005CUL) /**< Offset from I2S Base Address: 0x005C */ -#define MXC_R_I2S_WKFL ((uint32_t)0x00000060UL) /**< Offset from I2S Base Address: 0x0060 */ -/**@} end of group i2s_registers */ - -/** - * @ingroup i2s_registers - * @defgroup I2S_CTRL0CH0 I2S_CTRL0CH0 - * @brief Global mode channel. - * @{ - */ -#define MXC_F_I2S_CTRL0CH0_LSB_FIRST_POS 1 /**< CTRL0CH0_LSB_FIRST Position */ -#define MXC_F_I2S_CTRL0CH0_LSB_FIRST ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_LSB_FIRST_POS)) /**< CTRL0CH0_LSB_FIRST Mask */ - -#define MXC_F_I2S_CTRL0CH0_PDM_FILT_POS 2 /**< CTRL0CH0_PDM_FILT Position */ -#define MXC_F_I2S_CTRL0CH0_PDM_FILT ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_PDM_FILT_POS)) /**< CTRL0CH0_PDM_FILT Mask */ - -#define MXC_F_I2S_CTRL0CH0_PDM_EN_POS 3 /**< CTRL0CH0_PDM_EN Position */ -#define MXC_F_I2S_CTRL0CH0_PDM_EN ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_PDM_EN_POS)) /**< CTRL0CH0_PDM_EN Mask */ - -#define MXC_F_I2S_CTRL0CH0_USEDDR_POS 4 /**< CTRL0CH0_USEDDR Position */ -#define MXC_F_I2S_CTRL0CH0_USEDDR ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_USEDDR_POS)) /**< CTRL0CH0_USEDDR Mask */ - -#define MXC_F_I2S_CTRL0CH0_PDM_INV_POS 5 /**< CTRL0CH0_PDM_INV Position */ -#define MXC_F_I2S_CTRL0CH0_PDM_INV ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_PDM_INV_POS)) /**< CTRL0CH0_PDM_INV Mask */ - -#define MXC_F_I2S_CTRL0CH0_CH_MODE_POS 6 /**< CTRL0CH0_CH_MODE Position */ -#define MXC_F_I2S_CTRL0CH0_CH_MODE ((uint32_t)(0x3UL << MXC_F_I2S_CTRL0CH0_CH_MODE_POS)) /**< CTRL0CH0_CH_MODE Mask */ - -#define MXC_F_I2S_CTRL0CH0_WS_POL_POS 8 /**< CTRL0CH0_WS_POL Position */ -#define MXC_F_I2S_CTRL0CH0_WS_POL ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_WS_POL_POS)) /**< CTRL0CH0_WS_POL Mask */ - -#define MXC_F_I2S_CTRL0CH0_MSB_LOC_POS 9 /**< CTRL0CH0_MSB_LOC Position */ -#define MXC_F_I2S_CTRL0CH0_MSB_LOC ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_MSB_LOC_POS)) /**< CTRL0CH0_MSB_LOC Mask */ - -#define MXC_F_I2S_CTRL0CH0_ALIGN_POS 10 /**< CTRL0CH0_ALIGN Position */ -#define MXC_F_I2S_CTRL0CH0_ALIGN ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_ALIGN_POS)) /**< CTRL0CH0_ALIGN Mask */ - -#define MXC_F_I2S_CTRL0CH0_EXT_SEL_POS 11 /**< CTRL0CH0_EXT_SEL Position */ -#define MXC_F_I2S_CTRL0CH0_EXT_SEL ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_EXT_SEL_POS)) /**< CTRL0CH0_EXT_SEL Mask */ - -#define MXC_F_I2S_CTRL0CH0_STEREO_POS 12 /**< CTRL0CH0_STEREO Position */ -#define MXC_F_I2S_CTRL0CH0_STEREO ((uint32_t)(0x3UL << MXC_F_I2S_CTRL0CH0_STEREO_POS)) /**< CTRL0CH0_STEREO Mask */ - -#define MXC_F_I2S_CTRL0CH0_WSIZE_POS 14 /**< CTRL0CH0_WSIZE Position */ -#define MXC_F_I2S_CTRL0CH0_WSIZE ((uint32_t)(0x3UL << MXC_F_I2S_CTRL0CH0_WSIZE_POS)) /**< CTRL0CH0_WSIZE Mask */ - -#define MXC_F_I2S_CTRL0CH0_TX_EN_POS 16 /**< CTRL0CH0_TX_EN Position */ -#define MXC_F_I2S_CTRL0CH0_TX_EN ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_TX_EN_POS)) /**< CTRL0CH0_TX_EN Mask */ - -#define MXC_F_I2S_CTRL0CH0_RX_EN_POS 17 /**< CTRL0CH0_RX_EN Position */ -#define MXC_F_I2S_CTRL0CH0_RX_EN ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_RX_EN_POS)) /**< CTRL0CH0_RX_EN Mask */ - -#define MXC_F_I2S_CTRL0CH0_FLUSH_POS 18 /**< CTRL0CH0_FLUSH Position */ -#define MXC_F_I2S_CTRL0CH0_FLUSH ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_FLUSH_POS)) /**< CTRL0CH0_FLUSH Mask */ - -#define MXC_F_I2S_CTRL0CH0_RST_POS 19 /**< CTRL0CH0_RST Position */ -#define MXC_F_I2S_CTRL0CH0_RST ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_RST_POS)) /**< CTRL0CH0_RST Mask */ - -#define MXC_F_I2S_CTRL0CH0_FIFO_LSB_POS 20 /**< CTRL0CH0_FIFO_LSB Position */ -#define MXC_F_I2S_CTRL0CH0_FIFO_LSB ((uint32_t)(0x1UL << MXC_F_I2S_CTRL0CH0_FIFO_LSB_POS)) /**< CTRL0CH0_FIFO_LSB Mask */ - -#define MXC_F_I2S_CTRL0CH0_RX_THD_VAL_POS 24 /**< CTRL0CH0_RX_THD_VAL Position */ -#define MXC_F_I2S_CTRL0CH0_RX_THD_VAL ((uint32_t)(0xFFUL << MXC_F_I2S_CTRL0CH0_RX_THD_VAL_POS)) /**< CTRL0CH0_RX_THD_VAL Mask */ - -/**@} end of group I2S_CTRL0CH0_Register */ - -/** - * @ingroup i2s_registers - * @defgroup I2S_CTRL1CH0 I2S_CTRL1CH0 - * @brief Local channel Setup. - * @{ - */ -#define MXC_F_I2S_CTRL1CH0_BITS_WORD_POS 0 /**< CTRL1CH0_BITS_WORD Position */ -#define MXC_F_I2S_CTRL1CH0_BITS_WORD ((uint32_t)(0x1FUL << MXC_F_I2S_CTRL1CH0_BITS_WORD_POS)) /**< CTRL1CH0_BITS_WORD Mask */ - -#define MXC_F_I2S_CTRL1CH0_EN_POS 8 /**< CTRL1CH0_EN Position */ -#define MXC_F_I2S_CTRL1CH0_EN ((uint32_t)(0x1UL << MXC_F_I2S_CTRL1CH0_EN_POS)) /**< CTRL1CH0_EN Mask */ - -#define MXC_F_I2S_CTRL1CH0_SMP_SIZE_POS 9 /**< CTRL1CH0_SMP_SIZE Position */ -#define MXC_F_I2S_CTRL1CH0_SMP_SIZE ((uint32_t)(0x1FUL << MXC_F_I2S_CTRL1CH0_SMP_SIZE_POS)) /**< CTRL1CH0_SMP_SIZE Mask */ - -#define MXC_F_I2S_CTRL1CH0_CLKSEL_POS 14 /**< CTRL1CH0_CLKSEL Position */ -#define MXC_F_I2S_CTRL1CH0_CLKSEL ((uint32_t)(0x1UL << MXC_F_I2S_CTRL1CH0_CLKSEL_POS)) /**< CTRL1CH0_CLKSEL Mask */ - -#define MXC_F_I2S_CTRL1CH0_ADJUST_POS 15 /**< CTRL1CH0_ADJUST Position */ -#define MXC_F_I2S_CTRL1CH0_ADJUST ((uint32_t)(0x1UL << MXC_F_I2S_CTRL1CH0_ADJUST_POS)) /**< CTRL1CH0_ADJUST Mask */ - -#define MXC_F_I2S_CTRL1CH0_CLKDIV_POS 16 /**< CTRL1CH0_CLKDIV Position */ -#define MXC_F_I2S_CTRL1CH0_CLKDIV ((uint32_t)(0xFFFFUL << MXC_F_I2S_CTRL1CH0_CLKDIV_POS)) /**< CTRL1CH0_CLKDIV Mask */ - -/**@} end of group I2S_CTRL1CH0_Register */ - -/** - * @ingroup i2s_registers - * @defgroup I2S_DMACH0 I2S_DMACH0 - * @brief DMA Control. - * @{ - */ -#define MXC_F_I2S_DMACH0_DMA_TX_THD_VAL_POS 0 /**< DMACH0_DMA_TX_THD_VAL Position */ -#define MXC_F_I2S_DMACH0_DMA_TX_THD_VAL ((uint32_t)(0x7FUL << MXC_F_I2S_DMACH0_DMA_TX_THD_VAL_POS)) /**< DMACH0_DMA_TX_THD_VAL Mask */ - -#define MXC_F_I2S_DMACH0_DMA_TX_EN_POS 7 /**< DMACH0_DMA_TX_EN Position */ -#define MXC_F_I2S_DMACH0_DMA_TX_EN ((uint32_t)(0x1UL << MXC_F_I2S_DMACH0_DMA_TX_EN_POS)) /**< DMACH0_DMA_TX_EN Mask */ - -#define MXC_F_I2S_DMACH0_DMA_RX_THD_VAL_POS 8 /**< DMACH0_DMA_RX_THD_VAL Position */ -#define MXC_F_I2S_DMACH0_DMA_RX_THD_VAL ((uint32_t)(0x7FUL << MXC_F_I2S_DMACH0_DMA_RX_THD_VAL_POS)) /**< DMACH0_DMA_RX_THD_VAL Mask */ - -#define MXC_F_I2S_DMACH0_DMA_RX_EN_POS 15 /**< DMACH0_DMA_RX_EN Position */ -#define MXC_F_I2S_DMACH0_DMA_RX_EN ((uint32_t)(0x1UL << MXC_F_I2S_DMACH0_DMA_RX_EN_POS)) /**< DMACH0_DMA_RX_EN Mask */ - -#define MXC_F_I2S_DMACH0_TX_LVL_POS 16 /**< DMACH0_TX_LVL Position */ -#define MXC_F_I2S_DMACH0_TX_LVL ((uint32_t)(0xFFUL << MXC_F_I2S_DMACH0_TX_LVL_POS)) /**< DMACH0_TX_LVL Mask */ - -#define MXC_F_I2S_DMACH0_RX_LVL_POS 24 /**< DMACH0_RX_LVL Position */ -#define MXC_F_I2S_DMACH0_RX_LVL ((uint32_t)(0xFFUL << MXC_F_I2S_DMACH0_RX_LVL_POS)) /**< DMACH0_RX_LVL Mask */ - -/**@} end of group I2S_DMACH0_Register */ - -/** - * @ingroup i2s_registers - * @defgroup I2S_FIFOCH0 I2S_FIFOCH0 - * @brief I2S Fifo. - * @{ - */ -#define MXC_F_I2S_FIFOCH0_DATA_POS 0 /**< FIFOCH0_DATA Position */ -#define MXC_F_I2S_FIFOCH0_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_I2S_FIFOCH0_DATA_POS)) /**< FIFOCH0_DATA Mask */ - -/**@} end of group I2S_FIFOCH0_Register */ - -/** - * @ingroup i2s_registers - * @defgroup I2S_INTFL I2S_INTFL - * @brief ISR Status. - * @{ - */ -#define MXC_F_I2S_INTFL_RX_OV_CH0_POS 0 /**< INTFL_RX_OV_CH0 Position */ -#define MXC_F_I2S_INTFL_RX_OV_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_RX_OV_CH0_POS)) /**< INTFL_RX_OV_CH0 Mask */ - -#define MXC_F_I2S_INTFL_RX_THD_CH0_POS 1 /**< INTFL_RX_THD_CH0 Position */ -#define MXC_F_I2S_INTFL_RX_THD_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_RX_THD_CH0_POS)) /**< INTFL_RX_THD_CH0 Mask */ - -#define MXC_F_I2S_INTFL_TX_OB_CH0_POS 2 /**< INTFL_TX_OB_CH0 Position */ -#define MXC_F_I2S_INTFL_TX_OB_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_TX_OB_CH0_POS)) /**< INTFL_TX_OB_CH0 Mask */ - -#define MXC_F_I2S_INTFL_TX_HE_CH0_POS 3 /**< INTFL_TX_HE_CH0 Position */ -#define MXC_F_I2S_INTFL_TX_HE_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTFL_TX_HE_CH0_POS)) /**< INTFL_TX_HE_CH0 Mask */ - -/**@} end of group I2S_INTFL_Register */ - -/** - * @ingroup i2s_registers - * @defgroup I2S_INTEN I2S_INTEN - * @brief Interrupt Enable. - * @{ - */ -#define MXC_F_I2S_INTEN_RX_OV_CH0_POS 0 /**< INTEN_RX_OV_CH0 Position */ -#define MXC_F_I2S_INTEN_RX_OV_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTEN_RX_OV_CH0_POS)) /**< INTEN_RX_OV_CH0 Mask */ - -#define MXC_F_I2S_INTEN_RX_THD_CH0_POS 1 /**< INTEN_RX_THD_CH0 Position */ -#define MXC_F_I2S_INTEN_RX_THD_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTEN_RX_THD_CH0_POS)) /**< INTEN_RX_THD_CH0 Mask */ - -#define MXC_F_I2S_INTEN_TX_OB_CH0_POS 2 /**< INTEN_TX_OB_CH0 Position */ -#define MXC_F_I2S_INTEN_TX_OB_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTEN_TX_OB_CH0_POS)) /**< INTEN_TX_OB_CH0 Mask */ - -#define MXC_F_I2S_INTEN_TX_HE_CH0_POS 3 /**< INTEN_TX_HE_CH0 Position */ -#define MXC_F_I2S_INTEN_TX_HE_CH0 ((uint32_t)(0x1UL << MXC_F_I2S_INTEN_TX_HE_CH0_POS)) /**< INTEN_TX_HE_CH0 Mask */ - -/**@} end of group I2S_INTEN_Register */ - -/** - * @ingroup i2s_registers - * @defgroup I2S_EXTSETUP I2S_EXTSETUP - * @brief Ext Control. - * @{ - */ -#define MXC_F_I2S_EXTSETUP_EXT_BITS_WORD_POS 0 /**< EXTSETUP_EXT_BITS_WORD Position */ -#define MXC_F_I2S_EXTSETUP_EXT_BITS_WORD ((uint32_t)(0x1FUL << MXC_F_I2S_EXTSETUP_EXT_BITS_WORD_POS)) /**< EXTSETUP_EXT_BITS_WORD Mask */ - -/**@} end of group I2S_EXTSETUP_Register */ - -#ifdef __cplusplus -} -#endif - -#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_I2S_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/lpcmp_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/lpcmp_regs.h deleted file mode 100644 index 209995cb182..00000000000 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/lpcmp_regs.h +++ /dev/null @@ -1,115 +0,0 @@ -/** - * @file lpcmp_regs.h - * @brief Registers, Bit Masks and Bit Positions for the LPCMP Peripheral Module. - * @note This file is @generated. - * @ingroup lpcmp_registers - */ - -/****************************************************************************** - * - * Copyright (C) 2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ******************************************************************************/ - -#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_LPCMP_REGS_H_ -#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_LPCMP_REGS_H_ - -/* **** Includes **** */ -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined (__ICCARM__) - #pragma system_include -#endif - -#if defined (__CC_ARM) - #pragma anon_unions -#endif -/// @cond -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif -#ifndef __R -#define __R volatile const -#endif -/// @endcond - -/* **** Definitions **** */ - -/** - * @ingroup lpcmp - * @defgroup lpcmp_registers LPCMP_Registers - * @brief Registers, Bit Masks and Bit Positions for the LPCMP Peripheral Module. - * @details Low Power Comparator - */ - -/** - * @ingroup lpcmp_registers - * Structure type to access the LPCMP Registers. - */ -typedef struct { - __IO uint32_t ctrl[3]; /**< \b 0x00: LPCMP CTRL Register */ -} mxc_lpcmp_regs_t; - -/* Register offsets for module LPCMP */ -/** - * @ingroup lpcmp_registers - * @defgroup LPCMP_Register_Offsets Register Offsets - * @brief LPCMP Peripheral Register Offsets from the LPCMP Base Peripheral Address. - * @{ - */ -#define MXC_R_LPCMP_CTRL ((uint32_t)0x00000000UL) /**< Offset from LPCMP Base Address: 0x0000 */ -/**@} end of group lpcmp_registers */ - -/** - * @ingroup lpcmp_registers - * @defgroup LPCMP_CTRL LPCMP_CTRL - * @brief Comparator Control Register. - * @{ - */ -#define MXC_F_LPCMP_CTRL_EN_POS 0 /**< CTRL_EN Position */ -#define MXC_F_LPCMP_CTRL_EN ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_EN_POS)) /**< CTRL_EN Mask */ - -#define MXC_F_LPCMP_CTRL_POL_POS 5 /**< CTRL_POL Position */ -#define MXC_F_LPCMP_CTRL_POL ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_POL_POS)) /**< CTRL_POL Mask */ - -#define MXC_F_LPCMP_CTRL_INTR_EN_POS 6 /**< CTRL_INTR_EN Position */ -#define MXC_F_LPCMP_CTRL_INTR_EN ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_INTR_EN_POS)) /**< CTRL_INTR_EN Mask */ - -#define MXC_F_LPCMP_CTRL_OUT_POS 14 /**< CTRL_OUT Position */ -#define MXC_F_LPCMP_CTRL_OUT ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_OUT_POS)) /**< CTRL_OUT Mask */ - -#define MXC_F_LPCMP_CTRL_INTR_FL_POS 15 /**< CTRL_INTR_FL Position */ -#define MXC_F_LPCMP_CTRL_INTR_FL ((uint32_t)(0x1UL << MXC_F_LPCMP_CTRL_INTR_FL_POS)) /**< CTRL_INTR_FL Mask */ - -/**@} end of group LPCMP_CTRL_Register */ - -#ifdef __cplusplus -} -#endif - -#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_LPCMP_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/lpgcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/lpgcr_regs.h deleted file mode 100644 index 3c2208e5125..00000000000 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/lpgcr_regs.h +++ /dev/null @@ -1,148 +0,0 @@ -/** - * @file lpgcr_regs.h - * @brief Registers, Bit Masks and Bit Positions for the LPGCR Peripheral Module. - * @note This file is @generated. - * @ingroup lpgcr_registers - */ - -/****************************************************************************** - * - * Analog Devices, Inc.), - * Copyright (C) 2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ******************************************************************************/ - -#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_LPGCR_REGS_H_ -#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_LPGCR_REGS_H_ - -/* **** Includes **** */ -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined (__ICCARM__) - #pragma system_include -#endif - -#if defined (__CC_ARM) - #pragma anon_unions -#endif -/// @cond -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif -#ifndef __R -#define __R volatile const -#endif -/// @endcond - -/* **** Definitions **** */ - -/** - * @ingroup lpgcr - * @defgroup lpgcr_registers LPGCR_Registers - * @brief Registers, Bit Masks and Bit Positions for the LPGCR Peripheral Module. - * @details Low Power Global Control. - */ - -/** - * @ingroup lpgcr_registers - * Structure type to access the LPGCR Registers. - */ -typedef struct { - __R uint32_t rsv_0x0_0x7[2]; - __IO uint32_t rst; /**< \b 0x08: LPGCR RST Register */ - __IO uint32_t pclkdis; /**< \b 0x0C: LPGCR PCLKDIS Register */ -} mxc_lpgcr_regs_t; - -/* Register offsets for module LPGCR */ -/** - * @ingroup lpgcr_registers - * @defgroup LPGCR_Register_Offsets Register Offsets - * @brief LPGCR Peripheral Register Offsets from the LPGCR Base Peripheral Address. - * @{ - */ -#define MXC_R_LPGCR_RST ((uint32_t)0x00000008UL) /**< Offset from LPGCR Base Address: 0x0008 */ -#define MXC_R_LPGCR_PCLKDIS ((uint32_t)0x0000000CUL) /**< Offset from LPGCR Base Address: 0x000C */ -/**@} end of group lpgcr_registers */ - -/** - * @ingroup lpgcr_registers - * @defgroup LPGCR_RST LPGCR_RST - * @brief Low Power Reset Register. - * @{ - */ -#define MXC_F_LPGCR_RST_GPIO2_POS 0 /**< RST_GPIO2 Position */ -#define MXC_F_LPGCR_RST_GPIO2 ((uint32_t)(0x1UL << MXC_F_LPGCR_RST_GPIO2_POS)) /**< RST_GPIO2 Mask */ - -#define MXC_F_LPGCR_RST_WDT1_POS 1 /**< RST_WDT1 Position */ -#define MXC_F_LPGCR_RST_WDT1 ((uint32_t)(0x1UL << MXC_F_LPGCR_RST_WDT1_POS)) /**< RST_WDT1 Mask */ - -#define MXC_F_LPGCR_RST_TMR4_POS 2 /**< RST_TMR4 Position */ -#define MXC_F_LPGCR_RST_TMR4 ((uint32_t)(0x1UL << MXC_F_LPGCR_RST_TMR4_POS)) /**< RST_TMR4 Mask */ - -#define MXC_F_LPGCR_RST_TMR5_POS 3 /**< RST_TMR5 Position */ -#define MXC_F_LPGCR_RST_TMR5 ((uint32_t)(0x1UL << MXC_F_LPGCR_RST_TMR5_POS)) /**< RST_TMR5 Mask */ - -#define MXC_F_LPGCR_RST_UART3_POS 4 /**< RST_UART3 Position */ -#define MXC_F_LPGCR_RST_UART3 ((uint32_t)(0x1UL << MXC_F_LPGCR_RST_UART3_POS)) /**< RST_UART3 Mask */ - -#define MXC_F_LPGCR_RST_LPCOMP_POS 6 /**< RST_LPCOMP Position */ -#define MXC_F_LPGCR_RST_LPCOMP ((uint32_t)(0x1UL << MXC_F_LPGCR_RST_LPCOMP_POS)) /**< RST_LPCOMP Mask */ - -/**@} end of group LPGCR_RST_Register */ - -/** - * @ingroup lpgcr_registers - * @defgroup LPGCR_PCLKDIS LPGCR_PCLKDIS - * @brief Low Power Peripheral Clock Disable Register. - * @{ - */ -#define MXC_F_LPGCR_PCLKDIS_GPIO2_POS 0 /**< PCLKDIS_GPIO2 Position */ -#define MXC_F_LPGCR_PCLKDIS_GPIO2 ((uint32_t)(0x1UL << MXC_F_LPGCR_PCLKDIS_GPIO2_POS)) /**< PCLKDIS_GPIO2 Mask */ - -#define MXC_F_LPGCR_PCLKDIS_WDT1_POS 1 /**< PCLKDIS_WDT1 Position */ -#define MXC_F_LPGCR_PCLKDIS_WDT1 ((uint32_t)(0x1UL << MXC_F_LPGCR_PCLKDIS_WDT1_POS)) /**< PCLKDIS_WDT1 Mask */ - -#define MXC_F_LPGCR_PCLKDIS_TMR4_POS 2 /**< PCLKDIS_TMR4 Position */ -#define MXC_F_LPGCR_PCLKDIS_TMR4 ((uint32_t)(0x1UL << MXC_F_LPGCR_PCLKDIS_TMR4_POS)) /**< PCLKDIS_TMR4 Mask */ - -#define MXC_F_LPGCR_PCLKDIS_TMR5_POS 3 /**< PCLKDIS_TMR5 Position */ -#define MXC_F_LPGCR_PCLKDIS_TMR5 ((uint32_t)(0x1UL << MXC_F_LPGCR_PCLKDIS_TMR5_POS)) /**< PCLKDIS_TMR5 Mask */ - -#define MXC_F_LPGCR_PCLKDIS_UART3_POS 4 /**< PCLKDIS_UART3 Position */ -#define MXC_F_LPGCR_PCLKDIS_UART3 ((uint32_t)(0x1UL << MXC_F_LPGCR_PCLKDIS_UART3_POS)) /**< PCLKDIS_UART3 Mask */ - -#define MXC_F_LPGCR_PCLKDIS_LPCOMP_POS 6 /**< PCLKDIS_LPCOMP Position */ -#define MXC_F_LPGCR_PCLKDIS_LPCOMP ((uint32_t)(0x1UL << MXC_F_LPGCR_PCLKDIS_LPCOMP_POS)) /**< PCLKDIS_LPCOMP Mask */ - -/**@} end of group LPGCR_PCLKDIS_Register */ - -#ifdef __cplusplus -} -#endif - -#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_LPGCR_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/owm_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/owm_regs.h deleted file mode 100644 index 4255e2b88fa..00000000000 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/owm_regs.h +++ /dev/null @@ -1,229 +0,0 @@ -/** - * @file owm_regs.h - * @brief Registers, Bit Masks and Bit Positions for the OWM Peripheral Module. - * @note This file is @generated. - * @ingroup owm_registers - */ - -/****************************************************************************** - * - * Analog Devices, Inc.), - * Copyright (C) 2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ******************************************************************************/ - -#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_OWM_REGS_H_ -#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_OWM_REGS_H_ - -/* **** Includes **** */ -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined (__ICCARM__) - #pragma system_include -#endif - -#if defined (__CC_ARM) - #pragma anon_unions -#endif -/// @cond -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif -#ifndef __R -#define __R volatile const -#endif -/// @endcond - -/* **** Definitions **** */ - -/** - * @ingroup owm - * @defgroup owm_registers OWM_Registers - * @brief Registers, Bit Masks and Bit Positions for the OWM Peripheral Module. - * @details 1-Wire Master Interface. - */ - -/** - * @ingroup owm_registers - * Structure type to access the OWM Registers. - */ -typedef struct { - __IO uint32_t ctrl0; /**< \b 0x0000: OWM CTRL0 Register */ - __IO uint32_t clkdiv; /**< \b 0x0004: OWM CLKDIV Register */ - __IO uint32_t ctrl1; /**< \b 0x0008: OWM CTRL1 Register */ - __IO uint32_t data; /**< \b 0x000C: OWM DATA Register */ - __IO uint32_t intfl; /**< \b 0x0010: OWM INTFL Register */ - __IO uint32_t inten; /**< \b 0x0014: OWM INTEN Register */ -} mxc_owm_regs_t; - -/* Register offsets for module OWM */ -/** - * @ingroup owm_registers - * @defgroup OWM_Register_Offsets Register Offsets - * @brief OWM Peripheral Register Offsets from the OWM Base Peripheral Address. - * @{ - */ -#define MXC_R_OWM_CTRL0 ((uint32_t)0x00000000UL) /**< Offset from OWM Base Address: 0x0000 */ -#define MXC_R_OWM_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from OWM Base Address: 0x0004 */ -#define MXC_R_OWM_CTRL1 ((uint32_t)0x00000008UL) /**< Offset from OWM Base Address: 0x0008 */ -#define MXC_R_OWM_DATA ((uint32_t)0x0000000CUL) /**< Offset from OWM Base Address: 0x000C */ -#define MXC_R_OWM_INTFL ((uint32_t)0x00000010UL) /**< Offset from OWM Base Address: 0x0010 */ -#define MXC_R_OWM_INTEN ((uint32_t)0x00000014UL) /**< Offset from OWM Base Address: 0x0014 */ -/**@} end of group owm_registers */ - -/** - * @ingroup owm_registers - * @defgroup OWM_CTRL0 OWM_CTRL0 - * @brief 1-Wire Master Control Register. - * @{ - */ -#define MXC_F_OWM_CTRL0_LL_EN_POS 0 /**< CTRL0_LL_EN Position */ -#define MXC_F_OWM_CTRL0_LL_EN ((uint32_t)(0x1UL << MXC_F_OWM_CTRL0_LL_EN_POS)) /**< CTRL0_LL_EN Mask */ - -#define MXC_F_OWM_CTRL0_FPRESDET_POS 1 /**< CTRL0_FPRESDET Position */ -#define MXC_F_OWM_CTRL0_FPRESDET ((uint32_t)(0x1UL << MXC_F_OWM_CTRL0_FPRESDET_POS)) /**< CTRL0_FPRESDET Mask */ - -#define MXC_F_OWM_CTRL0_BB_EN_POS 2 /**< CTRL0_BB_EN Position */ -#define MXC_F_OWM_CTRL0_BB_EN ((uint32_t)(0x1UL << MXC_F_OWM_CTRL0_BB_EN_POS)) /**< CTRL0_BB_EN Mask */ - -#define MXC_F_OWM_CTRL0_EXT_PU_MODE_POS 3 /**< CTRL0_EXT_PU_MODE Position */ -#define MXC_F_OWM_CTRL0_EXT_PU_MODE ((uint32_t)(0x1UL << MXC_F_OWM_CTRL0_EXT_PU_MODE_POS)) /**< CTRL0_EXT_PU_MODE Mask */ - -#define MXC_F_OWM_CTRL0_EXT_PU_EN_POS 4 /**< CTRL0_EXT_PU_EN Position */ -#define MXC_F_OWM_CTRL0_EXT_PU_EN ((uint32_t)(0x1UL << MXC_F_OWM_CTRL0_EXT_PU_EN_POS)) /**< CTRL0_EXT_PU_EN Mask */ - -#define MXC_F_OWM_CTRL0_SB_EN_POS 5 /**< CTRL0_SB_EN Position */ -#define MXC_F_OWM_CTRL0_SB_EN ((uint32_t)(0x1UL << MXC_F_OWM_CTRL0_SB_EN_POS)) /**< CTRL0_SB_EN Mask */ - -#define MXC_F_OWM_CTRL0_OD_POS 6 /**< CTRL0_OD Position */ -#define MXC_F_OWM_CTRL0_OD ((uint32_t)(0x1UL << MXC_F_OWM_CTRL0_OD_POS)) /**< CTRL0_OD Mask */ - -#define MXC_F_OWM_CTRL0_INT_PU_EN_POS 7 /**< CTRL0_INT_PU_EN Position */ -#define MXC_F_OWM_CTRL0_INT_PU_EN ((uint32_t)(0x1UL << MXC_F_OWM_CTRL0_INT_PU_EN_POS)) /**< CTRL0_INT_PU_EN Mask */ - -/**@} end of group OWM_CTRL0_Register */ - -/** - * @ingroup owm_registers - * @defgroup OWM_CLKDIV OWM_CLKDIV - * @brief 1-Wire Master Clock Divisor. - * @{ - */ -#define MXC_F_OWM_CLKDIV_DIVISOR_POS 0 /**< CLKDIV_DIVISOR Position */ -#define MXC_F_OWM_CLKDIV_DIVISOR ((uint32_t)(0xFFUL << MXC_F_OWM_CLKDIV_DIVISOR_POS)) /**< CLKDIV_DIVISOR Mask */ - -/**@} end of group OWM_CLKDIV_Register */ - -/** - * @ingroup owm_registers - * @defgroup OWM_CTRL1 OWM_CTRL1 - * @brief 1-Wire Master Control/Status. - * @{ - */ -#define MXC_F_OWM_CTRL1_RST_POS 0 /**< CTRL1_RST Position */ -#define MXC_F_OWM_CTRL1_RST ((uint32_t)(0x1UL << MXC_F_OWM_CTRL1_RST_POS)) /**< CTRL1_RST Mask */ - -#define MXC_F_OWM_CTRL1_SRA_EN_POS 1 /**< CTRL1_SRA_EN Position */ -#define MXC_F_OWM_CTRL1_SRA_EN ((uint32_t)(0x1UL << MXC_F_OWM_CTRL1_SRA_EN_POS)) /**< CTRL1_SRA_EN Mask */ - -#define MXC_F_OWM_CTRL1_BB_OUT_EN_POS 2 /**< CTRL1_BB_OUT_EN Position */ -#define MXC_F_OWM_CTRL1_BB_OUT_EN ((uint32_t)(0x1UL << MXC_F_OWM_CTRL1_BB_OUT_EN_POS)) /**< CTRL1_BB_OUT_EN Mask */ - -#define MXC_F_OWM_CTRL1_INPUT_ST_POS 3 /**< CTRL1_INPUT_ST Position */ -#define MXC_F_OWM_CTRL1_INPUT_ST ((uint32_t)(0x1UL << MXC_F_OWM_CTRL1_INPUT_ST_POS)) /**< CTRL1_INPUT_ST Mask */ - -#define MXC_F_OWM_CTRL1_OD_SPEC_ST_POS 4 /**< CTRL1_OD_SPEC_ST Position */ -#define MXC_F_OWM_CTRL1_OD_SPEC_ST ((uint32_t)(0x1UL << MXC_F_OWM_CTRL1_OD_SPEC_ST_POS)) /**< CTRL1_OD_SPEC_ST Mask */ - -#define MXC_F_OWM_CTRL1_PRESDET_ST_POS 7 /**< CTRL1_PRESDET_ST Position */ -#define MXC_F_OWM_CTRL1_PRESDET_ST ((uint32_t)(0x1UL << MXC_F_OWM_CTRL1_PRESDET_ST_POS)) /**< CTRL1_PRESDET_ST Mask */ - -/**@} end of group OWM_CTRL1_Register */ - -/** - * @ingroup owm_registers - * @defgroup OWM_DATA OWM_DATA - * @brief 1-Wire Master Data Buffer. - * @{ - */ -#define MXC_F_OWM_DATA_DATA_POS 0 /**< DATA_DATA Position */ -#define MXC_F_OWM_DATA_DATA ((uint32_t)(0xFFUL << MXC_F_OWM_DATA_DATA_POS)) /**< DATA_DATA Mask */ - -/**@} end of group OWM_DATA_Register */ - -/** - * @ingroup owm_registers - * @defgroup OWM_INTFL OWM_INTFL - * @brief 1-Wire Master Interrupt Flags. - * @{ - */ -#define MXC_F_OWM_INTFL_RST_DONE_POS 0 /**< INTFL_RST_DONE Position */ -#define MXC_F_OWM_INTFL_RST_DONE ((uint32_t)(0x1UL << MXC_F_OWM_INTFL_RST_DONE_POS)) /**< INTFL_RST_DONE Mask */ - -#define MXC_F_OWM_INTFL_TX_EM_POS 1 /**< INTFL_TX_EM Position */ -#define MXC_F_OWM_INTFL_TX_EM ((uint32_t)(0x1UL << MXC_F_OWM_INTFL_TX_EM_POS)) /**< INTFL_TX_EM Mask */ - -#define MXC_F_OWM_INTFL_RX_RDY_POS 2 /**< INTFL_RX_RDY Position */ -#define MXC_F_OWM_INTFL_RX_RDY ((uint32_t)(0x1UL << MXC_F_OWM_INTFL_RX_RDY_POS)) /**< INTFL_RX_RDY Mask */ - -#define MXC_F_OWM_INTFL_LINE_SHORT_POS 3 /**< INTFL_LINE_SHORT Position */ -#define MXC_F_OWM_INTFL_LINE_SHORT ((uint32_t)(0x1UL << MXC_F_OWM_INTFL_LINE_SHORT_POS)) /**< INTFL_LINE_SHORT Mask */ - -#define MXC_F_OWM_INTFL_LINE_LOW_POS 4 /**< INTFL_LINE_LOW Position */ -#define MXC_F_OWM_INTFL_LINE_LOW ((uint32_t)(0x1UL << MXC_F_OWM_INTFL_LINE_LOW_POS)) /**< INTFL_LINE_LOW Mask */ - -/**@} end of group OWM_INTFL_Register */ - -/** - * @ingroup owm_registers - * @defgroup OWM_INTEN OWM_INTEN - * @brief 1-Wire Master Interrupt Enables. - * @{ - */ -#define MXC_F_OWM_INTEN_RST_DONE_POS 0 /**< INTEN_RST_DONE Position */ -#define MXC_F_OWM_INTEN_RST_DONE ((uint32_t)(0x1UL << MXC_F_OWM_INTEN_RST_DONE_POS)) /**< INTEN_RST_DONE Mask */ - -#define MXC_F_OWM_INTEN_TX_EM_POS 1 /**< INTEN_TX_EM Position */ -#define MXC_F_OWM_INTEN_TX_EM ((uint32_t)(0x1UL << MXC_F_OWM_INTEN_TX_EM_POS)) /**< INTEN_TX_EM Mask */ - -#define MXC_F_OWM_INTEN_RX_RDY_POS 2 /**< INTEN_RX_RDY Position */ -#define MXC_F_OWM_INTEN_RX_RDY ((uint32_t)(0x1UL << MXC_F_OWM_INTEN_RX_RDY_POS)) /**< INTEN_RX_RDY Mask */ - -#define MXC_F_OWM_INTEN_LINE_SHORT_POS 3 /**< INTEN_LINE_SHORT Position */ -#define MXC_F_OWM_INTEN_LINE_SHORT ((uint32_t)(0x1UL << MXC_F_OWM_INTEN_LINE_SHORT_POS)) /**< INTEN_LINE_SHORT Mask */ - -#define MXC_F_OWM_INTEN_LINE_LOW_POS 4 /**< INTEN_LINE_LOW Position */ -#define MXC_F_OWM_INTEN_LINE_LOW ((uint32_t)(0x1UL << MXC_F_OWM_INTEN_LINE_LOW_POS)) /**< INTEN_LINE_LOW Mask */ - -/**@} end of group OWM_INTEN_Register */ - -#ifdef __cplusplus -} -#endif - -#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_OWM_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/pt_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/pt_regs.h deleted file mode 100644 index 7ad2723ef21..00000000000 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/pt_regs.h +++ /dev/null @@ -1,211 +0,0 @@ -/** - * @file pt_regs.h - * @brief Registers, Bit Masks and Bit Positions for the PT Peripheral Module. - * @note This file is @generated. - * @ingroup pt_registers - */ - -/****************************************************************************** - * - * Analog Devices, Inc.), - * Copyright (C) 2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ******************************************************************************/ - -#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_PT_REGS_H_ -#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_PT_REGS_H_ - -/* **** Includes **** */ -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined (__ICCARM__) - #pragma system_include -#endif - -#if defined (__CC_ARM) - #pragma anon_unions -#endif -/// @cond -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif -#ifndef __R -#define __R volatile const -#endif -/// @endcond - -/* **** Definitions **** */ - -/** - * @ingroup pt - * @defgroup pt_registers PT_Registers - * @brief Registers, Bit Masks and Bit Positions for the PT Peripheral Module. - * @details Pulse Train - */ - -/** - * @ingroup pt_registers - * Structure type to access the PT Registers. - */ -typedef struct { - __IO uint32_t rate_length; /**< \b 0x0000: PT RATE_LENGTH Register */ - __IO uint32_t train; /**< \b 0x0004: PT TRAIN Register */ - __IO uint32_t loop; /**< \b 0x0008: PT LOOP Register */ - __IO uint32_t restart; /**< \b 0x000C: PT RESTART Register */ -} mxc_pt_regs_t; - -/* Register offsets for module PT */ -/** - * @ingroup pt_registers - * @defgroup PT_Register_Offsets Register Offsets - * @brief PT Peripheral Register Offsets from the PT Base Peripheral Address. - * @{ - */ -#define MXC_R_PT_RATE_LENGTH ((uint32_t)0x00000000UL) /**< Offset from PT Base Address: 0x0000 */ -#define MXC_R_PT_TRAIN ((uint32_t)0x00000004UL) /**< Offset from PT Base Address: 0x0004 */ -#define MXC_R_PT_LOOP ((uint32_t)0x00000008UL) /**< Offset from PT Base Address: 0x0008 */ -#define MXC_R_PT_RESTART ((uint32_t)0x0000000CUL) /**< Offset from PT Base Address: 0x000C */ -/**@} end of group pt_registers */ - -/** - * @ingroup pt_registers - * @defgroup PT_RATE_LENGTH PT_RATE_LENGTH - * @brief Pulse Train Configuration - * @{ - */ -#define MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS 0 /**< RATE_LENGTH_RATE_CONTROL Position */ -#define MXC_F_PT_RATE_LENGTH_RATE_CONTROL ((uint32_t)(0x7FFFFFFUL << MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS)) /**< RATE_LENGTH_RATE_CONTROL Mask */ - -#define MXC_F_PT_RATE_LENGTH_MODE_POS 27 /**< RATE_LENGTH_MODE Position */ -#define MXC_F_PT_RATE_LENGTH_MODE ((uint32_t)(0x1FUL << MXC_F_PT_RATE_LENGTH_MODE_POS)) /**< RATE_LENGTH_MODE Mask */ -#define MXC_V_PT_RATE_LENGTH_MODE_32_BIT ((uint32_t)0x0UL) /**< RATE_LENGTH_MODE_32_BIT Value */ -#define MXC_S_PT_RATE_LENGTH_MODE_32_BIT (MXC_V_PT_RATE_LENGTH_MODE_32_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_32_BIT Setting */ -#define MXC_V_PT_RATE_LENGTH_MODE_SQUARE_WAVE ((uint32_t)0x1UL) /**< RATE_LENGTH_MODE_SQUARE_WAVE Value */ -#define MXC_S_PT_RATE_LENGTH_MODE_SQUARE_WAVE (MXC_V_PT_RATE_LENGTH_MODE_SQUARE_WAVE << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_SQUARE_WAVE Setting */ -#define MXC_V_PT_RATE_LENGTH_MODE_2_BIT ((uint32_t)0x2UL) /**< RATE_LENGTH_MODE_2_BIT Value */ -#define MXC_S_PT_RATE_LENGTH_MODE_2_BIT (MXC_V_PT_RATE_LENGTH_MODE_2_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_2_BIT Setting */ -#define MXC_V_PT_RATE_LENGTH_MODE_3_BIT ((uint32_t)0x3UL) /**< RATE_LENGTH_MODE_3_BIT Value */ -#define MXC_S_PT_RATE_LENGTH_MODE_3_BIT (MXC_V_PT_RATE_LENGTH_MODE_3_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_3_BIT Setting */ -#define MXC_V_PT_RATE_LENGTH_MODE_4_BIT ((uint32_t)0x4UL) /**< RATE_LENGTH_MODE_4_BIT Value */ -#define MXC_S_PT_RATE_LENGTH_MODE_4_BIT (MXC_V_PT_RATE_LENGTH_MODE_4_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_4_BIT Setting */ -#define MXC_V_PT_RATE_LENGTH_MODE_5_BIT ((uint32_t)0x5UL) /**< RATE_LENGTH_MODE_5_BIT Value */ -#define MXC_S_PT_RATE_LENGTH_MODE_5_BIT (MXC_V_PT_RATE_LENGTH_MODE_5_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_5_BIT Setting */ -#define MXC_V_PT_RATE_LENGTH_MODE_6_BIT ((uint32_t)0x6UL) /**< RATE_LENGTH_MODE_6_BIT Value */ -#define MXC_S_PT_RATE_LENGTH_MODE_6_BIT (MXC_V_PT_RATE_LENGTH_MODE_6_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_6_BIT Setting */ -#define MXC_V_PT_RATE_LENGTH_MODE_7_BIT ((uint32_t)0x7UL) /**< RATE_LENGTH_MODE_7_BIT Value */ -#define MXC_S_PT_RATE_LENGTH_MODE_7_BIT (MXC_V_PT_RATE_LENGTH_MODE_7_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_7_BIT Setting */ -#define MXC_V_PT_RATE_LENGTH_MODE_8_BIT ((uint32_t)0x8UL) /**< RATE_LENGTH_MODE_8_BIT Value */ -#define MXC_S_PT_RATE_LENGTH_MODE_8_BIT (MXC_V_PT_RATE_LENGTH_MODE_8_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_8_BIT Setting */ -#define MXC_V_PT_RATE_LENGTH_MODE_9_BIT ((uint32_t)0x9UL) /**< RATE_LENGTH_MODE_9_BIT Value */ -#define MXC_S_PT_RATE_LENGTH_MODE_9_BIT (MXC_V_PT_RATE_LENGTH_MODE_9_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_9_BIT Setting */ -#define MXC_V_PT_RATE_LENGTH_MODE_10_BIT ((uint32_t)0xAUL) /**< RATE_LENGTH_MODE_10_BIT Value */ -#define MXC_S_PT_RATE_LENGTH_MODE_10_BIT (MXC_V_PT_RATE_LENGTH_MODE_10_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_10_BIT Setting */ -#define MXC_V_PT_RATE_LENGTH_MODE_11_BIT ((uint32_t)0xBUL) /**< RATE_LENGTH_MODE_11_BIT Value */ -#define MXC_S_PT_RATE_LENGTH_MODE_11_BIT (MXC_V_PT_RATE_LENGTH_MODE_11_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_11_BIT Setting */ -#define MXC_V_PT_RATE_LENGTH_MODE_12_BIT ((uint32_t)0xCUL) /**< RATE_LENGTH_MODE_12_BIT Value */ -#define MXC_S_PT_RATE_LENGTH_MODE_12_BIT (MXC_V_PT_RATE_LENGTH_MODE_12_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_12_BIT Setting */ -#define MXC_V_PT_RATE_LENGTH_MODE_13_BIT ((uint32_t)0xDUL) /**< RATE_LENGTH_MODE_13_BIT Value */ -#define MXC_S_PT_RATE_LENGTH_MODE_13_BIT (MXC_V_PT_RATE_LENGTH_MODE_13_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_13_BIT Setting */ -#define MXC_V_PT_RATE_LENGTH_MODE_14_BIT ((uint32_t)0xEUL) /**< RATE_LENGTH_MODE_14_BIT Value */ -#define MXC_S_PT_RATE_LENGTH_MODE_14_BIT (MXC_V_PT_RATE_LENGTH_MODE_14_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_14_BIT Setting */ -#define MXC_V_PT_RATE_LENGTH_MODE_15_BIT ((uint32_t)0xFUL) /**< RATE_LENGTH_MODE_15_BIT Value */ -#define MXC_S_PT_RATE_LENGTH_MODE_15_BIT (MXC_V_PT_RATE_LENGTH_MODE_15_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_15_BIT Setting */ -#define MXC_V_PT_RATE_LENGTH_MODE_16_BIT ((uint32_t)0x10UL) /**< RATE_LENGTH_MODE_16_BIT Value */ -#define MXC_S_PT_RATE_LENGTH_MODE_16_BIT (MXC_V_PT_RATE_LENGTH_MODE_16_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_16_BIT Setting */ -#define MXC_V_PT_RATE_LENGTH_MODE_17_BIT ((uint32_t)0x11UL) /**< RATE_LENGTH_MODE_17_BIT Value */ -#define MXC_S_PT_RATE_LENGTH_MODE_17_BIT (MXC_V_PT_RATE_LENGTH_MODE_17_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_17_BIT Setting */ -#define MXC_V_PT_RATE_LENGTH_MODE_18_BIT ((uint32_t)0x12UL) /**< RATE_LENGTH_MODE_18_BIT Value */ -#define MXC_S_PT_RATE_LENGTH_MODE_18_BIT (MXC_V_PT_RATE_LENGTH_MODE_18_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_18_BIT Setting */ -#define MXC_V_PT_RATE_LENGTH_MODE_19_BIT ((uint32_t)0x13UL) /**< RATE_LENGTH_MODE_19_BIT Value */ -#define MXC_S_PT_RATE_LENGTH_MODE_19_BIT (MXC_V_PT_RATE_LENGTH_MODE_19_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_19_BIT Setting */ -#define MXC_V_PT_RATE_LENGTH_MODE_20_BIT ((uint32_t)0x14UL) /**< RATE_LENGTH_MODE_20_BIT Value */ -#define MXC_S_PT_RATE_LENGTH_MODE_20_BIT (MXC_V_PT_RATE_LENGTH_MODE_20_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_20_BIT Setting */ -#define MXC_V_PT_RATE_LENGTH_MODE_21_BIT ((uint32_t)0x15UL) /**< RATE_LENGTH_MODE_21_BIT Value */ -#define MXC_S_PT_RATE_LENGTH_MODE_21_BIT (MXC_V_PT_RATE_LENGTH_MODE_21_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_21_BIT Setting */ -#define MXC_V_PT_RATE_LENGTH_MODE_22_BIT ((uint32_t)0x16UL) /**< RATE_LENGTH_MODE_22_BIT Value */ -#define MXC_S_PT_RATE_LENGTH_MODE_22_BIT (MXC_V_PT_RATE_LENGTH_MODE_22_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_22_BIT Setting */ -#define MXC_V_PT_RATE_LENGTH_MODE_23_BIT ((uint32_t)0x17UL) /**< RATE_LENGTH_MODE_23_BIT Value */ -#define MXC_S_PT_RATE_LENGTH_MODE_23_BIT (MXC_V_PT_RATE_LENGTH_MODE_23_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_23_BIT Setting */ -#define MXC_V_PT_RATE_LENGTH_MODE_24_BIT ((uint32_t)0x18UL) /**< RATE_LENGTH_MODE_24_BIT Value */ -#define MXC_S_PT_RATE_LENGTH_MODE_24_BIT (MXC_V_PT_RATE_LENGTH_MODE_24_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_24_BIT Setting */ -#define MXC_V_PT_RATE_LENGTH_MODE_25_BIT ((uint32_t)0x19UL) /**< RATE_LENGTH_MODE_25_BIT Value */ -#define MXC_S_PT_RATE_LENGTH_MODE_25_BIT (MXC_V_PT_RATE_LENGTH_MODE_25_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_25_BIT Setting */ -#define MXC_V_PT_RATE_LENGTH_MODE_26_BIT ((uint32_t)0x1AUL) /**< RATE_LENGTH_MODE_26_BIT Value */ -#define MXC_S_PT_RATE_LENGTH_MODE_26_BIT (MXC_V_PT_RATE_LENGTH_MODE_26_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_26_BIT Setting */ -#define MXC_V_PT_RATE_LENGTH_MODE_27_BIT ((uint32_t)0x1BUL) /**< RATE_LENGTH_MODE_27_BIT Value */ -#define MXC_S_PT_RATE_LENGTH_MODE_27_BIT (MXC_V_PT_RATE_LENGTH_MODE_27_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_27_BIT Setting */ -#define MXC_V_PT_RATE_LENGTH_MODE_28_BIT ((uint32_t)0x1CUL) /**< RATE_LENGTH_MODE_28_BIT Value */ -#define MXC_S_PT_RATE_LENGTH_MODE_28_BIT (MXC_V_PT_RATE_LENGTH_MODE_28_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_28_BIT Setting */ -#define MXC_V_PT_RATE_LENGTH_MODE_29_BIT ((uint32_t)0x1DUL) /**< RATE_LENGTH_MODE_29_BIT Value */ -#define MXC_S_PT_RATE_LENGTH_MODE_29_BIT (MXC_V_PT_RATE_LENGTH_MODE_29_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_29_BIT Setting */ -#define MXC_V_PT_RATE_LENGTH_MODE_30_BIT ((uint32_t)0x1EUL) /**< RATE_LENGTH_MODE_30_BIT Value */ -#define MXC_S_PT_RATE_LENGTH_MODE_30_BIT (MXC_V_PT_RATE_LENGTH_MODE_30_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_30_BIT Setting */ -#define MXC_V_PT_RATE_LENGTH_MODE_31_BIT ((uint32_t)0x1FUL) /**< RATE_LENGTH_MODE_31_BIT Value */ -#define MXC_S_PT_RATE_LENGTH_MODE_31_BIT (MXC_V_PT_RATE_LENGTH_MODE_31_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS) /**< RATE_LENGTH_MODE_31_BIT Setting */ - -/**@} end of group PT_RATE_LENGTH_Register */ - -/** - * @ingroup pt_registers - * @defgroup PT_LOOP PT_LOOP - * @brief Pulse Train Loop Count - * @{ - */ -#define MXC_F_PT_LOOP_COUNT_POS 0 /**< LOOP_COUNT Position */ -#define MXC_F_PT_LOOP_COUNT ((uint32_t)(0xFFFFUL << MXC_F_PT_LOOP_COUNT_POS)) /**< LOOP_COUNT Mask */ - -#define MXC_F_PT_LOOP_DELAY_POS 16 /**< LOOP_DELAY Position */ -#define MXC_F_PT_LOOP_DELAY ((uint32_t)(0xFFFUL << MXC_F_PT_LOOP_DELAY_POS)) /**< LOOP_DELAY Mask */ - -/**@} end of group PT_LOOP_Register */ - -/** - * @ingroup pt_registers - * @defgroup PT_RESTART PT_RESTART - * @brief Pulse Train Auto-Restart Configuration. - * @{ - */ -#define MXC_F_PT_RESTART_PT_X_SELECT_POS 0 /**< RESTART_PT_X_SELECT Position */ -#define MXC_F_PT_RESTART_PT_X_SELECT ((uint32_t)(0x1FUL << MXC_F_PT_RESTART_PT_X_SELECT_POS)) /**< RESTART_PT_X_SELECT Mask */ - -#define MXC_F_PT_RESTART_ON_PT_X_LOOP_EXIT_POS 7 /**< RESTART_ON_PT_X_LOOP_EXIT Position */ -#define MXC_F_PT_RESTART_ON_PT_X_LOOP_EXIT ((uint32_t)(0x1UL << MXC_F_PT_RESTART_ON_PT_X_LOOP_EXIT_POS)) /**< RESTART_ON_PT_X_LOOP_EXIT Mask */ - -#define MXC_F_PT_RESTART_PT_Y_SELECT_POS 8 /**< RESTART_PT_Y_SELECT Position */ -#define MXC_F_PT_RESTART_PT_Y_SELECT ((uint32_t)(0x1FUL << MXC_F_PT_RESTART_PT_Y_SELECT_POS)) /**< RESTART_PT_Y_SELECT Mask */ - -#define MXC_F_PT_RESTART_ON_PT_Y_LOOP_EXIT_POS 15 /**< RESTART_ON_PT_Y_LOOP_EXIT Position */ -#define MXC_F_PT_RESTART_ON_PT_Y_LOOP_EXIT ((uint32_t)(0x1UL << MXC_F_PT_RESTART_ON_PT_Y_LOOP_EXIT_POS)) /**< RESTART_ON_PT_Y_LOOP_EXIT Mask */ - -/**@} end of group PT_RESTART_Register */ - -#ifdef __cplusplus -} -#endif - -#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_PT_REGS_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/ptg_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/ptg_regs.h deleted file mode 100644 index 1ec3278293e..00000000000 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/ptg_regs.h +++ /dev/null @@ -1,267 +0,0 @@ -/** - * @file ptg_regs.h - * @brief Registers, Bit Masks and Bit Positions for the PTG Peripheral Module. - * @note This file is @generated. - * @ingroup ptg_registers - */ - -/****************************************************************************** - * - * Analog Devices, Inc.), - * Copyright (C) 2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ******************************************************************************/ - -#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_PTG_REGS_H_ -#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_PTG_REGS_H_ - -/* **** Includes **** */ -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined (__ICCARM__) - #pragma system_include -#endif - -#if defined (__CC_ARM) - #pragma anon_unions -#endif -/// @cond -/* - If types are not defined elsewhere (CMSIS) define them here -*/ -#ifndef __IO -#define __IO volatile -#endif -#ifndef __I -#define __I volatile const -#endif -#ifndef __O -#define __O volatile -#endif -#ifndef __R -#define __R volatile const -#endif -/// @endcond - -/* **** Definitions **** */ - -/** - * @ingroup ptg - * @defgroup ptg_registers PTG_Registers - * @brief Registers, Bit Masks and Bit Positions for the PTG Peripheral Module. - * @details Pulse Train Generation - */ - -/** - * @ingroup ptg_registers - * Structure type to access the PTG Registers. - */ -typedef struct { - __IO uint32_t enable; /**< \b 0x0000: PTG ENABLE Register */ - __IO uint32_t resync; /**< \b 0x0004: PTG RESYNC Register */ - __IO uint32_t stop_intfl; /**< \b 0x0008: PTG STOP_INTFL Register */ - __IO uint32_t stop_inten; /**< \b 0x000C: PTG STOP_INTEN Register */ - __O uint32_t safe_en; /**< \b 0x0010: PTG SAFE_EN Register */ - __O uint32_t safe_dis; /**< \b 0x0014: PTG SAFE_DIS Register */ - __IO uint32_t ready_intfl; /**< \b 0x0018: PTG READY_INTFL Register */ - __IO uint32_t ready_inten; /**< \b 0x001C: PTG READY_INTEN Register */ -} mxc_ptg_regs_t; - -/* Register offsets for module PTG */ -/** - * @ingroup ptg_registers - * @defgroup PTG_Register_Offsets Register Offsets - * @brief PTG Peripheral Register Offsets from the PTG Base Peripheral Address. - * @{ - */ -#define MXC_R_PTG_ENABLE ((uint32_t)0x00000000UL) /**< Offset from PTG Base Address: 0x0000 */ -#define MXC_R_PTG_RESYNC ((uint32_t)0x00000004UL) /**< Offset from PTG Base Address: 0x0004 */ -#define MXC_R_PTG_STOP_INTFL ((uint32_t)0x00000008UL) /**< Offset from PTG Base Address: 0x0008 */ -#define MXC_R_PTG_STOP_INTEN ((uint32_t)0x0000000CUL) /**< Offset from PTG Base Address: 0x000C */ -#define MXC_R_PTG_SAFE_EN ((uint32_t)0x00000010UL) /**< Offset from PTG Base Address: 0x0010 */ -#define MXC_R_PTG_SAFE_DIS ((uint32_t)0x00000014UL) /**< Offset from PTG Base Address: 0x0014 */ -#define MXC_R_PTG_READY_INTFL ((uint32_t)0x00000018UL) /**< Offset from PTG Base Address: 0x0018 */ -#define MXC_R_PTG_READY_INTEN ((uint32_t)0x0000001CUL) /**< Offset from PTG Base Address: 0x001C */ -/**@} end of group ptg_registers */ - -/** - * @ingroup ptg_registers - * @defgroup PTG_ENABLE PTG_ENABLE - * @brief Global Enable/Disable Controls for All Pulse Trains - * @{ - */ -#define MXC_F_PTG_ENABLE_PT0_POS 0 /**< ENABLE_PT0 Position */ -#define MXC_F_PTG_ENABLE_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT0_POS)) /**< ENABLE_PT0 Mask */ - -#define MXC_F_PTG_ENABLE_PT1_POS 1 /**< ENABLE_PT1 Position */ -#define MXC_F_PTG_ENABLE_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT1_POS)) /**< ENABLE_PT1 Mask */ - -#define MXC_F_PTG_ENABLE_PT2_POS 2 /**< ENABLE_PT2 Position */ -#define MXC_F_PTG_ENABLE_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT2_POS)) /**< ENABLE_PT2 Mask */ - -#define MXC_F_PTG_ENABLE_PT3_POS 3 /**< ENABLE_PT3 Position */ -#define MXC_F_PTG_ENABLE_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_ENABLE_PT3_POS)) /**< ENABLE_PT3 Mask */ - -/**@} end of group PTG_ENABLE_Register */ - -/** - * @ingroup ptg_registers - * @defgroup PTG_RESYNC PTG_RESYNC - * @brief Global Resync (All Pulse Trains) Control - * @{ - */ -#define MXC_F_PTG_RESYNC_PT0_POS 0 /**< RESYNC_PT0 Position */ -#define MXC_F_PTG_RESYNC_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT0_POS)) /**< RESYNC_PT0 Mask */ - -#define MXC_F_PTG_RESYNC_PT1_POS 1 /**< RESYNC_PT1 Position */ -#define MXC_F_PTG_RESYNC_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT1_POS)) /**< RESYNC_PT1 Mask */ - -#define MXC_F_PTG_RESYNC_PT2_POS 2 /**< RESYNC_PT2 Position */ -#define MXC_F_PTG_RESYNC_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT2_POS)) /**< RESYNC_PT2 Mask */ - -#define MXC_F_PTG_RESYNC_PT3_POS 3 /**< RESYNC_PT3 Position */ -#define MXC_F_PTG_RESYNC_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_RESYNC_PT3_POS)) /**< RESYNC_PT3 Mask */ - -/**@} end of group PTG_RESYNC_Register */ - -/** - * @ingroup ptg_registers - * @defgroup PTG_STOP_INTFL PTG_STOP_INTFL - * @brief Pulse Train Stop Interrupt Flags - * @{ - */ -#define MXC_F_PTG_STOP_INTFL_PT0_POS 0 /**< STOP_INTFL_PT0 Position */ -#define MXC_F_PTG_STOP_INTFL_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTFL_PT0_POS)) /**< STOP_INTFL_PT0 Mask */ - -#define MXC_F_PTG_STOP_INTFL_PT1_POS 1 /**< STOP_INTFL_PT1 Position */ -#define MXC_F_PTG_STOP_INTFL_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTFL_PT1_POS)) /**< STOP_INTFL_PT1 Mask */ - -#define MXC_F_PTG_STOP_INTFL_PT2_POS 2 /**< STOP_INTFL_PT2 Position */ -#define MXC_F_PTG_STOP_INTFL_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTFL_PT2_POS)) /**< STOP_INTFL_PT2 Mask */ - -#define MXC_F_PTG_STOP_INTFL_PT3_POS 3 /**< STOP_INTFL_PT3 Position */ -#define MXC_F_PTG_STOP_INTFL_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTFL_PT3_POS)) /**< STOP_INTFL_PT3 Mask */ - -/**@} end of group PTG_STOP_INTFL_Register */ - -/** - * @ingroup ptg_registers - * @defgroup PTG_STOP_INTEN PTG_STOP_INTEN - * @brief Pulse Train Stop Interrupt Enable/Disable - * @{ - */ -#define MXC_F_PTG_STOP_INTEN_PT0_POS 0 /**< STOP_INTEN_PT0 Position */ -#define MXC_F_PTG_STOP_INTEN_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTEN_PT0_POS)) /**< STOP_INTEN_PT0 Mask */ - -#define MXC_F_PTG_STOP_INTEN_PT1_POS 1 /**< STOP_INTEN_PT1 Position */ -#define MXC_F_PTG_STOP_INTEN_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTEN_PT1_POS)) /**< STOP_INTEN_PT1 Mask */ - -#define MXC_F_PTG_STOP_INTEN_PT2_POS 2 /**< STOP_INTEN_PT2 Position */ -#define MXC_F_PTG_STOP_INTEN_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTEN_PT2_POS)) /**< STOP_INTEN_PT2 Mask */ - -#define MXC_F_PTG_STOP_INTEN_PT3_POS 3 /**< STOP_INTEN_PT3 Position */ -#define MXC_F_PTG_STOP_INTEN_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_STOP_INTEN_PT3_POS)) /**< STOP_INTEN_PT3 Mask */ - -/**@} end of group PTG_STOP_INTEN_Register */ - -/** - * @ingroup ptg_registers - * @defgroup PTG_SAFE_EN PTG_SAFE_EN - * @brief Pulse Train Global Safe Enable. - * @{ - */ -#define MXC_F_PTG_SAFE_EN_PT0_POS 0 /**< SAFE_EN_PT0 Position */ -#define MXC_F_PTG_SAFE_EN_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT0_POS)) /**< SAFE_EN_PT0 Mask */ - -#define MXC_F_PTG_SAFE_EN_PT1_POS 1 /**< SAFE_EN_PT1 Position */ -#define MXC_F_PTG_SAFE_EN_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT1_POS)) /**< SAFE_EN_PT1 Mask */ - -#define MXC_F_PTG_SAFE_EN_PT2_POS 2 /**< SAFE_EN_PT2 Position */ -#define MXC_F_PTG_SAFE_EN_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT2_POS)) /**< SAFE_EN_PT2 Mask */ - -#define MXC_F_PTG_SAFE_EN_PT3_POS 3 /**< SAFE_EN_PT3 Position */ -#define MXC_F_PTG_SAFE_EN_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_EN_PT3_POS)) /**< SAFE_EN_PT3 Mask */ - -/**@} end of group PTG_SAFE_EN_Register */ - -/** - * @ingroup ptg_registers - * @defgroup PTG_SAFE_DIS PTG_SAFE_DIS - * @brief Pulse Train Global Safe Disable. - * @{ - */ -#define MXC_F_PTG_SAFE_DIS_PT0_POS 0 /**< SAFE_DIS_PT0 Position */ -#define MXC_F_PTG_SAFE_DIS_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT0_POS)) /**< SAFE_DIS_PT0 Mask */ - -#define MXC_F_PTG_SAFE_DIS_PT1_POS 1 /**< SAFE_DIS_PT1 Position */ -#define MXC_F_PTG_SAFE_DIS_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT1_POS)) /**< SAFE_DIS_PT1 Mask */ - -#define MXC_F_PTG_SAFE_DIS_PT2_POS 2 /**< SAFE_DIS_PT2 Position */ -#define MXC_F_PTG_SAFE_DIS_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT2_POS)) /**< SAFE_DIS_PT2 Mask */ - -#define MXC_F_PTG_SAFE_DIS_PT3_POS 3 /**< SAFE_DIS_PT3 Position */ -#define MXC_F_PTG_SAFE_DIS_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_SAFE_DIS_PT3_POS)) /**< SAFE_DIS_PT3 Mask */ - -/**@} end of group PTG_SAFE_DIS_Register */ - -/** - * @ingroup ptg_registers - * @defgroup PTG_READY_INTFL PTG_READY_INTFL - * @brief Pulse Train Ready Interrupt Flags - * @{ - */ -#define MXC_F_PTG_READY_INTFL_PT0_POS 0 /**< READY_INTFL_PT0 Position */ -#define MXC_F_PTG_READY_INTFL_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT0_POS)) /**< READY_INTFL_PT0 Mask */ - -#define MXC_F_PTG_READY_INTFL_PT1_POS 1 /**< READY_INTFL_PT1 Position */ -#define MXC_F_PTG_READY_INTFL_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT1_POS)) /**< READY_INTFL_PT1 Mask */ - -#define MXC_F_PTG_READY_INTFL_PT2_POS 2 /**< READY_INTFL_PT2 Position */ -#define MXC_F_PTG_READY_INTFL_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT2_POS)) /**< READY_INTFL_PT2 Mask */ - -#define MXC_F_PTG_READY_INTFL_PT3_POS 3 /**< READY_INTFL_PT3 Position */ -#define MXC_F_PTG_READY_INTFL_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTFL_PT3_POS)) /**< READY_INTFL_PT3 Mask */ - -/**@} end of group PTG_READY_INTFL_Register */ - -/** - * @ingroup ptg_registers - * @defgroup PTG_READY_INTEN PTG_READY_INTEN - * @brief Pulse Train Ready Interrupt Enable/Disable - * @{ - */ -#define MXC_F_PTG_READY_INTEN_PT0_POS 0 /**< READY_INTEN_PT0 Position */ -#define MXC_F_PTG_READY_INTEN_PT0 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT0_POS)) /**< READY_INTEN_PT0 Mask */ - -#define MXC_F_PTG_READY_INTEN_PT1_POS 1 /**< READY_INTEN_PT1 Position */ -#define MXC_F_PTG_READY_INTEN_PT1 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT1_POS)) /**< READY_INTEN_PT1 Mask */ - -#define MXC_F_PTG_READY_INTEN_PT2_POS 2 /**< READY_INTEN_PT2 Position */ -#define MXC_F_PTG_READY_INTEN_PT2 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT2_POS)) /**< READY_INTEN_PT2 Mask */ - -#define MXC_F_PTG_READY_INTEN_PT3_POS 3 /**< READY_INTEN_PT3 Position */ -#define MXC_F_PTG_READY_INTEN_PT3 ((uint32_t)(0x1UL << MXC_F_PTG_READY_INTEN_PT3_POS)) /**< READY_INTEN_PT3 Mask */ - -/**@} end of group PTG_READY_INTEN_Register */ - -#ifdef __cplusplus -} -#endif - -#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_PTG_REGS_H_ From 609b7b7cc80e190891b99947f98c3a735e91ae32 Mon Sep 17 00:00:00 2001 From: Sadik Ozer Date: Thu, 18 Apr 2024 15:56:08 +0300 Subject: [PATCH 11/93] Add MAX32657 in zephyr build system This commit enable MAX32657 zephyr support. Signed-off-by: Sadik Ozer --- Libraries/zephyr/MAX/CMakeLists.txt | 1 + Libraries/zephyr/MAX/Include/wrap_max32xxx.h | 2 + .../zephyr/MAX/Source/MAX32657/CMakeLists.txt | 143 ++++++++++++++++++ .../MAX/Source/MAX32657/max32xxx_system.c | 24 +++ 4 files changed, 170 insertions(+) create mode 100644 Libraries/zephyr/MAX/Source/MAX32657/CMakeLists.txt create mode 100644 Libraries/zephyr/MAX/Source/MAX32657/max32xxx_system.c diff --git a/Libraries/zephyr/MAX/CMakeLists.txt b/Libraries/zephyr/MAX/CMakeLists.txt index d48409cdb7b..eb6414c4039 100644 --- a/Libraries/zephyr/MAX/CMakeLists.txt +++ b/Libraries/zephyr/MAX/CMakeLists.txt @@ -49,6 +49,7 @@ add_subdirectory_ifdef(CONFIG_SOC_MAX32570 Source/MAX32570) add_subdirectory_ifdef(CONFIG_SOC_MAX32572 Source/MAX32572) add_subdirectory_ifdef(CONFIG_SOC_MAX32650 Source/MAX32650) add_subdirectory_ifdef(CONFIG_SOC_MAX32655 Source/MAX32655) +add_subdirectory_ifdef(CONFIG_SOC_MAX32657 Source/MAX32657) add_subdirectory_ifdef(CONFIG_SOC_MAX32660 Source/MAX32660) add_subdirectory_ifdef(CONFIG_SOC_MAX32662 Source/MAX32662) add_subdirectory_ifdef(CONFIG_SOC_MAX32665 Source/MAX32665) diff --git a/Libraries/zephyr/MAX/Include/wrap_max32xxx.h b/Libraries/zephyr/MAX/Include/wrap_max32xxx.h index fc8c250fbb1..a8baaea0eab 100644 --- a/Libraries/zephyr/MAX/Include/wrap_max32xxx.h +++ b/Libraries/zephyr/MAX/Include/wrap_max32xxx.h @@ -57,6 +57,8 @@ extern "C" { #include #elif defined(CONFIG_SOC_MAX78002) #include +#elif defined(CONFIG_SOC_MAX32657) +#include #endif #ifdef __cplusplus diff --git a/Libraries/zephyr/MAX/Source/MAX32657/CMakeLists.txt b/Libraries/zephyr/MAX/Source/MAX32657/CMakeLists.txt new file mode 100644 index 00000000000..b60488ac19a --- /dev/null +++ b/Libraries/zephyr/MAX/Source/MAX32657/CMakeLists.txt @@ -0,0 +1,143 @@ +############################################################################## +# +# Copyright (C) 2024 Analog Devices, Inc. +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +############################################################################## + + +if(NOT TARGET_REV) + # Default version A1, not actively use in driver but requires to be defined. + zephyr_compile_definitions(-DTARGET_REV=0x4131) +endif() + +zephyr_include_directories( + ${MSDK_PERIPH_SRC_DIR}/SYS + ${MSDK_PERIPH_SRC_DIR}/AES + ${MSDK_PERIPH_SRC_DIR}/CRC + ${MSDK_PERIPH_SRC_DIR}/DMA + ${MSDK_PERIPH_SRC_DIR}/FLC + ${MSDK_PERIPH_SRC_DIR}/GPIO + ${MSDK_PERIPH_SRC_DIR}/I2C + ${MSDK_PERIPH_SRC_DIR}/ICC + ${MSDK_PERIPH_SRC_DIR}/LP + ${MSDK_PERIPH_SRC_DIR}/RTC + ${MSDK_PERIPH_SRC_DIR}/SPI + ${MSDK_PERIPH_SRC_DIR}/TRNG + ${MSDK_PERIPH_SRC_DIR}/TMR + ${MSDK_PERIPH_SRC_DIR}/UART + ${MSDK_PERIPH_SRC_DIR}/WDT + ${MSDK_PERIPH_SRC_DIR}/WUT +) + +zephyr_library_sources( + ./max32xxx_system.c + + ${MSDK_CMSIS_DIR}/Source/system_max32657.c + + ${MSDK_PERIPH_SRC_DIR}/SYS/mxc_assert.c + ${MSDK_PERIPH_SRC_DIR}/SYS/mxc_delay.c + ${MSDK_PERIPH_SRC_DIR}/SYS/mxc_lock.c + ${MSDK_PERIPH_SRC_DIR}/SYS/pins_me30.c + ${MSDK_PERIPH_SRC_DIR}/SYS/sys_me30.c + + ${MSDK_PERIPH_SRC_DIR}/ICC/icc_me30.c + ${MSDK_PERIPH_SRC_DIR}/ICC/icc_reva.c + + ${MSDK_PERIPH_SRC_DIR}/LP/lp_me30.c + + ${MSDK_PERIPH_SRC_DIR}/WUT/wut_me30.c + ${MSDK_PERIPH_SRC_DIR}/WUT/wut_reva.c + + ${MSDK_PERIPH_SRC_DIR}/DMA/dma_me30.c + ${MSDK_PERIPH_SRC_DIR}/DMA/dma_reva.c +) + +if (CONFIG_UART_MAX32) +zephyr_library_sources( + ${MSDK_PERIPH_SRC_DIR}/UART/uart_common.c + ${MSDK_PERIPH_SRC_DIR}/UART/uart_me30.c + ${MSDK_PERIPH_SRC_DIR}/UART/uart_revb.c +) +endif() + +if (CONFIG_GPIO_MAX32) +zephyr_library_sources( + ${MSDK_PERIPH_SRC_DIR}/GPIO/gpio_common.c + ${MSDK_PERIPH_SRC_DIR}/GPIO/gpio_me30.c + ${MSDK_PERIPH_SRC_DIR}/GPIO/gpio_reva.c +) +endif() + +if (CONFIG_SPI_MAX32) +zephyr_library_sources( + ${MSDK_PERIPH_SRC_DIR}/SPI/spi_me30.c + ${MSDK_PERIPH_SRC_DIR}/SPI/spi_reva1.c +) +endif() + +if (CONFIG_I2C_MAX32) +zephyr_library_sources( + ${MSDK_PERIPH_SRC_DIR}/I2C/i2c_me30.c + ${MSDK_PERIPH_SRC_DIR}/I2C/i2c_reva.c +) +endif() + +if (CONFIG_WDT_MAX32) +zephyr_library_sources( + ${MSDK_PERIPH_SRC_DIR}/WDT/wdt_common.c + ${MSDK_PERIPH_SRC_DIR}/WDT/wdt_me30.c + ${MSDK_PERIPH_SRC_DIR}/WDT/wdt_revb.c +) +endif() + +if (CONFIG_RTC_MAX32 OR CONFIG_COUNTER_RTC_MAX32) +zephyr_library_sources( + ${MSDK_PERIPH_SRC_DIR}/RTC/rtc_me30.c + ${MSDK_PERIPH_SRC_DIR}/RTC/rtc_reva.c +) +endif() + +if (CONFIG_SOC_FLASH_MAX32) +zephyr_library_sources( + ${MSDK_PERIPH_SRC_DIR}/FLC/flc_common.c + ${MSDK_PERIPH_SRC_DIR}/FLC/flc_me30.c + ${MSDK_PERIPH_SRC_DIR}/FLC/flc_reva.c +) +endif() + +if (CONFIG_PWM_MAX32 OR CONFIG_TIMER_MAX32 OR CONFIG_COUNTER_TIMER_MAX32) +zephyr_library_sources( + ${MSDK_PERIPH_SRC_DIR}/TMR/tmr_common.c + ${MSDK_PERIPH_SRC_DIR}/TMR/tmr_me30.c + ${MSDK_PERIPH_SRC_DIR}/TMR/tmr_revb.c +) +endif() + +if (CONFIG_ENTROPY_MAX32_TRNG) +zephyr_library_sources( + ${MSDK_PERIPH_SRC_DIR}/TRNG/trng_me30.c + ${MSDK_PERIPH_SRC_DIR}/TRNG/trng_revb.c +) +endif() + +if (CONFIG_CRYPTO_MAX32) +zephyr_library_sources( + ${MSDK_PERIPH_SRC_DIR}/AES/aes_me30.c + ${MSDK_PERIPH_SRC_DIR}/AES/aes_revb.c + + ${MSDK_PERIPH_SRC_DIR}/CRC/crc_me30.c + ${MSDK_PERIPH_SRC_DIR}/CRC/crc_reva.c +) +endif() diff --git a/Libraries/zephyr/MAX/Source/MAX32657/max32xxx_system.c b/Libraries/zephyr/MAX/Source/MAX32657/max32xxx_system.c new file mode 100644 index 00000000000..9998ccfb0b8 --- /dev/null +++ b/Libraries/zephyr/MAX/Source/MAX32657/max32xxx_system.c @@ -0,0 +1,24 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#include "max32657.h" + +/* + * This function is called during boot up. + */ +void max32xx_system_init(void) {} From 5d26d282a9b910004c31b60a508423744cc7757a Mon Sep 17 00:00:00 2001 From: Sadik Ozer Date: Thu, 18 Apr 2024 19:26:39 +0300 Subject: [PATCH 12/93] Update wrappers to cover MAX32657 Signed-off-by: Sadik Ozer --- Libraries/zephyr/MAX/Include/wrap_max32_dma.h | 2 +- Libraries/zephyr/MAX/Include/wrap_max32_i2c.h | 2 +- Libraries/zephyr/MAX/Include/wrap_max32_lp.h | 3 ++- Libraries/zephyr/MAX/Include/wrap_max32_spi.h | 2 +- Libraries/zephyr/MAX/Include/wrap_max32_sys.h | 2 +- Libraries/zephyr/MAX/Include/wrap_max32_tmr.h | 2 +- Libraries/zephyr/MAX/Include/wrap_max32_trng.h | 2 +- Libraries/zephyr/MAX/Include/wrap_max32_uart.h | 2 +- Libraries/zephyr/MAX/Include/wrap_max32_wdt.h | 2 +- 9 files changed, 10 insertions(+), 9 deletions(-) diff --git a/Libraries/zephyr/MAX/Include/wrap_max32_dma.h b/Libraries/zephyr/MAX/Include/wrap_max32_dma.h index 191713b4796..23830507d31 100644 --- a/Libraries/zephyr/MAX/Include/wrap_max32_dma.h +++ b/Libraries/zephyr/MAX/Include/wrap_max32_dma.h @@ -84,7 +84,7 @@ static inline int Wrap_MXC_DMA_DoTransfer(mxc_dma_regs_t *dma, mxc_dma_config_t */ #elif defined(CONFIG_SOC_MAX32690) || (CONFIG_SOC_MAX32655) || (CONFIG_SOC_MAX32670) || \ (CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32662) || (CONFIG_SOC_MAX32675) || \ - (CONFIG_SOC_MAX32680) + (CONFIG_SOC_MAX32680) || (CONFIG_SOC_MAX32657) #define ADI_MAX32_DMA_CTRL_DIS_IE MXC_F_DMA_CTRL_DIS_IE #define ADI_MAX32_DMA_CTRL_CTZIEN MXC_F_DMA_CTRL_CTZ_IE diff --git a/Libraries/zephyr/MAX/Include/wrap_max32_i2c.h b/Libraries/zephyr/MAX/Include/wrap_max32_i2c.h index a3bf611e741..4437a6f43a5 100644 --- a/Libraries/zephyr/MAX/Include/wrap_max32_i2c.h +++ b/Libraries/zephyr/MAX/Include/wrap_max32_i2c.h @@ -130,7 +130,7 @@ static inline void Wrap_MXC_I2C_Stop(mxc_i2c_regs_t *i2c) */ #elif defined(CONFIG_SOC_MAX32690) || (CONFIG_SOC_MAX32655) || (CONFIG_SOC_MAX32670) || \ (CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32662) || (CONFIG_SOC_MAX32675) || \ - (CONFIG_SOC_MAX32680) + (CONFIG_SOC_MAX32680) || (CONFIG_SOC_MAX32657) /* * Control register bits */ diff --git a/Libraries/zephyr/MAX/Include/wrap_max32_lp.h b/Libraries/zephyr/MAX/Include/wrap_max32_lp.h index 3e4c22b0151..e68c3fc396b 100644 --- a/Libraries/zephyr/MAX/Include/wrap_max32_lp.h +++ b/Libraries/zephyr/MAX/Include/wrap_max32_lp.h @@ -55,7 +55,8 @@ static inline void Wrap_MXC_LP_EnterPowerDownMode(void) /* * MAX32690, MAX32655 related mapping */ -#elif defined(CONFIG_SOC_MAX32690) || (CONFIG_SOC_MAX32655) || (CONFIG_SOC_MAX32680) +#elif defined(CONFIG_SOC_MAX32690) || (CONFIG_SOC_MAX32655) || (CONFIG_SOC_MAX32680) || \ + (CONFIG_SOC_MAX32657) static inline void Wrap_MXC_LP_EnterLowPowerMode(void) { diff --git a/Libraries/zephyr/MAX/Include/wrap_max32_spi.h b/Libraries/zephyr/MAX/Include/wrap_max32_spi.h index 389339c7eaf..ba0acfa4c81 100644 --- a/Libraries/zephyr/MAX/Include/wrap_max32_spi.h +++ b/Libraries/zephyr/MAX/Include/wrap_max32_spi.h @@ -75,7 +75,7 @@ static inline int Wrap_MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int qua */ #elif defined(CONFIG_SOC_MAX32690) || (CONFIG_SOC_MAX32655) || (CONFIG_SOC_MAX32670) || \ (CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32662) || (CONFIG_SOC_MAX32675) || \ - (CONFIG_SOC_MAX32680) + (CONFIG_SOC_MAX32680) || (CONFIG_SOC_MAX32657) #define ADI_MAX32_SPI_CTRL_MASTER_MODE MXC_F_SPI_CTRL0_MST_MODE diff --git a/Libraries/zephyr/MAX/Include/wrap_max32_sys.h b/Libraries/zephyr/MAX/Include/wrap_max32_sys.h index 467f053f7c0..67ac5aa99e1 100644 --- a/Libraries/zephyr/MAX/Include/wrap_max32_sys.h +++ b/Libraries/zephyr/MAX/Include/wrap_max32_sys.h @@ -56,7 +56,7 @@ static inline void Wrap_MXC_SYS_SetClockDiv(int div) */ #elif defined(CONFIG_SOC_MAX32690) || (CONFIG_SOC_MAX32655) || (CONFIG_SOC_MAX32670) || \ (CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32662) || (CONFIG_SOC_MAX32675) || \ - (CONFIG_SOC_MAX32680) + (CONFIG_SOC_MAX32680) || (CONFIG_SOC_MAX32657) #define ADI_MAX32_CLK_IPO MXC_SYS_CLOCK_IPO #define ADI_MAX32_CLK_ERFO MXC_SYS_CLOCK_ERFO diff --git a/Libraries/zephyr/MAX/Include/wrap_max32_tmr.h b/Libraries/zephyr/MAX/Include/wrap_max32_tmr.h index 7b10d6b2bc6..4c55c52a8d9 100644 --- a/Libraries/zephyr/MAX/Include/wrap_max32_tmr.h +++ b/Libraries/zephyr/MAX/Include/wrap_max32_tmr.h @@ -103,7 +103,7 @@ int Wrap_MXC_TMR_GetPendingInt(mxc_tmr_regs_t *tmr) */ #elif defined(CONFIG_SOC_MAX32690) || (CONFIG_SOC_MAX32655) || (CONFIG_SOC_MAX32670) || \ (CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32662) || (CONFIG_SOC_MAX32675) || \ - (CONFIG_SOC_MAX32680) + (CONFIG_SOC_MAX32680) || (CONFIG_SOC_MAX32657) #if defined(CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32675) /* All timers are 32bits */ diff --git a/Libraries/zephyr/MAX/Include/wrap_max32_trng.h b/Libraries/zephyr/MAX/Include/wrap_max32_trng.h index 9ce5e4e4529..84fdc24fbc8 100644 --- a/Libraries/zephyr/MAX/Include/wrap_max32_trng.h +++ b/Libraries/zephyr/MAX/Include/wrap_max32_trng.h @@ -46,7 +46,7 @@ static inline int Wrap_MXC_TRNG_RandomInt_NonBlocking(uint32_t *data) */ #elif defined(CONFIG_SOC_MAX32690) || (CONFIG_SOC_MAX32655) || (CONFIG_SOC_MAX32670) || \ (CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32662) || (CONFIG_SOC_MAX32675) || \ - (CONFIG_SOC_MAX32680) + (CONFIG_SOC_MAX32680) || (CONFIG_SOC_MAX32657) static inline int Wrap_MXC_TRNG_RandomInt_NonBlocking(uint32_t *data) { diff --git a/Libraries/zephyr/MAX/Include/wrap_max32_uart.h b/Libraries/zephyr/MAX/Include/wrap_max32_uart.h index 30bed803fc6..a7d1d9f0b95 100644 --- a/Libraries/zephyr/MAX/Include/wrap_max32_uart.h +++ b/Libraries/zephyr/MAX/Include/wrap_max32_uart.h @@ -119,7 +119,7 @@ static inline void Wrap_MXC_UART_DisableRxDMA(mxc_uart_regs_t *uart) */ #elif defined(CONFIG_SOC_MAX32690) || (CONFIG_SOC_MAX32655) || (CONFIG_SOC_MAX32670) || \ (CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32662) || (CONFIG_SOC_MAX32675) || \ - (CONFIG_SOC_MAX32680) + (CONFIG_SOC_MAX32680) || (CONFIG_SOC_MAX32657) // status flags #define ADI_MAX32_UART_RX_EMPTY MXC_F_UART_STATUS_RX_EM #define ADI_MAX32_UART_TX_EMPTY MXC_F_UART_STATUS_TX_EM diff --git a/Libraries/zephyr/MAX/Include/wrap_max32_wdt.h b/Libraries/zephyr/MAX/Include/wrap_max32_wdt.h index 6bee4338041..6fc4dca6813 100644 --- a/Libraries/zephyr/MAX/Include/wrap_max32_wdt.h +++ b/Libraries/zephyr/MAX/Include/wrap_max32_wdt.h @@ -85,7 +85,7 @@ static inline int Wrap_MXC_WDT_SelectClockSource(mxc_wdt_regs_t *wdt, uint32_t c */ #elif defined(CONFIG_SOC_MAX32690) || (CONFIG_SOC_MAX32655) || (CONFIG_SOC_MAX32670) || \ (CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32662) || (CONFIG_SOC_MAX32675) || \ - (CONFIG_SOC_MAX32680) + (CONFIG_SOC_MAX32680) || (CONFIG_SOC_MAX32657) #define WRAP_MXC_F_WDT_CTRL_EN MXC_F_WDT_CTRL_EN From b87895f9010c71de51fe29ef27405dbb0f16feaf Mon Sep 17 00:00:00 2001 From: Lorne Smith <65424047+lorne-maxim@users.noreply.github.com> Date: Fri, 19 Apr 2024 15:49:04 -0500 Subject: [PATCH 13/93] feat(PeriphDrivers): Add PinMux tool supporting functions (#997) Co-authored-by: lorne-maxim --- .../Maxim/MAX32520/Source/system_max32520.c | 12 ++++++++++ .../Maxim/MAX32570/Source/system_max32570.c | 12 ++++++++++ .../Maxim/MAX32572/Source/system_max32572.c | 12 ++++++++++ .../Maxim/MAX32650/Source/system_max32650.c | 12 ++++++++++ .../Maxim/MAX32655/Source/system_max32655.c | 12 ++++++++++ .../Maxim/MAX32660/Source/system_max32660.c | 12 ++++++++++ .../Maxim/MAX32662/Source/system_max32662.c | 12 ++++++++++ .../Maxim/MAX32665/Source/system_max32665.c | 12 ++++++++++ .../Maxim/MAX32670/Source/system_max32670.c | 12 ++++++++++ .../Maxim/MAX32672/Source/system_max32672.c | 12 ++++++++++ .../Maxim/MAX32675/Source/system_max32675.c | 12 ++++++++++ .../Maxim/MAX32680/Source/system_max32680.c | 12 ++++++++++ .../Maxim/MAX32690/Source/system_max32690.c | 12 ++++++++++ .../Maxim/MAX78000/Source/system_max78000.c | 12 ++++++++++ .../Maxim/MAX78002/Source/system_max78002.c | 12 ++++++++++ .../PeriphDrivers/Include/MAX32520/gpio.h | 22 +++++++++++++++++++ .../PeriphDrivers/Include/MAX32570/gpio.h | 22 +++++++++++++++++++ .../PeriphDrivers/Include/MAX32572/gpio.h | 22 +++++++++++++++++++ .../PeriphDrivers/Include/MAX32650/gpio.h | 22 +++++++++++++++++++ .../PeriphDrivers/Include/MAX32655/gpio.h | 22 +++++++++++++++++++ .../PeriphDrivers/Include/MAX32660/gpio.h | 22 +++++++++++++++++++ .../PeriphDrivers/Include/MAX32662/gpio.h | 22 +++++++++++++++++++ .../PeriphDrivers/Include/MAX32665/gpio.h | 22 +++++++++++++++++++ .../PeriphDrivers/Include/MAX32670/gpio.h | 22 +++++++++++++++++++ .../PeriphDrivers/Include/MAX32672/gpio.h | 22 +++++++++++++++++++ .../PeriphDrivers/Include/MAX32675/gpio.h | 22 +++++++++++++++++++ .../PeriphDrivers/Include/MAX32680/gpio.h | 22 +++++++++++++++++++ .../PeriphDrivers/Include/MAX32690/gpio.h | 22 +++++++++++++++++++ .../PeriphDrivers/Include/MAX78000/gpio.h | 22 +++++++++++++++++++ .../PeriphDrivers/Include/MAX78002/gpio.h | 22 +++++++++++++++++++ .../PeriphDrivers/Source/GPIO/gpio_ai85.c | 17 ++++++++++++++ .../PeriphDrivers/Source/GPIO/gpio_ai87.c | 17 ++++++++++++++ .../PeriphDrivers/Source/GPIO/gpio_common.c | 11 ++++++++++ .../PeriphDrivers/Source/GPIO/gpio_common.h | 2 ++ .../PeriphDrivers/Source/GPIO/gpio_es17.c | 15 +++++++++++++ .../PeriphDrivers/Source/GPIO/gpio_me10.c | 17 ++++++++++++++ .../PeriphDrivers/Source/GPIO/gpio_me11.c | 15 +++++++++++++ .../PeriphDrivers/Source/GPIO/gpio_me12.c | 17 ++++++++++++++ .../PeriphDrivers/Source/GPIO/gpio_me13.c | 15 +++++++++++++ .../PeriphDrivers/Source/GPIO/gpio_me14.c | 17 ++++++++++++++ .../PeriphDrivers/Source/GPIO/gpio_me15.c | 15 +++++++++++++ .../PeriphDrivers/Source/GPIO/gpio_me16.c | 15 +++++++++++++ .../PeriphDrivers/Source/GPIO/gpio_me17.c | 17 ++++++++++++++ .../PeriphDrivers/Source/GPIO/gpio_me18.c | 17 ++++++++++++++ .../PeriphDrivers/Source/GPIO/gpio_me20.c | 22 +++++++++++++++++++ .../PeriphDrivers/Source/GPIO/gpio_me21.c | 15 +++++++++++++ .../PeriphDrivers/Source/GPIO/gpio_me55.c | 15 +++++++++++++ .../PeriphDrivers/Source/GPIO/gpio_reva.c | 15 +++++++++++++ .../PeriphDrivers/Source/GPIO/gpio_revb.c | 10 +++++++++ 49 files changed, 794 insertions(+) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32520/Source/system_max32520.c b/Libraries/CMSIS/Device/Maxim/MAX32520/Source/system_max32520.c index b1bde766e36..4fdbbe9bca7 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32520/Source/system_max32520.c +++ b/Libraries/CMSIS/Device/Maxim/MAX32520/Source/system_max32520.c @@ -91,6 +91,17 @@ __weak int PreInit(void) return 0; } +/* This function is called before the Board_Init function. This weak + * implementation does nothing, but you may over-ride this function in your + * program if you want to configure the state of all pins prior to the + * application running. This is useful when using external tools (like a + * Pin Mux configuration tool) that generate code to initialize the pins. + */ +__weak void PinInit(void) +{ + /* Do nothing */ +} + /* This function can be implemented by the application to initialize the board */ __weak int Board_Init(void) { @@ -139,5 +150,6 @@ __weak void SystemInit(void) MXC_GPIO1->pdpu_sel0 |= 0xFFFFFFFF; MXC_GPIO1->pdpu_sel1 &= ~(0xFFFFFFFF); + PinInit(); Board_Init(); } diff --git a/Libraries/CMSIS/Device/Maxim/MAX32570/Source/system_max32570.c b/Libraries/CMSIS/Device/Maxim/MAX32570/Source/system_max32570.c index 40d3596fc93..8c0fc6d125d 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32570/Source/system_max32570.c +++ b/Libraries/CMSIS/Device/Maxim/MAX32570/Source/system_max32570.c @@ -97,6 +97,17 @@ __weak int PreInit(void) return 0; } +/* This function is called before the Board_Init function. This weak + * implementation does nothing, but you may over-ride this function in your + * program if you want to configure the state of all pins prior to the + * application running. This is useful when using external tools (like a + * Pin Mux configuration tool) that generate code to initialize the pins. + */ +__weak void PinInit(void) +{ + /* Do nothing */ +} + /* This function can be implemented by the application to initialize the board */ __weak int Board_Init(void) { @@ -138,5 +149,6 @@ __weak void SystemInit(void) MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO0); MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO1); + PinInit(); Board_Init(); } diff --git a/Libraries/CMSIS/Device/Maxim/MAX32572/Source/system_max32572.c b/Libraries/CMSIS/Device/Maxim/MAX32572/Source/system_max32572.c index eb905848ac3..13d09951ed1 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32572/Source/system_max32572.c +++ b/Libraries/CMSIS/Device/Maxim/MAX32572/Source/system_max32572.c @@ -97,6 +97,17 @@ __weak int PreInit(void) return 0; } +/* This function is called before the Board_Init function. This weak + * implementation does nothing, but you may over-ride this function in your + * program if you want to configure the state of all pins prior to the + * application running. This is useful when using external tools (like a + * Pin Mux configuration tool) that generate code to initialize the pins. + */ +__weak void PinInit(void) +{ + /* Do nothing */ +} + /* This function can be implemented by the application to initialize the board */ __weak int Board_Init(void) { @@ -139,5 +150,6 @@ __weak void SystemInit(void) MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO0); MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO1); + PinInit(); Board_Init(); } diff --git a/Libraries/CMSIS/Device/Maxim/MAX32650/Source/system_max32650.c b/Libraries/CMSIS/Device/Maxim/MAX32650/Source/system_max32650.c index e50743a909e..567c6ca19d7 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32650/Source/system_max32650.c +++ b/Libraries/CMSIS/Device/Maxim/MAX32650/Source/system_max32650.c @@ -96,6 +96,17 @@ __weak int PreInit(void) return 0; } +/* This function is called before the Board_Init function. This weak + * implementation does nothing, but you may over-ride this function in your + * program if you want to configure the state of all pins prior to the + * application running. This is useful when using external tools (like a + * Pin Mux configuration tool) that generate code to initialize the pins. + */ +__weak void PinInit(void) +{ + /* Do nothing */ +} + /* This function can be implemented by the application to initialize the board */ __weak int Board_Init(void) { @@ -177,6 +188,7 @@ __weak void SystemInit(void) MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2S); MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SPIXIPR); + PinInit(); Board_Init(); } diff --git a/Libraries/CMSIS/Device/Maxim/MAX32655/Source/system_max32655.c b/Libraries/CMSIS/Device/Maxim/MAX32655/Source/system_max32655.c index 8b058431ce8..d269e39c513 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32655/Source/system_max32655.c +++ b/Libraries/CMSIS/Device/Maxim/MAX32655/Source/system_max32655.c @@ -114,6 +114,17 @@ __weak int PreInit(void) return 0; } +/* This function is called before the Board_Init function. This weak + * implementation does nothing, but you may over-ride this function in your + * program if you want to configure the state of all pins prior to the + * application running. This is useful when using external tools (like a + * Pin Mux configuration tool) that generate code to initialize the pins. + */ +__weak void PinInit(void) +{ + /* Do nothing */ +} + /* This function can be implemented by the application to initialize the board */ __weak int Board_Init(void) { @@ -164,6 +175,7 @@ __weak void SystemInit(void) MXC_SYS_SetClockDiv(MXC_SYS_CLOCK_DIV_1); SystemCoreClockUpdate(); + PinInit(); Board_Init(); PalSysInit(); diff --git a/Libraries/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c b/Libraries/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c index 36f669c7b2e..bb818302ff5 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c +++ b/Libraries/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c @@ -97,6 +97,17 @@ __weak int PreInit(void) return 0; } +/* This function is called before the Board_Init function. This weak + * implementation does nothing, but you may over-ride this function in your + * program if you want to configure the state of all pins prior to the + * application running. This is useful when using external tools (like a + * Pin Mux configuration tool) that generate code to initialize the pins. + */ +__weak void PinInit(void) +{ + /* Do nothing */ +} + /* This function can be implemented by the application to initialize the board */ __weak int Board_Init(void) { @@ -142,6 +153,7 @@ __weak void SystemInit(void) MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR2); MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C1); + PinInit(); Board_Init(); } diff --git a/Libraries/CMSIS/Device/Maxim/MAX32662/Source/system_max32662.c b/Libraries/CMSIS/Device/Maxim/MAX32662/Source/system_max32662.c index 9053e557baf..1d0fcd037d4 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32662/Source/system_max32662.c +++ b/Libraries/CMSIS/Device/Maxim/MAX32662/Source/system_max32662.c @@ -121,6 +121,17 @@ __weak int PreInit(void) return 0; } +/* This function is called before the Board_Init function. This weak + * implementation does nothing, but you may over-ride this function in your + * program if you want to configure the state of all pins prior to the + * application running. This is useful when using external tools (like a + * Pin Mux configuration tool) that generate code to initialize the pins. + */ +__weak void PinInit(void) +{ + /* Do nothing */ +} + /* This function can be implemented by the application to initialize the board */ __weak int Board_Init(void) { @@ -161,6 +172,7 @@ __weak void SystemInit(void) MXC_SYS_Clock_Select(MXC_SYS_CLOCK_IPO); SystemCoreClockUpdate(); + PinInit(); Board_Init(); __enable_irq(); diff --git a/Libraries/CMSIS/Device/Maxim/MAX32665/Source/system_max32665.c b/Libraries/CMSIS/Device/Maxim/MAX32665/Source/system_max32665.c index ced360ab52a..a7e5bb1411c 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32665/Source/system_max32665.c +++ b/Libraries/CMSIS/Device/Maxim/MAX32665/Source/system_max32665.c @@ -120,6 +120,17 @@ __weak int PreInit(void) return 0; } +/* This function is called before the Board_Init function. This weak + * implementation does nothing, but you may over-ride this function in your + * program if you want to configure the state of all pins prior to the + * application running. This is useful when using external tools (like a + * Pin Mux configuration tool) that generate code to initialize the pins. + */ +__weak void PinInit(void) +{ + /* Do nothing */ +} + // This function can be implemented by the application to initialize the board __weak int Board_Init(void) { @@ -191,6 +202,7 @@ __weak void SystemInit(void) /* Disable fast wakeup due to issues with SIMO in wakeup */ MXC_PWRSEQ->lpcn &= ~MXC_F_PWRSEQ_LPCN_FWKM; + PinInit(); Board_Init(); PalSysInit(); diff --git a/Libraries/CMSIS/Device/Maxim/MAX32670/Source/system_max32670.c b/Libraries/CMSIS/Device/Maxim/MAX32670/Source/system_max32670.c index e75afb56ae4..7b8b644d6c2 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32670/Source/system_max32670.c +++ b/Libraries/CMSIS/Device/Maxim/MAX32670/Source/system_max32670.c @@ -102,6 +102,17 @@ __weak int PreInit(void) return 0; } +/* This function is called before the Board_Init function. This weak + * implementation does nothing, but you may over-ride this function in your + * program if you want to configure the state of all pins prior to the + * application running. This is useful when using external tools (like a + * Pin Mux configuration tool) that generate code to initialize the pins. + */ +__weak void PinInit(void) +{ + /* Do nothing */ +} + /* This function can be implemented by the application to initialize the board */ __weak int Board_Init(void) { @@ -148,6 +159,7 @@ __weak void SystemInit(void) MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO0); MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO1); + PinInit(); Board_Init(); } diff --git a/Libraries/CMSIS/Device/Maxim/MAX32672/Source/system_max32672.c b/Libraries/CMSIS/Device/Maxim/MAX32672/Source/system_max32672.c index 35991ecc2ca..fbe7fc3b453 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32672/Source/system_max32672.c +++ b/Libraries/CMSIS/Device/Maxim/MAX32672/Source/system_max32672.c @@ -115,6 +115,17 @@ __weak int PreInit(void) return 0; } +/* This function is called before the Board_Init function. This weak + * implementation does nothing, but you may over-ride this function in your + * program if you want to configure the state of all pins prior to the + * application running. This is useful when using external tools (like a + * Pin Mux configuration tool) that generate code to initialize the pins. + */ +__weak void PinInit(void) +{ + /* Do nothing */ +} + /* This function can be implemented by the application to initialize the board */ __weak int Board_Init(void) { @@ -154,5 +165,6 @@ __weak void SystemInit(void) MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO0); MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO1); + PinInit(); Board_Init(); } diff --git a/Libraries/CMSIS/Device/Maxim/MAX32675/Source/system_max32675.c b/Libraries/CMSIS/Device/Maxim/MAX32675/Source/system_max32675.c index fed7e7dcf51..0b9b117f248 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32675/Source/system_max32675.c +++ b/Libraries/CMSIS/Device/Maxim/MAX32675/Source/system_max32675.c @@ -117,6 +117,17 @@ __weak int PreInit(void) return 0; } +/* This function is called before the Board_Init function. This weak + * implementation does nothing, but you may over-ride this function in your + * program if you want to configure the state of all pins prior to the + * application running. This is useful when using external tools (like a + * Pin Mux configuration tool) that generate code to initialize the pins. + */ +__weak void PinInit(void) +{ + /* Do nothing */ +} + /* This function can be implemented by the application to initialize the board */ __weak int Board_Init(void) { @@ -156,6 +167,7 @@ __weak void SystemInit(void) MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO0); MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO1); + PinInit(); Board_Init(); } diff --git a/Libraries/CMSIS/Device/Maxim/MAX32680/Source/system_max32680.c b/Libraries/CMSIS/Device/Maxim/MAX32680/Source/system_max32680.c index fe6af4ed518..33191b596dd 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32680/Source/system_max32680.c +++ b/Libraries/CMSIS/Device/Maxim/MAX32680/Source/system_max32680.c @@ -101,6 +101,17 @@ __weak int PreInit(void) return 0; } +/* This function is called before the Board_Init function. This weak + * implementation does nothing, but you may over-ride this function in your + * program if you want to configure the state of all pins prior to the + * application running. This is useful when using external tools (like a + * Pin Mux configuration tool) that generate code to initialize the pins. + */ +__weak void PinInit(void) +{ + /* Do nothing */ +} + /* This function can be implemented by the application to initialize the board */ __weak int Board_Init(void) { @@ -143,6 +154,7 @@ __weak void SystemInit(void) MXC_SYS_SetClockDiv(MXC_SYS_CLOCK_DIV_1); SystemCoreClockUpdate(); + PinInit(); Board_Init(); PalSysInit(); diff --git a/Libraries/CMSIS/Device/Maxim/MAX32690/Source/system_max32690.c b/Libraries/CMSIS/Device/Maxim/MAX32690/Source/system_max32690.c index a5c3297c271..08c66bc3094 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32690/Source/system_max32690.c +++ b/Libraries/CMSIS/Device/Maxim/MAX32690/Source/system_max32690.c @@ -100,6 +100,17 @@ __weak int PreInit(void) return 0; } +/* This function is called before the Board_Init function. This weak + * implementation does nothing, but you may over-ride this function in your + * program if you want to configure the state of all pins prior to the + * application running. This is useful when using external tools (like a + * Pin Mux configuration tool) that generate code to initialize the pins. + */ +__weak void PinInit(void) +{ + /* Do nothing */ +} + /* This function can be implemented by the application to initialize the board */ __weak int Board_Init(void) { @@ -150,6 +161,7 @@ __weak void SystemInit(void) PalSysInit(); + PinInit(); Board_Init(); __enable_irq(); diff --git a/Libraries/CMSIS/Device/Maxim/MAX78000/Source/system_max78000.c b/Libraries/CMSIS/Device/Maxim/MAX78000/Source/system_max78000.c index 21cbe33328b..2b05de216cc 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78000/Source/system_max78000.c +++ b/Libraries/CMSIS/Device/Maxim/MAX78000/Source/system_max78000.c @@ -97,6 +97,17 @@ __weak int PreInit(void) return 0; } +/* This function is called before the Board_Init function. This weak + * implementation does nothing, but you may over-ride this function in your + * program if you want to configure the state of all pins prior to the + * application running. This is useful when using external tools (like a + * Pin Mux configuration tool) that generate code to initialize the pins. + */ +__weak void PinInit(void) +{ + /* Do nothing */ +} + /* This function can be implemented by the application to initialize the board */ __weak int Board_Init(void) { @@ -131,5 +142,6 @@ __weak void SystemInit(void) SystemCoreClockUpdate(); + PinInit(); Board_Init(); } diff --git a/Libraries/CMSIS/Device/Maxim/MAX78002/Source/system_max78002.c b/Libraries/CMSIS/Device/Maxim/MAX78002/Source/system_max78002.c index 080d75b42a5..1f153a3bd0b 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78002/Source/system_max78002.c +++ b/Libraries/CMSIS/Device/Maxim/MAX78002/Source/system_max78002.c @@ -102,6 +102,17 @@ __weak int PreInit(void) return 0; } +/* This function is called before the Board_Init function. This weak + * implementation does nothing, but you may over-ride this function in your + * program if you want to configure the state of all pins prior to the + * application running. This is useful when using external tools (like a + * Pin Mux configuration tool) that generate code to initialize the pins. + */ +__weak void PinInit(void) +{ + /* Do nothing */ +} + /* This function can be implemented by the application to initialize the board */ __weak int Board_Init(void) { @@ -133,5 +144,6 @@ __weak void SystemInit(void) SystemCoreClockUpdate(); + PinInit(); Board_Init(); } diff --git a/Libraries/PeriphDrivers/Include/MAX32520/gpio.h b/Libraries/PeriphDrivers/Include/MAX32520/gpio.h index e4f4eb499c1..9a2b4da6130 100644 --- a/Libraries/PeriphDrivers/Include/MAX32520/gpio.h +++ b/Libraries/PeriphDrivers/Include/MAX32520/gpio.h @@ -190,6 +190,14 @@ typedef enum { MXC_GPIO_INT_BOTH ///< Interrupt triggers on either edge } mxc_gpio_int_pol_t; +/** + * @brief Enumeration type for the pin configuration lock mechanism. + */ +typedef enum { + MXC_GPIO_CONFIG_UNLOCKED = 0, /**< Allow changing pins' configuration. */ + MXC_GPIO_CONFIG_LOCKED, /**< Ignore changes to a pin's configuration. */ +} mxc_gpio_config_lock_t; + /* **** Function Prototypes **** */ /** @@ -373,6 +381,20 @@ uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port); */ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, uint32_t mask); +/** + * @brief Enables/Disables the lock on all pins' configurations. If + * locked, any changes to a pin's configuration made through the + * MXC_GPIO_Config function will be ignored. + * + * @param locked Determines if changes will be allowed. */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked); + +/** + * @brief Reads the current lock state on pin configuration. + * + * @returns The lock state. */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void); + /**@} end of group gpio */ #ifdef __cplusplus diff --git a/Libraries/PeriphDrivers/Include/MAX32570/gpio.h b/Libraries/PeriphDrivers/Include/MAX32570/gpio.h index 16d643f9459..51698a6bc24 100644 --- a/Libraries/PeriphDrivers/Include/MAX32570/gpio.h +++ b/Libraries/PeriphDrivers/Include/MAX32570/gpio.h @@ -190,6 +190,14 @@ typedef enum { MXC_GPIO_INT_BOTH ///< Interrupt triggers on either edge } mxc_gpio_int_pol_t; +/** + * @brief Enumeration type for the pin configuration lock mechanism. + */ +typedef enum { + MXC_GPIO_CONFIG_UNLOCKED = 0, /**< Allow changing pins' configuration. */ + MXC_GPIO_CONFIG_LOCKED, /**< Ignore changes to a pin's configuration. */ +} mxc_gpio_config_lock_t; + /* **** Function Prototypes **** */ /** @@ -373,6 +381,20 @@ uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port); */ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, uint32_t mask); +/** + * @brief Enables/Disables the lock on all pins' configurations. If + * locked, any changes to a pin's configuration made through the + * MXC_GPIO_Config function will be ignored. + * + * @param locked Determines if changes will be allowed. */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked); + +/** + * @brief Reads the current lock state on pin configuration. + * + * @returns The lock state. */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void); + /**@} end of group gpio */ #ifdef __cplusplus diff --git a/Libraries/PeriphDrivers/Include/MAX32572/gpio.h b/Libraries/PeriphDrivers/Include/MAX32572/gpio.h index 6160c4d7007..bedf6886cdb 100644 --- a/Libraries/PeriphDrivers/Include/MAX32572/gpio.h +++ b/Libraries/PeriphDrivers/Include/MAX32572/gpio.h @@ -191,6 +191,14 @@ typedef enum { MXC_GPIO_INT_BOTH ///< Interrupt triggers on either edge } mxc_gpio_int_pol_t; +/** + * @brief Enumeration type for the pin configuration lock mechanism. + */ +typedef enum { + MXC_GPIO_CONFIG_UNLOCKED = 0, /**< Allow changing pins' configuration. */ + MXC_GPIO_CONFIG_LOCKED, /**< Ignore changes to a pin's configuration. */ +} mxc_gpio_config_lock_t; + /* **** Function Prototypes **** */ /** @@ -374,6 +382,20 @@ uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port); */ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, uint32_t mask); +/** + * @brief Enables/Disables the lock on all pins' configurations. If + * locked, any changes to a pin's configuration made through the + * MXC_GPIO_Config function will be ignored. + * + * @param locked Determines if changes will be allowed. */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked); + +/** + * @brief Reads the current lock state on pin configuration. + * + * @returns The lock state. */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void); + /**@} end of group gpio */ #ifdef __cplusplus diff --git a/Libraries/PeriphDrivers/Include/MAX32650/gpio.h b/Libraries/PeriphDrivers/Include/MAX32650/gpio.h index fe8d78730e5..709ec65afa9 100644 --- a/Libraries/PeriphDrivers/Include/MAX32650/gpio.h +++ b/Libraries/PeriphDrivers/Include/MAX32650/gpio.h @@ -180,6 +180,14 @@ typedef enum { MXC_GPIO_INT_BOTH /**< Interrupt triggers on either edge */ } mxc_gpio_int_pol_t; +/** + * @brief Enumeration type for the pin configuration lock mechanism. + */ +typedef enum { + MXC_GPIO_CONFIG_UNLOCKED = 0, /**< Allow changing pins' configuration. */ + MXC_GPIO_CONFIG_LOCKED, /**< Ignore changes to a pin's configuration. */ +} mxc_gpio_config_lock_t; + /* **** Function Prototypes **** */ /** @@ -367,6 +375,20 @@ uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port); */ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, uint32_t mask); +/** + * @brief Enables/Disables the lock on all pins' configurations. If + * locked, any changes to a pin's configuration made through the + * MXC_GPIO_Config function will be ignored. + * + * @param locked Determines if changes will be allowed. */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked); + +/** + * @brief Reads the current lock state on pin configuration. + * + * @returns The lock state. */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void); + /**@} end of group gpio */ #ifdef __cplusplus diff --git a/Libraries/PeriphDrivers/Include/MAX32655/gpio.h b/Libraries/PeriphDrivers/Include/MAX32655/gpio.h index 14d13cf992d..9b51de8d4a7 100644 --- a/Libraries/PeriphDrivers/Include/MAX32655/gpio.h +++ b/Libraries/PeriphDrivers/Include/MAX32655/gpio.h @@ -190,6 +190,14 @@ typedef enum { MXC_GPIO_INT_BOTH /**< Interrupt triggers on either edge */ } mxc_gpio_int_pol_t; +/** + * @brief Enumeration type for the pin configuration lock mechanism. + */ +typedef enum { + MXC_GPIO_CONFIG_UNLOCKED = 0, /**< Allow changing pins' configuration. */ + MXC_GPIO_CONFIG_LOCKED, /**< Ignore changes to a pin's configuration. */ +} mxc_gpio_config_lock_t; + /* **** Function Prototypes **** */ /** @@ -369,6 +377,20 @@ uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port); */ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, uint32_t mask); +/** + * @brief Enables/Disables the lock on all pins' configurations. If + * locked, any changes to a pin's configuration made through the + * MXC_GPIO_Config function will be ignored. + * + * @param locked Determines if changes will be allowed. */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked); + +/** + * @brief Reads the current lock state on pin configuration. + * + * @returns The lock state. */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void); + /**@} end of group gpio */ #ifdef __cplusplus diff --git a/Libraries/PeriphDrivers/Include/MAX32660/gpio.h b/Libraries/PeriphDrivers/Include/MAX32660/gpio.h index 0ec9e92ef33..abdfbfb0666 100644 --- a/Libraries/PeriphDrivers/Include/MAX32660/gpio.h +++ b/Libraries/PeriphDrivers/Include/MAX32660/gpio.h @@ -169,6 +169,14 @@ typedef enum { MXC_GPIO_INT_BOTH ///< Interrupt triggers on either edge } mxc_gpio_int_pol_t; +/** + * @brief Enumeration type for the pin configuration lock mechanism. + */ +typedef enum { + MXC_GPIO_CONFIG_UNLOCKED = 0, /**< Allow changing pins' configuration. */ + MXC_GPIO_CONFIG_LOCKED, /**< Ignore changes to a pin's configuration. */ +} mxc_gpio_config_lock_t; + /* **** Function Prototypes **** */ /** @@ -350,6 +358,20 @@ uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port); */ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, uint32_t mask); +/** + * @brief Enables/Disables the lock on all pins' configurations. If + * locked, any changes to a pin's configuration made through the + * MXC_GPIO_Config function will be ignored. + * + * @param locked Determines if changes will be allowed. */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked); + +/** + * @brief Reads the current lock state on pin configuration. + * + * @returns The lock state. */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void); + /**@} end of group gpio */ #ifdef __cplusplus diff --git a/Libraries/PeriphDrivers/Include/MAX32662/gpio.h b/Libraries/PeriphDrivers/Include/MAX32662/gpio.h index d3131883a60..dfe4ff2ffbd 100644 --- a/Libraries/PeriphDrivers/Include/MAX32662/gpio.h +++ b/Libraries/PeriphDrivers/Include/MAX32662/gpio.h @@ -189,6 +189,14 @@ typedef enum { MXC_GPIO_INT_BOTH /**< Interrupt triggers on either edge */ } mxc_gpio_int_pol_t; +/** + * @brief Enumeration type for the pin configuration lock mechanism. + */ +typedef enum { + MXC_GPIO_CONFIG_UNLOCKED = 0, /**< Allow changing pins' configuration. */ + MXC_GPIO_CONFIG_LOCKED, /**< Ignore changes to a pin's configuration. */ +} mxc_gpio_config_lock_t; + /* **** Function Prototypes **** */ /** @@ -368,6 +376,20 @@ uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port); */ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, uint32_t mask); +/** + * @brief Enables/Disables the lock on all pins' configurations. If + * locked, any changes to a pin's configuration made through the + * MXC_GPIO_Config function will be ignored. + * + * @param locked Determines if changes will be allowed. */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked); + +/** + * @brief Reads the current lock state on pin configuration. + * + * @returns The lock state. */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void); + /**@} end of group gpio */ #ifdef __cplusplus diff --git a/Libraries/PeriphDrivers/Include/MAX32665/gpio.h b/Libraries/PeriphDrivers/Include/MAX32665/gpio.h index 4931988d60b..8f68f8f0ef0 100644 --- a/Libraries/PeriphDrivers/Include/MAX32665/gpio.h +++ b/Libraries/PeriphDrivers/Include/MAX32665/gpio.h @@ -189,6 +189,14 @@ typedef enum { MXC_GPIO_INT_BOTH /**< Interrupt triggers on either edge */ } mxc_gpio_int_pol_t; +/** + * @brief Enumeration type for the pin configuration lock mechanism. + */ +typedef enum { + MXC_GPIO_CONFIG_UNLOCKED = 0, /**< Allow changing pins' configuration. */ + MXC_GPIO_CONFIG_LOCKED, /**< Ignore changes to a pin's configuration. */ +} mxc_gpio_config_lock_t; + /* **** Function Prototypes **** */ /** @@ -372,6 +380,20 @@ uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port); */ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, uint32_t mask); +/** + * @brief Enables/Disables the lock on all pins' configurations. If + * locked, any changes to a pin's configuration made through the + * MXC_GPIO_Config function will be ignored. + * + * @param locked Determines if changes will be allowed. */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked); + +/** + * @brief Reads the current lock state on pin configuration. + * + * @returns The lock state. */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void); + /**@} end of group gpio */ #ifdef __cplusplus diff --git a/Libraries/PeriphDrivers/Include/MAX32670/gpio.h b/Libraries/PeriphDrivers/Include/MAX32670/gpio.h index d8933256ed9..de6ea6efa9e 100644 --- a/Libraries/PeriphDrivers/Include/MAX32670/gpio.h +++ b/Libraries/PeriphDrivers/Include/MAX32670/gpio.h @@ -190,6 +190,14 @@ typedef enum { MXC_GPIO_INT_BOTH ///< Interrupt triggers on either edge } mxc_gpio_int_pol_t; +/** + * @brief Enumeration type for the pin configuration lock mechanism. + */ +typedef enum { + MXC_GPIO_CONFIG_UNLOCKED = 0, /**< Allow changing pins' configuration. */ + MXC_GPIO_CONFIG_LOCKED, /**< Ignore changes to a pin's configuration. */ +} mxc_gpio_config_lock_t; + /* **** Function Prototypes **** */ /** @@ -371,6 +379,20 @@ uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port); */ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, uint32_t mask); +/** + * @brief Enables/Disables the lock on all pins' configurations. If + * locked, any changes to a pin's configuration made through the + * MXC_GPIO_Config function will be ignored. + * + * @param locked Determines if changes will be allowed. */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked); + +/** + * @brief Reads the current lock state on pin configuration. + * + * @returns The lock state. */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void); + /**@} end of group gpio */ #ifdef __cplusplus diff --git a/Libraries/PeriphDrivers/Include/MAX32672/gpio.h b/Libraries/PeriphDrivers/Include/MAX32672/gpio.h index 97b7983436a..496b33f92b0 100644 --- a/Libraries/PeriphDrivers/Include/MAX32672/gpio.h +++ b/Libraries/PeriphDrivers/Include/MAX32672/gpio.h @@ -190,6 +190,14 @@ typedef enum { MXC_GPIO_INT_BOTH ///< Interrupt triggers on either edge } mxc_gpio_int_pol_t; +/** + * @brief Enumeration type for the pin configuration lock mechanism. + */ +typedef enum { + MXC_GPIO_CONFIG_UNLOCKED = 0, /**< Allow changing pins' configuration. */ + MXC_GPIO_CONFIG_LOCKED, /**< Ignore changes to a pin's configuration. */ +} mxc_gpio_config_lock_t; + /* **** Function Prototypes **** */ /** @@ -371,6 +379,20 @@ uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port); */ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, uint32_t mask); +/** + * @brief Enables/Disables the lock on all pins' configurations. If + * locked, any changes to a pin's configuration made through the + * MXC_GPIO_Config function will be ignored. + * + * @param locked Determines if changes will be allowed. */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked); + +/** + * @brief Reads the current lock state on pin configuration. + * + * @returns The lock state. */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void); + /**@} end of group gpio */ #ifdef __cplusplus diff --git a/Libraries/PeriphDrivers/Include/MAX32675/gpio.h b/Libraries/PeriphDrivers/Include/MAX32675/gpio.h index 661becff7a2..dbfe5c0ea22 100644 --- a/Libraries/PeriphDrivers/Include/MAX32675/gpio.h +++ b/Libraries/PeriphDrivers/Include/MAX32675/gpio.h @@ -190,6 +190,14 @@ typedef enum { MXC_GPIO_INT_BOTH ///< Interrupt triggers on either edge } mxc_gpio_int_pol_t; +/** + * @brief Enumeration type for the pin configuration lock mechanism. + */ +typedef enum { + MXC_GPIO_CONFIG_UNLOCKED = 0, /**< Allow changing pins' configuration. */ + MXC_GPIO_CONFIG_LOCKED, /**< Ignore changes to a pin's configuration. */ +} mxc_gpio_config_lock_t; + /* **** Function Prototypes **** */ /** @@ -371,6 +379,20 @@ uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port); */ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, uint32_t mask); +/** + * @brief Enables/Disables the lock on all pins' configurations. If + * locked, any changes to a pin's configuration made through the + * MXC_GPIO_Config function will be ignored. + * + * @param locked Determines if changes will be allowed. */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked); + +/** + * @brief Reads the current lock state on pin configuration. + * + * @returns The lock state. */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void); + /**@} end of group gpio */ #ifdef __cplusplus diff --git a/Libraries/PeriphDrivers/Include/MAX32680/gpio.h b/Libraries/PeriphDrivers/Include/MAX32680/gpio.h index 8b6bbfd3b46..071f6d1bd59 100644 --- a/Libraries/PeriphDrivers/Include/MAX32680/gpio.h +++ b/Libraries/PeriphDrivers/Include/MAX32680/gpio.h @@ -190,6 +190,14 @@ typedef enum { MXC_GPIO_INT_BOTH /**< Interrupt triggers on either edge */ } mxc_gpio_int_pol_t; +/** + * @brief Enumeration type for the pin configuration lock mechanism. + */ +typedef enum { + MXC_GPIO_CONFIG_UNLOCKED = 0, /**< Allow changing pins' configuration. */ + MXC_GPIO_CONFIG_LOCKED, /**< Ignore changes to a pin's configuration. */ +} mxc_gpio_config_lock_t; + /* **** Function Prototypes **** */ /** @@ -369,6 +377,20 @@ uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port); */ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, uint32_t mask); +/** + * @brief Enables/Disables the lock on all pins' configurations. If + * locked, any changes to a pin's configuration made through the + * MXC_GPIO_Config function will be ignored. + * + * @param locked Determines if changes will be allowed. */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked); + +/** + * @brief Reads the current lock state on pin configuration. + * + * @returns The lock state. */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void); + /**@} end of group gpio */ #ifdef __cplusplus diff --git a/Libraries/PeriphDrivers/Include/MAX32690/gpio.h b/Libraries/PeriphDrivers/Include/MAX32690/gpio.h index 9f93da57f55..096bd839f3e 100644 --- a/Libraries/PeriphDrivers/Include/MAX32690/gpio.h +++ b/Libraries/PeriphDrivers/Include/MAX32690/gpio.h @@ -191,6 +191,14 @@ typedef enum { MXC_GPIO_INT_BOTH /**< Interrupt triggers on either edge */ } mxc_gpio_int_pol_t; +/** + * @brief Enumeration type for the pin configuration lock mechanism. + */ +typedef enum { + MXC_GPIO_CONFIG_UNLOCKED = 0, /**< Allow changing pins' configuration. */ + MXC_GPIO_CONFIG_LOCKED, /**< Ignore changes to a pin's configuration. */ +} mxc_gpio_config_lock_t; + /* **** Function Prototypes **** */ /** @@ -370,6 +378,20 @@ uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port); */ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, uint32_t mask); +/** + * @brief Enables/Disables the lock on all pins' configurations. If + * locked, any changes to a pin's configuration made through the + * MXC_GPIO_Config function will be ignored. + * + * @param locked Determines if changes will be allowed. */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked); + +/** + * @brief Reads the current lock state on pin configuration. + * + * @returns The lock state. */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void); + /**@} end of group gpio */ #ifdef __cplusplus diff --git a/Libraries/PeriphDrivers/Include/MAX78000/gpio.h b/Libraries/PeriphDrivers/Include/MAX78000/gpio.h index 3d33787bd67..b97fd17e7c9 100644 --- a/Libraries/PeriphDrivers/Include/MAX78000/gpio.h +++ b/Libraries/PeriphDrivers/Include/MAX78000/gpio.h @@ -190,6 +190,14 @@ typedef enum { MXC_GPIO_INT_BOTH /**< Interrupt triggers on either edge */ } mxc_gpio_int_pol_t; +/** + * @brief Enumeration type for the pin configuration lock mechanism. + */ +typedef enum { + MXC_GPIO_CONFIG_UNLOCKED = 0, /**< Allow changing pins' configuration. */ + MXC_GPIO_CONFIG_LOCKED, /**< Ignore changes to a pin's configuration. */ +} mxc_gpio_config_lock_t; + /* **** Function Prototypes **** */ /** @@ -371,6 +379,20 @@ uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port); */ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, uint32_t mask); +/** + * @brief Enables/Disables the lock on all pins' configurations. If + * locked, any changes to a pin's configuration made through the + * MXC_GPIO_Config function will be ignored. + * + * @param locked Determines if changes will be allowed. */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked); + +/** + * @brief Reads the current lock state on pin configuration. + * + * @returns The lock state. */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void); + /**@} end of group gpio */ #ifdef __cplusplus diff --git a/Libraries/PeriphDrivers/Include/MAX78002/gpio.h b/Libraries/PeriphDrivers/Include/MAX78002/gpio.h index 42203ee4f48..218a7dda19e 100644 --- a/Libraries/PeriphDrivers/Include/MAX78002/gpio.h +++ b/Libraries/PeriphDrivers/Include/MAX78002/gpio.h @@ -190,6 +190,14 @@ typedef enum { MXC_GPIO_INT_BOTH /**< Interrupt triggers on either edge */ } mxc_gpio_int_pol_t; +/** + * @brief Enumeration type for the pin configuration lock mechanism. + */ +typedef enum { + MXC_GPIO_CONFIG_UNLOCKED = 0, /**< Allow changing pins' configuration. */ + MXC_GPIO_CONFIG_LOCKED, /**< Ignore changes to a pin's configuration. */ +} mxc_gpio_config_lock_t; + /* **** Function Prototypes **** */ /** @@ -369,6 +377,20 @@ uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port); */ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, uint32_t mask); +/** + * @brief Enables/Disables the lock on all pins' configurations. If + * locked, any changes to a pin's configuration made through the + * MXC_GPIO_Config function will be ignored. + * + * @param locked Determines if changes will be allowed. */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked); + +/** + * @brief Reads the current lock state on pin configuration. + * + * @returns The lock state. */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void); + /**@} end of group gpio */ #ifdef __cplusplus diff --git a/Libraries/PeriphDrivers/Source/GPIO/gpio_ai85.c b/Libraries/PeriphDrivers/Source/GPIO/gpio_ai85.c index a6c5c31a9d8..e586e496114 100644 --- a/Libraries/PeriphDrivers/Source/GPIO/gpio_ai85.c +++ b/Libraries/PeriphDrivers/Source/GPIO/gpio_ai85.c @@ -109,6 +109,11 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) MXC_GPIO_Init(1 << port); + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + // Configure the vssel error = MXC_GPIO_SetVSSEL(gpio, cfg->vssel, cfg->mask); if (error != E_NO_ERROR) { @@ -413,3 +418,15 @@ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, u { return MXC_GPIO_RevA_SetDriveStrength((mxc_gpio_reva_regs_t *)port, drvstr, mask); } + +/* ************************************************************************** */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked) +{ + MXC_GPIO_Common_SetConfigLock(locked); +} + +/* ************************************************************************** */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void) +{ + return MXC_GPIO_Common_GetConfigLock(); +} diff --git a/Libraries/PeriphDrivers/Source/GPIO/gpio_ai87.c b/Libraries/PeriphDrivers/Source/GPIO/gpio_ai87.c index a6c5c31a9d8..e586e496114 100644 --- a/Libraries/PeriphDrivers/Source/GPIO/gpio_ai87.c +++ b/Libraries/PeriphDrivers/Source/GPIO/gpio_ai87.c @@ -109,6 +109,11 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) MXC_GPIO_Init(1 << port); + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + // Configure the vssel error = MXC_GPIO_SetVSSEL(gpio, cfg->vssel, cfg->mask); if (error != E_NO_ERROR) { @@ -413,3 +418,15 @@ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, u { return MXC_GPIO_RevA_SetDriveStrength((mxc_gpio_reva_regs_t *)port, drvstr, mask); } + +/* ************************************************************************** */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked) +{ + MXC_GPIO_Common_SetConfigLock(locked); +} + +/* ************************************************************************** */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void) +{ + return MXC_GPIO_Common_GetConfigLock(); +} diff --git a/Libraries/PeriphDrivers/Source/GPIO/gpio_common.c b/Libraries/PeriphDrivers/Source/GPIO/gpio_common.c index fad63225a52..e5717e2aea6 100644 --- a/Libraries/PeriphDrivers/Source/GPIO/gpio_common.c +++ b/Libraries/PeriphDrivers/Source/GPIO/gpio_common.c @@ -29,6 +29,7 @@ static void (*callback[MXC_CFG_GPIO_INSTANCES][MXC_CFG_GPIO_PINS_PORT])(void *); static void *cbparam[MXC_CFG_GPIO_INSTANCES][MXC_CFG_GPIO_PINS_PORT]; static uint8_t initialized = 0; +static mxc_gpio_config_lock_t cfg_lock = MXC_GPIO_CONFIG_UNLOCKED; /* **** Functions **** */ int MXC_GPIO_Common_Init(uint32_t portmask) @@ -94,3 +95,13 @@ void MXC_GPIO_Common_Handler(unsigned int port) stat >>= 1; } } + +void MXC_GPIO_Common_SetConfigLock(mxc_gpio_config_lock_t locked) +{ + cfg_lock = locked; +} + +mxc_gpio_config_lock_t MXC_GPIO_Common_GetConfigLock(void) +{ + return cfg_lock; +} diff --git a/Libraries/PeriphDrivers/Source/GPIO/gpio_common.h b/Libraries/PeriphDrivers/Source/GPIO/gpio_common.h index ac5cdd5efa6..ecef4865ded 100644 --- a/Libraries/PeriphDrivers/Source/GPIO/gpio_common.h +++ b/Libraries/PeriphDrivers/Source/GPIO/gpio_common.h @@ -35,6 +35,8 @@ int MXC_GPIO_Common_Init(uint32_t portmask); void MXC_GPIO_Common_RegisterCallback(const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn callback, void *cbdata); void MXC_GPIO_Common_Handler(unsigned int port); +void MXC_GPIO_Common_SetConfigLock(mxc_gpio_config_lock_t locked); +mxc_gpio_config_lock_t MXC_GPIO_Common_GetConfigLock(void); /**@} end of group gpio */ diff --git a/Libraries/PeriphDrivers/Source/GPIO/gpio_es17.c b/Libraries/PeriphDrivers/Source/GPIO/gpio_es17.c index f741c1b6e73..96fbd2b118c 100644 --- a/Libraries/PeriphDrivers/Source/GPIO/gpio_es17.c +++ b/Libraries/PeriphDrivers/Source/GPIO/gpio_es17.c @@ -74,6 +74,11 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) int error; mxc_gpio_regs_t *gpio = cfg->port; + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + // Configure the vssel error = MXC_GPIO_SetVSSEL(gpio, cfg->vssel, cfg->mask); if (error != E_NO_ERROR) { @@ -219,3 +224,13 @@ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, u { return MXC_GPIO_RevA_SetDriveStrength((mxc_gpio_reva_regs_t *)port, drvstr, mask); } + +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked) +{ + MXC_GPIO_Common_SetConfigLock(locked); +} + +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void) +{ + return MXC_GPIO_Common_GetConfigLock(); +} diff --git a/Libraries/PeriphDrivers/Source/GPIO/gpio_me10.c b/Libraries/PeriphDrivers/Source/GPIO/gpio_me10.c index 83c5bf208ac..46740343680 100644 --- a/Libraries/PeriphDrivers/Source/GPIO/gpio_me10.c +++ b/Libraries/PeriphDrivers/Source/GPIO/gpio_me10.c @@ -101,6 +101,11 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) int err; mxc_gpio_regs_t *gpio = cfg->port; + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + // Configure the vssel err = MXC_GPIO_SetVSSEL(gpio, cfg->vssel, cfg->mask); if (err != E_NO_ERROR) { @@ -259,3 +264,15 @@ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, u { return MXC_GPIO_RevA_SetDriveStrength((mxc_gpio_reva_regs_t *)port, drvstr, mask); } + +/* ************************************************************************** */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked) +{ + MXC_GPIO_Common_SetConfigLock(locked); +} + +/* ************************************************************************** */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void) +{ + return MXC_GPIO_Common_GetConfigLock(); +} diff --git a/Libraries/PeriphDrivers/Source/GPIO/gpio_me11.c b/Libraries/PeriphDrivers/Source/GPIO/gpio_me11.c index 91fb1548dcc..b6ed678b9ce 100644 --- a/Libraries/PeriphDrivers/Source/GPIO/gpio_me11.c +++ b/Libraries/PeriphDrivers/Source/GPIO/gpio_me11.c @@ -62,6 +62,11 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) int error; mxc_gpio_regs_t *gpio = cfg->port; + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + // Configure the vssel error = MXC_GPIO_SetVSSEL(gpio, cfg->vssel, cfg->mask); if (error != E_NO_ERROR) { @@ -223,3 +228,13 @@ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, u { return MXC_GPIO_RevA_SetDriveStrength((mxc_gpio_reva_regs_t *)port, drvstr, mask); } + +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked) +{ + MXC_GPIO_Common_SetConfigLock(locked); +} + +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void) +{ + return MXC_GPIO_Common_GetConfigLock(); +} diff --git a/Libraries/PeriphDrivers/Source/GPIO/gpio_me12.c b/Libraries/PeriphDrivers/Source/GPIO/gpio_me12.c index 167047828bf..abee1ac3227 100644 --- a/Libraries/PeriphDrivers/Source/GPIO/gpio_me12.c +++ b/Libraries/PeriphDrivers/Source/GPIO/gpio_me12.c @@ -69,6 +69,11 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) port = MXC_GPIO_GET_IDX(cfg->port); MXC_GPIO_Init(1 << port); + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + // Configure the vssel error = MXC_GPIO_SetVSSEL(gpio, cfg->vssel, cfg->mask); if (error != E_NO_ERROR) { @@ -217,3 +222,15 @@ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, u { return MXC_GPIO_RevA_SetDriveStrength((mxc_gpio_reva_regs_t *)port, drvstr, mask); } + +/* ************************************************************************** */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked) +{ + MXC_GPIO_Common_SetConfigLock(locked); +} + +/* ************************************************************************** */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void) +{ + return MXC_GPIO_Common_GetConfigLock(); +} diff --git a/Libraries/PeriphDrivers/Source/GPIO/gpio_me13.c b/Libraries/PeriphDrivers/Source/GPIO/gpio_me13.c index b3f309284bb..3b684e98083 100644 --- a/Libraries/PeriphDrivers/Source/GPIO/gpio_me13.c +++ b/Libraries/PeriphDrivers/Source/GPIO/gpio_me13.c @@ -98,6 +98,11 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) int error; mxc_gpio_regs_t *gpio = cfg->port; + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + // Configure the vssel error = MXC_GPIO_SetVSSEL(gpio, cfg->vssel, cfg->mask); if (error != E_NO_ERROR) { @@ -243,3 +248,13 @@ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, u { return MXC_GPIO_RevA_SetDriveStrength((mxc_gpio_reva_regs_t *)port, drvstr, mask); } + +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked) +{ + MXC_GPIO_Common_SetConfigLock(locked); +} + +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void) +{ + return MXC_GPIO_Common_GetConfigLock(); +} diff --git a/Libraries/PeriphDrivers/Source/GPIO/gpio_me14.c b/Libraries/PeriphDrivers/Source/GPIO/gpio_me14.c index 7803d5f7d7a..2ab67ebb9cb 100644 --- a/Libraries/PeriphDrivers/Source/GPIO/gpio_me14.c +++ b/Libraries/PeriphDrivers/Source/GPIO/gpio_me14.c @@ -78,6 +78,11 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) int error; mxc_gpio_regs_t *gpio = cfg->port; + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + // Configure the vssel error = MXC_GPIO_SetVSSEL(gpio, cfg->vssel, cfg->mask); if (error != E_NO_ERROR) { @@ -236,3 +241,15 @@ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, u { return MXC_GPIO_RevA_SetDriveStrength((mxc_gpio_reva_regs_t *)port, drvstr, mask); } + +/* ************************************************************************** */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked) +{ + MXC_GPIO_Common_SetConfigLock(locked); +} + +/* ************************************************************************** */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void) +{ + return MXC_GPIO_Common_GetConfigLock(); +} diff --git a/Libraries/PeriphDrivers/Source/GPIO/gpio_me15.c b/Libraries/PeriphDrivers/Source/GPIO/gpio_me15.c index 8d49fc89993..09962f49c18 100644 --- a/Libraries/PeriphDrivers/Source/GPIO/gpio_me15.c +++ b/Libraries/PeriphDrivers/Source/GPIO/gpio_me15.c @@ -73,6 +73,11 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) int error; mxc_gpio_regs_t *gpio = cfg->port; + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + // Configure alternate function error = MXC_GPIO_RevA_SetAF((mxc_gpio_reva_regs_t *)gpio, cfg->func, cfg->mask); @@ -197,3 +202,13 @@ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, u { return MXC_GPIO_RevA_SetDriveStrength((mxc_gpio_reva_regs_t *)port, drvstr, mask); } + +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked) +{ + MXC_GPIO_Common_SetConfigLock(locked); +} + +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void) +{ + return MXC_GPIO_Common_GetConfigLock(); +} diff --git a/Libraries/PeriphDrivers/Source/GPIO/gpio_me16.c b/Libraries/PeriphDrivers/Source/GPIO/gpio_me16.c index 73e45fc1afe..3a31217ec40 100644 --- a/Libraries/PeriphDrivers/Source/GPIO/gpio_me16.c +++ b/Libraries/PeriphDrivers/Source/GPIO/gpio_me16.c @@ -75,6 +75,11 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) int error; mxc_gpio_regs_t *gpio = cfg->port; + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + // Configure alternate function error = MXC_GPIO_RevA_SetAF((mxc_gpio_reva_regs_t *)gpio, cfg->func, cfg->mask); if (error != E_NO_ERROR) { @@ -198,3 +203,13 @@ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, u { return MXC_GPIO_RevA_SetDriveStrength((mxc_gpio_reva_regs_t *)port, drvstr, mask); } + +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked) +{ + MXC_GPIO_Common_SetConfigLock(locked); +} + +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void) +{ + return MXC_GPIO_Common_GetConfigLock(); +} diff --git a/Libraries/PeriphDrivers/Source/GPIO/gpio_me17.c b/Libraries/PeriphDrivers/Source/GPIO/gpio_me17.c index a6c5c31a9d8..e586e496114 100644 --- a/Libraries/PeriphDrivers/Source/GPIO/gpio_me17.c +++ b/Libraries/PeriphDrivers/Source/GPIO/gpio_me17.c @@ -109,6 +109,11 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) MXC_GPIO_Init(1 << port); + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + // Configure the vssel error = MXC_GPIO_SetVSSEL(gpio, cfg->vssel, cfg->mask); if (error != E_NO_ERROR) { @@ -413,3 +418,15 @@ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, u { return MXC_GPIO_RevA_SetDriveStrength((mxc_gpio_reva_regs_t *)port, drvstr, mask); } + +/* ************************************************************************** */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked) +{ + MXC_GPIO_Common_SetConfigLock(locked); +} + +/* ************************************************************************** */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void) +{ + return MXC_GPIO_Common_GetConfigLock(); +} diff --git a/Libraries/PeriphDrivers/Source/GPIO/gpio_me18.c b/Libraries/PeriphDrivers/Source/GPIO/gpio_me18.c index a7576e73b13..0eedd4f76ec 100644 --- a/Libraries/PeriphDrivers/Source/GPIO/gpio_me18.c +++ b/Libraries/PeriphDrivers/Source/GPIO/gpio_me18.c @@ -138,6 +138,11 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) // Initialize callback function pointers MXC_GPIO_Init(1 << port); + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + // Configure the vssel if (port < 4) { error = MXC_GPIO_SetVSSEL(gpio, cfg->vssel, cfg->mask); @@ -443,3 +448,15 @@ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, u { return MXC_GPIO_RevA_SetDriveStrength((mxc_gpio_reva_regs_t *)port, drvstr, mask); } + +/* ************************************************************************** */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked) +{ + MXC_GPIO_Common_SetConfigLock(locked); +} + +/* ************************************************************************** */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void) +{ + return MXC_GPIO_Common_GetConfigLock(); +} diff --git a/Libraries/PeriphDrivers/Source/GPIO/gpio_me20.c b/Libraries/PeriphDrivers/Source/GPIO/gpio_me20.c index fc5ddec7be7..450a1d26db4 100644 --- a/Libraries/PeriphDrivers/Source/GPIO/gpio_me20.c +++ b/Libraries/PeriphDrivers/Source/GPIO/gpio_me20.c @@ -81,6 +81,11 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) port = MXC_GPIO_GET_IDX(cfg->port); if (cfg->port == MXC_GPIO3) { + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + if (cfg->mask & MXC_GPIO_PIN_0) { switch (cfg->func) { case MXC_GPIO_FUNC_IN: @@ -142,6 +147,11 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) MXC_GPIO_Init(1 << port); } + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + // Configure the vssel error = MXC_GPIO_SetVSSEL(gpio, cfg->vssel, cfg->mask); if (error != E_NO_ERROR) { @@ -368,3 +378,15 @@ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, u { return MXC_GPIO_RevA_SetDriveStrength((mxc_gpio_reva_regs_t *)port, drvstr, mask); } + +/* ************************************************************************** */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked) +{ + MXC_GPIO_Common_SetConfigLock(locked); +} + +/* ************************************************************************** */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void) +{ + return MXC_GPIO_Common_GetConfigLock(); +} diff --git a/Libraries/PeriphDrivers/Source/GPIO/gpio_me21.c b/Libraries/PeriphDrivers/Source/GPIO/gpio_me21.c index afb9ef1f766..01ce3065594 100644 --- a/Libraries/PeriphDrivers/Source/GPIO/gpio_me21.c +++ b/Libraries/PeriphDrivers/Source/GPIO/gpio_me21.c @@ -76,6 +76,11 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) port = MXC_GPIO_GET_IDX(cfg->port); MXC_GPIO_Init(1 << port); + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + // Configure alternate function error = MXC_GPIO_RevA_SetAF((mxc_gpio_reva_regs_t *)gpio, cfg->func, cfg->mask); if (error != E_NO_ERROR) { @@ -199,3 +204,13 @@ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, u { return MXC_GPIO_RevA_SetDriveStrength((mxc_gpio_reva_regs_t *)port, drvstr, mask); } + +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked) +{ + MXC_GPIO_Common_SetConfigLock(locked); +} + +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void) +{ + return MXC_GPIO_Common_GetConfigLock(); +} diff --git a/Libraries/PeriphDrivers/Source/GPIO/gpio_me55.c b/Libraries/PeriphDrivers/Source/GPIO/gpio_me55.c index 009119266ce..e760363d7fc 100644 --- a/Libraries/PeriphDrivers/Source/GPIO/gpio_me55.c +++ b/Libraries/PeriphDrivers/Source/GPIO/gpio_me55.c @@ -76,6 +76,11 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) int error; mxc_gpio_regs_t *gpio = cfg->port; + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + // Configure the vssel error = MXC_GPIO_SetVSSEL(gpio, cfg->vssel, cfg->mask); if (error != E_NO_ERROR) { @@ -221,3 +226,13 @@ int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, u { return MXC_GPIO_RevA_SetDriveStrength((mxc_gpio_reva_regs_t *)port, drvstr, mask); } + +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked) +{ + MXC_GPIO_Common_SetConfigLock(locked); +} + +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void) +{ + return MXC_GPIO_Common_GetConfigLock(); +} diff --git a/Libraries/PeriphDrivers/Source/GPIO/gpio_reva.c b/Libraries/PeriphDrivers/Source/GPIO/gpio_reva.c index 8455802b6a4..aeb33c59e83 100644 --- a/Libraries/PeriphDrivers/Source/GPIO/gpio_reva.c +++ b/Libraries/PeriphDrivers/Source/GPIO/gpio_reva.c @@ -121,6 +121,11 @@ uint32_t MXC_GPIO_RevA_GetFlags(mxc_gpio_reva_regs_t *port) int MXC_GPIO_RevA_SetVSSEL(mxc_gpio_reva_regs_t *port, mxc_gpio_vssel_t vssel, uint32_t mask) { + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + // Configure the vssel switch (vssel) { case MXC_GPIO_VSSEL_VDDIO: @@ -140,6 +145,11 @@ int MXC_GPIO_RevA_SetVSSEL(mxc_gpio_reva_regs_t *port, mxc_gpio_vssel_t vssel, u int MXC_GPIO_RevA_SetAF(mxc_gpio_reva_regs_t *port, mxc_gpio_func_t func, uint32_t mask) { + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + //This is required for new devices going forward. port->inen |= mask; @@ -226,6 +236,11 @@ uint32_t MXC_GPIO_RevA_GetWakeEn(mxc_gpio_reva_regs_t *port) int MXC_GPIO_RevA_SetDriveStrength(mxc_gpio_reva_regs_t *port, mxc_gpio_drvstr_t drvstr, uint32_t mask) { + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + // Configure the drive strength. switch (drvstr) { case MXC_GPIO_DRVSTR_0: diff --git a/Libraries/PeriphDrivers/Source/GPIO/gpio_revb.c b/Libraries/PeriphDrivers/Source/GPIO/gpio_revb.c index 7064344a013..ab6ed1dd695 100644 --- a/Libraries/PeriphDrivers/Source/GPIO/gpio_revb.c +++ b/Libraries/PeriphDrivers/Source/GPIO/gpio_revb.c @@ -31,6 +31,11 @@ int MXC_GPIO_RevB_Config(const mxc_gpio_cfg_t *cfg, uint8_t psMask) { mxc_gpio_regs_t *gpio = cfg->port; + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + // Set the GPIO type switch (cfg->func) { case MXC_GPIO_FUNC_IN: @@ -198,6 +203,11 @@ uint32_t MXC_GPIO_RevB_GetFlags(mxc_gpio_regs_t *port) int MXC_GPIO_RevB_SetVSSEL(mxc_gpio_regs_t *port, mxc_gpio_vssel_t vssel, uint32_t mask) { + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + // Configure the vssel switch (vssel) { case MXC_GPIO_VSSEL_VDDIO: From 47408bb9dd8d45a285c6f945eecee7bcc6f307c2 Mon Sep 17 00:00:00 2001 From: Lorne Smith <65424047+lorne-maxim@users.noreply.github.com> Date: Thu, 25 Apr 2024 10:03:38 -0500 Subject: [PATCH 14/93] fix(Tools): Update Keil support for ECC enabled versions of the MAX32675 (#1001) Co-authored-by: lorne-maxim Co-authored-by: Sihyung Woo <75494566+sihyung-maxim@users.noreply.github.com> --- .../Maxim/MAX32675/Source/system_max32675.c | 6 +++++ Tools/Keil/MAX32675.sct | 23 +++++++++++++++++++ Tools/Keil/project_wizard/README.md | 18 ++++++++------- 3 files changed, 39 insertions(+), 8 deletions(-) create mode 100644 Tools/Keil/MAX32675.sct diff --git a/Libraries/CMSIS/Device/Maxim/MAX32675/Source/system_max32675.c b/Libraries/CMSIS/Device/Maxim/MAX32675/Source/system_max32675.c index 0b9b117f248..190e2b21852 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32675/Source/system_max32675.c +++ b/Libraries/CMSIS/Device/Maxim/MAX32675/Source/system_max32675.c @@ -167,6 +167,12 @@ __weak void SystemInit(void) MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO0); MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO1); + /* Various revisions of the MAX32675 have different startup frequencies. + Calling SystemCoreClockUpdate will examine the part's registers to + determine the correct initial value for the SystemCoreClock variable. + */ + SystemCoreClockUpdate(); + PinInit(); Board_Init(); } diff --git a/Tools/Keil/MAX32675.sct b/Tools/Keil/MAX32675.sct new file mode 100644 index 00000000000..3e2edfd228c --- /dev/null +++ b/Tools/Keil/MAX32675.sct @@ -0,0 +1,23 @@ +LR_IROM1 0x10000000 0x60000 +{ + ER_IROM1 0x10000000 0x60000 + { + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + + PAD_IROM1 +0 ALIGN 16 EMPTY 0 + { + ; This empty region forces the previous region to + ; always be a multiple of 16 bytes. This is + ; necessary for devices where flash ECC is enabled. + } + + RW_IRAM1 0x20000000 0x00028000 + { + .ANY (+RW +ZI) + } +} + diff --git a/Tools/Keil/project_wizard/README.md b/Tools/Keil/project_wizard/README.md index 9d97232cd89..e9325abed63 100644 --- a/Tools/Keil/project_wizard/README.md +++ b/Tools/Keil/project_wizard/README.md @@ -23,7 +23,7 @@ To properly setup your project using the Project Wizard App, follow these steps: - `Pack Installer` menu location: ![Pack Installer Location](https://github.com/analogdevicesinc/msdk/blob/feat/keil_project_wizard/Tools/Keil/project_wizard/docs/pack_installer_location.png) 5. Find `Maxim` -> `MAX32675 Family` and select the `MAX32675`. 6. Open the `Packs` Tab (usually on the right half column) and expand `Device Specific`. -7. Install the `Maxim::MAX32675` v1.3.0 pack file. +7. Install the `Maxim::MAX32675` v1.3.1 pack file. 8. Close Keil. 9. Run the Project Wizard App located in the cloned MSDK repository - located in `msdk/Tools/Keil/project_wizard/project_wizard.exe`. 10. Fill in desired project settings in the opened GUI. @@ -41,13 +41,15 @@ To properly setup your project using the Project Wizard App, follow these steps: - Press `ALT+F7` for macro shortcut to `Options for Target...`. 14. In the `Target` Tab -> `Code Generation` section -> `ARM Compiler` options, select `Use default compiler version 6`. 15. In the `C/C++ (AC6)` Tab -> `Language / COde Generation` section -> `Language C:` options, select `c99`. -16. In the `Debug` Tab -> Top right corner, select the `CMSIS-DAP Debugger` or the board's supported debugger adapter. - - (Optional) Press the `Run to main()` checkbox right underneath the debugger adapter selector. -17. In the `Utilities` Tab, press the `Settings` button in the `Configure Flash Menu Command` section. A `Target Driver Setup` window should open. -18. In the `Flash Download` Tab, click the `Erase Full Chip` option in the `Download Function` section. -19. In the `Debug` Tab, within the sections `Debug` -> `Connect & Reset Options`, select the `Reset:` option to `VECTRESET`. -20. Press `OK` to save everything. -21. Build and load the project. Enjoy! +16. In the `Linker` Tab, uncheck `Use Memory Layout from Target Dialog`. +17. Use the browse button (`...`) next to the `Scatter File` text box to select the `MAX32675.sct` file located in the `Tools/Keil/` folder of the MSDK repository you cloned in step #2. +18. In the `Debug` Tab -> Top right corner, select the `CMSIS-DAP Debugger` or the board's supported debugger adapter. +19. In the `Utilities` Tab, press the `Settings` button in the `Configure Flash Menu Command` section. A `Target Driver Setup` window should open. +20. In the `Flash Download` Tab, click the `Erase Full Chip` option in the `Download Function` section. +21. In the `RAM for Algorithm`, set the `Size` field to `0x3000`. +22. If using the `CMSIS-DAP Debugger` from step **18**: In the `Debug` Tab, within the sections `Debug` -> `Connect & Reset Options`, select the `Reset:` option to `VECTRESET`. +23. Press `OK` to save everything. +24. Build and load the project. Enjoy! ### Support From 3678f41d0d9b07ba811f0fff4e36ed35057f40bb Mon Sep 17 00:00:00 2001 From: Jake Carter Date: Mon, 29 Apr 2024 13:55:39 -0600 Subject: [PATCH 15/93] Add MAX32657 peripheral interface files These files are exact copy of MAX32655 Files will be updated in next sections, added here to demonstrate delta clearly on next steps Signed-off-by: Sadik Ozer --- .../PeriphDrivers/Include/MAX32572/spi.h | 1 - .../PeriphDrivers/Include/MAX32657/aes.h | 271 +++++ .../PeriphDrivers/Include/MAX32657/crc.h | 167 ++++ .../PeriphDrivers/Include/MAX32657/dma.h | 449 +++++++++ .../PeriphDrivers/Include/MAX32657/flc.h | 193 ++++ .../PeriphDrivers/Include/MAX32657/gpio.h | 398 ++++++++ .../PeriphDrivers/Include/MAX32657/i2c.h | 928 ++++++++++++++++++ .../PeriphDrivers/Include/MAX32657/icc.h | 79 ++ Libraries/PeriphDrivers/Include/MAX32657/lp.h | 248 +++++ .../PeriphDrivers/Include/MAX32657/mxc.h | 30 +- .../Include/MAX32657/mxc_assert.h | 6 +- .../Include/MAX32657/mxc_delay.h | 27 +- .../Include/MAX32657/mxc_device.h | 4 +- .../Include/MAX32657/mxc_errors.h | 6 +- .../PeriphDrivers/Include/MAX32657/mxc_lock.h | 6 +- .../PeriphDrivers/Include/MAX32657/mxc_pins.h | 86 +- .../PeriphDrivers/Include/MAX32657/mxc_sys.h | 52 +- .../Include/MAX32657/nvic_table.h | 16 +- .../PeriphDrivers/Include/MAX32657/rtc.h | 226 +++++ .../PeriphDrivers/Include/MAX32657/spi.h | 703 +++++++++++++ .../PeriphDrivers/Include/MAX32657/tmr.h | 412 ++++++++ .../PeriphDrivers/Include/MAX32657/trng.h | 127 +++ .../PeriphDrivers/Include/MAX32657/uart.h | 734 ++++++++++++++ .../PeriphDrivers/Include/MAX32657/wdt.h | 227 +++++ .../PeriphDrivers/Include/MAX32657/wut.h | 285 ++++++ .../PeriphDrivers/Include/MAX32690/spi.h | 1 - .../PeriphDrivers/Include/MAX78002/spi.h | 1 - 27 files changed, 5582 insertions(+), 101 deletions(-) create mode 100644 Libraries/PeriphDrivers/Include/MAX32657/aes.h create mode 100644 Libraries/PeriphDrivers/Include/MAX32657/crc.h create mode 100644 Libraries/PeriphDrivers/Include/MAX32657/dma.h create mode 100644 Libraries/PeriphDrivers/Include/MAX32657/flc.h create mode 100644 Libraries/PeriphDrivers/Include/MAX32657/gpio.h create mode 100644 Libraries/PeriphDrivers/Include/MAX32657/i2c.h create mode 100644 Libraries/PeriphDrivers/Include/MAX32657/icc.h create mode 100644 Libraries/PeriphDrivers/Include/MAX32657/lp.h create mode 100644 Libraries/PeriphDrivers/Include/MAX32657/rtc.h create mode 100644 Libraries/PeriphDrivers/Include/MAX32657/spi.h create mode 100644 Libraries/PeriphDrivers/Include/MAX32657/tmr.h create mode 100644 Libraries/PeriphDrivers/Include/MAX32657/trng.h create mode 100644 Libraries/PeriphDrivers/Include/MAX32657/uart.h create mode 100644 Libraries/PeriphDrivers/Include/MAX32657/wdt.h create mode 100644 Libraries/PeriphDrivers/Include/MAX32657/wut.h diff --git a/Libraries/PeriphDrivers/Include/MAX32572/spi.h b/Libraries/PeriphDrivers/Include/MAX32572/spi.h index 7f06f46d44c..bf119b2e843 100644 --- a/Libraries/PeriphDrivers/Include/MAX32572/spi.h +++ b/Libraries/PeriphDrivers/Include/MAX32572/spi.h @@ -606,7 +606,6 @@ unsigned int MXC_SPI_GetTXThreshold(mxc_spi_regs_t *spi); */ unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t *spi); -//////>>> Previous Implementation /** * @brief Sets the number of bits per character * diff --git a/Libraries/PeriphDrivers/Include/MAX32657/aes.h b/Libraries/PeriphDrivers/Include/MAX32657/aes.h new file mode 100644 index 00000000000..7f51f371c1b --- /dev/null +++ b/Libraries/PeriphDrivers/Include/MAX32657/aes.h @@ -0,0 +1,271 @@ +/** + * @file aes.h + * @brief AES driver. + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_AES_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_AES_H_ + +/***** Includes *****/ +#include "aes_regs.h" +#include "aeskeys_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup aes AES + * @ingroup periphlibs + * @{ + */ +/*@} end of group aes */ + +/***** Definitions *****/ + +typedef void (*mxc_aes_complete_t)(void *req, int result); + +/* ************************************************************************* */ +/* Cipher Definitions */ +/* ************************************************************************* */ + +/** + * @brief Enumeration type to select AES key + * + */ +typedef enum { + MXC_AES_128BITS = MXC_S_AES_CTRL_KEY_SIZE_AES128, ///< Select AES-128 bit key + MXC_AES_192BITS = MXC_S_AES_CTRL_KEY_SIZE_AES192, ///< Select AES-192 bit key + MXC_AES_256BITS = MXC_S_AES_CTRL_KEY_SIZE_AES256, ///< Select AES-256 bit key +} mxc_aes_keys_t; + +/** + * @brief Enumeration type to select AES key source and encryption type + * + */ +typedef enum { + MXC_AES_ENCRYPT_EXT_KEY = 0, ///< Encryption using External key + MXC_AES_DECRYPT_EXT_KEY = 1, ///< Encryption using internal key + MXC_AES_DECRYPT_INT_KEY = 2 ///< Decryption using internal key +} mxc_aes_enc_type_t; + +/** + * @brief Structure used to set up AES request + * + */ +typedef struct _mxc_aes_cipher_req_t { + uint32_t length; ///< Length of the data + uint32_t *inputData; ///< Pointer to input data + uint32_t *resultData; ///< Pointer to encrypted data + mxc_aes_keys_t keySize; ///< Size of AES key + mxc_aes_enc_type_t encryption; ///< Encrytion type or \ref mxc_aes_enc_type_t + mxc_aes_complete_t callback; ///< Callback function +} mxc_aes_req_t; + +/***** Function Prototypes *****/ + +/* ************************************************************************* */ +/* Global Control/Configuration functions */ +/* ************************************************************************* */ + +/** + * @brief Enable portions of the AES + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_AES_Init(void); + +/** + * @brief Enable AES Interrupts + * + * @param interrupt interrupt to enable + */ +void MXC_AES_EnableInt(uint32_t interrupt); + +/** + * @brief Disable AES Interrupts + * + * @param interrupt interrupt to disable + */ +void MXC_AES_DisableInt(uint32_t interrupt); + +/** + * @brief Checks the global AES Busy Status + * + * @return E_BUSY if busy and E_NO_ERROR otherwise, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_AES_IsBusy(void); + +/** + * @brief Disable and reset portions of the AES + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_AES_Shutdown(void); + +/** + * @brief This function should be called from the DMA Handler + * when using Async functions + */ +void MXC_AES_DMACallback(int ch, int error); + +/** + * @brief This function should be called before encryption to genrate external key + */ +void MXC_AES_GenerateKey(void); + +/** + * @brief Set Key size for encryption or decryption + * + * @param key Key size, see \ref mxc_aes_keys_t for a list of keys + */ +void MXC_AES_SetKeySize(mxc_aes_keys_t key); + +/** + * @brief Get the currently set key size + * + * @return mxc_aes_keys_t see \ref mxc_aes_keys_t + */ +mxc_aes_keys_t MXC_AES_GetKeySize(void); + +/** + * @brief Flush Input Data FIFO + * + */ +void MXC_AES_FlushInputFIFO(void); + +/** + * @brief Flush Output Data FIFO + * + */ +void MXC_AES_FlushOutputFIFO(void); + +/** + * @brief Start AES Calculations + * + */ +void MXC_AES_Start(void); + +/** + * @brief Get Interrupt flags set + * + * @return return the flags set in intfl register + */ +uint32_t MXC_AES_GetFlags(void); + +/** + * @brief Clear the interrupts + * + * @param flags flags to be cleared + */ +void MXC_AES_ClearFlags(uint32_t flags); + +/** + * @brief + * @note The result will be stored in the req structure + * + * @param req Structure containing data for the encryption + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_AES_Generic(mxc_aes_req_t *req); + +/** + * @brief Perform an encryption + * @note The result will be stored in the req structure + * + * @param req Structure containing data for the encryption + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_AES_Encrypt(mxc_aes_req_t *req); + +/** + * @brief Perform a decryption + * @note The result will be stored in the req structure + * + * @param req Structure containing data for the decryption + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_AES_Decrypt(mxc_aes_req_t *req); + +/** + * @brief Perform AES TX using DMA. Configures DMA request and starts the transmission. + * + * @param src_addr source address + * @param len number of words of data + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_AES_TXDMAConfig(void *src_addr, int len); + +/** + * @brief Perform AES RX using DMA. Configures DMA request and receives data from AES FIFO. + * + * @param dest_addr destination address + * @param len number of words of data + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_AES_RXDMAConfig(void *dest_addr, int len); + +/** + * @brief Perform encryption or decryption using DMA + * + * @param req The result will be stored in the req structure. The user needs + * to call MXC_AES_Handler() in the ISR + * @param enc 0 for encryption and 1 for decryption + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_AES_GenericAsync(mxc_aes_req_t *req, uint8_t enc); + +/** + * @brief Perform an encryption using Interrupt + * @note The result will be stored in the req structure. The user needs + * to call MXC_AES_Handler() in the ISR + * + * @param req Structure containing data for the encryption + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_AES_EncryptAsync(mxc_aes_req_t *req); + +/** + * @brief Perform a decryption using Interrupt + * @note The result will be stored in the req structure. The user needs + * to call MXC_AES_Handler() in the ISR + * + * @param req Structure containing data for the decryption + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_AES_DecryptAsync(mxc_aes_req_t *req); + +/** + * @brief Set the external key + * @param key Buffer for the key. + * @param len Key size. + */ +void MXC_AES_SetExtKey(const void *key, mxc_aes_keys_t len); + +#ifdef __cplusplus +} +#endif +/**@} end of group aes */ + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_AES_H_ diff --git a/Libraries/PeriphDrivers/Include/MAX32657/crc.h b/Libraries/PeriphDrivers/Include/MAX32657/crc.h new file mode 100644 index 00000000000..35218bf1f23 --- /dev/null +++ b/Libraries/PeriphDrivers/Include/MAX32657/crc.h @@ -0,0 +1,167 @@ +/** + * @file crc.h + * @brief cyclic redundancy check driver. + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_CRC_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_CRC_H_ + +/***** Includes *****/ +#include "crc_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup crc CRC + * @ingroup periphlibs + * @{ + */ + +/***** CRC Definitions *****/ +/** + * @brief Structure used to set up CRC request + * + */ +typedef struct _mxc_crc_req_t { + uint32_t *dataBuffer; ///< Pointer to the data + uint32_t dataLen; ///< Length of the data + uint32_t resultCRC; ///< Calculated CRC value +} mxc_crc_req_t; + +/** + * @brief CRC data bit order + * + */ +typedef enum { CRC_LSB_FIRST, CRC_MSB_FIRST } mxc_crc_bitorder_t; + +/***** Function Prototypes *****/ + +/* ************************************************************************* */ +/* Global Control/Configuration functions */ +/* ************************************************************************* */ + +/** + * @brief Enable portions of the CRC + * + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_CRC_Init(void); + +/** + * @brief Disable and reset portions of the CRC + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_CRC_Shutdown(void); + +/** + * @brief This function should be called from the CRC ISR Handler + * when using Async functions + * @param ch DMA channel + * @param error error + */ +void MXC_CRC_Handler(int ch, int error); + +/** + * @brief Set the bit-order of CRC calculation + * + * @param bitOrder The direction to perform CRC calculation in + */ +void MXC_CRC_SetDirection(mxc_crc_bitorder_t bitOrder); + +/** + * @brief Set the bit-order of CRC calculation + * + * @return The direction of calculation, 1 for MSB first, 0 for LSB first + */ +mxc_crc_bitorder_t MXC_CRC_GetDirection(void); + +/** + * @brief Byte Swap CRC Data Input + * + * @param bitOrder The direction to perform CRC calculation in + */ +void MXC_CRC_SwapDataIn(mxc_crc_bitorder_t bitOrder); + +/** + * @brief Byte Swap CRC Data output + * + * @param bitOrder The direction to perform CRC calculation in + */ +void MXC_CRC_SwapDataOut(mxc_crc_bitorder_t bitOrder); + +/** + * @brief Set the Polynomial for CRC calculation + * + * @param poly The polynomial to use for CRC calculation + */ +void MXC_CRC_SetPoly(uint32_t poly); + +/** + * @brief Get the polynomial for CRC calculation + * + * @return The polynomial used in calculation + */ +uint32_t MXC_CRC_GetPoly(void); + +/** + * @brief Get the result of a CRC calculation + * + * @return The calculated CRC value + */ +uint32_t MXC_CRC_GetResult(void); + +/*******************************/ +/* High Level Functions */ +/*******************************/ + +/** + * @brief Perform a CRC computation + * @note The result of the CRC calculation will be placed in the + * mxc_crc_req_t structure + * + * @param req Structure containing the data for calculation + * + * @return see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_CRC_Compute(mxc_crc_req_t *req); + +/** + * @brief Perform a CRC computation using DMA + * @note The result of the CRC calculation will be placed in the + * mxc_crc_req_t structure. The user must call + * MXC_DMA_Handler() in the ISR + * + * @param req Structure containing the data for calculation + * + * @return see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_CRC_ComputeAsync(mxc_crc_req_t *req); + +#ifdef __cplusplus +} +#endif +/**@} end of group crc */ + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_CRC_H_ diff --git a/Libraries/PeriphDrivers/Include/MAX32657/dma.h b/Libraries/PeriphDrivers/Include/MAX32657/dma.h new file mode 100644 index 00000000000..747e5702681 --- /dev/null +++ b/Libraries/PeriphDrivers/Include/MAX32657/dma.h @@ -0,0 +1,449 @@ +/** + * @file dma.h + * @brief Direct Memory Access (DMA) driver function prototypes and data types. + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_DMA_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_DMA_H_ + +/* **** Includes **** */ +#include +#include "mxc_device.h" +#include "dma_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup dma Direct Memory Access (DMA) + * @ingroup periphlibs + * @{ + */ + +/* **** Definitions **** */ + +/** + * @brief Enumeration for the DMA Channel's priority level. + * + */ +typedef enum { + MXC_DMA_PRIO_HIGH = MXC_V_DMA_CTRL_PRI_HIGH, ///< High Priority + MXC_DMA_PRIO_MEDHIGH = MXC_V_DMA_CTRL_PRI_MEDHIGH, ///< Medium High Priority + MXC_DMA_PRIO_MEDLOW = MXC_V_DMA_CTRL_PRI_MEDLOW, ///< Medium Low Priority + MXC_DMA_PRIO_LOW = MXC_V_DMA_CTRL_PRI_LOW, ///< Low Priority +} mxc_dma_priority_t; + +/** @brief DMA request select */ +typedef enum { + MXC_DMA_REQUEST_MEMTOMEM = + MXC_S_DMA_CTRL_REQUEST_MEMTOMEM, ///< Memory to Memory DMA Request Selection + MXC_DMA_REQUEST_SPI1RX = MXC_S_DMA_CTRL_REQUEST_SPI1RX, ///< SPI1 Receive DMA Request Selection + MXC_DMA_REQUEST_SPI0RX = MXC_S_DMA_CTRL_REQUEST_SPI0RX, ///< SPI0 Receive DMA Request Selection + MXC_DMA_REQUEST_UART0RX = + MXC_S_DMA_CTRL_REQUEST_UART0RX, ///< UART0 Receive DMA Request Selection + MXC_DMA_REQUEST_UART1RX = + MXC_S_DMA_CTRL_REQUEST_UART1RX, ///< UART1 Receive DMA Request Selection + MXC_DMA_REQUEST_I2C0RX = MXC_S_DMA_CTRL_REQUEST_I2C0RX, ///< I2C0 Receive DMA Request Selection + MXC_DMA_REQUEST_I2C1RX = MXC_S_DMA_CTRL_REQUEST_I2C1RX, ///< I2C1 Receive DMA Request Selection + MXC_DMA_REQUEST_ADC = MXC_S_DMA_CTRL_REQUEST_ADC, ///< ADC Receive DMA Request Selection + MXC_DMA_REQUEST_I2C2RX = MXC_S_DMA_CTRL_REQUEST_I2C2RX, ///< I2C2 Receive DMA Request Selection + MXC_DMA_REQUEST_AESRX = MXC_S_DMA_CTRL_REQUEST_AESRX, ///< AES Receive DMA Request Selection + MXC_DMA_REQUEST_UART2RX = + MXC_S_DMA_CTRL_REQUEST_UART2RX, ///< UART2 Receive DMA Request Selection + MXC_DMA_REQUEST_UART3RX = + MXC_S_DMA_CTRL_REQUEST_UART3RX, ///< UART3 Receive DMA Request Selection + MXC_DMA_REQUEST_I2SRX = MXC_S_DMA_CTRL_REQUEST_I2SRX, ///< I2S Receive DMA Request Selection + MXC_DMA_REQUEST_SPI1TX = MXC_S_DMA_CTRL_REQUEST_SPI1TX, ///< SPI1 Transmit DMA Request Selection + MXC_DMA_REQUEST_SPI0TX = MXC_S_DMA_CTRL_REQUEST_SPI0TX, ///< SPI0 Transmit DMA Request Selection + MXC_DMA_REQUEST_UART0TX = + MXC_S_DMA_CTRL_REQUEST_UART0TX, ///< UART0 Transmit DMA Request Selection + MXC_DMA_REQUEST_UART1TX = + MXC_S_DMA_CTRL_REQUEST_UART1TX, ///< UART1 Transmit DMA Request Selection + MXC_DMA_REQUEST_I2C0TX = MXC_S_DMA_CTRL_REQUEST_I2C0TX, ///< I2C0 Transmit DMA Request Selection + MXC_DMA_REQUEST_I2C1TX = MXC_S_DMA_CTRL_REQUEST_I2C1TX, ///< I2C1 Transmit DMA Request Selection + MXC_DMA_REQUEST_I2C2TX = + MXC_S_DMA_CTRL_REQUEST_I2C2TX, ///< I2C2 Transmit DMA Request Selection */ + MXC_DMA_REQUEST_CRCTX = MXC_S_DMA_CTRL_REQUEST_CRCTX, ///< CRC Transmit DMA Request Selection */ + MXC_DMA_REQUEST_AESTX = MXC_S_DMA_CTRL_REQUEST_AESTX, ///< AES Transmit DMA Request Selection + MXC_DMA_REQUEST_UART2TX = + MXC_S_DMA_CTRL_REQUEST_UART2TX, ///< UART2 Transmit DMA Request Selection + MXC_DMA_REQUEST_UART3TX = + MXC_S_DMA_CTRL_REQUEST_UART3TX, ///< UART3 Transmit DMA Request Selection + MXC_DMA_REQUEST_I2STX = MXC_S_DMA_CTRL_REQUEST_I2STX, ///< I2S Transmit DMA Request Selection +} mxc_dma_reqsel_t; + +/** @brief Enumeration for the DMA prescaler */ +typedef enum { + MXC_DMA_PRESCALE_DISABLE = MXC_S_DMA_CTRL_TO_CLKDIV_DIS, ///< Prescaler disabled + MXC_DMA_PRESCALE_DIV256 = MXC_S_DMA_CTRL_TO_CLKDIV_DIV256, ///< Divide by 256 + MXC_DMA_PRESCALE_DIV64K = MXC_S_DMA_CTRL_TO_CLKDIV_DIV64K, ///< Divide by 65,536 + MXC_DMA_PRESCALE_DIV16M = MXC_S_DMA_CTRL_TO_CLKDIV_DIV16M, ///< Divide by 16,777,216 +} mxc_dma_prescale_t; + +/** @brief Enumeration for the DMA timeout value */ +typedef enum { + MXC_DMA_TIMEOUT_4_CLK = MXC_S_DMA_CTRL_TO_PER_TO4, ///< DMA timeout of 4 clocks + MXC_DMA_TIMEOUT_8_CLK = MXC_S_DMA_CTRL_TO_PER_TO8, ///< DMA timeout of 8 clocks + MXC_DMA_TIMEOUT_16_CLK = MXC_S_DMA_CTRL_TO_PER_TO16, ///< DMA timeout of 16 clocks + MXC_DMA_TIMEOUT_32_CLK = MXC_S_DMA_CTRL_TO_PER_TO32, ///< DMA timeout of 32 clocks + MXC_DMA_TIMEOUT_64_CLK = MXC_S_DMA_CTRL_TO_PER_TO64, ///< DMA timeout of 64 clocks + MXC_DMA_TIMEOUT_128_CLK = MXC_S_DMA_CTRL_TO_PER_TO128, ///< DMA timeout of 128 clocks + MXC_DMA_TIMEOUT_256_CLK = MXC_S_DMA_CTRL_TO_PER_TO256, ///< DMA timeout of 256 clocks + MXC_DMA_TIMEOUT_512_CLK = MXC_S_DMA_CTRL_TO_PER_TO512, ///< DMA timeout of 512 clocks +} mxc_dma_timeout_t; + +/** @brief DMA transfer data width */ +typedef enum { + /* Using the '_V_' define instead of the '_S_' since these same values will be used to + specify the DSTWD also. The API functions will shift the value the correct amount + prior to writing the cfg register. */ + MXC_DMA_WIDTH_BYTE = MXC_V_DMA_CTRL_SRCWD_BYTE, ///< DMA transfer in bytes + MXC_DMA_WIDTH_HALFWORD = MXC_V_DMA_CTRL_SRCWD_HALFWORD, ///< DMA transfer in 16-bit half-words + MXC_DMA_WIDTH_WORD = MXC_V_DMA_CTRL_SRCWD_WORD, ///< DMA transfer in 32-bit words +} mxc_dma_width_t; + +/** + * @brief The basic configuration information to set up a DMA channel + * and prepare it for transfers. + * + */ +typedef struct { + int ch; ///< The channel to load the configuration data into + mxc_dma_reqsel_t reqsel; ///< The request select line to be used (mem2mem, peripheral) + mxc_dma_width_t srcwd; ///< The source width (could be dependent on FIFO width) + mxc_dma_width_t dstwd; ///< The destination width (could be dependent on FIFO width) + int srcinc_en; ///< Whether to increment the source address during the transfer + int dstinc_en; ///< Whether to increment the source address during the transfer +} mxc_dma_config_t; + +/** + * @brief The information needed to complete a DMA transfer + * + */ +typedef struct { + int ch; ///< The channel to use for the transfer + void *source; ///< Pointer to the source address, if applicable + void *dest; ///< Pointer to the destination address, if applicable + int len; ///< Number of bytes to transfer +} mxc_dma_srcdst_t; + +/** + * @brief The advanced configuration options, these are optional but could + * be needed in cases where multiple DMA channels are running concurrently + * or DMA is being used with low bandwidth peripherals. + * + */ +typedef struct { + int ch; ///< The channel to use for the transfer + mxc_dma_priority_t prio; ///< The DMA priority for the channel + unsigned int reqwait_en; ///< Delay the timeout timer start until after first transfer + mxc_dma_timeout_t tosel; ///< Number of prescaled clocks seen by the channel before a timeout + mxc_dma_prescale_t pssel; ///< Prescaler for the timeout timer + unsigned int burst_size; ///< Number of bytes moved in a single burst +} mxc_dma_adv_config_t; + +/** + * @brief The callback called on completion of a DMA_MemCpy() transfer + * + * @param dest Pointer to the destination of the copy + */ +typedef void (*mxc_dma_complete_cb_t)(void *dest); + +/** + * @brief The callback called on completion of a transfer, + * @note This callback is used with MXC_DMA_DoTransfer() + * to allow the user to chain an unlimited number of + * DMA Transfers. + * + * @param trans Struct of the completed transfer + * + * @return Returns the next transfer to be completed, or NULL + * if no more transfers will be done + */ +typedef mxc_dma_srcdst_t (*mxc_dma_trans_chain_t)(mxc_dma_srcdst_t dest); + +/* **** Function Prototypes **** */ +/*************************/ +/* Low Level Functions */ +/*************************/ +/** + * @brief Initialize DMA resources + * @details This initialization is required before using the DMA driver functions. + * @note On default this function enables DMA peripheral clock. + * if you wish to manage clock and gpio related things in upper level instead of here. + * Define MSDK_NO_GPIO_CLK_INIT flag in project.mk file. + * By this flag this function will remove clock and gpio related codes from file. + * @return #E_NO_ERROR if successful + */ +int MXC_DMA_Init(void); + +/** + * @brief De-Initialize DMA resources. + */ +void MXC_DMA_DeInit(void); + +/** + * @brief Request DMA channel + * @details Returns a handle to the first free DMA channel, which can be used via API calls + * or direct access to channel registers using the MXC_DMA_GetCHRegs(int ch) function. + * @return Non-negative channel handle (inclusive of zero). + * @return #E_NONE_AVAIL All channels in use. + * @return #E_BAD_STATE DMA is not initialized, call MXC_DMA_Init() first. + * @return #E_BUSY DMA is currently busy (locked), try again later. + */ +int MXC_DMA_AcquireChannel(void); + +/** + * @brief Release DMA channel + * @details Stops any DMA operation on the channel and returns it to the pool of free channels. + * + * @param ch DMA channel to release + * + * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise + */ +int MXC_DMA_ReleaseChannel(int ch); + +/** + * @brief Configure the DMA channel + * @details Configures the channel, which was previously requested by MXC_DMA_Getchannel() + * + * @param config Struct containing DMA configuration parameters + * @param srcdst Struct containing pointers and length of DMA operation + * + * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise + */ +int MXC_DMA_ConfigChannel(mxc_dma_config_t config, mxc_dma_srcdst_t srcdst); + +/** + * @brief Configure the DMA channel with more advanced parameters + * + * @param advConfig Struct containing advanced DMA parameters + * + * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise + */ +int MXC_DMA_AdvConfigChannel(mxc_dma_adv_config_t advConfig); + +/** + * @brief Set channel source, destination, and count for the transfer + * @param srcdst Struct containing the channel, source, destination, and count for the channel + * @note Unless the channel request select is #mxc_dma_srcdst_t = MXC_DMA_REQUEST_MEMTOMEM, + * either src_addr or dst_addr will be ignored by the DMA engine. + * In these cases, the address is a don't-care. See the User's + * Guide for more information. + * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise + */ +int MXC_DMA_SetSrcDst(mxc_dma_srcdst_t srcdst); + +/** + * @brief Get channel source, destination, and count for transfer + * + * @param srcdst Pointer to struct with the correct channel number + * + * @return See \ref MXC_Error_Codes for a list of return values + */ +int MXC_DMA_GetSrcDst(mxc_dma_srcdst_t *srcdst); + +/** + * @brief Set channel reload source, destination, and count for the transfer + * @param srcdstReload Struct containing the channel, source, destination, and count for the channel + * @note Unless the channel request select is #mxc_dma_srcdst_t = MXC_DMA_REQUEST_MEMTOMEM, + * either src_addr or dst_addr will be ignored by the DMA engine. + * In these cases, the address is a don't-care. See the User's + * Guide for more information. + * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise + */ +int MXC_DMA_SetSrcReload(mxc_dma_srcdst_t srcdstReload); + +/** + * @brief Get channel reload source, destination, and count for transfer + * + * @param srcdstReload Pointer to struct with the correct channel number + * + * @return See \ref MXC_Error_Codes for a list of return values + */ +int MXC_DMA_GetSrcReload(mxc_dma_srcdst_t *srcdstReload); + +/** + * @brief Set channel interrupt callback + * @param ch DMA channel + * @param callback Pointer to a function to call when the channel + * interrupt flag is set and interrupts are enabled or + * when DMA is shutdown by the driver. + * @details Configures the channel interrupt callback. The @p callback + * function is called for two conditions: + * -# When the channel's interrupt flag is set and DMA interrupts + * are enabled. + * -# If the driver calls the MXC_DMA_Shutdown() function. The + * callback function prototype is: + * @code + * void callback_fn(int ch, int reason); + * @endcode + * @p ch indicates the channel that generated the callback, @p + * reason is either #E_NO_ERROR for a DMA interrupt or #E_SHUTDOWN + * if the DMA is being shutdown. + * + * @return #E_BAD_PARAM if an unused or invalid channel handle, + * #E_NO_ERROR otherwise, \ref MXC_Error_Codes + */ +int MXC_DMA_SetCallback(int ch, void (*callback)(int, int)); + +/** + * @brief Set channel interrupt + * @note Each channel has two interrupts (complete, and count to zero). + * To enable complete, pass true for chdis. To enable count to zero, + * pass true for ctz. + * @param ch DMA channel + * @param chdis Enable channel complete interrupt + * @param ctz Enable channel count to zero interrupt. + * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise + */ +int MXC_DMA_SetChannelInterruptEn(int ch, bool chdis, bool ctz); + +/** + * @brief Enable channel interrupt + * @note Each channel has two interrupts (complete, and count to zero) + which must also be enabled with MXC_DMA_SetChannelInterruptEn() + * @param ch DMA channel to enable interrupts for. + * @param flags The flags to enable + * @return #E_BAD_PARAM if an unused or invalid channel handle, + * #E_NO_ERROR otherwise, \ref MXC_Error_Codes + */ +int MXC_DMA_ChannelEnableInt(int ch, int flags); + +/** + * @brief Disable channel interrupt + * @param ch DMA channel to clear flags for. + * @param flags The flags to disable + * @return #E_BAD_PARAM if an unused or invalid channel handle, + * #E_NO_ERROR otherwise, \ref MXC_Error_Codes + */ +int MXC_DMA_ChannelDisableInt(int ch, int flags); + +/** + * @brief Read channel interrupt flags + * @param ch DMA channel to get interrupt status from. + * @return #E_BAD_PARAM if an unused or invalid channel handle, + * flags otherwise, \ref MXC_Error_Codes + */ +int MXC_DMA_ChannelGetFlags(int ch); + +/** + * @brief Clear channel interrupt flags + * @param ch DMA channel to clear the interrupt flag for. + * @param flags The flags to clear + * @return #E_BAD_PARAM if an unused or invalid channel handle, + * #E_NO_ERROR otherwise, \ref MXC_Error_Codes + */ +int MXC_DMA_ChannelClearFlags(int ch, int flags); + +/** + * @brief Enable channel interrupt + * @note Each channel has two interrupts (complete, and count to zero) + which must also be enabled with MXC_DMA_SetChannelInterruptEn() + * @param ch DMA channel to enable interrupts for. + * @return #E_BAD_PARAM if an unused or invalid channel handle, + * #E_NO_ERROR otherwise, \ref MXC_Error_Codes + */ +int MXC_DMA_EnableInt(int ch); + +/** + * @brief Disable channel interrupt + * @param ch DMA channel to disable interrupts for. + * @return #E_BAD_PARAM if an unused or invalid channel handle, + * #E_NO_ERROR otherwise, \ref MXC_Error_Codes + */ +int MXC_DMA_DisableInt(int ch); + +/** + * @brief Start transfer + * @param ch DMA channel + * @details Start the DMA channel transfer, assumes that MXC_DMA_SetSrcDstCnt() has been called beforehand. + * @return #E_BAD_PARAM if an unused or invalid channel handle, + * #E_NO_ERROR otherwise, \ref MXC_Error_Codes + */ +int MXC_DMA_Start(int ch); + +/** + * @brief Stop DMA transfer, irrespective of status (complete or in-progress) + * @param ch DMA channel + * @return #E_BAD_PARAM if an unused or invalid channel handle, + * #E_NO_ERROR otherwise, \ref MXC_Error_Codes + */ +int MXC_DMA_Stop(int ch); + +/** + * @brief Get a pointer to the DMA channel registers + * @param ch DMA channel + * @note If direct access to DMA channel registers is required, this + * function can be used on a channel handle returned by MXC_DMA_AcquireChannel(). + * @return NULL if an unused or invalid channel handle, or a valid pointer otherwise + */ +mxc_dma_ch_regs_t *MXC_DMA_GetCHRegs(int ch); + +/** + * @brief Interrupt handler function + * @details Call this function as the ISR for each DMA channel under driver control. + * Interrupt flags for channel ch will be automatically cleared before return. + */ +void MXC_DMA_Handler(void); + +/*************************/ +/* High Level Functions */ +/*************************/ + +/** + * @brief Performs a memcpy, using DMA, optionally asynchronous + * @note The user must have the DMA interrupt enabled and call + * MXC_DMA_Handler() from the ISR. + * + * @param dest pointer to destination memory + * @param src pointer to source memory + * @param len number of bytes to copy + * @param callback function to call when transfer is complete + * + * @return see \ref MXC_Error_Codes + */ +int MXC_DMA_MemCpy(void *dest, void *src, int len, mxc_dma_complete_cb_t callback); + +/** + * @brief Performs a memcpy, using DMA, optionally asynchronous + * @note The user must have the DMA interrupt enabled and call + * MXC_DMA_Handler() from the ISR. + * + * @param config The channel config struct + * @param firstSrcDst The source, destination, and count for the first transfer + * @param callback function is called when transfer is complete + * + * @return see \ref MXC_Error_Codes + */ +int MXC_DMA_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, + mxc_dma_trans_chain_t callback); +/** + * For other functional uses of DMA (UART, SPI, etc) see the appropriate peripheral driver + */ + +/**@} end of group dma */ +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_DMA_H_ diff --git a/Libraries/PeriphDrivers/Include/MAX32657/flc.h b/Libraries/PeriphDrivers/Include/MAX32657/flc.h new file mode 100644 index 00000000000..849da76ebce --- /dev/null +++ b/Libraries/PeriphDrivers/Include/MAX32657/flc.h @@ -0,0 +1,193 @@ +/** + * @file flc.h + * @brief Flash Controller driver. + * @details This driver can be used to operate on the embedded flash memory. + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_FLC_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_FLC_H_ + +/* **** Includes **** */ +#include "flc_regs.h" +#include "mxc_sys.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup flc Flash Controller (FLC) + * @ingroup periphlibs + * @{ + */ + +/***** Definitions *****/ + +/// Bit mask that can be used to find the starting address of a page in flash +#define MXC_FLASH_PAGE_MASK ~(MXC_FLASH_PAGE_SIZE - 1) + +/// Calculate the address of a page in flash from the page number +#define MXC_FLASH_PAGE_ADDR(page) (MXC_FLASH_MEM_BASE + ((uint32_t)page * MXC_FLASH_PAGE_SIZE)) + +/***** Function Prototypes *****/ + +/** + * @brief Initializes the Flash Controller for erase/write operations + * @return #E_NO_ERROR if successful. + */ +int MXC_FLC_Init(void); + +/** + * @brief Checks if Flash Controller is busy. + * @details Reading or executing from flash is not possible if flash is busy + * with an erase or write operation. + * @return If non-zero, flash operation is in progress + */ +int MXC_FLC_Busy(void); + +/** + * @brief Erases the entire flash array. + * @note This function must be executed from RAM. + * @return #E_NO_ERROR If function is successful. + */ +int MXC_FLC_MassErase(void); + +/** + * @brief Erases the page of flash at the specified address. + * @note This function must be executed from RAM. + * @param address Any address within the page to erase. + * @return #E_NO_ERROR If function is successful. + */ +int MXC_FLC_PageErase(uint32_t address); + +/** + * @brief Read Data out of Flash from an address + * + * @param[in] address The address to read from + * @param buffer The buffer to read the data into + * @param[in] len The length of the buffer + * + */ +void MXC_FLC_Read(int address, void *buffer, int len); + +/** + * @brief Writes data to flash. + * @note This function must be executed from RAM. + * @param address Address in flash to start writing from. + * @param length Number of bytes to be written. + * @param buffer Pointer to data to be written to flash. + * @return #E_NO_ERROR If function is successful. + * @note make sure to disable ICC with ICC_Disable(); before Running this function + */ +int MXC_FLC_Write(uint32_t address, uint32_t length, uint32_t *buffer); + +/** + * @brief Writes 32 bits of data to flash. + * @note This function must be executed from RAM. + * @param address Address in flash to start writing from. + * @param data Pointer to data to be written to flash. + * @return #E_NO_ERROR If function is successful. + * @note make sure to disable ICC with ICC_Disable(); before Running this function + */ +int MXC_FLC_Write32(uint32_t address, uint32_t data); + +/** + * @brief Writes 128 bits of data to flash. + * @note This function must be executed from RAM. + * @param address Address in flash to start writing from. + * @param data Pointer to data to be written to flash. + * @return #E_NO_ERROR If function is successful. + * @note make sure to disable ICC with ICC_Disable(); before Running this function + */ +int MXC_FLC_Write128(uint32_t address, uint32_t *data); + +/** + * @brief Enable flash interrupts + * @param flags Interrupts to enable + * @return #E_NO_ERROR If function is successful. + */ +int MXC_FLC_EnableInt(uint32_t flags); + +/** + * @brief Disable flash interrupts + * @param flags Interrupts to disable + * @return #E_NO_ERROR If function is successful. + */ +int MXC_FLC_DisableInt(uint32_t flags); + +/** + * @brief Retrieve flash interrupt flags + * @return Interrupt flags registers + */ +int MXC_FLC_GetFlags(void); + +/** + * @brief Clear flash interrupt flags + * @note Provide the bit position to clear, even if the flag is write-0-to-clear + * @param flags Flag bit(s) to clear + * @return #E_NO_ERROR If function is successful. + */ +int MXC_FLC_ClearFlags(uint32_t flags); + +/** + * @brief Unlock info block + * + * @param[in] address The address in the info block needing written to + * + * @return #E_NO_ERROR If function is successful. + */ +int MXC_FLC_UnlockInfoBlock(uint32_t address); + +/** + * @brief Lock info block + * + * @param[in] address The address in the info block that was written to + * @return #E_NO_ERROR If function is successful. + */ +int MXC_FLC_LockInfoBlock(uint32_t address); + +/** + * @brief Blocks write operations to the flash page associated with the 'address' argument + * @note Flash pages cannot be unblocked except for on POR and external resets + * + * @param address Absolute address located anywhere in the flash page to be locked (does not need to be word-aligned) + * + * @return #E_NO_ERROR If function is successful. + */ +int MXC_FLC_BlockPageWrite(uint32_t address); + +/** + * @brief Blocks read operations from the flash page associated with the 'address' argument + * @note Flash pages cannot be unblocked except for on POR and external resets + * + * @param address Absolute address located anywhere in the flash page to be locked (does not need to be word-aligned) + * + * @return #E_NO_ERROR If function is successful. + */ +int MXC_FLC_BlockPageRead(uint32_t address); + +/**@} end of group flc */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_FLC_H_ diff --git a/Libraries/PeriphDrivers/Include/MAX32657/gpio.h b/Libraries/PeriphDrivers/Include/MAX32657/gpio.h new file mode 100644 index 00000000000..8949a33e434 --- /dev/null +++ b/Libraries/PeriphDrivers/Include/MAX32657/gpio.h @@ -0,0 +1,398 @@ +/** + * @file gpio.h + * @brief General-Purpose Input/Output (GPIO) function prototypes and data types. + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* Define to prevent redundant inclusion */ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_GPIO_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_GPIO_H_ + +/* **** Includes **** */ +#include "gpio_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup gpio General-Purpose Input/Output (GPIO) + * @ingroup periphlibs + * @{ + */ + +/* **** Definitions **** */ +/** + * @defgroup gpio_port_pin Port and Pin Definitions + * @ingroup gpio + * @{ + * @defgroup gpio_port Port Definitions + * @ingroup gpio_port_pin + * @{ + */ +#define MXC_GPIO_PORT_0 ((uint32_t)(1UL << 0)) /**< Port 0 Define*/ +#define MXC_GPIO_PORT_1 ((uint32_t)(1UL << 1)) /**< Port 1 Define*/ +#define MXC_GPIO_PORT_2 ((uint32_t)(1UL << 2)) /**< Port 2 Define*/ +#define MXC_GPIO_PORT_3 ((uint32_t)(1UL << 3)) /**< Port 3 Define*/ +/**@} end of gpio_port group*/ +/** + * @defgroup gpio_pin Pin Definitions + * @ingroup gpio_port_pin + * @{ + */ +#define MXC_GPIO_PIN_0 ((uint32_t)(1UL << 0)) /**< Pin 0 Define */ +#define MXC_GPIO_PIN_1 ((uint32_t)(1UL << 1)) /**< Pin 1 Define */ +#define MXC_GPIO_PIN_2 ((uint32_t)(1UL << 2)) /**< Pin 2 Define */ +#define MXC_GPIO_PIN_3 ((uint32_t)(1UL << 3)) /**< Pin 3 Define */ +#define MXC_GPIO_PIN_4 ((uint32_t)(1UL << 4)) /**< Pin 4 Define */ +#define MXC_GPIO_PIN_5 ((uint32_t)(1UL << 5)) /**< Pin 5 Define */ +#define MXC_GPIO_PIN_6 ((uint32_t)(1UL << 6)) /**< Pin 6 Define */ +#define MXC_GPIO_PIN_7 ((uint32_t)(1UL << 7)) /**< Pin 7 Define */ +#define MXC_GPIO_PIN_8 ((uint32_t)(1UL << 8)) /**< Pin 8 Define */ +#define MXC_GPIO_PIN_9 ((uint32_t)(1UL << 9)) /**< Pin 9 Define */ +#define MXC_GPIO_PIN_10 ((uint32_t)(1UL << 10)) /**< Pin 10 Define */ +#define MXC_GPIO_PIN_11 ((uint32_t)(1UL << 11)) /**< Pin 11 Define */ +#define MXC_GPIO_PIN_12 ((uint32_t)(1UL << 12)) /**< Pin 12 Define */ +#define MXC_GPIO_PIN_13 ((uint32_t)(1UL << 13)) /**< Pin 13 Define */ +#define MXC_GPIO_PIN_14 ((uint32_t)(1UL << 14)) /**< Pin 14 Define */ +#define MXC_GPIO_PIN_15 ((uint32_t)(1UL << 15)) /**< Pin 15 Define */ +#define MXC_GPIO_PIN_16 ((uint32_t)(1UL << 16)) /**< Pin 16 Define */ +#define MXC_GPIO_PIN_17 ((uint32_t)(1UL << 17)) /**< Pin 17 Define */ +#define MXC_GPIO_PIN_18 ((uint32_t)(1UL << 18)) /**< Pin 18 Define */ +#define MXC_GPIO_PIN_19 ((uint32_t)(1UL << 19)) /**< Pin 19 Define */ +#define MXC_GPIO_PIN_20 ((uint32_t)(1UL << 20)) /**< Pin 20 Define */ +#define MXC_GPIO_PIN_21 ((uint32_t)(1UL << 21)) /**< Pin 21 Define */ +#define MXC_GPIO_PIN_22 ((uint32_t)(1UL << 22)) /**< Pin 22 Define */ +#define MXC_GPIO_PIN_23 ((uint32_t)(1UL << 23)) /**< Pin 23 Define */ +#define MXC_GPIO_PIN_24 ((uint32_t)(1UL << 24)) /**< Pin 24 Define */ +#define MXC_GPIO_PIN_25 ((uint32_t)(1UL << 25)) /**< Pin 25 Define */ +#define MXC_GPIO_PIN_26 ((uint32_t)(1UL << 26)) /**< Pin 26 Define */ +#define MXC_GPIO_PIN_27 ((uint32_t)(1UL << 27)) /**< Pin 27 Define */ +#define MXC_GPIO_PIN_28 ((uint32_t)(1UL << 28)) /**< Pin 28 Define */ +#define MXC_GPIO_PIN_29 ((uint32_t)(1UL << 29)) /**< Pin 29 Define */ +#define MXC_GPIO_PIN_30 ((uint32_t)(1UL << 30)) /**< Pin 30 Define */ +#define MXC_GPIO_PIN_31 ((uint32_t)(1UL << 31)) /**< Pin 31 Define */ +/**@} end of gpio_pin group */ +/**@} end of gpio_port_pin group */ + +/** + * @brief Type alias for a GPIO callback function with prototype: + * @code + void callback_fn(void *cbdata); + * @endcode + * @param cbdata A void pointer to the data type as registered when + * MXC_GPIO_RegisterCallback() was called. + */ +typedef void (*mxc_gpio_callback_fn)(void *cbdata); + +/** + * @brief Enumeration type for the GPIO Function Type + */ +typedef enum { + MXC_GPIO_FUNC_IN, /**< GPIO Input */ + MXC_GPIO_FUNC_OUT, /**< GPIO Output */ + MXC_GPIO_FUNC_ALT1, /**< Alternate Function Selection */ + MXC_GPIO_FUNC_ALT2, /**< Alternate Function Selection */ + MXC_GPIO_FUNC_ALT3, /**< Alternate Function Selection */ + MXC_GPIO_FUNC_ALT4, /**< Alternate Function Selection */ +} mxc_gpio_func_t; + +/** + * @brief Enumeration type for the voltage level on a given pin. + */ +typedef enum { + MXC_GPIO_VSSEL_VDDIO, /**< Set pin to VIDDIO voltage */ + MXC_GPIO_VSSEL_VDDIOH, /**< Set pin to VIDDIOH voltage */ +} mxc_gpio_vssel_t; + +/** + * @brief Enumeration type for drive strength on a given pin. + * This represents what the two GPIO_DS[2] (Drive Strength) + * registers are set to for a given GPIO pin; NOT the + * drive strength level. + * + * For example: + * MXC_GPIO_DRVSTR_0: GPIO_DS1[pin] = 0; GPIO_DS0[pin] = 0 + * MXC_GPIO_DRVSTR_1: GPIO_DS1[pin] = 0; GPIO_DS0[pin] = 1 + * MXC_GPIO_DRVSTR_2: GPIO_DS1[pin] = 1; GPIO_DS0[pin] = 0 + * MXC_GPIO_DRVSTR_3: GPIO_DS1[pin] = 1; GPIO_DS0[pin] = 1 + * + * Refer to the user guide and datasheet to select the + * appropriate drive strength. Note: the drive strength values + * are not linear, and can vary from pin-to-pin and the state + * of the GPIO pin (alternate function and voltage level). + */ +typedef enum { + MXC_GPIO_DRVSTR_0, /**< Drive Strength GPIO_DS[2][pin]=0b00 */ + MXC_GPIO_DRVSTR_1, /**< Drive Strength GPIO_DS[2][pin]=0b01 */ + MXC_GPIO_DRVSTR_2, /**< Drive Strength GPIO_DS[2][pin]=0b10 */ + MXC_GPIO_DRVSTR_3, /**< Drive Strength GPIO_DS[2][pin]=0b11 */ +} mxc_gpio_drvstr_t; + +/** + * @brief Enumeration type for the type of GPIO pad on a given pin. + */ +typedef enum { + MXC_GPIO_PAD_NONE, /**< No pull-up or pull-down */ + MXC_GPIO_PAD_PULL_UP, /**< Set pad to strong pull-up */ + MXC_GPIO_PAD_PULL_DOWN, /**< Set pad to strong pull-down */ + MXC_GPIO_PAD_WEAK_PULL_UP, /**< Set pad to weak pull-up */ + MXC_GPIO_PAD_WEAK_PULL_DOWN, /**< Set pad to weak pull-down */ +} mxc_gpio_pad_t; + +/** + * @brief Structure type for configuring a GPIO port. + */ +typedef struct { + mxc_gpio_regs_t *port; /**< Pointer to GPIO regs */ + uint32_t mask; /**< Pin mask (multiple pins may be set) */ + mxc_gpio_func_t func; /**< Function type */ + mxc_gpio_pad_t pad; /**< Pad type */ + mxc_gpio_vssel_t vssel; /**< Voltage select */ + mxc_gpio_drvstr_t drvstr; /**< Drive Strength select */ +} mxc_gpio_cfg_t; + +/** + * @brief Enumeration type for the interrupt modes. + */ +typedef enum { + MXC_GPIO_INT_LEVEL, /**< Interrupt is level sensitive */ + MXC_GPIO_INT_EDGE /**< Interrupt is edge sensitive */ +} mxc_gpio_int_mode_t; + +/** + * @brief Enumeration type for the interrupt polarity. + */ +typedef enum { + MXC_GPIO_INT_FALLING, /**< Interrupt triggers on falling edge */ + MXC_GPIO_INT_HIGH, /**< Interrupt triggers when level is high */ + MXC_GPIO_INT_RISING, /**< Interrupt triggers on rising edge */ + MXC_GPIO_INT_LOW, /**< Interrupt triggers when level is low */ + MXC_GPIO_INT_BOTH /**< Interrupt triggers on either edge */ +} mxc_gpio_int_pol_t; + +/** + * @brief Enumeration type for the pin configuration lock mechanism. + */ +typedef enum { + MXC_GPIO_CONFIG_UNLOCKED = 0, /**< Allow changing pins' configuration. */ + MXC_GPIO_CONFIG_LOCKED, /**< Ignore changes to a pin's configuration. */ +} mxc_gpio_config_lock_t; + +/* **** Function Prototypes **** */ + +/** + * @brief Initialize GPIO. + * @param portMask Mask for the port to be initialized + * @return #E_NO_ERROR if everything is successful. + */ +int MXC_GPIO_Init(uint32_t portMask); + +/** + * @brief Shutdown GPIO. + * @param portMask Mask for the port to be initialized + * @return #E_NO_ERROR if everything is successful. + */ +int MXC_GPIO_Shutdown(uint32_t portMask); + +/** + * @brief Reset GPIO. + * @param portMask Mask for the port to be initialized + * @return #E_NO_ERROR if everything is successful. + */ +int MXC_GPIO_Reset(uint32_t portMask); + +/** + * @brief Configure GPIO pin(s). + * @param cfg Pointer to configuration structure describing the pin. + * @return #E_NO_ERROR if everything is successful. + */ +int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg); + +/** + * @brief Gets the pin(s) input state. + * @param port Pointer to the GPIO port registers + * @param mask Mask of the pin(s) to read + * @return The requested pin state. + */ +uint32_t MXC_GPIO_InGet(mxc_gpio_regs_t *port, uint32_t mask); + +/** + * @brief Sets the pin(s) to a high level output. + * @param port Pointer to the GPIO port registers + * @param mask Mask of the pin(s) to set + */ +void MXC_GPIO_OutSet(mxc_gpio_regs_t *port, uint32_t mask); + +/** + * @brief Clears the pin(s) to a low level output. + * @param port Pointer to the GPIO port registers + * @param mask Mask of the pin(s) to clear + */ +void MXC_GPIO_OutClr(mxc_gpio_regs_t *port, uint32_t mask); + +/** + * @brief Gets the pin(s) output state. + * @param port Pointer to the GPIO port registers + * @param mask Mask of the pin(s) to read the output state of + * @return The state of the requested pin. + * + */ +uint32_t MXC_GPIO_OutGet(mxc_gpio_regs_t *port, uint32_t mask); + +/** + * @brief Write the pin(s) to a desired output level. + * @param port Pointer to the GPIO port registers + * @param mask Mask of the pin(s) to set output level of + * @param val Desired output level of the pin(s). This will be masked + * with the configuration mask. + */ +void MXC_GPIO_OutPut(mxc_gpio_regs_t *port, uint32_t mask, uint32_t val); + +/** + * @brief Toggles the the pin(s) output level. + * @param port Pointer to the GPIO port registers + * @param mask Mask of the pin(s) to toggle the output + */ +void MXC_GPIO_OutToggle(mxc_gpio_regs_t *port, uint32_t mask); + +/** + * @brief Configure GPIO interrupt(s) + * @param cfg Pointer to configuration structure describing the pin. + * @param pol Requested interrupt polarity. + * @return #E_NO_ERROR if everything is successful. + */ +int MXC_GPIO_IntConfig(const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol); + +/** + * @brief Enables the specified GPIO interrupt + * @param port Pointer to the GPIO port registers + * @param mask Mask of the pin(s) to enable interrupts for + * + */ +void MXC_GPIO_EnableInt(mxc_gpio_regs_t *port, uint32_t mask); + +/** + * @brief Disables the specified GPIO interrupt. + * @param port Pointer to the GPIO port registers + * @param mask Mask of the pin(s) to disable interrupts for + */ +void MXC_GPIO_DisableInt(mxc_gpio_regs_t *port, uint32_t mask); + +/** + * @brief Gets the interrupt(s) status on a GPIO port + * + * @param port Pointer to the GPIO port registers + * + * @return The requested interrupt status. + */ +uint32_t MXC_GPIO_GetFlags(mxc_gpio_regs_t *port); + +/** + * @brief Gets the interrupt(s) status on a GPIO port + * + * @param port Pointer to the GPIO port registers + * @param flags The flags to clear + */ +void MXC_GPIO_ClearFlags(mxc_gpio_regs_t *port, uint32_t flags); + +/** + * @brief Registers a callback for the interrupt on a given port and pin. + * @param cfg Pointer to configuration structure describing the pin + * @param callback A pointer to a function of type #callback_fn. + * @param cbdata The parameter to be passed to the callback function, #callback_fn, when an interrupt occurs. + * + */ +void MXC_GPIO_RegisterCallback(const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn callback, + void *cbdata); + +/** + * @brief GPIO IRQ Handler. @note If a callback is registered for a given + * interrupt, the callback function will be called. + * + * @param port Number of the port that generated the interrupt service routine. + * + */ +void MXC_GPIO_Handler(unsigned int port); + +/** + * @brief Set Voltage select for pins to VDDIO or VDDIOH + * + * @param port Pointer to the GPIO port registers + * @param[in] vssel VDDIO or VDDIOH to set the voltatge to + * @param[in] mask Pins in the GPIO port that will be set to the voltage. + */ +int MXC_GPIO_SetVSSEL(mxc_gpio_regs_t *port, mxc_gpio_vssel_t vssel, uint32_t mask); + +/** + * @brief Enables GPIO pins to be used as a wakeup source. + * + * @param port The GPIO port + * @param mask Pins in the GPIO port that will be enabled as a wakeup source. + */ +void MXC_GPIO_SetWakeEn(mxc_gpio_regs_t *port, uint32_t mask); + +/** + * @brief Disables GPIO pins from being used as a wakeup source. + * + * @param port The GPIO port + * @param mask Pins in the GPIO port that will be disabled as a wakeup source. + */ +void MXC_GPIO_ClearWakeEn(mxc_gpio_regs_t *port, uint32_t mask); + +/** + * @brief Returns the pins currently enabled as wakeup sources. + * + * @param port The GPIO port to check. + * + * @returns The value of the wake enable register. + */ +uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port); + +/** + * @brief Set Drive Strength for pins. + * + * @param port The GPIO port. + * @param[in] ds Drive strength level. Ref /mxc_gpio_ds_t enum type. + * @param[in] mask Pins in the GPIO port that will be set to the voltage. + */ +int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, uint32_t mask); + +/** + * @brief Enables/Disables the lock on all pins' configurations. If + * locked, any changes to a pin's configuration made through the + * MXC_GPIO_Config function will be ignored. + * + * @param locked Determines if changes will be allowed. */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked); + +/** + * @brief Reads the current lock state on pin configuration. + * + * @returns The lock state. */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void); + +/**@} end of group gpio */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_GPIO_H_ diff --git a/Libraries/PeriphDrivers/Include/MAX32657/i2c.h b/Libraries/PeriphDrivers/Include/MAX32657/i2c.h new file mode 100644 index 00000000000..6315f749dd2 --- /dev/null +++ b/Libraries/PeriphDrivers/Include/MAX32657/i2c.h @@ -0,0 +1,928 @@ +/** +* @file i2c.h +* @brief Inter-integrated circuit (I2C) communications interface driver. +*/ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* Define to prevent redundant inclusion */ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_I2C_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_I2C_H_ + +#include +#include +#include "mxc_sys.h" +#include "i2c_regs.h" +#include "dma_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup i2c I2C + * @ingroup periphlibs + * @{ + */ + +/***** Definitions *****/ +#define MXC_I2C_STD_MODE 100000 +#define MXC_I2C_FAST_SPEED 400000 +#define MXC_I2C_FASTPLUS_SPEED 1000000 +#define MXC_I2C_HIGH_SPEED 3400000 + +typedef struct _i2c_req_t mxc_i2c_req_t; +/** + * @brief The callback used by the MXC_I2C_ReadByteInteractive() function. + * + * The callback routine used by the MXC_I2C_ReadByteInteractive() function. This + * function allows the application to determine whether the byte received + * should be acknowledged or not. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param byte The byte received. + * + * @return 0 if the byte should not be acknowledged (NACK), non-zero to + * acknowledge the byte. + */ +typedef int (*mxc_i2c_getAck_t)(mxc_i2c_regs_t *i2c, unsigned char byte); + +/** + * @brief The callback routine used by the MXC_I2C_MasterTransactionAsync() + * function to indicate the transaction has completed. + * + * @param req The details of the transaction. + * @param result 0 if all bytes are acknowledged, 1 if any byte + * transmitted is not acknowledged, negative if error. + * See \ref MXC_Error_Codes for the list of error codes. + */ +typedef void (*mxc_i2c_complete_cb_t)(mxc_i2c_req_t *req, int result); + +/** + * @brief The callback routine used by the I2C Read/Write FIFO DMA + * functions to indicate the transaction has completed. + * + * @param len The length of data actually read/written + * @param result See \ref MXC_Error_Codes for the list of error codes. + */ +typedef void (*mxc_i2c_dma_complete_cb_t)(int len, int result); + +/** + * @brief The information required to perform a complete I2C transaction as + * the bus master. + * + * The information required to perform a complete I2C transaction as the bus + * master. This structure is used by the MXC_I2C_MasterTransaction() and + * MXC_I2C_MasterTransactionAsync() functions. + */ +struct _i2c_req_t { + mxc_i2c_regs_t *i2c; ///< Pointer to I2C registers (selects the + ///< I2C block used.) + unsigned int addr; ///< The 7-bit or 10-bit address of the slave. + unsigned char *tx_buf; ///< The buffer containing the bytes to write. + unsigned int tx_len; ///< The number of bytes to write. On return + ///< from the function, this will be set to + ///< the number of bytes actually transmitted. + unsigned char *rx_buf; ///< The buffer to read the data into. + unsigned int rx_len; ///< The number of bytes to read. On return + ///< from the function, this will be set to + ///< the number of bytes actually received. + int restart; ///< Controls whether the transaction is + ///< terminated with a stop or repeated start + ///< condition. Use 0 for a stop, non-zero + ///< for repeated start. + mxc_i2c_complete_cb_t callback; ///< The callback used to indicate the + ///< transaction is complete or an error has + ///< occurred. This field may be set to NULL + ///< if no indication is necessary. This + ///< field is only used by the + ///< MXC_I2C_MasterTransactionAsync() function. + ///< MXC_I2C_MasterTransaction() ignores the + ///< callback field. +}; + +/** + * @brief The list of events reported by the MXC_I2C_SlaveTransaction() and + * MXC_I2C_SlaveTransactionAsync() functions. + * + * The list of events reported by the MXC_I2C_SlaveTransaction() and + * MXC_I2C_SlaveTransactionAsync() functions. It is up to the calling + * application to handle these events. + */ +typedef enum { + MXC_I2C_EVT_MASTER_WR, ///< A slave address match occurred with the master + ///< requesting a write to the slave. + MXC_I2C_EVT_MASTER_RD, ///< A slave address match occurred with the master + ///< requesting a read from the slave. + MXC_I2C_EVT_RX_THRESH, ///< The receive FIFO contains more bytes than its + ///< threshold level. + MXC_I2C_EVT_TX_THRESH, ///< The transmit FIFO contains fewer bytes than its + ///< threshold level. + MXC_I2C_EVT_TRANS_COMP, ///< The transaction has ended. + MXC_I2C_EVT_UNDERFLOW, ///< The master has attempted a read when the + ///< transmit FIFO was empty. + MXC_I2C_EVT_OVERFLOW, ///< The master has written data when the receive + ///< FIFO was already full. +} mxc_i2c_slave_event_t; + +/** + * @brief The callback routine used by the MXC_I2C_SlaveTransaction() and + * MXC_I2C_SlaveTransactionAsync functions to handle the various I2C + * slave events. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param event The event that occurred to trigger this callback. + * @param data This field is used to pass Success/Fail for the + * MXC_I2C_EVT_TRANS_COMP event. + * + * @return The return value is only used in the case of an MXC_I2C_EVT_RX_THRESH + * event. In this case, the return specifies if the last byte + * received should be acknowledged or not. Return 0 to acknowledge, + * non-zero to not acknowledge. The return value is ignored for all + * other event types. + */ +typedef int (*mxc_i2c_slave_handler_t)(mxc_i2c_regs_t *i2c, mxc_i2c_slave_event_t event, + void *data); + +/***** Function Prototypes *****/ + +/* ************************************************************************* */ +/* Control/Configuration functions */ +/* ************************************************************************* */ + +/** + * @brief Initialize and enable I2C peripheral. + * + * @note On default this function enables I2C peripheral clock and i2c gpio pins. + * if you wish to manage clock and gpio related things in upper level instead of here. + * Define MSDK_NO_GPIO_CLK_INIT flag in project.mk file. + * By this flag this function will remove clock and gpio related codes from file. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param masterMode Whether to put the device in master or slave mode. Use + * non-zero + * for master mode, and zero for slave mode. + * @param slaveAddr 7-bit or 10-bit address to use when in slave mode. + * This parameter is ignored when masterMode is non-zero. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_Init(mxc_i2c_regs_t *i2c, int masterMode, unsigned int slaveAddr); + +/** + * @brief Set slave address for I2C instances acting as slaves on the bus. + * @note Set idx to zero, multiple I2C instances acting as slaves on the + * bus is not yet supported. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param slaveAddr 7-bit or 10-bit address to use when in slave mode. + * This parameter is ignored when masterMode is non-zero. + * @param idx Index of the I2C slave. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_SetSlaveAddr(mxc_i2c_regs_t *i2c, unsigned int slaveAddr, int idx); + +/** + * @brief Disable and shutdown I2C peripheral. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_Shutdown(mxc_i2c_regs_t *i2c); + +/** + * @brief Reset the I2C peripheral. + * @note The peripheral will need to be initialized with MXC_I2C_Init() before use + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_Reset(mxc_i2c_regs_t *i2c); + +/** + * @brief Set the frequency of the I2C interface. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param hz The desired frequency in Hertz. + * + * @return Negative if error, otherwise actual speed set. See \ref + * MXC_Error_Codes for the list of error return codes. + */ +int MXC_I2C_SetFrequency(mxc_i2c_regs_t *i2c, unsigned int hz); + +/** + * @brief Get the frequency of the I2C interface. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * + * @return The I2C bus frequency in Hertz + */ +int MXC_I2C_GetFrequency(mxc_i2c_regs_t *i2c); + +/** + * @brief Checks if the given I2C bus can be placed in sleep more. + * + * This functions checks to see if there are any on-going I2C transactions in + * progress. If there are transactions in progress, the application should + * wait until the I2C bus is free before entering a low-power state. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * + * @return #E_NO_ERROR if ready, and non-zero if busy or error. See \ref + * MXC_Error_Codes for the list of error return codes. + */ +int MXC_I2C_ReadyForSleep(mxc_i2c_regs_t *i2c); + +/** + * @brief Enables or disables clock stretching by the slave. + * + * Enables or disables clock stretching by the slave. This function has no + * affect when operating as the master. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param enable Enables clock stretching if non-zero, disables if zero. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_SetClockStretching(mxc_i2c_regs_t *i2c, int enable); + +/** + * @brief Determines if clock stretching has been enabled. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * + * @return Zero if clock stretching is disabled, non-zero otherwise + */ +int MXC_I2C_GetClockStretching(mxc_i2c_regs_t *i2c); + +/** + * @brief Initializes the DMA for I2C DMA transactions. + * + * This function will release any acquired DMA channels before reacquiring and + * reconfiguring selected I2C DMA TX or RX channels. + * + * @param i2c Pointer to I2C registers (selects the I2C block used). + * @param dma Pointer to DMA registers (selects the DMA block used). + * @param use_dma_tx If true, acquire and configure DMA TX channel, else release any + * acquired DMA TX channel. + * @param use_dma_rx If true, acquire and configure DMA RX channel, else release any + * acquired DMA RX channel. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_DMA_Init(mxc_i2c_regs_t *i2c, mxc_dma_regs_t *dma, bool use_dma_tx, bool use_dma_rx); + +/** + * @brief Retreive the DMA TX Channel associated with I2C instance. + * + * @param i2c Pointer to I2C registers (selects the I2C block used). + * + * @return If successful, the DMA TX Channel number is returned. Otherwise, see + * \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_DMA_GetTXChannel(mxc_i2c_regs_t *i2c); + +/** + * @brief Retreive the DMA RX Channel associated with I2C instance. + * + * @param i2c Pointer to I2C registers (selects the I2C block used). + * + * @return If successful, the DMA RX Channel number is returned. Otherwise, see + * \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_DMA_GetRXChannel(mxc_i2c_regs_t *i2c); + +/** + * @brief Sets the I2C instance's DMA TX/RX request select. + * + * @param i2c Pointer to I2C registers (selects the I2C block used). + * @param txData Pointer to transmit buffer. + * @param rxData Pointer to receive buffer. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_DMA_SetRequestSelect(mxc_i2c_regs_t *i2c, uint8_t *txData, uint8_t *rxData); + +/* ************************************************************************* */ +/* Low-level functions */ +/* ************************************************************************* */ + +/** + * @brief Generate a start (or repeated start) condition on the I2C bus. + * + * Generate a start (or repeated start) condition on the I2C bus. This + * function may opt to delay the actual generation of the start condition + * until data is actually transferred. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_Start(mxc_i2c_regs_t *i2c); + +/** + * @brief Generate a stop condition on the I2C bus. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_Stop(mxc_i2c_regs_t *i2c); + +/** + * @brief Write a single byte to the I2C bus. + * + * Write a single byte to the I2C bus. This function assumes the I2C bus is + * already in the proper state (i.e. a start condition has already been + * generated and the bus is in the write phase of an I2C transaction). If any + * bytes are pending in the FIFO (i.e. in the case of clock stretching), this + * function will return E_OVERFLOW. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param byte The byte to transmit. + * + * @return 0 if byte is acknowledged, 1 if not acknowledged, negative if + * error. See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_I2C_WriteByte(mxc_i2c_regs_t *i2c, unsigned char byte); + +/** + * @brief Read a single byte from the I2C bus. + * + * Read a single byte from the I2C bus. This function assumes the I2C bus is + * already in the proper state (i.e. a start condition has already been + * generated and the bus is in the read phase of an I2C transaction). If the FIFO + * is empty, this function will return E_UNDERFLOW. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param byte Pointer to the byte to read into. + * @param ack Whether or not to acknowledge the byte once received. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_ReadByte(mxc_i2c_regs_t *i2c, unsigned char *byte, int ack); + +/** + * @brief Read a single byte from the I2C bus. + * + * Read a single byte from the I2C bus. After the byte is received, the + * provided callback will be used to determine if the byte should be + * acknowledged or not before continuing with the rest of the transaction. + * This function assumes the I2C bus is already in the proper state (i.e. a + * start condition has already been generated and the bus is in the read + * phase of an I2C transaction). This function must be called with clock + * stretching enabled. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param byte Pointer to the byte to read into. + * @param getAck A function to be called to determine whether or not + * to acknowledge the byte once received. A non-zero + * return value will acknowledge the byte. If this + * parameter is set to NULL or its return value is 0, + * the byte received will not be acknowledged (i.e., it + * will be NACKed). + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_ReadByteInteractive(mxc_i2c_regs_t *i2c, unsigned char *byte, mxc_i2c_getAck_t getAck); + +/** + * @brief Write multiple bytes to the I2C bus. + * + * Write multiple bytes to the I2C bus. This function assumes the I2C bus is + * already in the proper state (i.e. a start condition has already been + * generated and the bus is in the write phase of an I2C transaction). + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param bytes The buffer containing the bytes to transmit. + * @param len The number of bytes to write. On return from the + * function, this will be set to the number of bytes + * actually transmitted. + * + * @return 0 if all bytes are acknowledged, 1 if any byte transmitted is not + * acknowledged, negative if error. See \ref MXC_Error_Codes for the + * list of error return codes. + */ +int MXC_I2C_Write(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int *len); + +/** + * @brief Read multiple bytes from the I2C bus. + * + * Read multiple byte from the I2C bus. This function assumes the I2C bus is + * already in the proper state (i.e. a start condition has already been + * generated and the bus is in the read phase of an I2C transaction). + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param bytes The buffer to read the data into. + * @param len The number of bytes to read. On return from the + * function, this will be set to the number of bytes + * actually received. + * @param ack Whether or not to acknowledge the last byte once it is + * received. All previous bytes will be acknowledged. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_Read(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int *len, int ack); + +/** + * @brief Unloads bytes from the receive FIFO. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param bytes The buffer to read the data into. + * @param len The number of bytes to read. + * + * @return The number of bytes actually read. + */ +int MXC_I2C_ReadRXFIFO(mxc_i2c_regs_t *i2c, volatile unsigned char *bytes, unsigned int len); + +/** + * @brief Unloads bytes from the receive FIFO using DMA for longer reads. + * + * @note The operation is not complete until the callback has been called + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param bytes The buffer to read the data into. + * @param len The number of bytes to read. + * @param callback The function to call when the read is complete + * + * @return See \ref MXC_Error_Codes for a list of return values. + */ +int MXC_I2C_ReadRXFIFODMA(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int len, + mxc_i2c_dma_complete_cb_t callback); + +/** + * @brief Get the number of bytes currently available in the receive FIFO. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * + * @return The number of bytes available. + */ +int MXC_I2C_GetRXFIFOAvailable(mxc_i2c_regs_t *i2c); + +/** + * @brief Loads bytes into the transmit FIFO. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param bytes The buffer containing the bytes to write + * @param len The number of bytes to write. + * + * @return The number of bytes actually written. + */ +int MXC_I2C_WriteTXFIFO(mxc_i2c_regs_t *i2c, volatile unsigned char *bytes, unsigned int len); + +/** + * @brief Loads bytes into the transmit FIFO using DMA for longer writes. + * + * @note The operation is not complete until the callback has been called + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param bytes The buffer containing the bytes to write + * @param len The number of bytes to write. + * @param callback The function to call when the read is complete + * + * @return See \ref MXC_Error_Codes for a list of return values + */ +int MXC_I2C_WriteTXFIFODMA(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int len, + mxc_i2c_dma_complete_cb_t callback); + +/** + * @brief Get the amount of free space available in the transmit FIFO. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * + * @return The number of bytes available. + */ +int MXC_I2C_GetTXFIFOAvailable(mxc_i2c_regs_t *i2c); + +/** + * @brief Removes and discards all bytes currently in the receive FIFO. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + */ +void MXC_I2C_ClearRXFIFO(mxc_i2c_regs_t *i2c); + +/** + * @brief Removes and discards all bytes currently in the transmit FIFO. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + */ +void MXC_I2C_ClearTXFIFO(mxc_i2c_regs_t *i2c); + +/** + * @brief Get the presently set interrupt flags. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param flags0 Pointer to variable to store interrupt status for interrupt register intfl0. + * @param flags1 Pointer to variable to store interrupt status for interrupt register intfl1. + */ +int MXC_I2C_GetFlags(mxc_i2c_regs_t *i2c, unsigned int *flags0, unsigned int *flags1); + +/** + * @brief Clears the Interrupt Flags. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param flags0 Flags to clear in interrupt register intfl0. + * @param flags1 Flags to clear in interrupt register intfl1. + */ +void MXC_I2C_ClearFlags(mxc_i2c_regs_t *i2c, unsigned int flags0, unsigned int flags1); + +/** + * @brief Enable Interrupts. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param flags0 Interrupts to be enabled in int->en0 + * @param flags1 Interrupts to be enabled in int->en1 + */ +void MXC_I2C_EnableInt(mxc_i2c_regs_t *i2c, unsigned int flags0, unsigned int flags1); + +/** + * @brief Disable Interrupts. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param flags0 Interrupts to be disabled in int->en0 + * @param flags1 Interrupts to be disabled in int->en1 + */ +void MXC_I2C_DisableInt(mxc_i2c_regs_t *i2c, unsigned int flags0, unsigned int flags1); + +/** + * @brief Enables the slave preload mode + * + * Use this mode to preload the slave TX FIFO with data that can be sent when + * the slave is addressed for a read operation without software intervention. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + */ +void MXC_I2C_EnablePreload(mxc_i2c_regs_t *i2c); + +/** + * @brief Disable the slave preload mode + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + */ +void MXC_I2C_DisablePreload(mxc_i2c_regs_t *i2c); + +/** + * @brief Enables the slave to respond to the general call address + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + */ +void MXC_I2C_EnableGeneralCall(mxc_i2c_regs_t *i2c); + +/** + * @brief Prevents the slave from responding to the general call address + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + */ +void MXC_I2C_DisableGeneralCall(mxc_i2c_regs_t *i2c); + +/** + * @brief Set the I2C Timeout + * + * The I2C timeout determines the amount of time the master will wait while the + * slave is stretching the clock, and the amount of time the slave will stretch + * the clock while waiting for software to unload the fifo. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param timeout Timeout in uS + */ +void MXC_I2C_SetTimeout(mxc_i2c_regs_t *i2c, unsigned int timeout); + +/** + * @brief Get the current I2C timeout + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * + * @return The current timeout in uS + */ +unsigned int MXC_I2C_GetTimeout(mxc_i2c_regs_t *i2c); + +/** + * @brief Attempts to recover the I2C bus, ensuring the I2C lines are idle. + * + * Attempts to recover and reset an I2C bus by sending I2C clocks. During + * each clock cycle, the SDA line is cycled to determine if the master has + * control of the line. The following steps are performed to create one SCL + * clock cycle: + * 1. Drive SCL low + * 2. Verify SCL is low + * 3. Drive SDA low + * 4. Verify SDA is low + * 5. Release SDA allowing it to return high + * 6. Verify SDA is high + * 7. Release SCL allowing it to return high. + * 8. Verify SCL is high + * If any of the steps fail, the bus is considered to still be busy and the + * sequence is repeated up to the requested number of times. If all steps + * succeed, a final stop condition is generated on the I2C bus. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param retries Number of times to attempt the clock cycle sequence. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_Recover(mxc_i2c_regs_t *i2c, unsigned int retries); + +/* ************************************************************************* */ +/* Transaction level functions */ +/* ************************************************************************* */ + +/** + * @brief Performs a blocking I2C master transaction. + * + * Performs a blocking I2C master transaction. These actions will be performed: + * 1. If necessary, generate a start condition on the bus. + * 2. Send the slave address with the low bit set to 0 (indicating a write). + * 3. Transmit req->tx_len bytes of req->tx_buff. + * 4. Generate a repeated start condition on the bus. + * 5. Send the slave address with the low bit set to 1 (indicating a read). + * 6. Receive req->rx_len bytes into req->rx_buf, acknowledging each byte. + * 7. Generate a stop (or repeated start) condition on the bus. + * Steps 3-6 will be skipped if req->tx_len and req->rx_len are both 0. + * Steps 2-4 will be skipped if req->tx_len equals 0. + * Steps 4-6 will be skipped if req->rx_len equals 0. + * + * @param req Pointer to details of the transaction + * + * @return 0 if all bytes are acknowledged, 1 if any byte transmitted is not + * acknowledged, negative if error. See \ref MXC_Error_Codes for the + * list of error return codes. + */ +int MXC_I2C_MasterTransaction(mxc_i2c_req_t *req); + +/** + * @brief Performs a non-blocking I2C master transaction. + * + * Performs a non-blocking I2C master transaction. These actions will be performed: + * 1. If necessary, generate a start condition on the bus. + * 2. Send the slave address with the low bit set to 0 (indicating a write). + * 3. Transmit req->tx_len bytes of req->tx_buff. + * 4. Generate a repeated start condition on the bus. + * 5. Send the slave address with the low bit set to 1 (indicating a read). + * 6. Receive req->rx_len bytes into req->rx_buf, acknowledging each byte. + * 7. Generate a stop (or repeated start) condition on the bus. + * 8. Execute req->callback to indicate the transaction is complete. + * Steps 3-6 will be skipped if tx_len and rx_len are both 0. + * Steps 2-4 will be skipped if tx_len equals 0. + * Steps 4-6 will be skipped if rx_len equals 0. + * + * @note MXC_I2C_AsyncHandler() must be called periodically for this function + * to operate properly. Ideally from the I2C ISR. + * + * @param req Pointer to details of the transaction. The memory + * used by this parameter must remain available until + * the callback is executed. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_MasterTransactionAsync(mxc_i2c_req_t *req); + +/** + * @brief Performs a non-blocking I2C Master transaction using DMA for reduced time + * in the ISR. This function initializes the DMA and acquires DMA channels + * if MXC_I2C_DMA_Init(...) was not called earlier. + * + * It is recommended to initialize the DMA by calling MXC_I2C_DMA_Init(...) function + * before calling MXC_I2C_MasterTransactionDMA(...). This provides flexibility in + * setting up generic DMA channel vectors during run-time without knowing what DMA + * channels will be acquired beforehand. + * + * Performs a non-blocking I2C transaction. These actions will be performed: + * 1. If necessary, generate a start condition on the bus. + * 2. Send the slave address with the low bit set to 0 (indicating a write). + * 3. Transmit req->tx_len bytes of req->tx_buff. + * 4. Generate a repeated start condition on the bus. + * 5. Send the slave address with the low bit set to 1 (indicating a read). + * 6. Receive req->rx_len bytes into req->rx_buf, acknowledging each byte. + * 7. Generate a stop (or repeated start) condition on the bus. + * 8. Execute req->callback to indicate the transaction is complete. + * Steps 3-6 will be skipped if tx_len and rx_len are both 0. + * Steps 2-4 will be skipped if tx_len equals 0. + * Steps 4-6 will be skipped if rx_len equals 0. + * + * @note MXC_I2C_AsyncHandler() must be called periodically for this function + * to operate properly. Ideally from the I2C ISR. + * + * @param req Pointer to details of the transaction. The memory + * used by this parameter must remain available until + * the callback is executed. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_MasterTransactionDMA(mxc_i2c_req_t *req); + +/** + * @brief Performs a blocking I2C slave transaction. + * + * Performs a blocking I2C slave transaction. This function will block until a + * complete transaction with this slave has been performed. A transaction + * begins with the master addressing the slave and ends with a repeated start + * condition, a stop condition, or a bus error. The provided callback + * function will be called for these events: + * - A slave address match occurs with the master requesting a write to + * the slave. + * - A slave address match occurs with the master requesting a read from + * the slave. + * - The receive FIFO crosses the set threshold (see + * MXC_I2C_SetRXThreshold()). The callback code should unload the receive + * FIFO (see MXC_I2C_ReadFIFO()) to allow the master to send more data. + * The return value of the callback function will determine if the + * last byte received should be acknowledged or not. Return 0 to + * acknowledge, non-zero to not acknowledge. + * - The transmit FIFO crosses the set threshold (see + * MXC_I2C_SetTXThreshold()). If the master is expected to read more + * data from this slave, the callback code should add data to the + * transmit FIFO (see MXC_I2C_WriteFIFO()). + * - The transaction ends. If the master was writing to the slave, the + * receive FIFO may still contain valid data that needs to be + * retreived (see MXC_I2C_ReadFIFO()). + * - The transmit FIFO underflows because the master requests data when + * the transmit FIFO is empty. + * - The receive FIFO overflows because the master writes data while the + * receive FIFO was full. + * + * If clock stretching is disabled, careful attention must be paid to the timing + * of the callback to avoid losing data on write or unintentionally nacking a read. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param callback The function to be called when an I2C event occurs. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_SlaveTransaction(mxc_i2c_regs_t *i2c, mxc_i2c_slave_handler_t callback); + +/** + * @brief Performs a non-blocking I2C slave transaction. + * + * Performs a non-blocking I2C slave transaction. This request will remain active + * until a complete transaction with this slave has been performed. A + * transaction begins with the master begins with the master addressing the + * slave and ends with a repeated start condition, a stop condition, or a bus + * error. The provided callback function will be called for these events: + * - A slave address match occurs with the master requesting a write to + * the slave. + * - A slave address match occurs with the master requesting a read from + * the slave. + * - The receive FIFO crosses the set threshold (see + * MXC_I2C_SetRXThreshold()). The callback code should unload the receive + * FIFO (see MXC_I2C_ReadFIFO()) to allow the master to send more data. + * The return value of the callback function will determine if the + * last byte received should be acknowledged or not. Return 0 to + * acknowledge, non-zero to not acknowledge. + * - The transmit FIFO crosses the set threshold (see + * MXC_I2C_SetTXThreshold()). If the master is expected to read more + * data from this slave, the callback code should add data to the + * transmit FIFO (see MXC_I2C_WriteFIFO()). + * - The transaction ends. If the master was writing to the slave, the + * receive FIFO may still contain valid data that needs to be + * retreived (see MXC_I2C_ReadFIFO()). + * - The transmit FIFO underflows because the master requests data when + * the transmit FIFO is empty. + * - The receive FIFO overflows because the master writes data while the + * receive FIFO was full. + * + * If clock stretching is disabled, careful attention must be paid to the timing + * of the callback to avoid losing data on write or unintentionally nacking a read. + * + * @note MXC_I2C_AsyncHandler() must be called peridocally for this function + * to operate properly. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param callback The function to be called when an I2C event occurs. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_SlaveTransactionAsync(mxc_i2c_regs_t *i2c, mxc_i2c_slave_handler_t callback); + +/** + * @brief Set the receive threshold level. + * + * When operating as a master, the function sets the receive threshold level + * for when the master should unload the receive FIFO. Smaller values may + * consume more CPU cycles, but decrease the chances of the master delaying + * the generation of I2C bus clocks because it has no room in the FIFO to + * receive data. Larger values may consume fewer CPU cycles, but risk delays + * of the I2C clock. When operating as a slave, this function sets the number + * of bytes the slave transaction functions should receive before issuing a + * call to their callback function. Smaller values may consume more CPU + * cycles, but reduce the risk of missing data from the master due to the + * recieve FIFO being full. Larger values may reduce the number of CPU + * cycles, but may cause bytes sent from the master to be missed. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param numBytes The threshold level to set. This value must be + * between 0 and 8 inclusive. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_SetRXThreshold(mxc_i2c_regs_t *i2c, unsigned int numBytes); + +/** + * @brief Get the current receive threshold level. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * + * @return The receive threshold value (in bytes). + */ +int MXC_I2C_GetRXThreshold(mxc_i2c_regs_t *i2c); + +/** + * @brief Set the transmit threshold level. + * + * When operating as a master, the function sets the transmit threshold level + * for when the master should add additional bytes to the transmit FIFO. + * Larger values may consume more CPU cycles, but decrease the chances of the + * master delaying the generation of I2C bus clocks because it has no data in + * the FIFO to transmit. Smaller values may consume fewer CPU cycles, but + * risk delays of the I2C clock. When operating as a slave, this function + * sets the number of bytes the slave transaction functions should transmit + * before issuing a call to their callback function. Larger values may + * consume more CPU cycles, but reduce the risk of not having data ready when + * the master requests it. Smaller values may reduce the number of CPU + * cycles, but may cause the master to read from an empty FIFO. (The master + * will read 0xFF in this case.) + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * @param numBytes The threshold level to set. This value must be + * between 0 and 8 inclusive. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_I2C_SetTXThreshold(mxc_i2c_regs_t *i2c, unsigned int numBytes); + +/** + * @brief Get the current transmit threshold level. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + * + * @return The transmit threshold value (in bytes). + */ +int MXC_I2C_GetTXThreshold(mxc_i2c_regs_t *i2c); + +/** + * @brief Stop any asynchronous requests in progress. + * + * Stop any asynchronous requests in progress. Any callbacks associated with + * the active transaction will be NOT executed. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + */ +void MXC_I2C_AsyncStop(mxc_i2c_regs_t *i2c); + +/** + * @brief Abort any asynchronous requests in progress. + * + * Abort any asynchronous requests in progress. Any callbacks associated with + * the active transaction will be executed to indicate when the transaction + * has been terminated. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + */ +void MXC_I2C_AbortAsync(mxc_i2c_regs_t *i2c); + +/** + * @brief The processing function for asynchronous transactions. + * + * When using the asynchronous functions, the application must call this + * function periodically. This can be done from within the I2C interrupt + * handler or periodically by the application if I2C interrupts are disabled. + * + * @param i2c Pointer to I2C registers (selects the I2C block used.) + */ +void MXC_I2C_AsyncHandler(mxc_i2c_regs_t *i2c); + +/** + * @brief The processing function for DMA transactions. + * + * When using the DMA functions, the application must call this + * function periodically. This can be done from within the DMA Interrupt Handler. + * + * @param ch DMA channel + * @param error Error status + */ +void MXC_I2C_DMACallback(int ch, int error); + +/**@} end of group i2c */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_I2C_H_ diff --git a/Libraries/PeriphDrivers/Include/MAX32657/icc.h b/Libraries/PeriphDrivers/Include/MAX32657/icc.h new file mode 100644 index 00000000000..962cf0217be --- /dev/null +++ b/Libraries/PeriphDrivers/Include/MAX32657/icc.h @@ -0,0 +1,79 @@ +/** + * @file icc.h + * @brief Instruction Controller Cache(ICC) function prototypes and data types. + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* Define to prevent redundant inclusion */ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_ICC_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_ICC_H_ + +/* **** Includes **** */ +#include +#include "icc_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup icc ICC + * @ingroup periphlibs + * @{ + */ + +/** + * @brief Enumeration type for the Cache ID Register + */ +typedef enum { + ICC_INFO_RELNUM, // Identifies the RTL release version + ICC_INFO_PARTNUM, // Specifies the value of C_ID Port Number + ICC_INFO_ID // Specifies the value of Cache ID +} mxc_icc_info_t; + +/** + * @brief Reads the data from the Cache Id Register. + * @param cid Enumeration type for Cache Id Register. + * @retval Returns the contents of Cache Id Register. + */ +int MXC_ICC_ID(mxc_icc_regs_t *icc, mxc_icc_info_t cid); + +/** + * @brief Enable the instruction cache controller. + */ +void MXC_ICC_Enable(mxc_icc_regs_t *icc); + +/** + * @brief Disable the instruction cache controller. + */ +void MXC_ICC_Disable(mxc_icc_regs_t *icc); + +/** + * @brief Flush the instruction cache controller. + */ +void MXC_ICC_Flush(mxc_icc_regs_t *icc); + +/**@} end of group icc */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_ICC_H_ diff --git a/Libraries/PeriphDrivers/Include/MAX32657/lp.h b/Libraries/PeriphDrivers/Include/MAX32657/lp.h new file mode 100644 index 00000000000..bd9c7b0b9e8 --- /dev/null +++ b/Libraries/PeriphDrivers/Include/MAX32657/lp.h @@ -0,0 +1,248 @@ +/** + * @file lp.h + * @brief Low Power(LP) function prototypes and data types. + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* Define to prevent redundant inclusion */ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_LP_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_LP_H_ + +/* **** Includes **** */ +#include +#include "pwrseq_regs.h" +#include "mcr_regs.h" +#include "gcr_regs.h" +#include "gpio.h" +#include "tmr.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup pwrseq Low Power (LP) + * @ingroup periphlibs + * @{ + */ + +/** + * @brief Enumeration type for voltage selection + * + */ +typedef enum { MXC_LP_V0_9 = 0, MXC_LP_V1_0, MXC_LP_V1_1 } mxc_lp_ovr_t; + +/** + * @brief Enumeration type for PM Mode + * + */ +typedef enum { + MXC_LP_IPO = MXC_F_GCR_PM_IPO_PD, + MXC_LP_IBRO = MXC_F_GCR_PM_IBRO_PD, +} mxc_lp_cfg_ds_pd_t; + +/** + * @brief Places the device into SLEEP mode. This function returns once an RTC or external interrupt occur. + */ +void MXC_LP_EnterSleepMode(void); + +/** + * @brief Places the device into Low Power mode. This function returns once an RTC or external interrupt occur. + */ +void MXC_LP_EnterLowPowerMode(void); + +/** + * @brief Places the device into Micro Power mode. This function returns once an RTC or external interrupt occur. + */ +void MXC_LP_EnterMicroPowerMode(void); + +/** + * @brief Places the device into Standby mode. This function returns once an RTC or external interrupt occur. + */ +void MXC_LP_EnterStandbyMode(void); + +/** + * @brief Places the device into BACKUP mode. CPU state is not maintained in this mode, so this function never returns. + * Instead, the device will restart once an RTC or external interrupt occur. + */ +void MXC_LP_EnterBackupMode(void); + +/** + * @brief Places the device into Shutdown mode. CPU state is not maintained in this mode, so this function never returns. + * Instead, the device will restart once an RTC, USB wakeup, or external interrupt occur. + */ +void MXC_LP_EnterPowerDownMode(void); + +/** + * @brief Set ovr bits to set the voltage the micro will run at. + * + * @param[in] ovr The ovr options are only 0.9V, 1.0V, and 1.1V use enum mxc_lp_ovr_t + */ +void MXC_LP_SetOVR(mxc_lp_ovr_t ovr); + +/** + * @brief Turn bandgap on + */ +void MXC_LP_BandgapOn(void); + +/** + * @brief Turn bandgap off + */ +void MXC_LP_BandgapOff(void); + +/** + * @brief Is the bandgap on or off + * + * @return 1 = bandgap on , 0 = bandgap off + */ +int MXC_LP_BandgapIsOn(void); + +/** + * @brief clear all wake up status + */ +void MXC_LP_ClearWakeStatus(void); + +/** + * @brief Enables the selected GPIO port and its selected pins to wake up the device from any low power mode. + * Call this function multiple times to enable pins on multiple ports. This function does not configure + * the GPIO pins nor does it setup their interrupt functionality. + * @param wu_pins The port and pins to configure as wakeup sources. Only the gpio and mask fields of the + * structure are used. The func and pad fields are ignored. + */ + +void MXC_LP_EnableGPIOWakeup(mxc_gpio_cfg_t *wu_pins); + +/** + * @brief Disables the selected GPIO port and its selected pins as a wake up source. + * Call this function multiple times to disable pins on multiple ports. + * @param wu_pins The port and pins to disable as wakeup sources. Only the gpio and mask fields of the + * structure are used. The func and pad fields are ignored. + */ +void MXC_LP_DisableGPIOWakeup(mxc_gpio_cfg_t *wu_pins); + +/** + * @brief Enables the RTC alarm to wake up the device from any low power mode. + */ +void MXC_LP_EnableRTCAlarmWakeup(void); + +/** + * @brief Disables the RTC alarm from waking up the device. + */ +void MXC_LP_DisableRTCAlarmWakeup(void); + +/** + * @brief Enables Timer to wakeup from any low power mode. + * + * @param tmr Pointer to timer module. + */ +void MXC_LP_EnableTimerWakeup(mxc_tmr_regs_t *tmr); + +/** + * @brief Disables Timer from waking up device. + * + * @param tmr Pointer to timer module. + */ +void MXC_LP_DisableTimerWakeup(mxc_tmr_regs_t *tmr); + +/** + * @brief Enables the USB to wake up the device from any low power mode. + */ +void MXC_LP_EnableUSBWakeup(void); + +/** + * @brief Disables the USB from waking up the device. + */ +void MXC_LP_DisableUSBWakeup(void); + +/** + * @brief Enables the WUT alarm to wake up the device from any low power mode. + */ +void MXC_LP_EnableWUTAlarmWakeup(void); + +/** + * @brief Disables the WUT alarm from waking up the device. + */ +void MXC_LP_DisableWUTAlarmWakeup(void); + +/** + * @brief Enables the LPCMP to wake up the device from any low power mode. + */ +void MXC_LP_EnableLPCMPWakeup(mxc_lpcmp_cmpsel_t cmp); + +/** + * @brief Disables the LPCMP from waking up the device. + */ +void MXC_LP_DisableLPCMPWakeup(mxc_lpcmp_cmpsel_t cmp); + +/** + * @brief Enables the HA0 to wake up the device from any low power mode. + */ +void MXC_LP_EnableHA0Wakeup(void); + +/** + * @brief Disables the HA)0 from waking up the device. + */ +void MXC_LP_DisableHA0Wakeup(void); +/** + * @brief Enables the HA1 to wake up the device from any low power mode. + */ +void MXC_LP_EnableHA1Wakeup(void); + +/** + * @brief Disables the HA1 from waking up the device. + */ +void MXC_LP_DisableHA1Wakeup(void); + +/** + * @brief Configure which clocks are powered down at deep sleep and which are not affected. + * + * @note Need to configure all clocks at once any clock not passed in the mask will be unaffected by Deepsleep. This will + * always overwrite the previous settings of ALL clocks. + * + * @param[in] mask The mask of the clocks to power down when part goes into deepsleep + * + * @return #E_NO_ERROR or error based on /ref MXC_Error_Codes + */ +int MXC_LP_ConfigDeepSleepClocks(uint32_t mask); + +/** + * @brief Enable NFC Oscilator Bypass + */ +void MXC_LP_NFCOscBypassEnable(void); + +/** + * @brief Disable NFC Oscilator Bypass + */ +void MXC_LP_NFCOscBypassDisable(void); + +/** + * @brief Is NFC Oscilator Bypass Enabled + * + * @return 1 = enabled, 0 = disabled + */ +int MXC_LP_NFCOscBypassIsEnabled(void); + +/**@} end of group pwrseq */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_LP_H_ diff --git a/Libraries/PeriphDrivers/Include/MAX32657/mxc.h b/Libraries/PeriphDrivers/Include/MAX32657/mxc.h index 666f6bbbb55..16256644580 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/mxc.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/mxc.h @@ -1,8 +1,6 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -18,19 +16,8 @@ * ******************************************************************************/ -#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX78000_MXC_H_ -#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX78000_MXC_H_ - -#ifdef __riscv -// TODO(JC): This is a somewhat ugly hack added to avoid -// implicit function warnings on RISC-V projects -// when LIB_BOARD was added to libs.mk. When the -// RISC-V build system is improved to use libs.mk -// this should be removed. -#ifndef LIB_BOARD -#define LIB_BOARD -#endif -#endif +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_H_ #include "mxc_device.h" #include "mxc_delay.h" @@ -47,26 +34,17 @@ /* * Peripheral Driver Includes */ -#include "adc.h" -#include "aes.h" -#include "cameraif.h" -#include "crc.h" #include "dma.h" #include "flc.h" #include "gpio.h" #include "i2c.h" -#include "i2s.h" #include "icc.h" #include "lp.h" -#include "owm.h" -#include "pt.h" #include "rtc.h" -#include "sema.h" #include "spi.h" #include "tmr.h" -#include "trng.h" #include "uart.h" #include "wdt.h" #include "wut.h" -#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX78000_MXC_H_ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_H_ diff --git a/Libraries/PeriphDrivers/Include/MAX32657/mxc_assert.h b/Libraries/PeriphDrivers/Include/MAX32657/mxc_assert.h index d5f490d0934..f87740ca752 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/mxc_assert.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/mxc_assert.h @@ -1,13 +1,11 @@ /** - * @file + * @file mxc_assert.h * @brief Assertion checks for debugging. */ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/Libraries/PeriphDrivers/Include/MAX32657/mxc_delay.h b/Libraries/PeriphDrivers/Include/MAX32657/mxc_delay.h index e88d315a4ea..e3ec9af932c 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/mxc_delay.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/mxc_delay.h @@ -1,13 +1,11 @@ /** - * @file + * @file mxc_delay.h * @brief Asynchronous delay routines based on the SysTick Timer. */ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -71,23 +69,6 @@ extern "C" { */ typedef void (*mxc_delay_complete_t)(int result); -#ifdef __riscv - -/** - * @brief Blocks and delays for the specified number of microseconds. - * @details Uses the Performance Counter to create the requested delay. The current - * and settings of the performance counter registers will be destroyed. - * @param us microseconds to delay - * @return #E_NO_ERROR if no errors, @ref MXC_Error_Codes "error" if unsuccessful. - */ -int MXC_Delay(uint32_t us); - -int MXC_DelayAsync(uint32_t us, mxc_delay_complete_t callback); -int MXC_DelayCheck(void); -void MXC_DelayAbort(void); - -#else - /***** Function Prototypes *****/ /** @@ -109,7 +90,7 @@ int MXC_Delay(uint32_t us); * @note MXC_Delay_handler() must be called from the SysTick interrupt service * routine or at a rate greater than the SysTick overflow rate. * @param us microseconds to delay - * @param callback Function pointer to the function to call after the delay has expired. + * @param callback Function pointer to the function to call after the delay has expired. * @return #E_NO_ERROR if no errors, #E_BUSY if currently servicing another * delay request. */ @@ -137,8 +118,6 @@ void MXC_DelayHandler(void); /**@} end of group MXC_delay */ -#endif /* __riscv */ - #ifdef __cplusplus } #endif diff --git a/Libraries/PeriphDrivers/Include/MAX32657/mxc_device.h b/Libraries/PeriphDrivers/Include/MAX32657/mxc_device.h index 5f19c29c894..ba719631e81 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/mxc_device.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/mxc_device.h @@ -1,8 +1,6 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/Libraries/PeriphDrivers/Include/MAX32657/mxc_errors.h b/Libraries/PeriphDrivers/Include/MAX32657/mxc_errors.h index 125e3b9fca3..b369f40272c 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/mxc_errors.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/mxc_errors.h @@ -1,12 +1,10 @@ /** - * @file + * @file mxc_errors.h * @brief List of common error return codes for Maxim Integrated libraries. */ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/Libraries/PeriphDrivers/Include/MAX32657/mxc_lock.h b/Libraries/PeriphDrivers/Include/MAX32657/mxc_lock.h index 4b53f368493..880692b02c3 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/mxc_lock.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/mxc_lock.h @@ -1,13 +1,11 @@ /** - * @file + * @file mxc_lock.h * @brief Exclusive access lock utility functions. */ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/Libraries/PeriphDrivers/Include/MAX32657/mxc_pins.h b/Libraries/PeriphDrivers/Include/MAX32657/mxc_pins.h index 7a5dab91d6e..c16d1399521 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/mxc_pins.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/mxc_pins.h @@ -5,9 +5,7 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -28,4 +26,84 @@ #include "gpio.h" -// TODO(ME30) +/***** Global Variables *****/ +// Predefined GPIO Configurations +extern const mxc_gpio_cfg_t gpio_cfg_extclk; +extern const mxc_gpio_cfg_t gpio_cfg_i2c0; +extern const mxc_gpio_cfg_t gpio_cfg_i2c1; +extern const mxc_gpio_cfg_t gpio_cfg_i2c2; +extern const mxc_gpio_cfg_t gpio_cfg_i2c2b; +extern const mxc_gpio_cfg_t gpio_cfg_i2c2c; + +extern const mxc_gpio_cfg_t gpio_cfg_uart0; +extern const mxc_gpio_cfg_t gpio_cfg_uart0_flow; +extern const mxc_gpio_cfg_t gpio_cfg_uart0_flow_disable; +extern const mxc_gpio_cfg_t gpio_cfg_uart1; +extern const mxc_gpio_cfg_t gpio_cfg_uart1_flow; +extern const mxc_gpio_cfg_t gpio_cfg_uart1_flow_disable; +extern const mxc_gpio_cfg_t gpio_cfg_uart2; +extern const mxc_gpio_cfg_t gpio_cfg_uart2_flow; +extern const mxc_gpio_cfg_t gpio_cfg_uart2_flow_disable; +extern const mxc_gpio_cfg_t gpio_cfg_uart3; + +extern const mxc_gpio_cfg_t antenna_ctrl0; +extern const mxc_gpio_cfg_t antenna_ctrl1; + +// Timers are only defined once, depending on package, each timer could be mapped to other pins +extern const mxc_gpio_cfg_t gpio_cfg_tmr0; +extern const mxc_gpio_cfg_t gpio_cfg_tmr1; +extern const mxc_gpio_cfg_t gpio_cfg_tmr2; +extern const mxc_gpio_cfg_t gpio_cfg_tmr3; +extern const mxc_gpio_cfg_t gpio_cfg_tmr0b; +extern const mxc_gpio_cfg_t gpio_cfg_tmr1b; +extern const mxc_gpio_cfg_t gpio_cfg_tmr1_MapB; +extern const mxc_gpio_cfg_t gpio_cfg_tmr2b; +extern const mxc_gpio_cfg_t gpio_cfg_tmr3b; + +extern const mxc_gpio_cfg_t gpio_cfg_i2s0; +extern const mxc_gpio_cfg_t gpio_cfg_i2s0_clkext; + +extern const mxc_gpio_cfg_t gpio_cfg_owm; +extern const mxc_gpio_cfg_t gpio_cfg_owmb; + +extern const mxc_gpio_cfg_t gpio_cfg_rtcsqw; +extern const mxc_gpio_cfg_t gpio_cfg_rtcsqwb; + +extern const mxc_gpio_cfg_t gpio_cfg_pt0; +extern const mxc_gpio_cfg_t gpio_cfg_pt1; +extern const mxc_gpio_cfg_t gpio_cfg_pt2; +extern const mxc_gpio_cfg_t gpio_cfg_pt3; + +extern const mxc_gpio_cfg_t gpio_cfg_adc_ain0; +extern const mxc_gpio_cfg_t gpio_cfg_adc_ain1; +extern const mxc_gpio_cfg_t gpio_cfg_adc_ain2; +extern const mxc_gpio_cfg_t gpio_cfg_adc_ain3; +extern const mxc_gpio_cfg_t gpio_cfg_adc_ain4; +extern const mxc_gpio_cfg_t gpio_cfg_adc_ain5; +extern const mxc_gpio_cfg_t gpio_cfg_adc_ain6; +extern const mxc_gpio_cfg_t gpio_cfg_adc_ain7; + +extern const mxc_gpio_cfg_t gpio_cfg_rv_jtag; + +extern const mxc_gpio_cfg_t gpio_cfg_cmp0; +extern const mxc_gpio_cfg_t gpio_cfg_cmp1; +extern const mxc_gpio_cfg_t gpio_cfg_cmp2; +extern const mxc_gpio_cfg_t gpio_cfg_cmp3; + +// SPI v2 Pin Definitions +extern const mxc_gpio_cfg_t gpio_cfg_spi0_standard; +extern const mxc_gpio_cfg_t gpio_cfg_spi0_3wire; +extern const mxc_gpio_cfg_t gpio_cfg_spi0_dual; +extern const mxc_gpio_cfg_t gpio_cfg_spi0_quad; +extern const mxc_gpio_cfg_t gpio_cfg_spi1_standard; +extern const mxc_gpio_cfg_t gpio_cfg_spi1_3wire; +extern const mxc_gpio_cfg_t gpio_cfg_spi1_dual; +extern const mxc_gpio_cfg_t gpio_cfg_spi1_quad; + +// SPI v2 Target Selects Pin Definitions +extern const mxc_gpio_cfg_t gpio_cfg_spi0_ts0; +extern const mxc_gpio_cfg_t gpio_cfg_spi0_ts1; +extern const mxc_gpio_cfg_t gpio_cfg_spi0_ts2; +extern const mxc_gpio_cfg_t gpio_cfg_spi1_ts0; + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_PINS_H_ diff --git a/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h b/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h index ded3b795ffa..2bb366ac654 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h @@ -1,8 +1,6 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -27,8 +25,8 @@ #define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_SYS_H_ #include "mxc_device.h" -#include "lpgcr_regs.h" #include "gcr_regs.h" +#include "lpgcr_regs.h" #ifdef __cplusplus extern "C" { @@ -73,6 +71,7 @@ typedef enum { MXC_SYS_RESET1_SMPHR = (MXC_F_GCR_RST1_SMPHR_POS + 32), /**< Reset SMPHR */ MXC_SYS_RESET1_I2C2 = (MXC_F_GCR_RST1_I2C2_POS + 32), /**< Reset I2C2 */ MXC_SYS_RESET1_I2S = (MXC_F_GCR_RST1_I2S_POS + 32), /**< Reset I2S*/ + // MXC_SYS_RESET1_BTLE = (MXC_F_GCR_RST1_BTLE_POS + 32), /**< Reset BTLE*/ MXC_SYS_RESET1_DVS = (MXC_F_GCR_RST1_DVS_POS + 32), /**< Reset DVS */ MXC_SYS_RESET1_SIMO = (MXC_F_GCR_RST1_SIMO_POS + 32), /**< Reset SIMO */ MXC_SYS_RESET1_SPI0 = (MXC_F_GCR_RST1_SPI0_POS + 32), /**< Reset SPI0 */ @@ -134,8 +133,6 @@ typedef enum { (MXC_F_GCR_PCLKDIS1_I2S_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_I2S clock */ MXC_SYS_PERIPH_CLOCK_SPI0 = (MXC_F_GCR_PCLKDIS1_SPI0_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_SPI0 clock */ - MXC_SYS_PERIPH_CLOCK_PCIF = - (MXC_F_GCR_PCLKDIS1_PCIF_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_PCIF clock */ MXC_SYS_PERIPH_CLOCK_I2C2 = (MXC_F_GCR_PCLKDIS1_I2C2_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_I2C2 clock */ MXC_SYS_PERIPH_CLOCK_WDT0 = @@ -146,7 +143,7 @@ typedef enum { MXC_SYS_PERIPH_CLOCK_GPIO2 = (MXC_F_LPGCR_PCLKDIS_GPIO2_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_GPIO2 clock */ MXC_SYS_PERIPH_CLOCK_WDT1 = - (MXC_F_LPGCR_PCLKDIS_WDT1_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_WDT2 clock */ + (MXC_F_LPGCR_PCLKDIS_WDT1_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_WDT1 clock */ MXC_SYS_PERIPH_CLOCK_TMR4 = (MXC_F_LPGCR_PCLKDIS_TMR4_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_TMR4 clock */ MXC_SYS_PERIPH_CLOCK_TMR5 = @@ -159,12 +156,14 @@ typedef enum { /** @brief Enumeration to select System Clock source */ typedef enum { + MXC_SYS_CLOCK_ISO = + MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ISO, /**< Select the Internal Secondary Oscillator (ISO) */ MXC_SYS_CLOCK_IPO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO, /**< Select the Internal Primary Oscillator (IPO) */ MXC_SYS_CLOCK_IBRO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO, /**< Select the Internal Baud Rate Oscillator (IBRO) */ - MXC_SYS_CLOCK_ISO = - MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ISO, /**< Select the Internal Secondary Oscillator (ISO) */ + MXC_SYS_CLOCK_ERFO = + MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO, /**< Select the External RF Crystal Oscillator */ MXC_SYS_CLOCK_INRO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO, /**< Select the Internal Nanoring Oscillator (INRO) */ MXC_SYS_CLOCK_ERTCO = @@ -331,6 +330,24 @@ void MXC_SYS_RTCClockEnable(void); */ int MXC_SYS_RTCClockDisable(void); +/** + * @brief Enables the 32kHz oscillator to be powered down when not in use. + * Only available for ME17 Rev. B and older chips. This has no effect on ME17 + * Rev. A chips. + * + * @returns E_NO_ERROR if everything is successful + */ +void MXC_SYS_RTCClockPowerDownEn(void); + +/** + * @brief Disables the 32kHz oscillator from being powered down when not in use. + * Only available for ME17 Rev. B and older chips. This has no effect on ME17 + * Rev. A chips. + * + * @returns E_NO_ERROR if everything is successful + */ +void MXC_SYS_RTCClockPowerDownDis(void); + /** * @brief Enable System Clock Source without switching to it * @param clock The clock to enable @@ -346,10 +363,12 @@ int MXC_SYS_ClockSourceEnable(mxc_sys_system_clock_t clock); int MXC_SYS_ClockSourceDisable(mxc_sys_system_clock_t clock); /** - * @brief Get the current system clock divider. - * @returns The enumerator for the current system clock divider. + * @brief Select the system clock. + * @param clock Enumeration for desired clock. Note: If using the external clock input be sure to define EXTCLK_FREQ correctly. + * The default EXTCLK_FREQ value is defined in the system_max32655.h file and can be overridden at compile time. + * @returns E_NO_ERROR if everything is successful. */ -mxc_sys_system_clock_div_t MXC_SYS_GetClockDiv(void); +int MXC_SYS_Clock_Select(mxc_sys_system_clock_t clock); /** * @brief Set the system clock divider. @@ -358,12 +377,10 @@ mxc_sys_system_clock_div_t MXC_SYS_GetClockDiv(void); void MXC_SYS_SetClockDiv(mxc_sys_system_clock_div_t div); /** - * @brief Select the system clock. - * @param clock Enumeration for desired clock. Note: If using the external clock input be sure to define EXTCLK_FREQ correctly. - * The default EXTCLK_FREQ value is defined in the system_max32657.h file and can be overridden at compile time. - * @returns E_NO_ERROR if everything is successful. + * @brief Get the system clock divider. + * @returns System clock divider. */ -int MXC_SYS_Clock_Select(mxc_sys_system_clock_t clock); +mxc_sys_system_clock_div_t MXC_SYS_GetClockDiv(void); /** * @brief Wait for a clock to enable with timeout @@ -371,7 +388,6 @@ int MXC_SYS_Clock_Select(mxc_sys_system_clock_t clock); * @return E_NO_ERROR if ready, E_TIME_OUT if timeout */ int MXC_SYS_Clock_Timeout(uint32_t ready); - /** * @brief Reset the peripherals and/or CPU in the rstr0 or rstr1 register. * @param Enumeration for what to reset. Can reset multiple items at once. diff --git a/Libraries/PeriphDrivers/Include/MAX32657/nvic_table.h b/Libraries/PeriphDrivers/Include/MAX32657/nvic_table.h index e13fdfaaba8..0b96279aab5 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/nvic_table.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/nvic_table.h @@ -5,9 +5,7 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -23,16 +21,14 @@ * ******************************************************************************/ -#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX78000_NVIC_TABLE_H_ -#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX78000_NVIC_TABLE_H_ - -#ifndef __riscv +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_NVIC_TABLE_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_NVIC_TABLE_H_ #ifdef __cplusplus extern "C" { #endif -#include "max78000.h" +#include "max32657.h" /** * @brief Set an IRQ hander callback function. If the IRQ table is in @@ -106,6 +102,4 @@ NVIC_GetVector(IRQn_Type irqn) } #endif -#endif /* !__riscv */ - -#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX78000_NVIC_TABLE_H_ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_NVIC_TABLE_H_ diff --git a/Libraries/PeriphDrivers/Include/MAX32657/rtc.h b/Libraries/PeriphDrivers/Include/MAX32657/rtc.h new file mode 100644 index 00000000000..ad8c192a5f9 --- /dev/null +++ b/Libraries/PeriphDrivers/Include/MAX32657/rtc.h @@ -0,0 +1,226 @@ +/** + * @file rtc.h + * @brief Real Time Clock (RTC) functions and prototypes. + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* Define to prevent redundant inclusion */ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_RTC_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_RTC_H_ + +/* **** Includes **** */ +#include +#include "mxc_device.h" +#include "rtc_regs.h" +#include "mxc_sys.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup rtc Real Time Clock (RTC) + * @ingroup periphlibs + * @{ + */ + +#define MXC_RTC_MAX_SSEC (MXC_F_RTC_SSEC_SSEC + 1) +#define MXC_RTC_TRIM_TMR_IRQ \ + 0x0 //Place holder to prevent build errors, RevA function which uses this will never be called + +/* **** Definitions **** */ +/** + * Bitmasks for each of the RTC's Frequency. + */ +typedef enum { + MXC_RTC_F_1HZ = MXC_S_RTC_CTRL_SQW_SEL_FREQ1HZ, /**< 1Hz (Compensated) */ + MXC_RTC_F_512HZ = MXC_S_RTC_CTRL_SQW_SEL_FREQ512HZ, /**< 512Hz (Compensated) */ + MXC_RTC_F_4KHZ = MXC_S_RTC_CTRL_SQW_SEL_FREQ4KHZ, /**< 4Khz */ + MXC_RTC_F_32KHZ = 32, /**< 32Khz */ +} mxc_rtc_freq_sel_t; + +/** + * @brief Bitmasks for each of the RTC's interrupt enables. + */ +typedef enum { + MXC_RTC_INT_EN_LONG = MXC_F_RTC_CTRL_TOD_ALARM_IE, /**< Long-interval alarm interrupt enable */ + MXC_RTC_INT_EN_SHORT = + MXC_F_RTC_CTRL_SSEC_ALARM_IE, /**< Short-interval alarm interrupt enable */ + MXC_RTC_INT_EN_READY = MXC_F_RTC_CTRL_RDY_IE, /**< Timer ready interrupt enable */ +} mxc_rtc_int_en_t; + +/** + * @brief Bitmasks for each of the RTC's interrupt flags. + */ +typedef enum { + MXC_RTC_INT_FL_LONG = MXC_F_RTC_CTRL_TOD_ALARM, /**< Long-interval alarm interrupt flag */ + MXC_RTC_INT_FL_SHORT = MXC_F_RTC_CTRL_SSEC_ALARM, /**< Short-interval alarm interrupt flag */ + MXC_RTC_INT_FL_READY = MXC_F_RTC_CTRL_RDY, /**< Timer ready interrupt flag */ +} mxc_rtc_int_fl_t; + +/** + * @brief Set Time-of-Day alarm value and enable Interrupt + * @param ras 20-bit value 0-0xFFFFF + * @retval returns Success or Fail, see \ref MXC_ERROR_CODES + */ +int MXC_RTC_SetTimeofdayAlarm(uint32_t ras); + +/** + * @brief Set Sub-Second alarm value and enable interrupt, + * @brief this is to be called after the init_rtc() function + * @param rssa 32-bit value 0-0xFFFFFFFF + * @retval returns Success or Fail, see \ref MXC_ERROR_CODES + */ +int MXC_RTC_SetSubsecondAlarm(uint32_t rssa); + +/** + * @brief Start the Real Time Clock (Blocking function) + * @retval returns Success or Fail, see \ref MXC_ERROR_CODES + */ +int MXC_RTC_Start(void); +/** + * @brief Stop the Real Time Clock (Blocking function) + * @retval returns Success or Fail, see \ref MXC_ERROR_CODES + */ +int MXC_RTC_Stop(void); + +/** + * @brief Initialize the sec and ssec registers and enable RTC (Blocking function) + * @param sec set the RTC Sec counter (32-bit) + * @param ssec set the RTC Sub-second counter (12-bit) + * @retval returns Success or Fail, see \ref MXC_ERROR_CODES + */ +int MXC_RTC_Init(uint32_t sec, uint16_t ssec); + +/** + * @brief Allow generation of Square Wave on the SQW pin (Blocking function) + * @param fq Frequency output selection + * @retval returns Success or Fail, see \ref MXC_ERROR_CODES + */ +int MXC_RTC_SquareWaveStart(mxc_rtc_freq_sel_t fq); + +/** + * @brief Stop the generation of square wave (Blocking function) + * @retval returns Success or Fail, see \ref MXC_ERROR_CODES + */ +int MXC_RTC_SquareWaveStop(void); + +/** + * @brief Set Trim register value (Blocking function) + * @param trm set the RTC Trim (8-bit, +/- 127) + * @retval returns Success or Fail, see \ref MXC_ERROR_CODES + */ +int MXC_RTC_Trim(int8_t trm); + +/** + * @brief Enable Interurpts (Blocking function) + * @param mask The bitwise OR of interrupts to enable. + * See #mxc_rtc_int_en_t for available choices. + * @retval returns Success or Fail, see \ref MXC_ERROR_CODES + */ +int MXC_RTC_EnableInt(uint32_t mask); + +/** + * @brief Disable Interurpts (Blocking function) + * @param mask The mask of interrupts to disable. + * See #mxc_rtc_int_en_t for available choices. + * @retval returns Success or Fail, see \ref MXC_ERROR_CODES + */ +int MXC_RTC_DisableInt(uint32_t mask); + +/** + * @brief Gets interrupt flags. + * @retval The bitwise OR of any interrupts flags that are + * currently set. See #mxc_rtc_int_fl_t for the list + * of possible flags. + */ +int MXC_RTC_GetFlags(void); + +/** + * @brief Clear interrupt flags. + * @param flags The bitwise OR of the interrupts flags to cleear. + * See #mxc_rtc_int_fl_t for the list of possible flags. + * @retval returns Success or Fail, see \ref MXC_ERROR_CODES + */ +int MXC_RTC_ClearFlags(int flags); + +/** + * @brief Get SubSecond or E_BUSY, see /ref MXC_ERROR_CODES + * @retval Returns subsecond value + */ +#ifdef __GNUC__ +__attribute__((deprecated("Use MXC_RTC_GetSubSeconds() instead."))) +#endif +int MXC_RTC_GetSubSecond(void); + +/** + * @brief This function stores the current value of the sub-seconds counter into a + * pointer if the RTC is not busy. If the RTC is busy, an error is returned. + * @param ssec Pointer to the variable to store the current sub-seconds value. + * @retval E_NO_ERROR if successful, otherwise an error code (see /ref MXC_ERROR_CODES). + */ +int MXC_RTC_GetSubSeconds(uint32_t *ssec); + +/** + * @brief Get Second or E_BUSY, see /ref MXC_ERROR_CODES + * @retval returns second value + */ +#ifdef __GNUC__ +__attribute__((deprecated("Use MXC_RTC_GetSeconds() instead."))) +#endif +int MXC_RTC_GetSecond(void); + +/** + * @brief This function stores the current value of the seconds counter into a + * pointer if the RTC is not busy. If the RTC is busy, an error is returned. + * @param sec Pointer to the variable to store the current seconds value. + * @retval E_NO_ERROR if successful, otherwise an error code (see /ref MXC_ERROR_CODES). + */ +int MXC_RTC_GetSeconds(uint32_t *sec); + +/** + * @brief Get the current second and sub-second counts + * @param sec pointer to store seconds value + * @param subsec pointer to store subseconds value + * @retval returns Success or Fail, see /ref MXC_ERROR_CODES + */ +int MXC_RTC_GetTime(uint32_t *sec, uint32_t *subsec); + +/** + * @brief Get RTC busy flag. + * @retval returns Success or E_BUSY, see /ref MXC_ERROR_CODES + */ +int MXC_RTC_GetBusyFlag(void); + +/** + * @brief Use the 32 MHz crystal to trim the 32 kHz crystal. + * @details Assumes that RTC interrupts are disabled and 32 MHz crystal is + * enabled and selected as the system clock. + * @retval returns trimmed value of 32 kHz crystal or error, + * see /ref MXC_ERROR_CODES + */ +int MXC_RTC_TrimCrystal(void); + +/**@} end of group rtc */ +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_RTC_H_ diff --git a/Libraries/PeriphDrivers/Include/MAX32657/spi.h b/Libraries/PeriphDrivers/Include/MAX32657/spi.h new file mode 100644 index 00000000000..de855f2cb0e --- /dev/null +++ b/Libraries/PeriphDrivers/Include/MAX32657/spi.h @@ -0,0 +1,703 @@ +/** + * @file spi.h + * @brief Serial Peripheral Interface (SPI) communications driver. + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_SPI_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_SPI_H_ + +/***** includes *******/ +#include +#include "spi_regs.h" +#include "mxc_sys.h" +#include "mxc_assert.h" +#include "gpio.h" +#include "mxc_pins.h" +#include "mxc_lock.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup spi SPI + * @ingroup periphlibs + * @{ + */ + +/***** Definitions *****/ + +/** + * @brief The list of SPI Widths supported + * + * The SPI Width can be set on a per-transaction basis. + * An example use case of SPI_WIDTH_STANDARD_HALFDUPLEX is + * given. + * + * Using a MAX31865 RTD-to-SPI IC, read back the temperature + * The IC requires a SPI Read to be executed as + * 1. Assert SS + * 2. Write an 8bit register address + * 3. Read back the 8 bit register + * 4. Deassert SS + * This can be accomplished with the STANDARD_HALFDUPLEX width + * 1. set txData to the address, txLen=1 + * 2. set rxData to a buffer of 1 byte, rxLen=1 + * 3. The driver will transmit the txData, and after completion of + * txData begin to recieve data, padding MOSI with DefaultTXData + * + */ +typedef enum { + SPI_WIDTH_3WIRE, ///< 1 Data line, half duplex + SPI_WIDTH_STANDARD, ///< MISO/MOSI, full duplex + SPI_WIDTH_DUAL, ///< 2 Data lines, half duplex + SPI_WIDTH_QUAD, ///< 4 Data lines, half duplex +} mxc_spi_width_t; + +/** + * @brief The list of SPI modes + * + * SPI supports four combinations of clock and phase polarity + * + * Clock polarity is controlled using the bit SPIn_CTRL2.cpol + * and determines if the clock is active high or active low + * + * Clock phase determines when the data must be stable for sampling + * + */ +typedef enum { + SPI_MODE_0, ///< clock phase = 0, clock polarity = 0 + SPI_MODE_1, ///< clock phase = 0, clock polarity = 1 + SPI_MODE_2, ///< clock phase = 1, clock polarity = 0 + SPI_MODE_3, ///< clock phase = 1, clock polarity = 1 +} mxc_spi_mode_t; + +typedef struct _mxc_spi_pins_t mxc_spi_pins_t; + +/** + * @brief Structure used to initialize SPI pins. + * + * @note All values must be initialized. + * + * @note True equals pin is set for the spi function false the pin is left to its latest state. + */ +struct _mxc_spi_pins_t { + bool clock; /// 8 bits, use two bytes per character + ///< and pad the MSB of the upper byte with zeros + uint8_t *rxData; ///< Buffer to store received data For character sizes + ///< < 8 bits, pad the MSB of each byte with zeros. For + ///< character sizes > 8 bits, use two bytes per character + ///< and pad the MSB of the upper byte with zeros + uint32_t txLen; ///< Number of bytes to be sent from txData + uint32_t rxLen; ///< Number of bytes to be stored in rxData + uint32_t txCnt; ///< Number of bytes actually transmitted from txData + uint32_t rxCnt; ///< Number of bytes stored in rxData + + spi_complete_cb_t completeCB; ///< Pointer to function called when transaction is complete +}; + +/* ************************************************************************* */ +/* Control/Configuration functions */ +/* ************************************************************************* */ + +/** + * @brief Initialize and enable SPI peripheral. + * + * This function initializes everything necessary to call a SPI transaction function. + * Some parameters are set to defaults as follows: + * SPI Mode - 0 + * SPI Width - SPI_WIDTH_STANDARD (even if quadModeUsed is set) + * + * These parameters can be modified after initialization using low level functions + * + * @note On default this function enables SPI peripheral clock and spi gpio pins. + * if you wish to manage clock and gpio related things in upper level instead of here. + * Define MSDK_NO_GPIO_CLK_INIT flag in project.mk file. + * By this flag this function will remove clock and gpio related codes from file. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param masterMode Whether to put the device in master or slave mode. Use + * non-zero for master mode, and zero for slave mode. + * @param quadModeUsed Whether to obtain control of the SDIO2/3 pins. Use + * non-zero if the pins are needed (if Quad Mode will + * be used), and zero if they are not needed (quad mode + * will never be used). + * @param numSlaves The number of slaves used, if in master mode. This + * is used to obtain control of the necessary SS pins. + * In slave mode this is ignored and SS1 is used. + * @param ssPolarity This field sets the SS active polarity for each + * slave, each bit position corresponds to each SS line. + * @param hz The requested clock frequency. The actual clock frequency + * will be returned by the function if successful. Used in + * master mode only. + * @param pins SPI pin structure. Pins selected as true will be initialized + * for the requested SPI block. Has no effect incase of + * MSDK_NO_GPIO_CLK_INIT has been defined. + * + * @return If successful, the actual clock frequency is returned. Otherwise, see + * \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int quadModeUsed, int numSlaves, + unsigned ssPolarity, unsigned int hz, mxc_spi_pins_t pins); + +/** + * @brief Disable and shutdown SPI peripheral. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_Shutdown(mxc_spi_regs_t *spi); + +/** + * @brief Checks if the given SPI bus can be placed in sleep mode. + * + * This functions checks to see if there are any on-going SPI transactions in + * progress. If there are transactions in progress, the application should + * wait until the SPI bus is free before entering a low-power state. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return #E_NO_ERROR if ready, and non-zero if busy or error. See \ref + * MXC_Error_Codes for the list of error return codes. + */ +int MXC_SPI_ReadyForSleep(mxc_spi_regs_t *spi); + +/** + * @brief Returns the frequency of the clock used as the bit rate generator for a given SPI instance. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return Frequency of the clock used as the bit rate generator + */ +int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t *spi); + +/** + * @brief Set the frequency of the SPI interface. + * + * This function is applicable in Master mode only + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param hz The desired frequency in Hertz. + * + * @return Negative if error, otherwise actual speed set. See \ref + * MXC_Error_Codes for the list of error return codes. + */ +int MXC_SPI_SetFrequency(mxc_spi_regs_t *spi, unsigned int hz); + +/** + * @brief Get the frequency of the SPI interface. + * + * This function is applicable in Master mode only + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return The SPI bus frequency in Hertz + */ +unsigned int MXC_SPI_GetFrequency(mxc_spi_regs_t *spi); + +/** + * @brief Sets the number of bits per character + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param dataSize The number of bits per character + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_SetDataSize(mxc_spi_regs_t *spi, int dataSize); + +/** + * @brief Gets the number of bits per character + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_GetDataSize(mxc_spi_regs_t *spi); + +/** + * @brief Sets Multi-Transaction (MT) mode on or off + * + * This function allows Multi-Transaction Mode to be enabled or disabled. MT Mode + * provides a performance improvement on back-to-back DMA operations. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param mtMode 1 to enable, 0 to disable (default) + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_SetMTMode(mxc_spi_regs_t *spi, int mtMode); + +/** + * @brief Gets the current setting for Multi-Transaction (MT) mode + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return The current value of MT mode, either 1 (enabled) or 0 (disabled) + */ +int MXC_SPI_GetMTMode(mxc_spi_regs_t *spi); + +/* ************************************************************************* */ +/* Low-level functions */ +/* ************************************************************************* */ + +/** + * @brief Sets the slave select (SS) line used for transmissions + * + * This function is applicable in Master mode only + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param ssIdx Slave select index + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_SetSlave(mxc_spi_regs_t *spi, int ssIdx); + +/** + * @brief Gets the slave select (SS) line used for transmissions + * + * This function is applicable in Master mode only + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return slave slect + */ +int MXC_SPI_GetSlave(mxc_spi_regs_t *spi); + +/** + * @brief Sets the SPI width used for transmissions + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param spiWidth SPI Width (3-Wire, Standard, Dual SPI, Quad SPI) + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_SetWidth(mxc_spi_regs_t *spi, mxc_spi_width_t spiWidth); + +/** + * @brief Gets the SPI width used for transmissions + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return Spi Width + */ +mxc_spi_width_t MXC_SPI_GetWidth(mxc_spi_regs_t *spi); + +/** + * @brief Sets the spi mode using clock polarity and clock phase + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param spiMode \ref mxc_spi_mode_t + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_SetMode(mxc_spi_regs_t *spi, mxc_spi_mode_t spiMode); + +/** + * @brief Gets the spi mode + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return mxc_spi_mode_t \ref mxc_spi_mode_t + */ +mxc_spi_mode_t MXC_SPI_GetMode(mxc_spi_regs_t *spi); + +/** + * @brief Starts a SPI Transmission + * + * This function is applicable in Master mode only + * + * The user must ensure that there are no ongoing transmissions before + * calling this function + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_StartTransmission(mxc_spi_regs_t *spi); + +/** + * @brief Checks the SPI Peripheral for an ongoing transmission + * + * This function is applicable in Master mode only + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return Active/Inactive, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_GetActive(mxc_spi_regs_t *spi); + +/** + * @brief Aborts an ongoing SPI Transmission + * + * This function is applicable in Master mode only + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_AbortTransmission(mxc_spi_regs_t *spi); + +/** + * @brief Unloads bytes from the receive FIFO. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param bytes The buffer to read the data into. + * @param len The number of bytes to read. + * + * @return The number of bytes actually read. + */ +unsigned int MXC_SPI_ReadRXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len); + +/** + * @brief Get the number of bytes currently available in the receive FIFO. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return The number of bytes available. + */ +unsigned int MXC_SPI_GetRXFIFOAvailable(mxc_spi_regs_t *spi); + +/** + * @brief Loads bytes into the transmit FIFO. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param bytes The buffer containing the bytes to write + * @param len The number of bytes to write. + * + * @return The number of bytes actually written. + */ +unsigned int MXC_SPI_WriteTXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len); + +/** + * @brief Get the amount of free space available in the transmit FIFO. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return The number of bytes available. + */ +unsigned int MXC_SPI_GetTXFIFOAvailable(mxc_spi_regs_t *spi); + +/** + * @brief Removes and discards all bytes currently in the receive FIFO. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + */ +void MXC_SPI_ClearRXFIFO(mxc_spi_regs_t *spi); + +/** + * @brief Removes and discards all bytes currently in the transmit FIFO. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + */ +void MXC_SPI_ClearTXFIFO(mxc_spi_regs_t *spi); + +/** + * @brief Set the receive threshold level. + * + * RX FIFO Receive threshold. Smaller values will cause + * interrupts to occur more often, but reduce the possibility + * of losing data because of a FIFO overflow. Larger values + * will reduce the time required by the ISR, but increase the + * possibility of data loss. Passing an invalid value will + * cause the driver to use the value already set in the + * appropriate register. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param numBytes The threshold level to set. This value must be + * between 0 and 8 inclusive. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_SetRXThreshold(mxc_spi_regs_t *spi, unsigned int numBytes); + +/** + * @brief Get the current receive threshold level. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return The receive threshold value (in bytes). + */ +unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t *spi); + +/** + * @brief Set the transmit threshold level. + * + * TX FIFO threshold. Smaller values will cause interrupts + * to occur more often, but reduce the possibility of terminating + * a transaction early in master mode, or transmitting invalid data + * in slave mode. Larger values will reduce the time required by + * the ISR, but increase the possibility errors occurring. Passing + * an invalid value will cause the driver to use the value already + * set in the appropriate register. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param numBytes The threshold level to set. This value must be + * between 0 and 8 inclusive. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_SetTXThreshold(mxc_spi_regs_t *spi, unsigned int numBytes); + +/** + * @brief Get the current transmit threshold level. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return The transmit threshold value (in bytes). + */ +unsigned int MXC_SPI_GetTXThreshold(mxc_spi_regs_t *spi); + +/** + * @brief Gets the interrupt flags that are currently set + * + * These functions should not be used while using non-blocking Transaction Level + * functions (Async or DMA) + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + * @return The interrupt flags + */ +unsigned int MXC_SPI_GetFlags(mxc_spi_regs_t *spi); + +/** + * @brief Clears the interrupt flags that are currently set + * + * These functions should not be used while using non-blocking Transaction Level + * functions (Async or DMA) + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * + */ +void MXC_SPI_ClearFlags(mxc_spi_regs_t *spi); + +/** + * @brief Enables specific interrupts + * + * These functions should not be used while using non-blocking Transaction Level + * functions (Async or DMA) + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param intEn The interrupts to be enabled + */ +void MXC_SPI_EnableInt(mxc_spi_regs_t *spi, unsigned int intEn); + +/** + * @brief Disables specific interrupts + * + * These functions should not be used while using non-blocking Transaction Level + * functions (Async or DMA) + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param intDis The interrupts to be disabled + */ +void MXC_SPI_DisableInt(mxc_spi_regs_t *spi, unsigned int intDis); + +/* ************************************************************************* */ +/* Transaction level functions */ +/* ************************************************************************* */ + +/** + * @brief Performs a blocking SPI transaction. + * + * Performs a blocking SPI transaction. + * These actions will be performed in Master Mode: + * 1. Assert the specified SS + * 2. In Full Duplex Modes, send TX data while receiving RX Data + * if rxLen > txLen, pad txData with DefaultTXData + * if txLen > rxLen, discard rxData where rxCnt > rxLen + * 3. In Half Duplex Modes, send TX Data, then receive RX Data + * 4. Deassert the specified SS + * + * These actions will be performed in Slave Mode: + * 1. Fill FIFO with txData + * 2. Wait for SS Assert + * 3. If needed, pad txData with DefaultTXData + * 4. Unload RX FIFO as needed + * 5. On SS Deassert, return + * + * @param req Pointer to details of the transaction + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_SPI_MasterTransaction(mxc_spi_req_t *req); + +/** + * @brief Setup an interrupt-driven SPI transaction + * + * The TX FIFO will be filled with txData, padded with DefaultTXData if necessary + * Relevant interrupts will be enabled, and relevant registers set (SS, Width, etc) + * + * @param req Pointer to details of the transaction + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_SPI_MasterTransactionAsync(mxc_spi_req_t *req); + +/** + * @brief Setup a DMA driven SPI transaction + * + * The TX FIFO will be filled with txData, padded with DefaultTXData if necessary + * Relevant interrupts will be enabled, and relevant registers set (SS, Width, etc) + * + * The lowest-indexed unused DMA channel will be acquired (using the DMA API) and + * set up to load/unload the FIFOs with as few interrupt-based events as + * possible. The channel will be reset and returned to the system at the end of + * the transaction. + * + * @param req Pointer to details of the transaction + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req); + +/** + * @brief Performs a blocking SPI transaction. + * + * Performs a blocking SPI transaction. + * These actions will be performed in Slave Mode: + * 1. Fill FIFO with txData + * 2. Wait for SS Assert + * 3. If needed, pad txData with DefaultTXData + * 4. Unload RX FIFO as needed + * 5. On SS Deassert, return + * + * @param req Pointer to details of the transaction + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_SPI_SlaveTransaction(mxc_spi_req_t *req); + +/** + * @brief Setup an interrupt-driven SPI transaction + * + * The TX FIFO will be filled with txData, padded with DefaultTXData if necessary + * Relevant interrupts will be enabled, and relevant registers set (SS, Width, etc) + * + * @param req Pointer to details of the transactionz + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_SPI_SlaveTransactionAsync(mxc_spi_req_t *req); + +/** + * @brief Setup a DMA driven SPI transaction + * + * The TX FIFO will be filled with txData, padded with DefaultTXData if necessary + * Relevant interrupts will be enabled, and relevant registers set (SS, Width, etc) + * + * The lowest-indexed unused DMA channel will be acquired (using the DMA API) and + * set up to load/unload the FIFOs with as few interrupt-based events as + * possible. The channel will be reset and returned to the system at the end of + * the transaction. + * + * @param req Pointer to details of the transaction + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req); + +/** + * @brief Sets the TX data to transmit as a 'dummy' byte + * + * In single wire master mode, this data is transmitted on MOSI when performing + * an RX (MISO) only transaction. This defaults to 0. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param defaultTXData Data to shift out in RX-only transactions + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_SPI_SetDefaultTXData(mxc_spi_regs_t *spi, unsigned int defaultTXData); + +/** + * @brief Abort any asynchronous requests in progress. + * + * Abort any asynchronous requests in progress. Any callbacks associated with + * the active transaction will be executed to indicate when the transaction + * has been terminated. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + */ +void MXC_SPI_AbortAsync(mxc_spi_regs_t *spi); + +/** + * @brief The processing function for asynchronous transactions. + * + * When using the asynchronous functions, the application must call this + * function periodically. This can be done from within the SPI interrupt + * handler or periodically by the application if SPI interrupts are disabled. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + */ +void MXC_SPI_AsyncHandler(mxc_spi_regs_t *spi); + +/** + * @brief Enable/Disable HW CS control feature. + * + * Depending on the application, the user might need to manually drive the slave select pin. + * The SPI driver automatically drives the SS pin and this function enables/disables this + * feature. + * + * @param spi Pointer to SPI registers (selects the SPI block used.) + * @param state Non-zero values: enable HW SS mode. Zero: disable HW SS mode. + */ +void MXC_SPI_HWSSControl(mxc_spi_regs_t *spi, int state); + +/**@} end of group spi */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_SPI_H_ diff --git a/Libraries/PeriphDrivers/Include/MAX32657/tmr.h b/Libraries/PeriphDrivers/Include/MAX32657/tmr.h new file mode 100644 index 00000000000..89e3feb3760 --- /dev/null +++ b/Libraries/PeriphDrivers/Include/MAX32657/tmr.h @@ -0,0 +1,412 @@ +/** + * @file tmr.h + * @brief Timer (TMR) function prototypes and data types. + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* Define to prevent redundant inclusion */ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_TMR_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_TMR_H_ + +/* **** Includes **** */ +#include "mxc_device.h" +#include "tmr_regs.h" +#include "mxc_sys.h" +#include "gcr_regs.h" +#include "mcr_regs.h" +#include "stdbool.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup tmr Timer (TMR) + * @ingroup periphlibs + * @{ + */ + +/** + * @brief Timer prescaler values + */ +typedef enum { + MXC_TMR_PRES_1 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1, /**< Divide input clock by 1 */ + MXC_TMR_PRES_2 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2, /**< Divide input clock by 2 */ + MXC_TMR_PRES_4 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4, /**< Divide input clock by 4 */ + MXC_TMR_PRES_8 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_8, /**< Divide input clock by 8 */ + MXC_TMR_PRES_16 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_16, /**< Divide input clock by 16 */ + MXC_TMR_PRES_32 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_32, /**< Divide input clock by 32 */ + MXC_TMR_PRES_64 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_64, /**< Divide input clock by 64 */ + MXC_TMR_PRES_128 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_128, /**< Divide input clock by 128 */ + MXC_TMR_PRES_256 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_256, /**< Divide input clock by 256 */ + MXC_TMR_PRES_512 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_512, /**< Divide input clock by 512 */ + MXC_TMR_PRES_1024 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_1024, /**< Divide input clock by 1024 */ + MXC_TMR_PRES_2048 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_2048, /**< Divide input clock by 2048 */ + MXC_TMR_PRES_4096 = MXC_S_TMR_CTRL0_CLKDIV_A_DIV_BY_4096, /**< Divide input clock by 4096 */ + + // Legacy names + TMR_PRES_1 = MXC_TMR_PRES_1, + TMR_PRES_2 = MXC_TMR_PRES_2, + TMR_PRES_4 = MXC_TMR_PRES_4, + TMR_PRES_8 = MXC_TMR_PRES_8, + TMR_PRES_16 = MXC_TMR_PRES_16, + TMR_PRES_32 = MXC_TMR_PRES_32, + TMR_PRES_64 = MXC_TMR_PRES_64, + TMR_PRES_128 = MXC_TMR_PRES_128, + TMR_PRES_256 = MXC_TMR_PRES_256, + TMR_PRES_512 = MXC_TMR_PRES_512, + TMR_PRES_1024 = MXC_TMR_PRES_1024, + TMR_PRES_2048 = MXC_TMR_PRES_2048, + TMR_PRES_4096 = MXC_TMR_PRES_4096 +} mxc_tmr_pres_t; + +/** + * @brief Timer modes + */ +typedef enum { + MXC_TMR_MODE_ONESHOT = MXC_V_TMR_CTRL0_MODE_A_ONE_SHOT, ///< Timer Mode ONESHOT + MXC_TMR_MODE_CONTINUOUS = MXC_V_TMR_CTRL0_MODE_A_CONTINUOUS, ///< Timer Mode CONTINUOUS + MXC_TMR_MODE_COUNTER = MXC_V_TMR_CTRL0_MODE_A_COUNTER, ///< Timer Mode COUNTER + MXC_TMR_MODE_PWM = MXC_V_TMR_CTRL0_MODE_A_PWM, ///< Timer Mode PWM + MXC_TMR_MODE_CAPTURE = MXC_V_TMR_CTRL0_MODE_A_CAPTURE, ///< Timer Mode CAPTURE + MXC_TMR_MODE_COMPARE = MXC_V_TMR_CTRL0_MODE_A_COMPARE, ///< Timer Mode COMPARE + MXC_TMR_MODE_GATED = MXC_V_TMR_CTRL0_MODE_A_GATED, ///< Timer Mode GATED + MXC_TMR_MODE_CAPTURE_COMPARE = MXC_V_TMR_CTRL0_MODE_A_CAPCOMP, ///< Timer Mode CAPTURECOMPARE + MXC_TMR_MODE_DUAL_EDGE = MXC_V_TMR_CTRL0_MODE_A_DUAL_EDGE, ///< Timer Mode DUALEDGE + + // Legacy names + TMR_MODE_ONESHOT = MXC_TMR_MODE_ONESHOT, + TMR_MODE_CONTINUOUS = MXC_TMR_MODE_CONTINUOUS, + TMR_MODE_COUNTER = MXC_TMR_MODE_COUNTER, + TMR_MODE_PWM = MXC_TMR_MODE_PWM, + TMR_MODE_CAPTURE = MXC_TMR_MODE_CAPTURE, + TMR_MODE_COMPARE = MXC_TMR_MODE_COMPARE, + TMR_MODE_GATED = MXC_TMR_MODE_GATED, + TMR_MODE_CAPTURE_COMPARE = MXC_TMR_MODE_CAPTURE_COMPARE, + TMR_MODE_DUAL_EDGE = MXC_TMR_MODE_DUAL_EDGE +} mxc_tmr_mode_t; + +/** + * @brief Timer bit mode + * + */ +typedef enum { + MXC_TMR_BIT_MODE_32 = 0, /**< Timer Mode 32 bit */ + MXC_TMR_BIT_MODE_16A, /**< Timer Mode Lower 16 bit */ + MXC_TMR_BIT_MODE_16B, /**< Timer Mode Upper 16 bit */ + + // Legacy names + TMR_BIT_MODE_32 = MXC_TMR_BIT_MODE_32, + TMR_BIT_MODE_16A = MXC_TMR_BIT_MODE_16A, + TMR_BIT_MODE_16B = MXC_TMR_BIT_MODE_16B, +} mxc_tmr_bit_mode_t; + +/** + * @brief Timer units of time enumeration + */ +typedef enum { + MXC_TMR_UNIT_NANOSEC = 0, /**< Nanosecond Unit Indicator */ + MXC_TMR_UNIT_MICROSEC, /**< Microsecond Unit Indicator */ + MXC_TMR_UNIT_MILLISEC, /**< Millisecond Unit Indicator */ + MXC_TMR_UNIT_SEC, /**< Second Unit Indicator */ + + // Legacy names + TMR_UNIT_NANOSEC = MXC_TMR_UNIT_NANOSEC, + TMR_UNIT_MICROSEC = MXC_TMR_UNIT_MICROSEC, + TMR_UNIT_MILLISEC = MXC_TMR_UNIT_MILLISEC, + TMR_UNIT_SEC = MXC_TMR_UNIT_SEC, +} mxc_tmr_unit_t; + +/** + * @brief Peripheral Clock settings + */ +typedef enum { + MXC_TMR_APB_CLK = 0, /**< PCLK */ + MXC_TMR_EXT_CLK = 1, /**< External Clock */ + MXC_TMR_ISO_CLK = 2, /**< 60MHz Clock */ + MXC_TMR_IBRO_CLK = 3, /**< 7.3728MHz Clock */ + MXC_TMR_ERTCO_CLK = 4, /**< 32.768KHz Clock */ + MXC_TMR_INRO_CLK = 5, /**< 8-30KHz Clock */ + MXC_TMR_IBRO_DIV8_CLK = 6, /**< (7.3728/8)MHz Clock */ + + // Legacy names + /*8M and 60M clocks can be used for Timers 0,1,2 and 3*/ + MXC_TMR_32M_CLK, // Not supported as TMR clock source + MXC_TMR_8M_CLK = MXC_TMR_IBRO_CLK, + /*32K clock can be used for Timers 0,1,2,3 and 4*/ + MXC_TMR_32K_CLK = MXC_TMR_ERTCO_CLK, + /*8K and EXT clocks can only be used for Timers 4 and 5*/ + MXC_TMR_8K_CLK = MXC_TMR_INRO_CLK, +} mxc_tmr_clock_t; + +/** + * @brief Timer Configuration + */ +typedef struct { + mxc_tmr_pres_t pres; /**< Desired timer prescaler */ + mxc_tmr_mode_t mode; /**< Desired timer mode */ + mxc_tmr_bit_mode_t bitMode; /**< Desired timer bits */ + mxc_tmr_clock_t clock; /**< Desired clock source */ + uint32_t cmp_cnt; /**< Compare register value in timer ticks */ + unsigned pol; /**< Polarity (0 or 1) */ +} mxc_tmr_cfg_t; + +/* **** Definitions **** */ +typedef void (*mxc_tmr_complete_t)(int error); + +/* **** Function Prototypes **** */ + +/** + * @brief Initialize timer module clock. + * @note On default this function enables TMR peripheral clock and related GPIOs. + * if you wish to manage clock and gpio related things in upper level instead of here. + * Define MSDK_NO_GPIO_CLK_INIT flag in project.mk file. + * By this flag this function will remove clock and gpio related codes from file. + * + * @param tmr Pointer to timer module to initialize. + * @param cfg System configuration object + * @param init_pins True will initialize pins corresponding to the TMR and False will not if pins are pinned out otherwise it will not + * be used, has no effect incase of MSDK_NO_GPIO_CLK_INIT has been defined. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_TMR_Init(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg, bool init_pins); + +/** + * @brief Shutdown timer module clock. + * @param tmr Pointer to timer module to initialize. + */ +void MXC_TMR_Shutdown(mxc_tmr_regs_t *tmr); + +/** + * @brief Start the timer counting. + * @param tmr Pointer to timer module to initialize. + */ +void MXC_TMR_Start(mxc_tmr_regs_t *tmr); + +/** + * @brief Stop the timer. + * @param tmr Pointer to timer module to initialize. + */ +void MXC_TMR_Stop(mxc_tmr_regs_t *tmr); + +/** + * @brief Set the value of the first transition in PWM mode + * @param tmr Pointer to timer module to initialize. + * @param pwm New pwm count. + * @note Will block until safe to change the period count. + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_TMR_SetPWM(mxc_tmr_regs_t *tmr, uint32_t pwm); + +/** + * @brief Get the timer compare count. + * @param tmr Pointer to timer module to initialize. + * @return Returns the current compare count. + */ +uint32_t MXC_TMR_GetCompare(mxc_tmr_regs_t *tmr); + +/** + * @brief Get the timer capture count. + * @param tmr Pointer to timer module to initialize. + * @return Returns the most recent capture count. + */ +uint32_t MXC_TMR_GetCapture(mxc_tmr_regs_t *tmr); + +/** + * @brief Get the timer count. + * @param tmr Pointer to timer module to initialize. + * @return Returns the current count. + */ +uint32_t MXC_TMR_GetCount(mxc_tmr_regs_t *tmr); + +/** + * @brief Calculate count for required frequency. + * @param tmr Timer + * @param clock Clock source. + * @param prescalar prescalar + * @param frequency required frequency. + * @return Returns the period count. + */ +uint32_t MXC_TMR_GetPeriod(mxc_tmr_regs_t *tmr, mxc_tmr_clock_t clock, uint32_t prescalar, + uint32_t frequency); + +/** + * @brief Clear the timer interrupt. + * @param tmr Pointer to timer module to initialize. + */ +void MXC_TMR_ClearFlags(mxc_tmr_regs_t *tmr); + +/** + * @brief Get the timer interrupt status. + * @param tmr Pointer to timer module to initialize. + * @return Returns the interrupt status. 1 if interrupt has occured. + */ +uint32_t MXC_TMR_GetFlags(mxc_tmr_regs_t *tmr); + +/** + * @brief enable interupt + * + * @param tmr Pointer to timer module to initialize. + */ +void MXC_TMR_EnableInt(mxc_tmr_regs_t *tmr); + +/** + * @brief disable interupt + * + * @param tmr Pointer to timer module to initialize. + */ +void MXC_TMR_DisableInt(mxc_tmr_regs_t *tmr); + +/** + * @brief Enable wakeup from sleep + * + * @param tmr Pointer to timer module to initialize. + * @param cfg System configuration object + */ +void MXC_TMR_EnableWakeup(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg); + +/** + * @brief Disable wakeup from sleep + * + * @param tmr Pointer to timer module to initialize. + * @param cfg System configuration object + */ +void MXC_TMR_DisableWakeup(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg); + +/** + * @brief Set the timer compare count. + * @param tmr Pointer to timer module to initialize. + * @param cmp_cnt New compare count. + * @note In PWM Mode use this to set the value of the second transition. + */ +void MXC_TMR_SetCompare(mxc_tmr_regs_t *tmr, uint32_t cmp_cnt); + +/** + * @brief Set the timer count. + * @param tmr Pointer to timer module to initialize. + * @param cnt New count. + */ +void MXC_TMR_SetCount(mxc_tmr_regs_t *tmr, uint32_t cnt); + +/** + * @brief Dealay for a set periord of time measured in microseconds + * + * @param tmr The timer + * @param us microseconds to delay for + */ +void MXC_TMR_Delay(mxc_tmr_regs_t *tmr, uint32_t us); + +/** + * @brief Start a timer that will time out after a certain number of microseconds + * + * @param tmr The timer + * @param us microseconds to time out after + */ +void MXC_TMR_TO_Start(mxc_tmr_regs_t *tmr, uint32_t us); + +/** + * @brief Check on time out timer + * + * @param tmr The timer + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_TMR_TO_Check(mxc_tmr_regs_t *tmr); + +/** + * @brief Stop the Timeout timer + * + * @param tmr The timer + */ +void MXC_TMR_TO_Stop(mxc_tmr_regs_t *tmr); + +/** + * @brief Clear timeout timer back to zero + * + * @param tmr The timer + */ +void MXC_TMR_TO_Clear(mxc_tmr_regs_t *tmr); + +/** + * @brief Get elapsed time of timeout timer + * + * @param tmr The timer + * + * @return Time that has elapsed in timeout timer + */ +unsigned int MXC_TMR_TO_Elapsed(mxc_tmr_regs_t *tmr); + +/** + * @brief Amount of time remaining until timeour + * + * @param tmr The timer + * + * @return Time that is left until timeout + */ +unsigned int MXC_TMR_TO_Remaining(mxc_tmr_regs_t *tmr); + +/** + * @brief Start stopwatch + * + * @param tmr The timer + */ +void MXC_TMR_SW_Start(mxc_tmr_regs_t *tmr); + +/** + * @brief Stopwatch stop + * + * @param tmr The timer + * + * @return the time when the stopwatch is stopped. + */ +unsigned int MXC_TMR_SW_Stop(mxc_tmr_regs_t *tmr); + +/** + * @brief Get time from timer + * + * @param tmr The timer + * @param ticks The ticks + * @param time The time + * @param units The units + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_TMR_GetTime(mxc_tmr_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tmr_unit_t *units); + +/** + * @brief Get ticks from timer + * + * @param tmr The timer + * @param time The time + * @param units The units + * @param ticks The ticks + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_TMR_GetTicks(mxc_tmr_regs_t *tmr, uint32_t time, mxc_tmr_unit_t units, uint32_t *ticks); + +/**@} end of group tmr */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_TMR_H_ diff --git a/Libraries/PeriphDrivers/Include/MAX32657/trng.h b/Libraries/PeriphDrivers/Include/MAX32657/trng.h new file mode 100644 index 00000000000..6d524edc935 --- /dev/null +++ b/Libraries/PeriphDrivers/Include/MAX32657/trng.h @@ -0,0 +1,127 @@ +/** + * @file trng.h + * @brief Random number generator driver. + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_TRNG_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_TRNG_H_ + +/***** Includes *****/ +#include "trng_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup trng TRNG + * @ingroup periphlibs + * @{ + */ + +/* IN ADDITION TO THIS HEADER, FCL WILL BE SUPPORTED AND PROVIDED IN BINARY FORM */ + +/***** Function Prototypes *****/ +typedef void (*mxc_trng_complete_t)(void *req, int result); + +/* ************************************************************************* */ +/* Global Control/Configuration functions */ +/* ************************************************************************* */ + +/** + * @brief Enable portions of the TRNG + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_TRNG_Init(void); + +/** + * @brief Enable TRNG Interrupts + * + */ +void MXC_TRNG_EnableInt(void); + +/** + * @brief Disable TRNG Interrupts + * + */ +void MXC_TRNG_DisableInt(void); + +/** + * @brief Disable and reset portions of the TRNG + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_TRNG_Shutdown(void); + +/** + * @brief This function should be called from the TRNG ISR Handler + * when using Async functions + */ +void MXC_TRNG_Handler(void); + +/* ************************************************************************* */ +/* True Random Number Generator (TRNG) functions */ +/* ************************************************************************* */ + +/** + * @brief Get a random number + * + * @return A random 32-bit number + */ +int MXC_TRNG_RandomInt(void); + +/** + * @brief Get a random number of length len + * + * @param data Pointer to a location to store the number + * @param len Length of random number in bytes + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_TRNG_Random(uint8_t *data, uint32_t len); + +/** + * @brief Get a random number of length len, do not block while generating data + * @note The user must call MXC_TRNG_Handler() in the ISR + * + * @param data Pointer to a location to store the number + * @param len Length of random number in bytes + * @param callback Function that will be called when all data has been generated + * + */ +void MXC_TRNG_RandomAsync(uint8_t *data, uint32_t len, mxc_trng_complete_t callback); + +/** + * @brief Perform health test of the TRNG entropy source + * + * @return If test fails the function will return E_BAD_STATE (-7), otherwise it will return E_NO_ERROR. + * + * @warning MAX32655 with Rev. A Silicon does not support health tests. (Check MXC_GCR->revision to see which revision your chip is.) + */ +int MXC_TRNG_HealthTest(void); + +#ifdef __cplusplus +} +#endif +/**@} end of group trng */ + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_TRNG_H_ diff --git a/Libraries/PeriphDrivers/Include/MAX32657/uart.h b/Libraries/PeriphDrivers/Include/MAX32657/uart.h new file mode 100644 index 00000000000..8acc38bb9b5 --- /dev/null +++ b/Libraries/PeriphDrivers/Include/MAX32657/uart.h @@ -0,0 +1,734 @@ +/** + * @file uart.h + * @brief Serial Peripheral Interface (UART) communications driver. + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* Define to prevent redundant inclusion */ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_UART_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_UART_H_ + +/***** Definitions *****/ +#include +#include "uart_regs.h" +#include "mxc_sys.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define UART_EXTCLK_FREQ E_BAD_PARAM + +/** + * @defgroup uart UART + * @ingroup periphlibs + * @{ + */ + +typedef struct _mxc_uart_req_t mxc_uart_req_t; +/** + * @brief The list of UART stop bit lengths supported + * + */ +typedef enum { + MXC_UART_STOP_1, ///< UART Stop 1 clock cycle + MXC_UART_STOP_2, ///< UART Stop 2 clock cycle (1.5 clocks for 5 bit characters) +} mxc_uart_stop_t; + +/** + * @brief The list of UART Parity options supported + * + */ +typedef enum { + MXC_UART_PARITY_DISABLE, ///< UART Parity Disabled + MXC_UART_PARITY_EVEN_0, ///< UART Parity Even, 0 based + MXC_UART_PARITY_EVEN_1, ///< UART Parity Even, 1 based + MXC_UART_PARITY_ODD_0, ///< UART Parity Odd, 0 based + MXC_UART_PARITY_ODD_1, ///< UART Parity Odd, 1 based +} mxc_uart_parity_t; + +/** + * @brief The list of UART flow control options supported + * + */ +typedef enum { + MXC_UART_FLOW_DIS, ///< UART Flow Control Disabled + MXC_UART_FLOW_EN, ///< UART Flow Control Enabled +} mxc_uart_flow_t; + +/** + * @brief Clock settings */ +typedef enum { + /*Only available for UARTS 0-2*/ + MXC_UART_APB_CLK = 0, + /*Available for all UARTs*/ + MXC_UART_IBRO_CLK = 2, + /*ERTCO clock can only be used for UART3*/ + MXC_UART_ERTCO_CLK = 4, +} mxc_uart_clock_t; + +/** + * @brief The callback routine used to indicate the transaction has terminated. + * + * @param req The details of the transaction. + * @param result See \ref MXC_Error_Codes for the list of error codes. + */ +typedef void (*mxc_uart_complete_cb_t)(mxc_uart_req_t *req, int result); + +/** + * @brief The callback routine used to indicate the transaction has terminated. + * + * @param req The details of the transaction. + * @param num The number of characters actually copied + * @param result See \ref MXC_Error_Codes for the list of error codes. + */ +typedef void (*mxc_uart_dma_complete_cb_t)(mxc_uart_req_t *req, int num, int result); + +/** + * @brief The information required to perform a complete UART transaction + * + * @note This structure is used by blocking, async, and DMA based transactions. + * @note "callback" only needs to be initialized for interrupt driven (Async) and DMA transactions. + */ +struct _mxc_uart_req_t { + mxc_uart_regs_t *uart; /// 8 bits, use two bytes per character + ///< and pad the MSB of the upper byte with zeros + uint8_t *rxData; ///< Buffer to store received data For character sizes + ///< < 8 bits, pad the MSB of each byte with zeros. For + ///< character sizes > 8 bits, use two bytes per character + ///< and pad the MSB of the upper byte with zeros + uint32_t txLen; ///< Number of bytes to be sent from txData + uint32_t rxLen; ///< Number of bytes to be stored in rxData + volatile uint32_t txCnt; ///< Number of bytes actually transmitted from txData + volatile uint32_t rxCnt; ///< Number of bytes stored in rxData + + mxc_uart_complete_cb_t callback; ///< Pointer to function called when transaction is complete +}; + +/***** Function Prototypes *****/ + +/* ************************************************************************* */ +/* Control/Configuration functions */ +/* ************************************************************************* */ + +/** + * @brief Initialize and enable UART peripheral. + * + * This function initializes everything necessary to call a UART transaction function. + * Some parameters are set to defaults as follows: + * UART Data Size - 8 bits + * UART Stop Bits - 1 bit + * UART Parity - None + * UART Flow Control - None + * + * These parameters can be modified after initialization using low level functions + * + * @note On default this function enables UART peripheral clock. + * if you wish to manage clock and gpio related things in upper level instead of here. + * Define MSDK_NO_GPIO_CLK_INIT flag in project.mk file. + * By this flag this function will remove clock and gpio related codes from file. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param baud The requested clock frequency. The actual clock frequency + * will be returned by the function if successful. + * @param clock Clock source + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_Init(mxc_uart_regs_t *uart, unsigned int baud, mxc_uart_clock_t clock); + +/** + * @brief Disable and shutdown UART peripheral. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_Shutdown(mxc_uart_regs_t *uart); + +/** + * @brief Checks if the given UART bus can be placed in sleep more. + * + * @note This functions checks to see if there are any on-going UART transactions in + * progress. If there are transactions in progress, the application should + * wait until the UART bus is free before entering a low-power state. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return #E_NO_ERROR if ready, and non-zero if busy or error. See \ref + * MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_ReadyForSleep(mxc_uart_regs_t *uart); + +/** + * @brief Set the frequency of the UART interface. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param baud The desired baud rate + * @param clock Clock source + * + * @return Negative if error, otherwise actual speed set. See \ref + * MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_SetFrequency(mxc_uart_regs_t *uart, unsigned int baud, mxc_uart_clock_t clock); + +/** + * @brief Get the frequency of the UART interface. + * + * @note This function is applicable in Master mode only + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return The UART baud rate + */ +int MXC_UART_GetFrequency(mxc_uart_regs_t *uart); + +/** + * @brief Sets the number of bits per character + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param dataSize The number of bits per character (5-8 bits/character are valid) + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_SetDataSize(mxc_uart_regs_t *uart, int dataSize); + +/** + * @brief Sets the number of stop bits sent at the end of a character + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param stopBits The number of stop bits used + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_SetStopBits(mxc_uart_regs_t *uart, mxc_uart_stop_t stopBits); + +/** + * @brief Sets the type of parity generation used + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param parity see \ref UART Parity Types for details + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_SetParity(mxc_uart_regs_t *uart, mxc_uart_parity_t parity); + +/** + * @brief Sets the flow control used + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param flowCtrl see \ref UART Flow Control Types for details + * @param rtsThreshold Number of bytes remaining in the RX FIFO when RTS is asserted + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_SetFlowCtrl(mxc_uart_regs_t *uart, mxc_uart_flow_t flowCtrl, int rtsThreshold); + +/** + * @brief Sets the clock source for the baud rate generator + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param clock Clock source + * + * @return Actual baud rate if successful, otherwise see \ref MXC_Error_Codes + * for a list of return codes. + */ +int MXC_UART_SetClockSource(mxc_uart_regs_t *uart, mxc_uart_clock_t clock); + +/* ************************************************************************* */ +/* Low-level functions */ +/* ************************************************************************* */ + +/** + * @brief Checks the UART Peripheral for an ongoing transmission + * + * @note This function is applicable in Master mode only + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return Active/Inactive, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_GetActive(mxc_uart_regs_t *uart); + +/** + * @brief Aborts an ongoing UART Transmission + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_AbortTransmission(mxc_uart_regs_t *uart); + +/** + * @brief Reads the next available character. If no character is available, this function + * will return an error. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return The character read, otherwise see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_ReadCharacterRaw(mxc_uart_regs_t *uart); + +/** + * @brief Writes a character on the UART. If the character cannot be written because the + * transmit FIFO is currently full, this function returns an error. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param character The character to write + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_WriteCharacterRaw(mxc_uart_regs_t *uart, uint8_t character); + +/** + * @brief Reads the next available character + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return The character read, otherwise see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_ReadCharacter(mxc_uart_regs_t *uart); + +/** + * @brief Writes a character on the UART + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param character The character to write + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_WriteCharacter(mxc_uart_regs_t *uart, uint8_t character); + +/** + * @brief Reads the next available character + * @note This function blocks until len characters are received + * See MXC_UART_TransactionAsync() for a non-blocking version + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param buffer Buffer to store data in + * @param len Number of characters + * + * @return The character read, otherwise see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_Read(mxc_uart_regs_t *uart, uint8_t *buffer, int *len); + +/** + * @brief Writes a byte on the UART + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param byte The buffer of characters to write + * @param len The number of characters to write + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_Write(mxc_uart_regs_t *uart, const uint8_t *byte, int *len); + +/** + * @brief Unloads bytes from the receive FIFO. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param bytes The buffer to read the data into. + * @param len The number of bytes to read. + * + * @return The number of bytes actually read. + */ +unsigned int MXC_UART_ReadRXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len); + +/** + * @brief Unloads bytes from the receive FIFO user DMA for longer reads. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param bytes The buffer to read the data into. + * @param len The number of bytes to read. + * @param callback The function to call when the read is complete + * + * @return See \ref MXC_ERROR_CODES for a list of return values + */ +int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len, + mxc_uart_dma_complete_cb_t callback); + +/** + * @brief Get the number of bytes currently available in the receive FIFO. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return The number of bytes available. + */ +unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart); + +/** + * @brief Loads bytes into the transmit FIFO. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param bytes The buffer containing the bytes to write + * @param len The number of bytes to write. + * + * @return The number of bytes actually written. + */ +unsigned int MXC_UART_WriteTXFIFO(mxc_uart_regs_t *uart, const unsigned char *bytes, + unsigned int len); + +/** + * @brief Loads bytes into the transmit FIFO using DMA for longer writes + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param bytes The buffer containing the bytes to write + * @param len The number of bytes to write. + * @param callback The function to call when the write is complete + * + * @return See \ref MXC_ERROR_CODES for a list of return values + */ +int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, const unsigned char *bytes, unsigned int len, + mxc_uart_dma_complete_cb_t callback); + +/** + * @brief Get the amount of free space available in the transmit FIFO. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return The number of bytes available. + */ +unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart); + +/** + * @brief Removes and discards all bytes currently in the receive FIFO. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_ClearRXFIFO(mxc_uart_regs_t *uart); + +/** + * @brief Removes and discards all bytes currently in the transmit FIFO. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_ClearTXFIFO(mxc_uart_regs_t *uart); + +/** + * @brief Set the receive threshold level. + * + * @note RX FIFO Receive threshold. Smaller values will cause + * interrupts to occur more often, but reduce the possibility + * of losing data because of a FIFO overflow. Larger values + * will reduce the time required by the ISR, but increase the + * possibility of data loss. Passing an invalid value will + * cause the driver to use the value already set in the + * appropriate register. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param numBytes The threshold level to set. This value must be + * between 0 and 8 inclusive. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_SetRXThreshold(mxc_uart_regs_t *uart, unsigned int numBytes); + +/** + * @brief Get the current receive threshold level. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return The receive threshold value (in bytes). + */ +unsigned int MXC_UART_GetRXThreshold(mxc_uart_regs_t *uart); + +/** + * @brief Set the transmit threshold level. + * + * @note TX FIFO threshold. Smaller values will cause interrupts + * to occur more often, but reduce the possibility of terminating + * a transaction early in master mode, or transmitting invalid data + * in slave mode. Larger values will reduce the time required by + * the ISR, but increase the possibility errors occurring. Passing + * an invalid value will cause the driver to use the value already + * set in the appropriate register. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param numBytes The threshold level to set. This value must be + * between 0 and 8 inclusive. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_SetTXThreshold(mxc_uart_regs_t *uart, unsigned int numBytes); + +/** + * @brief Get the current transmit threshold level. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return The transmit threshold value (in bytes). + */ +unsigned int MXC_UART_GetTXThreshold(mxc_uart_regs_t *uart); + +/** + * @brief Gets the interrupt flags that are currently set + * + * @note These functions should not be used while using non-blocking Transaction Level + * functions (Async or DMA) + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return The interrupt flags + */ +unsigned int MXC_UART_GetFlags(mxc_uart_regs_t *uart); + +/** + * @brief Clears the interrupt flags that are currently set + * + * @note These functions should not be used while using non-blocking Transaction Level + * functions (Async or DMA) + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param flags mask of flags to clear + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_ClearFlags(mxc_uart_regs_t *uart, unsigned int flags); + +/** + * @brief Enables specific interrupts + * + * @note These functions should not be used while using non-blocking Transaction Level + * functions (Async or DMA) + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param mask The interrupts to be enabled + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_EnableInt(mxc_uart_regs_t *uart, unsigned int mask); + +/** + * @brief Disables specific interrupts + * + * @note These functions should not be used while using non-blocking Transaction Level + * functions (Async or DMA) + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param mask The interrupts to be disabled + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_DisableInt(mxc_uart_regs_t *uart, unsigned int mask); + +/** + * @brief Gets the status flags that are currently set + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return The status flags + */ +unsigned int MXC_UART_GetStatus(mxc_uart_regs_t *uart); + +/* ************************************************************************* */ +/* Transaction level functions */ +/* ************************************************************************* */ + +/** + * @brief Performs a blocking UART transaction. + * + * @note Performs a blocking UART transaction as follows. + * If tx_len is non-zero, transmit TX data + * Once tx_len has been sent, if rx_len is non-zero, receive data + * + * @param req Pointer to details of the transaction + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_Transaction(mxc_uart_req_t *req); + +/** + * @brief Setup an interrupt-driven UART transaction + * + * @note The TX FIFO will be filled with txData if necessary + * Relevant interrupts will be enabled + * + * @param req Pointer to details of the transaction + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_TransactionAsync(mxc_uart_req_t *req); + +/** + * @brief Setup a DMA driven UART transaction + * + * @note The TX FIFO will be filled with txData if necessary + * Relevant interrupts will be enabled + * The DMA channel indicated by the request will be set up to load/unload the FIFOs + * with as few interrupt-based events as possible. The channel will be reset and + * returned to the system at the end of the transaction. + * + * @param req Pointer to details of the transaction + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_TransactionDMA(mxc_uart_req_t *req); + +/** + * @brief The processing function for DMA transactions. + * + * When using the DMA functions, the application must call this + * function periodically. This can be done from within the DMA Interrupt Handler. + * + * @param ch DMA channel + * @param error Error status + */ +void MXC_UART_DMACallback(int ch, int error); + +/** + * @brief Async callback + * + * @param uart The uart + * @param retVal The ret value + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_AsyncCallback(mxc_uart_regs_t *uart, int retVal); + +/** + * @brief stop any async callbacks + * + * @param uart The uart + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_AsyncStop(mxc_uart_regs_t *uart); + +/** + * @brief Abort any asynchronous requests in progress. + * + * @note Abort any asynchronous requests in progress. Any callbacks associated with + * the active transaction will be executed to indicate when the transaction + * has been terminated. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_AbortAsync(mxc_uart_regs_t *uart); + +/** + * @brief The processing function for asynchronous transactions. + * + * @note When using the asynchronous functions, the application must call this + * function periodically. This can be done from within the UART interrupt + * handler or periodically by the application if UART interrupts are disabled. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return See \ref MXC_Error_Codes for the list of error return codes. + */ +int MXC_UART_AsyncHandler(mxc_uart_regs_t *uart); + +/** + * @brief Provide TXCount for asynchronous transactions.. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return Returns transmit bytes (in FIFO). + */ +uint32_t MXC_UART_GetAsyncTXCount(mxc_uart_req_t *req); + +/** + * @brief Provide RXCount for asynchronous transactions.. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return Returns receive bytes (in FIFO). + */ +uint32_t MXC_UART_GetAsyncRXCount(mxc_uart_req_t *req); + +/** + * @brief Enable or disable automatic DMA interrupt handlers for the UART module. + * + * The @ref MXC_UART_TransactionDMA functions require special interrupt handlers to work. + * + * When "Auto" DMA handlers are enabled, the UART drivers will acquire DMA channels + * and assign the appropriate handlers automatically. The acquired channels are + * released after each transaction. + * + * If "Auto" DMA handlers are disabled, the user must acquire DMA channels manually + * and assign them to the drivers with the @ref MXC_UART_SetTXDMAChannel and + * @ref MXC_UART_SetRXDMAChannel functions. + * + * @param uart Pointer to the UART module's registers. + * @param enable true to enable Auto DMA handlers, false to disable. + * @return 0 on success, or a non-zero error code on failure. + */ +int MXC_UART_SetAutoDMAHandlers(mxc_uart_regs_t *uart, bool enable); + +/** + * @brief Set the TX (Transmit) DMA channel for a UART module. + * + * This function assigns the DMA channel for transmitting data + * when @ref is MXC_UART_SetAutoDMAHandlers disabled. + * + * @param uart Pointer to the UART module's registers. + * @param channel The DMA channel number to be used for @ref MXC_UART_TransactionDMA. + */ +int MXC_UART_SetTXDMAChannel(mxc_uart_regs_t *uart, unsigned int channel); + +/** + * @brief Get the TX (Transmit) DMA channel for a UART module. + * + * This function retrieves the currently assigned DMA channel for transmitting data + * when @ref is MXC_UART_SetAutoDMAHandlers disabled. + * + * @param uart Pointer to the UART module's registers. + * @return The currently assigned TX DMA channel. + */ +int MXC_UART_GetTXDMAChannel(mxc_uart_regs_t *uart); + +/** + * @brief Set the RX (Receive) DMA channel for a UART module. + * + * This function assigns the DMA channel for receiving data + * when @ref is MXC_UART_SetAutoDMAHandlers disabled. + * + * @param uart Pointer to the UART module's registers. + * @param channel The DMA channel number to be used for @ref MXC_UART_TransactionDMA. + */ +int MXC_UART_SetRXDMAChannel(mxc_uart_regs_t *uart, unsigned int channel); + +/** + * @brief Get the RX (Receive) DMA channel for a UART module. + * + * This function retrieves the currently configured DMA channel for receiving data + * when @ref is MXC_UART_SetAutoDMAHandlers disabled. + * + * @param uart Pointer to the UART module's registers. + * @return The currently configured RX DMA channel. + */ +int MXC_UART_GetRXDMAChannel(mxc_uart_regs_t *uart); + +/**@} end of group uart */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_UART_H_ diff --git a/Libraries/PeriphDrivers/Include/MAX32657/wdt.h b/Libraries/PeriphDrivers/Include/MAX32657/wdt.h new file mode 100644 index 00000000000..df1cb667be4 --- /dev/null +++ b/Libraries/PeriphDrivers/Include/MAX32657/wdt.h @@ -0,0 +1,227 @@ +/** + * @file wdt.h + * @brief Watchdog timer (WDT) function prototypes and data types. + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* Define to prevent redundant inclusion */ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_WDT_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_WDT_H_ + +/* **** Includes **** */ +#include +#include "mxc_device.h" +#include "wdt_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup wdt WDT + * @ingroup periphlibs + * @{ + */ + +/* **** Definitions **** */ + +/** @brief Watchdog upper limit period enumeration. + Used to configure the period of the watchdog interrupt */ +typedef enum { + MXC_WDT_PERIOD_2_31 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW31, ///< Period 2^31 + MXC_WDT_PERIOD_2_30 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW30, ///< Period 2^30 + MXC_WDT_PERIOD_2_29 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW29, ///< Period 2^29 + MXC_WDT_PERIOD_2_28 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW28, ///< Period 2^28 + MXC_WDT_PERIOD_2_27 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW27, ///< Period 2^27 + MXC_WDT_PERIOD_2_26 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW26, ///< Period 2^26 + MXC_WDT_PERIOD_2_25 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW25, ///< Period 2^25 + MXC_WDT_PERIOD_2_24 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW24, ///< Period 2^24 + MXC_WDT_PERIOD_2_23 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW23, ///< Period 2^23 + MXC_WDT_PERIOD_2_22 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW22, ///< Period 2^22 + MXC_WDT_PERIOD_2_21 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW21, ///< Period 2^21 + MXC_WDT_PERIOD_2_20 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW20, ///< Period 2^20 + MXC_WDT_PERIOD_2_19 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW19, ///< Period 2^19 + MXC_WDT_PERIOD_2_18 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW18, ///< Period 2^18 + MXC_WDT_PERIOD_2_17 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW17, ///< Period 2^17 + MXC_WDT_PERIOD_2_16 = MXC_S_WDT_CTRL_INT_LATE_VAL_WDT2POW16, ///< Period 2^16 +} mxc_wdt_period_t; + +/** + * @brief Watchdog interrupt flag enumeration + */ +typedef enum { + MXC_WDT_INT_TOO_LATE = MXC_F_WDT_CTRL_INT_LATE, + MXC_WDT_INT_TOO_SOON = MXC_F_WDT_CTRL_INT_EARLY, +} mxc_wdt_int_t; + +/** + * @brief Watchdog reset flag enumeration + */ +typedef enum { + MXC_WDT_RST_TOO_LATE = MXC_F_WDT_CTRL_RST_LATE, + MXC_WDT_RST_TOO_SOON = MXC_F_WDT_CTRL_RST_EARLY, +} mxc_wdt_rst_t; + +/** + * @brief Watchdog mode enumeration + */ +typedef enum { + MXC_WDT_COMPATIBILITY = 0, + MXC_WDT_WINDOWED = 1, +} mxc_wdt_mode_t; + +/** + * @brief Peripheral Clock settings + */ +typedef enum { + MXC_WDT_PCLK = 0, + MXC_WDT_IBRO_CLK, + MXC_WDT_INRO_CLK, + MXC_WDT_ERTCO_CLK +} mxc_wdt_clock_t; + +/** + * @brief Timer Configuration + */ +typedef struct { + mxc_wdt_mode_t mode; ///< WDT mode + mxc_wdt_period_t upperResetPeriod; ///< Reset upper limit + mxc_wdt_period_t lowerResetPeriod; ///< Reset lower limit + mxc_wdt_period_t upperIntPeriod; ///< Interrupt upper limit + mxc_wdt_period_t lowerIntPeriod; ///< Interrupt lower limit +} mxc_wdt_cfg_t; +/* **** Function Prototypes **** */ + +/** + * @brief Initialize the Watchdog Timer + * @note On default this function enables WDT peripheral clock. + * if you wish to manage clock and gpio related things in upper level instead of here. + * Define MSDK_NO_GPIO_CLK_INIT flag in project.mk file. + * By this flag this function will remove clock and gpio related codes from file. + * + * @param wdt Pointer to the watchdog registers + * @param cfg watchdog configuration + * @return See \ref MXC_Error_Codes for the list of error codes. + */ +int MXC_WDT_Init(mxc_wdt_regs_t *wdt, mxc_wdt_cfg_t *cfg); + +/** + * @brief Shutdown the Watchdog Timer + * @param wdt Pointer to the watchdog registers + * @return See \ref MXC_Error_Codes for the list of error codes. + */ +int MXC_WDT_Shutdown(mxc_wdt_regs_t *wdt); + +/** + * @brief Set the period of the watchdog interrupt. + * @param wdt Pointer to watchdog registers. + * @param cfg watchdog configuration. + */ +void MXC_WDT_SetIntPeriod(mxc_wdt_regs_t *wdt, mxc_wdt_cfg_t *cfg); + +/** + * @brief Set the period of the watchdog reset. + * @param wdt Pointer to watchdog registers. + * @param cfg watchdog configuration. + */ +void MXC_WDT_SetResetPeriod(mxc_wdt_regs_t *wdt, mxc_wdt_cfg_t *cfg); + +/** + * @brief Enable the watchdog timer. + * @param wdt Pointer to watchdog registers. + */ +void MXC_WDT_Enable(mxc_wdt_regs_t *wdt); + +/** + * @brief Disable the watchdog timer. + * @param wdt Pointer to watchdog registers. + */ +void MXC_WDT_Disable(mxc_wdt_regs_t *wdt); + +/** + * @brief Enable the watchdog interrupt. + * @param wdt Pointer to watchdog registers. + */ +void MXC_WDT_EnableInt(mxc_wdt_regs_t *wdt); + +/** + * @brief Disable the watchdog interrupt. + * @param wdt Pointer to watchdog registers. + */ +void MXC_WDT_DisableInt(mxc_wdt_regs_t *wdt); + +/** + * @brief Enable the watchdog reset. + * @param wdt Pointer to watchdog registers. + */ +void MXC_WDT_EnableReset(mxc_wdt_regs_t *wdt); + +/** + * @brief Disable the watchdog reset. + * @param wdt Pointer to watchdog registers. + */ +void MXC_WDT_DisableReset(mxc_wdt_regs_t *wdt); + +/** + * @brief Reset the watchdog timer. + * @param wdt Pointer to watchdog registers. + */ +void MXC_WDT_ResetTimer(mxc_wdt_regs_t *wdt); + +/** + * @brief Get the status of the reset flag. + * @param wdt Pointer to watchdog registers. + * @returns 1 if the previous reset was caused by the watchdog, 0 otherwise. + */ +int MXC_WDT_GetResetFlag(mxc_wdt_regs_t *wdt); + +/** + * @brief Clears the reset flag. + * @param wdt Pointer to watchdog registers. + */ +void MXC_WDT_ClearResetFlag(mxc_wdt_regs_t *wdt); + +/** + * @brief Get the status of the interrupt flag. + * @param wdt Pointer to watchdog registers. + * @returns 1 if the interrupt is pending, 0 otherwise. + */ +int MXC_WDT_GetIntFlag(mxc_wdt_regs_t *wdt); + +/** + * @brief Clears the interrupt flag. + * @param wdt Pointer to watchdog registers. + */ +void MXC_WDT_ClearIntFlag(mxc_wdt_regs_t *wdt); + +/** + * @brief Sets clock source. + * @param wdt Pointer to watchdog registers. + * @param clock_source Clock source. + */ +int MXC_WDT_SetClockSource(mxc_wdt_regs_t *wdt, mxc_wdt_clock_t clock_source); + +/**@} end of group wdt */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_WDT_H_ diff --git a/Libraries/PeriphDrivers/Include/MAX32657/wut.h b/Libraries/PeriphDrivers/Include/MAX32657/wut.h new file mode 100644 index 00000000000..187fff5dadf --- /dev/null +++ b/Libraries/PeriphDrivers/Include/MAX32657/wut.h @@ -0,0 +1,285 @@ +/** + * @file wut.h + * @brief Wakeup Timer (WUT) function prototypes and data types. + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* Define to prevent redundant inclusion */ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_WUT_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_WUT_H_ + +/* **** Includes **** */ +#include "mxc_device.h" +#include "wut_regs.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup wut Wakeup Timer (WUT) + * @ingroup periphlibs + * @{ + */ + +/** + * @brief Wakeup Timer prescaler values + */ +typedef enum { + MXC_WUT_PRES_1 = MXC_S_WUT_CTRL_PRES_DIV1, /// Divide input clock by 1 + MXC_WUT_PRES_2 = MXC_S_WUT_CTRL_PRES_DIV2, /// Divide input clock by 2 + MXC_WUT_PRES_4 = MXC_S_WUT_CTRL_PRES_DIV4, /// Divide input clock by 4 + MXC_WUT_PRES_8 = MXC_S_WUT_CTRL_PRES_DIV8, /// Divide input clock by 8 + MXC_WUT_PRES_16 = MXC_S_WUT_CTRL_PRES_DIV16, /// Divide input clock by 16 + MXC_WUT_PRES_32 = MXC_S_WUT_CTRL_PRES_DIV32, /// Divide input clock by 32 + MXC_WUT_PRES_64 = MXC_S_WUT_CTRL_PRES_DIV64, /// Divide input clock by 64 + MXC_WUT_PRES_128 = MXC_S_WUT_CTRL_PRES_DIV128, /// Divide input clock by 128 + MXC_WUT_PRES_256 = MXC_F_WUT_CTRL_PRES3 | + MXC_S_WUT_CTRL_PRES_DIV1, /// Divide input clock by 256 + MXC_WUT_PRES_512 = MXC_F_WUT_CTRL_PRES3 | + MXC_S_WUT_CTRL_PRES_DIV2, /// Divide input clock by 512 + MXC_WUT_PRES_1024 = MXC_F_WUT_CTRL_PRES3 | + MXC_S_WUT_CTRL_PRES_DIV4, /// Divide input clock by 1024 + MXC_WUT_PRES_2048 = MXC_F_WUT_CTRL_PRES3 | + MXC_S_WUT_CTRL_PRES_DIV8, /// Divide input clock by 2048 + MXC_WUT_PRES_4096 = MXC_F_WUT_CTRL_PRES3 | + MXC_S_WUT_CTRL_PRES_DIV16 /// Divide input clock by 4096 +} mxc_wut_pres_t; + +/** + * @brief Wakeup Timer modes + */ +typedef enum { + MXC_WUT_MODE_ONESHOT = MXC_V_WUT_CTRL_TMODE_ONESHOT, /// Wakeup Timer Mode ONESHOT + MXC_WUT_MODE_CONTINUOUS = MXC_V_WUT_CTRL_TMODE_CONTINUOUS, /// Wakeup Timer Mode CONTINUOUS + MXC_WUT_MODE_COUNTER = MXC_V_WUT_CTRL_TMODE_COUNTER, /// Wakeup Timer Mode COUNTER + MXC_WUT_MODE_CAPTURE = MXC_V_WUT_CTRL_TMODE_CAPTURE, /// Wakeup Timer Mode CAPTURE + MXC_WUT_MODE_COMPARE = MXC_V_WUT_CTRL_TMODE_COMPARE, /// Wakeup Timer Mode COMPARE + MXC_WUT_MODE_GATED = MXC_V_WUT_CTRL_TMODE_GATED, /// Wakeup Timer Mode GATED + MXC_WUT_MODE_CAPTURE_COMPARE = + MXC_V_WUT_CTRL_TMODE_CAPTURECOMPARE /// Wakeup Timer Mode CAPTURECOMPARE +} mxc_wut_mode_t; + +/** + * @brief Wakeup Timer units of time enumeration + */ +typedef enum { + MXC_WUT_UNIT_NANOSEC = 0, /**< Nanosecond Unit Indicator. */ + MXC_WUT_UNIT_MICROSEC, /**< Microsecond Unit Indicator. */ + MXC_WUT_UNIT_MILLISEC, /**< Millisecond Unit Indicator. */ + MXC_WUT_UNIT_SEC /**< Second Unit Indicator. */ +} mxc_wut_unit_t; + +/** + * @brief Wakeup Timer Configuration + */ +typedef struct { + mxc_wut_mode_t mode; /// Desired timer mode + uint32_t cmp_cnt; /// Compare register value in timer ticks +} mxc_wut_cfg_t; + +/** + * @brief The callback routine used by the MXC_WUT_TrimCrystalAsync() + * function to indicate the transaction has completed. + * + * @param result Error code. + */ +typedef void (*mxc_wut_complete_cb_t)(int result); + +/* **** Definitions **** */ + +/* **** Function Prototypes **** */ + +/** + * @brief Initialize timer module clock. + * @param wut Pointer to Wakeup Timer instance to initialize. + * @param pres Prescaler value. + */ +void MXC_WUT_Init(mxc_wut_regs_t *wut, mxc_wut_pres_t pres); + +/** + * @brief Shutdown timer module clock. + * @param wut Pointer to Wakeup Timer instance to shutdown. + */ +void MXC_WUT_Shutdown(mxc_wut_regs_t *wut); + +/** + * @brief Enable the timer. + * @param wut Pointer to Wakeup Timer instance to enable. + */ +void MXC_WUT_Enable(mxc_wut_regs_t *wut); + +/** + * @brief Disable the timer. + * @param wut Pointer to Wakeup Timer instance to disable. + */ +void MXC_WUT_Disable(mxc_wut_regs_t *wut); + +/** + * @brief Configure the timer. + * @param wut Pointer to Wakeup Timer instance to configure. + * @param cfg Pointer to timer configuration struct. + */ +void MXC_WUT_Config(mxc_wut_regs_t *wut, const mxc_wut_cfg_t *cfg); + +/** + * @brief Get the timer compare count. + * @param wut Pointer to Wakeup Timer instance to get compare value from. + * @return Returns the current compare count. + */ +uint32_t MXC_WUT_GetCompare(mxc_wut_regs_t *wut); + +/** + * @brief Get the timer count. + * @param wut Pointer to Wakeup Timer instance to get count value from. + * @return Returns the current count. + */ +uint32_t MXC_WUT_GetCount(mxc_wut_regs_t *wut); + +/** + * @brief Clear the timer interrupt. + * @param wut Pointer to Wakeup Timer instance to clear interrupts for. + */ +void MXC_WUT_IntClear(mxc_wut_regs_t *wut); + +/** + * @brief Get the timer interrupt status. + * @param wut Pointer to Wakeup Timer instance to get interrupt staus from. + * @return Returns the interrupt status. 1 if interrupt has occurred. + */ +uint32_t MXC_WUT_IntStatus(mxc_wut_regs_t *wut); + +/** + * @brief Set the timer compare count. + * @param wut Pointer to Wakeup Timer instance to set compare value for. + * @param cmp_cnt New compare count. + * @note This function does not protect against output glitches in PWM mode. + * Use MXC_WUT_PWMSetPeriod when in PWM mode. + */ +void MXC_WUT_SetCompare(mxc_wut_regs_t *wut, uint32_t cmp_cnt); + +/** + * @brief Set the timer count. + * @param wut Pointer to Wakeup Timer instance to set count value for. + * @param cnt New count. + */ +void MXC_WUT_SetCount(mxc_wut_regs_t *wut, uint32_t cnt); + +/** + * @brief Convert real time to timer ticks. + * @param wut Pointer to Wakeup Timer instance to get tick count for. + * @param time Number of units of time. + * @param units Which units of time you want to convert. + * @param ticks Pointer to store the number of ticks calculated. + * @return #E_NO_ERROR If everything is successful. + * @return @ref MXC_Error_Codes If function is unsuccessful. + */ +int MXC_WUT_GetTicks(mxc_wut_regs_t *wut, uint32_t time, mxc_wut_unit_t units, uint32_t *ticks); + +/** + * @brief Convert timer ticks to real time. + * @param wut Pointer to Wakeup Timer instance to get time for. + * @param ticks Number of ticks. + * @param time Pointer to store number of units of time. + * @param units Pointer to store the units that time represents. + * @return #E_NO_ERROR If everything is successful. + * @return @ref MXC_Error_Codes If function is unsuccessful. + */ +int MXC_WUT_GetTime(mxc_wut_regs_t *wut, uint32_t ticks, uint32_t *time, mxc_wut_unit_t *units); + +/** + * @brief Wait for an edge of the WUT count register. + * @param wut Pointer to Wakeup Timer instance to wait on. + */ +void MXC_WUT_Edge(mxc_wut_regs_t *wut); + +/** + * @brief Store the count and snapshot values. + * @param wut Pointer to Wakeup Timer instance to store count and snapshot values for. + */ +void MXC_WUT_Store(mxc_wut_regs_t *wut); + +/** + * @brief Restore the DBB clock with the stored count and snapshot values. + * @param wut Pointer to Wakeup Timer instance restore count and snapshot values for. + * @param dbbFreq Frequency of DBB clock. + */ +void MXC_WUT_RestoreBBClock(mxc_wut_regs_t *wut, uint32_t dbbFreq); + +/** + * @brief Get the difference between the stored counter value + * and the current counter value. + * @param wut Pointer to Wakeup Timer instance to get current sleep ticks for. + * @return Returns the current counter value - stored counter value. + */ +uint32_t MXC_WUT_GetSleepTicks(mxc_wut_regs_t *wut); + +/** + * @brief Delays for the given number of milliseconds. + * @param wut Pointer to Wakeup Timer instance to use as the delay timer. + * @param waitMs Number of milliseconds to wait. + */ +void MXC_WUT_Delay_MS(mxc_wut_regs_t *wut, uint32_t waitMs); + +/** + * @brief Trim the 32 kHz crystal load settings, blocks until complete. + * @param wut Pointer to Wakeup Timer instance to trim. + * @details This procedure uses the WUT and the BLE DBB, driven by the 32 MHz crystal, + * to trim the load settings of the 32 kHz crystal. This procedure will only + * work if the BLE DBB is initialized and running. + * + * @return #E_NO_ERROR If everything is successful. + */ +int MXC_WUT_TrimCrystal(mxc_wut_regs_t *wut); + +/** + * @brief Trim the 32 kHz crystal load settings, non-blocking interrupt based. + * @param wut Pointer to Wakeup Timer instance to trim. + * @details This procedure uses the WUT and the BLE DBB, driven by the 32 MHz crystal, + * to trim the load settings of the 32 kHz crystal. This procedure will only + * work if the BLE DBB is initialized and running. + * + * @param cb Callback for when the trim is complete. + * @return #E_NO_ERROR If everything is successful. + */ +int MXC_WUT_TrimCrystalAsync(mxc_wut_regs_t *wut, mxc_wut_complete_cb_t cb); + +/** + * @brief Check to see if the trim procedure is ongoing. + * @param wut Pointer to Wakeup Timer instance to check trim status for. + * @details Must leave the 32 MHz clock and BLE DBB running while the trim procedure is pending. + * @return #E_NO_ERROR If trim is complete, E_BUSY if trim procedure is ongoing. + */ +int MXC_WUT_TrimPending(mxc_wut_regs_t *wut); + +/** + * @brief Interrupt handler for trim procedure. + * @param wut Pointer to Wakeup Timer instance to handle interrupts for. + * @return #E_NO_ERROR If trim is complete, E_BUSY if trim procedure is ongoing. + */ +int MXC_WUT_Handler(mxc_wut_regs_t *wut); + +/**@} end of group wut */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_WUT_H_ diff --git a/Libraries/PeriphDrivers/Include/MAX32690/spi.h b/Libraries/PeriphDrivers/Include/MAX32690/spi.h index 1063362a87b..b27fa01970e 100644 --- a/Libraries/PeriphDrivers/Include/MAX32690/spi.h +++ b/Libraries/PeriphDrivers/Include/MAX32690/spi.h @@ -591,7 +591,6 @@ unsigned int MXC_SPI_GetTXThreshold(mxc_spi_regs_t *spi); */ unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t *spi); -//////>>> Previous Implementation (SPI v1) /** * @brief Sets the number of bits per character * diff --git a/Libraries/PeriphDrivers/Include/MAX78002/spi.h b/Libraries/PeriphDrivers/Include/MAX78002/spi.h index 4d99415b096..8091c786738 100644 --- a/Libraries/PeriphDrivers/Include/MAX78002/spi.h +++ b/Libraries/PeriphDrivers/Include/MAX78002/spi.h @@ -592,7 +592,6 @@ unsigned int MXC_SPI_GetTXThreshold(mxc_spi_regs_t *spi); */ unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t *spi); -//////>>> Previous Implementation /** * @brief Sets the number of bits per character * From 12429e590fcef9068bce20e0adb9d87c24385339 Mon Sep 17 00:00:00 2001 From: Sadik Ozer Date: Fri, 19 Apr 2024 11:44:40 +0300 Subject: [PATCH 16/93] Add MAX32657 peripheral source files These files are exact copy of MAX32655 Files will be updated in next sections, added here to demonstrate delta clearly on next steps Signed-off-by: Sadik Ozer --- Libraries/PeriphDrivers/Source/AES/aes_me30.c | 155 +++++ Libraries/PeriphDrivers/Source/CRC/crc_me30.c | 99 +++ Libraries/PeriphDrivers/Source/DMA/dma_me30.c | 161 +++++ Libraries/PeriphDrivers/Source/FLC/flc_me30.c | 345 ++++++++++ .../PeriphDrivers/Source/GPIO/gpio_me30.c | 430 +++++++++++++ Libraries/PeriphDrivers/Source/I2C/i2c_me30.c | 413 ++++++++++++ Libraries/PeriphDrivers/Source/ICC/icc_me30.c | 57 ++ Libraries/PeriphDrivers/Source/LP/lp_me30.c | 254 ++++++++ Libraries/PeriphDrivers/Source/RTC/rtc_me30.c | 283 ++++++++ Libraries/PeriphDrivers/Source/SPI/spi_me30.c | 526 +++++++++++++++ .../PeriphDrivers/Source/SYS/pins_me30.c | 163 +++++ Libraries/PeriphDrivers/Source/SYS/sys_me30.c | 605 ++++++++++++++++++ Libraries/PeriphDrivers/Source/TMR/tmr_me30.c | 388 +++++++++++ .../PeriphDrivers/Source/TRNG/trng_me30.c | 93 +++ .../PeriphDrivers/Source/UART/uart_me30.c | 528 +++++++++++++++ Libraries/PeriphDrivers/Source/WDT/wdt_me30.c | 161 +++++ Libraries/PeriphDrivers/Source/WUT/wut_me30.c | 370 +++++++++++ 17 files changed, 5031 insertions(+) create mode 100644 Libraries/PeriphDrivers/Source/AES/aes_me30.c create mode 100644 Libraries/PeriphDrivers/Source/CRC/crc_me30.c create mode 100644 Libraries/PeriphDrivers/Source/DMA/dma_me30.c create mode 100644 Libraries/PeriphDrivers/Source/FLC/flc_me30.c create mode 100644 Libraries/PeriphDrivers/Source/GPIO/gpio_me30.c create mode 100644 Libraries/PeriphDrivers/Source/I2C/i2c_me30.c create mode 100644 Libraries/PeriphDrivers/Source/ICC/icc_me30.c create mode 100644 Libraries/PeriphDrivers/Source/LP/lp_me30.c create mode 100644 Libraries/PeriphDrivers/Source/RTC/rtc_me30.c create mode 100644 Libraries/PeriphDrivers/Source/SPI/spi_me30.c create mode 100644 Libraries/PeriphDrivers/Source/SYS/pins_me30.c create mode 100644 Libraries/PeriphDrivers/Source/SYS/sys_me30.c create mode 100644 Libraries/PeriphDrivers/Source/TMR/tmr_me30.c create mode 100644 Libraries/PeriphDrivers/Source/TRNG/trng_me30.c create mode 100644 Libraries/PeriphDrivers/Source/UART/uart_me30.c create mode 100644 Libraries/PeriphDrivers/Source/WDT/wdt_me30.c create mode 100644 Libraries/PeriphDrivers/Source/WUT/wut_me30.c diff --git a/Libraries/PeriphDrivers/Source/AES/aes_me30.c b/Libraries/PeriphDrivers/Source/AES/aes_me30.c new file mode 100644 index 00000000000..63603f4cf83 --- /dev/null +++ b/Libraries/PeriphDrivers/Source/AES/aes_me30.c @@ -0,0 +1,155 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#include "mxc_device.h" +#include "mxc_errors.h" +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "aes_revb.h" +#include "trng.h" +#include "trng_revb.h" + +/* ************************************************************************* */ +/* Global Control/Configuration functions */ +/* ************************************************************************* */ + +int MXC_AES_Init(void) +{ +#ifndef MSDK_NO_GPIO_CLK_INIT + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_AES); + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TRNG); +#endif + + return MXC_AES_RevB_Init((mxc_aes_revb_regs_t *)MXC_AES); +} + +void MXC_AES_EnableInt(uint32_t interrupt) +{ + MXC_AES_RevB_EnableInt((mxc_aes_revb_regs_t *)MXC_AES, interrupt); +} + +void MXC_AES_DisableInt(uint32_t interrupt) +{ + MXC_AES_RevB_DisableInt((mxc_aes_revb_regs_t *)MXC_AES, interrupt); +} + +int MXC_AES_IsBusy(void) +{ + return MXC_AES_RevB_IsBusy((mxc_aes_revb_regs_t *)MXC_AES); +} + +int MXC_AES_Shutdown(void) +{ + int error = MXC_AES_RevB_Shutdown((mxc_aes_revb_regs_t *)MXC_AES); + + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_AES); + + return error; +} + +void MXC_AES_DMACallback(int ch, int error) +{ + MXC_AES_RevB_DMACallback(ch, error); +} + +void MXC_AES_GenerateKey(void) +{ + // Generating a random key is part of the TRNG block. + MXC_TRNG_RevB_GenerateKey((mxc_trng_revb_regs_t *)MXC_TRNG); +} + +void MXC_AES_SetKeySize(mxc_aes_keys_t key) +{ + MXC_AES_RevB_SetKeySize((mxc_aes_revb_regs_t *)MXC_AES, (mxc_aes_revb_keys_t)key); +} + +mxc_aes_keys_t MXC_AES_GetKeySize(void) +{ + return MXC_AES_RevB_GetKeySize((mxc_aes_revb_regs_t *)MXC_AES); +} + +void MXC_AES_FlushInputFIFO(void) +{ + MXC_AES_RevB_FlushInputFIFO((mxc_aes_revb_regs_t *)MXC_AES); +} + +void MXC_AES_FlushOutputFIFO(void) +{ + MXC_AES_RevB_FlushOutputFIFO((mxc_aes_revb_regs_t *)MXC_AES); +} + +void MXC_AES_Start(void) +{ + MXC_AES_RevB_Start((mxc_aes_revb_regs_t *)MXC_AES); +} + +uint32_t MXC_AES_GetFlags(void) +{ + return MXC_AES_RevB_GetFlags((mxc_aes_revb_regs_t *)MXC_AES); +} + +void MXC_AES_ClearFlags(uint32_t flags) +{ + MXC_AES_RevB_ClearFlags((mxc_aes_revb_regs_t *)MXC_AES, flags); +} + +int MXC_AES_Generic(mxc_aes_req_t *req) +{ + return MXC_AES_RevB_Generic((mxc_aes_revb_regs_t *)MXC_AES, (mxc_aes_revb_req_t *)req); +} + +int MXC_AES_Encrypt(mxc_aes_req_t *req) +{ + return MXC_AES_RevB_Encrypt((mxc_aes_revb_regs_t *)MXC_AES, (mxc_aes_revb_req_t *)req); +} + +int MXC_AES_Decrypt(mxc_aes_req_t *req) +{ + return MXC_AES_RevB_Decrypt((mxc_aes_revb_regs_t *)MXC_AES, (mxc_aes_revb_req_t *)req); +} + +int MXC_AES_TXDMAConfig(void *src_addr, int len) +{ + return MXC_AES_RevB_TXDMAConfig(src_addr, len); +} + +int MXC_AES_RXDMAConfig(void *dest_addr, int len) +{ + return MXC_AES_RevB_RXDMAConfig(dest_addr, len); +} + +int MXC_AES_GenericAsync(mxc_aes_req_t *req, uint8_t enc) +{ + return MXC_AES_RevB_GenericAsync((mxc_aes_revb_regs_t *)MXC_AES, (mxc_aes_revb_req_t *)req, + enc); +} + +int MXC_AES_EncryptAsync(mxc_aes_req_t *req) +{ + return MXC_AES_RevB_EncryptAsync((mxc_aes_revb_regs_t *)MXC_AES, (mxc_aes_revb_req_t *)req); +} + +int MXC_AES_DecryptAsync(mxc_aes_req_t *req) +{ + return MXC_AES_RevB_DecryptAsync((mxc_aes_revb_regs_t *)MXC_AES, (mxc_aes_revb_req_t *)req); +} + +void MXC_AES_SetExtKey(const void *key, mxc_aes_keys_t len) +{ + MXC_AES_RevB_SetExtKey((mxc_aeskeys_revb_regs_t *)MXC_AESKEYS, key, len); +} diff --git a/Libraries/PeriphDrivers/Source/CRC/crc_me30.c b/Libraries/PeriphDrivers/Source/CRC/crc_me30.c new file mode 100644 index 00000000000..cf4819eb767 --- /dev/null +++ b/Libraries/PeriphDrivers/Source/CRC/crc_me30.c @@ -0,0 +1,99 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#include "mxc_device.h" +#include "mxc_errors.h" +#include "mxc_assert.h" +#include "mxc_sys.h" + +#include "crc.h" +#include "crc_reva.h" + +/* ************************************************************************* */ +/* Global Control/Configuration functions */ +/* ************************************************************************* */ + +int MXC_CRC_Init(void) +{ +#ifndef MSDK_NO_GPIO_CLK_INIT + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_CRC); +#endif + + MXC_CRC_RevA_Init((mxc_crc_reva_regs_t *)MXC_CRC); + + return E_NO_ERROR; +} + +int MXC_CRC_Shutdown(void) +{ + int error = MXC_CRC_RevA_Shutdown((mxc_crc_reva_regs_t *)MXC_CRC); + + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_CRC); + + return error; +} + +void MXC_CRC_Handler(int ch, int error) +{ + MXC_CRC_RevA_Handler(ch, error); +} + +void MXC_CRC_SetDirection(mxc_crc_bitorder_t bitOrder) +{ + MXC_CRC_RevA_SetDirection((mxc_crc_reva_regs_t *)MXC_CRC, (mxc_crc_reva_bitorder_t)bitOrder); +} + +mxc_crc_bitorder_t MXC_CRC_GetDirection(void) +{ + return MXC_CRC_RevA_GetDirection((mxc_crc_reva_regs_t *)MXC_CRC); +} + +void MXC_CRC_SwapDataIn(mxc_crc_bitorder_t bitOrder) +{ + MXC_CRC_RevA_SwapDataIn((mxc_crc_reva_regs_t *)MXC_CRC, (mxc_crc_reva_bitorder_t)bitOrder); +} + +void MXC_CRC_SwapDataOut(mxc_crc_bitorder_t bitOrder) +{ + MXC_CRC_RevA_SwapDataOut((mxc_crc_reva_regs_t *)MXC_CRC, (mxc_crc_reva_bitorder_t)bitOrder); +} + +void MXC_CRC_SetPoly(uint32_t poly) +{ + MXC_CRC_RevA_SetPoly((mxc_crc_reva_regs_t *)MXC_CRC, poly); +} + +uint32_t MXC_CRC_GetPoly(void) +{ + return MXC_CRC_RevA_GetPoly((mxc_crc_reva_regs_t *)MXC_CRC); +} + +uint32_t MXC_CRC_GetResult(void) +{ + return MXC_CRC_RevA_GetResult((mxc_crc_reva_regs_t *)MXC_CRC); +} + +int MXC_CRC_Compute(mxc_crc_req_t *req) +{ + return MXC_CRC_RevA_Compute((mxc_crc_reva_regs_t *)MXC_CRC, (mxc_crc_reva_req_t *)req); +} + +int MXC_CRC_ComputeAsync(mxc_crc_req_t *req) +{ + return MXC_CRC_RevA_ComputeAsync((mxc_crc_reva_regs_t *)MXC_CRC, (mxc_crc_reva_req_t *)req); +} diff --git a/Libraries/PeriphDrivers/Source/DMA/dma_me30.c b/Libraries/PeriphDrivers/Source/DMA/dma_me30.c new file mode 100644 index 00000000000..a0483bd536d --- /dev/null +++ b/Libraries/PeriphDrivers/Source/DMA/dma_me30.c @@ -0,0 +1,161 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/****** Includes *******/ +#include +#include +#include "mxc_device.h" +#include "mxc_assert.h" +#include "mxc_lock.h" +#include "mxc_sys.h" +#include "dma.h" +#include "dma_reva.h" + +/***** Definitions *****/ + +/******* Globals *******/ + +/****** Functions ******/ + +int MXC_DMA_Init(void) +{ +#ifndef MSDK_NO_GPIO_CLK_INIT + if (!MXC_SYS_IsClockEnabled(MXC_SYS_PERIPH_CLOCK_DMA)) { + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_DMA); + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_DMA); + } +#endif + + return MXC_DMA_RevA_Init((mxc_dma_reva_regs_t *)MXC_DMA); +} + +void MXC_DMA_DeInit(void) +{ + return MXC_DMA_RevA_DeInit((mxc_dma_reva_regs_t *)MXC_DMA); +} + +int MXC_DMA_AcquireChannel(void) +{ + return MXC_DMA_RevA_AcquireChannel((mxc_dma_reva_regs_t *)MXC_DMA); +} + +int MXC_DMA_ReleaseChannel(int ch) +{ + return MXC_DMA_RevA_ReleaseChannel(ch); +} + +int MXC_DMA_ConfigChannel(mxc_dma_config_t config, mxc_dma_srcdst_t srcdst) +{ + return MXC_DMA_RevA_ConfigChannel(config, srcdst); +} + +int MXC_DMA_AdvConfigChannel(mxc_dma_adv_config_t advConfig) +{ + return MXC_DMA_RevA_AdvConfigChannel(advConfig); +} + +int MXC_DMA_SetSrcDst(mxc_dma_srcdst_t srcdst) +{ + return MXC_DMA_RevA_SetSrcDst(srcdst); +} + +int MXC_DMA_GetSrcDst(mxc_dma_srcdst_t *srcdst) +{ + return MXC_DMA_RevA_GetSrcDst(srcdst); +} + +int MXC_DMA_SetSrcReload(mxc_dma_srcdst_t srcdst) +{ + return MXC_DMA_RevA_SetSrcReload(srcdst); +} + +int MXC_DMA_GetSrcReload(mxc_dma_srcdst_t *srcdst) +{ + return MXC_DMA_RevA_GetSrcReload(srcdst); +} + +int MXC_DMA_SetCallback(int ch, void (*callback)(int, int)) +{ + return MXC_DMA_RevA_SetCallback(ch, callback); +} + +int MXC_DMA_SetChannelInterruptEn(int ch, bool chdis, bool ctz) +{ + return MXC_DMA_RevA_SetChannelInterruptEn(ch, chdis, ctz); +} + +int MXC_DMA_ChannelEnableInt(int ch, int flags) +{ + return MXC_DMA_RevA_ChannelEnableInt(ch, flags); +} + +int MXC_DMA_ChannelDisableInt(int ch, int flags) +{ + return MXC_DMA_RevA_ChannelDisableInt(ch, flags); +} + +int MXC_DMA_ChannelGetFlags(int ch) +{ + return MXC_DMA_RevA_ChannelGetFlags(ch); +} + +int MXC_DMA_ChannelClearFlags(int ch, int flags) +{ + return MXC_DMA_RevA_ChannelClearFlags(ch, flags); +} + +int MXC_DMA_EnableInt(int ch) +{ + return MXC_DMA_RevA_EnableInt((mxc_dma_reva_regs_t *)MXC_DMA, ch); +} + +int MXC_DMA_DisableInt(int ch) +{ + return MXC_DMA_RevA_DisableInt((mxc_dma_reva_regs_t *)MXC_DMA, ch); +} + +int MXC_DMA_Start(int ch) +{ + return MXC_DMA_RevA_Start(ch); +} + +int MXC_DMA_Stop(int ch) +{ + return MXC_DMA_RevA_Stop(ch); +} + +mxc_dma_ch_regs_t *MXC_DMA_GetCHRegs(int ch) +{ + return MXC_DMA_RevA_GetCHRegs(ch); +} + +void MXC_DMA_Handler(void) +{ + MXC_DMA_RevA_Handler((mxc_dma_reva_regs_t *)MXC_DMA); +} + +int MXC_DMA_MemCpy(void *dest, void *src, int len, mxc_dma_complete_cb_t callback) +{ + return MXC_DMA_RevA_MemCpy((mxc_dma_reva_regs_t *)MXC_DMA, dest, src, len, callback); +} + +int MXC_DMA_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, + mxc_dma_trans_chain_t callback) +{ + return MXC_DMA_RevA_DoTransfer((mxc_dma_reva_regs_t *)MXC_DMA, config, firstSrcDst, callback); +} diff --git a/Libraries/PeriphDrivers/Source/FLC/flc_me30.c b/Libraries/PeriphDrivers/Source/FLC/flc_me30.c new file mode 100644 index 00000000000..961a912434c --- /dev/null +++ b/Libraries/PeriphDrivers/Source/FLC/flc_me30.c @@ -0,0 +1,345 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* **** Includes **** */ +#include +#include "mxc_device.h" +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "flc.h" +#include "flc_reva.h" +#include "flc_common.h" +#include "mcr_regs.h" // For ECCEN registers. + +//****************************************************************************** +void MXC_FLC_ME17_Flash_Operation(void) +{ + /* + This function should be called after modifying the contents of flash memory. + It flushes the instruction caches and line fill buffer. + + It should be called _afterwards_ because after flash is modified the cache + may contain instructions that may no longer be valid. _Before_ the + flash modifications the ICC may contain relevant cached instructions related to + the incoming flash instructions (especially relevant in the case of external memory), + and these instructions will be valid up until the point that the modifications are made. + + The line fill buffer is a FLC-related buffer that also may no longer be valid. + It's flushed by reading 2 pages of flash. + */ + + /* Flush all instruction caches */ + MXC_GCR->sysctrl |= MXC_F_GCR_SYSCTRL_ICC0_FLUSH; + + /* Wait for flush to complete */ + while (MXC_GCR->sysctrl & MXC_F_GCR_SYSCTRL_ICC0_FLUSH) {} + + // Clear the line fill buffer by reading 2 pages from flash + volatile uint32_t *line_addr; + volatile uint32_t __unused line; // __unused attribute removes warning + line_addr = (uint32_t *)(MXC_FLASH_MEM_BASE); + line = *line_addr; + line_addr = (uint32_t *)(MXC_FLASH_MEM_BASE + MXC_FLASH_PAGE_SIZE); + line = *line_addr; +} + +//****************************************************************************** +int MXC_FLC_ME17_GetByAddress(mxc_flc_regs_t **flc, uint32_t addr) +{ + if ((addr >= MXC_FLASH_MEM_BASE) && (addr < (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE))) { + *flc = MXC_FLC0; + } else if ((addr >= MXC_INFO_MEM_BASE) && (addr < (MXC_INFO_MEM_BASE + MXC_INFO_MEM_SIZE))) { + *flc = MXC_FLC0; + } else { + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +//****************************************************************************** +int MXC_FLC_ME17_GetPhysicalAddress(uint32_t addr, uint32_t *result) +{ + if ((addr >= MXC_FLASH_MEM_BASE) && (addr < (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE))) { + *result = addr & (MXC_FLASH_MEM_SIZE - 1); + } else if ((addr >= MXC_INFO_MEM_BASE) && (addr < (MXC_INFO_MEM_BASE + MXC_INFO_MEM_SIZE))) { + *result = (addr & (MXC_INFO_MEM_SIZE - 1)) + MXC_FLASH_MEM_SIZE; + } else { + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +//****************************************************************************** +int MXC_FLC_Init(void) +{ + return E_NO_ERROR; +} + +//****************************************************************************** +#if IAR_PRAGMAS +#pragma section = ".flashprog" +#else +__attribute__((section(".flashprog"))) +#endif +int MXC_FLC_Busy(void) +{ + return MXC_FLC_RevA_Busy(); +} + +//****************************************************************************** +#if IAR_PRAGMAS +#pragma section = ".flashprog" +#else +__attribute__((section(".flashprog"))) +#endif +int MXC_FLC_PageErase(uint32_t address) +{ + int err; + uint32_t addr; + mxc_flc_regs_t *flc = NULL; + + // Get FLC Instance + if ((err = MXC_FLC_ME17_GetByAddress(&flc, address)) != E_NO_ERROR) { + return err; + } + + if ((err = MXC_FLC_ME17_GetPhysicalAddress(address, &addr)) < E_NO_ERROR) { + return err; + } + + err = MXC_FLC_RevA_PageErase((mxc_flc_reva_regs_t *)flc, addr); + + // Flush the cache + MXC_FLC_ME17_Flash_Operation(); + + return err; +} + +//****************************************************************************** +#if IAR_PRAGMAS +#pragma section = ".flashprog" +#else +__attribute__((section(".flashprog"))) +#endif +// make sure to disable ICC with ICC_Disable(); before Running this function +int MXC_FLC_Write128(uint32_t address, uint32_t *data) +{ + int err; + mxc_flc_regs_t *flc = NULL; + uint32_t addr; + + // Address checked if it is 128-bit aligned + if (address & 0xF) { + return E_BAD_PARAM; + } + + // Get FLC Instance + if ((err = MXC_FLC_ME17_GetByAddress(&flc, address)) != E_NO_ERROR) { + return err; + } + + if ((err = MXC_FLC_ME17_GetPhysicalAddress(address, &addr)) < E_NO_ERROR) { + return err; + } + + err = MXC_FLC_RevA_Write128((mxc_flc_reva_regs_t *)flc, addr, data); + + // Flush the cache + MXC_FLC_ME17_Flash_Operation(); + + return err; +} + +//****************************************************************************** +int MXC_FLC_Write32(uint32_t address, uint32_t data) +{ + uint32_t addr, aligned; + int err; + mxc_flc_regs_t *flc = NULL; + + // Address checked if it is byte addressable + if (address & 0x3) { + return E_BAD_PARAM; + } + + // Align address to 128-bit word + aligned = address & 0xfffffff0; + + // Get FLC Instance + if ((err = MXC_FLC_ME17_GetByAddress(&flc, address)) != E_NO_ERROR) { + return err; + } + + if ((err = MXC_FLC_ME17_GetPhysicalAddress(aligned, &addr)) < E_NO_ERROR) { + return err; + } + + err = MXC_FLC_RevA_Write32Using128((mxc_flc_reva_regs_t *)flc, address, data, addr); + + // Flush the cache + MXC_FLC_ME17_Flash_Operation(); + + return err; +} + +//****************************************************************************** +int MXC_FLC_MassErase(void) +{ + int err, i; + mxc_flc_regs_t *flc; + + for (i = 0; i < MXC_FLC_INSTANCES; i++) { + flc = MXC_FLC_GET_FLC(i); + + err = MXC_FLC_RevA_MassErase((mxc_flc_reva_regs_t *)flc); + + // Flush the cache + MXC_FLC_ME17_Flash_Operation(); + + if (err != E_NO_ERROR) { + return err; + } + } + + return E_NO_ERROR; +} + +//****************************************************************************** +int MXC_FLC_UnlockInfoBlock(uint32_t address) +{ + int err; + mxc_flc_regs_t *flc; + + if ((err = MXC_FLC_ME17_GetByAddress(&flc, address)) != E_NO_ERROR) { + return err; + } + + return MXC_FLC_RevA_UnlockInfoBlock((mxc_flc_reva_regs_t *)flc, address); +} + +//****************************************************************************** +int MXC_FLC_LockInfoBlock(uint32_t address) +{ + int err; + mxc_flc_regs_t *flc; + + if ((err = MXC_FLC_ME17_GetByAddress(&flc, address)) != E_NO_ERROR) { + return err; + } + + return MXC_FLC_RevA_LockInfoBlock((mxc_flc_reva_regs_t *)flc, address); +} + +//****************************************************************************** +int MXC_FLC_Write(uint32_t address, uint32_t length, uint32_t *buffer) +{ + return MXC_FLC_Com_Write(address, length, buffer); +} + +//****************************************************************************** +void MXC_FLC_Read(int address, void *buffer, int len) +{ + MXC_FLC_Com_Read(address, buffer, len); +} + +//****************************************************************************** +int MXC_FLC_EnableInt(uint32_t flags) +{ + return MXC_FLC_RevA_EnableInt(flags); +} + +//****************************************************************************** +int MXC_FLC_DisableInt(uint32_t flags) +{ + return MXC_FLC_RevA_DisableInt(flags); +} + +//****************************************************************************** +int MXC_FLC_GetFlags(void) +{ + return MXC_FLC_RevA_GetFlags(); +} + +//****************************************************************************** +int MXC_FLC_ClearFlags(uint32_t flags) +{ + return MXC_FLC_RevA_ClearFlags(flags); +} + +//****************************************************************************** +int MXC_FLC_BlockPageWrite(uint32_t address) +{ + if (address < MXC_FLASH_MEM_BASE || address > (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE)) { + return E_INVALID; + } + + return MXC_FLC_RevA_BlockPageWrite(address, MXC_FLASH_MEM_BASE); +} + +//****************************************************************************** +int MXC_FLC_BlockPageRead(uint32_t address) +{ + if (address < MXC_FLASH_MEM_BASE || address > (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE)) { + return E_INVALID; + } + + return MXC_FLC_RevA_BlockPageRead(address, MXC_FLASH_MEM_BASE); +} + +//****************************************************************************** +volatile uint32_t *MXC_FLC_GetWELR(uint32_t address, uint32_t page_num) +{ + uint32_t reg_num; + reg_num = page_num >> + 5; // Divide by 32 to get WELR register number containing the page lock bit + + if (address < MXC_FLASH_MEM_BASE || address > (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE)) { + return NULL; + } + + switch (reg_num) { + case 0: + return &(MXC_FLC->welr0); + case 1: + return &(MXC_FLC->welr1); + } + + return NULL; +} + +//****************************************************************************** +volatile uint32_t *MXC_FLC_GetRLR(uint32_t address, uint32_t page_num) +{ + uint32_t reg_num; + reg_num = page_num >> 5; // Divide by 32 to get RLR register number containing the page lock bit + + if (address < MXC_FLASH_MEM_BASE || address > (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE)) { + return NULL; + } + + switch (reg_num) { + case 0: + return &(MXC_FLC->rlr0); + case 1: + return &(MXC_FLC->rlr1); + } + + return NULL; +} diff --git a/Libraries/PeriphDrivers/Source/GPIO/gpio_me30.c b/Libraries/PeriphDrivers/Source/GPIO/gpio_me30.c new file mode 100644 index 00000000000..5b3312315d7 --- /dev/null +++ b/Libraries/PeriphDrivers/Source/GPIO/gpio_me30.c @@ -0,0 +1,430 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* **** Includes **** */ +#include +#include "mxc_device.h" +#include "mxc_assert.h" +#include "gpio.h" +#include "gpio_reva.h" +#include "gpio_common.h" +#include "mxc_sys.h" +#include "lpgcr_regs.h" +#include "mcr_regs.h" +#include "pwrseq_regs.h" + +/* **** Definitions **** */ +// Pin 3.0 Definitions +#define P30_DATA_OUT(pin_mask) ((pin_mask & (1 << 0)) == (1 << 0) ? MXC_F_MCR_GPIO3_CTRL_P30_DO : 0) +#define P30_OUT_EN(pin_mask) ((pin_mask & (1 << 0)) == (1 << 0) ? MXC_F_MCR_GPIO3_CTRL_P30_OE : 0) +#define P30_PULL_DIS(pin_mask) ((pin_mask & (1 << 0)) == (1 << 0) ? MXC_F_MCR_GPIO3_CTRL_P30_PE : 0) +#define P30_DATA_IN(pin_mask) ((pin_mask & (1 << 0)) == (1 << 0) ? MXC_F_MCR_GPIO3_CTRL_P30_IN : 0) +#define PDOWN_OUT_EN(pin_mask) \ + ((pin_mask & (1 << 0)) == (1 << 0) ? MXC_F_MCR_OUTEN_PDOWN_OUT_EN : 0) + +// Pin 3.1 Definitions +#define P31_DATA_OUT(pin_mask) ((pin_mask & (1 << 1)) == (1 << 1) ? MXC_F_MCR_GPIO3_CTRL_P31_DO : 0) +#define P31_OUT_EN(pin_mask) ((pin_mask & (1 << 1)) == (1 << 1) ? MXC_F_MCR_GPIO3_CTRL_P31_OE : 0) +#define P31_PULL_DIS(pin_mask) ((pin_mask & (1 << 1)) == (1 << 1) ? MXC_F_MCR_GPIO3_CTRL_P31_PE : 0) +#define P31_DATA_IN(pin_mask) ((pin_mask & (1 << 1)) == (1 << 1) ? MXC_F_MCR_GPIO3_CTRL_P31_IN : 0) +#define SQWAVE_OUT_EN(pin_mask) ((pin_mask & (1 << 1)) == (1 << 1) ? MXC_F_MCR_OUTEN_SQWOUT_EN : 0) + +/* **** Globals **** */ + +/* **** Functions **** */ +int MXC_GPIO_Init(uint32_t portmask) +{ + if (portmask & 0x1) { + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO0); + } + + if (portmask & 0x2) { + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO1); + } + + if (portmask & 0x4) { + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO2); + } + + return MXC_GPIO_Common_Init(portmask); +} + +int MXC_GPIO_Shutdown(uint32_t portmask) +{ + if (portmask & 0x1) { + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_GPIO0); + } + + if (portmask & 0x2) { + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_GPIO1); + } + + if (portmask & 0x4) { + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_GPIO2); + } + + return E_NO_ERROR; +} + +int MXC_GPIO_Reset(uint32_t portmask) +{ + if (portmask & 0x1) { + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_GPIO0); + } + + if (portmask & 0x2) { + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_GPIO1); + } + + if (portmask & 0x4) { + MXC_SYS_Reset_Periph(MXC_SYS_RESET_GPIO2); + } + + return E_NO_ERROR; +} + +int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) +{ + int port, error; + mxc_gpio_regs_t *gpio = cfg->port; + + port = MXC_GPIO_GET_IDX(cfg->port); + + MXC_GPIO_Init(1 << port); + + if (MXC_GPIO_GetConfigLock() == MXC_GPIO_CONFIG_LOCKED) { + // Configuration is locked. Ignore any attempts to change it. + return E_NO_ERROR; + } + + // Configure the vssel + error = MXC_GPIO_SetVSSEL(gpio, cfg->vssel, cfg->mask); + if (error != E_NO_ERROR) { + return error; + } + + if (cfg->port == MXC_GPIO3) { + switch (cfg->func) { + case MXC_GPIO_FUNC_IN: + MXC_MCR->gpio3_ctrl &= ~(P30_OUT_EN(cfg->mask) | P31_OUT_EN(cfg->mask)); + MXC_MCR->outen &= ~(SQWAVE_OUT_EN(cfg->mask) | PDOWN_OUT_EN(cfg->mask)); + break; + + case MXC_GPIO_FUNC_OUT: + MXC_MCR->gpio3_ctrl |= P30_OUT_EN(cfg->mask) | P31_OUT_EN(cfg->mask); + MXC_MCR->outen &= ~(SQWAVE_OUT_EN(cfg->mask) | PDOWN_OUT_EN(cfg->mask)); + break; + + case MXC_GPIO_FUNC_ALT1: + MXC_MCR->gpio3_ctrl |= P30_OUT_EN(cfg->mask) | P31_OUT_EN(cfg->mask); + MXC_MCR->outen |= SQWAVE_OUT_EN(cfg->mask) | PDOWN_OUT_EN(cfg->mask); + break; + + default: + return E_NOT_SUPPORTED; + } + + switch (cfg->pad) { + case MXC_GPIO_PAD_NONE: + MXC_MCR->gpio3_ctrl |= P30_PULL_DIS(cfg->mask) | P31_PULL_DIS(cfg->mask); + break; + + case MXC_GPIO_PAD_PULL_UP: + case MXC_GPIO_PAD_WEAK_PULL_UP: + MXC_MCR->gpio3_ctrl |= P30_DATA_OUT(cfg->mask) | P31_DATA_OUT(cfg->mask); + MXC_MCR->gpio3_ctrl &= ~(P30_PULL_DIS(cfg->mask) | P31_PULL_DIS(cfg->mask)); + break; + + case MXC_GPIO_PAD_PULL_DOWN: + case MXC_GPIO_PAD_WEAK_PULL_DOWN: + MXC_MCR->gpio3_ctrl &= ~(P30_DATA_OUT(cfg->mask) | P31_DATA_OUT(cfg->mask)); + MXC_MCR->gpio3_ctrl &= ~(P30_PULL_DIS(cfg->mask) | P31_PULL_DIS(cfg->mask)); + break; + + default: + return E_NOT_SUPPORTED; + } + } else { + // Configure alternate function + error = MXC_GPIO_RevA_SetAF((mxc_gpio_reva_regs_t *)gpio, cfg->func, cfg->mask); + if (error != E_NO_ERROR) { + return error; + } + + // Configure the pad + switch (cfg->pad) { + case MXC_GPIO_PAD_NONE: + gpio->padctrl0 &= ~cfg->mask; + gpio->padctrl1 &= ~cfg->mask; + break; + + case MXC_GPIO_PAD_WEAK_PULL_UP: + gpio->padctrl0 |= cfg->mask; + gpio->padctrl1 &= ~cfg->mask; + gpio->ps &= ~cfg->mask; + break; + + case MXC_GPIO_PAD_PULL_UP: + gpio->padctrl0 |= cfg->mask; + gpio->padctrl1 &= ~cfg->mask; + gpio->ps |= cfg->mask; + break; + + case MXC_GPIO_PAD_WEAK_PULL_DOWN: + gpio->padctrl0 &= ~cfg->mask; + gpio->padctrl1 |= cfg->mask; + gpio->ps &= ~cfg->mask; + break; + + case MXC_GPIO_PAD_PULL_DOWN: + gpio->padctrl0 &= ~cfg->mask; + gpio->padctrl1 |= cfg->mask; + gpio->ps |= cfg->mask; + break; + + default: + return E_BAD_PARAM; + } + } + + // Configure the drive strength + if (cfg->func == MXC_GPIO_FUNC_IN) { + return E_NO_ERROR; + } else { + return MXC_GPIO_SetDriveStrength(gpio, cfg->drvstr, cfg->mask); + } +} + +/* ************************************************************************** */ +uint32_t MXC_GPIO_InGet(mxc_gpio_regs_t *port, uint32_t mask) +{ + uint32_t in = 0; + + if (port == MXC_GPIO3) { + if (MXC_MCR->gpio3_ctrl & P30_DATA_IN(mask)) { + in |= MXC_GPIO_PIN_0; + } + + if (MXC_MCR->gpio3_ctrl & P31_DATA_IN(mask)) { + in |= MXC_GPIO_PIN_1; + } + + return in; + } + + return MXC_GPIO_RevA_InGet((mxc_gpio_reva_regs_t *)port, mask); +} + +/* ************************************************************************** */ +void MXC_GPIO_OutSet(mxc_gpio_regs_t *port, uint32_t mask) +{ + if (port == MXC_GPIO3) { + MXC_MCR->gpio3_ctrl |= P30_DATA_OUT(mask) | P31_DATA_OUT(mask); + return; + } + + MXC_GPIO_RevA_OutSet((mxc_gpio_reva_regs_t *)port, mask); +} + +/* ************************************************************************** */ +void MXC_GPIO_OutClr(mxc_gpio_regs_t *port, uint32_t mask) +{ + if (port == MXC_GPIO3) { + MXC_MCR->gpio3_ctrl &= ~(P30_DATA_OUT(mask) | P31_DATA_OUT(mask)); + return; + } + + MXC_GPIO_RevA_OutClr((mxc_gpio_reva_regs_t *)port, mask); +} + +/* ************************************************************************** */ +uint32_t MXC_GPIO_OutGet(mxc_gpio_regs_t *port, uint32_t mask) +{ + uint32_t out = 0; + + if (port == MXC_GPIO3) { + if (MXC_MCR->gpio3_ctrl & P30_DATA_OUT(mask)) { + out |= MXC_GPIO_PIN_0; + } + + if (MXC_MCR->gpio3_ctrl & P31_DATA_OUT(mask)) { + out |= MXC_GPIO_PIN_1; + } + + return out; + } + + return MXC_GPIO_RevA_OutGet((mxc_gpio_reva_regs_t *)port, mask); +} + +/* ************************************************************************** */ +void MXC_GPIO_OutPut(mxc_gpio_regs_t *port, uint32_t mask, uint32_t val) +{ + if (port == MXC_GPIO3) { + uint32_t gpio3_cp = MXC_MCR->gpio3_ctrl & ~(P30_DATA_OUT(mask) | P31_DATA_OUT(mask)); + + MXC_MCR->gpio3_ctrl = gpio3_cp | P30_DATA_OUT((mask & val)) | P31_DATA_OUT((mask & val)); + return; + } + + MXC_GPIO_RevA_OutPut((mxc_gpio_reva_regs_t *)port, mask, val); +} + +/* ************************************************************************** */ +void MXC_GPIO_OutToggle(mxc_gpio_regs_t *port, uint32_t mask) +{ + if (port == MXC_GPIO3) { + MXC_MCR->gpio3_ctrl ^= P30_DATA_OUT(mask) | P31_DATA_OUT(mask); + return; + } + + MXC_GPIO_RevA_OutToggle((mxc_gpio_reva_regs_t *)port, mask); +} + +/* ************************************************************************** */ +int MXC_GPIO_IntConfig(const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol) +{ + if (cfg->port == MXC_GPIO3) { + if (pol != MXC_GPIO_INT_BOTH) { + return E_NOT_SUPPORTED; + } + + return E_NO_ERROR; + } + + return MXC_GPIO_RevA_IntConfig(cfg, pol); +} + +/* ************************************************************************** */ +void MXC_GPIO_EnableInt(mxc_gpio_regs_t *port, uint32_t mask) +{ + if (port == MXC_GPIO3) { + MXC_PWRSEQ->lpwken3 |= mask; + return; + } + + MXC_GPIO_RevA_EnableInt((mxc_gpio_reva_regs_t *)port, mask); +} + +/* ************************************************************************** */ +void MXC_GPIO_DisableInt(mxc_gpio_regs_t *port, uint32_t mask) +{ + if (port == MXC_GPIO3) { + MXC_PWRSEQ->lpwken3 &= ~mask; + return; + } + + MXC_GPIO_RevA_DisableInt((mxc_gpio_reva_regs_t *)port, mask); +} + +/* ************************************************************************** */ +void MXC_GPIO_RegisterCallback(const mxc_gpio_cfg_t *cfg, mxc_gpio_callback_fn func, void *cbdata) +{ + MXC_GPIO_Common_RegisterCallback(cfg, func, cbdata); +} + +/* ************************************************************************** */ +void MXC_GPIO_Handler(unsigned int port) +{ + MXC_GPIO_Common_Handler(port); +} + +/* ************************************************************************** */ +void MXC_GPIO_ClearFlags(mxc_gpio_regs_t *port, uint32_t flags) +{ + if (port == MXC_GPIO3) { + MXC_PWRSEQ->lpwkst3 = flags; + return; + } + + MXC_GPIO_RevA_ClearFlags((mxc_gpio_reva_regs_t *)port, flags); +} + +/* ************************************************************************** */ +uint32_t MXC_GPIO_GetFlags(mxc_gpio_regs_t *port) +{ + if (port == MXC_GPIO3) { + return MXC_PWRSEQ->lpwkst3; + } + + return MXC_GPIO_RevA_GetFlags((mxc_gpio_reva_regs_t *)port); +} + +/* ************************************************************************** */ +int MXC_GPIO_SetVSSEL(mxc_gpio_regs_t *port, mxc_gpio_vssel_t vssel, uint32_t mask) +{ + if (port == MXC_GPIO3) { + if (vssel == MXC_GPIO_VSSEL_VDDIO) { + return E_NOT_SUPPORTED; + } + + return E_NO_ERROR; + } + + return MXC_GPIO_RevA_SetVSSEL((mxc_gpio_reva_regs_t *)port, vssel, mask); +} + +/* ************************************************************************** */ +void MXC_GPIO_SetWakeEn(mxc_gpio_regs_t *port, uint32_t mask) +{ + if (port == MXC_GPIO3) { + MXC_PWRSEQ->lpwken3 |= mask; + return; + } + + MXC_GPIO_RevA_SetWakeEn((mxc_gpio_reva_regs_t *)port, mask); +} + +/* ************************************************************************** */ +void MXC_GPIO_ClearWakeEn(mxc_gpio_regs_t *port, uint32_t mask) +{ + if (port == MXC_GPIO3) { + MXC_PWRSEQ->lpwken3 &= ~mask; + return; + } + + MXC_GPIO_RevA_ClearWakeEn((mxc_gpio_reva_regs_t *)port, mask); +} + +/* ************************************************************************** */ +uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port) +{ + if (port == MXC_GPIO3) { + return MXC_PWRSEQ->lpwken3; + } + + return MXC_GPIO_RevA_GetWakeEn((mxc_gpio_reva_regs_t *)port); +} + +/* ************************************************************************** */ +int MXC_GPIO_SetDriveStrength(mxc_gpio_regs_t *port, mxc_gpio_drvstr_t drvstr, uint32_t mask) +{ + return MXC_GPIO_RevA_SetDriveStrength((mxc_gpio_reva_regs_t *)port, drvstr, mask); +} + +/* ************************************************************************** */ +void MXC_GPIO_SetConfigLock(mxc_gpio_config_lock_t locked) +{ + MXC_GPIO_Common_SetConfigLock(locked); +} + +/* ************************************************************************** */ +mxc_gpio_config_lock_t MXC_GPIO_GetConfigLock(void) +{ + return MXC_GPIO_Common_GetConfigLock(); +} diff --git a/Libraries/PeriphDrivers/Source/I2C/i2c_me30.c b/Libraries/PeriphDrivers/Source/I2C/i2c_me30.c new file mode 100644 index 00000000000..dacc6e77d78 --- /dev/null +++ b/Libraries/PeriphDrivers/Source/I2C/i2c_me30.c @@ -0,0 +1,413 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#include +#include +#include +#include "mxc_device.h" +#include "mxc_assert.h" +#include "mxc_lock.h" +#include "mxc_sys.h" +#include "mxc_delay.h" +#include "i2c_regs.h" +#include "dma_regs.h" +#include "i2c.h" +#include "i2c_reva.h" + +/* **** Variable Declaration **** */ +uint32_t interruptCheck = MXC_F_I2C_INTFL0_ADDR_MATCH | MXC_F_I2C_INTFL0_DNR_ERR; + +/* **** Function Prototypes **** */ + +/* ************************************************************************* */ +/* Control/Configuration functions */ +/* ************************************************************************* */ +int MXC_I2C_Init(mxc_i2c_regs_t *i2c, int masterMode, unsigned int slaveAddr) +{ + if (i2c == NULL) { + return E_NULL_PTR; + } + +#ifndef MSDK_NO_GPIO_CLK_INIT + MXC_I2C_Shutdown(i2c); // Clear everything out + + if (i2c == MXC_I2C0) { + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C0); + MXC_GPIO_Config(&gpio_cfg_i2c0); + } else if (i2c == MXC_I2C1) { + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C1); + MXC_GPIO_Config(&gpio_cfg_i2c1); + } else if (i2c == MXC_I2C2) { + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_I2C2); + MXC_GPIO_Config(&gpio_cfg_i2c2); + } else { + return E_NO_DEVICE; + } +#endif // MSDK_NO_GPIO_CLK_INIT + + return MXC_I2C_RevA_Init((mxc_i2c_reva_regs_t *)i2c, masterMode, slaveAddr); +} + +int MXC_I2C_SetSlaveAddr(mxc_i2c_regs_t *i2c, unsigned int slaveAddr, int idx) +{ + if (idx != 0) { + // MAX32655 only supports one slave device + return E_NOT_SUPPORTED; + } + + return MXC_I2C_RevA_SetSlaveAddr((mxc_i2c_reva_regs_t *)i2c, slaveAddr, idx); +} + +int MXC_I2C_Shutdown(mxc_i2c_regs_t *i2c) +{ + // Configure GPIO for I2C + if (i2c == MXC_I2C0) { + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C0); + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_I2C0); + } else if (i2c == MXC_I2C1) { + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C1); + MXC_SYS_Reset_Periph(MXC_SYS_RESET1_I2C1); + } else if (i2c == MXC_I2C2) { + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_I2C2); + MXC_SYS_Reset_Periph(MXC_SYS_RESET1_I2C2); + } else { + return E_NO_DEVICE; + } + + return MXC_I2C_RevA_Shutdown((mxc_i2c_reva_regs_t *)i2c); +} + +int MXC_I2C_Reset(mxc_i2c_regs_t *i2c) +{ + // Configure GPIO for I2C + if (i2c == MXC_I2C0) { + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_I2C0); + } else if (i2c == MXC_I2C1) { + MXC_SYS_Reset_Periph(MXC_SYS_RESET1_I2C1); + } else if (i2c == MXC_I2C2) { + MXC_SYS_Reset_Periph(MXC_SYS_RESET1_I2C2); + } else { + return E_NO_DEVICE; + } + + return E_NO_ERROR; +} + +int MXC_I2C_SetFrequency(mxc_i2c_regs_t *i2c, unsigned int hz) +{ + return MXC_I2C_RevA_SetFrequency((mxc_i2c_reva_regs_t *)i2c, hz); +} + +int MXC_I2C_GetFrequency(mxc_i2c_regs_t *i2c) +{ + return MXC_I2C_RevA_GetFrequency((mxc_i2c_reva_regs_t *)i2c); +} + +int MXC_I2C_ReadyForSleep(mxc_i2c_regs_t *i2c) +{ + return MXC_I2C_RevA_ReadyForSleep((mxc_i2c_reva_regs_t *)i2c); +} + +int MXC_I2C_SetClockStretching(mxc_i2c_regs_t *i2c, int enable) +{ + return MXC_I2C_RevA_SetClockStretching((mxc_i2c_reva_regs_t *)i2c, enable); +} + +int MXC_I2C_GetClockStretching(mxc_i2c_regs_t *i2c) +{ + return MXC_I2C_RevA_GetClockStretching((mxc_i2c_reva_regs_t *)i2c); +} + +int MXC_I2C_DMA_Init(mxc_i2c_regs_t *i2c, mxc_dma_regs_t *dma, bool use_dma_tx, bool use_dma_rx) +{ + return MXC_I2C_RevA_DMA_Init((mxc_i2c_reva_regs_t *)i2c, (mxc_dma_reva_regs_t *)dma, use_dma_tx, + use_dma_rx); +} + +int MXC_I2C_DMA_GetTXChannel(mxc_i2c_regs_t *i2c) +{ + return MXC_I2C_RevA_DMA_GetTXChannel((mxc_i2c_reva_regs_t *)i2c); +} + +int MXC_I2C_DMA_GetRXChannel(mxc_i2c_regs_t *i2c) +{ + return MXC_I2C_RevA_DMA_GetRXChannel((mxc_i2c_reva_regs_t *)i2c); +} + +int MXC_I2C_DMA_SetRequestSelect(mxc_i2c_regs_t *i2c, uint8_t *txData, uint8_t *rxData) +{ + int i2cNum; + int txReqSel = -1; + int rxReqSel = -1; + + if (i2c == NULL) { + return E_NULL_PTR; + } + + i2cNum = MXC_I2C_GET_IDX((mxc_i2c_regs_t *)i2c); + + if (txData != NULL) { + switch (i2cNum) { + case 0: + txReqSel = MXC_DMA_REQUEST_I2C0TX; + break; + + case 1: + txReqSel = MXC_DMA_REQUEST_I2C1TX; + break; + + case 2: + txReqSel = MXC_DMA_REQUEST_I2C2TX; + break; + + default: + return E_BAD_PARAM; + } + } + + if (rxData != NULL) { + switch (i2cNum) { + case 0: + rxReqSel = MXC_DMA_REQUEST_I2C0RX; + break; + + case 1: + rxReqSel = MXC_DMA_REQUEST_I2C1RX; + break; + + case 2: + rxReqSel = MXC_DMA_REQUEST_I2C2RX; + break; + + default: + return E_BAD_PARAM; + } + } + + return MXC_I2C_RevA_DMA_SetRequestSelect((mxc_i2c_reva_regs_t *)i2c, + (mxc_dma_reva_regs_t *)MXC_DMA, txReqSel, rxReqSel); +} + +/* ************************************************************************* */ +/* Low-level functions */ +/* ************************************************************************* */ +int MXC_I2C_Start(mxc_i2c_regs_t *i2c) +{ + return MXC_I2C_RevA_Start((mxc_i2c_reva_regs_t *)i2c); +} + +int MXC_I2C_Stop(mxc_i2c_regs_t *i2c) +{ + return MXC_I2C_RevA_Stop((mxc_i2c_reva_regs_t *)i2c); +} + +int MXC_I2C_WriteByte(mxc_i2c_regs_t *i2c, unsigned char byte) +{ + return MXC_I2C_RevA_WriteByte((mxc_i2c_reva_regs_t *)i2c, byte); +} + +int MXC_I2C_ReadByte(mxc_i2c_regs_t *i2c, unsigned char *byte, int ack) +{ + return MXC_I2C_RevA_ReadByte((mxc_i2c_reva_regs_t *)i2c, byte, ack); +} + +int MXC_I2C_ReadByteInteractive(mxc_i2c_regs_t *i2c, unsigned char *byte, mxc_i2c_getAck_t getAck) +{ + return MXC_I2C_RevA_ReadByteInteractive((mxc_i2c_reva_regs_t *)i2c, byte, + (mxc_i2c_reva_getAck_t)getAck); +} + +int MXC_I2C_Write(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int *len) +{ + return MXC_I2C_RevA_Write((mxc_i2c_reva_regs_t *)i2c, bytes, len); +} + +int MXC_I2C_Read(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int *len, int ack) +{ + return MXC_I2C_RevA_Read((mxc_i2c_reva_regs_t *)i2c, bytes, len, ack); +} + +int MXC_I2C_ReadRXFIFO(mxc_i2c_regs_t *i2c, volatile unsigned char *bytes, unsigned int len) +{ + return MXC_I2C_RevA_ReadRXFIFO((mxc_i2c_reva_regs_t *)i2c, bytes, len); +} + +int MXC_I2C_ReadRXFIFODMA(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int len, + mxc_i2c_dma_complete_cb_t callback) +{ + // The callback parameter was previously unused but keeping it for backwards-compatibility. + return MXC_I2C_RevA_ReadRXFIFODMA((mxc_i2c_reva_regs_t *)i2c, bytes, len, MXC_DMA); +} + +int MXC_I2C_GetRXFIFOAvailable(mxc_i2c_regs_t *i2c) +{ + return MXC_I2C_RevA_GetRXFIFOAvailable((mxc_i2c_reva_regs_t *)i2c); +} + +int MXC_I2C_WriteTXFIFO(mxc_i2c_regs_t *i2c, volatile unsigned char *bytes, unsigned int len) +{ + return MXC_I2C_RevA_WriteTXFIFO((mxc_i2c_reva_regs_t *)i2c, bytes, len); +} + +int MXC_I2C_WriteTXFIFODMA(mxc_i2c_regs_t *i2c, unsigned char *bytes, unsigned int len, + mxc_i2c_dma_complete_cb_t callback) +{ + // The callback parameter was previously unused but keeping it for backwards-compatibility. + return MXC_I2C_RevA_WriteTXFIFODMA((mxc_i2c_reva_regs_t *)i2c, bytes, len, MXC_DMA); +} + +int MXC_I2C_GetTXFIFOAvailable(mxc_i2c_regs_t *i2c) +{ + return MXC_I2C_RevA_GetTXFIFOAvailable((mxc_i2c_reva_regs_t *)i2c); +} + +void MXC_I2C_ClearRXFIFO(mxc_i2c_regs_t *i2c) +{ + MXC_I2C_RevA_ClearRXFIFO((mxc_i2c_reva_regs_t *)i2c); +} + +void MXC_I2C_ClearTXFIFO(mxc_i2c_regs_t *i2c) +{ + MXC_I2C_RevA_ClearTXFIFO((mxc_i2c_reva_regs_t *)i2c); +} + +int MXC_I2C_GetFlags(mxc_i2c_regs_t *i2c, unsigned int *flags0, unsigned int *flags1) +{ + return MXC_I2C_RevA_GetFlags((mxc_i2c_reva_regs_t *)i2c, flags0, flags1); +} + +void MXC_I2C_ClearFlags(mxc_i2c_regs_t *i2c, unsigned int flags0, unsigned int flags1) +{ + MXC_I2C_RevA_ClearFlags((mxc_i2c_reva_regs_t *)i2c, flags0, flags1); +} + +void MXC_I2C_EnableInt(mxc_i2c_regs_t *i2c, unsigned int flags0, unsigned int flags1) +{ + MXC_I2C_RevA_EnableInt((mxc_i2c_reva_regs_t *)i2c, flags0, flags1); +} + +void MXC_I2C_DisableInt(mxc_i2c_regs_t *i2c, unsigned int flags0, unsigned int flags1) +{ + MXC_I2C_RevA_DisableInt((mxc_i2c_reva_regs_t *)i2c, flags0, flags1); +} + +void MXC_I2C_EnablePreload(mxc_i2c_regs_t *i2c) +{ + MXC_I2C_RevA_EnablePreload((mxc_i2c_reva_regs_t *)i2c); +} + +void MXC_I2C_DisablePreload(mxc_i2c_regs_t *i2c) +{ + MXC_I2C_RevA_DisablePreload((mxc_i2c_reva_regs_t *)i2c); +} + +void MXC_I2C_EnableGeneralCall(mxc_i2c_regs_t *i2c) +{ + MXC_I2C_RevA_EnableGeneralCall((mxc_i2c_reva_regs_t *)i2c); +} + +void MXC_I2C_DisableGeneralCall(mxc_i2c_regs_t *i2c) +{ + MXC_I2C_RevA_DisableGeneralCall((mxc_i2c_reva_regs_t *)i2c); +} + +void MXC_I2C_SetTimeout(mxc_i2c_regs_t *i2c, unsigned int timeout) +{ + MXC_I2C_RevA_SetTimeout((mxc_i2c_reva_regs_t *)i2c, timeout); +} + +unsigned int MXC_I2C_GetTimeout(mxc_i2c_regs_t *i2c) +{ + return MXC_I2C_RevA_GetTimeout((mxc_i2c_reva_regs_t *)i2c); +} + +int MXC_I2C_Recover(mxc_i2c_regs_t *i2c, unsigned int retries) +{ + return MXC_I2C_RevA_Recover((mxc_i2c_reva_regs_t *)i2c, retries); +} + +/* ************************************************************************* */ +/* Transaction level functions */ +/* ************************************************************************* */ + +int MXC_I2C_MasterTransaction(mxc_i2c_req_t *req) +{ + return MXC_I2C_RevA_MasterTransaction((mxc_i2c_reva_req_t *)req); +} + +int MXC_I2C_MasterTransactionAsync(mxc_i2c_req_t *req) +{ + return MXC_I2C_RevA_MasterTransactionAsync((mxc_i2c_reva_req_t *)req); +} + +int MXC_I2C_MasterTransactionDMA(mxc_i2c_req_t *req) +{ + return MXC_I2C_RevA_MasterTransactionDMA((mxc_i2c_reva_req_t *)req, MXC_DMA); +} + +int MXC_I2C_SlaveTransaction(mxc_i2c_regs_t *i2c, mxc_i2c_slave_handler_t callback) +{ + return MXC_I2C_RevA_SlaveTransaction((mxc_i2c_reva_regs_t *)i2c, + (mxc_i2c_reva_slave_handler_t)callback, interruptCheck); +} + +int MXC_I2C_SlaveTransactionAsync(mxc_i2c_regs_t *i2c, mxc_i2c_slave_handler_t callback) +{ + return MXC_I2C_RevA_SlaveTransactionAsync( + (mxc_i2c_reva_regs_t *)i2c, (mxc_i2c_reva_slave_handler_t)callback, interruptCheck); +} + +int MXC_I2C_SetRXThreshold(mxc_i2c_regs_t *i2c, unsigned int numBytes) +{ + return MXC_I2C_RevA_SetRXThreshold((mxc_i2c_reva_regs_t *)i2c, numBytes); +} + +int MXC_I2C_GetRXThreshold(mxc_i2c_regs_t *i2c) +{ + return MXC_I2C_RevA_GetRXThreshold((mxc_i2c_reva_regs_t *)i2c); +} + +int MXC_I2C_SetTXThreshold(mxc_i2c_regs_t *i2c, unsigned int numBytes) +{ + return MXC_I2C_RevA_SetTXThreshold((mxc_i2c_reva_regs_t *)i2c, numBytes); +} + +int MXC_I2C_GetTXThreshold(mxc_i2c_regs_t *i2c) +{ + return MXC_I2C_RevA_GetTXThreshold((mxc_i2c_reva_regs_t *)i2c); +} + +void MXC_I2C_AsyncStop(mxc_i2c_regs_t *i2c) +{ + MXC_I2C_RevA_AsyncStop((mxc_i2c_reva_regs_t *)i2c); +} + +void MXC_I2C_AbortAsync(mxc_i2c_regs_t *i2c) +{ + MXC_I2C_RevA_AbortAsync((mxc_i2c_reva_regs_t *)i2c); +} + +void MXC_I2C_AsyncHandler(mxc_i2c_regs_t *i2c) +{ + MXC_I2C_RevA_AsyncHandler((mxc_i2c_reva_regs_t *)i2c, interruptCheck); +} + +void MXC_I2C_DMACallback(int ch, int error) +{ + MXC_I2C_RevA_DMACallback(ch, error); +} diff --git a/Libraries/PeriphDrivers/Source/ICC/icc_me30.c b/Libraries/PeriphDrivers/Source/ICC/icc_me30.c new file mode 100644 index 00000000000..1a9cc8cdda7 --- /dev/null +++ b/Libraries/PeriphDrivers/Source/ICC/icc_me30.c @@ -0,0 +1,57 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* **** Includes **** */ +#include "mxc_device.h" +#include "mxc_errors.h" +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "icc.h" +#include "icc_reva.h" +#include "icc_common.h" + +/* **** Definitions **** */ + +/* **** Globals **** */ + +/* **** Functions **** */ + +/* ****************************************************************************** +Maxim Internal Use + * ****************************************************************************** */ + +int MXC_ICC_ID(mxc_icc_regs_t *icc, mxc_icc_info_t cid) +{ + return MXC_ICC_RevA_ID((mxc_icc_reva_regs_t *)icc, cid); +} + +void MXC_ICC_Enable(mxc_icc_regs_t *icc) +{ + MXC_ICC_RevA_Enable((mxc_icc_reva_regs_t *)icc); +} + +void MXC_ICC_Disable(mxc_icc_regs_t *icc) +{ + MXC_ICC_RevA_Disable((mxc_icc_reva_regs_t *)icc); +} + +void MXC_ICC_Flush(mxc_icc_regs_t *icc) +{ + MXC_ICC_Disable(icc); + MXC_ICC_Enable(icc); +} diff --git a/Libraries/PeriphDrivers/Source/LP/lp_me30.c b/Libraries/PeriphDrivers/Source/LP/lp_me30.c new file mode 100644 index 00000000000..a041107d1ca --- /dev/null +++ b/Libraries/PeriphDrivers/Source/LP/lp_me30.c @@ -0,0 +1,254 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ +#include "mxc_device.h" +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "gcr_regs.h" +#include "mcr_regs.h" +#include "lp.h" +#include "lpcmp.h" + +#ifndef __riscv +/* ARM */ +#define SET_SLEEPDEEP(X) (SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk) +#define CLR_SLEEPDEEP(X) (SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk) +#else +/* RISCV */ +/* These bits do not exist for RISCV core */ +#define SET_SLEEPDEEP(X) +#define CLR_SLEEPDEEP(X) +#endif + +void MXC_LP_EnterSleepMode(void) +{ + MXC_LP_ClearWakeStatus(); + + /* Clear SLEEPDEEP bit */ + CLR_SLEEPDEEP(); + + /* Go into Sleep mode and wait for an interrupt to wake the processor */ + __WFI(); +} + +void MXC_LP_EnterLowPowerMode(void) +{ + MXC_LP_ClearWakeStatus(); + MXC_MCR->ctrl |= MXC_F_MCR_CTRL_ERTCO_EN; // Enabled for deep sleep mode + + /* Set SLEEPDEEP bit */ + SET_SLEEPDEEP(); + + /* Go into low power mode and wait for an interrupt to wake the processor */ + MXC_GCR->pm |= MXC_S_GCR_PM_MODE_LPM; + __WFI(); +} + +void MXC_LP_EnterMicroPowerMode(void) +{ + MXC_LP_ClearWakeStatus(); + MXC_MCR->ctrl |= MXC_F_MCR_CTRL_ERTCO_EN; // Enabled for deep sleep mode + + /* Set SLEEPDEEP bit */ + SET_SLEEPDEEP(); + + /* Go into Deepsleep mode and wait for an interrupt to wake the processor */ + MXC_GCR->pm |= MXC_S_GCR_PM_MODE_UPM; // UPM mode + __WFI(); +} + +void MXC_LP_EnterStandbyMode(void) +{ + MXC_LP_ClearWakeStatus(); + MXC_MCR->ctrl |= MXC_F_MCR_CTRL_ERTCO_EN; // Enabled for deep sleep mode + + /* Set SLEEPDEEP bit */ + SET_SLEEPDEEP(); + + /* Go into standby mode and wait for an interrupt to wake the processor */ + MXC_GCR->pm |= MXC_S_GCR_PM_MODE_STANDBY; // standby mode + __WFI(); +} + +void MXC_LP_EnterBackupMode(void) +{ + MXC_LP_ClearWakeStatus(); + + MXC_GCR->pm &= ~MXC_F_GCR_PM_MODE; + MXC_GCR->pm |= MXC_S_GCR_PM_MODE_BACKUP; + + while (1) {} + // Should never reach this line - device will jump to backup vector on exit from background mode. +} + +void MXC_LP_EnterPowerDownMode(void) +{ + MXC_GCR->pm &= ~MXC_F_GCR_PM_MODE; + MXC_GCR->pm |= MXC_S_GCR_PM_MODE_POWERDOWN; + + while (1) {} + // Should never reach this line - device will reset on exit from shutdown mode. +} + +void MXC_LP_SetOVR(mxc_lp_ovr_t ovr) +{ + //not supported yet +} + +void MXC_LP_BandgapOn(void) +{ + MXC_PWRSEQ->lpcn &= ~MXC_F_PWRSEQ_LPCN_BG_DIS; +} + +void MXC_LP_BandgapOff(void) +{ + MXC_PWRSEQ->lpcn |= MXC_F_PWRSEQ_LPCN_BG_DIS; +} + +int MXC_LP_BandgapIsOn(void) +{ + return (MXC_PWRSEQ->lpcn & MXC_F_PWRSEQ_LPCN_BG_DIS); +} + +void MXC_LP_ClearWakeStatus(void) +{ + /* Write 1 to clear */ + MXC_PWRSEQ->lpwkst0 = 0xFFFFFFFF; + MXC_PWRSEQ->lpwkst1 = 0xFFFFFFFF; + MXC_PWRSEQ->lpwkst2 = 0xFFFFFFFF; + MXC_PWRSEQ->lpwkst3 = 0xFFFFFFFF; + MXC_PWRSEQ->lppwst = 0xFFFFFFFF; +} + +void MXC_LP_EnableGPIOWakeup(mxc_gpio_cfg_t *wu_pins) +{ + MXC_GCR->pm |= MXC_F_GCR_PM_GPIO_WE; + + switch (1 << MXC_GPIO_GET_IDX(wu_pins->port)) { + case MXC_GPIO_PORT_0: + MXC_PWRSEQ->lpwken0 |= wu_pins->mask; + break; + + case MXC_GPIO_PORT_1: + MXC_PWRSEQ->lpwken1 |= wu_pins->mask; + break; + case MXC_GPIO_PORT_2: + MXC_PWRSEQ->lpwken2 |= wu_pins->mask; + break; + case MXC_GPIO_PORT_3: + MXC_PWRSEQ->lpwken3 |= wu_pins->mask; + break; + } +} + +void MXC_LP_DisableGPIOWakeup(mxc_gpio_cfg_t *wu_pins) +{ + switch (1 << MXC_GPIO_GET_IDX(wu_pins->port)) { + case MXC_GPIO_PORT_0: + MXC_PWRSEQ->lpwken0 &= ~wu_pins->mask; + break; + + case MXC_GPIO_PORT_1: + MXC_PWRSEQ->lpwken1 &= ~wu_pins->mask; + break; + case MXC_GPIO_PORT_2: + MXC_PWRSEQ->lpwken2 &= ~wu_pins->mask; + break; + case MXC_GPIO_PORT_3: + MXC_PWRSEQ->lpwken3 &= ~wu_pins->mask; + break; + } + + if (MXC_PWRSEQ->lpwken3 == 0 && MXC_PWRSEQ->lpwken2 == 0 && MXC_PWRSEQ->lpwken1 == 0 && + MXC_PWRSEQ->lpwken0 == 0) { + MXC_GCR->pm &= ~MXC_F_GCR_PM_GPIO_WE; + } +} + +void MXC_LP_EnableRTCAlarmWakeup(void) +{ + MXC_GCR->pm |= MXC_F_GCR_PM_RTC_WE; +} + +void MXC_LP_DisableRTCAlarmWakeup(void) +{ + MXC_GCR->pm &= ~MXC_F_GCR_PM_RTC_WE; +} + +void MXC_LP_EnableTimerWakeup(mxc_tmr_regs_t *tmr) +{ + MXC_ASSERT(MXC_TMR_GET_IDX(tmr) > 3); + + if (tmr == MXC_TMR4) { + MXC_PWRSEQ->lppwen |= MXC_F_PWRSEQ_LPPWEN_TMR4; + } else { + MXC_PWRSEQ->lppwen |= MXC_F_PWRSEQ_LPPWEN_TMR5; + } +} + +void MXC_LP_DisableTimerWakeup(mxc_tmr_regs_t *tmr) +{ + MXC_ASSERT(MXC_TMR_GET_IDX(tmr) > 3); + + if (tmr == MXC_TMR4) { + MXC_PWRSEQ->lppwen &= ~MXC_F_PWRSEQ_LPPWEN_TMR4; + } else { + MXC_PWRSEQ->lppwen &= ~MXC_F_PWRSEQ_LPPWEN_TMR5; + } +} + +void MXC_LP_EnableWUTAlarmWakeup(void) +{ + MXC_GCR->pm |= MXC_F_GCR_PM_WUT_WE; +} + +void MXC_LP_DisableWUTAlarmWakeup(void) +{ + MXC_GCR->pm &= ~MXC_F_GCR_PM_WUT_WE; +} + +void MXC_LP_EnableLPCMPWakeup(mxc_lpcmp_cmpsel_t cmp) +{ + MXC_ASSERT((cmp >= MXC_LPCMP_CMP0) && (cmp <= MXC_LPCMP_CMP3)); + + if (cmp == MXC_LPCMP_CMP0) { + MXC_PWRSEQ->lppwen |= MXC_F_PWRSEQ_LPPWEN_AINCOMP0; + } else { + MXC_PWRSEQ->lppwen |= MXC_F_PWRSEQ_LPPWEN_LPCMP; + } +} + +void MXC_LP_DisableLPCMPWakeup(mxc_lpcmp_cmpsel_t cmp) +{ + MXC_ASSERT((cmp >= MXC_LPCMP_CMP0) && (cmp <= MXC_LPCMP_CMP3)); + + if (cmp == MXC_LPCMP_CMP0) { + MXC_PWRSEQ->lppwen &= ~MXC_F_PWRSEQ_LPPWEN_AINCOMP0; + } else { + MXC_PWRSEQ->lppwen &= ~MXC_F_PWRSEQ_LPPWEN_LPCMP; + } +} + +int MXC_LP_ConfigDeepSleepClocks(uint32_t mask) +{ + if (!(mask & (MXC_F_GCR_PM_IBRO_PD | MXC_F_GCR_PM_IPO_PD))) { + return E_BAD_PARAM; + } + + MXC_GCR->pm |= mask; + return E_NO_ERROR; +} diff --git a/Libraries/PeriphDrivers/Source/RTC/rtc_me30.c b/Libraries/PeriphDrivers/Source/RTC/rtc_me30.c new file mode 100644 index 00000000000..6d6eefe2757 --- /dev/null +++ b/Libraries/PeriphDrivers/Source/RTC/rtc_me30.c @@ -0,0 +1,283 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#include "mxc_device.h" +#include "rtc_regs.h" +#include "rtc.h" +#include "mxc_sys.h" +#include "mxc_delay.h" +#include "gpio_regs.h" +#include "mxc_errors.h" +#include "mcr_regs.h" +#include "rtc_reva.h" +#include "tmr.h" +#include "trimsir_regs.h" + +#define SUBSECOND_MSEC_0 200 +#define SEARCH_STEPS 7 +#define SEARCH_TARGET 0x30d400 /* 1/2 of 32 MHz periods in 32.768 kHz */ + +#define RTCX1x_MASK 0x1F /* 5 bits */ +#define RTCX2x_MASK 0x1F /* 5 bits */ + +#define NOM_32K_FREQ 32768 +#define TICKS_PER_RTC 122 + +/* Converts a time in milleseconds to the equivalent RSSA register value. */ +#define MSEC_TO_RSSA(x) (unsigned int)(0x100000000ULL - ((x * 4096) / 1000)) + +/********************************************/ +/* Maxim Function Mapping */ +/********************************************/ + +int MXC_RTC_EnableInt(uint32_t mask) +{ + return MXC_RTC_RevA_EnableInt((mxc_rtc_reva_regs_t *)MXC_RTC, mask); +} + +int MXC_RTC_DisableInt(uint32_t mask) +{ + return MXC_RTC_RevA_DisableInt((mxc_rtc_reva_regs_t *)MXC_RTC, mask); +} + +int MXC_RTC_SetTimeofdayAlarm(uint32_t ras) +{ + return MXC_RTC_RevA_SetTimeofdayAlarm((mxc_rtc_reva_regs_t *)MXC_RTC, ras); +} + +int MXC_RTC_SetSubsecondAlarm(uint32_t rssa) +{ + return MXC_RTC_RevA_SetSubsecondAlarm((mxc_rtc_reva_regs_t *)MXC_RTC, rssa); +} + +int MXC_RTC_Start(void) +{ + return MXC_RTC_RevA_Start((mxc_rtc_reva_regs_t *)MXC_RTC); +} + +int MXC_RTC_Stop(void) +{ + return MXC_RTC_RevA_Stop((mxc_rtc_reva_regs_t *)MXC_RTC); +} + +int MXC_RTC_Init(uint32_t sec, uint16_t ssec) +{ + MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_ERTCO_EN; + + return MXC_RTC_RevA_Init((mxc_rtc_reva_regs_t *)MXC_RTC, sec, (ssec & MXC_F_RTC_SSEC_SSEC)); +} + +int MXC_RTC_SquareWaveStart(mxc_rtc_freq_sel_t ft) +{ + MXC_GPIO_Config(&gpio_cfg_rtcsqw); + MXC_MCR->outen |= MXC_F_MCR_OUTEN_SQWOUT_EN; + + return MXC_RTC_RevA_SquareWave((mxc_rtc_reva_regs_t *)MXC_RTC, MXC_RTC_REVA_SQUARE_WAVE_ENABLED, + ft); +} + +int MXC_RTC_SquareWaveStop(void) +{ + MXC_MCR->outen &= ~(MXC_F_MCR_OUTEN_SQWOUT_EN); + + return MXC_RTC_RevA_SquareWave((mxc_rtc_reva_regs_t *)MXC_RTC, + MXC_RTC_REVA_SQUARE_WAVE_DISABLED, 0); +} + +int MXC_RTC_Trim(int8_t trm) +{ + return MXC_RTC_RevA_Trim((mxc_rtc_reva_regs_t *)MXC_RTC, trm); +} + +int MXC_RTC_GetFlags(void) +{ + return MXC_RTC_RevA_GetFlags((mxc_rtc_reva_regs_t *)MXC_RTC); +} + +int MXC_RTC_ClearFlags(int flags) +{ + return MXC_RTC_RevA_ClearFlags((mxc_rtc_reva_regs_t *)MXC_RTC, flags); +} + +int MXC_RTC_GetSubSecond(void) +{ + return MXC_RTC_RevA_GetSubSecond((mxc_rtc_reva_regs_t *)MXC_RTC); +} + +int MXC_RTC_GetSecond(void) +{ + return MXC_RTC_RevA_GetSecond((mxc_rtc_reva_regs_t *)MXC_RTC); +} + +int MXC_RTC_GetSubSeconds(uint32_t *ssec) +{ + MXC_RTC->ctrl &= ~MXC_F_RTC_CTRL_RDY; // Ensure valid data is in SSEC register + while (!(MXC_RTC->ctrl & MXC_F_RTC_CTRL_RDY)) {} + + return MXC_RTC_RevA_GetSubSeconds((mxc_rtc_reva_regs_t *)MXC_RTC, ssec); +} + +int MXC_RTC_GetSeconds(uint32_t *sec) +{ + MXC_RTC->ctrl &= ~MXC_F_RTC_CTRL_RDY; // Ensure valid data is in SEC register + while (!(MXC_RTC->ctrl & MXC_F_RTC_CTRL_RDY)) {} + + return MXC_RTC_RevA_GetSeconds((mxc_rtc_reva_regs_t *)MXC_RTC, sec); +} + +int MXC_RTC_GetTime(uint32_t *sec, uint32_t *subsec) +{ + return MXC_RTC_RevA_GetTime((mxc_rtc_reva_regs_t *)MXC_RTC, sec, subsec); +} + +int MXC_RTC_GetBusyFlag(void) +{ + return MXC_RTC_RevA_GetBusyFlag((mxc_rtc_reva_regs_t *)MXC_RTC); +} + +int MXC_RTC_TrimCrystal(void) +{ +#if TARGET_NUM == 78000 + /* MAX78000 does not have the ERFO clock which the Trim function requires */ + return E_NOT_SUPPORTED; +#endif + + unsigned int search_step, elapsed; + unsigned int upper, lower, trim, oldtrim, bestTrim, bestElapsed, bestElapsedDiff; + unsigned int freq = NOM_32K_FREQ; + int retval; + + /* Determine starting point for internal load capacitors */ + upper = RTCX1x_MASK; + lower = 0; + trim = (upper + lower) / 2; + + /* Initialize best trim variables */ + bestTrim = trim; + bestElapsed = bestElapsedDiff = SEARCH_TARGET; + + /* Init timer to count 32 MHz periods */ + mxc_tmr_cfg_t tmr_cfg; + tmr_cfg.pres = MXC_TMR_PRES_1; + tmr_cfg.mode = MXC_TMR_MODE_CONTINUOUS; + tmr_cfg.bitMode = MXC_TMR_BIT_MODE_32; + tmr_cfg.clock = MXC_TMR_APB_CLK; + tmr_cfg.cmp_cnt = 0xFFFFFFFF; + tmr_cfg.pol = 0; + MXC_TMR_Init(MXC_TMR3, &tmr_cfg, FALSE); + + /* Clear out any previous configuration */ + MXC_RTC_DisableInt(MXC_F_RTC_CTRL_TOD_ALARM_IE | MXC_F_RTC_CTRL_SSEC_ALARM_IE | + MXC_F_RTC_CTRL_RDY_IE); + MXC_RTC_ClearFlags(MXC_RTC_GetFlags()); + + MXC_RTC->oscctrl &= ~(MXC_F_RTC_OSCCTRL_BYPASS | MXC_F_RTC_OSCCTRL_SQW_32K); + + /* Setup SSEC Alarm */ + MXC_RTC_DisableInt(MXC_F_RTC_CTRL_SSEC_ALARM_IE); + retval = MXC_RTC_SetSubsecondAlarm(MSEC_TO_RSSA(SUBSECOND_MSEC_0)); + if (retval != E_NO_ERROR) { + return retval; + } + MXC_RTC_EnableInt(MXC_F_RTC_CTRL_SSEC_ALARM_IE); + + /* Trim loop */ + search_step = 0; + while (search_step < SEARCH_STEPS) { + /* Set new trim point */ + oldtrim = trim; + trim = (lower + upper) / 2; + if ((search_step > 0) && (trim == oldtrim)) { + /* Found trim value */ + break; + } + + /* Set the trim values */ + MXC_SETFIELD(MXC_TRIMSIR->rtc, MXC_F_TRIMSIR_RTC_X1TRIM, + (trim << MXC_F_TRIMSIR_RTC_X1TRIM_POS)); + MXC_SETFIELD(MXC_TRIMSIR->rtc, MXC_F_TRIMSIR_RTC_X2TRIM, + (trim << MXC_F_TRIMSIR_RTC_X2TRIM_POS)); + + /* Sleep to settle new caps */ + MXC_Delay(MXC_DELAY_MSEC(10)); + + /* Start 200 msec sampling window */ + MXC_TMR_Stop(MXC_TMR3); + MXC_TMR_SetCount(MXC_TMR3, 0); + + /* Wait for an RTC edge */ + MXC_RTC_ClearFlags(MXC_RTC_GetFlags()); + while (!(MXC_RTC->ctrl & MXC_F_RTC_CTRL_SSEC_ALARM)) {} + + MXC_TMR_Start(MXC_TMR3); + + /* Wait for an RTC edge */ + MXC_RTC_ClearFlags(MXC_RTC_GetFlags()); + while (!(MXC_RTC->ctrl & MXC_F_RTC_CTRL_SSEC_ALARM)) {} + + /* Capture the TMR count and adjust for processing delay */ + elapsed = MXC_TMR_GetCount(MXC_TMR3); + MXC_TMR_Stop(MXC_TMR3); + elapsed += 810; + + /* Binary search for optimal trim value */ + if (elapsed > SEARCH_TARGET) { + /* Too slow */ + upper = trim; + + /* Record best setting */ + if ((elapsed - SEARCH_TARGET) <= bestElapsedDiff) { + bestElapsedDiff = elapsed - SEARCH_TARGET; + bestElapsed = elapsed; + bestTrim = trim; + } + } else { + /* Too fast */ + lower = trim; + + /* Record best setting */ + if ((SEARCH_TARGET - elapsed) <= bestElapsedDiff) { + bestElapsedDiff = SEARCH_TARGET - elapsed; + bestElapsed = elapsed; + bestTrim = trim; + } + } + + search_step++; + } + + /* Apply the closest trim setting */ + MXC_SETFIELD(MXC_TRIMSIR->rtc, MXC_F_TRIMSIR_RTC_X1TRIM, + (bestTrim << MXC_F_TRIMSIR_RTC_X1TRIM_POS)); + MXC_SETFIELD(MXC_TRIMSIR->rtc, MXC_F_TRIMSIR_RTC_X2TRIM, + (bestTrim << MXC_F_TRIMSIR_RTC_X2TRIM_POS)); + + /* Adjust 32K freq if we can't get close enough to 32768 Hz */ + if (bestElapsed >= SEARCH_TARGET) { + freq -= (((bestElapsed - SEARCH_TARGET) + (TICKS_PER_RTC / 2 - 1)) / TICKS_PER_RTC); + } else { + freq += (((SEARCH_TARGET - bestElapsed) + (TICKS_PER_RTC / 2 - 1)) / TICKS_PER_RTC); + } + + /* Clear hardware state */ + MXC_TMR_Stop(MXC_TMR3); + MXC_TMR_Shutdown(MXC_TMR3); + MXC_RTC_ClearFlags(MXC_RTC_GetFlags()); + + return freq; +} diff --git a/Libraries/PeriphDrivers/Source/SPI/spi_me30.c b/Libraries/PeriphDrivers/Source/SPI/spi_me30.c new file mode 100644 index 00000000000..da6225abb7b --- /dev/null +++ b/Libraries/PeriphDrivers/Source/SPI/spi_me30.c @@ -0,0 +1,526 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#include +#include +#include +#include + +#include "mxc_device.h" +#include "mxc_assert.h" +#include "mxc_lock.h" +#include "mxc_sys.h" +#include "mxc_delay.h" +#include "spi_reva1.h" +#include "dma.h" + +/* **** Definitions **** */ + +/* ************************************************************************** */ +int MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int quadModeUsed, int numSlaves, + unsigned ssPolarity, unsigned int hz, mxc_spi_pins_t pins) +{ + int spi_num; + + spi_num = MXC_SPI_GET_IDX(spi); + MXC_ASSERT(spi_num >= 0); + + if (numSlaves > MXC_SPI_SS_INSTANCES) { + return E_BAD_PARAM; + } + + // Check if frequency is too high + if ((spi_num == 0) && (hz > PeripheralClock)) { + return E_BAD_PARAM; + } + + if ((spi_num == 1) && (hz > SystemCoreClock)) { + return E_BAD_PARAM; + } + +#ifndef MSDK_NO_GPIO_CLK_INIT + mxc_gpio_cfg_t gpio_cfg_spi; + gpio_cfg_spi.pad = MXC_GPIO_PAD_NONE; + gpio_cfg_spi.port = MXC_GPIO0; + + // Set VDDIO level + if (pins.vddioh) { + gpio_cfg_spi.vssel = MXC_GPIO_VSSEL_VDDIOH; + } else { + gpio_cfg_spi.vssel = MXC_GPIO_VSSEL_VDDIO; + } + + // Configure GPIO for spi + if (spi == MXC_SPI1) { + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_SPI1); + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_SPI1); + +#if (TARGET != MAX78000 || TARGET_NUM == 32655) + + //Define pins + if (pins.ss1) { + gpio_cfg_spi.mask = MXC_GPIO_PIN_26; + gpio_cfg_spi.func = MXC_GPIO_FUNC_ALT2; + MXC_GPIO_Config(&gpio_cfg_spi); + } + + if (pins.ss2) { + gpio_cfg_spi.func = MXC_GPIO_FUNC_ALT2; + gpio_cfg_spi.mask = MXC_GPIO_PIN_27; + MXC_GPIO_Config(&gpio_cfg_spi); + } + +#endif + //clear mask + gpio_cfg_spi.mask = 0; + + // check rest of the pins + if (pins.clock) { + gpio_cfg_spi.mask |= MXC_GPIO_PIN_23; + } + + if (pins.miso) { + gpio_cfg_spi.mask |= MXC_GPIO_PIN_22; + } + + if (pins.mosi) { + gpio_cfg_spi.mask |= MXC_GPIO_PIN_21; + } + + if (pins.sdio2) { + gpio_cfg_spi.mask |= MXC_GPIO_PIN_24; + } + + if (pins.sdio3) { + gpio_cfg_spi.mask |= MXC_GPIO_PIN_25; + } + + if (pins.ss0) { + gpio_cfg_spi.mask |= MXC_GPIO_PIN_20; + } + + gpio_cfg_spi.func = MXC_GPIO_FUNC_ALT1; +#ifdef MXC_SPI0 + } else if (spi == MXC_SPI0) { + MXC_SYS_Reset_Periph(MXC_SYS_RESET1_SPI0); + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_SPI0); + + //Define pins + if (pins.ss1) { + gpio_cfg_spi.mask = MXC_GPIO_PIN_11; + gpio_cfg_spi.func = MXC_GPIO_FUNC_ALT2; + MXC_GPIO_Config(&gpio_cfg_spi); + } + + if (pins.ss2) { + gpio_cfg_spi.func = MXC_GPIO_FUNC_ALT2; + gpio_cfg_spi.mask = MXC_GPIO_PIN_10; + MXC_GPIO_Config(&gpio_cfg_spi); + } + + //clear mask + gpio_cfg_spi.mask = 0; + + // check rest of the pins + if (pins.clock) { + gpio_cfg_spi.mask |= MXC_GPIO_PIN_7; + } + + if (pins.miso) { + gpio_cfg_spi.mask |= MXC_GPIO_PIN_6; + } + + if (pins.mosi) { + gpio_cfg_spi.mask |= MXC_GPIO_PIN_5; + } + + if (pins.sdio2) { + gpio_cfg_spi.mask |= MXC_GPIO_PIN_8; + } + + if (pins.sdio3) { + gpio_cfg_spi.mask |= MXC_GPIO_PIN_9; + } + + if (pins.ss0) { + gpio_cfg_spi.mask |= MXC_GPIO_PIN_4; + } + + gpio_cfg_spi.func = MXC_GPIO_FUNC_ALT1; +#endif + } else { + return E_NO_DEVICE; + } + + MXC_GPIO_Config(&gpio_cfg_spi); +#else + (void)pins; +#endif // MSDK_NO_GPIO_CLK_INIT + + return MXC_SPI_RevA1_Init((mxc_spi_reva_regs_t *)spi, masterMode, quadModeUsed, numSlaves, + ssPolarity, hz); +} + +int MXC_SPI_Shutdown(mxc_spi_regs_t *spi) +{ + int spi_num; + spi_num = MXC_SPI_GET_IDX(spi); + MXC_ASSERT(spi_num >= 0); + (void)spi_num; + + MXC_SPI_RevA1_Shutdown((mxc_spi_reva_regs_t *)spi); + + if (spi == MXC_SPI1) { + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SPI1); +#ifdef MXC_SPI0 + } else if (spi == MXC_SPI0) { + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SPI0); +#endif + } else { + return E_NO_DEVICE; + } + + return E_NO_ERROR; +} + +int MXC_SPI_ReadyForSleep(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA1_ReadyForSleep((mxc_spi_reva_regs_t *)spi); +} + +int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t *spi) +{ + int retval; + + if (spi == MXC_SPI1) { + retval = PeripheralClock; +#ifdef MXC_SPI0 // SPI0 is not accessible from the RISC core. + } else if (spi == MXC_SPI0) { + int sys_clk = (MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_SEL) >> + MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS; + switch (sys_clk) { + case MXC_SYS_CLOCK_IPO: + retval = IPO_FREQ; + break; + case MXC_SYS_CLOCK_IBRO: + retval = IBRO_FREQ; + break; + case MXC_SYS_CLOCK_ISO: + retval = ISO_FREQ; + break; + case MXC_SYS_CLOCK_INRO: + retval = INRO_FREQ; + break; + case MXC_SYS_CLOCK_ERTCO: + retval = ERTCO_FREQ; + break; + case MXC_SYS_CLOCK_EXTCLK: + retval = EXTCLK_FREQ; + break; +#if TARGET_NUM == 32655 || TARGET_NUM == 32680 + case MXC_SYS_CLOCK_ERFO: + retval = ERFO_FREQ; + break; +#endif + default: + return E_BAD_STATE; + } +#endif // MXC_SPI0 + } else { + return E_BAD_PARAM; + } + + retval /= 2; + + return retval; +} + +int MXC_SPI_SetFrequency(mxc_spi_regs_t *spi, unsigned int hz) +{ + return MXC_SPI_RevA1_SetFrequency((mxc_spi_reva_regs_t *)spi, hz); +} + +unsigned int MXC_SPI_GetFrequency(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA1_GetFrequency((mxc_spi_reva_regs_t *)spi); +} + +int MXC_SPI_SetDataSize(mxc_spi_regs_t *spi, int dataSize) +{ + return MXC_SPI_RevA1_SetDataSize((mxc_spi_reva_regs_t *)spi, dataSize); +} + +int MXC_SPI_GetDataSize(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA1_GetDataSize((mxc_spi_reva_regs_t *)spi); +} + +int MXC_SPI_SetSlave(mxc_spi_regs_t *spi, int ssIdx) +{ + return MXC_SPI_RevA1_SetSlave((mxc_spi_reva_regs_t *)spi, ssIdx); +} + +int MXC_SPI_GetSlave(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA1_GetSlave((mxc_spi_reva_regs_t *)spi); +} + +int MXC_SPI_SetWidth(mxc_spi_regs_t *spi, mxc_spi_width_t spiWidth) +{ + return MXC_SPI_RevA1_SetWidth((mxc_spi_reva_regs_t *)spi, spiWidth); +} + +mxc_spi_width_t MXC_SPI_GetWidth(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA1_GetWidth((mxc_spi_reva_regs_t *)spi); +} + +int MXC_SPI_SetMTMode(mxc_spi_regs_t *spi, int mtMode) +{ + return MXC_SPI_RevA1_SetMTMode((mxc_spi_reva_regs_t *)spi, mtMode); +} + +int MXC_SPI_GetMTMode(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA1_GetMTMode((mxc_spi_reva_regs_t *)spi); +} + +int MXC_SPI_SetMode(mxc_spi_regs_t *spi, mxc_spi_mode_t spiMode) +{ + return MXC_SPI_RevA1_SetMode((mxc_spi_reva_regs_t *)spi, spiMode); +} + +mxc_spi_mode_t MXC_SPI_GetMode(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA1_GetMode((mxc_spi_reva_regs_t *)spi); +} + +int MXC_SPI_StartTransmission(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA1_StartTransmission((mxc_spi_reva_regs_t *)spi); +} + +int MXC_SPI_GetActive(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA1_GetActive((mxc_spi_reva_regs_t *)spi); +} + +int MXC_SPI_AbortTransmission(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA1_AbortTransmission((mxc_spi_reva_regs_t *)spi); +} + +unsigned int MXC_SPI_ReadRXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len) +{ + return MXC_SPI_RevA1_ReadRXFIFO((mxc_spi_reva_regs_t *)spi, bytes, len); +} + +unsigned int MXC_SPI_GetRXFIFOAvailable(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA1_GetRXFIFOAvailable((mxc_spi_reva_regs_t *)spi); +} + +unsigned int MXC_SPI_WriteTXFIFO(mxc_spi_regs_t *spi, unsigned char *bytes, unsigned int len) +{ + return MXC_SPI_RevA1_WriteTXFIFO((mxc_spi_reva_regs_t *)spi, bytes, len); +} + +unsigned int MXC_SPI_GetTXFIFOAvailable(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA1_GetTXFIFOAvailable((mxc_spi_reva_regs_t *)spi); +} + +void MXC_SPI_ClearRXFIFO(mxc_spi_regs_t *spi) +{ + MXC_SPI_RevA1_ClearRXFIFO((mxc_spi_reva_regs_t *)spi); +} + +void MXC_SPI_ClearTXFIFO(mxc_spi_regs_t *spi) +{ + MXC_SPI_RevA1_ClearTXFIFO((mxc_spi_reva_regs_t *)spi); +} + +int MXC_SPI_SetRXThreshold(mxc_spi_regs_t *spi, unsigned int numBytes) +{ + return MXC_SPI_RevA1_SetRXThreshold((mxc_spi_reva_regs_t *)spi, numBytes); +} + +unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA1_GetRXThreshold((mxc_spi_reva_regs_t *)spi); +} + +int MXC_SPI_SetTXThreshold(mxc_spi_regs_t *spi, unsigned int numBytes) +{ + return MXC_SPI_RevA1_SetTXThreshold((mxc_spi_reva_regs_t *)spi, numBytes); +} + +unsigned int MXC_SPI_GetTXThreshold(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA1_GetTXThreshold((mxc_spi_reva_regs_t *)spi); +} + +unsigned int MXC_SPI_GetFlags(mxc_spi_regs_t *spi) +{ + return MXC_SPI_RevA1_GetFlags((mxc_spi_reva_regs_t *)spi); +} + +void MXC_SPI_ClearFlags(mxc_spi_regs_t *spi) +{ + MXC_SPI_RevA1_ClearFlags((mxc_spi_reva_regs_t *)spi); +} + +void MXC_SPI_EnableInt(mxc_spi_regs_t *spi, unsigned int intEn) +{ + MXC_SPI_RevA1_EnableInt((mxc_spi_reva_regs_t *)spi, intEn); +} + +void MXC_SPI_DisableInt(mxc_spi_regs_t *spi, unsigned int intDis) +{ + MXC_SPI_RevA1_DisableInt((mxc_spi_reva_regs_t *)spi, intDis); +} + +int MXC_SPI_MasterTransaction(mxc_spi_req_t *req) +{ + return MXC_SPI_RevA1_MasterTransaction((mxc_spi_reva_req_t *)req); +} + +int MXC_SPI_MasterTransactionAsync(mxc_spi_req_t *req) +{ + return MXC_SPI_RevA1_MasterTransactionAsync((mxc_spi_reva_req_t *)req); +} + +int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req) +{ + int reqselTx = -1; + int reqselRx = -1; + + int spi_num; + + spi_num = MXC_SPI_GET_IDX(req->spi); + MXC_ASSERT(spi_num >= 0); + + if (req->txData != NULL) { + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + break; + + case 1: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + break; + + default: + return E_BAD_PARAM; + } + } + + if (req->rxData != NULL) { + switch (spi_num) { + case 0: + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; + + case 1: + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; + + default: + return E_BAD_PARAM; + } + } + + return MXC_SPI_RevA1_MasterTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, + MXC_DMA); +} + +int MXC_SPI_SlaveTransaction(mxc_spi_req_t *req) +{ + return MXC_SPI_RevA1_SlaveTransaction((mxc_spi_reva_req_t *)req); +} + +int MXC_SPI_SlaveTransactionAsync(mxc_spi_req_t *req) +{ + return MXC_SPI_RevA1_SlaveTransactionAsync((mxc_spi_reva_req_t *)req); +} + +int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req) +{ + int reqselTx = -1; + int reqselRx = -1; + + int spi_num; + + spi_num = MXC_SPI_GET_IDX(req->spi); + MXC_ASSERT(spi_num >= 0); + + if (req->txData != NULL) { + switch (spi_num) { + case 0: + reqselTx = MXC_DMA_REQUEST_SPI1TX; + break; + + case 1: + reqselTx = MXC_DMA_REQUEST_SPI0TX; + break; + + default: + return E_BAD_PARAM; + break; + } + } + + if (req->rxData != NULL) { + switch (spi_num) { + case 0: + reqselRx = MXC_DMA_REQUEST_SPI1RX; + break; + + case 1: + reqselRx = MXC_DMA_REQUEST_SPI0RX; + break; + + default: + return E_BAD_PARAM; + break; + } + } + + return MXC_SPI_RevA1_SlaveTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, + MXC_DMA); +} + +int MXC_SPI_SetDefaultTXData(mxc_spi_regs_t *spi, unsigned int defaultTXData) +{ + return MXC_SPI_RevA1_SetDefaultTXData((mxc_spi_reva_regs_t *)spi, defaultTXData); +} + +void MXC_SPI_AbortAsync(mxc_spi_regs_t *spi) +{ + MXC_SPI_RevA1_AbortAsync((mxc_spi_reva_regs_t *)spi); +} + +void MXC_SPI_AsyncHandler(mxc_spi_regs_t *spi) +{ + MXC_SPI_RevA1_AsyncHandler((mxc_spi_reva_regs_t *)spi); +} + +void MXC_SPI_HWSSControl(mxc_spi_regs_t *spi, int state) +{ + MXC_SPI_RevA1_HWSSControl((mxc_spi_reva_regs_t *)spi, state); +} diff --git a/Libraries/PeriphDrivers/Source/SYS/pins_me30.c b/Libraries/PeriphDrivers/Source/SYS/pins_me30.c new file mode 100644 index 00000000000..79c0d33bc52 --- /dev/null +++ b/Libraries/PeriphDrivers/Source/SYS/pins_me30.c @@ -0,0 +1,163 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#include "gpio.h" +#include "mxc_device.h" + +/***** Definitions *****/ + +/***** Global Variables *****/ + +// clang-format off +const mxc_gpio_cfg_t gpio_cfg_extclk = { MXC_GPIO0, (MXC_GPIO_PIN_12 | MXC_GPIO_PIN_13), MXC_GPIO_FUNC_ALT2, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; + +const mxc_gpio_cfg_t gpio_cfg_i2c0 = { MXC_GPIO0, (MXC_GPIO_PIN_10 | MXC_GPIO_PIN_11), MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_i2c1 = { MXC_GPIO0, (MXC_GPIO_PIN_16 | MXC_GPIO_PIN_17), MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_i2c2 = { MXC_GPIO0, (MXC_GPIO_PIN_30 | MXC_GPIO_PIN_31), MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; + +const mxc_gpio_cfg_t gpio_cfg_uart0 = { MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1), MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_uart0_flow = { MXC_GPIO0, (MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3), MXC_GPIO_FUNC_ALT2, + MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_uart0_flow_disable = { MXC_GPIO0, (MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3), MXC_GPIO_FUNC_IN, + MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_uart1 = { MXC_GPIO0, (MXC_GPIO_PIN_12 | MXC_GPIO_PIN_13), MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_uart1_flow = { MXC_GPIO0, (MXC_GPIO_PIN_14 | MXC_GPIO_PIN_15), MXC_GPIO_FUNC_ALT2, + MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_uart1_flow_disable = { MXC_GPIO0, (MXC_GPIO_PIN_14 | MXC_GPIO_PIN_15), MXC_GPIO_FUNC_IN, + MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_uart2 = { MXC_GPIO1, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1), MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_uart2_flow = { MXC_GPIO0, (MXC_GPIO_PIN_30 | MXC_GPIO_PIN_31), MXC_GPIO_FUNC_ALT2, + MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_uart2_flow_disable = { MXC_GPIO0, (MXC_GPIO_PIN_30 | MXC_GPIO_PIN_31), MXC_GPIO_FUNC_IN, + MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_uart3 = { MXC_GPIO2, (MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7), MXC_GPIO_FUNC_ALT2, + MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; + +const mxc_gpio_cfg_t antenna_ctrl0 = { MXC_GPIO1, (MXC_GPIO_PIN_8 | MXC_GPIO_PIN_9), MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t antenna_ctrl1 = { MXC_GPIO1, (MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7), MXC_GPIO_FUNC_ALT2, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; + +// Timers are only defined once, depending on package, each timer could be mapped to other pins +const mxc_gpio_cfg_t gpio_cfg_tmr0 = { MXC_GPIO0, (MXC_GPIO_PIN_2), MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_tmr0b = { MXC_GPIO0, (MXC_GPIO_PIN_3), MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_tmr1 = { MXC_GPIO0, (MXC_GPIO_PIN_14), MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_tmr1b = { MXC_GPIO0, (MXC_GPIO_PIN_15), MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_tmr1_MapB = { MXC_GPIO0, (MXC_GPIO_PIN_20), MXC_GPIO_FUNC_ALT2, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_tmr2 = { MXC_GPIO0, (MXC_GPIO_PIN_26), MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_tmr2b = { MXC_GPIO0, (MXC_GPIO_PIN_27), MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_tmr3 = { MXC_GPIO1, (MXC_GPIO_PIN_6), MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_tmr3b = { MXC_GPIO1, (MXC_GPIO_PIN_7), MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; + +const mxc_gpio_cfg_t gpio_cfg_i2s0 = { MXC_GPIO1, (MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3 | MXC_GPIO_PIN_4 | MXC_GPIO_PIN_5), + MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; + +const mxc_gpio_cfg_t gpio_cfg_i2s0_clkext = { MXC_GPIO0, MXC_GPIO_PIN_14, MXC_GPIO_FUNC_ALT2, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; + +const mxc_gpio_cfg_t gpio_cfg_rtcsqw = { MXC_GPIO3, MXC_GPIO_PIN_1, MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIOH, MXC_GPIO_DRVSTR_0}; + +const mxc_gpio_cfg_t gpio_cfg_pt0 = { MXC_GPIO0, MXC_GPIO_PIN_18, MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_pt1 = { MXC_GPIO0, MXC_GPIO_PIN_19, MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_pt2 = { MXC_GPIO0, MXC_GPIO_PIN_16, MXC_GPIO_FUNC_ALT2, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_pt3 = { MXC_GPIO0, MXC_GPIO_PIN_17, MXC_GPIO_FUNC_ALT2, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; + +// 1-Wire pins need to be at 3.3V so that MXC_GPIO_VSSEL_VDDIOH is selected. +const mxc_gpio_cfg_t gpio_cfg_owm = { MXC_GPIO0, (MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7), MXC_GPIO_FUNC_ALT2, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIOH, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_owmb = { MXC_GPIO0, (MXC_GPIO_PIN_18 | MXC_GPIO_PIN_19), MXC_GPIO_FUNC_ALT2, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIOH, MXC_GPIO_DRVSTR_0 }; + +const mxc_gpio_cfg_t gpio_cfg_adc_ain0 = { MXC_GPIO2, MXC_GPIO_PIN_0, MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_adc_ain1 = { MXC_GPIO2, MXC_GPIO_PIN_1, MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_adc_ain2 = { MXC_GPIO2, MXC_GPIO_PIN_2, MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_adc_ain3 = { MXC_GPIO2, MXC_GPIO_PIN_3, MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_adc_ain4 = { MXC_GPIO2, MXC_GPIO_PIN_4, MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_adc_ain5 = { MXC_GPIO2, MXC_GPIO_PIN_5, MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_adc_ain6 = { MXC_GPIO2, MXC_GPIO_PIN_6, MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_adc_ain7 = { MXC_GPIO2, MXC_GPIO_PIN_7, MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; + +const mxc_gpio_cfg_t gpio_cfg_rv_jtag = { MXC_GPIO1, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1 | MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3), + MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; + +const mxc_gpio_cfg_t gpio_cfg_cmp0 = { MXC_GPIO2, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1), MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_cmp1 = { MXC_GPIO2, (MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3), MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_cmp2 = { MXC_GPIO2, (MXC_GPIO_PIN_4 | MXC_GPIO_PIN_5), MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_cmp3 = { MXC_GPIO2, (MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7), MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; + +// SPI v2 Pin Definitions +const mxc_gpio_cfg_t gpio_cfg_spi0_standard = { MXC_GPIO0, (MXC_GPIO_PIN_5 | MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7), + MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_spi0_3wire = { MXC_GPIO0, (MXC_GPIO_PIN_5 | MXC_GPIO_PIN_7), MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_spi0_dual = { MXC_GPIO0, (MXC_GPIO_PIN_5 | MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7), MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_spi0_quad = { MXC_GPIO0, (MXC_GPIO_PIN_5 | MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7 | MXC_GPIO_PIN_8 | MXC_GPIO_PIN_9), + MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; + +const mxc_gpio_cfg_t gpio_cfg_spi1_standard = { MXC_GPIO0, (MXC_GPIO_PIN_21 | MXC_GPIO_PIN_22 | MXC_GPIO_PIN_23), MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_spi1_3wire = { MXC_GPIO0, (MXC_GPIO_PIN_21 | MXC_GPIO_PIN_23), MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_spi1_dual = { MXC_GPIO0, (MXC_GPIO_PIN_21 | MXC_GPIO_PIN_22 | MXC_GPIO_PIN_23), + MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_spi1_quad = { MXC_GPIO0, (MXC_GPIO_PIN_21 | MXC_GPIO_PIN_22 | MXC_GPIO_PIN_23 | MXC_GPIO_PIN_24 | MXC_GPIO_PIN_25), + MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; + +// SPI v2 Target Selects Pin Definitions +const mxc_gpio_cfg_t gpio_cfg_spi0_ts0 = { MXC_GPIO0, MXC_GPIO_PIN_4, MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_spi0_ts1 = { MXC_GPIO0, MXC_GPIO_PIN_26, MXC_GPIO_FUNC_ALT2, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_spi0_ts2 = { MXC_GPIO0, MXC_GPIO_PIN_27, MXC_GPIO_FUNC_ALT2, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_spi1_ts0 = { MXC_GPIO0, MXC_GPIO_PIN_20, MXC_GPIO_FUNC_ALT1, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; diff --git a/Libraries/PeriphDrivers/Source/SYS/sys_me30.c b/Libraries/PeriphDrivers/Source/SYS/sys_me30.c new file mode 100644 index 00000000000..4ad2ab85b67 --- /dev/null +++ b/Libraries/PeriphDrivers/Source/SYS/sys_me30.c @@ -0,0 +1,605 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/** + * @file mxc_sys.c + * @brief System layer driver. + * @details This driver is used to control the system layer of the device. + */ + +/* **** Includes **** */ +#include +#include +#include "mxc_device.h" +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "mxc_delay.h" +#include "lpgcr_regs.h" +#include "gcr_regs.h" +#include "fcr_regs.h" +#include "mcr_regs.h" +#include "pwrseq_regs.h" +#include "aes.h" +#include "flc.h" + +/** + * @ingroup mxc_sys + * @{ + */ + +/* **** Definitions **** */ +#define MXC_SYS_CLOCK_TIMEOUT MSEC(1) + +// DAP Lock macros +#define INFOBLOCK_DAP_LOCK_OFFSET 0x30 +#define DAP_LOCK_SEQUENCE_01 0x5A5AA5A5 +#define DAP_LOCK_SEQUENCE_23 0xFFFFFFFF + +/* **** Globals **** */ + +/* Symbol defined when loading RISCV image */ +extern uint32_t _binary_riscv_bin_start; + +/* **** Functions **** */ + +/* ************************************************************************** */ +int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum) +{ + int err = E_NO_ERROR; + uint32_t *infoblock = (uint32_t *)MXC_INFO0_MEM_BASE; + + if (usn == NULL) { + return E_NULL_PTR; + } + + /* Read the USN from the info block */ + MXC_FLC_UnlockInfoBlock(MXC_INFO0_MEM_BASE); + + memset(usn, 0, MXC_SYS_USN_CHECKSUM_LEN); + + usn[0] = (infoblock[0] & 0x007F8000) >> 15; + usn[1] = (infoblock[0] & 0x7F800000) >> 23; + usn[2] = (infoblock[1] & 0x0000007F) << 1; + usn[2] |= (infoblock[0] & 0x80000000) >> 31; + usn[3] = (infoblock[1] & 0x00007F80) >> 7; + usn[4] = (infoblock[1] & 0x007F8000) >> 15; + usn[5] = (infoblock[1] & 0x7F800000) >> 23; + usn[6] = (infoblock[2] & 0x007F8000) >> 15; + usn[7] = (infoblock[2] & 0x7F800000) >> 23; + usn[8] = (infoblock[3] & 0x0000007F) << 1; + usn[8] |= (infoblock[2] & 0x80000000) >> 31; + usn[9] = (infoblock[3] & 0x00007F80) >> 7; + usn[10] = (infoblock[3] & 0x007F8000) >> 15; + + /* If requested, verify and return the checksum */ + if (checksum != NULL) { + uint8_t check_csum[MXC_SYS_USN_CHECKSUM_LEN]; + uint8_t aes_key[MXC_SYS_USN_CHECKSUM_LEN] = { 0 }; // NULL Key (per checksum spec) + + checksum[0] = ((infoblock[3] & 0x7F800000) >> 23); + checksum[1] = ((infoblock[4] & 0x007F8000) >> 15); + + err = MXC_AES_Init(); + if (err) { + MXC_FLC_LockInfoBlock(MXC_INFO0_MEM_BASE); + return err; + } + + // Set NULL Key + MXC_AES_SetExtKey((const void *)aes_key, MXC_AES_128BITS); + + // Compute Checksum + mxc_aes_req_t aes_req; + aes_req.length = MXC_SYS_USN_CHECKSUM_LEN / 4; + aes_req.inputData = (uint32_t *)usn; + aes_req.resultData = (uint32_t *)check_csum; + aes_req.keySize = MXC_AES_128BITS; + aes_req.encryption = MXC_AES_ENCRYPT_EXT_KEY; + aes_req.callback = NULL; + + err = MXC_AES_Generic(&aes_req); + if (err) { + MXC_FLC_LockInfoBlock(MXC_INFO0_MEM_BASE); + return err; + } + + MXC_AES_Shutdown(); + + // Verify Checksum + if (check_csum[0] != checksum[1] || check_csum[1] != checksum[0]) { + MXC_FLC_LockInfoBlock(MXC_INFO0_MEM_BASE); + return E_INVALID; + } + } + + /* Add the info block checksum to the USN */ + usn[11] = ((infoblock[3] & 0x7F800000) >> 23); + usn[12] = ((infoblock[4] & 0x007F8000) >> 15); + + MXC_FLC_LockInfoBlock(MXC_INFO0_MEM_BASE); + + return err; +} + +/* ************************************************************************** */ +int MXC_SYS_GetRevision(void) +{ + return MXC_GCR->revision; +} + +/* ************************************************************************** */ +int MXC_SYS_IsClockEnabled(mxc_sys_periph_clock_t clock) +{ + /* The mxc_sys_periph_clock_t enum uses enum values that are the offset by 32 and 64 for the perckcn1 register. */ + if (clock > 63) { + clock -= 64; + return !(MXC_LPGCR->pclkdis & (0x1 << clock)); + } else if (clock > 31) { + clock -= 32; + return !(MXC_GCR->pclkdis1 & (0x1 << clock)); + } else { + return !(MXC_GCR->pclkdis0 & (0x1 << clock)); + } +} + +/* ************************************************************************** */ +void MXC_SYS_ClockDisable(mxc_sys_periph_clock_t clock) +{ + /* The mxc_sys_periph_clock_t enum uses enum values that are the offset by 32 and 64 for the perckcn1 register. */ + if (clock > 63) { + clock -= 64; + MXC_LPGCR->pclkdis |= (0x1 << clock); + } else if (clock > 31) { + clock -= 32; + MXC_GCR->pclkdis1 |= (0x1 << clock); + } else { + MXC_GCR->pclkdis0 |= (0x1 << clock); + } +} + +/* ************************************************************************** */ +void MXC_SYS_ClockEnable(mxc_sys_periph_clock_t clock) +{ + /* The mxc_sys_periph_clock_t enum uses enum values that are the offset by 32 and 64 for the perckcn1 register. */ + if (clock > 63) { + clock -= 64; + MXC_LPGCR->pclkdis &= ~(0x1 << clock); + } else if (clock > 31) { + clock -= 32; + MXC_GCR->pclkdis1 &= ~(0x1 << clock); + } else { + MXC_GCR->pclkdis0 &= ~(0x1 << clock); + } +} +/* ************************************************************************** */ +void MXC_SYS_RTCClockEnable() +{ + MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_ERTCO_EN; +} + +/* ************************************************************************** */ +int MXC_SYS_RTCClockDisable(void) +{ + /* Check that the RTC is not the system clock source */ + if ((MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_SEL) != MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO) { + MXC_GCR->clkctrl &= ~MXC_F_GCR_CLKCTRL_ERTCO_EN; + return E_NO_ERROR; + } else { + return E_BAD_STATE; + } +} + +#if TARGET_NUM == 32655 +/******************************************************************************/ +void MXC_SYS_RTCClockPowerDownEn(void) +{ + MXC_MCR->ctrl |= MXC_F_MCR_CTRL_32KOSC_EN; +} + +/******************************************************************************/ +void MXC_SYS_RTCClockPowerDownDis(void) +{ + MXC_MCR->ctrl &= ~MXC_F_MCR_CTRL_32KOSC_EN; +} +#endif //TARGET_NUM == 32655 + +/******************************************************************************/ +int MXC_SYS_ClockSourceEnable(mxc_sys_system_clock_t clock) +{ + switch (clock) { + case MXC_SYS_CLOCK_IPO: + MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_IPO_EN; + return MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_IPO_RDY); + break; + + case MXC_SYS_CLOCK_IBRO: + MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_IBRO_EN; + return MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_IBRO_RDY); + break; + + case MXC_SYS_CLOCK_EXTCLK: + // No "RDY" bit to monitor, so just configure the GPIO + return MXC_GPIO_Config(&gpio_cfg_extclk); + break; + + case MXC_SYS_CLOCK_INRO: + // The 80k clock is always enabled + return MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_INRO_RDY); + break; + + case MXC_SYS_CLOCK_ERFO: + MXC_GCR->btleldoctrl |= MXC_F_GCR_BTLELDOCTRL_LDOTXEN | MXC_F_GCR_BTLELDOCTRL_LDORXEN; + + /* Initialize kickstart circuit + Select Kick start circuit clock source- IPO/ISO + */ + MXC_FCR->erfoks = ((MXC_S_FCR_ERFOKS_KSCLKSEL_ISO) + /* Set Drive strengh - 0x1,0x2,0x3 */ + | ((0x1) << MXC_F_FCR_ERFOKS_KSERFODRIVER_POS) + /* Set kick count 1-127 */ + | (0x8) + /* Set double pulse length On/Off*/ + | (0 & MXC_F_FCR_ERFOKS_KSERFO2X) + /* Enable On/Off */ + | (MXC_F_FCR_ERFOKS_KSERFO_EN)); + + /* Enable ERFO */ + MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_ERFO_EN; + return MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_ERFO_RDY); + break; + + case MXC_SYS_CLOCK_ERTCO: + MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_ERTCO_EN; + return MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_ERTCO_RDY); + break; + + default: + return E_BAD_PARAM; + break; + } +} + +/******************************************************************************/ +int MXC_SYS_ClockSourceDisable(mxc_sys_system_clock_t clock) +{ + uint32_t current_clock; + + current_clock = MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_SEL; + + // Don't turn off the clock we're running on + if (clock == current_clock) { + return E_BAD_PARAM; + } + + switch (clock) { + case MXC_SYS_CLOCK_IPO: + MXC_GCR->clkctrl &= ~MXC_F_GCR_CLKCTRL_IPO_EN; + break; + + case MXC_SYS_CLOCK_IBRO: + MXC_GCR->clkctrl &= ~MXC_F_GCR_CLKCTRL_IBRO_EN; + break; + + case MXC_SYS_CLOCK_EXTCLK: + /* + There's not a great way to disable the external clock. + Deinitializing the GPIO here may have unintended consequences + for application code. + Selecting a different system clock source is sufficient + to "disable" the EXT_CLK source. + */ + break; + + case MXC_SYS_CLOCK_INRO: + // The 80k clock is always enabled + break; + + case MXC_SYS_CLOCK_ERFO: + MXC_GCR->clkctrl &= ~MXC_F_GCR_CLKCTRL_ERFO_EN; + break; + + case MXC_SYS_CLOCK_ERTCO: + MXC_GCR->clkctrl &= ~MXC_F_GCR_CLKCTRL_ERTCO_EN; + break; + + default: + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +/* ************************************************************************** */ +int MXC_SYS_Clock_Timeout(uint32_t ready) +{ +#ifdef __riscv + // The current RISC-V implementation is to block until the clock is ready. + // We do not have access to a system tick in the RV core. + while (!(MXC_GCR->clkctrl & ready)) {} + return E_NO_ERROR; +#else +#ifndef BOARD_ME17_TESTER + // Start timeout, wait for ready + MXC_DelayAsync(MXC_SYS_CLOCK_TIMEOUT, NULL); + + do { + if (MXC_GCR->clkctrl & ready) { + MXC_DelayAbort(); + return E_NO_ERROR; + } + } while (MXC_DelayCheck() == E_BUSY); + + return E_TIME_OUT; +#else + + return E_NO_ERROR; +#endif + +#endif // __riscv +} +/* ************************************************************************** */ +int MXC_SYS_Clock_Select(mxc_sys_system_clock_t clock) +{ + uint32_t current_clock; + int err = E_NO_ERROR; + + // Save the current system clock + current_clock = MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_SEL; + + switch (clock) { + case MXC_SYS_CLOCK_ISO: + + // Enable ISO clock + if (!(MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_ISO_EN)) { + MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_ISO_EN; + + // Check if ISO clock is ready + if (MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_ISO_RDY) != E_NO_ERROR) { + return E_TIME_OUT; + } + } + + // Set ISO clock as System Clock + MXC_SETFIELD(MXC_GCR->clkctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL, + MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ISO); + + break; + case MXC_SYS_CLOCK_IPO: + + // Enable IPO clock + if (!(MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_IPO_EN)) { + MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_IPO_EN; + + // Check if IPO clock is ready + if (MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_IPO_RDY) != E_NO_ERROR) { + return E_TIME_OUT; + } + } + + // Set IPO clock as System Clock + MXC_SETFIELD(MXC_GCR->clkctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL, + MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO); + + break; + + case MXC_SYS_CLOCK_IBRO: + + // Enable IBRO clock + if (!(MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_IBRO_EN)) { + MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_IBRO_EN; + + // Check if IBRO clock is ready + if (MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_IBRO_RDY) != E_NO_ERROR) { + return E_TIME_OUT; + } + } + + // Set IBRO clock as System Clock + MXC_SETFIELD(MXC_GCR->clkctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL, + MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IBRO); + + break; + + case MXC_SYS_CLOCK_EXTCLK: + /* + There's not "EXT_CLK RDY" bit for the ME17, so we'll + blindly enable (configure GPIO) the external clock every time. + */ + err = MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_EXTCLK); + if (err) + return err; + + // Set EXT clock as System Clock + MXC_SETFIELD(MXC_GCR->clkctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL, + MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK); + + break; + + case MXC_SYS_CLOCK_ERFO: + + // Enable ERFO clock + if (!(MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_ERFO_EN)) { + MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_ERFO_EN; + + // Check if ERFO clock is ready + if (MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_ERFO_RDY) != E_NO_ERROR) { + return E_TIME_OUT; + } + } + + // Set ERFO clock as System Clock + MXC_SETFIELD(MXC_GCR->clkctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL, + MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERFO); + + break; + + case MXC_SYS_CLOCK_INRO: + // Set INRO clock as System Clock + MXC_SETFIELD(MXC_GCR->clkctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL, + MXC_S_GCR_CLKCTRL_SYSCLK_SEL_INRO); + + break; + + case MXC_SYS_CLOCK_ERTCO: + + // Enable ERTCO clock + if (!(MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_ERTCO_EN)) { + MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_ERTCO_EN; + + // Check if ERTCO clock is ready + if (MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_ERTCO_RDY) != E_NO_ERROR) { + return E_TIME_OUT; + } + } + + // Set ERTCO clock as System Clock + MXC_SETFIELD(MXC_GCR->clkctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL, + MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO); + + break; + + default: + return E_BAD_PARAM; + } + + // Wait for system clock to be ready + if (MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_SYSCLK_RDY) != E_NO_ERROR) { + // Restore the old system clock if timeout + MXC_SETFIELD(MXC_GCR->clkctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL, current_clock); + + return E_TIME_OUT; + } + + // Update the system core clock + SystemCoreClockUpdate(); + + return E_NO_ERROR; +} + +/* ************************************************************************** */ +void MXC_SYS_SetClockDiv(mxc_sys_system_clock_div_t div) +{ + /* Return if this setting is already current */ + if (div == MXC_SYS_GetClockDiv()) { + return; + } + + MXC_SETFIELD(MXC_GCR->clkctrl, MXC_F_GCR_CLKCTRL_SYSCLK_DIV, div); + + SystemCoreClockUpdate(); +} + +/* ************************************************************************** */ +mxc_sys_system_clock_div_t MXC_SYS_GetClockDiv(void) +{ + return (MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_DIV); +} + +/* ************************************************************************** */ +void MXC_SYS_Reset_Periph(mxc_sys_reset_t reset) +{ + /* The mxc_sys_reset_t enum uses enum values that are the offset by 32 and 64 for the rst register. */ + if (reset > 63) { + reset -= 64; + MXC_LPGCR->rst = (0x1 << reset); + while (MXC_LPGCR->rst & (0x1 << reset)) {} + } else if (reset > 31) { + reset -= 32; + MXC_GCR->rst1 = (0x1 << reset); + while (MXC_GCR->rst1 & (0x1 << reset)) {} + } else { + MXC_GCR->rst0 = (0x1 << reset); + while (MXC_GCR->rst0 & (0x1 << reset)) {} + } +} + +/* ************************************************************************** */ +void MXC_SYS_RISCVRun(void) +{ + /* Disable the the RSCV */ + MXC_GCR->pclkdis1 |= MXC_F_GCR_PCLKDIS1_CPU1; + + /* Set the interrupt vector base address */ + MXC_FCR->urvbootaddr = (uint32_t)&_binary_riscv_bin_start; + + /* Power up the RSCV */ + MXC_GCR->pclkdis1 &= ~(MXC_F_GCR_PCLKDIS1_CPU1); + + /* CPU1 reset */ + MXC_GCR->rst1 |= MXC_F_GCR_RST1_CPU1; +} + +/* ************************************************************************** */ +void MXC_SYS_RISCVShutdown(void) +{ + /* Disable the the RSCV */ + MXC_GCR->pclkdis1 |= MXC_F_GCR_PCLKDIS1_CPU1; +} + +/* ************************************************************************** */ +uint32_t MXC_SYS_RiscVClockRate(void) +{ + // If in LPM mode and the PCLK is selected as the RV32 clock source, + if (((MXC_GCR->pm & MXC_F_GCR_PM_MODE) == MXC_S_GCR_PM_MODE_LPM) && + (MXC_PWRSEQ->lpcn & MXC_F_PWRSEQ_LPCN_LPMCLKSEL)) { + return ISO_FREQ; + } else { + return PeripheralClock; + } +} + +/* ************************************************************************** */ +int MXC_SYS_LockDAP_Permanent(void) +{ +#ifdef DEBUG + // Locking the DAP is not supported while in DEBUG. + // To use this function, build for release ("make release") + // or set DEBUG = 0 + // (see https://analogdevicesinc.github.io/msdk/USERGUIDE/#build-tables) + return E_NOT_SUPPORTED; +#else + int err; + uint32_t info_blk_addr; + uint32_t lock_sequence[4]; + + // Infoblock address to write lock sequence to + info_blk_addr = MXC_INFO_MEM_BASE + INFOBLOCK_DAP_LOCK_OFFSET; + + // Set lock sequence + lock_sequence[0] = DAP_LOCK_SEQUENCE_01; + lock_sequence[1] = DAP_LOCK_SEQUENCE_01; + lock_sequence[2] = DAP_LOCK_SEQUENCE_23; + lock_sequence[3] = DAP_LOCK_SEQUENCE_23; + + // Initialize FLC + MXC_FLC_Init(); + + // Unlock infoblock + MXC_FLC_UnlockInfoBlock(info_blk_addr); + + // Write DAP lock sequence to infoblock + err = MXC_FLC_Write128(info_blk_addr, lock_sequence); + + // Re-lock infoblock + MXC_FLC_LockInfoBlock(info_blk_addr); + + return err; +#endif +} + +/**@} end of mxc_sys */ diff --git a/Libraries/PeriphDrivers/Source/TMR/tmr_me30.c b/Libraries/PeriphDrivers/Source/TMR/tmr_me30.c new file mode 100644 index 00000000000..8c4404d6b6a --- /dev/null +++ b/Libraries/PeriphDrivers/Source/TMR/tmr_me30.c @@ -0,0 +1,388 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#include "tmr.h" +#include "tmr_revb.h" +#include "tmr_common.h" +#include "lpgcr_regs.h" +#include "stdbool.h" + +int MXC_TMR_Init(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg, bool init_pins) +{ + int tmr_id = MXC_TMR_GET_IDX(tmr); + uint8_t clockSource = MXC_TMR_CLK0; + + if (cfg == NULL) { + return E_NULL_PTR; + } + + MXC_ASSERT(tmr_id >= 0); + + switch (cfg->clock) { + case MXC_TMR_ISO_CLK: + if (tmr_id > 3) { // Timers 4-5 do not support this clock source + return E_NOT_SUPPORTED; + } + + clockSource = MXC_TMR_CLK1; + MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_ISO); + MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, ISO_FREQ); + break; + + case MXC_TMR_IBRO_CLK: + if (tmr_id > 3) { // Timers 4-5 do not support this clock source + return E_NOT_SUPPORTED; + } + + clockSource = MXC_TMR_CLK2; + MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_IBRO); + MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, IBRO_FREQ); + break; + + case MXC_TMR_IBRO_DIV8_CLK: + if (tmr_id != 5) { // Only timer 5 supports this clock source + return E_NOT_SUPPORTED; + } + + clockSource = MXC_TMR_CLK1; + MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_IBRO); + MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, (IBRO_FREQ / 8)); + break; + +#if (TARGET_NUM != 32680) + case MXC_TMR_ERTCO_CLK: + if (tmr_id == 4) { + clockSource = MXC_TMR_CLK1; + } else if (tmr_id < 4) { + clockSource = MXC_TMR_CLK3; + } else { // Timers 5 do not support this clock source + return E_NOT_SUPPORTED; + } + + MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_ERTCO); + MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, ERTCO_FREQ); + break; +#endif + + case MXC_TMR_INRO_CLK: + if (tmr_id < 4) { // Timers 0-3 do not support this clock source + return E_NOT_SUPPORTED; + } + + clockSource = MXC_TMR_CLK2; + MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_INRO); + MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, INRO_FREQ); + break; + + default: + MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, PeripheralClock); + break; + } + +#ifndef MSDK_NO_GPIO_CLK_INIT + //enable peripheral clock and configure gpio pins + switch (tmr_id) { + case 0: + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TMR0); + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR0); + + if (init_pins) { + if (cfg->bitMode != MXC_TMR_BIT_MODE_16B) { + MXC_GPIO_Config(&gpio_cfg_tmr0); + } else { + MXC_GPIO_Config(&gpio_cfg_tmr0b); + } + } + + break; + + case 1: + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TMR1); + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR1); + + if (init_pins) { + if (cfg->bitMode != MXC_TMR_BIT_MODE_16B) { + MXC_GPIO_Config(&gpio_cfg_tmr1); + } else { + MXC_GPIO_Config(&gpio_cfg_tmr1b); + } + } + + break; + + case 2: + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TMR2); + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR2); + + if (init_pins) { + if (cfg->bitMode != MXC_TMR_BIT_MODE_16B) { + MXC_GPIO_Config(&gpio_cfg_tmr2); + } else { + MXC_GPIO_Config(&gpio_cfg_tmr2b); + } + } + + break; + + case 3: + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TMR3); + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR3); + + if (init_pins) { + if (cfg->bitMode != MXC_TMR_BIT_MODE_16B) { + MXC_GPIO_Config(&gpio_cfg_tmr3); + } else { + MXC_GPIO_Config(&gpio_cfg_tmr3b); + } + } + + break; + + case 4: + MXC_SYS_Reset_Periph(MXC_SYS_RESET_TMR4); + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR4); + break; + + case 5: + MXC_SYS_Reset_Periph(MXC_SYS_RESET_TMR5); + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR5); + break; + } +#else + (void)init_pins; +#endif + + return MXC_TMR_RevB_Init((mxc_tmr_revb_regs_t *)tmr, cfg, clockSource); +} + +void MXC_TMR_Shutdown(mxc_tmr_regs_t *tmr) +{ + MXC_ASSERT(MXC_TMR_GET_IDX(tmr) >= 0); + + MXC_TMR_RevB_Shutdown((mxc_tmr_revb_regs_t *)tmr); + + // System settigns + //diasble peripheral clock + if (tmr == MXC_TMR0) { + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR0); + } + + if (tmr == MXC_TMR1) { + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR1); + } + + if (tmr == MXC_TMR2) { + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR2); + } + + if (tmr == MXC_TMR3) { + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR3); + } + + if (tmr == MXC_TMR4) { + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR4); + } + + if (tmr == MXC_TMR5) { + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TMR5); + } +} + +void MXC_TMR_Start(mxc_tmr_regs_t *tmr) +{ + MXC_TMR_RevB_Start((mxc_tmr_revb_regs_t *)tmr); +} + +void MXC_TMR_Stop(mxc_tmr_regs_t *tmr) +{ + MXC_TMR_RevB_Stop((mxc_tmr_revb_regs_t *)tmr); +} + +int MXC_TMR_SetPWM(mxc_tmr_regs_t *tmr, uint32_t pwm) +{ + return MXC_TMR_RevB_SetPWM((mxc_tmr_revb_regs_t *)tmr, pwm); +} + +uint32_t MXC_TMR_GetCompare(mxc_tmr_regs_t *tmr) +{ + return MXC_TMR_RevB_GetCompare((mxc_tmr_revb_regs_t *)tmr); +} + +uint32_t MXC_TMR_GetCapture(mxc_tmr_regs_t *tmr) +{ + return MXC_TMR_RevB_GetCapture((mxc_tmr_revb_regs_t *)tmr); +} + +uint32_t MXC_TMR_GetPeriod(mxc_tmr_regs_t *tmr, mxc_tmr_clock_t clock, uint32_t prescalar, + uint32_t frequency) +{ + uint32_t clockFrequency = PeripheralClock; + int tmr_id = MXC_TMR_GET_IDX(tmr); + + MXC_ASSERT(tmr_id >= 0); + + if (tmr_id > 3) { + switch (clock) { + case MXC_TMR_APB_CLK: + clockFrequency = IBRO_FREQ; + break; + +#if (TARGET_NUM != 32680) + case MXC_TMR_ERTCO_CLK: + clockFrequency = ERTCO_FREQ; + break; +#endif + + case MXC_TMR_INRO_CLK: + clockFrequency = INRO_FREQ; + break; + + case MXC_TMR_IBRO_DIV8_CLK: + clockFrequency = IBRO_FREQ / 8; + break; + + default: + break; + } + } else { + switch (clock) { + case MXC_TMR_APB_CLK: + clockFrequency = PeripheralClock; + break; + + case MXC_TMR_ISO_CLK: + clockFrequency = ISO_FREQ; + break; + + case MXC_TMR_IBRO_CLK: + clockFrequency = IBRO_FREQ; + break; + +#if (TARGET_NUM != 32680) + case MXC_TMR_ERTCO_CLK: + clockFrequency = ERTCO_FREQ; + break; +#endif + + default: + break; + } + } + + return MXC_TMR_RevB_GetPeriod((mxc_tmr_revb_regs_t *)tmr, clockFrequency, prescalar, frequency); +} + +uint32_t MXC_TMR_GetCount(mxc_tmr_regs_t *tmr) +{ + return MXC_TMR_RevB_GetCount((mxc_tmr_revb_regs_t *)tmr); +} + +void MXC_TMR_ClearFlags(mxc_tmr_regs_t *tmr) +{ + MXC_TMR_RevB_ClearFlags((mxc_tmr_revb_regs_t *)tmr); +} + +uint32_t MXC_TMR_GetFlags(mxc_tmr_regs_t *tmr) +{ + return MXC_TMR_RevB_GetFlags((mxc_tmr_revb_regs_t *)tmr); +} + +void MXC_TMR_EnableInt(mxc_tmr_regs_t *tmr) +{ + MXC_TMR_RevB_EnableInt((mxc_tmr_revb_regs_t *)tmr); +} + +void MXC_TMR_DisableInt(mxc_tmr_regs_t *tmr) +{ + MXC_TMR_RevB_DisableInt((mxc_tmr_revb_regs_t *)tmr); +} + +void MXC_TMR_EnableWakeup(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg) +{ + MXC_TMR_RevB_EnableWakeup((mxc_tmr_revb_regs_t *)tmr, cfg); +} + +void MXC_TMR_DisableWakeup(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg) +{ + MXC_TMR_RevB_DisableWakeup((mxc_tmr_revb_regs_t *)tmr, cfg); +} + +void MXC_TMR_SetCompare(mxc_tmr_regs_t *tmr, uint32_t cmp_cnt) +{ + MXC_TMR_RevB_SetCompare((mxc_tmr_revb_regs_t *)tmr, cmp_cnt); +} + +void MXC_TMR_SetCount(mxc_tmr_regs_t *tmr, uint32_t cnt) +{ + MXC_TMR_RevB_SetCount((mxc_tmr_revb_regs_t *)tmr, cnt); +} + +void MXC_TMR_Delay(mxc_tmr_regs_t *tmr, uint32_t us) +{ + MXC_TMR_Common_Delay(tmr, us); +} + +void MXC_TMR_TO_Start(mxc_tmr_regs_t *tmr, uint32_t us) +{ + MXC_TMR_RevB_TO_Start((mxc_tmr_revb_regs_t *)tmr, us); +} + +int MXC_TMR_TO_Check(mxc_tmr_regs_t *tmr) +{ + return MXC_TMR_Common_TO_Check(tmr); +} + +void MXC_TMR_TO_Stop(mxc_tmr_regs_t *tmr) +{ + MXC_TMR_Common_TO_Stop(tmr); +} + +void MXC_TMR_TO_Clear(mxc_tmr_regs_t *tmr) +{ + MXC_TMR_Common_TO_Clear(tmr); +} + +unsigned int MXC_TMR_TO_Elapsed(mxc_tmr_regs_t *tmr) +{ + return MXC_TMR_Common_TO_Elapsed(tmr); +} + +unsigned int MXC_TMR_TO_Remaining(mxc_tmr_regs_t *tmr) +{ + return MXC_TMR_Common_TO_Remaining(tmr); +} + +void MXC_TMR_SW_Start(mxc_tmr_regs_t *tmr) +{ + MXC_TMR_Common_SW_Start(tmr); +} + +unsigned int MXC_TMR_SW_Stop(mxc_tmr_regs_t *tmr) +{ + return MXC_TMR_Common_SW_Stop(tmr); +} + +int MXC_TMR_GetTime(mxc_tmr_regs_t *tmr, uint32_t ticks, uint32_t *time, mxc_tmr_unit_t *units) +{ + return MXC_TMR_RevB_GetTime((mxc_tmr_revb_regs_t *)tmr, ticks, time, units); +} + +int MXC_TMR_GetTicks(mxc_tmr_regs_t *tmr, uint32_t time, mxc_tmr_unit_t units, uint32_t *ticks) +{ + return MXC_TMR_RevB_GetTicks((mxc_tmr_revb_regs_t *)tmr, time, units, ticks); +} diff --git a/Libraries/PeriphDrivers/Source/TRNG/trng_me30.c b/Libraries/PeriphDrivers/Source/TRNG/trng_me30.c new file mode 100644 index 00000000000..0875de46e2d --- /dev/null +++ b/Libraries/PeriphDrivers/Source/TRNG/trng_me30.c @@ -0,0 +1,93 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#include "mxc_device.h" +#include "mxc_errors.h" +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "trng_revb.h" +#include "trng.h" + +/* ************************************************************************* */ +/* Global Control/Configuration functions */ +/* ************************************************************************* */ + +/********************************************************/ + +int MXC_TRNG_Init(void) +{ +#ifndef MSDK_NO_GPIO_CLK_INIT + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TRNG); +#endif + + MXC_TRNG_RevB_Init(); + + return E_NO_ERROR; +} + +void MXC_TRNG_EnableInt(void) +{ + MXC_TRNG_RevB_EnableInt((mxc_trng_revb_regs_t *)MXC_TRNG); +} + +void MXC_TRNG_DisableInt(void) +{ + MXC_TRNG_RevB_DisableInt((mxc_trng_revb_regs_t *)MXC_TRNG); +} + +int MXC_TRNG_Shutdown(void) +{ + int error = MXC_TRNG_RevB_Shutdown(); + + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_TRNG); + + return error; +} + +void MXC_TRNG_Handler(void) +{ + MXC_TRNG_RevB_Handler((mxc_trng_revb_regs_t *)MXC_TRNG); +} + +/* ************************************************************************* */ +/* True Random Number Generator (TRNG) functions */ +/* ************************************************************************* */ + +int MXC_TRNG_RandomInt(void) +{ + return MXC_TRNG_RevB_RandomInt((mxc_trng_revb_regs_t *)MXC_TRNG); +} + +int MXC_TRNG_Random(uint8_t *data, uint32_t len) +{ + return MXC_TRNG_RevB_Random(data, len); +} + +void MXC_TRNG_RandomAsync(uint8_t *data, uint32_t len, mxc_trng_complete_t callback) +{ + MXC_TRNG_RevB_RandomAsync((mxc_trng_revb_regs_t *)MXC_TRNG, data, len, callback); +} + +int MXC_TRNG_HealthTest(void) +{ + if ((MXC_SYS_GetRevision() & 0xF0) == 0xA0) { // ME17 Rev. A does not support health tests. + return E_NOT_SUPPORTED; + } + + return MXC_TRNG_RevB_HealthTest((mxc_trng_revb_regs_t *)MXC_TRNG); +} diff --git a/Libraries/PeriphDrivers/Source/UART/uart_me30.c b/Libraries/PeriphDrivers/Source/UART/uart_me30.c new file mode 100644 index 00000000000..32b722c786c --- /dev/null +++ b/Libraries/PeriphDrivers/Source/UART/uart_me30.c @@ -0,0 +1,528 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#include "uart.h" +#include "mxc_device.h" +#include "mxc_pins.h" +#include "mxc_assert.h" +#include "uart_revb.h" +#include "uart_common.h" +#include "lpgcr_regs.h" +#include "dma.h" + +void MXC_UART_DMACallback(int ch, int error) +{ + MXC_UART_RevB_DMACallback(ch, error); +} + +int MXC_UART_AsyncCallback(mxc_uart_regs_t *uart, int retVal) +{ + return MXC_UART_RevB_AsyncCallback((mxc_uart_revb_regs_t *)uart, retVal); +} + +int MXC_UART_AsyncStop(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevB_AsyncStop((mxc_uart_revb_regs_t *)uart); +} + +int MXC_UART_Init(mxc_uart_regs_t *uart, unsigned int baud, mxc_uart_clock_t clock) +{ +#ifndef MSDK_NO_GPIO_CLK_INIT + int retval; + + retval = MXC_UART_Shutdown(uart); + + if (retval) { + return retval; + } + + switch (clock) { +#if TARGET_NUM != 32680 + case MXC_UART_ERTCO_CLK: + MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_ERTCO); + break; +#endif + + case MXC_UART_IBRO_CLK: + MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_IBRO); + break; + + default: + break; + } + + switch (MXC_UART_GET_IDX(uart)) { + case 0: + MXC_GPIO_Config(&gpio_cfg_uart0); + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_UART0); + break; + + case 1: + MXC_GPIO_Config(&gpio_cfg_uart1); + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_UART1); + break; + + case 2: + MXC_GPIO_Config(&gpio_cfg_uart2); + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_UART2); + break; + + case 3: + MXC_GPIO_Config(&gpio_cfg_uart3); + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_UART3); + break; + + default: + return E_BAD_PARAM; + } +#endif // MSDK_NO_GPIO_CLK_INIT + + return MXC_UART_RevB_Init((mxc_uart_revb_regs_t *)uart, baud, clock); +} + +int MXC_UART_Shutdown(mxc_uart_regs_t *uart) +{ + switch (MXC_UART_GET_IDX(uart)) { + case 0: + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_UART0); + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_UART0); + break; + + case 1: + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_UART1); + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_UART1); + break; + + case 2: + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_UART2); + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_UART2); + break; + + case 3: + MXC_SYS_Reset_Periph(MXC_SYS_RESET_UART3); + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_UART3); + break; + + default: + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +int MXC_UART_ReadyForSleep(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevB_ReadyForSleep((mxc_uart_revb_regs_t *)uart); +} + +int MXC_UART_SetFrequency(mxc_uart_regs_t *uart, unsigned int baud, mxc_uart_clock_t clock) +{ + int freq; + unsigned mod = 0; + unsigned clkDiv = 0; + + if (MXC_UART_GET_IDX(uart) < 0) { + return E_BAD_PARAM; + } + + // check if the uart is LPUART + if (uart == MXC_UART3) { + // OSR default value + uart->osr = 5; + + switch (clock) { + case MXC_UART_IBRO_CLK: + uart->ctrl |= MXC_S_UART_CTRL_BCLKSRC_PERIPHERAL_CLOCK; + clkDiv = ((IBRO_FREQ) / baud); + mod = ((IBRO_FREQ) % baud); + break; + + case MXC_UART_ERTCO_CLK: + // Only supports up to 9600 baud with ERTCO clock. + if (baud > 9600) { + return E_NOT_SUPPORTED; + } + + uart->ctrl |= MXC_S_UART_CTRL_BCLKSRC_EXTERNAL_CLOCK; + uart->ctrl |= MXC_F_UART_CTRL_FDM; + if (baud == 9600) { + clkDiv = 7; + mod = 0; + } else { + clkDiv = ((ERTCO_FREQ * 2) / baud); + mod = ((ERTCO_FREQ * 2) % baud); + } + + if (baud > 2400) { + uart->osr = 0; + } else { + uart->osr = 1; + } + break; + + default: + return E_BAD_PARAM; + } + + if (!clkDiv || mod > (baud / 2)) { + clkDiv++; + } + uart->clkdiv = clkDiv; + + freq = MXC_UART_GetFrequency(uart); + } else { + if (clock == MXC_UART_ERTCO_CLK) { + return E_BAD_PARAM; + } + + freq = MXC_UART_RevB_SetFrequency((mxc_uart_revb_regs_t *)uart, baud, clock); + } + + if (freq > 0) { + // Enable baud clock and wait for it to become ready. + uart->ctrl |= MXC_F_UART_CTRL_BCLKEN; + while (((uart->ctrl & MXC_F_UART_CTRL_BCLKRDY) >> MXC_F_UART_CTRL_BCLKRDY_POS) == 0) {} + } + + return freq; +} + +int MXC_UART_GetFrequency(mxc_uart_regs_t *uart) +{ + int periphClock = 0; + + if (MXC_UART_GET_IDX(uart) < 0) { + return E_BAD_PARAM; + } + + // check if UART is LP UART + if (uart == MXC_UART3) { + if ((uart->ctrl & MXC_F_UART_CTRL_BCLKSRC) == + MXC_S_UART_REVB_CTRL_BCLKSRC_PERIPHERAL_CLOCK) { + periphClock = IBRO_FREQ; + } else if ((uart->ctrl & MXC_F_UART_CTRL_BCLKSRC) == + MXC_S_UART_REVB_CTRL_BCLKSRC_EXTERNAL_CLOCK) { + periphClock = ERTCO_FREQ * 2; + } else { + return E_NOT_SUPPORTED; + } + return (periphClock / uart->clkdiv); + } else { + return MXC_UART_RevB_GetFrequency((mxc_uart_revb_regs_t *)uart); + } +} + +int MXC_UART_SetDataSize(mxc_uart_regs_t *uart, int dataSize) +{ + return MXC_UART_RevB_SetDataSize((mxc_uart_revb_regs_t *)uart, dataSize); +} + +int MXC_UART_SetStopBits(mxc_uart_regs_t *uart, mxc_uart_stop_t stopBits) +{ + return MXC_UART_RevB_SetStopBits((mxc_uart_revb_regs_t *)uart, stopBits); +} + +int MXC_UART_SetParity(mxc_uart_regs_t *uart, mxc_uart_parity_t parity) +{ + return MXC_UART_RevB_SetParity((mxc_uart_revb_regs_t *)uart, parity); +} + +int MXC_UART_SetFlowCtrl(mxc_uart_regs_t *uart, mxc_uart_flow_t flowCtrl, int rtsThreshold) +{ + if (flowCtrl == MXC_UART_FLOW_EN) { + switch (MXC_UART_GET_IDX(uart)) { + case 0: + MXC_GPIO_Config(&gpio_cfg_uart0_flow); + break; + + case 1: + MXC_GPIO_Config(&gpio_cfg_uart1_flow); + break; + + case 2: + MXC_GPIO_Config(&gpio_cfg_uart2_flow); + break; + + default: + return E_BAD_PARAM; + } + } else { + switch (MXC_UART_GET_IDX(uart)) { + case 0: + MXC_GPIO_Config(&gpio_cfg_uart0_flow_disable); + break; + + case 1: + MXC_GPIO_Config(&gpio_cfg_uart1_flow_disable); + break; + + case 2: + MXC_GPIO_Config(&gpio_cfg_uart2_flow_disable); + break; + + default: + return E_BAD_PARAM; + } + } + + return MXC_UART_RevB_SetFlowCtrl((mxc_uart_revb_regs_t *)uart, flowCtrl, rtsThreshold); +} + +int MXC_UART_SetClockSource(mxc_uart_regs_t *uart, mxc_uart_clock_t clock) +{ + return MXC_UART_RevB_SetClockSource((mxc_uart_revb_regs_t *)uart, clock); +} + +int MXC_UART_GetActive(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevB_GetActive((mxc_uart_revb_regs_t *)uart); +} + +int MXC_UART_AbortTransmission(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevB_AbortTransmission((mxc_uart_revb_regs_t *)uart); +} + +int MXC_UART_ReadCharacterRaw(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevB_ReadCharacterRaw((mxc_uart_revb_regs_t *)uart); +} + +int MXC_UART_WriteCharacterRaw(mxc_uart_regs_t *uart, uint8_t character) +{ + return MXC_UART_RevB_WriteCharacterRaw((mxc_uart_revb_regs_t *)uart, character); +} + +int MXC_UART_ReadCharacter(mxc_uart_regs_t *uart) +{ + return MXC_UART_Common_ReadCharacter(uart); +} + +int MXC_UART_WriteCharacter(mxc_uart_regs_t *uart, uint8_t character) +{ + return MXC_UART_Common_WriteCharacter(uart, character); +} + +int MXC_UART_Read(mxc_uart_regs_t *uart, uint8_t *buffer, int *len) +{ + return MXC_UART_RevB_Read((mxc_uart_revb_regs_t *)uart, buffer, len); +} + +int MXC_UART_Write(mxc_uart_regs_t *uart, const uint8_t *byte, int *len) +{ + return MXC_UART_RevB_Write((mxc_uart_revb_regs_t *)uart, byte, len); +} + +unsigned int MXC_UART_ReadRXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len) +{ + return MXC_UART_RevB_ReadRXFIFO((mxc_uart_revb_regs_t *)uart, bytes, len); +} + +int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len, + mxc_uart_dma_complete_cb_t callback) +{ + mxc_dma_config_t config; + + int uart_num = MXC_UART_GET_IDX(uart); + + switch (uart_num) { + case 0: + config.reqsel = MXC_DMA_REQUEST_UART0RX; + break; + + case 1: + config.reqsel = MXC_DMA_REQUEST_UART1RX; + break; + + case 2: + config.reqsel = MXC_DMA_REQUEST_UART2RX; + break; + + case 3: + config.reqsel = MXC_DMA_REQUEST_UART3RX; + break; + + default: + return E_BAD_PARAM; + break; + } + + return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); +} + +unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevB_GetRXFIFOAvailable((mxc_uart_revb_regs_t *)uart); +} + +unsigned int MXC_UART_WriteTXFIFO(mxc_uart_regs_t *uart, const unsigned char *bytes, + unsigned int len) +{ + return MXC_UART_RevB_WriteTXFIFO((mxc_uart_revb_regs_t *)uart, bytes, len); +} + +int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, const unsigned char *bytes, unsigned int len, + mxc_uart_dma_complete_cb_t callback) +{ + mxc_dma_config_t config; + + int uart_num = MXC_UART_GET_IDX(uart); + switch (uart_num) { + case 0: + config.reqsel = MXC_DMA_REQUEST_UART0TX; + break; + + case 1: + config.reqsel = MXC_DMA_REQUEST_UART1TX; + break; + + case 2: + config.reqsel = MXC_DMA_REQUEST_UART2TX; + break; + + case 3: + config.reqsel = MXC_DMA_REQUEST_UART3TX; + break; + + default: + return E_BAD_PARAM; + break; + } + + return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); +} + +unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevB_GetTXFIFOAvailable((mxc_uart_revb_regs_t *)uart); +} + +int MXC_UART_ClearRXFIFO(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevB_ClearRXFIFO((mxc_uart_revb_regs_t *)uart); +} + +int MXC_UART_ClearTXFIFO(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevB_ClearTXFIFO((mxc_uart_revb_regs_t *)uart); +} + +int MXC_UART_SetRXThreshold(mxc_uart_regs_t *uart, unsigned int numBytes) +{ + return MXC_UART_RevB_SetRXThreshold((mxc_uart_revb_regs_t *)uart, numBytes); +} + +unsigned int MXC_UART_GetRXThreshold(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevB_GetRXThreshold((mxc_uart_revb_regs_t *)uart); +} + +int MXC_UART_SetTXThreshold(mxc_uart_regs_t *uart, unsigned int numBytes) +{ + return E_NOT_SUPPORTED; +} + +unsigned int MXC_UART_GetTXThreshold(mxc_uart_regs_t *uart) +{ + return E_NOT_SUPPORTED; +} + +unsigned int MXC_UART_GetFlags(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevB_GetFlags((mxc_uart_revb_regs_t *)uart); +} + +int MXC_UART_ClearFlags(mxc_uart_regs_t *uart, unsigned int flags) +{ + return MXC_UART_RevB_ClearFlags((mxc_uart_revb_regs_t *)uart, flags); +} + +int MXC_UART_EnableInt(mxc_uart_regs_t *uart, unsigned int intEn) +{ + return MXC_UART_RevB_EnableInt((mxc_uart_revb_regs_t *)uart, intEn); +} + +int MXC_UART_DisableInt(mxc_uart_regs_t *uart, unsigned int intDis) +{ + return MXC_UART_RevB_DisableInt((mxc_uart_revb_regs_t *)uart, intDis); +} + +unsigned int MXC_UART_GetStatus(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevB_GetStatus((mxc_uart_revb_regs_t *)uart); +} + +int MXC_UART_Transaction(mxc_uart_req_t *req) +{ + return MXC_UART_RevB_Transaction((mxc_uart_revb_req_t *)req); +} + +int MXC_UART_TransactionAsync(mxc_uart_req_t *req) +{ + return MXC_UART_RevB_TransactionAsync((mxc_uart_revb_req_t *)req); +} + +int MXC_UART_TransactionDMA(mxc_uart_req_t *req) +{ + return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req); +} + +int MXC_UART_AbortAsync(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevB_AbortAsync((mxc_uart_revb_regs_t *)uart); +} + +int MXC_UART_AsyncHandler(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevB_AsyncHandler((mxc_uart_revb_regs_t *)uart); +} + +uint32_t MXC_UART_GetAsyncTXCount(mxc_uart_req_t *req) +{ + return req->txCnt; +} + +uint32_t MXC_UART_GetAsyncRXCount(mxc_uart_req_t *req) +{ + return req->rxCnt; +} + +int MXC_UART_SetAutoDMAHandlers(mxc_uart_regs_t *uart, bool enable) +{ + return MXC_UART_RevB_SetAutoDMAHandlers((mxc_uart_revb_regs_t *)uart, enable); +} + +int MXC_UART_SetTXDMAChannel(mxc_uart_regs_t *uart, unsigned int channel) +{ + return MXC_UART_RevB_SetTXDMAChannel((mxc_uart_revb_regs_t *)uart, channel); +} + +int MXC_UART_GetTXDMAChannel(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevB_GetTXDMAChannel((mxc_uart_revb_regs_t *)uart); +} + +int MXC_UART_SetRXDMAChannel(mxc_uart_regs_t *uart, unsigned int channel) +{ + return MXC_UART_RevB_SetRXDMAChannel((mxc_uart_revb_regs_t *)uart, channel); +} + +int MXC_UART_GetRXDMAChannel(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevB_GetTXDMAChannel((mxc_uart_revb_regs_t *)uart); +} diff --git a/Libraries/PeriphDrivers/Source/WDT/wdt_me30.c b/Libraries/PeriphDrivers/Source/WDT/wdt_me30.c new file mode 100644 index 00000000000..0c761e70c7e --- /dev/null +++ b/Libraries/PeriphDrivers/Source/WDT/wdt_me30.c @@ -0,0 +1,161 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* **** Includes **** */ +#include "mxc_device.h" +#include "mxc_errors.h" +#include "mxc_assert.h" +#include "mxc_sys.h" +#include "wdt.h" +#include "wdt_revb.h" + +/* **** Functions **** */ + +int MXC_WDT_Init(mxc_wdt_regs_t *wdt, mxc_wdt_cfg_t *cfg) +{ +#ifndef MSDK_NO_GPIO_CLK_INIT + if (wdt == MXC_WDT0) { + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_WDT0); + } else if (wdt == MXC_WDT1) { + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_WDT1); + } else { + return E_BAD_PARAM; + } +#endif + + MXC_WDT_RevB_Init((mxc_wdt_revb_regs_t *)wdt, (mxc_wdt_revb_cfg_t *)cfg); + + return E_NO_ERROR; +} + +int MXC_WDT_Shutdown(mxc_wdt_regs_t *wdt) +{ + if (wdt == MXC_WDT0) { + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_WDT0); + } else if (wdt == MXC_WDT1) { + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_WDT1); + } else { + return E_BAD_PARAM; + } + + return E_NO_ERROR; +} + +void MXC_WDT_SetIntPeriod(mxc_wdt_regs_t *wdt, mxc_wdt_cfg_t *cfg) +{ + MXC_WDT_RevB_SetIntPeriod((mxc_wdt_revb_regs_t *)wdt, (mxc_wdt_revb_cfg_t *)cfg); +} + +void MXC_WDT_SetResetPeriod(mxc_wdt_regs_t *wdt, mxc_wdt_cfg_t *cfg) +{ + MXC_WDT_RevB_SetResetPeriod((mxc_wdt_revb_regs_t *)wdt, (mxc_wdt_revb_cfg_t *)cfg); +} + +void MXC_WDT_Enable(mxc_wdt_regs_t *wdt) +{ + MXC_WDT_RevB_Enable((mxc_wdt_revb_regs_t *)wdt); +} + +void MXC_WDT_Disable(mxc_wdt_regs_t *wdt) +{ + MXC_WDT_RevB_Disable((mxc_wdt_revb_regs_t *)wdt); +} + +void MXC_WDT_EnableInt(mxc_wdt_regs_t *wdt) +{ + MXC_WDT_RevB_EnableInt((mxc_wdt_revb_regs_t *)wdt, MXC_WDT_REVB_ENABLE); +} + +void MXC_WDT_DisableInt(mxc_wdt_regs_t *wdt) +{ + MXC_WDT_RevB_EnableInt((mxc_wdt_revb_regs_t *)wdt, MXC_WDT_REVB_DISABLE); +} + +void MXC_WDT_EnableReset(mxc_wdt_regs_t *wdt) +{ + MXC_WDT_RevB_EnableReset((mxc_wdt_revb_regs_t *)wdt, MXC_WDT_REVB_ENABLE); +} + +void MXC_WDT_DisableReset(mxc_wdt_regs_t *wdt) +{ + MXC_WDT_RevB_EnableReset((mxc_wdt_revb_regs_t *)wdt, MXC_WDT_REVB_DISABLE); +} + +void MXC_WDT_ResetTimer(mxc_wdt_regs_t *wdt) +{ + MXC_WDT_RevB_ResetTimer((mxc_wdt_revb_regs_t *)wdt); +} + +int MXC_WDT_GetResetFlag(mxc_wdt_regs_t *wdt) +{ + return MXC_WDT_RevB_GetResetFlag((mxc_wdt_revb_regs_t *)wdt); +} + +void MXC_WDT_ClearResetFlag(mxc_wdt_regs_t *wdt) +{ + MXC_WDT_RevB_ClearResetFlag((mxc_wdt_revb_regs_t *)wdt); +} + +int MXC_WDT_GetIntFlag(mxc_wdt_regs_t *wdt) +{ + return MXC_WDT_RevB_GetIntFlag((mxc_wdt_revb_regs_t *)wdt); +} + +void MXC_WDT_ClearIntFlag(mxc_wdt_regs_t *wdt) +{ + MXC_WDT_RevB_ClearIntFlag((mxc_wdt_revb_regs_t *)wdt); +} + +int MXC_WDT_SetClockSource(mxc_wdt_regs_t *wdt, mxc_wdt_clock_t clock_source) +{ + const uint8_t clock_source_num = 8; + uint8_t idx = 0; + uint8_t instance = 0; + +#if TARGET_NUM == 32655 || TARGET_NUM == 78000 + mxc_wdt_clock_t clock_sources[2][8] = { + { MXC_WDT_PCLK, MXC_WDT_IBRO_CLK, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, + { MXC_WDT_IBRO_CLK, MXC_WDT_INRO_CLK, MXC_WDT_ERTCO_CLK, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } + }; +#elif TARGET_NUM == 32680 + mxc_wdt_clock_t clock_sources[2][8] = { + { MXC_WDT_PCLK, MXC_WDT_IBRO_CLK, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, + { MXC_WDT_IBRO_CLK, 0xFF, MXC_WDT_INRO_CLK, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } + }; +#else +#error ME17 WDT driver does not support given target number. +#endif + + if (wdt == MXC_WDT0) { + instance = 0; + } else if (wdt == MXC_WDT1) { + instance = 1; + } else { + return E_BAD_PARAM; + } + + for (idx = 0; idx < clock_source_num; idx++) { + if (clock_sources[instance][idx] == clock_source) { + break; + } + } + + MXC_WDT_RevB_SetClockSource((mxc_wdt_revb_regs_t *)wdt, idx); + + return E_NO_ERROR; +} diff --git a/Libraries/PeriphDrivers/Source/WUT/wut_me30.c b/Libraries/PeriphDrivers/Source/WUT/wut_me30.c new file mode 100644 index 00000000000..7f6f8689381 --- /dev/null +++ b/Libraries/PeriphDrivers/Source/WUT/wut_me30.c @@ -0,0 +1,370 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/* **** Includes **** */ +#include +#include "mxc_device.h" +#include "mxc_assert.h" +#include "wut.h" +#include "wut_reva.h" +#include "trimsir_regs.h" + +/* **** Definitions **** */ + +/* Clock rate the BLE DBB counter */ +#ifndef BB_CLK_RATE_HZ +#define BB_CLK_RATE_HZ 1000000 +#endif + +/* Higher values will produce a more accurate measurement, but will consume more power */ +#define WUT_TRIM_TICKS 0x1000 + +/* **** Globals **** */ + +/* **** Local Variables **** */ + +/* Used for the asynchronous trim procedure */ +static uint32_t wutCnt0_async, snapshot0_async, bestTrim_async, bestDiff_async; +static int capAdded_async; +static int trimPending; +static mxc_wut_complete_cb_t cb_async; + +/* **** Functions **** */ + +/* ************************************************************************** */ +void MXC_WUT_Init(mxc_wut_regs_t *wut, mxc_wut_pres_t pres) +{ +#ifndef MSDK_NO_GPIO_CLK_INIT + MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_ERTCO); +#endif + MXC_WUT_RevA_Init((mxc_wut_reva_regs_t *)wut, pres); +} + +void MXC_WUT_Shutdown(mxc_wut_regs_t *wut) +{ + MXC_WUT_RevA_Shutdown((mxc_wut_reva_regs_t *)wut); +} + +/* ************************************************************************** */ +void MXC_WUT_Enable(mxc_wut_regs_t *wut) +{ + MXC_WUT_RevA_Enable((mxc_wut_reva_regs_t *)wut); +} + +/* ************************************************************************** */ +void MXC_WUT_Disable(mxc_wut_regs_t *wut) +{ + MXC_WUT_RevA_Disable((mxc_wut_reva_regs_t *)wut); +} + +/* ************************************************************************** */ +void MXC_WUT_Config(mxc_wut_regs_t *wut, const mxc_wut_cfg_t *cfg) +{ + MXC_WUT_RevA_Config((mxc_wut_reva_regs_t *)wut, (mxc_wut_reva_cfg_t *)cfg); +} + +/* ************************************************************************** */ +uint32_t MXC_WUT_GetCompare(mxc_wut_regs_t *wut) +{ + return MXC_WUT_RevA_GetCompare((mxc_wut_reva_regs_t *)wut); +} + +/* ************************************************************************* */ +uint32_t MXC_WUT_GetCount(mxc_wut_regs_t *wut) +{ + return MXC_WUT_RevA_GetCount((mxc_wut_reva_regs_t *)wut); +} + +/* ************************************************************************* */ +void MXC_WUT_IntClear(mxc_wut_regs_t *wut) +{ + MXC_WUT_RevA_IntClear((mxc_wut_reva_regs_t *)wut); +} + +/* ************************************************************************* */ +uint32_t MXC_WUT_IntStatus(mxc_wut_regs_t *wut) +{ + return MXC_WUT_RevA_IntStatus((mxc_wut_reva_regs_t *)wut); +} + +/* ************************************************************************* */ +void MXC_WUT_SetCompare(mxc_wut_regs_t *wut, uint32_t cmp_cnt) +{ + MXC_WUT_RevA_SetCompare((mxc_wut_reva_regs_t *)wut, cmp_cnt); +} + +/* ************************************************************************* */ +void MXC_WUT_SetCount(mxc_wut_regs_t *wut, uint32_t cnt) +{ + MXC_WUT_RevA_SetCount((mxc_wut_reva_regs_t *)wut, cnt); +} + +/* ************************************************************************* */ +int MXC_WUT_GetTicks(mxc_wut_regs_t *wut, uint32_t time, mxc_wut_unit_t units, uint32_t *ticks) +{ + return MXC_WUT_RevA_GetTicks((mxc_wut_reva_regs_t *)wut, ERTCO_FREQ, time, units, ticks); +} + +/* ************************************************************************* */ +int MXC_WUT_GetTime(mxc_wut_regs_t *wut, uint32_t ticks, uint32_t *time, mxc_wut_unit_t *units) +{ + return MXC_WUT_RevA_GetTime((mxc_wut_reva_regs_t *)wut, ERTCO_FREQ, ticks, time, + (mxc_wut_reva_unit_t *)units); +} + +/* ************************************************************************** */ +void MXC_WUT_Edge(mxc_wut_regs_t *wut) +{ + MXC_WUT_RevA_Edge((mxc_wut_reva_regs_t *)wut); +} + +/* ************************************************************************** */ +void MXC_WUT_Store(mxc_wut_regs_t *wut) +{ + MXC_WUT_RevA_Store((mxc_wut_reva_regs_t *)wut); +} + +/* ************************************************************************** */ +void MXC_WUT_RestoreBBClock(mxc_wut_regs_t *wut, uint32_t dbbFreq) +{ + MXC_WUT_RevA_RestoreBBClock((mxc_wut_reva_regs_t *)wut, dbbFreq, ERTCO_FREQ); +} + +/* ************************************************************************** */ +uint32_t MXC_WUT_GetSleepTicks(mxc_wut_regs_t *wut) +{ + return MXC_WUT_RevA_GetSleepTicks((mxc_wut_reva_regs_t *)wut); +} + +/* ************************************************************************** */ +void MXC_WUT_Delay_MS(mxc_wut_regs_t *wut, uint32_t waitMs) +{ + MXC_WUT_RevA_Delay_MS((mxc_wut_reva_regs_t *)wut, waitMs, ERTCO_FREQ); +} + +/* ************************************************************************** */ +static void MXC_WUT_GetWUTSync(mxc_wut_regs_t *wut, uint32_t *wutCnt, uint32_t *snapshot) +{ + MXC_WUT_RevA_Edge((mxc_wut_reva_regs_t *)wut); + *wutCnt = wut->cnt; + *snapshot = wut->snapshot; +} + +/* ************************************************************************** */ +static void MXC_WUT_SetTrim(uint32_t trimValue) +{ + MXC_SETFIELD(MXC_TRIMSIR->rtc, MXC_F_TRIMSIR_RTC_X1TRIM, + (trimValue << MXC_F_TRIMSIR_RTC_X1TRIM_POS)); + MXC_SETFIELD(MXC_TRIMSIR->rtc, MXC_F_TRIMSIR_RTC_X2TRIM, + (trimValue << MXC_F_TRIMSIR_RTC_X2TRIM_POS)); +} + +/* ************************************************************************** */ +static int MXC_WUT_StartTrim(mxc_wut_regs_t *wut) +{ + uint32_t wutCnt0, wutCnt1; + uint32_t snapshot0, snapshot1; + uint32_t trimValue; + + /* Make sure the WUT is running in compare mode */ + if (!(wut->ctrl & MXC_F_WUT_REVA_CTRL_TEN)) { + return E_UNINITIALIZED; + } + + /* Make sure that DBB counter is running */ + MXC_WUT_GetWUTSync(wut, &wutCnt0, &snapshot0); + MXC_WUT_GetWUTSync(wut, &wutCnt1, &snapshot1); + if (snapshot0 == snapshot1) { + return E_UNINITIALIZED; + } + + /* Start with existing trim value */ + trimValue = (MXC_TRIMSIR->rtc & MXC_F_TRIMSIR_RTC_X1TRIM) >> MXC_F_TRIMSIR_RTC_X1TRIM_POS; + MXC_WUT_SetTrim(trimValue); + + /* Initialize the variables */ + bestTrim_async = trimValue; + bestDiff_async = 0xFFFF; + + /* Get the initial snapshot */ + MXC_WUT_GetWUTSync(wut, &wutCnt0_async, &snapshot0_async); + + trimPending = 1; + + return E_NO_ERROR; +} + +/* ************************************************************************** */ +int MXC_WUT_Handler(mxc_wut_regs_t *wut) +{ + uint32_t wutCnt1; + uint32_t snapshot1; + uint32_t trimValue; + uint32_t snapTicks, wutTicks; + uint64_t calcTicks; + int trimComplete; + mxc_wut_complete_cb_t cbTemp; + + /* Clear the interrupt flags */ + MXC_WUT_IntClear(wut); + + if (!trimPending) { + return E_NO_ERROR; + } + + /* Store the snapshot */ + MXC_WUT_GetWUTSync(wut, &wutCnt1, &snapshot1); + snapTicks = snapshot1 - snapshot0_async; + wutTicks = wutCnt1 - wutCnt0_async; + + /* Calculate the ideal number of DBB ticks in WUT_TRIM_TICKS */ + calcTicks = ((uint64_t)wutTicks * (uint64_t)BB_CLK_RATE_HZ) / (uint64_t)32768; + + trimComplete = 0; + trimValue = (MXC_TRIMSIR->rtc & MXC_F_TRIMSIR_RTC_X1TRIM) >> MXC_F_TRIMSIR_RTC_X1TRIM_POS; + + if (snapTicks > calcTicks) { + /* See if we're closer to the calculated value */ + if ((snapTicks - calcTicks) <= bestDiff_async) { + bestDiff_async = snapTicks - calcTicks; + bestTrim_async = trimValue; + } + + /* Running slow, reduce cap */ + if (trimValue == 0) { + /* We're maxed out on trim range */ + trimComplete = 1; + } + trimValue--; + + if (capAdded_async == 1) { + /* We've hit an inflection point */ + trimComplete = 1; + } + capAdded_async = -1; + + } else if (snapTicks < calcTicks) { + /* See if we're closer to the calculated value */ + if ((calcTicks - snapTicks) <= bestDiff_async) { + bestDiff_async = calcTicks - snapTicks; + bestTrim_async = trimValue; + } + + /* Running fast, increase cap */ + if (trimValue == 0x1f) { + /* We're maxed out on trim range */ + trimComplete = 1; + } + trimValue++; + + if (capAdded_async == -1) { + /* We've hit an inflection point */ + trimComplete = 1; + } + capAdded_async = 1; + + } else { + /* Just right */ + bestTrim_async = trimValue; + trimComplete = 1; + } + + if (trimComplete) { + /* Apply the best trim value */ + MXC_WUT_SetTrim(bestTrim_async); + + trimPending = 0; + + /* Call the callback */ + if (cb_async != NULL) { + cbTemp = cb_async; + cb_async = NULL; + cbTemp(E_NO_ERROR); + } + + return E_NO_ERROR; + } + + /* Start the next step */ + MXC_WUT_SetTrim(trimValue); + MXC_WUT_GetWUTSync(wut, &wutCnt0_async, &snapshot0_async); + + if (cb_async != NULL) { + /* Prime the compare interrupt */ + wut->cmp = wut->cnt + WUT_TRIM_TICKS - 1; + } + + /* Return E_BUSY to indicate the trim procedure is still running */ + return E_BUSY; +} + +/* ************************************************************************** */ +int MXC_WUT_TrimCrystal(mxc_wut_regs_t *wut) +{ + int err, i; + + /* Clear the async callback pointer */ + cb_async = NULL; + + /* Start the trim procedure */ + err = MXC_WUT_StartTrim(wut); + if (err != E_NO_ERROR) { + return err; + } + do { + for (i = 0; i < (WUT_TRIM_TICKS - 1); i++) { + MXC_WUT_RevA_Edge((mxc_wut_reva_regs_t *)wut); + } + } while (MXC_WUT_Handler(wut) != E_NO_ERROR); + + return E_NO_ERROR; +} + +/* ************************************************************************** */ +int MXC_WUT_TrimCrystalAsync(mxc_wut_regs_t *wut, mxc_wut_complete_cb_t cb) +{ + int err; + + if (cb == NULL) { + return E_NULL_PTR; + } + + /* Save the callback */ + cb_async = cb; + + /* Start the trim procedure */ + err = MXC_WUT_StartTrim(wut); + if (err != E_NO_ERROR) { + return err; + } + + /* Prime the compare interrupt */ + wut->cmp = wut->cnt + WUT_TRIM_TICKS - 1; + + return E_NO_ERROR; +} + +/* ************************************************************************** */ +int MXC_WUT_TrimPending(mxc_wut_regs_t *wut) +{ + if (trimPending) { + return E_BUSY; + } + + return E_NO_ERROR; +} From c3a53629dffbede29e749a076fcd0f49fa9562bd Mon Sep 17 00:00:00 2001 From: Jake Carter Date: Mon, 29 Apr 2024 15:40:57 -0600 Subject: [PATCH 17/93] Set FPU 'fpv5-sp-d16' for ME30 --- .../CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.mk | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.mk b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.mk index 82b06cb91aa..2fc1415874f 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.mk +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.mk @@ -120,6 +120,12 @@ LIBPATH+=$(CMSIS_ROOT)/Device/Maxim/$(TARGET_UC)/Source/GCC # Set target architecture MCPU := cortex-m33 +# Set FPU architecture +# (See Arm Cortex M33 Technical Reference Manual Chapter B5 +# Armv8-M Floating-Point extension with FPv5 architecture +# Single-precision with 16 double-word registers +MFPU := fpv5-sp-d16 + # Include the rules and goals for building include $(CMSIS_ROOT)/Device/Maxim/GCC/gcc.mk From 03a5c6a584856e8e8b1ba6d631956035f948b68e Mon Sep 17 00:00:00 2001 From: Woo Date: Mon, 29 Apr 2024 18:19:17 -0500 Subject: [PATCH 18/93] Update register files to match appropriate IP --- .../Device/Maxim/MAX32657/Include/fcr_regs.h | 48 +- .../Device/Maxim/MAX32657/Include/gcr_regs.h | 461 +-- .../Device/Maxim/MAX32657/Include/max32657.h | 757 ----- .../Maxim/MAX32657/Include/max32657.svd | 2983 ++--------------- .../Device/Maxim/MAX32657/Include/sir_regs.h | 8 +- .../Device/Maxim/MAX32657/Include/spi_regs.h | 110 +- .../Maxim/MAX32657/Include/system_max32657.h | 101 - 7 files changed, 413 insertions(+), 4055 deletions(-) delete mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h delete mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h index 53dd1268f50..f9badfb8265 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h @@ -76,9 +76,9 @@ typedef struct { __IO uint32_t fctrl1; /**< \b 0x04: FCR FCTRL1 Register */ __IO uint32_t fctrl2; /**< \b 0x08: FCR FCTRL2 Register */ __IO uint32_t fctrl3; /**< \b 0x0C: FCR FCTRL3 Register */ - __R uint32_t rsv_0x10_0x1b[3]; - __IO uint32_t gp; /**< \b 0x1C: FCR GP Register */ - __IO uint32_t msrtrim; /**< \b 0x20: FCR MSRTRIM Register */ + __R uint32_t rsv_0x10_0x17[2]; + __IO uint32_t erfoks; /**< \b 0x18: FCR ERFOKS Register */ + __R uint32_t rsv_0x1c_0x23[2]; __IO uint32_t flvfilt; /**< \b 0x24: FCR FLVFILT Register */ } mxc_fcr_regs_t; @@ -93,8 +93,7 @@ typedef struct { #define MXC_R_FCR_FCTRL1 ((uint32_t)0x00000004UL) /**< Offset from FCR Base Address: 0x0004 */ #define MXC_R_FCR_FCTRL2 ((uint32_t)0x00000008UL) /**< Offset from FCR Base Address: 0x0008 */ #define MXC_R_FCR_FCTRL3 ((uint32_t)0x0000000CUL) /**< Offset from FCR Base Address: 0x000C */ -#define MXC_R_FCR_GP ((uint32_t)0x0000001CUL) /**< Offset from FCR Base Address: 0x001C */ -#define MXC_R_FCR_MSRTRIM ((uint32_t)0x00000020UL) /**< Offset from FCR Base Address: 0x0020 */ +#define MXC_R_FCR_ERFOKS ((uint32_t)0x00000018UL) /**< Offset from FCR Base Address: 0x0018 */ #define MXC_R_FCR_FLVFILT ((uint32_t)0x00000024UL) /**< Offset from FCR Base Address: 0x0024 */ /**@} end of group fcr_registers */ @@ -104,8 +103,19 @@ typedef struct { * @brief Register 0. * @{ */ -#define MXC_F_FCR_FCTRL0_USBCLKSEL_POS 16 /**< FCTRL0_USBCLKSEL Position */ -#define MXC_F_FCR_FCTRL0_USBCLKSEL ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_USBCLKSEL_POS)) /**< FCTRL0_USBCLKSEL Mask */ +#define MXC_F_FCR_FCTRL0_BTLELDOTX_POS 0 /**< FCTRL0_BTLELDOTX Position */ +#define MXC_F_FCR_FCTRL0_BTLELDOTX ((uint32_t)(0x1FUL << MXC_F_FCR_FCTRL0_BTLELDOTX_POS)) /**< FCTRL0_BTLELDOTX Mask */ +#define MXC_V_FCR_FCTRL0_BTLELDOTX_SYS ((uint32_t)0x0UL) /**< FCTRL0_BTLELDOTX_SYS Value */ +#define MXC_S_FCR_FCTRL0_BTLELDOTX_SYS (MXC_V_FCR_FCTRL0_BTLELDOTX_SYS << MXC_F_FCR_FCTRL0_BTLELDOTX_POS) /**< FCTRL0_BTLELDOTX_SYS Setting */ +#define MXC_V_FCR_FCTRL0_BTLELDOTX_DIG ((uint32_t)0x1UL) /**< FCTRL0_BTLELDOTX_DIG Value */ +#define MXC_S_FCR_FCTRL0_BTLELDOTX_DIG (MXC_V_FCR_FCTRL0_BTLELDOTX_DIG << MXC_F_FCR_FCTRL0_BTLELDOTX_POS) /**< FCTRL0_BTLELDOTX_DIG Setting */ + +#define MXC_F_FCR_FCTRL0_BTLELDORX_POS 8 /**< FCTRL0_BTLELDORX Position */ +#define MXC_F_FCR_FCTRL0_BTLELDORX ((uint32_t)(0x1FUL << MXC_F_FCR_FCTRL0_BTLELDORX_POS)) /**< FCTRL0_BTLELDORX Mask */ +#define MXC_V_FCR_FCTRL0_BTLELDORX_SYS ((uint32_t)0x0UL) /**< FCTRL0_BTLELDORX_SYS Value */ +#define MXC_S_FCR_FCTRL0_BTLELDORX_SYS (MXC_V_FCR_FCTRL0_BTLELDORX_SYS << MXC_F_FCR_FCTRL0_BTLELDORX_POS) /**< FCTRL0_BTLELDORX_SYS Setting */ +#define MXC_V_FCR_FCTRL0_BTLELDORX_DIG ((uint32_t)0x1UL) /**< FCTRL0_BTLELDORX_DIG Value */ +#define MXC_S_FCR_FCTRL0_BTLELDORX_DIG (MXC_V_FCR_FCTRL0_BTLELDORX_DIG << MXC_F_FCR_FCTRL0_BTLELDORX_POS) /**< FCTRL0_BTLELDORX_DIG Setting */ #define MXC_F_FCR_FCTRL0_I2C0DGEN0_POS 20 /**< FCTRL0_I2C0DGEN0 Position */ #define MXC_F_FCR_FCTRL0_I2C0DGEN0 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0DGEN0_POS)) /**< FCTRL0_I2C0DGEN0 Mask */ @@ -216,28 +226,14 @@ typedef struct { /** * @ingroup fcr_registers - * @defgroup FCR_GP FCR_GP - * @brief General Purpose Register. + * @defgroup FCR_ERFOKS FCR_ERFOKS + * @brief ERFO Kick Start Register. * @{ */ -#define MXC_F_FCR_GP_GP_POS 0 /**< GP_GP Position */ -#define MXC_F_FCR_GP_GP ((uint32_t)(0xFFFFFFFFUL << MXC_F_FCR_GP_GP_POS)) /**< GP_GP Mask */ +#define MXC_F_FCR_ERFOKS_GP_POS 0 /**< ERFOKS_GP Position */ +#define MXC_F_FCR_ERFOKS_GP ((uint32_t)(0xFFFFFFFFUL << MXC_F_FCR_ERFOKS_GP_POS)) /**< ERFOKS_GP Mask */ -/**@} end of group FCR_GP_Register */ - -/** - * @ingroup fcr_registers - * @defgroup FCR_MSRTRIM FCR_MSRTRIM - * @brief MSR Trim Register. - * @{ - */ -#define MXC_F_FCR_MSRTRIM_R1_POS 0 /**< MSRTRIM_R1 Position */ -#define MXC_F_FCR_MSRTRIM_R1 ((uint32_t)(0x3UL << MXC_F_FCR_MSRTRIM_R1_POS)) /**< MSRTRIM_R1 Mask */ - -#define MXC_F_FCR_MSRTRIM_R2_POS 2 /**< MSRTRIM_R2 Position */ -#define MXC_F_FCR_MSRTRIM_R2 ((uint32_t)(0x7UL << MXC_F_FCR_MSRTRIM_R2_POS)) /**< MSRTRIM_R2 Mask */ - -/**@} end of group FCR_MSRTRIM_Register */ +/**@} end of group FCR_ERFOKS_Register */ /** * @ingroup fcr_registers diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h index 16a0777d191..9877604cad3 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h @@ -89,10 +89,9 @@ typedef struct { __IO uint32_t eventen; /**< \b 0x4C: GCR EVENTEN Register */ __I uint32_t revision; /**< \b 0x50: GCR REVISION Register */ __IO uint32_t sysinten; /**< \b 0x54: GCR SYSINTEN Register */ - __IO uint32_t ipocnt; /**< \b 0x58: GCR IPOCNT Register */ - __R uint32_t rsv_0x5c_0x63[2]; + __R uint32_t rsv_0x58_0x63[3]; __IO uint32_t eccerr; /**< \b 0x64: GCR ECCERR Register */ - __IO uint32_t eccced; /**< \b 0x68: GCR ECCCED Register */ + __R uint32_t rsv_0x68; __IO uint32_t eccinten; /**< \b 0x6C: GCR ECCINTEN Register */ __IO uint32_t eccaddr; /**< \b 0x70: GCR ECCADDR Register */ __IO uint32_t btleldoctrl; /**< \b 0x74: GCR BTLELDOCTRL Register */ @@ -124,9 +123,7 @@ typedef struct { #define MXC_R_GCR_EVENTEN ((uint32_t)0x0000004CUL) /**< Offset from GCR Base Address: 0x004C */ #define MXC_R_GCR_REVISION ((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: 0x0050 */ #define MXC_R_GCR_SYSINTEN ((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: 0x0054 */ -#define MXC_R_GCR_IPOCNT ((uint32_t)0x00000058UL) /**< Offset from GCR Base Address: 0x0058 */ #define MXC_R_GCR_ECCERR ((uint32_t)0x00000064UL) /**< Offset from GCR Base Address: 0x0064 */ -#define MXC_R_GCR_ECCCED ((uint32_t)0x00000068UL) /**< Offset from GCR Base Address: 0x0068 */ #define MXC_R_GCR_ECCINTEN ((uint32_t)0x0000006CUL) /**< Offset from GCR Base Address: 0x006C */ #define MXC_R_GCR_ECCADDR ((uint32_t)0x00000070UL) /**< Offset from GCR Base Address: 0x0070 */ #define MXC_R_GCR_BTLELDOCTRL ((uint32_t)0x00000074UL) /**< Offset from GCR Base Address: 0x0074 */ @@ -161,23 +158,11 @@ typedef struct { #define MXC_F_GCR_SYSCTRL_ICC_FLUSH_POS 6 /**< SYSCTRL_ICC_FLUSH Position */ #define MXC_F_GCR_SYSCTRL_ICC_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_ICC_FLUSH_POS)) /**< SYSCTRL_ICC_FLUSH Mask */ -#define MXC_F_GCR_SYSCTRL_SRCC_FLUSH_POS 7 /**< SYSCTRL_SRCC_FLUSH Position */ -#define MXC_F_GCR_SYSCTRL_SRCC_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_SRCC_FLUSH_POS)) /**< SYSCTRL_SRCC_FLUSH Mask */ +#define MXC_F_GCR_SYSCTRL_CCHK_POS 13 /**< SYSCTRL_CCHK Position */ +#define MXC_F_GCR_SYSCTRL_CCHK ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CCHK_POS)) /**< SYSCTRL_CCHK Mask */ -#define MXC_F_GCR_SYSCTRL_SRCC_DIS_POS 9 /**< SYSCTRL_SRCC_DIS Position */ -#define MXC_F_GCR_SYSCTRL_SRCC_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_SRCC_DIS_POS)) /**< SYSCTRL_SRCC_DIS Mask */ - -#define MXC_F_GCR_SYSCTRL_CHKRES1_POS 11 /**< SYSCTRL_CHKRES1 Position */ -#define MXC_F_GCR_SYSCTRL_CHKRES1 ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CHKRES1_POS)) /**< SYSCTRL_CHKRES1 Mask */ - -#define MXC_F_GCR_SYSCTRL_CCHK1_POS 12 /**< SYSCTRL_CCHK1 Position */ -#define MXC_F_GCR_SYSCTRL_CCHK1 ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CCHK1_POS)) /**< SYSCTRL_CCHK1 Mask */ - -#define MXC_F_GCR_SYSCTRL_CCHK0_POS 13 /**< SYSCTRL_CCHK0 Position */ -#define MXC_F_GCR_SYSCTRL_CCHK0 ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CCHK0_POS)) /**< SYSCTRL_CCHK0 Mask */ - -#define MXC_F_GCR_SYSCTRL_CHKRES0_POS 15 /**< SYSCTRL_CHKRES0 Position */ -#define MXC_F_GCR_SYSCTRL_CHKRES0 ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CHKRES0_POS)) /**< SYSCTRL_CHKRES0 Mask */ +#define MXC_F_GCR_SYSCTRL_CHKRES_POS 15 /**< SYSCTRL_CHKRES Position */ +#define MXC_F_GCR_SYSCTRL_CHKRES ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_CHKRES_POS)) /**< SYSCTRL_CHKRES Mask */ #define MXC_F_GCR_SYSCTRL_OVR_POS 16 /**< SYSCTRL_OVR Position */ #define MXC_F_GCR_SYSCTRL_OVR ((uint32_t)(0x3UL << MXC_F_GCR_SYSCTRL_OVR_POS)) /**< SYSCTRL_OVR Mask */ @@ -190,18 +175,15 @@ typedef struct { * @brief Reset. * @{ */ -#define MXC_F_GCR_RST0_DMA_POS 0 /**< RST0_DMA Position */ -#define MXC_F_GCR_RST0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_RST0_DMA_POS)) /**< RST0_DMA Mask */ +#define MXC_F_GCR_RST0_DMA0_POS 0 /**< RST0_DMA0 Position */ +#define MXC_F_GCR_RST0_DMA0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_DMA0_POS)) /**< RST0_DMA0 Mask */ -#define MXC_F_GCR_RST0_WDT0_POS 1 /**< RST0_WDT0 Position */ -#define MXC_F_GCR_RST0_WDT0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_WDT0_POS)) /**< RST0_WDT0 Mask */ +#define MXC_F_GCR_RST0_WDT_POS 1 /**< RST0_WDT Position */ +#define MXC_F_GCR_RST0_WDT ((uint32_t)(0x1UL << MXC_F_GCR_RST0_WDT_POS)) /**< RST0_WDT Mask */ #define MXC_F_GCR_RST0_GPIO0_POS 2 /**< RST0_GPIO0 Position */ #define MXC_F_GCR_RST0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO0_POS)) /**< RST0_GPIO0 Mask */ -#define MXC_F_GCR_RST0_GPIO1_POS 3 /**< RST0_GPIO1 Position */ -#define MXC_F_GCR_RST0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_GPIO1_POS)) /**< RST0_GPIO1 Mask */ - #define MXC_F_GCR_RST0_TMR0_POS 5 /**< RST0_TMR0 Position */ #define MXC_F_GCR_RST0_TMR0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR0_POS)) /**< RST0_TMR0 Mask */ @@ -220,44 +202,26 @@ typedef struct { #define MXC_F_GCR_RST0_TMR5_POS 10 /**< RST0_TMR5 Position */ #define MXC_F_GCR_RST0_TMR5 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR5_POS)) /**< RST0_TMR5 Mask */ -#define MXC_F_GCR_RST0_UART0_POS 11 /**< RST0_UART0 Position */ -#define MXC_F_GCR_RST0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART0_POS)) /**< RST0_UART0 Mask */ - -#define MXC_F_GCR_RST0_UART1_POS 12 /**< RST0_UART1 Position */ -#define MXC_F_GCR_RST0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART1_POS)) /**< RST0_UART1 Mask */ - -#define MXC_F_GCR_RST0_SPI0_POS 13 /**< RST0_SPI0 Position */ -#define MXC_F_GCR_RST0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI0_POS)) /**< RST0_SPI0 Mask */ - -#define MXC_F_GCR_RST0_SPI1_POS 14 /**< RST0_SPI1 Position */ -#define MXC_F_GCR_RST0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI1_POS)) /**< RST0_SPI1 Mask */ +#define MXC_F_GCR_RST0_UART_POS 11 /**< RST0_UART Position */ +#define MXC_F_GCR_RST0_UART ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART_POS)) /**< RST0_UART Mask */ -#define MXC_F_GCR_RST0_SPI2_POS 15 /**< RST0_SPI2 Position */ -#define MXC_F_GCR_RST0_SPI2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI2_POS)) /**< RST0_SPI2 Mask */ +#define MXC_F_GCR_RST0_SPI_POS 13 /**< RST0_SPI Position */ +#define MXC_F_GCR_RST0_SPI ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SPI_POS)) /**< RST0_SPI Mask */ -#define MXC_F_GCR_RST0_I2C0_POS 16 /**< RST0_I2C0 Position */ -#define MXC_F_GCR_RST0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_I2C0_POS)) /**< RST0_I2C0 Mask */ +#define MXC_F_GCR_RST0_I3C_POS 16 /**< RST0_I3C Position */ +#define MXC_F_GCR_RST0_I3C ((uint32_t)(0x1UL << MXC_F_GCR_RST0_I3C_POS)) /**< RST0_I3C Mask */ #define MXC_F_GCR_RST0_RTC_POS 17 /**< RST0_RTC Position */ #define MXC_F_GCR_RST0_RTC ((uint32_t)(0x1UL << MXC_F_GCR_RST0_RTC_POS)) /**< RST0_RTC Mask */ -#define MXC_F_GCR_RST0_TMR6_POS 20 /**< RST0_TMR6 Position */ -#define MXC_F_GCR_RST0_TMR6 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR6_POS)) /**< RST0_TMR6 Mask */ - -#define MXC_F_GCR_RST0_TMR7_POS 21 /**< RST0_TMR7 Position */ -#define MXC_F_GCR_RST0_TMR7 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TMR7_POS)) /**< RST0_TMR7 Mask */ - -#define MXC_F_GCR_RST0_SEMA_POS 22 /**< RST0_SEMA Position */ -#define MXC_F_GCR_RST0_SEMA ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SEMA_POS)) /**< RST0_SEMA Mask */ +#define MXC_F_GCR_RST0_BTLE_POS 18 /**< RST0_BTLE Position */ +#define MXC_F_GCR_RST0_BTLE ((uint32_t)(0x1UL << MXC_F_GCR_RST0_BTLE_POS)) /**< RST0_BTLE Mask */ #define MXC_F_GCR_RST0_TRNG_POS 24 /**< RST0_TRNG Position */ #define MXC_F_GCR_RST0_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_RST0_TRNG_POS)) /**< RST0_TRNG Mask */ -#define MXC_F_GCR_RST0_ADC_POS 26 /**< RST0_ADC Position */ -#define MXC_F_GCR_RST0_ADC ((uint32_t)(0x1UL << MXC_F_GCR_RST0_ADC_POS)) /**< RST0_ADC Mask */ - -#define MXC_F_GCR_RST0_UART2_POS 28 /**< RST0_UART2 Position */ -#define MXC_F_GCR_RST0_UART2 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_UART2_POS)) /**< RST0_UART2 Mask */ +#define MXC_F_GCR_RST0_DMA1_POS 27 /**< RST0_DMA1 Position */ +#define MXC_F_GCR_RST0_DMA1 ((uint32_t)(0x1UL << MXC_F_GCR_RST0_DMA1_POS)) /**< RST0_DMA1 Mask */ #define MXC_F_GCR_RST0_SOFT_POS 29 /**< RST0_SOFT Position */ #define MXC_F_GCR_RST0_SOFT ((uint32_t)(0x1UL << MXC_F_GCR_RST0_SOFT_POS)) /**< RST0_SOFT Mask */ @@ -324,27 +288,13 @@ typedef struct { #define MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS 13 /**< CLKCTRL_SYSCLK_RDY Position */ #define MXC_F_GCR_CLKCTRL_SYSCLK_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS)) /**< CLKCTRL_SYSCLK_RDY Mask */ -#define MXC_F_GCR_CLKCTRL_IPO_DIV_POS 14 /**< CLKCTRL_IPO_DIV Position */ -#define MXC_F_GCR_CLKCTRL_IPO_DIV ((uint32_t)(0x3UL << MXC_F_GCR_CLKCTRL_IPO_DIV_POS)) /**< CLKCTRL_IPO_DIV Mask */ -#define MXC_V_GCR_CLKCTRL_IPO_DIV_DIV1 ((uint32_t)0x0UL) /**< CLKCTRL_IPO_DIV_DIV1 Value */ -#define MXC_S_GCR_CLKCTRL_IPO_DIV_DIV1 (MXC_V_GCR_CLKCTRL_IPO_DIV_DIV1 << MXC_F_GCR_CLKCTRL_IPO_DIV_POS) /**< CLKCTRL_IPO_DIV_DIV1 Setting */ -#define MXC_V_GCR_CLKCTRL_IPO_DIV_DIV2 ((uint32_t)0x1UL) /**< CLKCTRL_IPO_DIV_DIV2 Value */ -#define MXC_S_GCR_CLKCTRL_IPO_DIV_DIV2 (MXC_V_GCR_CLKCTRL_IPO_DIV_DIV2 << MXC_F_GCR_CLKCTRL_IPO_DIV_POS) /**< CLKCTRL_IPO_DIV_DIV2 Setting */ -#define MXC_V_GCR_CLKCTRL_IPO_DIV_DIV4 ((uint32_t)0x2UL) /**< CLKCTRL_IPO_DIV_DIV4 Value */ -#define MXC_S_GCR_CLKCTRL_IPO_DIV_DIV4 (MXC_V_GCR_CLKCTRL_IPO_DIV_DIV4 << MXC_F_GCR_CLKCTRL_IPO_DIV_POS) /**< CLKCTRL_IPO_DIV_DIV4 Setting */ -#define MXC_V_GCR_CLKCTRL_IPO_DIV_DIV8 ((uint32_t)0x3UL) /**< CLKCTRL_IPO_DIV_DIV8 Value */ -#define MXC_S_GCR_CLKCTRL_IPO_DIV_DIV8 (MXC_V_GCR_CLKCTRL_IPO_DIV_DIV8 << MXC_F_GCR_CLKCTRL_IPO_DIV_POS) /**< CLKCTRL_IPO_DIV_DIV8 Setting */ - #define MXC_F_GCR_CLKCTRL_ERFO_EN_POS 16 /**< CLKCTRL_ERFO_EN Position */ #define MXC_F_GCR_CLKCTRL_ERFO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERFO_EN_POS)) /**< CLKCTRL_ERFO_EN Mask */ #define MXC_F_GCR_CLKCTRL_ERTCO_EN_POS 17 /**< CLKCTRL_ERTCO_EN Position */ #define MXC_F_GCR_CLKCTRL_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERTCO_EN_POS)) /**< CLKCTRL_ERTCO_EN Mask */ -#define MXC_F_GCR_CLKCTRL_ISO_EN_POS 18 /**< CLKCTRL_ISO_EN Position */ -#define MXC_F_GCR_CLKCTRL_ISO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ISO_EN_POS)) /**< CLKCTRL_ISO_EN Mask */ - -#define MXC_F_GCR_CLKCTRL_IPO_EN_POS 19 /**< CLKCTRL_IPO_EN Position */ +#define MXC_F_GCR_CLKCTRL_IPO_EN_POS 18 /**< CLKCTRL_IPO_EN Position */ #define MXC_F_GCR_CLKCTRL_IPO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_EN_POS)) /**< CLKCTRL_IPO_EN Mask */ #define MXC_F_GCR_CLKCTRL_IBRO_EN_POS 20 /**< CLKCTRL_IBRO_EN Position */ @@ -359,10 +309,7 @@ typedef struct { #define MXC_F_GCR_CLKCTRL_ERTCO_RDY_POS 25 /**< CLKCTRL_ERTCO_RDY Position */ #define MXC_F_GCR_CLKCTRL_ERTCO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERTCO_RDY_POS)) /**< CLKCTRL_ERTCO_RDY Mask */ -#define MXC_F_GCR_CLKCTRL_ISO_RDY_POS 26 /**< CLKCTRL_ISO_RDY Position */ -#define MXC_F_GCR_CLKCTRL_ISO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ISO_RDY_POS)) /**< CLKCTRL_ISO_RDY Mask */ - -#define MXC_F_GCR_CLKCTRL_IPO_RDY_POS 27 /**< CLKCTRL_IPO_RDY Position */ +#define MXC_F_GCR_CLKCTRL_IPO_RDY_POS 28 /**< CLKCTRL_IPO_RDY Position */ #define MXC_F_GCR_CLKCTRL_IPO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_RDY_POS)) /**< CLKCTRL_IPO_RDY Mask */ #define MXC_F_GCR_CLKCTRL_IBRO_RDY_POS 28 /**< CLKCTRL_IBRO_RDY Position */ @@ -380,7 +327,7 @@ typedef struct { * @{ */ #define MXC_F_GCR_PM_MODE_POS 0 /**< PM_MODE Position */ -#define MXC_F_GCR_PM_MODE ((uint32_t)(0x7UL << MXC_F_GCR_PM_MODE_POS)) /**< PM_MODE Mask */ +#define MXC_F_GCR_PM_MODE ((uint32_t)(0xFUL << MXC_F_GCR_PM_MODE_POS)) /**< PM_MODE Mask */ #define MXC_V_GCR_PM_MODE_ACTIVE ((uint32_t)0x0UL) /**< PM_MODE_ACTIVE Value */ #define MXC_S_GCR_PM_MODE_ACTIVE (MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_ACTIVE Setting */ #define MXC_V_GCR_PM_MODE_DEEPSLEEP ((uint32_t)0x2UL) /**< PM_MODE_DEEPSLEEP Value */ @@ -396,20 +343,8 @@ typedef struct { #define MXC_F_GCR_PM_RTC_WE_POS 5 /**< PM_RTC_WE Position */ #define MXC_F_GCR_PM_RTC_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_RTC_WE_POS)) /**< PM_RTC_WE Mask */ -#define MXC_F_GCR_PM_USB_WE_POS 6 /**< PM_USB_WE Position */ -#define MXC_F_GCR_PM_USB_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_USB_WE_POS)) /**< PM_USB_WE Mask */ - -#define MXC_F_GCR_PM_ERFO_PD_POS 12 /**< PM_ERFO_PD Position */ -#define MXC_F_GCR_PM_ERFO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_ERFO_PD_POS)) /**< PM_ERFO_PD Mask */ - -#define MXC_F_GCR_PM_ISO_PD_POS 15 /**< PM_ISO_PD Position */ -#define MXC_F_GCR_PM_ISO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_ISO_PD_POS)) /**< PM_ISO_PD Mask */ - -#define MXC_F_GCR_PM_IPO_PD_POS 16 /**< PM_IPO_PD Position */ -#define MXC_F_GCR_PM_IPO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_IPO_PD_POS)) /**< PM_IPO_PD Mask */ - -#define MXC_F_GCR_PM_IBRO_PD_POS 17 /**< PM_IBRO_PD Position */ -#define MXC_F_GCR_PM_IBRO_PD ((uint32_t)(0x1UL << MXC_F_GCR_PM_IBRO_PD_POS)) /**< PM_IBRO_PD Mask */ +#define MXC_F_GCR_PM_WUT_WE_POS 7 /**< PM_WUT_WE Position */ +#define MXC_F_GCR_PM_WUT_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_WUT_WE_POS)) /**< PM_WUT_WE Mask */ #define MXC_F_GCR_PM_ERFO_BP_POS 20 /**< PM_ERFO_BP Position */ #define MXC_F_GCR_PM_ERFO_BP ((uint32_t)(0x1UL << MXC_F_GCR_PM_ERFO_BP_POS)) /**< PM_ERFO_BP Mask */ @@ -425,17 +360,6 @@ typedef struct { #define MXC_F_GCR_PCLKDIV_ADCFRQ_POS 10 /**< PCLKDIV_ADCFRQ Position */ #define MXC_F_GCR_PCLKDIV_ADCFRQ ((uint32_t)(0xFUL << MXC_F_GCR_PCLKDIV_ADCFRQ_POS)) /**< PCLKDIV_ADCFRQ Mask */ -#define MXC_F_GCR_PCLKDIV_AONCLKDIV_POS 14 /**< PCLKDIV_AONCLKDIV Position */ -#define MXC_F_GCR_PCLKDIV_AONCLKDIV ((uint32_t)(0x3UL << MXC_F_GCR_PCLKDIV_AONCLKDIV_POS)) /**< PCLKDIV_AONCLKDIV Mask */ -#define MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV4 ((uint32_t)0x0UL) /**< PCLKDIV_AONCLKDIV_DIV4 Value */ -#define MXC_S_GCR_PCLKDIV_AONCLKDIV_DIV4 (MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV4 << MXC_F_GCR_PCLKDIV_AONCLKDIV_POS) /**< PCLKDIV_AONCLKDIV_DIV4 Setting */ -#define MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV8 ((uint32_t)0x1UL) /**< PCLKDIV_AONCLKDIV_DIV8 Value */ -#define MXC_S_GCR_PCLKDIV_AONCLKDIV_DIV8 (MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV8 << MXC_F_GCR_PCLKDIV_AONCLKDIV_POS) /**< PCLKDIV_AONCLKDIV_DIV8 Setting */ -#define MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV16 ((uint32_t)0x2UL) /**< PCLKDIV_AONCLKDIV_DIV16 Value */ -#define MXC_S_GCR_PCLKDIV_AONCLKDIV_DIV16 (MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV16 << MXC_F_GCR_PCLKDIV_AONCLKDIV_POS) /**< PCLKDIV_AONCLKDIV_DIV16 Setting */ -#define MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV32 ((uint32_t)0x3UL) /**< PCLKDIV_AONCLKDIV_DIV32 Value */ -#define MXC_S_GCR_PCLKDIV_AONCLKDIV_DIV32 (MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV32 << MXC_F_GCR_PCLKDIV_AONCLKDIV_POS) /**< PCLKDIV_AONCLKDIV_DIV32 Setting */ - /**@} end of group GCR_PCLKDIV_Register */ /** @@ -447,29 +371,17 @@ typedef struct { #define MXC_F_GCR_PCLKDIS0_GPIO0_POS 0 /**< PCLKDIS0_GPIO0 Position */ #define MXC_F_GCR_PCLKDIS0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_GPIO0_POS)) /**< PCLKDIS0_GPIO0 Mask */ -#define MXC_F_GCR_PCLKDIS0_GPIO1_POS 1 /**< PCLKDIS0_GPIO1 Position */ -#define MXC_F_GCR_PCLKDIS0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_GPIO1_POS)) /**< PCLKDIS0_GPIO1 Mask */ - -#define MXC_F_GCR_PCLKDIS0_DMA_POS 5 /**< PCLKDIS0_DMA Position */ -#define MXC_F_GCR_PCLKDIS0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_DMA_POS)) /**< PCLKDIS0_DMA Mask */ - -#define MXC_F_GCR_PCLKDIS0_SPI0_POS 6 /**< PCLKDIS0_SPI0 Position */ -#define MXC_F_GCR_PCLKDIS0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI0_POS)) /**< PCLKDIS0_SPI0 Mask */ - -#define MXC_F_GCR_PCLKDIS0_SPI1_POS 7 /**< PCLKDIS0_SPI1 Position */ -#define MXC_F_GCR_PCLKDIS0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI1_POS)) /**< PCLKDIS0_SPI1 Mask */ +#define MXC_F_GCR_PCLKDIS0_DMA0_POS 5 /**< PCLKDIS0_DMA0 Position */ +#define MXC_F_GCR_PCLKDIS0_DMA0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_DMA0_POS)) /**< PCLKDIS0_DMA0 Mask */ -#define MXC_F_GCR_PCLKDIS0_SPI2_POS 8 /**< PCLKDIS0_SPI2 Position */ -#define MXC_F_GCR_PCLKDIS0_SPI2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI2_POS)) /**< PCLKDIS0_SPI2 Mask */ +#define MXC_F_GCR_PCLKDIS0_SPI_POS 6 /**< PCLKDIS0_SPI Position */ +#define MXC_F_GCR_PCLKDIS0_SPI ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_SPI_POS)) /**< PCLKDIS0_SPI Mask */ -#define MXC_F_GCR_PCLKDIS0_UART0_POS 9 /**< PCLKDIS0_UART0 Position */ -#define MXC_F_GCR_PCLKDIS0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_UART0_POS)) /**< PCLKDIS0_UART0 Mask */ +#define MXC_F_GCR_PCLKDIS0_UART_POS 9 /**< PCLKDIS0_UART Position */ +#define MXC_F_GCR_PCLKDIS0_UART ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_UART_POS)) /**< PCLKDIS0_UART Mask */ -#define MXC_F_GCR_PCLKDIS0_UART1_POS 10 /**< PCLKDIS0_UART1 Position */ -#define MXC_F_GCR_PCLKDIS0_UART1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_UART1_POS)) /**< PCLKDIS0_UART1 Mask */ - -#define MXC_F_GCR_PCLKDIS0_I2C0_POS 13 /**< PCLKDIS0_I2C0 Position */ -#define MXC_F_GCR_PCLKDIS0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_I2C0_POS)) /**< PCLKDIS0_I2C0 Mask */ +#define MXC_F_GCR_PCLKDIS0_I3C_POS 13 /**< PCLKDIS0_I3C Position */ +#define MXC_F_GCR_PCLKDIS0_I3C ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_I3C_POS)) /**< PCLKDIS0_I3C Mask */ #define MXC_F_GCR_PCLKDIS0_TMR0_POS 15 /**< PCLKDIS0_TMR0 Position */ #define MXC_F_GCR_PCLKDIS0_TMR0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR0_POS)) /**< PCLKDIS0_TMR0 Mask */ @@ -489,21 +401,6 @@ typedef struct { #define MXC_F_GCR_PCLKDIS0_TMR5_POS 20 /**< PCLKDIS0_TMR5 Position */ #define MXC_F_GCR_PCLKDIS0_TMR5 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR5_POS)) /**< PCLKDIS0_TMR5 Mask */ -#define MXC_F_GCR_PCLKDIS0_ADC_POS 23 /**< PCLKDIS0_ADC Position */ -#define MXC_F_GCR_PCLKDIS0_ADC ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_ADC_POS)) /**< PCLKDIS0_ADC Mask */ - -#define MXC_F_GCR_PCLKDIS0_TMR6_POS 24 /**< PCLKDIS0_TMR6 Position */ -#define MXC_F_GCR_PCLKDIS0_TMR6 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR6_POS)) /**< PCLKDIS0_TMR6 Mask */ - -#define MXC_F_GCR_PCLKDIS0_TMR7_POS 25 /**< PCLKDIS0_TMR7 Position */ -#define MXC_F_GCR_PCLKDIS0_TMR7 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_TMR7_POS)) /**< PCLKDIS0_TMR7 Mask */ - -#define MXC_F_GCR_PCLKDIS0_I2C1_POS 28 /**< PCLKDIS0_I2C1 Position */ -#define MXC_F_GCR_PCLKDIS0_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_I2C1_POS)) /**< PCLKDIS0_I2C1 Mask */ - -#define MXC_F_GCR_PCLKDIS0_PT_POS 29 /**< PCLKDIS0_PT Position */ -#define MXC_F_GCR_PCLKDIS0_PT ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS0_PT_POS)) /**< PCLKDIS0_PT Mask */ - /**@} end of group GCR_PCLKDIS0_Register */ /** @@ -515,66 +412,6 @@ typedef struct { #define MXC_F_GCR_MEMCTRL_FWS_POS 0 /**< MEMCTRL_FWS Position */ #define MXC_F_GCR_MEMCTRL_FWS ((uint32_t)(0x7UL << MXC_F_GCR_MEMCTRL_FWS_POS)) /**< MEMCTRL_FWS Mask */ -#define MXC_F_GCR_MEMCTRL_SRAM_WS_POS 4 /**< MEMCTRL_SRAM_WS Position */ -#define MXC_F_GCR_MEMCTRL_SRAM_WS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_SRAM_WS_POS)) /**< MEMCTRL_SRAM_WS Mask */ - -#define MXC_F_GCR_MEMCTRL_ROM1_WS_POS 7 /**< MEMCTRL_ROM1_WS Position */ -#define MXC_F_GCR_MEMCTRL_ROM1_WS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_ROM1_WS_POS)) /**< MEMCTRL_ROM1_WS Mask */ - -#define MXC_F_GCR_MEMCTRL_RAM0_WS_POS 8 /**< MEMCTRL_RAM0_WS Position */ -#define MXC_F_GCR_MEMCTRL_RAM0_WS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM0_WS_POS)) /**< MEMCTRL_RAM0_WS Mask */ - -#define MXC_F_GCR_MEMCTRL_RAM1_WS_POS 9 /**< MEMCTRL_RAM1_WS Position */ -#define MXC_F_GCR_MEMCTRL_RAM1_WS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM1_WS_POS)) /**< MEMCTRL_RAM1_WS Mask */ - -#define MXC_F_GCR_MEMCTRL_RAM2_WS_POS 10 /**< MEMCTRL_RAM2_WS Position */ -#define MXC_F_GCR_MEMCTRL_RAM2_WS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM2_WS_POS)) /**< MEMCTRL_RAM2_WS Mask */ - -#define MXC_F_GCR_MEMCTRL_RAM3_WS_POS 11 /**< MEMCTRL_RAM3_WS Position */ -#define MXC_F_GCR_MEMCTRL_RAM3_WS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM3_WS_POS)) /**< MEMCTRL_RAM3_WS Mask */ - -#define MXC_F_GCR_MEMCTRL_RAM4_WS_POS 12 /**< MEMCTRL_RAM4_WS Position */ -#define MXC_F_GCR_MEMCTRL_RAM4_WS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM4_WS_POS)) /**< MEMCTRL_RAM4_WS Mask */ - -#define MXC_F_GCR_MEMCTRL_RAM5_WS_POS 13 /**< MEMCTRL_RAM5_WS Position */ -#define MXC_F_GCR_MEMCTRL_RAM5_WS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM5_WS_POS)) /**< MEMCTRL_RAM5_WS Mask */ - -#define MXC_F_GCR_MEMCTRL_RAM0LS_EN_POS 16 /**< MEMCTRL_RAM0LS_EN Position */ -#define MXC_F_GCR_MEMCTRL_RAM0LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM0LS_EN_POS)) /**< MEMCTRL_RAM0LS_EN Mask */ - -#define MXC_F_GCR_MEMCTRL_RAM1LS_EN_POS 17 /**< MEMCTRL_RAM1LS_EN Position */ -#define MXC_F_GCR_MEMCTRL_RAM1LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM1LS_EN_POS)) /**< MEMCTRL_RAM1LS_EN Mask */ - -#define MXC_F_GCR_MEMCTRL_RAM2LS_EN_POS 18 /**< MEMCTRL_RAM2LS_EN Position */ -#define MXC_F_GCR_MEMCTRL_RAM2LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM2LS_EN_POS)) /**< MEMCTRL_RAM2LS_EN Mask */ - -#define MXC_F_GCR_MEMCTRL_RAM3LS_EN_POS 19 /**< MEMCTRL_RAM3LS_EN Position */ -#define MXC_F_GCR_MEMCTRL_RAM3LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM3LS_EN_POS)) /**< MEMCTRL_RAM3LS_EN Mask */ - -#define MXC_F_GCR_MEMCTRL_RAM4LS_EN_POS 20 /**< MEMCTRL_RAM4LS_EN Position */ -#define MXC_F_GCR_MEMCTRL_RAM4LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM4LS_EN_POS)) /**< MEMCTRL_RAM4LS_EN Mask */ - -#define MXC_F_GCR_MEMCTRL_RAM5LS_EN_POS 21 /**< MEMCTRL_RAM5LS_EN Position */ -#define MXC_F_GCR_MEMCTRL_RAM5LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_RAM5LS_EN_POS)) /**< MEMCTRL_RAM5LS_EN Mask */ - -#define MXC_F_GCR_MEMCTRL_ICCLS_EN_POS 24 /**< MEMCTRL_ICCLS_EN Position */ -#define MXC_F_GCR_MEMCTRL_ICCLS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_ICCLS_EN_POS)) /**< MEMCTRL_ICCLS_EN Mask */ - -#define MXC_F_GCR_MEMCTRL_ICCXIPLS_EN_POS 25 /**< MEMCTRL_ICCXIPLS_EN Position */ -#define MXC_F_GCR_MEMCTRL_ICCXIPLS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_ICCXIPLS_EN_POS)) /**< MEMCTRL_ICCXIPLS_EN Mask */ - -#define MXC_F_GCR_MEMCTRL_SRCCLS_EN_POS 26 /**< MEMCTRL_SRCCLS_EN Position */ -#define MXC_F_GCR_MEMCTRL_SRCCLS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_SRCCLS_EN_POS)) /**< MEMCTRL_SRCCLS_EN Mask */ - -#define MXC_F_GCR_MEMCTRL_USBLS_EN_POS 28 /**< MEMCTRL_USBLS_EN Position */ -#define MXC_F_GCR_MEMCTRL_USBLS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_USBLS_EN_POS)) /**< MEMCTRL_USBLS_EN Mask */ - -#define MXC_F_GCR_MEMCTRL_ROM0LS_EN_POS 29 /**< MEMCTRL_ROM0LS_EN Position */ -#define MXC_F_GCR_MEMCTRL_ROM0LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_ROM0LS_EN_POS)) /**< MEMCTRL_ROM0LS_EN Mask */ - -#define MXC_F_GCR_MEMCTRL_ROM1LS_EN_POS 30 /**< MEMCTRL_ROM1LS_EN Position */ -#define MXC_F_GCR_MEMCTRL_ROM1LS_EN ((uint32_t)(0x1UL << MXC_F_GCR_MEMCTRL_ROM1LS_EN_POS)) /**< MEMCTRL_ROM1LS_EN Mask */ - /**@} end of group GCR_MEMCTRL_Register */ /** @@ -583,42 +420,24 @@ typedef struct { * @brief Memory Zeroize Control. * @{ */ -#define MXC_F_GCR_MEMZ_RAM0_POS 0 /**< MEMZ_RAM0 Position */ -#define MXC_F_GCR_MEMZ_RAM0 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM0_POS)) /**< MEMZ_RAM0 Mask */ +#define MXC_F_GCR_MEMZ_SRAM0_POS 0 /**< MEMZ_SRAM0 Position */ +#define MXC_F_GCR_MEMZ_SRAM0 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_SRAM0_POS)) /**< MEMZ_SRAM0 Mask */ -#define MXC_F_GCR_MEMZ_RAM1_POS 1 /**< MEMZ_RAM1 Position */ -#define MXC_F_GCR_MEMZ_RAM1 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM1_POS)) /**< MEMZ_RAM1 Mask */ +#define MXC_F_GCR_MEMZ_SRAM1_POS 1 /**< MEMZ_SRAM1 Position */ +#define MXC_F_GCR_MEMZ_SRAM1 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_SRAM1_POS)) /**< MEMZ_SRAM1 Mask */ -#define MXC_F_GCR_MEMZ_RAM2_POS 2 /**< MEMZ_RAM2 Position */ -#define MXC_F_GCR_MEMZ_RAM2 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM2_POS)) /**< MEMZ_RAM2 Mask */ +#define MXC_F_GCR_MEMZ_SRAM2_POS 2 /**< MEMZ_SRAM2 Position */ +#define MXC_F_GCR_MEMZ_SRAM2 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_SRAM2_POS)) /**< MEMZ_SRAM2 Mask */ -#define MXC_F_GCR_MEMZ_RAM3_POS 3 /**< MEMZ_RAM3 Position */ -#define MXC_F_GCR_MEMZ_RAM3 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM3_POS)) /**< MEMZ_RAM3 Mask */ +#define MXC_F_GCR_MEMZ_SRAM3_POS 3 /**< MEMZ_SRAM3 Position */ +#define MXC_F_GCR_MEMZ_SRAM3 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_SRAM3_POS)) /**< MEMZ_SRAM3 Mask */ -#define MXC_F_GCR_MEMZ_RAM4_POS 4 /**< MEMZ_RAM4 Position */ -#define MXC_F_GCR_MEMZ_RAM4 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM4_POS)) /**< MEMZ_RAM4 Mask */ +#define MXC_F_GCR_MEMZ_SRAM4_POS 4 /**< MEMZ_SRAM4 Position */ +#define MXC_F_GCR_MEMZ_SRAM4 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_SRAM4_POS)) /**< MEMZ_SRAM4 Mask */ -#define MXC_F_GCR_MEMZ_RAM5_POS 5 /**< MEMZ_RAM5 Position */ -#define MXC_F_GCR_MEMZ_RAM5 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM5_POS)) /**< MEMZ_RAM5 Mask */ - -#define MXC_F_GCR_MEMZ_RAM6_POS 6 /**< MEMZ_RAM6 Position */ -#define MXC_F_GCR_MEMZ_RAM6 ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_RAM6_POS)) /**< MEMZ_RAM6 Mask */ - -#define MXC_F_GCR_MEMZ_ICC_POS 8 /**< MEMZ_ICC Position */ +#define MXC_F_GCR_MEMZ_ICC_POS 5 /**< MEMZ_ICC Position */ #define MXC_F_GCR_MEMZ_ICC ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_ICC_POS)) /**< MEMZ_ICC Mask */ -#define MXC_F_GCR_MEMZ_ICCXIP_POS 9 /**< MEMZ_ICCXIP Position */ -#define MXC_F_GCR_MEMZ_ICCXIP ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_ICCXIP_POS)) /**< MEMZ_ICCXIP Mask */ - -#define MXC_F_GCR_MEMZ_SRCCDATA_POS 10 /**< MEMZ_SRCCDATA Position */ -#define MXC_F_GCR_MEMZ_SRCCDATA ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_SRCCDATA_POS)) /**< MEMZ_SRCCDATA Mask */ - -#define MXC_F_GCR_MEMZ_SRCCTAG_POS 11 /**< MEMZ_SRCCTAG Position */ -#define MXC_F_GCR_MEMZ_SRCCTAG ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_SRCCTAG_POS)) /**< MEMZ_SRCCTAG Mask */ - -#define MXC_F_GCR_MEMZ_USBFIFO_POS 13 /**< MEMZ_USBFIFO Position */ -#define MXC_F_GCR_MEMZ_USBFIFO ((uint32_t)(0x1UL << MXC_F_GCR_MEMZ_USBFIFO_POS)) /**< MEMZ_USBFIFO Mask */ - /**@} end of group GCR_MEMZ_Register */ /** @@ -630,15 +449,6 @@ typedef struct { #define MXC_F_GCR_SYSST_ICELOCK_POS 0 /**< SYSST_ICELOCK Position */ #define MXC_F_GCR_SYSST_ICELOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_ICELOCK_POS)) /**< SYSST_ICELOCK Mask */ -#define MXC_F_GCR_SYSST_CODEAUTHERR_POS 1 /**< SYSST_CODEAUTHERR Position */ -#define MXC_F_GCR_SYSST_CODEAUTHERR ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_CODEAUTHERR_POS)) /**< SYSST_CODEAUTHERR Mask */ - -#define MXC_F_GCR_SYSST_DATAAUTHERR_POS 2 /**< SYSST_DATAAUTHERR Position */ -#define MXC_F_GCR_SYSST_DATAAUTHERR ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_DATAAUTHERR_POS)) /**< SYSST_DATAAUTHERR Mask */ - -#define MXC_F_GCR_SYSST_SCMEMF_POS 5 /**< SYSST_SCMEMF Position */ -#define MXC_F_GCR_SYSST_SCMEMF ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_SCMEMF_POS)) /**< SYSST_SCMEMF Mask */ - /**@} end of group GCR_SYSST_Register */ /** @@ -647,45 +457,12 @@ typedef struct { * @brief Reset 1. * @{ */ -#define MXC_F_GCR_RST1_I2C1_POS 0 /**< RST1_I2C1 Position */ -#define MXC_F_GCR_RST1_I2C1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C1_POS)) /**< RST1_I2C1 Mask */ - -#define MXC_F_GCR_RST1_PT_POS 1 /**< RST1_PT Position */ -#define MXC_F_GCR_RST1_PT ((uint32_t)(0x1UL << MXC_F_GCR_RST1_PT_POS)) /**< RST1_PT Mask */ - -#define MXC_F_GCR_RST1_OWIRE_POS 7 /**< RST1_OWIRE Position */ -#define MXC_F_GCR_RST1_OWIRE ((uint32_t)(0x1UL << MXC_F_GCR_RST1_OWIRE_POS)) /**< RST1_OWIRE Mask */ - -#define MXC_F_GCR_RST1_WDT1_POS 8 /**< RST1_WDT1 Position */ -#define MXC_F_GCR_RST1_WDT1 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_WDT1_POS)) /**< RST1_WDT1 Mask */ - #define MXC_F_GCR_RST1_CRC_POS 9 /**< RST1_CRC Position */ #define MXC_F_GCR_RST1_CRC ((uint32_t)(0x1UL << MXC_F_GCR_RST1_CRC_POS)) /**< RST1_CRC Mask */ #define MXC_F_GCR_RST1_AES_POS 10 /**< RST1_AES Position */ #define MXC_F_GCR_RST1_AES ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AES_POS)) /**< RST1_AES Mask */ -#define MXC_F_GCR_RST1_I2S_POS 13 /**< RST1_I2S Position */ -#define MXC_F_GCR_RST1_I2S ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2S_POS)) /**< RST1_I2S Mask */ - -#define MXC_F_GCR_RST1_AC_POS 14 /**< RST1_AC Position */ -#define MXC_F_GCR_RST1_AC ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AC_POS)) /**< RST1_AC Mask */ - -#define MXC_F_GCR_RST1_SEMA_POS 16 /**< RST1_SEMA Position */ -#define MXC_F_GCR_RST1_SEMA ((uint32_t)(0x1UL << MXC_F_GCR_RST1_SEMA_POS)) /**< RST1_SEMA Mask */ - -#define MXC_F_GCR_RST1_I2C2_POS 17 /**< RST1_I2C2 Position */ -#define MXC_F_GCR_RST1_I2C2 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_I2C2_POS)) /**< RST1_I2C2 Mask */ - -#define MXC_F_GCR_RST1_UART3_POS 18 /**< RST1_UART3 Position */ -#define MXC_F_GCR_RST1_UART3 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_UART3_POS)) /**< RST1_UART3 Mask */ - -#define MXC_F_GCR_RST1_UART4_POS 19 /**< RST1_UART4 Position */ -#define MXC_F_GCR_RST1_UART4 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_UART4_POS)) /**< RST1_UART4 Mask */ - -#define MXC_F_GCR_RST1_UART5_POS 20 /**< RST1_UART5 Position */ -#define MXC_F_GCR_RST1_UART5 ((uint32_t)(0x1UL << MXC_F_GCR_RST1_UART5_POS)) /**< RST1_UART5 Mask */ - /**@} end of group GCR_RST1_Register */ /** @@ -694,50 +471,20 @@ typedef struct { * @brief Peripheral Clock Disable. * @{ */ -#define MXC_F_GCR_PCLKDIS1_BTLE_POS 0 /**< PCLKDIS1_BTLE Position */ -#define MXC_F_GCR_PCLKDIS1_BTLE ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_BTLE_POS)) /**< PCLKDIS1_BTLE Mask */ - -#define MXC_F_GCR_PCLKDIS1_UART2_POS 1 /**< PCLKDIS1_UART2 Position */ -#define MXC_F_GCR_PCLKDIS1_UART2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_UART2_POS)) /**< PCLKDIS1_UART2 Mask */ - #define MXC_F_GCR_PCLKDIS1_TRNG_POS 2 /**< PCLKDIS1_TRNG Position */ #define MXC_F_GCR_PCLKDIS1_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_TRNG_POS)) /**< PCLKDIS1_TRNG Mask */ -#define MXC_F_GCR_PCLKDIS1_WDT0_POS 4 /**< PCLKDIS1_WDT0 Position */ -#define MXC_F_GCR_PCLKDIS1_WDT0 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_WDT0_POS)) /**< PCLKDIS1_WDT0 Mask */ - -#define MXC_F_GCR_PCLKDIS1_WDT1_POS 5 /**< PCLKDIS1_WDT1 Position */ -#define MXC_F_GCR_PCLKDIS1_WDT1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_WDT1_POS)) /**< PCLKDIS1_WDT1 Mask */ - -#define MXC_F_GCR_PCLKDIS1_SRCC_POS 7 /**< PCLKDIS1_SRCC Position */ -#define MXC_F_GCR_PCLKDIS1_SRCC ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_SRCC_POS)) /**< PCLKDIS1_SRCC Mask */ - -#define MXC_F_GCR_PCLKDIS1_SEMA_POS 9 /**< PCLKDIS1_SEMA Position */ -#define MXC_F_GCR_PCLKDIS1_SEMA ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_SEMA_POS)) /**< PCLKDIS1_SEMA Mask */ - -#define MXC_F_GCR_PCLKDIS1_OWIRE_POS 13 /**< PCLKDIS1_OWIRE Position */ -#define MXC_F_GCR_PCLKDIS1_OWIRE ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_OWIRE_POS)) /**< PCLKDIS1_OWIRE Mask */ - #define MXC_F_GCR_PCLKDIS1_CRC_POS 14 /**< PCLKDIS1_CRC Position */ #define MXC_F_GCR_PCLKDIS1_CRC ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_CRC_POS)) /**< PCLKDIS1_CRC Mask */ #define MXC_F_GCR_PCLKDIS1_AES_POS 15 /**< PCLKDIS1_AES Position */ #define MXC_F_GCR_PCLKDIS1_AES ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_AES_POS)) /**< PCLKDIS1_AES Mask */ -#define MXC_F_GCR_PCLKDIS1_I2S_POS 16 /**< PCLKDIS1_I2S Position */ -#define MXC_F_GCR_PCLKDIS1_I2S ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_I2S_POS)) /**< PCLKDIS1_I2S Mask */ - -#define MXC_F_GCR_PCLKDIS1_I2C2_POS 21 /**< PCLKDIS1_I2C2 Position */ -#define MXC_F_GCR_PCLKDIS1_I2C2 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_I2C2_POS)) /**< PCLKDIS1_I2C2 Mask */ - -#define MXC_F_GCR_PCLKDIS1_UART3_POS 22 /**< PCLKDIS1_UART3 Position */ -#define MXC_F_GCR_PCLKDIS1_UART3 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_UART3_POS)) /**< PCLKDIS1_UART3 Mask */ +#define MXC_F_GCR_PCLKDIS1_SPI_POS 16 /**< PCLKDIS1_SPI Position */ +#define MXC_F_GCR_PCLKDIS1_SPI ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_SPI_POS)) /**< PCLKDIS1_SPI Mask */ -#define MXC_F_GCR_PCLKDIS1_UART4_POS 23 /**< PCLKDIS1_UART4 Position */ -#define MXC_F_GCR_PCLKDIS1_UART4 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_UART4_POS)) /**< PCLKDIS1_UART4 Mask */ - -#define MXC_F_GCR_PCLKDIS1_UART5_POS 24 /**< PCLKDIS1_UART5 Position */ -#define MXC_F_GCR_PCLKDIS1_UART5 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_UART5_POS)) /**< PCLKDIS1_UART5 Mask */ +#define MXC_F_GCR_PCLKDIS1_WDT_POS 27 /**< PCLKDIS1_WDT Position */ +#define MXC_F_GCR_PCLKDIS1_WDT ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_WDT_POS)) /**< PCLKDIS1_WDT Mask */ /**@} end of group GCR_PCLKDIS1_Register */ @@ -747,11 +494,11 @@ typedef struct { * @brief Event Enable Register. * @{ */ -#define MXC_F_GCR_EVENTEN_DMA_POS 0 /**< EVENTEN_DMA Position */ -#define MXC_F_GCR_EVENTEN_DMA ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_DMA_POS)) /**< EVENTEN_DMA Mask */ +#define MXC_F_GCR_EVENTEN_DMA0_POS 0 /**< EVENTEN_DMA0 Position */ +#define MXC_F_GCR_EVENTEN_DMA0 ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_DMA0_POS)) /**< EVENTEN_DMA0 Mask */ -#define MXC_F_GCR_EVENTEN_RX_POS 1 /**< EVENTEN_RX Position */ -#define MXC_F_GCR_EVENTEN_RX ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_RX_POS)) /**< EVENTEN_RX Mask */ +#define MXC_F_GCR_EVENTEN_DMA1_POS 1 /**< EVENTEN_DMA1 Position */ +#define MXC_F_GCR_EVENTEN_DMA1 ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_DMA1_POS)) /**< EVENTEN_DMA1 Mask */ #define MXC_F_GCR_EVENTEN_TX_POS 2 /**< EVENTEN_TX Position */ #define MXC_F_GCR_EVENTEN_TX ((uint32_t)(0x1UL << MXC_F_GCR_EVENTEN_TX_POS)) /**< EVENTEN_TX Mask */ @@ -778,126 +525,26 @@ typedef struct { #define MXC_F_GCR_SYSINTEN_ICEUNLOCK_POS 0 /**< SYSINTEN_ICEUNLOCK Position */ #define MXC_F_GCR_SYSINTEN_ICEUNLOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSINTEN_ICEUNLOCK_POS)) /**< SYSINTEN_ICEUNLOCK Mask */ -#define MXC_F_GCR_SYSINTEN_CIE_POS 1 /**< SYSINTEN_CIE Position */ -#define MXC_F_GCR_SYSINTEN_CIE ((uint32_t)(0x1UL << MXC_F_GCR_SYSINTEN_CIE_POS)) /**< SYSINTEN_CIE Mask */ - -#define MXC_F_GCR_SYSINTEN_SCMF_POS 5 /**< SYSINTEN_SCMF Position */ -#define MXC_F_GCR_SYSINTEN_SCMF ((uint32_t)(0x1UL << MXC_F_GCR_SYSINTEN_SCMF_POS)) /**< SYSINTEN_SCMF Mask */ - /**@} end of group GCR_SYSINTEN_Register */ -/** - * @ingroup gcr_registers - * @defgroup GCR_IPOCNT GCR_IPOCNT - * @brief IPO Warmup Count Register. - * @{ - */ -#define MXC_F_GCR_IPOCNT_WMUPCNT_POS 0 /**< IPOCNT_WMUPCNT Position */ -#define MXC_F_GCR_IPOCNT_WMUPCNT ((uint32_t)(0x3FFUL << MXC_F_GCR_IPOCNT_WMUPCNT_POS)) /**< IPOCNT_WMUPCNT Mask */ - -/**@} end of group GCR_IPOCNT_Register */ - /** * @ingroup gcr_registers * @defgroup GCR_ECCERR GCR_ECCERR * @brief ECC Error Register * @{ */ -#define MXC_F_GCR_ECCERR_RAM0_POS 0 /**< ECCERR_RAM0 Position */ -#define MXC_F_GCR_ECCERR_RAM0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM0_POS)) /**< ECCERR_RAM0 Mask */ - -#define MXC_F_GCR_ECCERR_RAM1_POS 1 /**< ECCERR_RAM1 Position */ -#define MXC_F_GCR_ECCERR_RAM1 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM1_POS)) /**< ECCERR_RAM1 Mask */ - -#define MXC_F_GCR_ECCERR_RAM2_POS 2 /**< ECCERR_RAM2 Position */ -#define MXC_F_GCR_ECCERR_RAM2 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM2_POS)) /**< ECCERR_RAM2 Mask */ - -#define MXC_F_GCR_ECCERR_RAM3_POS 3 /**< ECCERR_RAM3 Position */ -#define MXC_F_GCR_ECCERR_RAM3 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM3_POS)) /**< ECCERR_RAM3 Mask */ - -#define MXC_F_GCR_ECCERR_RAM4_POS 4 /**< ECCERR_RAM4 Position */ -#define MXC_F_GCR_ECCERR_RAM4 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM4_POS)) /**< ECCERR_RAM4 Mask */ - -#define MXC_F_GCR_ECCERR_RAM5_POS 5 /**< ECCERR_RAM5 Position */ -#define MXC_F_GCR_ECCERR_RAM5 ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_RAM5_POS)) /**< ECCERR_RAM5 Mask */ - -#define MXC_F_GCR_ECCERR_ICC_POS 8 /**< ECCERR_ICC Position */ -#define MXC_F_GCR_ECCERR_ICC ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_ICC_POS)) /**< ECCERR_ICC Mask */ - -#define MXC_F_GCR_ECCERR_ICCXIP_POS 10 /**< ECCERR_ICCXIP Position */ -#define MXC_F_GCR_ECCERR_ICCXIP ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_ICCXIP_POS)) /**< ECCERR_ICCXIP Mask */ - -#define MXC_F_GCR_ECCERR_FLASH_POS 11 /**< ECCERR_FLASH Position */ +#define MXC_F_GCR_ECCERR_FLASH_POS 0 /**< ECCERR_FLASH Position */ #define MXC_F_GCR_ECCERR_FLASH ((uint32_t)(0x1UL << MXC_F_GCR_ECCERR_FLASH_POS)) /**< ECCERR_FLASH Mask */ /**@} end of group GCR_ECCERR_Register */ -/** - * @ingroup gcr_registers - * @defgroup GCR_ECCCED GCR_ECCCED - * @brief ECC Not Double Error Detect Register - * @{ - */ -#define MXC_F_GCR_ECCCED_RAM0_POS 0 /**< ECCCED_RAM0 Position */ -#define MXC_F_GCR_ECCCED_RAM0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM0_POS)) /**< ECCCED_RAM0 Mask */ - -#define MXC_F_GCR_ECCCED_RAM1_POS 1 /**< ECCCED_RAM1 Position */ -#define MXC_F_GCR_ECCCED_RAM1 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM1_POS)) /**< ECCCED_RAM1 Mask */ - -#define MXC_F_GCR_ECCCED_RAM2_POS 2 /**< ECCCED_RAM2 Position */ -#define MXC_F_GCR_ECCCED_RAM2 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM2_POS)) /**< ECCCED_RAM2 Mask */ - -#define MXC_F_GCR_ECCCED_RAM3_POS 3 /**< ECCCED_RAM3 Position */ -#define MXC_F_GCR_ECCCED_RAM3 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM3_POS)) /**< ECCCED_RAM3 Mask */ - -#define MXC_F_GCR_ECCCED_RAM4_POS 4 /**< ECCCED_RAM4 Position */ -#define MXC_F_GCR_ECCCED_RAM4 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM4_POS)) /**< ECCCED_RAM4 Mask */ - -#define MXC_F_GCR_ECCCED_RAM5_POS 5 /**< ECCCED_RAM5 Position */ -#define MXC_F_GCR_ECCCED_RAM5 ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_RAM5_POS)) /**< ECCCED_RAM5 Mask */ - -#define MXC_F_GCR_ECCCED_ICC_POS 8 /**< ECCCED_ICC Position */ -#define MXC_F_GCR_ECCCED_ICC ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_ICC_POS)) /**< ECCCED_ICC Mask */ - -#define MXC_F_GCR_ECCCED_ICCXIP_POS 10 /**< ECCCED_ICCXIP Position */ -#define MXC_F_GCR_ECCCED_ICCXIP ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_ICCXIP_POS)) /**< ECCCED_ICCXIP Mask */ - -#define MXC_F_GCR_ECCCED_FLASH_POS 11 /**< ECCCED_FLASH Position */ -#define MXC_F_GCR_ECCCED_FLASH ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_FLASH_POS)) /**< ECCCED_FLASH Mask */ - -/**@} end of group GCR_ECCCED_Register */ - /** * @ingroup gcr_registers * @defgroup GCR_ECCINTEN GCR_ECCINTEN * @brief ECC Interrupt Enable Register * @{ */ -#define MXC_F_GCR_ECCINTEN_RAM0_POS 0 /**< ECCINTEN_RAM0 Position */ -#define MXC_F_GCR_ECCINTEN_RAM0 ((uint32_t)(0x1UL << MXC_F_GCR_ECCINTEN_RAM0_POS)) /**< ECCINTEN_RAM0 Mask */ - -#define MXC_F_GCR_ECCINTEN_RAM1_POS 1 /**< ECCINTEN_RAM1 Position */ -#define MXC_F_GCR_ECCINTEN_RAM1 ((uint32_t)(0x1UL << MXC_F_GCR_ECCINTEN_RAM1_POS)) /**< ECCINTEN_RAM1 Mask */ - -#define MXC_F_GCR_ECCINTEN_RAM2_POS 2 /**< ECCINTEN_RAM2 Position */ -#define MXC_F_GCR_ECCINTEN_RAM2 ((uint32_t)(0x1UL << MXC_F_GCR_ECCINTEN_RAM2_POS)) /**< ECCINTEN_RAM2 Mask */ - -#define MXC_F_GCR_ECCINTEN_RAM3_POS 3 /**< ECCINTEN_RAM3 Position */ -#define MXC_F_GCR_ECCINTEN_RAM3 ((uint32_t)(0x1UL << MXC_F_GCR_ECCINTEN_RAM3_POS)) /**< ECCINTEN_RAM3 Mask */ - -#define MXC_F_GCR_ECCINTEN_RAM4_POS 4 /**< ECCINTEN_RAM4 Position */ -#define MXC_F_GCR_ECCINTEN_RAM4 ((uint32_t)(0x1UL << MXC_F_GCR_ECCINTEN_RAM4_POS)) /**< ECCINTEN_RAM4 Mask */ - -#define MXC_F_GCR_ECCINTEN_RAM5_POS 5 /**< ECCINTEN_RAM5 Position */ -#define MXC_F_GCR_ECCINTEN_RAM5 ((uint32_t)(0x1UL << MXC_F_GCR_ECCINTEN_RAM5_POS)) /**< ECCINTEN_RAM5 Mask */ - -#define MXC_F_GCR_ECCINTEN_ICC_POS 8 /**< ECCINTEN_ICC Position */ -#define MXC_F_GCR_ECCINTEN_ICC ((uint32_t)(0x1UL << MXC_F_GCR_ECCINTEN_ICC_POS)) /**< ECCINTEN_ICC Mask */ - -#define MXC_F_GCR_ECCINTEN_ICCXIP_POS 10 /**< ECCINTEN_ICCXIP Position */ -#define MXC_F_GCR_ECCINTEN_ICCXIP ((uint32_t)(0x1UL << MXC_F_GCR_ECCINTEN_ICCXIP_POS)) /**< ECCINTEN_ICCXIP Mask */ - -#define MXC_F_GCR_ECCINTEN_FLASH_POS 11 /**< ECCINTEN_FLASH Position */ +#define MXC_F_GCR_ECCINTEN_FLASH_POS 0 /**< ECCINTEN_FLASH Position */ #define MXC_F_GCR_ECCINTEN_FLASH ((uint32_t)(0x1UL << MXC_F_GCR_ECCINTEN_FLASH_POS)) /**< ECCINTEN_FLASH Mask */ /**@} end of group GCR_ECCINTEN_Register */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h deleted file mode 100644 index c6c60785f1e..00000000000 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h +++ /dev/null @@ -1,757 +0,0 @@ -/** - * @file max32657.h - * @brief Device-specific perhiperal header file - */ - -/****************************************************************************** - * - * Analog Devices, Inc.), - * Copyright (C) 2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ******************************************************************************/ - -#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_MAX32657_H_ -#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_MAX32657_H_ - -#ifndef TARGET_NUM -#define TARGET_NUM 32657 -#endif - -#define MXC_NUMCORES 1 - -#include - -#ifndef FALSE -#define FALSE (0) -#endif - -#ifndef TRUE -#define TRUE (1) -#endif - -/* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */ -#if defined(__GNUC__) -#ifndef __weak -#define __weak __attribute__((weak)) -#endif - -#elif defined(__CC_ARM) - -#define inline __inline -#pragma anon_unions - -#endif - -/* ================================================================================ */ -/* ================== Interrupt Number Table Section ================== */ -/* ================================================================================ */ - -// clang-format off -typedef enum { - NonMaskableInt_IRQn = -14, - HardFault_IRQn = -13, - MemoryManagement_IRQn = -12, - BusFault_IRQn = -11, - UsageFault_IRQn = -10, - SVCall_IRQn = -5, - DebugMonitor_IRQn = -4, - PendSV_IRQn = -2, - SysTick_IRQn = -1, - - /* Device-specific interrupt sources (external to ARM core) */ - /* table entry number */ - /* |||| */ - /* |||| table offset address */ - /* vvvv vvvvvv */ - - ICE_IRQn = 0, /* 0x10 0x0040 16: ICE Unlock */ - WDT_IRQn, /* 0x11 0x0044 17: Watchdog Timer */ - RTC_IRQn, /* 0x12 0x0048 18: RTC */ - TRNG_IRQn, /* 0x13 0x004C 19: True Random Number Generator */ - TMR0_IRQn, /* 0x14 0x0050 20: Timer 0 */ - TMR1_IRQn, /* 0x15 0x0054 21: Timer 1 */ - TMR2_IRQn, /* 0x16 0x0058 22: Timer 2 */ - TMR3_IRQn, /* 0x17 0x005C 23: Timer 3 */ - TMR4_IRQn, /* 0x18 0x0060 24: Timer 4 */ - TMR5_IRQn, /* 0x19 0x0064 25: Timer 5 */ - I3C_IRQn, /* 0x1A 0x0068 26: I3C */ - UART_IRQn, /* 0x1B 0x006C 27: UART */ - SPI_IRQn, /* 0x1C 0x0070 28: SPI */ - FLC_IRQn, /* 0x1D 0x0074 29: FLC */ - GPIO0_IRQn, /* 0x1E 0x0078 30: GPIO0 */ - RSV15_IRQn, /* 0x1F 0x007C 31: Reserved */ - DMA0_CH0_IRQn, /* 0x20 0x0080 32: DMA0 Channel 0 */ - DMA0_CH1_IRQn, /* 0x21 0x0084 33: DMA0 Channel 1 */ - DMA0_CH2_IRQn, /* 0x22 0x0088 34: DMA0 Channel 2 */ - DMA0_CH3_IRQn, /* 0x23 0x008C 35: DMA0 Channel 3 */ - DMA1_CH0_IRQn, /* 0x24 0x0090 36: DMA1 Channel 0 */ - DMA1_CH1_IRQn, /* 0x25 0x0094 37: DMA1 Channel 1 */ - DMA1_CH2_IRQn, /* 0x26 0x0098 38: DMA1 CHannel 2 */ - DMA1_CH3_IRQn, /* 0x27 0x009C 39: DMA1 Channel 3 */ - WUT0_IRQn, /* 0x28 0x00A0 40: Wakeup Timer 0 */ - WUT1_IRQn, /* 0x29 0x00A4 41: Wakeup TImer 1 */ - GPIOWAKE_IRQn, /* 0x2A 0x00A8 42: GPIO Wakeup */ - CRC_IRQn, /* 0x2B 0x00AC 43: CRC */ - AES_IRQn, /* 0x2C 0x00B0 44: AES */ - ERFO_IRQn, /* 0x2D 0x00B4 45: ERFO Ready */ - BOOST_IRQn, /* 0x2E 0x00B8 46: Boost Controller */ - ECC_IRQn, /* 0x2F 0x00BC 47: ECC */ - BTLE_TX_DONE_IRQn, /* 0x30 0x00C0 48: BTLE TX Done */ - BTLE_RX_RCVD_IRQn, /* 0x31 0x00C4 49: BTLE RX Received */ - BTLE_RX_ENG_DET_IRQn, /* 0x32 0x00C8 50: BTLE RX Energy Detected */ - BTLE_SFD_DET_IRQn, /* 0x33 0x00CC 51: BTLE SFD Detected */ - BTLE_SFD_TO_IRQn, /* 0x34 0x00D0 52: BTLE SFD Timeout */ - BTLE_GP_EVENT_IRQn, /* 0x35 0x00D4 53: BTLE BTLE Timestamp */ - BTLE_CFO_IRQn, /* 0x36 0x00D8 54: BTLE CFO Done */ - BTLE_SIG_DET_IRQn, /* 0x37 0x00DC 55: BTLE Signal Detected */ - BTLE_AGC_EVENT_IRQn, /* 0x38 0x00E0 56: BTLE AGC Event */ - BTLE_RFFE_SPIM_IRQn, /* 0x39 0x00E4 57: BTLE RFFE SPIM Done */ - BTLE_TX_AES_IRQn, /* 0x3A 0x00E8 58: BTLE TX AES Done */ - BTLE_RX_AES_IRQn, /* 0x3B 0x00EC 59: BTLE RX AES Done */ - BTLE_INV_APB_ADDR_IRQn, /* 0x3C 0x00F0 60: BTLE Invalid APB Address */ - BTLE_IQ_DATA_VALID_IRQn, /* 0x3D 0x00F4 61:BTLE IQ Data Valid */ - BTLE_XXXX_IRQn, /* 0x3E 0x00F8 62: BTLE XXXX TODO(ME30): Verify BTLE IRQs */ - RSV47_IRQn, /* 0x3F 0x00FC 63: Reserved */ - MPC_IRQn, /* 0x40 0x0100 64: MPC Combined (Secure) */ - PPC_IRQn, /* 0x41 0x0104 65: PPC Combined (Secure) */ - RSV50_IRQn, /* 0x42 0x0108 66: Reserved */ - RSV51_IRQn, /* 0x43 0x010C 67: Reserved */ - RSV52_IRQn, /* 0x44 0x0110 68: Reserved */ - RSV53_IRQn, /* 0x45 0x0114 69: Reserved */ - MXC_IRQ_EXT_COUNT, -} IRQn_Type; -// clang-format on - -#define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16) - -/* ================================================================================ */ -/* ================== Processor Section ================== */ -/* ================================================================================ */ - -#define __CM33_REV 0x0000U /**< Cortex-M33 Core revision */ -#define __DSP_PRESENT 1U /**< Presence of DSP */ -#define __FPU_PRESENT 1U /**< Presence of FPU */ -#define __MPU_PRESENT 1U /**< Presence of MPU */ -#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ -#define __TZ_PRESENT 1U /**< Presence of TrustZone */ -#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ -#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ -#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ - -/* ================================================================================ */ -/* ================== Device Specific Memory Section ================== */ -/* ================================================================================ */ - -/* Non-secure Regions */ -#define MXC_FLASH_NS_MEM_BASE 0x01000000UL -#define MXC_FLASH_NS_PAGE_SIZE 0x00002000UL -#define MXC_FLASH_NS_MEM_SIZE 0x00100000UL -#define MXC_SRAM_NS_MEM_BASE 0x20000000UL -#define MXC_SRAM_NS_MEM_SIZE 0x00040000UL - -/* Secure Regions */ -/* ROM is always in secure region. */ -#define MXC_ROM_MEM_BASE 0x00000000UL -#define MXC_ROM_MEM_SIZE 0x00010000UL -#define MXC_FLASH_S_MEM_BASE 0x11000000UL -#define MXC_FLASH_S_PAGE_SIZE 0x00002000UL -#define MXC_FLASH_S_MEM_SIZE 0x00100000UL -#define MXC_INFO_S_MEM_BASE 0x12000000UL -#define MXC_INFO_S_MEM_SIZE 0x00004000UL -#define MXC_SRAM_S_MEM_BASE 0x30000000UL -#define MXC_SRAM_S_MEM_SIZE 0x00040000UL - -/* Secure Region name redefinitions for explicit use */ -#define MXC_FLASH_MEM_BASE MXC_FLASH_S_MEM_BASE -#define MXC_FLASH_PAGE_SIZE MXC_FLASH_S_PAGE_SIZE -#define MXC_FLASH_MEM_SIZE MXC_FLASH_S_MEM_SIZE -#define MXC_INFO_MEM_BASE MXC_INFO_S_MEM_BASE -#define MXC_INFO_MEM_SIZE MXC_INFO_S_MEM_SIZE -#define MXC_SRAM_MEM_BASE MXC_SRAM_S_MEM_BASE -#define MXC_SRAM_MEM_SIZE MXC_SRAM_S_MEM_SIZE - -/* ================================================================================ */ -/* ================ Device Specific Peripheral Section ================ */ -/* ================================================================================ */ - -/* - Base addresses and configuration settings for all MAX78000 peripheral modules. -*/ - -/******************************************************************************/ -/* Global control */ - -/* Non-secure Mapping */ -#define MXC_BASE_GCR_NS ((uint32_t)0x40000000UL) -#define MXC_GCR_NS ((mxc_gcr_regs_t *)MXC_BASE_GCR_NS) - -/* Secure Mapping */ -#define MXC_BASE_GCR_S ((uint32_t)0x50000000UL) -#define MXC_GCR_S ((mxc_gcr_regs_t *)MXC_BASE_GCR_S) - -#define MXC_BASE_GCR MXC_BASE_GCR_S -#define MXC_GCR MXC_GCR_S - -/******************************************************************************/ -/* Non-battery backed SI Registers */ - -/* Non-secure Mapping */ -#define MXC_BASE_SIR_NS ((uint32_t)0x40000400UL) -#define MXC_SIR_NS ((mxc_sir_regs_t *)MXC_BASE_SIR_NS) - -/* Secure Mapping */ -#define MXC_BASE_SIR_S ((uint32_t)0x50000400UL) -#define MXC_SIR_S ((mxc_sir_regs_t *)MXC_BASE_SIR_S) - -#define MXC_BASE_SIR MXC_BASE_SIR_S -#define MXC_SIR MXC_SIR_S - -/******************************************************************************/ -/* Non-Battery Backed Function Control */ - -/* Non-secure Mapping */ -#define MXC_BASE_FCR_NS ((uint32_t)0x40000800UL) -#define MXC_FCR_NS ((mxc_fcr_regs_t *)MXC_BASE_FCR_NS) - -/* Secure Mapping */ -#define MXC_BASE_FCR_S ((uint32_t)0x50000800UL) -#define MXC_FCR_S ((mxc_fcr_regs_t *)MXC_BASE_FCR_S) - -/******************************************************************************/ -/* Windowed Watchdog Timer */ -#define MXC_CFG_WDT_INSTANCES (1) - -/* Non-secure Mapping */ -#define MXC_BASE_WDT_NS ((uint32_t)0x40003000UL) -#define MXC_WDT_NS ((mxc_wdt_regs_t *)MXC_BASE_WDT_NS) - -/* Secure Mapping */ -#define MXC_BASE_WDT_S ((uint32_t)0x50003000UL) -#define MXC_WDT_S ((mxc_wdt_regs_t *)MXC_BASE_WDT_S) - -#define MXC_BASE_WDT MXC_BASE_WDT_S -#define MXC_WDT MXC_WDT_S - -/******************************************************************************/ -/* SVM Controller */ - -/* Non-secure Mapping */ -#define MXC_BASE_SVM_NS ((uint32_t)0x40004800UL) -#define MXC_SVM_NS //TODO(ME30): Add SVM controller registers. - -/* Secure Mapping */ -#define MXC_BASE_SVM_S ((uint32_t)0x50004800UL) -#define MXC_SVM_S //TODO(ME30): Add SVM controller registers. - -#define MXC_BASE_SVM MXC_BASE_SVM_S -#define MXC_SVM //TODO(ME30): Add SVM controller registers. - -/******************************************************************************/ -/* Boost Controller */ - -/* Non-secure Mapping */ -#define MXC_BASE_BOOST_NS ((uint32_t)0x40004C00UL) -#define MXC_BOOST_NS //TODO(ME30): Add Boost controller registers. - -/* Secure Mapping */ -#define MXC_BASE_BOOST_S ((uint32_t)0x50004C00UL) -#define MXC_BOOST_S //TODO(ME30): Add Boost controller registers. - -#define MXC_BASE_BOOST MXC_BASE_BOOST_S -#define MXC_BOOST //TODO(ME30): Add Boost controller registers. - -/******************************************************************************/ -/* Trim System Initalization Register */ - -/* Non-secure Mapping */ -#define MXC_BASE_TRIMSIR_NS ((uint32_t)0x40005400UL) -#define MXC_TRIMSIR_NS ((mxc_trimsir_regs_t *)MXC_BASE_TRIMSIR_NS) - -/* Secure Mapping */ -#define MXC_BASE_TRIMSIR_S ((uint32_t)0x50005400UL) -#define MXC_TRIMSIR_S ((mxc_trimsir_regs_t *)MXC_BASE_TRIMSIR_S) - -#define MXC_BASE_TRIMSIR MXC_BASE_TRIMSIR_S -#define MXC_TRIMSIR MXC_TRIMSIR_S - -/******************************************************************************/ -/* Real Time Clock */ - -/* Non-secure Mapping */ -#define MXC_BASE_RTC_NS ((uint32_t)0x40006000UL) -#define MXC_RTC_NS ((mxc_rtc_regs_t *)MXC_BASE_RTC_NS) - -/* Secure Mapping */ -#define MXC_BASE_RTC_S ((uint32_t)0x50006000UL) -#define MXC_RTC_S ((mxc_rtc_regs_t *)MXC_BASE_RTC_S) - -#define MXC_BASE_RTC MXC_BASE_RTC_S -#define MXC_RTC MXC_RTC_S - -/******************************************************************************/ -/* Wake-Up Timer (WUT) */ -#define MXC_CFG_WUT_INSTANCES (2) - -/* Non-secure Mapping */ -#define MXC_BASE_WUT0_NS ((uint32_t)0x40006400UL) -#define MXC_WUT0_NS ((mxc_wut_regs_t *)MXC_BASE_WUT0_NS) -#define MXC_BASE_WUT1_NS ((uint32_t)0x40006600UL) -#define MXC_WUT1_NS ((mxc_wut_regs_t *)MXC_BASE_WUT1_NS) - -/* Secure Mapping */ -#define MXC_BASE_WUT0_S ((uint32_t)0x50006400UL) -#define MXC_WUT0_S ((mxc_wut_regs_t *)MXC_BASE_WUT0_S) -#define MXC_BASE_WUT1_S ((uint32_t)0x50006600UL) -#define MXC_WUT1_S ((mxc_wut_regs_t *)MXC_BASE_WUT1_S) - -#define MXC_BASE_WUT0 MXC_BASE_WUT0_S -#define MXC_WUT0 MXC_WUT0_S -#define MXC_BASE_WUT1 MXC_BASE_WUT1_S -#define MXC_WUT1 MXC_WUT1_S - -/******************************************************************************/ -/* Power Sequencer */ - -/* Non-secure Mapping */ -#define MXC_BASE_PWRSEQ_NS ((uint32_t)0x40006800UL) -#define MXC_PWRSEQ_NS ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ_NS) - -/* Secure Mapping */ -#define MXC_BASE_PWRSEQ_S ((uint32_t)0x50006800UL) -#define MXC_PWRSEQ_S ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ_S) - -#define MXC_BASE_PWRSEQ MXC_BASE_PWRSEQ_S -#define MXC_PWRSEQ MXC_PWRSEQ_S - -/******************************************************************************/ -/* Misc Control */ - -/* Non-secure Mapping */ -#define MXC_BASE_MCR_NS ((uint32_t)0x40006C00UL) -#define MXC_MCR_NS ((mxc_mcr_regs_t *)MXC_BASE_MCR_NS) - -/* Secure Mapping */ -#define MXC_BASE_MCR_S ((uint32_t)0x50006C00UL) -#define MXC_MCR_S ((mxc_mcr_regs_t *)MXC_BASE_MCR_S) - -#define MXC_BASE_MCR MXC_BASE_MCR_S -#define MXC_MCR MXC_MCR_S - -/******************************************************************************/ -/* AES */ - -/* Non-secure Mapping */ -#define MXC_BASE_AES_NS ((uint32_t)0x40007400UL) -#define MXC_AES_NS ((mxc_aes_regs_t *)MXC_BASE_AES_NS) - -/* Secure Mapping */ -#define MXC_BASE_AES_S ((uint32_t)0x50007400UL) -#define MXC_AES_S ((mxc_aes_regs_t *)MXC_BASE_AES_NS) - -#define MXC_BASE_AES MXC_BASE_AES_S -#define MXC_AES MXC_AES_S - -/******************************************************************************/ -/* AES Keys */ - -/* Non-secure Mapping */ -#define MXC_BASE_AESKEYS_NS ((uint32_t)0x40007800UL) -#define MXC_AESKEYS_NS ((mxc_aeskeys_regs_t *)MXC_BASE_AESKEYS_NS) - -/* Secure Mapping */ -#define MXC_BASE_AESKEYS_S ((uint32_t)0x50007800UL) -#define MXC_AESKEYS_S ((mxc_aeskeys_regs_t *)MXC_BASE_AESKEYS_S) - -#define MXC_BASE_AESKEYS MXC_BASE_AESKEYS_S -#define MXC_AESKEYS MXC_AESKEYS_S - -/******************************************************************************/ -/* GPIO */ -#define MXC_CFG_GPIO_INSTANCES (1) -#define MXC_CFG_GPIO_PINS_PORT (32) - -/* Non-secure Mapping */ -#define MXC_BASE_GPIO0_NS ((uint32_t)0x40008000UL) -#define MXC_GPIO0_NS ((mxc_gpio_regs_t *)MXC_BASE_GPIO0_NS) - -#define MXC_GPIO_NS_GET_IDX(p) ((p) == MXC_GPIO0_NS ? 0 : -1) -#define MXC_GPIO_NS_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0_NS : 0) - -/* Secure Mapping */ -#define MXC_BASE_GPIO0_S ((uint32_t)0x50008000UL) -#define MXC_GPIO0_S ((mxc_gpio_regs_t *)MXC_BASE_GPIO0_S) - -#define MXC_BASE_GPIO0 MXC_BASE_GPIO0_S -#define MXC_GPIO0 MXC_GPIO0_S - -/******************************************************************************/ -/* CRC */ - -/* Non-secure Mapping */ -#define MXC_BASE_CRC_NS ((uint32_t)0x4000F000UL) -#define MXC_CRC_NS ((mxc_crc_regs_t *)MXC_BASE_CRC_NS) - -/* Secure Mapping */ -#define MXC_BASE_CRC_S ((uint32_t)0x5000F000UL) -#define MXC_CRC_S ((mxc_crc_regs_t *)MXC_BASE_CRC_S) - -#define MXC_BASE_CRC MXC_BASE_CRC_S -#define MXC_CRC MXC_CRC_S - -/******************************************************************************/ -/* Timer */ -#define SEC(s) (((uint32_t)s) * 1000000UL) -#define MSEC(ms) (ms * 1000UL) -#define USEC(us) (us) - -#define MXC_CFG_TMR_INSTANCES (6) - -/* Non-secure Mapping */ -#define MXC_BASE_TMR0_NS ((uint32_t)0x40010000UL) -#define MXC_TMR0_NS ((mxc_tmr_regs_t *)MXC_BASE_TMR0_NS) -#define MXC_BASE_TMR1_NS ((uint32_t)0x40011000UL) -#define MXC_TMR1_NS ((mxc_tmr_regs_t *)MXC_BASE_TMR1_NS) -#define MXC_BASE_TMR2_NS ((uint32_t)0x40012000UL) -#define MXC_TMR2_NS ((mxc_tmr_regs_t *)MXC_BASE_TMR2_NS) -#define MXC_BASE_TMR3_NS ((uint32_t)0x40013000UL) -#define MXC_TMR3_NS ((mxc_tmr_regs_t *)MXC_BASE_TMR3_NS) -#define MXC_BASE_TMR4_NS ((uint32_t)0x40080C00UL) -#define MXC_TMR4_NS ((mxc_tmr_regs_t *)MXC_BASE_TMR4_NS) -#define MXC_BASE_TMR5_NS ((uint32_t)0x40081000UL) -#define MXC_TMR5_NS ((mxc_tmr_regs_t *)MXC_BASE_TMR5_NS) - -#define MXC_TMR_NS_GET_BASE(i) \ - ((i) == 0 ? MXC_BASE_TMR0_NS : \ - (i) == 1 ? MXC_BASE_TMR1_NS : \ - (i) == 2 ? MXC_BASE_TMR2_NS : \ - (i) == 3 ? MXC_BASE_TMR3_NS : \ - (i) == 4 ? MXC_BASE_TMR4_NS : \ - (i) == 5 ? MXC_BASE_TMR5_NS : \ - 0) - -#define MXC_TMR_NS_GET_TMR(i) \ - ((i) == 0 ? MXC_TMR0_NS : \ - (i) == 1 ? MXC_TMR1_NS : \ - (i) == 2 ? MXC_TMR2_NS : \ - (i) == 3 ? MXC_TMR3_NS : \ - (i) == 4 ? MXC_TMR4_NS : \ - (i) == 5 ? MXC_TMR5_NS : \ - 0) - -/* Secure Mapping */ -#define MXC_BASE_TMR0_S ((uint32_t)0x50010000UL) -#define MXC_TMR0_S ((mxc_tmr_regs_t *)MXC_BASE_TMR0_S) -#define MXC_BASE_TMR1_S ((uint32_t)0x50011000UL) -#define MXC_TMR1_S ((mxc_tmr_regs_t *)MXC_BASE_TMR1_S) -#define MXC_BASE_TMR2_S ((uint32_t)0x50012000UL) -#define MXC_TMR2_S ((mxc_tmr_regs_t *)MXC_BASE_TMR2_S) -#define MXC_BASE_TMR3_S ((uint32_t)0x50013000UL) -#define MXC_TMR3_S ((mxc_tmr_regs_t *)MXC_BASE_TMR3_S) -#define MXC_BASE_TMR4_S ((uint32_t)0x50080C00UL) -#define MXC_TMR4_S ((mxc_tmr_regs_t *)MXC_BASE_TMR4_S) -#define MXC_BASE_TMR5_S ((uint32_t)0x50081000UL) -#define MXC_TMR5_S ((mxc_tmr_regs_t *)MXC_BASE_TMR5_S) - -#define MXC_BASE_TMR0 MXC_BASE_TMR0_S -#define MXC_TMR0 MXC_TMR0_S -#define MXC_BASE_TMR1 MXC_BASE_TMR1_S -#define MXC_TMR1 MXC_TMR1_S -#define MXC_BASE_TMR2 MXC_BASE_TMR2_S -#define MXC_TMR2 MXC_TMR2_S -#define MXC_BASE_TMR3 MXC_BASE_TMR3_S -#define MXC_TMR3 MXC_TMR3_S -#define MXC_BASE_TMR4 MXC_BASE_TMR4_S -#define MXC_TMR4 MXC_TMR4_S -#define MXC_BASE_TMR5 MXC_BASE_TMR5_S -#define MXC_TMR5 MXC_TMR5_S - -#define MXC_TMR_S_GET_BASE(i) \ - ((i) == 0 ? MXC_BASE_TMR0_S : \ - (i) == 1 ? MXC_BASE_TMR1_S : \ - (i) == 2 ? MXC_BASE_TMR2_S : \ - (i) == 3 ? MXC_BASE_TMR3_S : \ - (i) == 4 ? MXC_BASE_TMR4_S : \ - (i) == 5 ? MXC_BASE_TMR5_S : \ - 0) - -#define MXC_TMR_S_GET_TMR(i) \ - ((i) == 0 ? MXC_TMR0_S : \ - (i) == 1 ? MXC_TMR1_S : \ - (i) == 2 ? MXC_TMR2_S : \ - (i) == 3 ? MXC_TMR3_S : \ - (i) == 4 ? MXC_TMR4_S : \ - (i) == 5 ? MXC_TMR5_S : \ - 0) - -#define MXC_TMR_GET_IRQ(i) \ - (IRQn_Type)((i) == 0 ? TMR0_IRQn : \ - (i) == 1 ? TMR1_IRQn : \ - (i) == 2 ? TMR2_IRQn : \ - (i) == 3 ? TMR3_IRQn : \ - (i) == 4 ? TMR4_IRQn : \ - (i) == 5 ? TMR5_IRQn : \ - 0) - -#define MXC_TMR_GET_IDX(p) \ - ((p) == MXC_TMR0_NS ? 0 : \ - (p) == MXC_TMR1_NS ? 1 : \ - (p) == MXC_TMR2_NS ? 2 : \ - (p) == MXC_TMR3_NS ? 3 : \ - (p) == MXC_TMR4_NS ? 4 : \ - (p) == MXC_TMR5_NS ? 5 : \ - (p) == MXC_TMR0_S ? 0 : \ - (p) == MXC_TMR1_S ? 1 : \ - (p) == MXC_TMR2_S ? 2 : \ - (p) == MXC_TMR3_S ? 3 : \ - (p) == MXC_TMR4_S ? 4 : \ - (p) == MXC_TMR5_S ? 5 : \ - -1) - -/******************************************************************************/ -/* I3C */ -/* Non-secure Mapping */ -#define MXC_BASE_I3C_NS ((uint32_t)0x4001D000UL) -#define MXC_I3C_NS ((mxc_i2c_regs_t *)MXC_BASE_I3C_NS) - -/* Secure Mapping */ -#define MXC_BASE_I3C_S ((uint32_t)0x5001D000UL) -#define MXC_I3C_S ((mxc_i2c_regs_t *)MXC_BASE_I3C_S) - -#define MXC_BASE_I3C MXC_BASE_I2C_S -#define MXC_I3C MXC_I3C_S - -#define MXC_I3C_FIFO_DEPTH (8) // TODO(ME30): Confirm this is correct. - -/******************************************************************************/ -/* DMA */ -#define MXC_DMA_CHANNELS (4) -#define MXC_DMA_INSTANCES (2) - -/* Non-secure Mapping */ -#define MXC_BASE_DMA0_NS ((uint32_t)0x40028000UL) -#define MXC_DMA0_NS ((mxc_dma_regs_t *)MXC_BASE_DMA0_NS) -/* DMA1 instance only for secure mode. */ - -/* Secure Mapping */ -#define MXC_BASE_DMA0_S ((uint32_t)0x50028000UL) -#define MXC_DMA0_S ((mxc_dma_regs_t *)MXC_BASE_DMA0_S) -#define MXC_BASE_DMA1_S ((uint32_t)0x50035000UL) -#define MXC_DMA1_S ((mxc_dma_regs_t *)MXC_BASE_DMA1_S) - -#define MXC_BASE_DMA0 MXC_BASE_DMA0_S -#define MXC_DMA0 MXC_DMA0_S -#define MXC_BASE_DMA1 MXC_BASE_DMA1_S -#define MXC_DMA1 MXC_DMA1_S - -#define MXC_DMA_CH_GET_IRQ(i) \ - ((IRQn_Type)(((i) == 0) ? DMA0_IRQn : \ - ((i) == 1) ? DMA1_IRQn : \ - ((i) == 2) ? DMA2_IRQn : \ - ((i) == 3) ? DMA3_IRQn : \ - 0)) - -/******************************************************************************/ -/* Flash Controller */ -#define MXC_FLC_INSTANCES (1) - -/* Secure Mapping Only */ -#define MXC_BASE_FLC ((uint32_t)0x50029000UL) -#define MXC_FLC ((mxc_flc_regs_t *)MXC_BASE_FLC) - -/* Added for consistency and explicitness */ -#define MXC_BASE_FLC_S MXC_BASE_FLC -#define MXC_FLC_S MXC_FLC - -/******************************************************************************/ -/* Internal Cache Controller */ -#define MXC_ICC_INSTANCES (1) - -/* Secure Mapping Only */ -#define MXC_BASE_ICC ((uint32_t)0x5002A000UL) -#define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC_S) - -/* Added for consistency and explicitness */ -#define MXC_BASE_ICC_S MXC_BASE_ICC -#define MXC_ICC_S MXC_ICC - -/******************************************************************************/ -/* UART / Serial Port Interface */ -#define MXC_UART_INSTANCES (1) -#define MXC_UART_FIFO_DEPTH (8) // TOD(ME30): Check this is correct. - -/* Non-secure Mapping */ -#define MXC_BASE_UART_NS ((uint32_t)0x40042000UL) -#define MXC_UART_NS ((mxc_uart_regs_t *)MXC_BASE_UART_NS) - -#define MXC_UART_NS_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0_NS : 0) -#define MXC_UART_NS_GET_UART(i) ((i) == 0 ? MXC_UART_NS : 0) - -/* Secure Mapping */ -#define MXC_BASE_UART_S ((uint32_t)0x50042000UL) -#define MXC_UART_S ((mxc_uart_regs_t *)MXC_BASE_UART_S) - -#define MXC_BASE_UART MXC_BASE_UART_S -#define MXC_UART MXC_UART_S - -#define MXC_UART_S_GET_UART(i) ((i) == 0 ? MXC_UART_S : 0) -#define MXC_UART_S_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0_S : 0) - -#define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : 0) -#define MXC_UART_GET_IDX(p) ((p) == MXC_UART_NS ? 0 : (p) == MXC_UART_S ? 0 : -1) - -/******************************************************************************/ -/* SPI */ -#define MXC_SPI_INSTANCES (1) -#define MXC_SPI_SS_INSTANCES (4) -#define MXC_SPI_FIFO_DEPTH (32) - -/* Non-secure Mapping */ -#define MXC_BASE_SPI_NS ((uint32_t)0x40046000UL) -#define MXC_SPI_NS ((mxc_spi_regs_t *)MXC_BASE_SPI_NS) - -#define MXC_SPI_NS_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI_NS : 0) -#define MXC_SPI_NS_GET_SPI(i) ((i) == 0 ? MXC_SPI_NS : 0) - -/* Secure Mapping */ -#define MXC_BASE_SPI_S ((uint32_t)0x50046000UL) -#define MXC_SPI_S ((mxc_spi_regs_t *)MXC_BASE_SPI_S) - -#define MXC_BASE_SPI MXC_BASE_SPI_S -#define MXC_SPI MXC_SPI_S - -#define MXC_SPI_S_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI_S : 0) -#define MXC_SPI_S_GET_SPI(i) ((i) == 0 ? MXC_SPI_S : 0) - -#define MXC_SPI_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SPI_IRQn : 0) -#define MXC_SPI_GET_IDX(p) ((p) == MXC_SPI_NS ? 0 : (p) == MXC_SPI_S ? 0 : -1) - -/******************************************************************************/ -/* TRNG */ - -/* Non-secure Mapping */ -#define MXC_BASE_TRNG_NS ((uint32_t)0x4004D000UL) -#define MXC_TRNG_NS ((mxc_trng_regs_t *)MXC_BASE_TRNG_NS) - -/* Secure Mapping */ -#define MXC_BASE_TRNG_S ((uint32_t)0x5004D000UL) -#define MXC_TRNG_S ((mxc_trng_regs_t *)MXC_BASE_TRNG_S) - -#define MXC_BASE_TRNG MXC_BASE_TRNG_S -#define MXC_TRNG MXC_TRNG_S - -/******************************************************************************/ -/* BTLE */ -// TODO(ME30): Verify with bluetooth team. This section does not exist in our prev -// bluetooth-supported parts. -/* Non-secure Mapping */ -#define MXC_BASE_BTLE_NS ((uint32_t)0x40050000UL) -#define MXC_BTLE_NS // TODO(ME30): Add BTLE related registers? This section doesn't exist for ME17. - -/* Secure Mapping */ -#define MXC_BASE_BTLE_S ((uint32_t)0x50050000UL) -#define MXC_BTLE_S // TODO(ME30): Add BTLE related registers? This section doesn't exist for ME17. - -#define MXC_BASE_BTLE MXC_BASE_BTLE_S -#define MXC_BTLE // TODO(ME30): Does this have registers? - -/******************************************************************************/ -/* Secure Privilege Control (SPC TZ) */ - -/* Secure Mapping Only */ -#define MXC_BASE_SPC ((uint32_t)0x50090000UL) -#define MXC_SPC // TODO(ME30): Does this have registers? - -#define MXC_BASE_SPC_S MXC_BASE_SPC -#define MXC_SPC_S // TODO(ME30): Does this have registers? - -/******************************************************************************/ -/* MPC */ - -/* Secure Mapping Only */ -#define MXC_BASE_MPC_SRAM0 ((uint32_t)0x50091000UL) -#define MXC_MPC_SRAM0 // TODO(ME30): Does this have registers? -#define MXC_BASE_MPC_SRAM1 ((uint32_t)0x50092000UL) -#define MXC_MPC_SRAM1 // TODO(ME30): Does this have registers? -#define MXC_BASE_MPC_SRAM2 ((uint32_t)0x50093000UL) -#define MXC_MPC_SRAM2 // TODO(ME30): Does this have registers? -#define MXC_BASE_MPC_SRAM3 ((uint32_t)0x50094000UL) -#define MXC_MPC_SRAM3 // TODO(ME30): Does this have registers? -#define MXC_BASE_MPC_SRAM4 ((uint32_t)0x50095000UL) -#define MXC_MPC_SRAM4 // TODO(ME30): Does this have registers? -#define MXC_BASE_MPC_FLASH ((uint32_t)0x50096000UL) -#define MXC_MPC_FLASH // TODO(ME30): Does this have registers? - -/* Added for consistency and explicitness */ -#define MXC_BASE_MPC_SRAM0_S MXC_BASE_MPC_SRAM0 -#define MXC_MPC_SRAM0_S // TODO(ME30): Does this have registers? -#define MXC_BASE_MPC_SRAM1_S MXC_BASE_MPC_SRAM1 -#define MXC_MPC_SRAM1_S // TODO(ME30): Does this have registers? -#define MXC_BASE_MPC_SRAM2_S MXC_BASE_MPC_SRAM2 -#define MXC_MPC_SRAM2_S // TODO(ME30): Does this have registers? -#define MXC_BASE_MPC_SRAM3_S MXC_BASE_MPC_SRAM3 -#define MXC_MPC_SRAM3_S // TODO(ME30): Does this have registers? -#define MXC_BASE_MPC_SRAM4_S MXC_BASE_MPC_SRAM4 -#define MXC_MPC_SRAM4_S // TODO(ME30): Does this have registers? -#define MXC_BASE_MPC_FLASH_S MXC_BASE_MPC_FLASH -#define MXC_MPC_FLASH_S // TODO(ME30): Does this have registers? - -/******************************************************************************/ -/* Bit Shifting */ -#define MXC_F_BIT_0 (1 << 0) -#define MXC_F_BIT_1 (1 << 1) -#define MXC_F_BIT_2 (1 << 2) -#define MXC_F_BIT_3 (1 << 3) -#define MXC_F_BIT_4 (1 << 4) -#define MXC_F_BIT_5 (1 << 5) -#define MXC_F_BIT_6 (1 << 6) -#define MXC_F_BIT_7 (1 << 7) -#define MXC_F_BIT_8 (1 << 8) -#define MXC_F_BIT_9 (1 << 9) -#define MXC_F_BIT_10 (1 << 10) -#define MXC_F_BIT_11 (1 << 11) -#define MXC_F_BIT_12 (1 << 12) -#define MXC_F_BIT_13 (1 << 13) -#define MXC_F_BIT_14 (1 << 14) -#define MXC_F_BIT_15 (1 << 15) -#define MXC_F_BIT_16 (1 << 16) -#define MXC_F_BIT_17 (1 << 17) -#define MXC_F_BIT_18 (1 << 18) -#define MXC_F_BIT_19 (1 << 19) -#define MXC_F_BIT_20 (1 << 20) -#define MXC_F_BIT_21 (1 << 21) -#define MXC_F_BIT_22 (1 << 22) -#define MXC_F_BIT_23 (1 << 23) -#define MXC_F_BIT_24 (1 << 24) -#define MXC_F_BIT_25 (1 << 25) -#define MXC_F_BIT_26 (1 << 26) -#define MXC_F_BIT_27 (1 << 27) -#define MXC_F_BIT_28 (1 << 28) -#define MXC_F_BIT_29 (1 << 29) -#define MXC_F_BIT_30 (1 << 30) -#define MXC_F_BIT_31 (1 << 31) - -/******************************************************************************/ -/* Bit Banding */ -#define BITBAND(reg, bit) \ - ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg)&0x0fffffff) << 5) + \ - ((bit) << 2)) - -#define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0) -#define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1) -#define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit)) - -#define MXC_SETFIELD(reg, mask, setting) ((reg) = ((reg) & ~(mask)) | ((setting) & (mask))) - -#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX326657_INCLUDE_MAX32657_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd index b1c96806256..f12f6e39590 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd @@ -1154,10 +1154,28 @@ read-write - USBCLKSEL - USB External Core Clock Select. - 16 - 1 + BTLELDOTX + BTLE LDO TX Trim + 0 + 5 + + + sys + Generated clock from system clock. + 0 + + + dig + Digital clock from a GPIO. + 1 + + + + + BTLELDORX + BTLE LDO RX Trim + 8 + 5 sys @@ -1528,9 +1546,9 @@ - GP - General Purpose Register. - 0x1C + ERFOKS + ERFO Kick Start Register. + 0x18 read-write @@ -1541,26 +1559,6 @@ - - MSRTRIM - MSR Trim Register. - 0x20 - read-write - - - R1 - MSR Trim R1. - 0 - 2 - - - R2 - MSR Trim R2. - 2 - 3 - - - FLVFILT Flash Low Voltage Filter Control Register. @@ -2003,80 +2001,8 @@ - SRCC_FLUSH - Data Cache Flush. The system cache (s) will be flushed when this bit is set. - 7 - 1 - - - normal - Normal System Cache Operation - 0 - - - flush - System Cache is flushed - 1 - - - - - SRCC_DIS - Data Cache Disable. The system cache (s) will be completely disabled when this bit is set. - 9 - 1 - - - en - Is enabled. - 0 - - - dis - Is Disabled. - 1 - - - - - CHKRES1 - ROM1 Checksum Result. This bit is only valid when the checksum is done and CCHK1 bit is cleared.. - 11 - 1 - - - complete - No operation/complete. - 0 - - - start - Start operation. - 1 - - - - - CCHK1 - Compute ROM1 Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. - 12 - 1 - - - complete - No operation/complete. - 0 - - - start - Start operation. - 1 - - - - - CCHK0 - Compute ROM0 Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. + CCHK + Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. 13 1 @@ -2093,7 +2019,7 @@ - CHKRES0 + CHKRES ROM0 Checksum Result. This bit is only valid when the checksum is done and CCHK0 bit is cleared.. 15 1 @@ -2124,141 +2050,99 @@ 0x04 - DMA - DMA Reset. + DMA0 + DMA0 Reset. 0 1 - - WDT0 + + WDT Watchdog Timer Reset. 1 1 - + GPIO0 - GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states. + GPIO0 Reset. 2 1 - - GPIO1 - GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states. - 3 - 1 - - + TMR0 - Timer0 Reset. Setting this bit to 1 resets Timer 0 blocks. + Timer0 Reset. 5 1 - + TMR1 - Timer1 Reset. Setting this bit to 1 resets Timer 1 blocks. + Timer1 Reset. 6 1 - + TMR2 - Timer2 Reset. Setting this bit to 1 resets Timer 2 blocks. + Timer2 Reset. 7 1 - + TMR3 - Timer3 Reset. Setting this bit to 1 resets Timer 3 blocks. + Timer3 Reset. 8 1 - + TMR4 - Timer4 Reset. Setting this bit to 1 resets Timer 4 blocks. + Timer4 Reset. 9 1 - + TMR5 - Timer5 Reset. Setting this bit to 1 resets Timer 5 blocks. + Timer5 Reset. 10 1 - - UART0 - UART0 Reset. Setting this bit to 1 resets all UART 0 blocks. + + UART + UART Reset. 11 1 - - UART1 - UART1 Reset. Setting this bit to 1 resets all UART 1 blocks. - 12 - 1 - - - SPI0 - SPI0 Reset. Setting this bit to 1 resets all SPI 0 blocks. + + SPI + SPI0 Reset. 13 1 - - SPI1 - SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks. - 14 - 1 - - - SPI2 - SPI2 Reset. Setting this bit to 1 resets all SPI 2 blocks. - 15 - 1 - - - I2C0 - I2C0 Reset. + + I3C + I3C Reset. 16 1 - + RTC Real Time Clock Reset. 17 1 - - TMR6 - Timer6 Reset. Setting this bit to 1 resets Timer 6 blocks. - 20 - 1 - - - TMR7 - Timer7 Reset. Setting this bit to 1 resets Timer 7 blocks. - 21 - 1 - - - SEMA - Semaphore Reset. - 22 + + BTLE + Bluetooth Reset. + 18 1 - + TRNG - TODO(5-2-2023): Remove this bit before release. TRNG Reset. Setting this bit resets the TRNG block. + TRNG Reset. 24 1 - - ADC - Analog to Digital Reset. - 26 - 1 - - - UART2 - UART2 Reset. Setting this bit to 1 resets all UART 2 blocks. - 28 + + DMA1 + DMA1 Reset. + 27 1 @@ -2420,34 +2304,6 @@ - - IPO_DIV - IPO clock divider - 14 - 2 - - - DIV1 - Divide 1. - 0 - - - DIV2 - Divide 2. - 1 - - - DIV4 - Divide 4. - 2 - - - DIV8 - Divide 8. - 3 - - - ERFO_EN 27MHz Crystal Oscillator Enable. @@ -2472,16 +2328,10 @@ 17 1 - - ISO_EN - 60MHz High Frequency Internal Reference Clock Enable. - 18 - 1 - IPO_EN - 96MHz High Frequency Internal Reference Clock Enable. - 19 + Internal Primary Oscillator Clock Enable. + 18 1 @@ -2521,16 +2371,10 @@ 25 1 - - ISO_RDY - 60MHz ISO Ready. - 26 - 1 - IPO_RDY Internal Primary Oscillator Ready. - 27 + 28 1 @@ -2556,7 +2400,7 @@ MODE Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode. 0 - 3 + 4 active @@ -2593,82 +2437,10 @@ 1 - USB_WE - USB Wake Up Enable. This bit enables USB activity as wakeup source. - 6 - 1 - - - ERFO_PD - Radio Frequency oscilator Crystal Power Down. This bit selects the power state in DEEPSLEEP mode. - 12 - 1 - - - active - Mode is Active. - 0 - - - deepsleep - Powered down in DEEPSLEEP. - 1 - - - - - ISO_PD - Internal Secondary Oscilator Power Down. This bit selects the power state in DEEPSLEEP mode. - 15 - 1 - - - active - Mode is Active. - 0 - - - deepsleep - Powered down in DEEPSLEEP. - 1 - - - - - IPO_PD - Internal Primary Oscilatory power down. This bit selects the power state in DEEPSLEEP mode. - 16 - 1 - - - active - Mode is Active. - 0 - - - deepsleep - Powered down in DEEPSLEEP. - 1 - - - - - IBRO_PD - Internal Baud Rate Oscillator power down. This bit selects the power state in DEEPSLEEP mode. - 17 + WUT_WE + Enable wakeup timer as a wakeup source. + 7 1 - - - active - Mode is Active. - 0 - - - deepsleep - Powered down in DEEPSLEEP. - 1 - - ERFO_BP @@ -2698,45 +2470,17 @@ ADCFRQ - ADC clock Frequency. These bits define the ADC clock frequency. FADC = FPCLK / (ADCFRQ). + TODO(4-29-2024): Remove register? 10 4 - - AONCLKDIV - Always-ON (AON) domain Clock Divider. These bits define the AON domain clock divider. - 14 - 2 - - - DIV4 - PCLK divide by 4. - 0 - - - DIV8 - PCLK divide by 8. - 1 - - - DIV16 - PCLK divide by 16. - 2 - - - DIV32 - PCLK divide by 32. - 3 - - - - - - - PCLKDIS0 - Peripheral Clock Disable. - 0x24 - + + + + PCLKDIS0 + Peripheral Clock Disable. + 0x24 + GPIO0 GPIO0 Clock Disable. @@ -2756,50 +2500,26 @@ - GPIO1 - GPIO1 Disable. - 1 - 1 - - - DMA - DMA Disable. + DMA0 + DMA0 Disable. 5 1 - SPI0 - SPI 0 Disable. + SPI + SPI Disable. 6 1 - SPI1 - SPI 1 Disable. - 7 - 1 - - - SPI2 - SPI 2 Disable. - 8 - 1 - - - UART0 - UART 0 Disable. + UART + UART Disable. 9 1 - UART1 - UART 1 Disable. - 10 - 1 - - - I2C0 - I2C 0 Disable. + I3C + I3C Disable. 13 1 @@ -2839,36 +2559,6 @@ 20 1 - - ADC - ADC Disable. - 23 - 1 - - - TMR6 - Timer 6 Disable. - 24 - 1 - - - TMR7 - Timer 7 Disable. - 25 - 1 - - - I2C1 - I2C 1 Disable. - 28 - 1 - - - PT - PT Clock Disable. - 29 - 1 - @@ -2882,138 +2572,6 @@ 0 3 - - SRAM_WS - SRAM Wait State Enable - 4 - 1 - - - ROM1_WS - ROM1 Wait State Enable - 7 - 1 - - - RAM0_WS - System RAM 0 Wait State Enable - 8 - 1 - - - RAM1_WS - System RAM 1 Wait State Enable - 9 - 1 - - - RAM2_WS - System RAM 2 Wait State Enable - 10 - 1 - - - RAM3_WS - System RAM 3 Wait State Enable - 11 - 1 - - - RAM4_WS - System RAM 4 Wait State Enable - 12 - 1 - - - RAM5_WS - System RAM 5 Wait State Enable - 13 - 1 - - - RAM0LS_EN - System RAM 0 Light Sleep Mode. - 16 - 1 - - - active - RAM is active. - 0 - - - light_sleep - RAM is in Light Sleep mode. - 1 - - - - - RAM1LS_EN - System RAM 1 Light Sleep Mode. - 17 - 1 - - - RAM2LS_EN - System RAM 2 Light Sleep Mode. - 18 - 1 - - - RAM3LS_EN - System RAM 3 Light Sleep Mode. - 19 - 1 - - - RAM4LS_EN - System RAM 4 Light Sleep Mode. - 20 - 1 - - - RAM5LS_EN - System RAM 5 Light Sleep Mode. - 21 - 1 - - - ICCLS_EN - ICache RAM Light Sleep Mode. - 24 - 1 - - - ICCXIPLS_EN - ICACHE-XIP RAM Light Sleep Mode. - 25 - 1 - - - SRCCLS_EN - SysCache RAM Light Sleep Mode. - 26 - 1 - - - USBLS_EN - USB FIFO Light Sleep Mode. - 28 - 1 - - - ROM0LS_EN - ROM0 Light Sleep Mode. - 29 - 1 - - - ROM1LS_EN - ROM1 Light Sleep Mode. - 30 - 1 - @@ -3022,7 +2580,7 @@ 0x2C - RAM0 + SRAM0 System RAM Block 0. 0 1 @@ -3039,70 +2597,34 @@ - - RAM1 + + SRAM1 System RAM Block 1. 1 1 - - RAM2 + + SRAM2 System RAM Block 2. 2 1 - - RAM3 + + SRAM3 System RAM Block 3. 3 1 - - RAM4 + + SRAM4 System RAM Block 4. 4 1 - - RAM5 - System RAM Block 5. - 5 - 1 - - - RAM6 - System RAM Block 6. - 6 - 1 - - + ICC - Instruction Cache. - 8 - 1 - - - ICCXIP - Instruction Cache XIP Data and Tag Ram zeroizatoin. - 9 - 1 - - - SRCCDATA - System Cache Data Ram Zeroization. - 10 - 1 - - - SRCCTAG - System Cache Tag Zeroization. - 11 - 1 - - - USBFIFO - USB FIFO Zeroization. - 13 + Internal Cache. + 5 1 @@ -3130,60 +2652,6 @@ - - CODEAUTHERR - Code Authentication Error Flag. This bit indicates a code authentication error has occured in XiP interface. - 1 - 1 - - - norm - Normal Operating Condition. - 0 - - - code - Code Integrity Error. - 1 - - - - - DATAAUTHERR - Data Authentication Error Flag. This bit indicates a data authentication error has occured in XiP interface. - 2 - 1 - - - norm - Normal Operating Condition. - 0 - - - code - Code Integrity Error. - 1 - - - - - SCMEMF - System Cache Memory Fault Flag. This bit indicates a memory fault has occured in the System Cache while receiving data from the Hyperbus Interface. - 5 - 1 - - - norm - Normal Operating Condition. - 0 - - - memory - Memory Fault. - 1 - - - @@ -3192,202 +2660,52 @@ 0x44 - I2C1 - I2C1 Reset. - 0 - 1 - - - PT - PT Reset. - 1 - 1 - - - OWIRE - OWIRE Reset. - 7 - 1 - - - WDT1 - WDT1 Reset. - 8 - 1 - - CRC CRC Reset. 9 1 - + AES AES Reset. 10 1 - - I2S - I2S Reset. - 13 + + + + PCLKDIS1 + Peripheral Clock Disable. + 0x48 + + + TRNG + TRNG Disable. + 2 1 - - AC - AC Reset. + + CRC + CRC Clock Disable. 14 1 - - SEMA - Semaphore Reset. - 16 - 1 - - - I2C2 - I2C2 Reset. - 17 + + AES + AES Clock Disable. + 15 1 - - UART3 - UART3 Reset. - 18 + + SPI + SPI Clock Disable. + 16 1 - - UART4 - UART4 Reset. - 19 - 1 - - - UART5 - UART5 Reset. - 20 - 1 - - - - - PCLKDIS1 - Peripheral Clock Disable. - 0x48 - - - BTLE - Bluetooth Clock Disable. - 0 - 1 - - - en - Enable. - 0 - - - dis - Disable. - 1 - - - - - UART2 - UART2 Disable. - 1 - 1 - - - en - Enable. - 0 - - - dis - Disable. - 1 - - - - - TRNG - TRNG Disable. - 2 - 1 - - - WDT0 - WDT0 Clock Disable - 4 - 1 - - - WDT1 - WDT1 Clock Disable - 5 - 1 - - - SRCC - System Cache Clock Disable. - 7 - 1 - - - SEMA - Semaphore Clock Disable. - 9 - 1 - - - OWIRE - One-Wire Clock Disable. - 13 - 1 - - - CRC - CRC Clock Disable. - 14 - 1 - - - AES - AES Clock Disable. - 15 - 1 - - - I2S - I2S Clock Disable. - 16 - 1 - - - I2C2 - I2C2 Clock Disable - 21 - 1 - - - UART3 - UART3 Clock Disable - 22 - 1 - - - UART4 - UART4 Clock Disable - 23 - 1 - - - UART5 - UART5 Clock Disable - 24 + + WDT + Watchdog Clock Disable + 27 1 @@ -3398,14 +2716,14 @@ 0x4C - DMA - Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode. + DMA0 + Enable DMA0 event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode. 0 1 - RX - Enable RXEV pin event. When this bit is set, a logic high of GPIO0[24] will cause an RXEV event to wake the CPU from WFE sleep mode. + DMA1 + Enable DMA1 event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode. 1 1 @@ -3454,31 +2772,6 @@ - - CIE - Code Integrity Error Interrupt Enable. - 1 - 1 - - - SCMF - System Cache Memory Fault Interrupt Enable. - 5 - 1 - - - - - IPOCNT - IPO Warmup Count Register. - 0x58 - - - WMUPCNT - TBD - 0 - 10 - @@ -3486,121 +2779,12 @@ ECC Error Register 0x64 - - RAM0 - ECC System RAM0 Error Flag. Write 1 to clear. - 0 - 1 - - - RAM1 - ECC System RAM1 Error Flag. Write 1 to clear. - 1 - 1 - - - RAM2 - ECC System RAM2 Error Flag. Write 1 to clear. - 2 - 1 - - - RAM3 - ECC System RAM3 Error Flag. Write 1 to clear. - 3 - 1 - - - RAM4 - ECC System RAM4 Error Flag. Write 1 to clear. - 4 - 1 - - - RAM5 - ECC System RAM5 Error Flag. Write 1 to clear. - 5 - 1 - - - ICC - ECC Icache0 Error Flag. Write 1 to clear. - 8 - 1 - - - ICCXIP - ECC SFCC Instruction Cache Error Flag. Write 1 to clear. - 10 - 1 - FLASH - ECC Flash0 Error Flag. Write 1 to clear. - 11 - 1 - - - - - ECCCED - ECC Not Double Error Detect Register - 0x68 - - - RAM0 - ECC System RAM0 Error Flag. Write 1 to clear. + ECC Flash Error Flag. Write 1 to clear. 0 1 - - RAM1 - ECC System RAM1 Not Double Error Detect. Write 1 to clear. - 1 - 1 - - - RAM2 - ECC System RAM2 Not Double Error Detect. Write 1 to clear. - 2 - 1 - - - RAM3 - ECC System RAM3 Not Double Error Detect. Write 1 to clear. - 3 - 1 - - - RAM4 - ECC System RAM4 Not Double Error Detect. Write 1 to clear. - 4 - 1 - - - RAM5 - ECC System RAM5 Not Double Error Detect. Write 1 to clear. - 5 - 1 - - - ICC - ECC Icache0 Not Double Error Detect. Write 1 to clear. - 8 - 1 - - - ICCXIP - ECC IcacheXIP Not Double Error Detect. Write 1 to clear. - 10 - 1 - - - FLASH - ECC Flash0 Not Double Error Detect. Write 1 to clear. - 11 - 1 - @@ -3608,58 +2792,10 @@ ECC Interrupt Enable Register 0x6C - - RAM0 - ECC System RAM0 Interrupt Enable. - 0 - 1 - - - RAM1 - ECC System RAM1 Interrupt Enable. - 1 - 1 - - - RAM2 - ECC System RAM2 Interrupt Enable. - 2 - 1 - - - RAM3 - ECC System RAM3 Interrupt Enable. - 3 - 1 - - - RAM4 - ECC System RAM4 Interrupt Enable. - 4 - 1 - - - RAM5 - ECC System RAM5 Interrupt Enable. - 5 - 1 - - - ICC - ECC Icache0 Interrupt Enable. - 8 - 1 - - - ICCXIP - ECC IcacheXIP Interrupt Enable. - 10 - 1 - FLASH - ECC Flash0 Interrupt Enable. - 11 + ECC Flash Interrupt Enable. + 0 1 @@ -4407,1620 +3543,152 @@ pu - Weak pull-up mode. - 1 - - - pd - weak pull-down mode. - 2 - - - - - - - EN1 - GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. - 0x68 - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - primary - Primary function selected. - 0 - - - secondary - Secondary function selected. - 1 - - - - - - - EN1_SET - GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register. - 0x6C - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - - - EN1_CLR - GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register. - 0x70 - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - - - EN2 - GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. - 0x74 - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - primary - Primary function selected. - 0 - - - secondary - Secondary function selected. - 1 - - - - - - - EN2_SET - GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1, without affecting other bits in that register. - 0x78 - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - - - EN2_CLR - GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0, without affecting other bits in that register. - 0x7C - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - - - HYSEN - GPIO Input Hysteresis Enable. - 0xA8 - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - - - SRSEL - GPIO Slew Rate Enable Register. - 0xAC - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - FAST - Fast Slew Rate selected. - 0 - - - SLOW - Slow Slew Rate selected. - 1 - - - - - - - DS0 - GPIO Drive Strength 0 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. - 0xB0 - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - ld - GPIO port pin is in low-drive mode. - 0 - - - hd - GPIO port pin is in high-drive mode. - 1 - - - - - - - DS1 - GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. - 0xB4 - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - - - PSSEL - GPIO Pull Select Mode. - 0xB8 - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - - - VSSEL - GPIO Voltage Select. - 0xC0 - - - ALL - Mask of all of the pins on the port. - 0 - 32 - - - - - - - - I2C0 - Inter-Integrated Circuit. - I2C - 0x4001D000 - 32 - - 0x00 - 0x1000 - registers - - - I2C0 - I2C0 IRQ - 13 - - - - CTRL - Control Register0. - 0x00 - - - EN - I2C Enable. - [0:0] - read-write - - - dis - Disable I2C. - 0 - - - en - enable I2C. - 1 - - - - - MST_MODE - Master Mode Enable. - [1:1] - read-write - - - slave_mode - Slave Mode. - 0 - - - master_mode - Master Mode. - 1 - - - - - GC_ADDR_EN - General Call Address Enable. - [2:2] - read-write - - - dis - Ignore Gneral Call Address. - 0 - - - en - Acknowledge general call address. - 1 - - - - - IRXM_EN - Interactive Receive Mode. - [3:3] - read-write - - - dis - Disable Interactive Receive Mode. - 0 - - - en - Enable Interactive Receive Mode. - 1 - - - - - IRXM_ACK - Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0. - [4:4] - read-write - - - ack - return ACK (pulling SDA LOW). - 0 - - - nack - return NACK (leaving SDA HIGH). - 1 - - - - - SCL_OUT - SCL Output. This bits control SCL output when SWOE =1. - [6:6] - read-write - - - drive_scl_low - Drive SCL low. - 0 - - - release_scl - Release SCL. - 1 - - - - - SDA_OUT - SDA Output. This bits control SDA output when SWOE = 1. - [7:7] - read-write - - - drive_sda_low - Drive SDA low. - 0 - - - release_sda - Release SDA. - 1 - - - - - SCL - SCL status. This bit reflects the logic gate of SCL signal. - [8:8] - read-only - - - SDA - SDA status. THis bit reflects the logic gate of SDA signal. - [9:9] - read-only - - - BB_EN - Software Output Enable. - [10:10] - read-write - - - outputs_disable - I2C Outputs SCLO and SDAO disabled. - 0 - - - outputs_enable - I2C Outputs SCLO and SDAO enabled. - 1 - - - - - READ - Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match (GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set. - [11:11] - read-only - - - write - Write. - 0 - - - read - Read. - 1 - - - - - CLKSTR_DIS - This bit will disable slave clock stretching when set. - [12:12] - read-write - - - en - Slave clock stretching enabled. - 0 - - - dis - Slave clock stretching disabled. - 1 - - - - - ONE_MST_MODE - SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low. - [13:13] - read-write - - - dis - Standard open-drain operation: - drive low for 0, Hi-Z for 1 - 0 - - - en - Non-standard push-pull operation: - drive low for 0, drive high for 1 - 1 - - - - - HS_EN - High speed mode enable - [15:15] - read-write - - - - - STATUS - Status Register. - 0x04 - - - BUSY - Bus Status. - [0:0] - read-only - - - idle - I2C Bus Idle. - 0 - - - busy - I2C Bus Busy. - 1 - - - - - RX_EM - RX empty. - [1:1] - read-only - - - not_empty - Not Empty. - 0 - - - empty - Empty. - 1 - - - - - RX_FULL - RX Full. - [2:2] - read-only - - - not_full - Not Full. - 0 - - - full - Full. - 1 - - - - - TX_EM - TX Empty. - [3:3] - - - not_empty - Not Empty. - 0 - - - empty - Empty. - 1 - - - - - TX_FULL - TX Full. - [4:4] - - - not_empty - Not Empty. - 0 - - - empty - Empty. - 1 - - - - - MST_BUSY - Clock Mode. - [5:5] - read-only - - - not_actively_driving_scl_clock - Device not actively driving SCL clock cycles. - 0 - - - actively_driving_scl_clock - Device operating as master and actively driving SCL clock cycles. - 1 - - - - - - - INTFL0 - Interrupt Status Register. - 0x08 - - - DONE - Transfer Done Interrupt. - [0:0] - - INT_FL0_Done - - inactive - No Interrupt is Pending. - 0 - - - pending - An interrupt is pending. - 1 - - - - - IRXM - Interactive Receive Interrupt. - [1:1] - - - inactive - No Interrupt is Pending. - 0 - - - pending - An interrupt is pending. - 1 - - - - - GC_ADDR_MATCH - Slave General Call Address Match Interrupt. - [2:2] - - - inactive - No Interrupt is Pending. - 0 - - - pending - An interrupt is pending. - 1 - - - - - ADDR_MATCH - Slave Address Match Interrupt. - [3:3] - - - inactive - No Interrupt is Pending. - 0 - - - pending - An interrupt is pending. - 1 - - - - - RX_THD - Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level. - [4:4] - - - inactive - No interrupt is pending. - 0 - - - pending - An interrupt is pending. RX_FIFO equal or more bytes than the threshold. - 1 - - - - - TX_THD - Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level. - [5:5] - - - inactive - No interrupt is pending. - 0 - - - pending - An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. - 1 - - - - - STOP - STOP Interrupt. - [6:6] - - - inactive - No interrupt is pending. - 0 - - - pending - An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. - 1 - - - - - ADDR_ACK - Address Acknowledge Interrupt. - [7:7] - - - inactive - No Interrupt is Pending. - 0 - - - pending - An interrupt is pending. - 1 - - - - - ARB_ERR - Arbritation error Interrupt. - [8:8] - - - inactive - No Interrupt is Pending. - 0 - - - pending - An interrupt is pending. - 1 - - - - - TO_ERR - timeout Error Interrupt. - [9:9] - - - inactive - No Interrupt is Pending. - 0 - - - pending - An interrupt is pending. - 1 - - - - - ADDR_NACK_ERR - Address NACK Error Interrupt. - [10:10] - - - inactive - No Interrupt is Pending. - 0 - - - pending - An interrupt is pending. - 1 - - - - - DATA_ERR - Data NACK Error Interrupt. - [11:11] - - - inactive - No Interrupt is Pending. - 0 - - - pending - An interrupt is pending. - 1 - - - - - DNR_ERR - Do Not Respond Error Interrupt. - [12:12] - - - inactive - No Interrupt is Pending. - 0 - - - pending - An interrupt is pending. - 1 - - - - - START_ERR - Start Error Interrupt. - [13:13] - - - inactive - No Interrupt is Pending. - 0 - - - pending - An interrupt is pending. - 1 - - - - - STOP_ERR - Stop Error Interrupt. - [14:14] - - - inactive - No Interrupt is Pending. - 0 - - - pending - An interrupt is pending. - 1 - - - - - TX_LOCKOUT - Transmit Lock Out Interrupt. - [15:15] - - - MAMI - Multiple Address Match Interrupt - [21:16] - - - RD_ADDR_MATCH - Slave Read Address Match Interrupt - [22:22] - - - WR_ADDR_MATCH - Slave Write Address Match Interrupt - [23:23] - - - - - INTEN0 - Interrupt Enable Register. - 0x0C - read-write - - - DONE - Transfer Done Interrupt Enable. - [0:0] - read-write - - - dis - Interrupt disabled. - 0 - - - en - Interrupt enabled when DONE = 1. - 1 - - - - - IRXM - Description not available. - [1:1] - read-write - - - dis - Interrupt disabled. - 0 - - - en - Interrupt enabled when RX_MODE = 1. - 1 - - - - - GC_ADDR_MATCH - Slave mode general call address match received input enable. - [2:2] - read-write - - - dis - Interrupt disabled. - 0 - - - en - Interrupt enabled when GEN_CTRL_ADDR = 1. - 1 - - - - - ADDR_MATCH - Slave mode incoming address match interrupt. - [3:3] - read-write - - - dis - Interrupt disabled. - 0 - - - en - Interrupt enabled when ADDR_MATCH = 1. - 1 - - - - - RX_THD - RX FIFO Above Treshold Level Interrupt Enable. - [4:4] - read-write - - - dis - Interrupt disabled. - 0 - - - en - Interrupt enabled. - 1 - - - - - TX_THD - TX FIFO Below Treshold Level Interrupt Enable. - [5:5] - - - dis - Interrupt disabled. - 0 - - - en - Interrupt enabled. - 1 - - - - - STOP - Stop Interrupt Enable - [6:6] - read-write - - - dis - Interrupt disabled. - 0 - - - en - Interrupt enabled when STOP = 1. - 1 - - - - - ADDR_ACK - Received Address ACK from Slave Interrupt. - [7:7] - - - dis - Interrupt disabled. - 0 - - - en - Interrupt enabled. - 1 - - - - - ARB_ERR - Master Mode Arbitration Lost Interrupt. - [8:8] - - - dis - Interrupt disabled. - 0 - - - en - Interrupt enabled. - 1 - - - - - TO_ERR - Timeout Error Interrupt Enable. - [9:9] - - - dis - Interrupt disabled. - 0 - - - en - Interrupt enabled. - 1 - - - - - ADDR_NACK_ERR - Master Mode Address NACK Received Interrupt. - [10:10] - - - dis - Interrupt disabled. - 0 - - - en - Interrupt enabled. - 1 - - - - - DATA_ERR - Master Mode Data NACK Received Interrupt. - [11:11] - - - dis - Interrupt disabled. - 0 - - - en - Interrupt enabled. - 1 - - - - - DNR_ERR - Slave Mode Do Not Respond Interrupt. - [12:12] - - - dis - Interrupt disabled. - 0 - - - en - Interrupt enabled. - 1 - - - - - START_ERR - Out of Sequence START condition detected interrupt. - [13:13] - - - dis - Interrupt disabled. - 0 - - - en - Interrupt enabled. - 1 - - - - - STOP_ERR - Out of Sequence STOP condition detected interrupt. - [14:14] - - - dis - Interrupt disabled. - 0 - - - en - Interrupt enabled. - 1 - - - - - TX_LOCKOUT - TX FIFO Locked Out Interrupt. - [15:15] - - - MAMI - Multiple Address Match Interrupt - [21:16] - - - RD_ADDR_MATCH - Slave Read Address Match Interrupt - [22:22] - - - WR_ADDR_MATCH - Slave Write Address Match Interrupt - [23:23] - - - - - INTFL1 - Interrupt Status Register 1. - 0x10 - - - RX_OV - Receiver Overflow Interrupt. When operating as a slave receiver, this bit is set when you reach the first data bit and the RX FIFO and shift register are both full. - [0:0] - - - inactive - No Interrupt is Pending. - 0 - - - pending - An interrupt is pending. - 1 - - - - - TX_UN - Transmit Underflow Interrupt. When operating as a slave transmitter, this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet). - [1:1] - - - inactive - No Interrupt is Pending. - 0 - - - pending - An interrupt is pending. - 1 - - - - - START - START Condition Status Flag. - [2:2] - - - - - INTEN1 - Interrupt Staus Register 1. - 0x14 - read-write - - - RX_OV - Receiver Overflow Interrupt Enable. - [0:0] - - - dis - No Interrupt is Pending. - 0 - - - en - An interrupt is pending. - 1 - - - - - TX_UN - Transmit Underflow Interrupt Enable. - [1:1] - - - dis - No Interrupt is Pending. - 0 - - - en - An interrupt is pending. - 1 - - - - - START - START Condition Interrupt Enable. - [2:2] - - - - - FIFOLEN - FIFO Configuration Register. - 0x18 - - - RX_DEPTH - Receive FIFO Length. - [7:0] - read-only - - - TX_DEPTH - Transmit FIFO Length. - [15:8] - read-only - - - - - RXCTRL0 - Receive Control Register 0. - 0x1C - - - DNR - Do Not Respond. - [0:0] - - - respond - Always respond to address match. - 0 - - - not_respond_rx_fifo_empty - Do not respond to address match when RX_FIFO is not empty. - 1 - - - - - FLUSH - Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status. - [7:7] - - - not_flushed - FIFO not flushed. - 0 - - - flush - Flush RX_FIFO. - 1 - - - - - THD_LVL - Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold. - [11:8] - - - - - RXCTRL1 - Receive Control Register 1. - 0x20 - - - CNT - Receive Count Bits. These bits define the number of bytes to be received in a transaction, except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction. - [7:0] - - - LVL - Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0. - [11:8] - read-only - - - - - TXCTRL0 - Transmit Control Register 0. - 0x24 - - - PRELOAD_MODE - Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match. - [0:0] - - - TX_READY_MODE - Transmit FIFO Ready Manual Mode. - [1:1] - - - en - HW control of I2CTXRDY enabled. - 0 - - - dis - HW control of I2CTXRDY disabled. - 1 - - - - - GC_ADDR_FLUSH_DIS - TX FIFO General Call Address Match Auto Flush Disable. - [2:2] - - - en - Enabled. - 0 - - - dis - Disabled. - 1 - - - - - WR_ADDR_FLUSH_DIS - TX FIFO Slave Address Match Write Auto Flush Disable. - [3:3] - - - en - Enabled. - 0 - - - dis - Disabled. - 1 - - - - - RD_ADDR_FLUSH_DIS - TX FIFO Slave Address Match Read Auto Flush Disable. - [4:4] - - - en - Enabled. - 0 - - - dis - Disabled. - 1 - - - - - NACK_FLUSH_DIS - TX FIFO received NACK Auto Flush Disable. - [5:5] - - - en - Enabled. - 0 + Weak pull-up mode. + 1 - dis - Disabled. - 1 + pd + weak pull-down mode. + 2 + + + + EN1 + GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. + 0x68 + - FLUSH - Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation. - [7:7] + ALL + Mask of all of the pins on the port. + 0 + 32 - not_flushed - FIFO not flushed. + primary + Primary function selected. 0 - flush - Flush TX_FIFO. + secondary + Secondary function selected. 1 - - THD_VAL - Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold. - [11:8] - - TXCTRL1 - Transmit Control Register 1. - 0x28 + EN1_SET + GPIO Alternate Function Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN1 to 1, without affecting other bits in that register. + 0x6C - PRELOAD_RDY - Transmit FIFO Preload Ready. - [0:0] - - - LAST - Transmit Last. - [1:1] - - - LVL - Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO. - [11:8] - read-only + ALL + Mask of all of the pins on the port. + 0 + 32 - FIFO - Data Register. - 0x2C + EN1_CLR + GPIO Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN1 to 0, without affecting other bits in that register. + 0x70 - DATA - Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location. + ALL + Mask of all of the pins on the port. 0 - 8 + 32 - MSTCTRL - Master Control Register. - 0x30 + EN2 + GPIO Alternate Function Enable Register. Each bit in this register selects between primary/secondary functions for the associated GPIO pin in this port. + 0x74 - START - Setting this bit to 1 will start a master transfer. - [0:0] - - - RESTART - Setting this bit to 1 will generate a repeated START. - [1:1] - - - STOP - Setting this bit to 1 will generate a STOP condition. - [2:2] - - - EX_ADDR_EN - Slave Extend Address Select. - [7:7] + ALL + Mask of all of the pins on the port. + 0 + 32 - 7_bits_address - 7-bit address. + primary + Primary function selected. 0 - 10_bits_address - 10-bit address. + secondary + Secondary function selected. 1 - - CODE - Master Code. - [10:8] - - - IGN_ACK - Master Ignore Acknowledge. - [12:12] - - - - - CLKLO - Clock Low Register. - 0x34 - - - LO - Clock low. In master mode, these bits define the SCL low period. In slave mode, these bits define the time SCL will be held low after data is outputted. - [8:0] - - CLKHI - Clock high Register. - 0x38 + EN2_SET + GPIO Alternate Function 2 Set. Writing a 1 to one or more bits in this register sets the bits in the same positions in GPIO_EN2 to 1, without affecting other bits in that register. + 0x78 - HI - Clock High. In master mode, these bits define the SCL high period. - [8:0] + ALL + Mask of all of the pins on the port. + 0 + 32 - HSCLK - Clock high Register. - 0x3C + EN2_CLR + GPIO Wake Alternate Function Clear. Writing a 1 to one or more bits in this register clears the bits in the same positions in GPIO_EN2 to 0, without affecting other bits in that register. + 0x7C - LO - Clock Low. This field sets the Hs-Mode clock low count. In Slave mode, this is the time SCL is held low after data is output on SDA. - [7:0] - - - HI - Clock High. This field sets the Hs-Mode clock high count. In Slave mode, this is the time SCL is held high after data is output on SDA - [15:8] + ALL + Mask of all of the pins on the port. + 0 + 32 - TIMEOUT - Timeout Register - 0x40 + HYSEN + GPIO Input Hysteresis Enable. + 0xA8 - SCL_TO_VAL - Timeout - [15:0] + ALL + Mask of all of the pins on the port. + 0 + 32 - DMA - DMA Register. - 0x48 + SRSEL + GPIO Slew Rate Enable Register. + 0xAC - TX_EN - TX channel enable. - [0:0] - - - dis - Disable. - 0 - - - en - Enable. - 1 - - - - - RX_EN - RX channel enable. - [1:1] + ALL + Mask of all of the pins on the port. + 0 + 32 - dis - Disable. + FAST + Fast Slew Rate selected. 0 - en - Enable. + SLOW + Slow Slew Rate selected. 1 @@ -6028,38 +3696,24 @@ - 4 - 4 - SLAVE_MULTI[%s] - Slave Address Register. - SLAVE0 - 0x4C - 32 - read-write + DS0 + GPIO Drive Strength 0 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. + 0xB0 - ADDR - Slave Address. - [9:0] - - - DIS - Slave Disable. - [10:10] - - - EXT_ADDR_EN - Extended Address Select. - [15:15] + ALL + Mask of all of the pins on the port. + 0 + 32 - 7_bits_address - 7-bit address. + ld + GPIO port pin is in low-drive mode. 0 - 10_bits_address - 10-bit address. + hd + GPIO port pin is in high-drive mode. 1 @@ -6067,50 +3721,47 @@ - SLAVE0 - Slave Address Register. - 0x4C - - - SLAVE1 - Slave Address Register. - 0x50 + DS1 + GPIO Drive Strength 1 Register. Each bit in this register selects the drive strength for the associated GPIO pin in this port. Refer to the Datasheet for sink/source current of GPIO pins in each mode. + 0xB4 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + - SLAVE2 - Slave Address Register. - 0x54 + PSSEL + GPIO Pull Select Mode. + 0xB8 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + - SLAVE3 - Slave Address Register. - 0x58 + VSSEL + GPIO Voltage Select. + 0xC0 + + + ALL + Mask of all of the pins on the port. + 0 + 32 + + - - - I2C1 - Inter-Integrated Circuit. 1 - 0x4001E000 - - I2C1 - I2C1 IRQ - 36 - - - - - I2C2 - Inter-Integrated Circuit. 2 - 0x4001F000 - - I2C2 - I2C2 IRQ - 62 - - - + ICC0 Instruction Cache Controller Registers @@ -10854,7 +8505,7 @@ FSTAT - funcstat register. + Function Status register. 0x100 read-only @@ -10920,38 +8571,6 @@ 0 1 - - TRNG - TRNG Function. - 2 - 1 - - - no - 0 - - - yes - 1 - - - - - AES - AES Block. - 3 - 1 - - - no - 0 - - - yes - 1 - - - @@ -11337,8 +8956,8 @@ - MST_MODE - Master Mode Enable. + CTRLR_MODE + Controller Mode Enable. 1 1 @@ -11355,8 +8974,8 @@ - SS_IO - Slave Select 0, IO direction, to support Multi-Master mode,Slave Select 0 can be input in Master mode. This bit has no effect in slave mode. + TS_IO + Target Select 0, IO direction, to support Multi-Controller mode, Target Select 0 can be input in Controller mode. This bit has no effect in target mode. 4 1 @@ -11386,8 +9005,8 @@ - SS_CTRL - Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction. + TS_CTRL + Target Select Control. Used in Controller mode to control the behavior of the Target Select signal at the end of a transaction. 8 1 @@ -11404,8 +9023,8 @@ - SS_ACTIVE - Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected. + TS_ACTIVE + Target Select, when in Master mode selects which Target devices are selected. More than one Target device can be selected. 16 4 @@ -11643,8 +9262,8 @@ - SSPOL - Slave Select Polarity, each Slave Select can have unique polarity. + TSPOL + Target Select Polarity, each Target Select can have unique polarity. 16 4 @@ -11673,8 +9292,8 @@ - SSTIME - Register for controlling SPI peripheral/Slave Select Timing. + TSTIME + Register for controlling SPI peripheral/Target Select Timing. 0x10 read-write @@ -11952,8 +9571,8 @@ - SSA - Slave Select Asserted. + TSA + Target Select Asserted. 4 1 @@ -11965,8 +9584,8 @@ - SSD - Slave Select Deasserted. + TSD + Target Select Deasserted. 5 1 @@ -12004,8 +9623,8 @@ - MST_DONE - Master Done, set when SPI Master has completed any transactions. + CTRLR_DONE + Controller Done, set when SPI Master has completed any transactions. 11 1 @@ -12149,8 +9768,8 @@ - SSA - Slave Select Asserted interrupt enable. + TSA + Target Select Asserted interrupt enable. 4 1 @@ -12167,8 +9786,8 @@ - SSD - Slave Select Deasserted interrupt enable. + TSD + Target Select Deasserted interrupt enable. 5 1 @@ -12221,8 +9840,8 @@ - MST_DONE - Master Done interrupt enable. + CTRLR_DONE + Controller Done interrupt enable. 11 1 @@ -12481,17 +10100,6 @@ - - SPI1 - SPI peripheral. 1 - 0x40046000 - - SPI1 - SPI1 IRQ - 32 - - - TMR Low-Power Configurable Timer @@ -14207,24 +11815,6 @@ - - UART1 - UART Low Power Registers 1 - 0x40043000 - - - - UART2 - UART Low Power Registers 2 - 0x40044000 - - - - UART3 - UART Low Power Registers 3 - 0x40081400 - - WDT Windowed Watchdog Timer @@ -14816,17 +12406,6 @@ - - WDT1 - Windowed Watchdog Timer 1 - 0x40080800 - - WDT1 - WDT1 IRQ - 57 - - - WUT 32-bit reloadable timer that can be used for timing and wakeup. diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sir_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sir_regs.h index 7b9be1b01bb..995328c05c0 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sir_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sir_regs.h @@ -139,7 +139,7 @@ typedef struct { /** * @ingroup sir_registers * @defgroup SIR_FSTAT SIR_FSTAT - * @brief funcstat register. + * @brief Function Status register. * @{ */ #define MXC_F_SIR_FSTAT_FPU_POS 0 /**< FSTAT_FPU Position */ @@ -162,12 +162,6 @@ typedef struct { #define MXC_F_SIR_SFSTAT_SECBOOT_POS 0 /**< SFSTAT_SECBOOT Position */ #define MXC_F_SIR_SFSTAT_SECBOOT ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_SECBOOT_POS)) /**< SFSTAT_SECBOOT Mask */ -#define MXC_F_SIR_SFSTAT_TRNG_POS 2 /**< SFSTAT_TRNG Position */ -#define MXC_F_SIR_SFSTAT_TRNG ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_TRNG_POS)) /**< SFSTAT_TRNG Mask */ - -#define MXC_F_SIR_SFSTAT_AES_POS 3 /**< SFSTAT_AES Position */ -#define MXC_F_SIR_SFSTAT_AES ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_AES_POS)) /**< SFSTAT_AES Mask */ - /**@} end of group SIR_SFSTAT_Register */ #ifdef __cplusplus diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spi_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spi_regs.h index 4935a745e1c..076ccdcd6e4 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spi_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spi_regs.h @@ -80,7 +80,7 @@ typedef struct { __IO uint32_t ctrl0; /**< \b 0x04: SPI CTRL0 Register */ __IO uint32_t ctrl1; /**< \b 0x08: SPI CTRL1 Register */ __IO uint32_t ctrl2; /**< \b 0x0C: SPI CTRL2 Register */ - __IO uint32_t sstime; /**< \b 0x10: SPI SSTIME Register */ + __IO uint32_t tstime; /**< \b 0x10: SPI TSTIME Register */ __IO uint32_t clkctrl; /**< \b 0x14: SPI CLKCTRL Register */ __R uint32_t rsv_0x18; __IO uint32_t dma; /**< \b 0x1C: SPI DMA Register */ @@ -104,7 +104,7 @@ typedef struct { #define MXC_R_SPI_CTRL0 ((uint32_t)0x00000004UL) /**< Offset from SPI Base Address: 0x0004 */ #define MXC_R_SPI_CTRL1 ((uint32_t)0x00000008UL) /**< Offset from SPI Base Address: 0x0008 */ #define MXC_R_SPI_CTRL2 ((uint32_t)0x0000000CUL) /**< Offset from SPI Base Address: 0x000C */ -#define MXC_R_SPI_SSTIME ((uint32_t)0x00000010UL) /**< Offset from SPI Base Address: 0x0010 */ +#define MXC_R_SPI_TSTIME ((uint32_t)0x00000010UL) /**< Offset from SPI Base Address: 0x0010 */ #define MXC_R_SPI_CLKCTRL ((uint32_t)0x00000014UL) /**< Offset from SPI Base Address: 0x0014 */ #define MXC_R_SPI_DMA ((uint32_t)0x0000001CUL) /**< Offset from SPI Base Address: 0x001C */ #define MXC_R_SPI_INTFL ((uint32_t)0x00000020UL) /**< Offset from SPI Base Address: 0x0020 */ @@ -156,28 +156,28 @@ typedef struct { #define MXC_F_SPI_CTRL0_EN_POS 0 /**< CTRL0_EN Position */ #define MXC_F_SPI_CTRL0_EN ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_EN_POS)) /**< CTRL0_EN Mask */ -#define MXC_F_SPI_CTRL0_MST_MODE_POS 1 /**< CTRL0_MST_MODE Position */ -#define MXC_F_SPI_CTRL0_MST_MODE ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_MST_MODE_POS)) /**< CTRL0_MST_MODE Mask */ +#define MXC_F_SPI_CTRL0_CTRLR_MODE_POS 1 /**< CTRL0_CTRLR_MODE Position */ +#define MXC_F_SPI_CTRL0_CTRLR_MODE ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_CTRLR_MODE_POS)) /**< CTRL0_CTRLR_MODE Mask */ -#define MXC_F_SPI_CTRL0_SS_IO_POS 4 /**< CTRL0_SS_IO Position */ -#define MXC_F_SPI_CTRL0_SS_IO ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_IO_POS)) /**< CTRL0_SS_IO Mask */ +#define MXC_F_SPI_CTRL0_TS_IO_POS 4 /**< CTRL0_TS_IO Position */ +#define MXC_F_SPI_CTRL0_TS_IO ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_TS_IO_POS)) /**< CTRL0_TS_IO Mask */ #define MXC_F_SPI_CTRL0_START_POS 5 /**< CTRL0_START Position */ #define MXC_F_SPI_CTRL0_START ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_START_POS)) /**< CTRL0_START Mask */ -#define MXC_F_SPI_CTRL0_SS_CTRL_POS 8 /**< CTRL0_SS_CTRL Position */ -#define MXC_F_SPI_CTRL0_SS_CTRL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_SS_CTRL_POS)) /**< CTRL0_SS_CTRL Mask */ +#define MXC_F_SPI_CTRL0_TS_CTRL_POS 8 /**< CTRL0_TS_CTRL Position */ +#define MXC_F_SPI_CTRL0_TS_CTRL ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_TS_CTRL_POS)) /**< CTRL0_TS_CTRL Mask */ -#define MXC_F_SPI_CTRL0_SS_ACTIVE_POS 16 /**< CTRL0_SS_ACTIVE Position */ -#define MXC_F_SPI_CTRL0_SS_ACTIVE ((uint32_t)(0xFUL << MXC_F_SPI_CTRL0_SS_ACTIVE_POS)) /**< CTRL0_SS_ACTIVE Mask */ -#define MXC_V_SPI_CTRL0_SS_ACTIVE_SS0 ((uint32_t)0x1UL) /**< CTRL0_SS_ACTIVE_SS0 Value */ -#define MXC_S_SPI_CTRL0_SS_ACTIVE_SS0 (MXC_V_SPI_CTRL0_SS_ACTIVE_SS0 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS0 Setting */ -#define MXC_V_SPI_CTRL0_SS_ACTIVE_SS1 ((uint32_t)0x2UL) /**< CTRL0_SS_ACTIVE_SS1 Value */ -#define MXC_S_SPI_CTRL0_SS_ACTIVE_SS1 (MXC_V_SPI_CTRL0_SS_ACTIVE_SS1 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS1 Setting */ -#define MXC_V_SPI_CTRL0_SS_ACTIVE_SS2 ((uint32_t)0x4UL) /**< CTRL0_SS_ACTIVE_SS2 Value */ -#define MXC_S_SPI_CTRL0_SS_ACTIVE_SS2 (MXC_V_SPI_CTRL0_SS_ACTIVE_SS2 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS2 Setting */ -#define MXC_V_SPI_CTRL0_SS_ACTIVE_SS3 ((uint32_t)0x8UL) /**< CTRL0_SS_ACTIVE_SS3 Value */ -#define MXC_S_SPI_CTRL0_SS_ACTIVE_SS3 (MXC_V_SPI_CTRL0_SS_ACTIVE_SS3 << MXC_F_SPI_CTRL0_SS_ACTIVE_POS) /**< CTRL0_SS_ACTIVE_SS3 Setting */ +#define MXC_F_SPI_CTRL0_TS_ACTIVE_POS 16 /**< CTRL0_TS_ACTIVE Position */ +#define MXC_F_SPI_CTRL0_TS_ACTIVE ((uint32_t)(0xFUL << MXC_F_SPI_CTRL0_TS_ACTIVE_POS)) /**< CTRL0_TS_ACTIVE Mask */ +#define MXC_V_SPI_CTRL0_TS_ACTIVE_SS0 ((uint32_t)0x1UL) /**< CTRL0_TS_ACTIVE_SS0 Value */ +#define MXC_S_SPI_CTRL0_TS_ACTIVE_SS0 (MXC_V_SPI_CTRL0_TS_ACTIVE_SS0 << MXC_F_SPI_CTRL0_TS_ACTIVE_POS) /**< CTRL0_TS_ACTIVE_SS0 Setting */ +#define MXC_V_SPI_CTRL0_TS_ACTIVE_SS1 ((uint32_t)0x2UL) /**< CTRL0_TS_ACTIVE_SS1 Value */ +#define MXC_S_SPI_CTRL0_TS_ACTIVE_SS1 (MXC_V_SPI_CTRL0_TS_ACTIVE_SS1 << MXC_F_SPI_CTRL0_TS_ACTIVE_POS) /**< CTRL0_TS_ACTIVE_SS1 Setting */ +#define MXC_V_SPI_CTRL0_TS_ACTIVE_SS2 ((uint32_t)0x4UL) /**< CTRL0_TS_ACTIVE_SS2 Value */ +#define MXC_S_SPI_CTRL0_TS_ACTIVE_SS2 (MXC_V_SPI_CTRL0_TS_ACTIVE_SS2 << MXC_F_SPI_CTRL0_TS_ACTIVE_POS) /**< CTRL0_TS_ACTIVE_SS2 Setting */ +#define MXC_V_SPI_CTRL0_TS_ACTIVE_SS3 ((uint32_t)0x8UL) /**< CTRL0_TS_ACTIVE_SS3 Value */ +#define MXC_S_SPI_CTRL0_TS_ACTIVE_SS3 (MXC_V_SPI_CTRL0_TS_ACTIVE_SS3 << MXC_F_SPI_CTRL0_TS_ACTIVE_POS) /**< CTRL0_TS_ACTIVE_SS3 Setting */ /**@} end of group SPI_CTRL0_Register */ @@ -257,41 +257,41 @@ typedef struct { #define MXC_F_SPI_CTRL2_THREE_WIRE_POS 15 /**< CTRL2_THREE_WIRE Position */ #define MXC_F_SPI_CTRL2_THREE_WIRE ((uint32_t)(0x1UL << MXC_F_SPI_CTRL2_THREE_WIRE_POS)) /**< CTRL2_THREE_WIRE Mask */ -#define MXC_F_SPI_CTRL2_SSPOL_POS 16 /**< CTRL2_SSPOL Position */ -#define MXC_F_SPI_CTRL2_SSPOL ((uint32_t)(0xFUL << MXC_F_SPI_CTRL2_SSPOL_POS)) /**< CTRL2_SSPOL Mask */ -#define MXC_V_SPI_CTRL2_SSPOL_SS0_HIGH ((uint32_t)0x1UL) /**< CTRL2_SSPOL_SS0_HIGH Value */ -#define MXC_S_SPI_CTRL2_SSPOL_SS0_HIGH (MXC_V_SPI_CTRL2_SSPOL_SS0_HIGH << MXC_F_SPI_CTRL2_SSPOL_POS) /**< CTRL2_SSPOL_SS0_HIGH Setting */ -#define MXC_V_SPI_CTRL2_SSPOL_SS1_HIGH ((uint32_t)0x2UL) /**< CTRL2_SSPOL_SS1_HIGH Value */ -#define MXC_S_SPI_CTRL2_SSPOL_SS1_HIGH (MXC_V_SPI_CTRL2_SSPOL_SS1_HIGH << MXC_F_SPI_CTRL2_SSPOL_POS) /**< CTRL2_SSPOL_SS1_HIGH Setting */ -#define MXC_V_SPI_CTRL2_SSPOL_SS2_HIGH ((uint32_t)0x4UL) /**< CTRL2_SSPOL_SS2_HIGH Value */ -#define MXC_S_SPI_CTRL2_SSPOL_SS2_HIGH (MXC_V_SPI_CTRL2_SSPOL_SS2_HIGH << MXC_F_SPI_CTRL2_SSPOL_POS) /**< CTRL2_SSPOL_SS2_HIGH Setting */ -#define MXC_V_SPI_CTRL2_SSPOL_SS3_HIGH ((uint32_t)0x8UL) /**< CTRL2_SSPOL_SS3_HIGH Value */ -#define MXC_S_SPI_CTRL2_SSPOL_SS3_HIGH (MXC_V_SPI_CTRL2_SSPOL_SS3_HIGH << MXC_F_SPI_CTRL2_SSPOL_POS) /**< CTRL2_SSPOL_SS3_HIGH Setting */ +#define MXC_F_SPI_CTRL2_TSPOL_POS 16 /**< CTRL2_TSPOL Position */ +#define MXC_F_SPI_CTRL2_TSPOL ((uint32_t)(0xFUL << MXC_F_SPI_CTRL2_TSPOL_POS)) /**< CTRL2_TSPOL Mask */ +#define MXC_V_SPI_CTRL2_TSPOL_SS0_HIGH ((uint32_t)0x1UL) /**< CTRL2_TSPOL_SS0_HIGH Value */ +#define MXC_S_SPI_CTRL2_TSPOL_SS0_HIGH (MXC_V_SPI_CTRL2_TSPOL_SS0_HIGH << MXC_F_SPI_CTRL2_TSPOL_POS) /**< CTRL2_TSPOL_SS0_HIGH Setting */ +#define MXC_V_SPI_CTRL2_TSPOL_SS1_HIGH ((uint32_t)0x2UL) /**< CTRL2_TSPOL_SS1_HIGH Value */ +#define MXC_S_SPI_CTRL2_TSPOL_SS1_HIGH (MXC_V_SPI_CTRL2_TSPOL_SS1_HIGH << MXC_F_SPI_CTRL2_TSPOL_POS) /**< CTRL2_TSPOL_SS1_HIGH Setting */ +#define MXC_V_SPI_CTRL2_TSPOL_SS2_HIGH ((uint32_t)0x4UL) /**< CTRL2_TSPOL_SS2_HIGH Value */ +#define MXC_S_SPI_CTRL2_TSPOL_SS2_HIGH (MXC_V_SPI_CTRL2_TSPOL_SS2_HIGH << MXC_F_SPI_CTRL2_TSPOL_POS) /**< CTRL2_TSPOL_SS2_HIGH Setting */ +#define MXC_V_SPI_CTRL2_TSPOL_SS3_HIGH ((uint32_t)0x8UL) /**< CTRL2_TSPOL_SS3_HIGH Value */ +#define MXC_S_SPI_CTRL2_TSPOL_SS3_HIGH (MXC_V_SPI_CTRL2_TSPOL_SS3_HIGH << MXC_F_SPI_CTRL2_TSPOL_POS) /**< CTRL2_TSPOL_SS3_HIGH Setting */ /**@} end of group SPI_CTRL2_Register */ /** * @ingroup spi_registers - * @defgroup SPI_SSTIME SPI_SSTIME - * @brief Register for controlling SPI peripheral/Slave Select Timing. + * @defgroup SPI_TSTIME SPI_TSTIME + * @brief Register for controlling SPI peripheral/Target Select Timing. * @{ */ -#define MXC_F_SPI_SSTIME_PRE_POS 0 /**< SSTIME_PRE Position */ -#define MXC_F_SPI_SSTIME_PRE ((uint32_t)(0xFFUL << MXC_F_SPI_SSTIME_PRE_POS)) /**< SSTIME_PRE Mask */ -#define MXC_V_SPI_SSTIME_PRE_256 ((uint32_t)0x0UL) /**< SSTIME_PRE_256 Value */ -#define MXC_S_SPI_SSTIME_PRE_256 (MXC_V_SPI_SSTIME_PRE_256 << MXC_F_SPI_SSTIME_PRE_POS) /**< SSTIME_PRE_256 Setting */ +#define MXC_F_SPI_TSTIME_PRE_POS 0 /**< TSTIME_PRE Position */ +#define MXC_F_SPI_TSTIME_PRE ((uint32_t)(0xFFUL << MXC_F_SPI_TSTIME_PRE_POS)) /**< TSTIME_PRE Mask */ +#define MXC_V_SPI_TSTIME_PRE_256 ((uint32_t)0x0UL) /**< TSTIME_PRE_256 Value */ +#define MXC_S_SPI_TSTIME_PRE_256 (MXC_V_SPI_TSTIME_PRE_256 << MXC_F_SPI_TSTIME_PRE_POS) /**< TSTIME_PRE_256 Setting */ -#define MXC_F_SPI_SSTIME_POST_POS 8 /**< SSTIME_POST Position */ -#define MXC_F_SPI_SSTIME_POST ((uint32_t)(0xFFUL << MXC_F_SPI_SSTIME_POST_POS)) /**< SSTIME_POST Mask */ -#define MXC_V_SPI_SSTIME_POST_256 ((uint32_t)0x0UL) /**< SSTIME_POST_256 Value */ -#define MXC_S_SPI_SSTIME_POST_256 (MXC_V_SPI_SSTIME_POST_256 << MXC_F_SPI_SSTIME_POST_POS) /**< SSTIME_POST_256 Setting */ +#define MXC_F_SPI_TSTIME_POST_POS 8 /**< TSTIME_POST Position */ +#define MXC_F_SPI_TSTIME_POST ((uint32_t)(0xFFUL << MXC_F_SPI_TSTIME_POST_POS)) /**< TSTIME_POST Mask */ +#define MXC_V_SPI_TSTIME_POST_256 ((uint32_t)0x0UL) /**< TSTIME_POST_256 Value */ +#define MXC_S_SPI_TSTIME_POST_256 (MXC_V_SPI_TSTIME_POST_256 << MXC_F_SPI_TSTIME_POST_POS) /**< TSTIME_POST_256 Setting */ -#define MXC_F_SPI_SSTIME_INACT_POS 16 /**< SSTIME_INACT Position */ -#define MXC_F_SPI_SSTIME_INACT ((uint32_t)(0xFFUL << MXC_F_SPI_SSTIME_INACT_POS)) /**< SSTIME_INACT Mask */ -#define MXC_V_SPI_SSTIME_INACT_256 ((uint32_t)0x0UL) /**< SSTIME_INACT_256 Value */ -#define MXC_S_SPI_SSTIME_INACT_256 (MXC_V_SPI_SSTIME_INACT_256 << MXC_F_SPI_SSTIME_INACT_POS) /**< SSTIME_INACT_256 Setting */ +#define MXC_F_SPI_TSTIME_INACT_POS 16 /**< TSTIME_INACT Position */ +#define MXC_F_SPI_TSTIME_INACT ((uint32_t)(0xFFUL << MXC_F_SPI_TSTIME_INACT_POS)) /**< TSTIME_INACT Mask */ +#define MXC_V_SPI_TSTIME_INACT_256 ((uint32_t)0x0UL) /**< TSTIME_INACT_256 Value */ +#define MXC_S_SPI_TSTIME_INACT_256 (MXC_V_SPI_TSTIME_INACT_256 << MXC_F_SPI_TSTIME_INACT_POS) /**< TSTIME_INACT_256 Setting */ -/**@} end of group SPI_SSTIME_Register */ +/**@} end of group SPI_TSTIME_Register */ /** * @ingroup spi_registers @@ -371,11 +371,11 @@ typedef struct { #define MXC_F_SPI_INTFL_RX_FULL_POS 3 /**< INTFL_RX_FULL Position */ #define MXC_F_SPI_INTFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_RX_FULL_POS)) /**< INTFL_RX_FULL Mask */ -#define MXC_F_SPI_INTFL_SSA_POS 4 /**< INTFL_SSA Position */ -#define MXC_F_SPI_INTFL_SSA ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_SSA_POS)) /**< INTFL_SSA Mask */ +#define MXC_F_SPI_INTFL_TSA_POS 4 /**< INTFL_TSA Position */ +#define MXC_F_SPI_INTFL_TSA ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TSA_POS)) /**< INTFL_TSA Mask */ -#define MXC_F_SPI_INTFL_SSD_POS 5 /**< INTFL_SSD Position */ -#define MXC_F_SPI_INTFL_SSD ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_SSD_POS)) /**< INTFL_SSD Mask */ +#define MXC_F_SPI_INTFL_TSD_POS 5 /**< INTFL_TSD Position */ +#define MXC_F_SPI_INTFL_TSD ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TSD_POS)) /**< INTFL_TSD Mask */ #define MXC_F_SPI_INTFL_FAULT_POS 8 /**< INTFL_FAULT Position */ #define MXC_F_SPI_INTFL_FAULT ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_FAULT_POS)) /**< INTFL_FAULT Mask */ @@ -383,8 +383,8 @@ typedef struct { #define MXC_F_SPI_INTFL_ABORT_POS 9 /**< INTFL_ABORT Position */ #define MXC_F_SPI_INTFL_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_ABORT_POS)) /**< INTFL_ABORT Mask */ -#define MXC_F_SPI_INTFL_MST_DONE_POS 11 /**< INTFL_MST_DONE Position */ -#define MXC_F_SPI_INTFL_MST_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_MST_DONE_POS)) /**< INTFL_MST_DONE Mask */ +#define MXC_F_SPI_INTFL_CTRLR_DONE_POS 11 /**< INTFL_CTRLR_DONE Position */ +#define MXC_F_SPI_INTFL_CTRLR_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_CTRLR_DONE_POS)) /**< INTFL_CTRLR_DONE Mask */ #define MXC_F_SPI_INTFL_TX_OV_POS 12 /**< INTFL_TX_OV Position */ #define MXC_F_SPI_INTFL_TX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_OV_POS)) /**< INTFL_TX_OV Mask */ @@ -418,11 +418,11 @@ typedef struct { #define MXC_F_SPI_INTEN_RX_FULL_POS 3 /**< INTEN_RX_FULL Position */ #define MXC_F_SPI_INTEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_RX_FULL_POS)) /**< INTEN_RX_FULL Mask */ -#define MXC_F_SPI_INTEN_SSA_POS 4 /**< INTEN_SSA Position */ -#define MXC_F_SPI_INTEN_SSA ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_SSA_POS)) /**< INTEN_SSA Mask */ +#define MXC_F_SPI_INTEN_TSA_POS 4 /**< INTEN_TSA Position */ +#define MXC_F_SPI_INTEN_TSA ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TSA_POS)) /**< INTEN_TSA Mask */ -#define MXC_F_SPI_INTEN_SSD_POS 5 /**< INTEN_SSD Position */ -#define MXC_F_SPI_INTEN_SSD ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_SSD_POS)) /**< INTEN_SSD Mask */ +#define MXC_F_SPI_INTEN_TSD_POS 5 /**< INTEN_TSD Position */ +#define MXC_F_SPI_INTEN_TSD ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TSD_POS)) /**< INTEN_TSD Mask */ #define MXC_F_SPI_INTEN_FAULT_POS 8 /**< INTEN_FAULT Position */ #define MXC_F_SPI_INTEN_FAULT ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_FAULT_POS)) /**< INTEN_FAULT Mask */ @@ -430,8 +430,8 @@ typedef struct { #define MXC_F_SPI_INTEN_ABORT_POS 9 /**< INTEN_ABORT Position */ #define MXC_F_SPI_INTEN_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_ABORT_POS)) /**< INTEN_ABORT Mask */ -#define MXC_F_SPI_INTEN_MST_DONE_POS 11 /**< INTEN_MST_DONE Position */ -#define MXC_F_SPI_INTEN_MST_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_MST_DONE_POS)) /**< INTEN_MST_DONE Mask */ +#define MXC_F_SPI_INTEN_CTRLR_DONE_POS 11 /**< INTEN_CTRLR_DONE Position */ +#define MXC_F_SPI_INTEN_CTRLR_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_CTRLR_DONE_POS)) /**< INTEN_CTRLR_DONE Mask */ #define MXC_F_SPI_INTEN_TX_OV_POS 12 /**< INTEN_TX_OV Position */ #define MXC_F_SPI_INTEN_TX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_OV_POS)) /**< INTEN_TX_OV Mask */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h deleted file mode 100644 index fe34a75832e..00000000000 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h +++ /dev/null @@ -1,101 +0,0 @@ -/****************************************************************************** - * - * Copyright (C) 2024 Analog Devices, Inc. - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - ******************************************************************************/ - -#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_SYSTEM_MAX32657_H_ -#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_SYSTEM_MAX32657_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ - -/* NOTE: HIRC was previously named CRYPTO */ -#ifdef CRYPTO_FREQ -#warning WARNING: CRYPTO_FREQ does not exist in MAX78000, replace with HIRC_FREQ! -#define HIRC_FREQ CRYPTO_FREQ -#endif - -/* NOTE: EXTCLK needs to be defined by user based on the clock they supply */ -#ifndef EXTCLK_FREQ -#define EXTCLK_FREQ 75000000 -#endif - -/* NOTE: This is the nominal value for INRO. The actual value may vary from chip to chip. - Update if use of this oscillator requires precise timing.*/ -/* NOTE: INRO was previously named NANORING */ -#ifndef INRO_FREQ -#define INRO_FREQ 8000 -#endif - -#ifndef IPO_FREQ -#define IPO_FREQ 100000000 -#endif - -#ifndef ISO_FREQ -#define ISO_FREQ 60000000 -#endif - -#ifndef ERFO_FREQ -#define ERFO_FREQ 32000000 -#endif - -#ifndef IBRO_FREQ -#define IBRO_FREQ 7372800 -#endif - -#ifndef ERTCO_FREQ -#define ERTCO_FREQ 32768 -#endif - -#ifndef HIRC_FREQ -#define HIRC_FREQ IPO_FREQ -#endif - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ -#ifdef PeripheralClock -#warning PeripheralClock define is being overidden. -#else -#define PeripheralClock (SystemCoreClock / 2) /*!< Peripheral Clock Frequency */ -#endif - -/* - * Initialize the system - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -void SystemInit(void); - -/* - * Update SystemCoreClock variable - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -void SystemCoreClockUpdate(void); - -#ifdef __cplusplus -} -#endif - -#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_SYSTEM_MAX32657_H_ From 326905c1b974184e4581d13b14ebfbdd70fd333c Mon Sep 17 00:00:00 2001 From: Woo Date: Tue, 30 Apr 2024 10:03:06 -0500 Subject: [PATCH 19/93] Re-add files that were accidentally removed --- .../Device/Maxim/MAX32657/Include/max32657.h | 757 ++++++++++++++++++ .../Maxim/MAX32657/Include/system_max32657.h | 101 +++ 2 files changed, 858 insertions(+) create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h new file mode 100644 index 00000000000..c6c60785f1e --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h @@ -0,0 +1,757 @@ +/** + * @file max32657.h + * @brief Device-specific perhiperal header file + */ + +/****************************************************************************** + * + * Analog Devices, Inc.), + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_MAX32657_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_MAX32657_H_ + +#ifndef TARGET_NUM +#define TARGET_NUM 32657 +#endif + +#define MXC_NUMCORES 1 + +#include + +#ifndef FALSE +#define FALSE (0) +#endif + +#ifndef TRUE +#define TRUE (1) +#endif + +/* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */ +#if defined(__GNUC__) +#ifndef __weak +#define __weak __attribute__((weak)) +#endif + +#elif defined(__CC_ARM) + +#define inline __inline +#pragma anon_unions + +#endif + +/* ================================================================================ */ +/* ================== Interrupt Number Table Section ================== */ +/* ================================================================================ */ + +// clang-format off +typedef enum { + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + MemoryManagement_IRQn = -12, + BusFault_IRQn = -11, + UsageFault_IRQn = -10, + SVCall_IRQn = -5, + DebugMonitor_IRQn = -4, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + + /* Device-specific interrupt sources (external to ARM core) */ + /* table entry number */ + /* |||| */ + /* |||| table offset address */ + /* vvvv vvvvvv */ + + ICE_IRQn = 0, /* 0x10 0x0040 16: ICE Unlock */ + WDT_IRQn, /* 0x11 0x0044 17: Watchdog Timer */ + RTC_IRQn, /* 0x12 0x0048 18: RTC */ + TRNG_IRQn, /* 0x13 0x004C 19: True Random Number Generator */ + TMR0_IRQn, /* 0x14 0x0050 20: Timer 0 */ + TMR1_IRQn, /* 0x15 0x0054 21: Timer 1 */ + TMR2_IRQn, /* 0x16 0x0058 22: Timer 2 */ + TMR3_IRQn, /* 0x17 0x005C 23: Timer 3 */ + TMR4_IRQn, /* 0x18 0x0060 24: Timer 4 */ + TMR5_IRQn, /* 0x19 0x0064 25: Timer 5 */ + I3C_IRQn, /* 0x1A 0x0068 26: I3C */ + UART_IRQn, /* 0x1B 0x006C 27: UART */ + SPI_IRQn, /* 0x1C 0x0070 28: SPI */ + FLC_IRQn, /* 0x1D 0x0074 29: FLC */ + GPIO0_IRQn, /* 0x1E 0x0078 30: GPIO0 */ + RSV15_IRQn, /* 0x1F 0x007C 31: Reserved */ + DMA0_CH0_IRQn, /* 0x20 0x0080 32: DMA0 Channel 0 */ + DMA0_CH1_IRQn, /* 0x21 0x0084 33: DMA0 Channel 1 */ + DMA0_CH2_IRQn, /* 0x22 0x0088 34: DMA0 Channel 2 */ + DMA0_CH3_IRQn, /* 0x23 0x008C 35: DMA0 Channel 3 */ + DMA1_CH0_IRQn, /* 0x24 0x0090 36: DMA1 Channel 0 */ + DMA1_CH1_IRQn, /* 0x25 0x0094 37: DMA1 Channel 1 */ + DMA1_CH2_IRQn, /* 0x26 0x0098 38: DMA1 CHannel 2 */ + DMA1_CH3_IRQn, /* 0x27 0x009C 39: DMA1 Channel 3 */ + WUT0_IRQn, /* 0x28 0x00A0 40: Wakeup Timer 0 */ + WUT1_IRQn, /* 0x29 0x00A4 41: Wakeup TImer 1 */ + GPIOWAKE_IRQn, /* 0x2A 0x00A8 42: GPIO Wakeup */ + CRC_IRQn, /* 0x2B 0x00AC 43: CRC */ + AES_IRQn, /* 0x2C 0x00B0 44: AES */ + ERFO_IRQn, /* 0x2D 0x00B4 45: ERFO Ready */ + BOOST_IRQn, /* 0x2E 0x00B8 46: Boost Controller */ + ECC_IRQn, /* 0x2F 0x00BC 47: ECC */ + BTLE_TX_DONE_IRQn, /* 0x30 0x00C0 48: BTLE TX Done */ + BTLE_RX_RCVD_IRQn, /* 0x31 0x00C4 49: BTLE RX Received */ + BTLE_RX_ENG_DET_IRQn, /* 0x32 0x00C8 50: BTLE RX Energy Detected */ + BTLE_SFD_DET_IRQn, /* 0x33 0x00CC 51: BTLE SFD Detected */ + BTLE_SFD_TO_IRQn, /* 0x34 0x00D0 52: BTLE SFD Timeout */ + BTLE_GP_EVENT_IRQn, /* 0x35 0x00D4 53: BTLE BTLE Timestamp */ + BTLE_CFO_IRQn, /* 0x36 0x00D8 54: BTLE CFO Done */ + BTLE_SIG_DET_IRQn, /* 0x37 0x00DC 55: BTLE Signal Detected */ + BTLE_AGC_EVENT_IRQn, /* 0x38 0x00E0 56: BTLE AGC Event */ + BTLE_RFFE_SPIM_IRQn, /* 0x39 0x00E4 57: BTLE RFFE SPIM Done */ + BTLE_TX_AES_IRQn, /* 0x3A 0x00E8 58: BTLE TX AES Done */ + BTLE_RX_AES_IRQn, /* 0x3B 0x00EC 59: BTLE RX AES Done */ + BTLE_INV_APB_ADDR_IRQn, /* 0x3C 0x00F0 60: BTLE Invalid APB Address */ + BTLE_IQ_DATA_VALID_IRQn, /* 0x3D 0x00F4 61:BTLE IQ Data Valid */ + BTLE_XXXX_IRQn, /* 0x3E 0x00F8 62: BTLE XXXX TODO(ME30): Verify BTLE IRQs */ + RSV47_IRQn, /* 0x3F 0x00FC 63: Reserved */ + MPC_IRQn, /* 0x40 0x0100 64: MPC Combined (Secure) */ + PPC_IRQn, /* 0x41 0x0104 65: PPC Combined (Secure) */ + RSV50_IRQn, /* 0x42 0x0108 66: Reserved */ + RSV51_IRQn, /* 0x43 0x010C 67: Reserved */ + RSV52_IRQn, /* 0x44 0x0110 68: Reserved */ + RSV53_IRQn, /* 0x45 0x0114 69: Reserved */ + MXC_IRQ_EXT_COUNT, +} IRQn_Type; +// clang-format on + +#define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16) + +/* ================================================================================ */ +/* ================== Processor Section ================== */ +/* ================================================================================ */ + +#define __CM33_REV 0x0000U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ + +/* ================================================================================ */ +/* ================== Device Specific Memory Section ================== */ +/* ================================================================================ */ + +/* Non-secure Regions */ +#define MXC_FLASH_NS_MEM_BASE 0x01000000UL +#define MXC_FLASH_NS_PAGE_SIZE 0x00002000UL +#define MXC_FLASH_NS_MEM_SIZE 0x00100000UL +#define MXC_SRAM_NS_MEM_BASE 0x20000000UL +#define MXC_SRAM_NS_MEM_SIZE 0x00040000UL + +/* Secure Regions */ +/* ROM is always in secure region. */ +#define MXC_ROM_MEM_BASE 0x00000000UL +#define MXC_ROM_MEM_SIZE 0x00010000UL +#define MXC_FLASH_S_MEM_BASE 0x11000000UL +#define MXC_FLASH_S_PAGE_SIZE 0x00002000UL +#define MXC_FLASH_S_MEM_SIZE 0x00100000UL +#define MXC_INFO_S_MEM_BASE 0x12000000UL +#define MXC_INFO_S_MEM_SIZE 0x00004000UL +#define MXC_SRAM_S_MEM_BASE 0x30000000UL +#define MXC_SRAM_S_MEM_SIZE 0x00040000UL + +/* Secure Region name redefinitions for explicit use */ +#define MXC_FLASH_MEM_BASE MXC_FLASH_S_MEM_BASE +#define MXC_FLASH_PAGE_SIZE MXC_FLASH_S_PAGE_SIZE +#define MXC_FLASH_MEM_SIZE MXC_FLASH_S_MEM_SIZE +#define MXC_INFO_MEM_BASE MXC_INFO_S_MEM_BASE +#define MXC_INFO_MEM_SIZE MXC_INFO_S_MEM_SIZE +#define MXC_SRAM_MEM_BASE MXC_SRAM_S_MEM_BASE +#define MXC_SRAM_MEM_SIZE MXC_SRAM_S_MEM_SIZE + +/* ================================================================================ */ +/* ================ Device Specific Peripheral Section ================ */ +/* ================================================================================ */ + +/* + Base addresses and configuration settings for all MAX78000 peripheral modules. +*/ + +/******************************************************************************/ +/* Global control */ + +/* Non-secure Mapping */ +#define MXC_BASE_GCR_NS ((uint32_t)0x40000000UL) +#define MXC_GCR_NS ((mxc_gcr_regs_t *)MXC_BASE_GCR_NS) + +/* Secure Mapping */ +#define MXC_BASE_GCR_S ((uint32_t)0x50000000UL) +#define MXC_GCR_S ((mxc_gcr_regs_t *)MXC_BASE_GCR_S) + +#define MXC_BASE_GCR MXC_BASE_GCR_S +#define MXC_GCR MXC_GCR_S + +/******************************************************************************/ +/* Non-battery backed SI Registers */ + +/* Non-secure Mapping */ +#define MXC_BASE_SIR_NS ((uint32_t)0x40000400UL) +#define MXC_SIR_NS ((mxc_sir_regs_t *)MXC_BASE_SIR_NS) + +/* Secure Mapping */ +#define MXC_BASE_SIR_S ((uint32_t)0x50000400UL) +#define MXC_SIR_S ((mxc_sir_regs_t *)MXC_BASE_SIR_S) + +#define MXC_BASE_SIR MXC_BASE_SIR_S +#define MXC_SIR MXC_SIR_S + +/******************************************************************************/ +/* Non-Battery Backed Function Control */ + +/* Non-secure Mapping */ +#define MXC_BASE_FCR_NS ((uint32_t)0x40000800UL) +#define MXC_FCR_NS ((mxc_fcr_regs_t *)MXC_BASE_FCR_NS) + +/* Secure Mapping */ +#define MXC_BASE_FCR_S ((uint32_t)0x50000800UL) +#define MXC_FCR_S ((mxc_fcr_regs_t *)MXC_BASE_FCR_S) + +/******************************************************************************/ +/* Windowed Watchdog Timer */ +#define MXC_CFG_WDT_INSTANCES (1) + +/* Non-secure Mapping */ +#define MXC_BASE_WDT_NS ((uint32_t)0x40003000UL) +#define MXC_WDT_NS ((mxc_wdt_regs_t *)MXC_BASE_WDT_NS) + +/* Secure Mapping */ +#define MXC_BASE_WDT_S ((uint32_t)0x50003000UL) +#define MXC_WDT_S ((mxc_wdt_regs_t *)MXC_BASE_WDT_S) + +#define MXC_BASE_WDT MXC_BASE_WDT_S +#define MXC_WDT MXC_WDT_S + +/******************************************************************************/ +/* SVM Controller */ + +/* Non-secure Mapping */ +#define MXC_BASE_SVM_NS ((uint32_t)0x40004800UL) +#define MXC_SVM_NS //TODO(ME30): Add SVM controller registers. + +/* Secure Mapping */ +#define MXC_BASE_SVM_S ((uint32_t)0x50004800UL) +#define MXC_SVM_S //TODO(ME30): Add SVM controller registers. + +#define MXC_BASE_SVM MXC_BASE_SVM_S +#define MXC_SVM //TODO(ME30): Add SVM controller registers. + +/******************************************************************************/ +/* Boost Controller */ + +/* Non-secure Mapping */ +#define MXC_BASE_BOOST_NS ((uint32_t)0x40004C00UL) +#define MXC_BOOST_NS //TODO(ME30): Add Boost controller registers. + +/* Secure Mapping */ +#define MXC_BASE_BOOST_S ((uint32_t)0x50004C00UL) +#define MXC_BOOST_S //TODO(ME30): Add Boost controller registers. + +#define MXC_BASE_BOOST MXC_BASE_BOOST_S +#define MXC_BOOST //TODO(ME30): Add Boost controller registers. + +/******************************************************************************/ +/* Trim System Initalization Register */ + +/* Non-secure Mapping */ +#define MXC_BASE_TRIMSIR_NS ((uint32_t)0x40005400UL) +#define MXC_TRIMSIR_NS ((mxc_trimsir_regs_t *)MXC_BASE_TRIMSIR_NS) + +/* Secure Mapping */ +#define MXC_BASE_TRIMSIR_S ((uint32_t)0x50005400UL) +#define MXC_TRIMSIR_S ((mxc_trimsir_regs_t *)MXC_BASE_TRIMSIR_S) + +#define MXC_BASE_TRIMSIR MXC_BASE_TRIMSIR_S +#define MXC_TRIMSIR MXC_TRIMSIR_S + +/******************************************************************************/ +/* Real Time Clock */ + +/* Non-secure Mapping */ +#define MXC_BASE_RTC_NS ((uint32_t)0x40006000UL) +#define MXC_RTC_NS ((mxc_rtc_regs_t *)MXC_BASE_RTC_NS) + +/* Secure Mapping */ +#define MXC_BASE_RTC_S ((uint32_t)0x50006000UL) +#define MXC_RTC_S ((mxc_rtc_regs_t *)MXC_BASE_RTC_S) + +#define MXC_BASE_RTC MXC_BASE_RTC_S +#define MXC_RTC MXC_RTC_S + +/******************************************************************************/ +/* Wake-Up Timer (WUT) */ +#define MXC_CFG_WUT_INSTANCES (2) + +/* Non-secure Mapping */ +#define MXC_BASE_WUT0_NS ((uint32_t)0x40006400UL) +#define MXC_WUT0_NS ((mxc_wut_regs_t *)MXC_BASE_WUT0_NS) +#define MXC_BASE_WUT1_NS ((uint32_t)0x40006600UL) +#define MXC_WUT1_NS ((mxc_wut_regs_t *)MXC_BASE_WUT1_NS) + +/* Secure Mapping */ +#define MXC_BASE_WUT0_S ((uint32_t)0x50006400UL) +#define MXC_WUT0_S ((mxc_wut_regs_t *)MXC_BASE_WUT0_S) +#define MXC_BASE_WUT1_S ((uint32_t)0x50006600UL) +#define MXC_WUT1_S ((mxc_wut_regs_t *)MXC_BASE_WUT1_S) + +#define MXC_BASE_WUT0 MXC_BASE_WUT0_S +#define MXC_WUT0 MXC_WUT0_S +#define MXC_BASE_WUT1 MXC_BASE_WUT1_S +#define MXC_WUT1 MXC_WUT1_S + +/******************************************************************************/ +/* Power Sequencer */ + +/* Non-secure Mapping */ +#define MXC_BASE_PWRSEQ_NS ((uint32_t)0x40006800UL) +#define MXC_PWRSEQ_NS ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ_NS) + +/* Secure Mapping */ +#define MXC_BASE_PWRSEQ_S ((uint32_t)0x50006800UL) +#define MXC_PWRSEQ_S ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ_S) + +#define MXC_BASE_PWRSEQ MXC_BASE_PWRSEQ_S +#define MXC_PWRSEQ MXC_PWRSEQ_S + +/******************************************************************************/ +/* Misc Control */ + +/* Non-secure Mapping */ +#define MXC_BASE_MCR_NS ((uint32_t)0x40006C00UL) +#define MXC_MCR_NS ((mxc_mcr_regs_t *)MXC_BASE_MCR_NS) + +/* Secure Mapping */ +#define MXC_BASE_MCR_S ((uint32_t)0x50006C00UL) +#define MXC_MCR_S ((mxc_mcr_regs_t *)MXC_BASE_MCR_S) + +#define MXC_BASE_MCR MXC_BASE_MCR_S +#define MXC_MCR MXC_MCR_S + +/******************************************************************************/ +/* AES */ + +/* Non-secure Mapping */ +#define MXC_BASE_AES_NS ((uint32_t)0x40007400UL) +#define MXC_AES_NS ((mxc_aes_regs_t *)MXC_BASE_AES_NS) + +/* Secure Mapping */ +#define MXC_BASE_AES_S ((uint32_t)0x50007400UL) +#define MXC_AES_S ((mxc_aes_regs_t *)MXC_BASE_AES_NS) + +#define MXC_BASE_AES MXC_BASE_AES_S +#define MXC_AES MXC_AES_S + +/******************************************************************************/ +/* AES Keys */ + +/* Non-secure Mapping */ +#define MXC_BASE_AESKEYS_NS ((uint32_t)0x40007800UL) +#define MXC_AESKEYS_NS ((mxc_aeskeys_regs_t *)MXC_BASE_AESKEYS_NS) + +/* Secure Mapping */ +#define MXC_BASE_AESKEYS_S ((uint32_t)0x50007800UL) +#define MXC_AESKEYS_S ((mxc_aeskeys_regs_t *)MXC_BASE_AESKEYS_S) + +#define MXC_BASE_AESKEYS MXC_BASE_AESKEYS_S +#define MXC_AESKEYS MXC_AESKEYS_S + +/******************************************************************************/ +/* GPIO */ +#define MXC_CFG_GPIO_INSTANCES (1) +#define MXC_CFG_GPIO_PINS_PORT (32) + +/* Non-secure Mapping */ +#define MXC_BASE_GPIO0_NS ((uint32_t)0x40008000UL) +#define MXC_GPIO0_NS ((mxc_gpio_regs_t *)MXC_BASE_GPIO0_NS) + +#define MXC_GPIO_NS_GET_IDX(p) ((p) == MXC_GPIO0_NS ? 0 : -1) +#define MXC_GPIO_NS_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0_NS : 0) + +/* Secure Mapping */ +#define MXC_BASE_GPIO0_S ((uint32_t)0x50008000UL) +#define MXC_GPIO0_S ((mxc_gpio_regs_t *)MXC_BASE_GPIO0_S) + +#define MXC_BASE_GPIO0 MXC_BASE_GPIO0_S +#define MXC_GPIO0 MXC_GPIO0_S + +/******************************************************************************/ +/* CRC */ + +/* Non-secure Mapping */ +#define MXC_BASE_CRC_NS ((uint32_t)0x4000F000UL) +#define MXC_CRC_NS ((mxc_crc_regs_t *)MXC_BASE_CRC_NS) + +/* Secure Mapping */ +#define MXC_BASE_CRC_S ((uint32_t)0x5000F000UL) +#define MXC_CRC_S ((mxc_crc_regs_t *)MXC_BASE_CRC_S) + +#define MXC_BASE_CRC MXC_BASE_CRC_S +#define MXC_CRC MXC_CRC_S + +/******************************************************************************/ +/* Timer */ +#define SEC(s) (((uint32_t)s) * 1000000UL) +#define MSEC(ms) (ms * 1000UL) +#define USEC(us) (us) + +#define MXC_CFG_TMR_INSTANCES (6) + +/* Non-secure Mapping */ +#define MXC_BASE_TMR0_NS ((uint32_t)0x40010000UL) +#define MXC_TMR0_NS ((mxc_tmr_regs_t *)MXC_BASE_TMR0_NS) +#define MXC_BASE_TMR1_NS ((uint32_t)0x40011000UL) +#define MXC_TMR1_NS ((mxc_tmr_regs_t *)MXC_BASE_TMR1_NS) +#define MXC_BASE_TMR2_NS ((uint32_t)0x40012000UL) +#define MXC_TMR2_NS ((mxc_tmr_regs_t *)MXC_BASE_TMR2_NS) +#define MXC_BASE_TMR3_NS ((uint32_t)0x40013000UL) +#define MXC_TMR3_NS ((mxc_tmr_regs_t *)MXC_BASE_TMR3_NS) +#define MXC_BASE_TMR4_NS ((uint32_t)0x40080C00UL) +#define MXC_TMR4_NS ((mxc_tmr_regs_t *)MXC_BASE_TMR4_NS) +#define MXC_BASE_TMR5_NS ((uint32_t)0x40081000UL) +#define MXC_TMR5_NS ((mxc_tmr_regs_t *)MXC_BASE_TMR5_NS) + +#define MXC_TMR_NS_GET_BASE(i) \ + ((i) == 0 ? MXC_BASE_TMR0_NS : \ + (i) == 1 ? MXC_BASE_TMR1_NS : \ + (i) == 2 ? MXC_BASE_TMR2_NS : \ + (i) == 3 ? MXC_BASE_TMR3_NS : \ + (i) == 4 ? MXC_BASE_TMR4_NS : \ + (i) == 5 ? MXC_BASE_TMR5_NS : \ + 0) + +#define MXC_TMR_NS_GET_TMR(i) \ + ((i) == 0 ? MXC_TMR0_NS : \ + (i) == 1 ? MXC_TMR1_NS : \ + (i) == 2 ? MXC_TMR2_NS : \ + (i) == 3 ? MXC_TMR3_NS : \ + (i) == 4 ? MXC_TMR4_NS : \ + (i) == 5 ? MXC_TMR5_NS : \ + 0) + +/* Secure Mapping */ +#define MXC_BASE_TMR0_S ((uint32_t)0x50010000UL) +#define MXC_TMR0_S ((mxc_tmr_regs_t *)MXC_BASE_TMR0_S) +#define MXC_BASE_TMR1_S ((uint32_t)0x50011000UL) +#define MXC_TMR1_S ((mxc_tmr_regs_t *)MXC_BASE_TMR1_S) +#define MXC_BASE_TMR2_S ((uint32_t)0x50012000UL) +#define MXC_TMR2_S ((mxc_tmr_regs_t *)MXC_BASE_TMR2_S) +#define MXC_BASE_TMR3_S ((uint32_t)0x50013000UL) +#define MXC_TMR3_S ((mxc_tmr_regs_t *)MXC_BASE_TMR3_S) +#define MXC_BASE_TMR4_S ((uint32_t)0x50080C00UL) +#define MXC_TMR4_S ((mxc_tmr_regs_t *)MXC_BASE_TMR4_S) +#define MXC_BASE_TMR5_S ((uint32_t)0x50081000UL) +#define MXC_TMR5_S ((mxc_tmr_regs_t *)MXC_BASE_TMR5_S) + +#define MXC_BASE_TMR0 MXC_BASE_TMR0_S +#define MXC_TMR0 MXC_TMR0_S +#define MXC_BASE_TMR1 MXC_BASE_TMR1_S +#define MXC_TMR1 MXC_TMR1_S +#define MXC_BASE_TMR2 MXC_BASE_TMR2_S +#define MXC_TMR2 MXC_TMR2_S +#define MXC_BASE_TMR3 MXC_BASE_TMR3_S +#define MXC_TMR3 MXC_TMR3_S +#define MXC_BASE_TMR4 MXC_BASE_TMR4_S +#define MXC_TMR4 MXC_TMR4_S +#define MXC_BASE_TMR5 MXC_BASE_TMR5_S +#define MXC_TMR5 MXC_TMR5_S + +#define MXC_TMR_S_GET_BASE(i) \ + ((i) == 0 ? MXC_BASE_TMR0_S : \ + (i) == 1 ? MXC_BASE_TMR1_S : \ + (i) == 2 ? MXC_BASE_TMR2_S : \ + (i) == 3 ? MXC_BASE_TMR3_S : \ + (i) == 4 ? MXC_BASE_TMR4_S : \ + (i) == 5 ? MXC_BASE_TMR5_S : \ + 0) + +#define MXC_TMR_S_GET_TMR(i) \ + ((i) == 0 ? MXC_TMR0_S : \ + (i) == 1 ? MXC_TMR1_S : \ + (i) == 2 ? MXC_TMR2_S : \ + (i) == 3 ? MXC_TMR3_S : \ + (i) == 4 ? MXC_TMR4_S : \ + (i) == 5 ? MXC_TMR5_S : \ + 0) + +#define MXC_TMR_GET_IRQ(i) \ + (IRQn_Type)((i) == 0 ? TMR0_IRQn : \ + (i) == 1 ? TMR1_IRQn : \ + (i) == 2 ? TMR2_IRQn : \ + (i) == 3 ? TMR3_IRQn : \ + (i) == 4 ? TMR4_IRQn : \ + (i) == 5 ? TMR5_IRQn : \ + 0) + +#define MXC_TMR_GET_IDX(p) \ + ((p) == MXC_TMR0_NS ? 0 : \ + (p) == MXC_TMR1_NS ? 1 : \ + (p) == MXC_TMR2_NS ? 2 : \ + (p) == MXC_TMR3_NS ? 3 : \ + (p) == MXC_TMR4_NS ? 4 : \ + (p) == MXC_TMR5_NS ? 5 : \ + (p) == MXC_TMR0_S ? 0 : \ + (p) == MXC_TMR1_S ? 1 : \ + (p) == MXC_TMR2_S ? 2 : \ + (p) == MXC_TMR3_S ? 3 : \ + (p) == MXC_TMR4_S ? 4 : \ + (p) == MXC_TMR5_S ? 5 : \ + -1) + +/******************************************************************************/ +/* I3C */ +/* Non-secure Mapping */ +#define MXC_BASE_I3C_NS ((uint32_t)0x4001D000UL) +#define MXC_I3C_NS ((mxc_i2c_regs_t *)MXC_BASE_I3C_NS) + +/* Secure Mapping */ +#define MXC_BASE_I3C_S ((uint32_t)0x5001D000UL) +#define MXC_I3C_S ((mxc_i2c_regs_t *)MXC_BASE_I3C_S) + +#define MXC_BASE_I3C MXC_BASE_I2C_S +#define MXC_I3C MXC_I3C_S + +#define MXC_I3C_FIFO_DEPTH (8) // TODO(ME30): Confirm this is correct. + +/******************************************************************************/ +/* DMA */ +#define MXC_DMA_CHANNELS (4) +#define MXC_DMA_INSTANCES (2) + +/* Non-secure Mapping */ +#define MXC_BASE_DMA0_NS ((uint32_t)0x40028000UL) +#define MXC_DMA0_NS ((mxc_dma_regs_t *)MXC_BASE_DMA0_NS) +/* DMA1 instance only for secure mode. */ + +/* Secure Mapping */ +#define MXC_BASE_DMA0_S ((uint32_t)0x50028000UL) +#define MXC_DMA0_S ((mxc_dma_regs_t *)MXC_BASE_DMA0_S) +#define MXC_BASE_DMA1_S ((uint32_t)0x50035000UL) +#define MXC_DMA1_S ((mxc_dma_regs_t *)MXC_BASE_DMA1_S) + +#define MXC_BASE_DMA0 MXC_BASE_DMA0_S +#define MXC_DMA0 MXC_DMA0_S +#define MXC_BASE_DMA1 MXC_BASE_DMA1_S +#define MXC_DMA1 MXC_DMA1_S + +#define MXC_DMA_CH_GET_IRQ(i) \ + ((IRQn_Type)(((i) == 0) ? DMA0_IRQn : \ + ((i) == 1) ? DMA1_IRQn : \ + ((i) == 2) ? DMA2_IRQn : \ + ((i) == 3) ? DMA3_IRQn : \ + 0)) + +/******************************************************************************/ +/* Flash Controller */ +#define MXC_FLC_INSTANCES (1) + +/* Secure Mapping Only */ +#define MXC_BASE_FLC ((uint32_t)0x50029000UL) +#define MXC_FLC ((mxc_flc_regs_t *)MXC_BASE_FLC) + +/* Added for consistency and explicitness */ +#define MXC_BASE_FLC_S MXC_BASE_FLC +#define MXC_FLC_S MXC_FLC + +/******************************************************************************/ +/* Internal Cache Controller */ +#define MXC_ICC_INSTANCES (1) + +/* Secure Mapping Only */ +#define MXC_BASE_ICC ((uint32_t)0x5002A000UL) +#define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC_S) + +/* Added for consistency and explicitness */ +#define MXC_BASE_ICC_S MXC_BASE_ICC +#define MXC_ICC_S MXC_ICC + +/******************************************************************************/ +/* UART / Serial Port Interface */ +#define MXC_UART_INSTANCES (1) +#define MXC_UART_FIFO_DEPTH (8) // TOD(ME30): Check this is correct. + +/* Non-secure Mapping */ +#define MXC_BASE_UART_NS ((uint32_t)0x40042000UL) +#define MXC_UART_NS ((mxc_uart_regs_t *)MXC_BASE_UART_NS) + +#define MXC_UART_NS_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0_NS : 0) +#define MXC_UART_NS_GET_UART(i) ((i) == 0 ? MXC_UART_NS : 0) + +/* Secure Mapping */ +#define MXC_BASE_UART_S ((uint32_t)0x50042000UL) +#define MXC_UART_S ((mxc_uart_regs_t *)MXC_BASE_UART_S) + +#define MXC_BASE_UART MXC_BASE_UART_S +#define MXC_UART MXC_UART_S + +#define MXC_UART_S_GET_UART(i) ((i) == 0 ? MXC_UART_S : 0) +#define MXC_UART_S_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0_S : 0) + +#define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : 0) +#define MXC_UART_GET_IDX(p) ((p) == MXC_UART_NS ? 0 : (p) == MXC_UART_S ? 0 : -1) + +/******************************************************************************/ +/* SPI */ +#define MXC_SPI_INSTANCES (1) +#define MXC_SPI_SS_INSTANCES (4) +#define MXC_SPI_FIFO_DEPTH (32) + +/* Non-secure Mapping */ +#define MXC_BASE_SPI_NS ((uint32_t)0x40046000UL) +#define MXC_SPI_NS ((mxc_spi_regs_t *)MXC_BASE_SPI_NS) + +#define MXC_SPI_NS_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI_NS : 0) +#define MXC_SPI_NS_GET_SPI(i) ((i) == 0 ? MXC_SPI_NS : 0) + +/* Secure Mapping */ +#define MXC_BASE_SPI_S ((uint32_t)0x50046000UL) +#define MXC_SPI_S ((mxc_spi_regs_t *)MXC_BASE_SPI_S) + +#define MXC_BASE_SPI MXC_BASE_SPI_S +#define MXC_SPI MXC_SPI_S + +#define MXC_SPI_S_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI_S : 0) +#define MXC_SPI_S_GET_SPI(i) ((i) == 0 ? MXC_SPI_S : 0) + +#define MXC_SPI_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SPI_IRQn : 0) +#define MXC_SPI_GET_IDX(p) ((p) == MXC_SPI_NS ? 0 : (p) == MXC_SPI_S ? 0 : -1) + +/******************************************************************************/ +/* TRNG */ + +/* Non-secure Mapping */ +#define MXC_BASE_TRNG_NS ((uint32_t)0x4004D000UL) +#define MXC_TRNG_NS ((mxc_trng_regs_t *)MXC_BASE_TRNG_NS) + +/* Secure Mapping */ +#define MXC_BASE_TRNG_S ((uint32_t)0x5004D000UL) +#define MXC_TRNG_S ((mxc_trng_regs_t *)MXC_BASE_TRNG_S) + +#define MXC_BASE_TRNG MXC_BASE_TRNG_S +#define MXC_TRNG MXC_TRNG_S + +/******************************************************************************/ +/* BTLE */ +// TODO(ME30): Verify with bluetooth team. This section does not exist in our prev +// bluetooth-supported parts. +/* Non-secure Mapping */ +#define MXC_BASE_BTLE_NS ((uint32_t)0x40050000UL) +#define MXC_BTLE_NS // TODO(ME30): Add BTLE related registers? This section doesn't exist for ME17. + +/* Secure Mapping */ +#define MXC_BASE_BTLE_S ((uint32_t)0x50050000UL) +#define MXC_BTLE_S // TODO(ME30): Add BTLE related registers? This section doesn't exist for ME17. + +#define MXC_BASE_BTLE MXC_BASE_BTLE_S +#define MXC_BTLE // TODO(ME30): Does this have registers? + +/******************************************************************************/ +/* Secure Privilege Control (SPC TZ) */ + +/* Secure Mapping Only */ +#define MXC_BASE_SPC ((uint32_t)0x50090000UL) +#define MXC_SPC // TODO(ME30): Does this have registers? + +#define MXC_BASE_SPC_S MXC_BASE_SPC +#define MXC_SPC_S // TODO(ME30): Does this have registers? + +/******************************************************************************/ +/* MPC */ + +/* Secure Mapping Only */ +#define MXC_BASE_MPC_SRAM0 ((uint32_t)0x50091000UL) +#define MXC_MPC_SRAM0 // TODO(ME30): Does this have registers? +#define MXC_BASE_MPC_SRAM1 ((uint32_t)0x50092000UL) +#define MXC_MPC_SRAM1 // TODO(ME30): Does this have registers? +#define MXC_BASE_MPC_SRAM2 ((uint32_t)0x50093000UL) +#define MXC_MPC_SRAM2 // TODO(ME30): Does this have registers? +#define MXC_BASE_MPC_SRAM3 ((uint32_t)0x50094000UL) +#define MXC_MPC_SRAM3 // TODO(ME30): Does this have registers? +#define MXC_BASE_MPC_SRAM4 ((uint32_t)0x50095000UL) +#define MXC_MPC_SRAM4 // TODO(ME30): Does this have registers? +#define MXC_BASE_MPC_FLASH ((uint32_t)0x50096000UL) +#define MXC_MPC_FLASH // TODO(ME30): Does this have registers? + +/* Added for consistency and explicitness */ +#define MXC_BASE_MPC_SRAM0_S MXC_BASE_MPC_SRAM0 +#define MXC_MPC_SRAM0_S // TODO(ME30): Does this have registers? +#define MXC_BASE_MPC_SRAM1_S MXC_BASE_MPC_SRAM1 +#define MXC_MPC_SRAM1_S // TODO(ME30): Does this have registers? +#define MXC_BASE_MPC_SRAM2_S MXC_BASE_MPC_SRAM2 +#define MXC_MPC_SRAM2_S // TODO(ME30): Does this have registers? +#define MXC_BASE_MPC_SRAM3_S MXC_BASE_MPC_SRAM3 +#define MXC_MPC_SRAM3_S // TODO(ME30): Does this have registers? +#define MXC_BASE_MPC_SRAM4_S MXC_BASE_MPC_SRAM4 +#define MXC_MPC_SRAM4_S // TODO(ME30): Does this have registers? +#define MXC_BASE_MPC_FLASH_S MXC_BASE_MPC_FLASH +#define MXC_MPC_FLASH_S // TODO(ME30): Does this have registers? + +/******************************************************************************/ +/* Bit Shifting */ +#define MXC_F_BIT_0 (1 << 0) +#define MXC_F_BIT_1 (1 << 1) +#define MXC_F_BIT_2 (1 << 2) +#define MXC_F_BIT_3 (1 << 3) +#define MXC_F_BIT_4 (1 << 4) +#define MXC_F_BIT_5 (1 << 5) +#define MXC_F_BIT_6 (1 << 6) +#define MXC_F_BIT_7 (1 << 7) +#define MXC_F_BIT_8 (1 << 8) +#define MXC_F_BIT_9 (1 << 9) +#define MXC_F_BIT_10 (1 << 10) +#define MXC_F_BIT_11 (1 << 11) +#define MXC_F_BIT_12 (1 << 12) +#define MXC_F_BIT_13 (1 << 13) +#define MXC_F_BIT_14 (1 << 14) +#define MXC_F_BIT_15 (1 << 15) +#define MXC_F_BIT_16 (1 << 16) +#define MXC_F_BIT_17 (1 << 17) +#define MXC_F_BIT_18 (1 << 18) +#define MXC_F_BIT_19 (1 << 19) +#define MXC_F_BIT_20 (1 << 20) +#define MXC_F_BIT_21 (1 << 21) +#define MXC_F_BIT_22 (1 << 22) +#define MXC_F_BIT_23 (1 << 23) +#define MXC_F_BIT_24 (1 << 24) +#define MXC_F_BIT_25 (1 << 25) +#define MXC_F_BIT_26 (1 << 26) +#define MXC_F_BIT_27 (1 << 27) +#define MXC_F_BIT_28 (1 << 28) +#define MXC_F_BIT_29 (1 << 29) +#define MXC_F_BIT_30 (1 << 30) +#define MXC_F_BIT_31 (1 << 31) + +/******************************************************************************/ +/* Bit Banding */ +#define BITBAND(reg, bit) \ + ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg)&0x0fffffff) << 5) + \ + ((bit) << 2)) + +#define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0) +#define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1) +#define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit)) + +#define MXC_SETFIELD(reg, mask, setting) ((reg) = ((reg) & ~(mask)) | ((setting) & (mask))) + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX326657_INCLUDE_MAX32657_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h new file mode 100644 index 00000000000..fe34a75832e --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h @@ -0,0 +1,101 @@ +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_SYSTEM_MAX32657_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_SYSTEM_MAX32657_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/*---------------------------------------------------------------------------- + Define clocks + *----------------------------------------------------------------------------*/ + +/* NOTE: HIRC was previously named CRYPTO */ +#ifdef CRYPTO_FREQ +#warning WARNING: CRYPTO_FREQ does not exist in MAX78000, replace with HIRC_FREQ! +#define HIRC_FREQ CRYPTO_FREQ +#endif + +/* NOTE: EXTCLK needs to be defined by user based on the clock they supply */ +#ifndef EXTCLK_FREQ +#define EXTCLK_FREQ 75000000 +#endif + +/* NOTE: This is the nominal value for INRO. The actual value may vary from chip to chip. + Update if use of this oscillator requires precise timing.*/ +/* NOTE: INRO was previously named NANORING */ +#ifndef INRO_FREQ +#define INRO_FREQ 8000 +#endif + +#ifndef IPO_FREQ +#define IPO_FREQ 100000000 +#endif + +#ifndef ISO_FREQ +#define ISO_FREQ 60000000 +#endif + +#ifndef ERFO_FREQ +#define ERFO_FREQ 32000000 +#endif + +#ifndef IBRO_FREQ +#define IBRO_FREQ 7372800 +#endif + +#ifndef ERTCO_FREQ +#define ERTCO_FREQ 32768 +#endif + +#ifndef HIRC_FREQ +#define HIRC_FREQ IPO_FREQ +#endif + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ +#ifdef PeripheralClock +#warning PeripheralClock define is being overidden. +#else +#define PeripheralClock (SystemCoreClock / 2) /*!< Peripheral Clock Frequency */ +#endif + +/* + * Initialize the system + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void); + +/* + * Update SystemCoreClock variable + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_SYSTEM_MAX32657_H_ From 471a09cb63a96c95a6d89d0e0ad81d5ad9ee49cb Mon Sep 17 00:00:00 2001 From: Woo Date: Tue, 30 Apr 2024 10:05:29 -0500 Subject: [PATCH 20/93] Remove ISO clock and set IPO to 50MHz --- .../CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h index fe34a75832e..95fbb55a4fd 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h @@ -48,11 +48,7 @@ extern "C" { #endif #ifndef IPO_FREQ -#define IPO_FREQ 100000000 -#endif - -#ifndef ISO_FREQ -#define ISO_FREQ 60000000 +#define IPO_FREQ 50000000 #endif #ifndef ERFO_FREQ From 03b7c759fe8b7f7acf2784368c9bb854629e1516 Mon Sep 17 00:00:00 2001 From: Woo Date: Tue, 30 Apr 2024 10:06:08 -0500 Subject: [PATCH 21/93] Fix for linter --- .../CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h index 95fbb55a4fd..c5a0952fe14 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h @@ -16,8 +16,8 @@ * ******************************************************************************/ -#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_SYSTEM_MAX32657_H_ -#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_SYSTEM_MAX32657_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_SYSTEM_MAX32657_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_SYSTEM_MAX32657_H_ #ifdef __cplusplus extern "C" { @@ -94,4 +94,4 @@ void SystemCoreClockUpdate(void); } #endif -#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32655_INCLUDE_SYSTEM_MAX32657_H_ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_SYSTEM_MAX32657_H_ From 77ce4ed30ca746b8adcdbc5841f9bd64ed794af3 Mon Sep 17 00:00:00 2001 From: Woo Date: Tue, 30 Apr 2024 10:07:50 -0500 Subject: [PATCH 22/93] Fix copyright --- Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h | 1 - 1 file changed, 1 deletion(-) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h index c6c60785f1e..396c9128ffb 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h @@ -5,7 +5,6 @@ /****************************************************************************** * - * Analog Devices, Inc.), * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); From 3927d4fe18ade1be8d8075c92ec79532c98fc5b8 Mon Sep 17 00:00:00 2001 From: Woo Date: Tue, 30 Apr 2024 12:34:39 -0500 Subject: [PATCH 23/93] Update ICC, SPI, and remove unsupported register files --- .../Device/Maxim/MAX32657/Include/dma_regs.h | 2 +- .../Device/Maxim/MAX32657/Include/icc_regs.h | 90 +- .../Maxim/MAX32657/Include/max32657.svd | 1582 ++++++++++++++--- .../Device/Maxim/MAX32657/Include/spi_regs.h | 32 +- .../Device/Maxim/MAX32657/Include/wut_regs.h | 12 +- .../Source/ADC/adc_reva_me30.svd | 362 ---- .../Source/ICC/icc_reva_me30.svd | 233 +++ .../Source/SPI/spi_reva_me30.svd | 116 +- .../Source/SYS/SVD/gcfr_me30.svd | 55 - .../Source/WUT/wut_reva_me30.svd | 4 +- 10 files changed, 1697 insertions(+), 791 deletions(-) delete mode 100644 Libraries/PeriphDrivers/Source/ADC/adc_reva_me30.svd create mode 100644 Libraries/PeriphDrivers/Source/ICC/icc_reva_me30.svd delete mode 100644 Libraries/PeriphDrivers/Source/SYS/SVD/gcfr_me30.svd diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/dma_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/dma_regs.h index ed564122112..822e7ff9cf8 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/dma_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/dma_regs.h @@ -86,7 +86,7 @@ typedef struct { __IO uint32_t inten; /**< \b 0x000: DMA INTEN Register */ __I uint32_t intfl; /**< \b 0x004: DMA INTFL Register */ __R uint32_t rsv_0x8_0xff[62]; - __IO mxc_dma_ch_regs_t ch[4]; /**< \b 0x100: DMA CH Register */ + __IO mxc_dma_ch_regs_t ch[4]; /**< \b 0x100: DMA CH Register */ } mxc_dma_regs_t; /* Register offsets for module DMA */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/icc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/icc_regs.h index 566417e782f..4a64475eb77 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/icc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/icc_regs.h @@ -71,12 +71,24 @@ extern "C" { * @ingroup icc_registers * Structure type to access the ICC Registers. */ +typedef struct { + __IO uint32_t lbound; /**< \b 0x0000: ICC LBOUND Register */ + __IO uint32_t hbound; /**< \b 0x004: ICC HBOUND Register */ +} mxc_icc_reg_regs_t; + typedef struct { __I uint32_t info; /**< \b 0x0000: ICC INFO Register */ __I uint32_t sz; /**< \b 0x0004: ICC SZ Register */ __R uint32_t rsv_0x8_0xff[62]; __IO uint32_t ctrl; /**< \b 0x0100: ICC CTRL Register */ - __R uint32_t rsv_0x104_0x6ff[383]; + __R uint32_t rsv_0x104_0x1ff[63]; + __IO uint32_t way; /**< \b 0x0200: ICC WAY Register */ + __IO uint32_t regctrl; /**< \b 0x0204: ICC REGCTRL Register */ + __IO mxc_icc_reg_regs_t region[15]; /**< \b 0x0208: ICC REGION Register */ + __R uint32_t rsv_0x244_0x2ff[47]; + __IO uint32_t pfmctrl; /**< \b 0x0300: ICC PFMCTRL Register */ + __IO uint32_t pfmcnt; /**< \b 0x0304: ICC PFMCNT Register */ + __R uint32_t rsv_0x308_0x6ff[254]; __IO uint32_t invalidate; /**< \b 0x0700: ICC INVALIDATE Register */ } mxc_icc_regs_t; @@ -87,9 +99,16 @@ typedef struct { * @brief ICC Peripheral Register Offsets from the ICC Base Peripheral Address. * @{ */ +#define MXC_R_ICC_LBOUND ((uint32_t)0x00000000UL) /**< Offset from ICC Base Address: 0x0000 */ +#define MXC_R_ICC_HBOUND ((uint32_t)0x00000004UL) /**< Offset from ICC Base Address: 0x0004 */ #define MXC_R_ICC_INFO ((uint32_t)0x00000000UL) /**< Offset from ICC Base Address: 0x0000 */ #define MXC_R_ICC_SZ ((uint32_t)0x00000004UL) /**< Offset from ICC Base Address: 0x0004 */ #define MXC_R_ICC_CTRL ((uint32_t)0x00000100UL) /**< Offset from ICC Base Address: 0x0100 */ +#define MXC_R_ICC_WAY ((uint32_t)0x00000200UL) /**< Offset from ICC Base Address: 0x0200 */ +#define MXC_R_ICC_REGCTRL ((uint32_t)0x00000204UL) /**< Offset from ICC Base Address: 0x0204 */ +#define MXC_R_ICC_REGION ((uint32_t)0x00000208UL) /**< Offset from ICC Base Address: 0x0208 */ +#define MXC_R_ICC_PFMCTRL ((uint32_t)0x00000300UL) /**< Offset from ICC Base Address: 0x0300 */ +#define MXC_R_ICC_PFMCNT ((uint32_t)0x00000304UL) /**< Offset from ICC Base Address: 0x0304 */ #define MXC_R_ICC_INVALIDATE ((uint32_t)0x00000700UL) /**< Offset from ICC Base Address: 0x0700 */ /**@} end of group icc_registers */ @@ -138,6 +157,53 @@ typedef struct { /**@} end of group ICC_CTRL_Register */ +/** + * @ingroup icc_registers + * @defgroup ICC_WAY ICC_WAY + * @brief Cache Way Control Register. + * @{ + */ +#define MXC_F_ICC_WAY_WAY_POS 0 /**< WAY_WAY Position */ +#define MXC_F_ICC_WAY_WAY ((uint32_t)(0x1UL << MXC_F_ICC_WAY_WAY_POS)) /**< WAY_WAY Mask */ + +/**@} end of group ICC_WAY_Register */ + +/** + * @ingroup icc_registers + * @defgroup ICC_REGCTRL ICC_REGCTRL + * @brief Regional Control Register. + * @{ + */ +#define MXC_F_ICC_REGCTRL_EN_POS 0 /**< REGCTRL_EN Position */ +#define MXC_F_ICC_REGCTRL_EN ((uint32_t)(0xFFUL << MXC_F_ICC_REGCTRL_EN_POS)) /**< REGCTRL_EN Mask */ + +#define MXC_F_ICC_REGCTRL_EXC_POS 8 /**< REGCTRL_EXC Position */ +#define MXC_F_ICC_REGCTRL_EXC ((uint32_t)(0xFFUL << MXC_F_ICC_REGCTRL_EXC_POS)) /**< REGCTRL_EXC Mask */ + +/**@} end of group ICC_REGCTRL_Register */ + +/** + * @ingroup icc_registers + * @defgroup ICC_PFMCTRL ICC_PFMCTRL + * @brief Performance Control Register. + * @{ + */ +#define MXC_F_ICC_PFMCTRL_EN_POS 0 /**< PFMCTRL_EN Position */ +#define MXC_F_ICC_PFMCTRL_EN ((uint32_t)(0x1UL << MXC_F_ICC_PFMCTRL_EN_POS)) /**< PFMCTRL_EN Mask */ + +/**@} end of group ICC_PFMCTRL_Register */ + +/** + * @ingroup icc_registers + * @defgroup ICC_PFMCNT ICC_PFMCNT + * @brief Performance Counter Register. + * @{ + */ +#define MXC_F_ICC_PFMCNT_CNT_POS 0 /**< PFMCNT_CNT Position */ +#define MXC_F_ICC_PFMCNT_CNT ((uint32_t)(0xFFFFFFFFUL << MXC_F_ICC_PFMCNT_CNT_POS)) /**< PFMCNT_CNT Mask */ + +/**@} end of group ICC_PFMCNT_Register */ + /** * @ingroup icc_registers * @defgroup ICC_INVALIDATE ICC_INVALIDATE @@ -149,6 +215,28 @@ typedef struct { /**@} end of group ICC_INVALIDATE_Register */ +/** + * @ingroup icc_registers + * @defgroup ICC_LBOUND ICC_LBOUND + * @brief Regional Low Bound Register. + * @{ + */ +#define MXC_F_ICC_REG_LBOUND_BOUND_POS 0 /**< REG_LBOUND_BOUND Position */ +#define MXC_F_ICC_REG_LBOUND_BOUND ((uint32_t)(0xFFFFFFFFUL << MXC_F_ICC_REG_LBOUND_BOUND_POS)) /**< REG_LBOUND_BOUND Mask */ + +/**@} end of group ICC_REG_LBOUND_Register */ + +/** + * @ingroup icc_registers + * @defgroup ICC_HBOUND ICC_HBOUND + * @brief DMA Channel Status Register. + * @{ + */ +#define MXC_F_ICC_REG_HBOUND_BOUND_POS 0 /**< REG_HBOUND_BOUND Position */ +#define MXC_F_ICC_REG_HBOUND_BOUND ((uint32_t)(0xFFFFFFFFUL << MXC_F_ICC_REG_HBOUND_BOUND_POS)) /**< REG_HBOUND_BOUND Mask */ + +/**@} end of group ICC_REG_HBOUND_Register */ + #ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd index f12f6e39590..45022692810 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd @@ -82,7 +82,7 @@ - + AES AES Keys. @@ -292,7 +292,7 @@ - + CRC CRC Registers. @@ -424,7 +424,7 @@ - + DMA DMA Controller Fully programmable, chaining capable DMA channels. @@ -1136,7 +1136,7 @@ - + FCR Function Control Register. @@ -1154,28 +1154,10 @@ read-write - BTLELDOTX - BTLE LDO TX Trim - 0 - 5 - - - sys - Generated clock from system clock. - 0 - - - dig - Digital clock from a GPIO. - 1 - - - - - BTLELDORX - BTLE LDO RX Trim - 8 - 5 + USBCLKSEL + USB External Core Clock Select. + 16 + 1 sys @@ -1546,9 +1528,9 @@ - ERFOKS - ERFO Kick Start Register. - 0x18 + GP + General Purpose Register. + 0x1C read-write @@ -1559,6 +1541,26 @@ + + MSRTRIM + MSR Trim Register. + 0x20 + read-write + + + R1 + MSR Trim R1. + 0 + 2 + + + R2 + MSR Trim R2. + 2 + 3 + + + FLVFILT Flash Low Voltage Filter Control Register. @@ -1587,7 +1589,7 @@ - + FLC Flash Memory Control. @@ -1905,7 +1907,7 @@ - + GCR Global Control Registers. @@ -2001,8 +2003,80 @@ - CCHK - Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. + SRCC_FLUSH + Data Cache Flush. The system cache (s) will be flushed when this bit is set. + 7 + 1 + + + normal + Normal System Cache Operation + 0 + + + flush + System Cache is flushed + 1 + + + + + SRCC_DIS + Data Cache Disable. The system cache (s) will be completely disabled when this bit is set. + 9 + 1 + + + en + Is enabled. + 0 + + + dis + Is Disabled. + 1 + + + + + CHKRES1 + ROM1 Checksum Result. This bit is only valid when the checksum is done and CCHK1 bit is cleared.. + 11 + 1 + + + complete + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + CCHK1 + Compute ROM1 Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. + 12 + 1 + + + complete + No operation/complete. + 0 + + + start + Start operation. + 1 + + + + + CCHK0 + Compute ROM0 Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. 13 1 @@ -2019,7 +2093,7 @@ - CHKRES + CHKRES0 ROM0 Checksum Result. This bit is only valid when the checksum is done and CCHK0 bit is cleared.. 15 1 @@ -2050,99 +2124,141 @@ 0x04 - DMA0 - DMA0 Reset. + DMA + DMA Reset. 0 1 - - WDT + + WDT0 Watchdog Timer Reset. 1 1 - + GPIO0 - GPIO0 Reset. + GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states. 2 1 - + + GPIO1 + GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states. + 3 + 1 + + TMR0 - Timer0 Reset. + Timer0 Reset. Setting this bit to 1 resets Timer 0 blocks. 5 1 - + TMR1 - Timer1 Reset. + Timer1 Reset. Setting this bit to 1 resets Timer 1 blocks. 6 1 - + TMR2 - Timer2 Reset. + Timer2 Reset. Setting this bit to 1 resets Timer 2 blocks. 7 1 - + TMR3 - Timer3 Reset. + Timer3 Reset. Setting this bit to 1 resets Timer 3 blocks. 8 1 - + TMR4 - Timer4 Reset. + Timer4 Reset. Setting this bit to 1 resets Timer 4 blocks. 9 1 - + TMR5 - Timer5 Reset. + Timer5 Reset. Setting this bit to 1 resets Timer 5 blocks. 10 1 - - UART - UART Reset. + + UART0 + UART0 Reset. Setting this bit to 1 resets all UART 0 blocks. 11 1 - - SPI - SPI0 Reset. + + UART1 + UART1 Reset. Setting this bit to 1 resets all UART 1 blocks. + 12 + 1 + + + SPI0 + SPI0 Reset. Setting this bit to 1 resets all SPI 0 blocks. 13 1 - - I3C - I3C Reset. + + SPI1 + SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks. + 14 + 1 + + + SPI2 + SPI2 Reset. Setting this bit to 1 resets all SPI 2 blocks. + 15 + 1 + + + I2C0 + I2C0 Reset. 16 1 - + RTC Real Time Clock Reset. 17 1 - - BTLE - Bluetooth Reset. - 18 + + TMR6 + Timer6 Reset. Setting this bit to 1 resets Timer 6 blocks. + 20 + 1 + + + TMR7 + Timer7 Reset. Setting this bit to 1 resets Timer 7 blocks. + 21 + 1 + + + SEMA + Semaphore Reset. + 22 1 - + TRNG - TRNG Reset. + TODO(5-2-2023): Remove this bit before release. TRNG Reset. Setting this bit resets the TRNG block. 24 1 - - DMA1 - DMA1 Reset. - 27 + + ADC + Analog to Digital Reset. + 26 + 1 + + + UART2 + UART2 Reset. Setting this bit to 1 resets all UART 2 blocks. + 28 1 @@ -2304,6 +2420,34 @@ + + IPO_DIV + IPO clock divider + 14 + 2 + + + DIV1 + Divide 1. + 0 + + + DIV2 + Divide 2. + 1 + + + DIV4 + Divide 4. + 2 + + + DIV8 + Divide 8. + 3 + + + ERFO_EN 27MHz Crystal Oscillator Enable. @@ -2329,11 +2473,17 @@ 1 - IPO_EN - Internal Primary Oscillator Clock Enable. + ISO_EN + 60MHz High Frequency Internal Reference Clock Enable. 18 1 + + IPO_EN + 96MHz High Frequency Internal Reference Clock Enable. + 19 + 1 + IBRO_EN 8MHz High Frequency Internal Reference Clock Enable. @@ -2371,10 +2521,16 @@ 25 1 + + ISO_RDY + 60MHz ISO Ready. + 26 + 1 + IPO_RDY Internal Primary Oscillator Ready. - 28 + 27 1 @@ -2400,7 +2556,7 @@ MODE Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode. 0 - 4 + 3 active @@ -2437,10 +2593,82 @@ 1 - WUT_WE - Enable wakeup timer as a wakeup source. - 7 + USB_WE + USB Wake Up Enable. This bit enables USB activity as wakeup source. + 6 + 1 + + + ERFO_PD + Radio Frequency oscilator Crystal Power Down. This bit selects the power state in DEEPSLEEP mode. + 12 1 + + + active + Mode is Active. + 0 + + + deepsleep + Powered down in DEEPSLEEP. + 1 + + + + + ISO_PD + Internal Secondary Oscilator Power Down. This bit selects the power state in DEEPSLEEP mode. + 15 + 1 + + + active + Mode is Active. + 0 + + + deepsleep + Powered down in DEEPSLEEP. + 1 + + + + + IPO_PD + Internal Primary Oscilatory power down. This bit selects the power state in DEEPSLEEP mode. + 16 + 1 + + + active + Mode is Active. + 0 + + + deepsleep + Powered down in DEEPSLEEP. + 1 + + + + + IBRO_PD + Internal Baud Rate Oscillator power down. This bit selects the power state in DEEPSLEEP mode. + 17 + 1 + + + active + Mode is Active. + 0 + + + deepsleep + Powered down in DEEPSLEEP. + 1 + + ERFO_BP @@ -2470,23 +2698,51 @@ ADCFRQ - TODO(4-29-2024): Remove register? + ADC clock Frequency. These bits define the ADC clock frequency. FADC = FPCLK / (ADCFRQ). 10 4 - - - - PCLKDIS0 - Peripheral Clock Disable. - 0x24 - - GPIO0 - GPIO0 Clock Disable. - 0 - 1 - + AONCLKDIV + Always-ON (AON) domain Clock Divider. These bits define the AON domain clock divider. + 14 + 2 + + + DIV4 + PCLK divide by 4. + 0 + + + DIV8 + PCLK divide by 8. + 1 + + + DIV16 + PCLK divide by 16. + 2 + + + DIV32 + PCLK divide by 32. + 3 + + + + + + + PCLKDIS0 + Peripheral Clock Disable. + 0x24 + + + GPIO0 + GPIO0 Clock Disable. + 0 + 1 + en enable it. @@ -2500,26 +2756,50 @@ - DMA0 - DMA0 Disable. + GPIO1 + GPIO1 Disable. + 1 + 1 + + + DMA + DMA Disable. 5 1 - SPI - SPI Disable. + SPI0 + SPI 0 Disable. 6 1 - UART - UART Disable. + SPI1 + SPI 1 Disable. + 7 + 1 + + + SPI2 + SPI 2 Disable. + 8 + 1 + + + UART0 + UART 0 Disable. 9 1 - I3C - I3C Disable. + UART1 + UART 1 Disable. + 10 + 1 + + + I2C0 + I2C 0 Disable. 13 1 @@ -2559,6 +2839,36 @@ 20 1 + + ADC + ADC Disable. + 23 + 1 + + + TMR6 + Timer 6 Disable. + 24 + 1 + + + TMR7 + Timer 7 Disable. + 25 + 1 + + + I2C1 + I2C 1 Disable. + 28 + 1 + + + PT + PT Clock Disable. + 29 + 1 + @@ -2572,6 +2882,138 @@ 0 3 + + SRAM_WS + SRAM Wait State Enable + 4 + 1 + + + ROM1_WS + ROM1 Wait State Enable + 7 + 1 + + + RAM0_WS + System RAM 0 Wait State Enable + 8 + 1 + + + RAM1_WS + System RAM 1 Wait State Enable + 9 + 1 + + + RAM2_WS + System RAM 2 Wait State Enable + 10 + 1 + + + RAM3_WS + System RAM 3 Wait State Enable + 11 + 1 + + + RAM4_WS + System RAM 4 Wait State Enable + 12 + 1 + + + RAM5_WS + System RAM 5 Wait State Enable + 13 + 1 + + + RAM0LS_EN + System RAM 0 Light Sleep Mode. + 16 + 1 + + + active + RAM is active. + 0 + + + light_sleep + RAM is in Light Sleep mode. + 1 + + + + + RAM1LS_EN + System RAM 1 Light Sleep Mode. + 17 + 1 + + + RAM2LS_EN + System RAM 2 Light Sleep Mode. + 18 + 1 + + + RAM3LS_EN + System RAM 3 Light Sleep Mode. + 19 + 1 + + + RAM4LS_EN + System RAM 4 Light Sleep Mode. + 20 + 1 + + + RAM5LS_EN + System RAM 5 Light Sleep Mode. + 21 + 1 + + + ICCLS_EN + ICache RAM Light Sleep Mode. + 24 + 1 + + + ICCXIPLS_EN + ICACHE-XIP RAM Light Sleep Mode. + 25 + 1 + + + SRCCLS_EN + SysCache RAM Light Sleep Mode. + 26 + 1 + + + USBLS_EN + USB FIFO Light Sleep Mode. + 28 + 1 + + + ROM0LS_EN + ROM0 Light Sleep Mode. + 29 + 1 + + + ROM1LS_EN + ROM1 Light Sleep Mode. + 30 + 1 + @@ -2580,7 +3022,7 @@ 0x2C - SRAM0 + RAM0 System RAM Block 0. 0 1 @@ -2597,36 +3039,72 @@ - - SRAM1 + + RAM1 System RAM Block 1. 1 1 - - SRAM2 + + RAM2 System RAM Block 2. 2 1 - - SRAM3 + + RAM3 System RAM Block 3. 3 1 - - SRAM4 + + RAM4 System RAM Block 4. 4 1 - - ICC - Internal Cache. + + RAM5 + System RAM Block 5. 5 1 + + RAM6 + System RAM Block 6. + 6 + 1 + + + ICC + Instruction Cache. + 8 + 1 + + + ICCXIP + Instruction Cache XIP Data and Tag Ram zeroizatoin. + 9 + 1 + + + SRCCDATA + System Cache Data Ram Zeroization. + 10 + 1 + + + SRCCTAG + System Cache Tag Zeroization. + 11 + 1 + + + USBFIFO + USB FIFO Zeroization. + 13 + 1 + @@ -2639,163 +3117,549 @@ ARM ICE Lock Status. 0 1 - - - unlocked - ICE is unlocked. - 0 - - - locked - ICE is locked. - 1 - - + + + unlocked + ICE is unlocked. + 0 + + + locked + ICE is locked. + 1 + + + + + CODEAUTHERR + Code Authentication Error Flag. This bit indicates a code authentication error has occured in XiP interface. + 1 + 1 + + + norm + Normal Operating Condition. + 0 + + + code + Code Integrity Error. + 1 + + + + + DATAAUTHERR + Data Authentication Error Flag. This bit indicates a data authentication error has occured in XiP interface. + 2 + 1 + + + norm + Normal Operating Condition. + 0 + + + code + Code Integrity Error. + 1 + + + + + SCMEMF + System Cache Memory Fault Flag. This bit indicates a memory fault has occured in the System Cache while receiving data from the Hyperbus Interface. + 5 + 1 + + + norm + Normal Operating Condition. + 0 + + + memory + Memory Fault. + 1 + + + + + + + RST1 + Reset 1. + 0x44 + + + I2C1 + I2C1 Reset. + 0 + 1 + + + PT + PT Reset. + 1 + 1 + + + OWIRE + OWIRE Reset. + 7 + 1 + + + WDT1 + WDT1 Reset. + 8 + 1 + + + CRC + CRC Reset. + 9 + 1 + + + AES + AES Reset. + 10 + 1 + + + I2S + I2S Reset. + 13 + 1 + + + AC + AC Reset. + 14 + 1 + + + SEMA + Semaphore Reset. + 16 + 1 + + + I2C2 + I2C2 Reset. + 17 + 1 + + + UART3 + UART3 Reset. + 18 + 1 + + + UART4 + UART4 Reset. + 19 + 1 + + + UART5 + UART5 Reset. + 20 + 1 + + + + + PCLKDIS1 + Peripheral Clock Disable. + 0x48 + + + BTLE + Bluetooth Clock Disable. + 0 + 1 + + + en + Enable. + 0 + + + dis + Disable. + 1 + + + + + UART2 + UART2 Disable. + 1 + 1 + + + en + Enable. + 0 + + + dis + Disable. + 1 + + + + + TRNG + TRNG Disable. + 2 + 1 + + + WDT0 + WDT0 Clock Disable + 4 + 1 + + + WDT1 + WDT1 Clock Disable + 5 + 1 + + + SRCC + System Cache Clock Disable. + 7 + 1 + + + SEMA + Semaphore Clock Disable. + 9 + 1 + + + OWIRE + One-Wire Clock Disable. + 13 + 1 + + + CRC + CRC Clock Disable. + 14 + 1 + + + AES + AES Clock Disable. + 15 + 1 + + + I2S + I2S Clock Disable. + 16 + 1 + + + I2C2 + I2C2 Clock Disable + 21 + 1 + + + UART3 + UART3 Clock Disable + 22 + 1 + + + UART4 + UART4 Clock Disable + 23 + 1 + + + UART5 + UART5 Clock Disable + 24 + 1 + + + + + EVENTEN + Event Enable Register. + 0x4C + + + DMA + Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode. + 0 + 1 + + + RX + Enable RXEV pin event. When this bit is set, a logic high of GPIO0[24] will cause an RXEV event to wake the CPU from WFE sleep mode. + 1 + 1 + + + TX + Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO[25]. + 2 + 1 + + + + + REVISION + Revision Register. + 0x50 + read-only + + + REVISION + Manufacturer Chip Revision. + 0 + 16 + + + + + SYSINTEN + System Status Interrupt Enable Register. + 0x54 + + + ICEUNLOCK + ARM ICE Unlock Interrupt Enable. + 0 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + CIE + Code Integrity Error Interrupt Enable. + 1 + 1 + + + SCMF + System Cache Memory Fault Interrupt Enable. + 5 + 1 + + + + + IPOCNT + IPO Warmup Count Register. + 0x58 + + + WMUPCNT + TBD + 0 + 10 + + + + + ECCERR + ECC Error Register + 0x64 + + + RAM0 + ECC System RAM0 Error Flag. Write 1 to clear. + 0 + 1 + + + RAM1 + ECC System RAM1 Error Flag. Write 1 to clear. + 1 + 1 + + + RAM2 + ECC System RAM2 Error Flag. Write 1 to clear. + 2 + 1 + + + RAM3 + ECC System RAM3 Error Flag. Write 1 to clear. + 3 + 1 + + + RAM4 + ECC System RAM4 Error Flag. Write 1 to clear. + 4 + 1 + + + RAM5 + ECC System RAM5 Error Flag. Write 1 to clear. + 5 + 1 + + + ICC + ECC Icache0 Error Flag. Write 1 to clear. + 8 + 1 + + + ICCXIP + ECC SFCC Instruction Cache Error Flag. Write 1 to clear. + 10 + 1 + + + FLASH + ECC Flash0 Error Flag. Write 1 to clear. + 11 + 1 - RST1 - Reset 1. - 0x44 + ECCCED + ECC Not Double Error Detect Register + 0x68 - CRC - CRC Reset. - 9 + RAM0 + ECC System RAM0 Error Flag. Write 1 to clear. + 0 1 - - AES - AES Reset. - 10 + + RAM1 + ECC System RAM1 Not Double Error Detect. Write 1 to clear. + 1 1 - - - - PCLKDIS1 - Peripheral Clock Disable. - 0x48 - - TRNG - TRNG Disable. + RAM2 + ECC System RAM2 Not Double Error Detect. Write 1 to clear. 2 1 - - CRC - CRC Clock Disable. - 14 + + RAM3 + ECC System RAM3 Not Double Error Detect. Write 1 to clear. + 3 1 - - AES - AES Clock Disable. - 15 + + RAM4 + ECC System RAM4 Not Double Error Detect. Write 1 to clear. + 4 1 - - SPI - SPI Clock Disable. - 16 + + RAM5 + ECC System RAM5 Not Double Error Detect. Write 1 to clear. + 5 1 - - WDT - Watchdog Clock Disable - 27 + + ICC + ECC Icache0 Not Double Error Detect. Write 1 to clear. + 8 + 1 + + + ICCXIP + ECC IcacheXIP Not Double Error Detect. Write 1 to clear. + 10 + 1 + + + FLASH + ECC Flash0 Not Double Error Detect. Write 1 to clear. + 11 1 - EVENTEN - Event Enable Register. - 0x4C + ECCINTEN + ECC Interrupt Enable Register + 0x6C - DMA0 - Enable DMA0 event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode. + RAM0 + ECC System RAM0 Interrupt Enable. 0 1 - DMA1 - Enable DMA1 event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode. + RAM1 + ECC System RAM1 Interrupt Enable. 1 1 - TX - Enable TXEV pin event. When this bit is set, TXEV event from the CPU is output to GPIO[25]. + RAM2 + ECC System RAM2 Interrupt Enable. 2 1 - - - - REVISION - Revision Register. - 0x50 - read-only - - REVISION - Manufacturer Chip Revision. - 0 - 16 + RAM3 + ECC System RAM3 Interrupt Enable. + 3 + 1 - - - - SYSINTEN - System Status Interrupt Enable Register. - 0x54 - - ICEUNLOCK - ARM ICE Unlock Interrupt Enable. - 0 + RAM4 + ECC System RAM4 Interrupt Enable. + 4 1 - - - dis - disabled. - 0 - - - en - enabled. - 1 - - - - - - ECCERR - ECC Error Register - 0x64 - - FLASH - ECC Flash Error Flag. Write 1 to clear. - 0 + RAM5 + ECC System RAM5 Interrupt Enable. + 5 + 1 + + + ICC + ECC Icache0 Interrupt Enable. + 8 + 1 + + + ICCXIP + ECC IcacheXIP Interrupt Enable. + 10 1 - - - - ECCINTEN - ECC Interrupt Enable Register - 0x6C - FLASH - ECC Flash Interrupt Enable. - 0 + ECC Flash0 Interrupt Enable. + 11 1 @@ -3052,7 +3916,7 @@ - + GPIO0 Individual I/O for each GPIO @@ -3761,9 +4625,9 @@ - + - ICC0 + ICC Instruction Cache Controller Registers 0x4002A000 @@ -3863,6 +4727,116 @@ + + WAY + Cache Way Control Register. + 0x0200 + + + WAY + Number of cache way, default is always 2. Allowed values are 1,2,4. + 0 + 1 + + + 1 + 1 + 0 + + + 2 + 2 + 1 + + + 4 + 4 + 2 + + + + + + + REGCTRL + Regional Control Register. + 0x0204 + + + EN + Enable the regional high andlow bound compare, cache the data only if the TAG content between the high and low bound. + 0 + 8 + + + EXC + Cache the data only if the TAG content is excluded in the high and low bound. + 8 + 8 + + + + + 15 + 0x20 + REGION[%s] + Regional Low and High Bound Registers. + icc_reg + 0x0208 + read-write + + LBOUND + Regional Low Bound Register. + 0x0000 + + + BOUND + Low Bound. + 0 + 32 + + + + + HBOUND + DMA Channel Status Register. + 0x004 + + + BOUND + High Bound. + 0 + 32 + + + + + + PFMCTRL + Performance Control Register. + 0x0300 + + + EN + Enable performance counter. Clear to 0 when AHB access counter reach 0. + 0 + 1 + + + + + PFMCNT + Performance Counter Register. + 0x0304 + + + CNT + Write the total AHB access counter. Read the current performance hit count. + 0 + 32 + + + INVALIDATE Invalidate All Registers. @@ -3879,7 +4853,7 @@ - + MCR Misc Control. @@ -4286,7 +5260,7 @@ - + PWRSEQ Power Sequencer / Low Power Control Register. @@ -7448,7 +8422,7 @@ - + RTC Real Time Clock and Alarm. @@ -7855,7 +8829,7 @@ - + SEMA The Semaphore peripheral allows multiple cores in a system to cooperate when accessing shred resources. @@ -7997,11 +8971,7 @@ - + SIMO Single Inductor Multiple Output Switching Converter @@ -8408,7 +9378,7 @@ - + SIR System Initialization Registers. @@ -8505,7 +9475,7 @@ FSTAT - Function Status register. + funcstat register. 0x100 read-only @@ -8571,11 +9541,43 @@ 0 1 + + TRNG + TRNG Function. + 2 + 1 + + + no + 0 + + + yes + 1 + + + + + AES + AES Block. + 3 + 1 + + + no + 0 + + + yes + 1 + + + - + SPC Secure Privilege Controller. @@ -8865,7 +9867,7 @@ - + SPI SPI peripheral. @@ -8963,30 +9965,30 @@ dis - SPI is Slave mode. + SPI is Target mode. 0 en - SPI is Master mode. + SPI is Controller mode. 1 TS_IO - Target Select 0, IO direction, to support Multi-Controller mode, Target Select 0 can be input in Controller mode. This bit has no effect in target mode. + Target Select 0, IO direction, to support Multi-Controller mode,Target Select 0 can be input in Controller mode. This bit has no effect in target mode. 4 1 output - Slave select 0 is output. + Target select 0 is output. 0 input - Slave Select 0 is input, only valid if MMEN=1. + Target Select 0 is input, only valid if MMEN=1. 1 @@ -8999,53 +10001,53 @@ start - Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction. + Controller Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Controller halts, if a transaction completes, and the TX FIFO is not empty, the Controller initiates another transaction. 1 TS_CTRL - Target Select Control. Used in Controller mode to control the behavior of the Target Select signal at the end of a transaction. + Start Select Control. Used in Controller mode to control the behavior of the Target Select signal at the end of a transaction. 8 1 DEASSERT - SPI De-asserts Slave Select at the end of a transaction. + SPI De-asserts Target Select at the end of a transaction. 0 - ASSERT - SPI leaves Slave Select asserted at the end of a transaction. + ATSERT + SPI leaves Target Select asserted at the end of a transaction. 1 TS_ACTIVE - Target Select, when in Master mode selects which Target devices are selected. More than one Target device can be selected. + Target Select, when in Controller mode selects which Target devices are selected. More than one Target device can be selected. 16 4 - SS0 - SS0 is selected. + TS0 + TS0 is selected. 0x1 - SS1 - SS1 is selected. + TS1 + TS1 is selected. 0x2 - SS2 - SS2 is selected. + TS2 + TS2 is selected. 0x4 - SS3 - SS3 is selected. + TS3 + TS3 is selected. 0x8 @@ -9268,23 +10270,23 @@ 4 - SS0_high - SS0 active high. + TS0_high + TS0 active high. 0x1 - SS1_high - SS1 active high. + TS1_high + TS1 active high. 0x2 - SS2_high - SS2 active high. + TS2_high + TS2 active high. 0x4 - SS3_high - SS3 active high. + TS3_high + TS3 active high. 0x8 @@ -9299,33 +10301,33 @@ PRE - Slave Select Pre delay 1. + Target Select Pre delay 1. 0 8 256 - 256 system clocks between SS active and first serial clock edge. + 256 system clocks between TS active and first serial clock edge. 0 POST - Slave Select Post delay 2. + Target Select Post delay 2. 8 8 256 - 256 system clocks between last serial clock edge and SS inactive. + 256 system clocks between last serial clock edge and TS inactive. 0 INACT - Slave Select Inactive delay. + Target Select Inactive delay. 16 8 @@ -9598,7 +10600,7 @@ FAULT - Multi-Master Mode Fault. + Multi-Controller Mode Fault. 8 1 @@ -9611,7 +10613,7 @@ ABORT - Slave Abort Detected. + Target Abort Detected. 9 1 @@ -9624,7 +10626,7 @@ CTRLR_DONE - Controller Done, set when SPI Master has completed any transactions. + Controller Done, set when SPI Controller has completed any transactions. 11 1 @@ -9805,7 +10807,7 @@ FAULT - Multi-Master Mode Fault interrupt enable. + Multi-Controller Mode Fault interrupt enable. 8 1 @@ -9823,7 +10825,7 @@ ABORT - Slave Abort Detected interrupt enable. + Target Abort Detected interrupt enable. 9 1 @@ -10079,7 +11081,7 @@ BUSY - SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. + SPI active status. In Controller mode, set when transaction starts, cleared when last bit of last character is acted upon and Target Select de-assertion would occur. In Target mode, set when Target Select is asserted, cleared when Target Select is de-asserted. Not used in Timer mode. 0 1 @@ -10099,7 +11101,7 @@ - + TMR Low-Power Configurable Timer @@ -10756,7 +11758,7 @@ - + TMR1 Low-Power Configurable Timer 1 @@ -10767,7 +11769,7 @@ 6 - + TMR2 Low-Power Configurable Timer 2 @@ -10778,7 +11780,7 @@ 7 - + TMR3 Low-Power Configurable Timer 3 @@ -10789,7 +11791,7 @@ 8 - + TMR4 Low-Power Configurable Timer 4 @@ -10800,7 +11802,7 @@ 9 - + TMR5 Low-Power Configurable Timer 5 @@ -10811,7 +11813,7 @@ 10 - + TRIMSIR Trim System Initilazation Registers @@ -10989,7 +11991,7 @@ - + TRNG Random Number Generator. @@ -11335,7 +12337,7 @@ - + UART UART Low Power Registers @@ -11814,7 +12816,7 @@ - + WDT Windowed Watchdog Timer @@ -12405,7 +13407,7 @@ - + WUT 32-bit reloadable timer that can be used for timing and wakeup. @@ -12450,13 +13452,13 @@ - INTR + INTFL Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt. 0x0C oneToClear - IF_CLR + CLR Clear Interrupt. 0 1 @@ -12663,6 +13665,6 @@ - + - + \ No newline at end of file diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spi_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spi_regs.h index 076ccdcd6e4..e965112191c 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spi_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spi_regs.h @@ -170,14 +170,14 @@ typedef struct { #define MXC_F_SPI_CTRL0_TS_ACTIVE_POS 16 /**< CTRL0_TS_ACTIVE Position */ #define MXC_F_SPI_CTRL0_TS_ACTIVE ((uint32_t)(0xFUL << MXC_F_SPI_CTRL0_TS_ACTIVE_POS)) /**< CTRL0_TS_ACTIVE Mask */ -#define MXC_V_SPI_CTRL0_TS_ACTIVE_SS0 ((uint32_t)0x1UL) /**< CTRL0_TS_ACTIVE_SS0 Value */ -#define MXC_S_SPI_CTRL0_TS_ACTIVE_SS0 (MXC_V_SPI_CTRL0_TS_ACTIVE_SS0 << MXC_F_SPI_CTRL0_TS_ACTIVE_POS) /**< CTRL0_TS_ACTIVE_SS0 Setting */ -#define MXC_V_SPI_CTRL0_TS_ACTIVE_SS1 ((uint32_t)0x2UL) /**< CTRL0_TS_ACTIVE_SS1 Value */ -#define MXC_S_SPI_CTRL0_TS_ACTIVE_SS1 (MXC_V_SPI_CTRL0_TS_ACTIVE_SS1 << MXC_F_SPI_CTRL0_TS_ACTIVE_POS) /**< CTRL0_TS_ACTIVE_SS1 Setting */ -#define MXC_V_SPI_CTRL0_TS_ACTIVE_SS2 ((uint32_t)0x4UL) /**< CTRL0_TS_ACTIVE_SS2 Value */ -#define MXC_S_SPI_CTRL0_TS_ACTIVE_SS2 (MXC_V_SPI_CTRL0_TS_ACTIVE_SS2 << MXC_F_SPI_CTRL0_TS_ACTIVE_POS) /**< CTRL0_TS_ACTIVE_SS2 Setting */ -#define MXC_V_SPI_CTRL0_TS_ACTIVE_SS3 ((uint32_t)0x8UL) /**< CTRL0_TS_ACTIVE_SS3 Value */ -#define MXC_S_SPI_CTRL0_TS_ACTIVE_SS3 (MXC_V_SPI_CTRL0_TS_ACTIVE_SS3 << MXC_F_SPI_CTRL0_TS_ACTIVE_POS) /**< CTRL0_TS_ACTIVE_SS3 Setting */ +#define MXC_V_SPI_CTRL0_TS_ACTIVE_TS0 ((uint32_t)0x1UL) /**< CTRL0_TS_ACTIVE_TS0 Value */ +#define MXC_S_SPI_CTRL0_TS_ACTIVE_TS0 (MXC_V_SPI_CTRL0_TS_ACTIVE_TS0 << MXC_F_SPI_CTRL0_TS_ACTIVE_POS) /**< CTRL0_TS_ACTIVE_TS0 Setting */ +#define MXC_V_SPI_CTRL0_TS_ACTIVE_TS1 ((uint32_t)0x2UL) /**< CTRL0_TS_ACTIVE_TS1 Value */ +#define MXC_S_SPI_CTRL0_TS_ACTIVE_TS1 (MXC_V_SPI_CTRL0_TS_ACTIVE_TS1 << MXC_F_SPI_CTRL0_TS_ACTIVE_POS) /**< CTRL0_TS_ACTIVE_TS1 Setting */ +#define MXC_V_SPI_CTRL0_TS_ACTIVE_TS2 ((uint32_t)0x4UL) /**< CTRL0_TS_ACTIVE_TS2 Value */ +#define MXC_S_SPI_CTRL0_TS_ACTIVE_TS2 (MXC_V_SPI_CTRL0_TS_ACTIVE_TS2 << MXC_F_SPI_CTRL0_TS_ACTIVE_POS) /**< CTRL0_TS_ACTIVE_TS2 Setting */ +#define MXC_V_SPI_CTRL0_TS_ACTIVE_TS3 ((uint32_t)0x8UL) /**< CTRL0_TS_ACTIVE_TS3 Value */ +#define MXC_S_SPI_CTRL0_TS_ACTIVE_TS3 (MXC_V_SPI_CTRL0_TS_ACTIVE_TS3 << MXC_F_SPI_CTRL0_TS_ACTIVE_POS) /**< CTRL0_TS_ACTIVE_TS3 Setting */ /**@} end of group SPI_CTRL0_Register */ @@ -259,14 +259,14 @@ typedef struct { #define MXC_F_SPI_CTRL2_TSPOL_POS 16 /**< CTRL2_TSPOL Position */ #define MXC_F_SPI_CTRL2_TSPOL ((uint32_t)(0xFUL << MXC_F_SPI_CTRL2_TSPOL_POS)) /**< CTRL2_TSPOL Mask */ -#define MXC_V_SPI_CTRL2_TSPOL_SS0_HIGH ((uint32_t)0x1UL) /**< CTRL2_TSPOL_SS0_HIGH Value */ -#define MXC_S_SPI_CTRL2_TSPOL_SS0_HIGH (MXC_V_SPI_CTRL2_TSPOL_SS0_HIGH << MXC_F_SPI_CTRL2_TSPOL_POS) /**< CTRL2_TSPOL_SS0_HIGH Setting */ -#define MXC_V_SPI_CTRL2_TSPOL_SS1_HIGH ((uint32_t)0x2UL) /**< CTRL2_TSPOL_SS1_HIGH Value */ -#define MXC_S_SPI_CTRL2_TSPOL_SS1_HIGH (MXC_V_SPI_CTRL2_TSPOL_SS1_HIGH << MXC_F_SPI_CTRL2_TSPOL_POS) /**< CTRL2_TSPOL_SS1_HIGH Setting */ -#define MXC_V_SPI_CTRL2_TSPOL_SS2_HIGH ((uint32_t)0x4UL) /**< CTRL2_TSPOL_SS2_HIGH Value */ -#define MXC_S_SPI_CTRL2_TSPOL_SS2_HIGH (MXC_V_SPI_CTRL2_TSPOL_SS2_HIGH << MXC_F_SPI_CTRL2_TSPOL_POS) /**< CTRL2_TSPOL_SS2_HIGH Setting */ -#define MXC_V_SPI_CTRL2_TSPOL_SS3_HIGH ((uint32_t)0x8UL) /**< CTRL2_TSPOL_SS3_HIGH Value */ -#define MXC_S_SPI_CTRL2_TSPOL_SS3_HIGH (MXC_V_SPI_CTRL2_TSPOL_SS3_HIGH << MXC_F_SPI_CTRL2_TSPOL_POS) /**< CTRL2_TSPOL_SS3_HIGH Setting */ +#define MXC_V_SPI_CTRL2_TSPOL_TS0_HIGH ((uint32_t)0x1UL) /**< CTRL2_TSPOL_TS0_HIGH Value */ +#define MXC_S_SPI_CTRL2_TSPOL_TS0_HIGH (MXC_V_SPI_CTRL2_TSPOL_TS0_HIGH << MXC_F_SPI_CTRL2_TSPOL_POS) /**< CTRL2_TSPOL_TS0_HIGH Setting */ +#define MXC_V_SPI_CTRL2_TSPOL_TS1_HIGH ((uint32_t)0x2UL) /**< CTRL2_TSPOL_TS1_HIGH Value */ +#define MXC_S_SPI_CTRL2_TSPOL_TS1_HIGH (MXC_V_SPI_CTRL2_TSPOL_TS1_HIGH << MXC_F_SPI_CTRL2_TSPOL_POS) /**< CTRL2_TSPOL_TS1_HIGH Setting */ +#define MXC_V_SPI_CTRL2_TSPOL_TS2_HIGH ((uint32_t)0x4UL) /**< CTRL2_TSPOL_TS2_HIGH Value */ +#define MXC_S_SPI_CTRL2_TSPOL_TS2_HIGH (MXC_V_SPI_CTRL2_TSPOL_TS2_HIGH << MXC_F_SPI_CTRL2_TSPOL_POS) /**< CTRL2_TSPOL_TS2_HIGH Setting */ +#define MXC_V_SPI_CTRL2_TSPOL_TS3_HIGH ((uint32_t)0x8UL) /**< CTRL2_TSPOL_TS3_HIGH Value */ +#define MXC_S_SPI_CTRL2_TSPOL_TS3_HIGH (MXC_V_SPI_CTRL2_TSPOL_TS3_HIGH << MXC_F_SPI_CTRL2_TSPOL_POS) /**< CTRL2_TSPOL_TS3_HIGH Setting */ /**@} end of group SPI_CTRL2_Register */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/wut_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/wut_regs.h index 6f7a078ee0f..37f3861f463 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/wut_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/wut_regs.h @@ -75,7 +75,7 @@ typedef struct { __IO uint32_t cnt; /**< \b 0x00: WUT CNT Register */ __IO uint32_t cmp; /**< \b 0x04: WUT CMP Register */ __R uint32_t rsv_0x8; - __IO uint32_t intr; /**< \b 0x0C: WUT INTR Register */ + __IO uint32_t intfl; /**< \b 0x0C: WUT INTFL Register */ __IO uint32_t ctrl; /**< \b 0x10: WUT CTRL Register */ __IO uint32_t nolcmp; /**< \b 0x14: WUT NOLCMP Register */ __IO uint32_t preset; /**< \b 0x18: WUT PRESET Register */ @@ -92,7 +92,7 @@ typedef struct { */ #define MXC_R_WUT_CNT ((uint32_t)0x00000000UL) /**< Offset from WUT Base Address: 0x0000 */ #define MXC_R_WUT_CMP ((uint32_t)0x00000004UL) /**< Offset from WUT Base Address: 0x0004 */ -#define MXC_R_WUT_INTR ((uint32_t)0x0000000CUL) /**< Offset from WUT Base Address: 0x000C */ +#define MXC_R_WUT_INTFL ((uint32_t)0x0000000CUL) /**< Offset from WUT Base Address: 0x000C */ #define MXC_R_WUT_CTRL ((uint32_t)0x00000010UL) /**< Offset from WUT Base Address: 0x0010 */ #define MXC_R_WUT_NOLCMP ((uint32_t)0x00000014UL) /**< Offset from WUT Base Address: 0x0014 */ #define MXC_R_WUT_PRESET ((uint32_t)0x00000018UL) /**< Offset from WUT Base Address: 0x0018 */ @@ -125,15 +125,15 @@ typedef struct { /** * @ingroup wut_registers - * @defgroup WUT_INTR WUT_INTR + * @defgroup WUT_INTFL WUT_INTFL * @brief Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the * associated interrupt. * @{ */ -#define MXC_F_WUT_INTR_IF_CLR_POS 0 /**< INTR_IF_CLR Position */ -#define MXC_F_WUT_INTR_IF_CLR ((uint32_t)(0x1UL << MXC_F_WUT_INTR_IF_CLR_POS)) /**< INTR_IF_CLR Mask */ +#define MXC_F_WUT_INTFL_CLR_POS 0 /**< INTFL_CLR Position */ +#define MXC_F_WUT_INTFL_CLR ((uint32_t)(0x1UL << MXC_F_WUT_INTFL_CLR_POS)) /**< INTFL_CLR Mask */ -/**@} end of group WUT_INTR_Register */ +/**@} end of group WUT_INTFL_Register */ /** * @ingroup wut_registers diff --git a/Libraries/PeriphDrivers/Source/ADC/adc_reva_me30.svd b/Libraries/PeriphDrivers/Source/ADC/adc_reva_me30.svd deleted file mode 100644 index 50b90f0ff63..00000000000 --- a/Libraries/PeriphDrivers/Source/ADC/adc_reva_me30.svd +++ /dev/null @@ -1,362 +0,0 @@ - - - - ADC - 10-bit Analog to Digital Converter - - 0x40034000 - 32 - read-write - - 0 - 0x1000 - registers - - - ADC - ADC IRQ - 20 - - - - - CTRL - ADC Control - 0x0000 - read-write - - - START - Start ADC Conversion - [0:0] - read-write - - - PWR - ADC Power Up - [1:1] - read-write - - - REBUF_PWR - ADC Reference Buffer Power Up - [3:3] - read-write - - - CHGPUMP_PWR - ADC Charge Pump Power Up - [4:4] - read-write - - - REF_SCALE - ADC Reference Scale - [8:8] - read-write - - - SCALE - ADC Scale - [9:9] - read-write - - - CLK_EN - ADC Clock Enable - [11:11] - read-write - - - CH_SEL - ADC Channel Select - [16:12] - read-write - - - AIN0 - 0 - - - AIN1 - 1 - - - AIN2 - 2 - - - AIN3 - 3 - - - AIN4 - 4 - - - AIN5 - 5 - - - AIN6 - 6 - - - AIN7 - 7 - - - VcoreA - 8 - - - VcoreB - 9 - - - Vrxout - 10 - - - Vtxout - 11 - - - VddA - 12 - - - VddB - VddB/4 - 13 - - - Vddio - Vddio/4 - 14 - - - Vddioh - Vddioh/4 - 15 - - - VregI - VregI/4 - 16 - - - - - DIVSEL - Scales the external inputs, all inputs are scaled the same - [18:17] - read-write - - - DIV1 - 0 - - - DIV2 - 1 - - - DIV3 - 2 - - - DIV4 - 3 - - - - - DATA_ALIGN - ADC Data Alignment Select - [20:20] - read-write - - - - - - STATUS - ADC Status - 0x0004 - read-write - - - ACTIVE - ADC Conversion In Progress - [0:0] - read-only - - - AFE_PWR_UP_ACTIVE - AFE Power Up Delay Active - [2:2] - read-only - - - OVERFLOW - ADC Overflow - [3:3] - read-only - - - - - - DATA - ADC Output Data - 0x0008 - read-write - - - DATA - ADC Converted Sample Data Output - [15:0] - read-only - - - - - - INTR - ADC Interrupt Control Register - 0x000C - read-write - - - DONE_IE - ADC Done Interrupt Enable - [0:0] - read-write - - - REF_READY_IE - ADC Reference Ready Interrupt Enable - [1:1] - read-write - - - HI_LIMIT_IE - ADC Hi Limit Monitor Interrupt Enable - [2:2] - read-write - - - LO_LIMIT_IE - ADC Lo Limit Monitor Interrupt Enable - [3:3] - read-write - - - OVERFLOW_IE - ADC Overflow Interrupt Enable - [4:4] - read-write - - - DONE_IF - ADC Done Interrupt Flag - [16:16] - read-write - oneToClear - - - REF_READY_IF - ADC Reference Ready Interrupt Flag - [17:17] - read-write - oneToClear - - - HI_LIMIT_IF - ADC Hi Limit Monitor Interrupt Flag - [18:18] - read-write - oneToClear - - - LO_LIMIT_IF - ADC Lo Limit Monitor Interrupt Flag - [19:19] - read-write - oneToClear - - - OVERFLOW_IF - ADC Overflow Interrupt Flag - [20:20] - read-write - oneToClear - - - PENDING - ADC Interrupt Pending Status - [22:22] - read-only - - - - - - 4 - 4 - LIMIT[%s] - ADC Limit - 0x0010 - read-write - - - CH_LO_LIMIT - Low Limit Threshold - [9:0] - read-write - - - CH_HI_LIMIT - High Limit Threshold - [21:12] - read-write - - - CH_SEL - ADC Channel Select - [27:24] - read-write - - - CH_LO_LIMIT_EN - Low Limit Monitoring Enable - [28:28] - read-write - - - CH_HI_LIMIT_EN - High Limit Monitoring Enable - [29:29] - read-write - - - - - DECCNT - ADC Decimation Count. - 0x0020 - read-write - - - DELAY - Delay. - [31:0] - read-write - - - - - - - \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/ICC/icc_reva_me30.svd b/Libraries/PeriphDrivers/Source/ICC/icc_reva_me30.svd new file mode 100644 index 00000000000..eba1471e67f --- /dev/null +++ b/Libraries/PeriphDrivers/Source/ICC/icc_reva_me30.svd @@ -0,0 +1,233 @@ + + + + ICC + Instruction Cache Controller Registers + 0x4002A000 + + 0x00 + 0x800 + registers + + + + INFO + Cache ID Register. + 0x0000 + read-only + + + RELNUM + Release Number. Identifies the RTL release version. + 0 + 6 + + + PARTNUM + Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter. + 6 + 4 + + + ID + Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter. + 10 + 6 + + + + + SZ + Memory Configuration Register. + 0x0004 + read-only + 0x00080008 + + + CCH + Cache Size. Indicates total size in Kbytes of cache. + 0 + 16 + + + MEM + Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller. + 16 + 16 + + + + + CTRL + Cache Control and Status Register. + 0x0100 + + + EN + Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated. + 0 + 1 + + + dis + Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array. + 0 + + + en + Cache Enabled. + 1 + + + + + RDY + Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready. + 16 + 1 + read-only + + + notReady + Not Ready. + 0 + + + ready + Ready. + 1 + + + + + + + WAY + Cache Way Control Register. + 0x0200 + + + WAY + Number of cache way, default is always 2. Allowed values are 1,2,4. + 0 + 1 + + + 1 + 1 + 0 + + + 2 + 2 + 1 + + + 4 + 4 + 2 + + + + + + + REGCTRL + Regional Control Register. + 0x0204 + + + EN + Enable the regional high andlow bound compare, cache the data only if the TAG content between the high and low bound. + 0 + 8 + + + EXC + Cache the data only if the TAG content is excluded in the high and low bound. + 8 + 8 + + + + + 15 + 0x20 + REGION[%s] + Regional Low and High Bound Registers. + icc_reg + 0x0208 + read-write + + LBOUND + Regional Low Bound Register. + 0x0000 + reg + + + BOUND + Low Bound. + 0 + 32 + + + + + HBOUND + DMA Channel Status Register. + 0x004 + reg + + + BOUND + High Bound. + 0 + 32 + + + + + + PFMCTRL + Performance Control Register. + 0x0300 + + + EN + Enable performance counter. Clear to 0 when AHB access counter reach 0. + 0 + 1 + + + + + PFMCNT + Performance Counter Register. + 0x0304 + + + CNT + Write the total AHB access counter. Read the current performance hit count. + 0 + 32 + + + + + INVALIDATE + Invalidate All Registers. + 0x0700 + read-write + + + INVALID + Invalidate. + 0 + 32 + + + + + + + \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/SPI/spi_reva_me30.svd b/Libraries/PeriphDrivers/Source/SPI/spi_reva_me30.svd index f91d21497cc..fb1b9851d5f 100644 --- a/Libraries/PeriphDrivers/Source/SPI/spi_reva_me30.svd +++ b/Libraries/PeriphDrivers/Source/SPI/spi_reva_me30.svd @@ -90,37 +90,37 @@ - MST_MODE - Master Mode Enable. + CTRLR_MODE + Controller Mode Enable. 1 1 dis - SPI is Slave mode. + SPI is Target mode. 0 en - SPI is Master mode. + SPI is Controller mode. 1 - SS_IO - Slave Select 0, IO direction, to support Multi-Master mode,Slave Select 0 can be input in Master mode. This bit has no effect in slave mode. + TS_IO + Target Select 0, IO direction, to support Multi-Controller mode,Target Select 0 can be input in Controller mode. This bit has no effect in target mode. 4 1 output - Slave select 0 is output. + Target select 0 is output. 0 input - Slave Select 0 is input, only valid if MMEN=1. + Target Select 0 is input, only valid if MMEN=1. 1 @@ -133,53 +133,53 @@ start - Master Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Master halts, if a transaction completes, and the TX FIFO is not empty, the Master initiates another transaction. + Controller Initiates a transaction, this bit is self clearing when transactions are done. If a transaction cimpletes, and the TX FIFO is empty, the Controller halts, if a transaction completes, and the TX FIFO is not empty, the Controller initiates another transaction. 1 - SS_CTRL - Start Select Control. Used in Master mode to control the behavior of the Slave Select signal at the end of a transaction. + TS_CTRL + Start Select Control. Used in Controller mode to control the behavior of the Target Select signal at the end of a transaction. 8 1 DEASSERT - SPI De-asserts Slave Select at the end of a transaction. + SPI De-asserts Target Select at the end of a transaction. 0 - ASSERT - SPI leaves Slave Select asserted at the end of a transaction. + ATSERT + SPI leaves Target Select asserted at the end of a transaction. 1 - SS_ACTIVE - Slave Select, when in Master mode selects which Slave devices are selected. More than one Slave device can be selected. + TS_ACTIVE + Target Select, when in Controller mode selects which Target devices are selected. More than one Target device can be selected. 16 4 - SS0 - SS0 is selected. + TS0 + TS0 is selected. 0x1 - SS1 - SS1 is selected. + TS1 + TS1 is selected. 0x2 - SS2 - SS2 is selected. + TS2 + TS2 is selected. 0x4 - SS3 - SS3 is selected. + TS3 + TS3 is selected. 0x8 @@ -396,29 +396,29 @@ - SSPOL - Slave Select Polarity, each Slave Select can have unique polarity. + TSPOL + Target Select Polarity, each Target Select can have unique polarity. 16 4 - SS0_high - SS0 active high. + TS0_high + TS0 active high. 0x1 - SS1_high - SS1 active high. + TS1_high + TS1 active high. 0x2 - SS2_high - SS2 active high. + TS2_high + TS2 active high. 0x4 - SS3_high - SS3 active high. + TS3_high + TS3 active high. 0x8 @@ -426,40 +426,40 @@ - SSTIME - Register for controlling SPI peripheral/Slave Select Timing. + TSTIME + Register for controlling SPI peripheral/Target Select Timing. 0x10 read-write PRE - Slave Select Pre delay 1. + Target Select Pre delay 1. 0 8 256 - 256 system clocks between SS active and first serial clock edge. + 256 system clocks between TS active and first serial clock edge. 0 POST - Slave Select Post delay 2. + Target Select Post delay 2. 8 8 256 - 256 system clocks between last serial clock edge and SS inactive. + 256 system clocks between last serial clock edge and TS inactive. 0 INACT - Slave Select Inactive delay. + Target Select Inactive delay. 16 8 @@ -705,8 +705,8 @@ - SSA - Slave Select Asserted. + TSA + Target Select Asserted. 4 1 @@ -718,8 +718,8 @@ - SSD - Slave Select Deasserted. + TSD + Target Select Deasserted. 5 1 @@ -732,7 +732,7 @@ FAULT - Multi-Master Mode Fault. + Multi-Controller Mode Fault. 8 1 @@ -745,7 +745,7 @@ ABORT - Slave Abort Detected. + Target Abort Detected. 9 1 @@ -757,8 +757,8 @@ - MST_DONE - Master Done, set when SPI Master has completed any transactions. + CTRLR_DONE + Controller Done, set when SPI Controller has completed any transactions. 11 1 @@ -902,8 +902,8 @@ - SSA - Slave Select Asserted interrupt enable. + TSA + Target Select Asserted interrupt enable. 4 1 @@ -920,8 +920,8 @@ - SSD - Slave Select Deasserted interrupt enable. + TSD + Target Select Deasserted interrupt enable. 5 1 @@ -939,7 +939,7 @@ FAULT - Multi-Master Mode Fault interrupt enable. + Multi-Controller Mode Fault interrupt enable. 8 1 @@ -957,7 +957,7 @@ ABORT - Slave Abort Detected interrupt enable. + Target Abort Detected interrupt enable. 9 1 @@ -974,8 +974,8 @@ - MST_DONE - Master Done interrupt enable. + CTRLR_DONE + Controller Done interrupt enable. 11 1 @@ -1213,7 +1213,7 @@ BUSY - SPI active status. In Master mode, set when transaction starts, cleared when last bit of last character is acted upon and Slave Select de-assertion would occur. In Slave mode, set when Slave Select is asserted, cleared when Slave Select is de-asserted. Not used in Timer mode. + SPI active status. In Controller mode, set when transaction starts, cleared when last bit of last character is acted upon and Target Select de-assertion would occur. In Target mode, set when Target Select is asserted, cleared when Target Select is de-asserted. Not used in Timer mode. 0 1 diff --git a/Libraries/PeriphDrivers/Source/SYS/SVD/gcfr_me30.svd b/Libraries/PeriphDrivers/Source/SYS/SVD/gcfr_me30.svd deleted file mode 100644 index 884a52161b4..00000000000 --- a/Libraries/PeriphDrivers/Source/SYS/SVD/gcfr_me30.svd +++ /dev/null @@ -1,55 +0,0 @@ - - - - GCFR - Global Control Function Register. - 0x40005800 - - 0x00 - 0x400 - registers - - - - REG0 - Register 0. - 0x00 - read-write - - - ISO_WUP - ISO Warm Up Value. - 0 - 9 - - - IPO_WUP - IPO Warm Up Value. - 16 - 11 - - - - - REG1 - Register 1. - 0x04 - read-write - - - ERFO_WUP - ERFO Warm Up Value. - 0 - 14 - - - IBRO_WUP - IBRO Warm Up Value. - 16 - 6 - - - - - - \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/WUT/wut_reva_me30.svd b/Libraries/PeriphDrivers/Source/WUT/wut_reva_me30.svd index e9c590e8b98..509e66968cc 100644 --- a/Libraries/PeriphDrivers/Source/WUT/wut_reva_me30.svd +++ b/Libraries/PeriphDrivers/Source/WUT/wut_reva_me30.svd @@ -44,13 +44,13 @@ - INTR + INTFL Clear Interrupt. Writing a value (0 or 1) to a bit in this register clears the associated interrupt. 0x0C oneToClear - IF_CLR + CLR Clear Interrupt. 0 1 From 6b34f9357687649c43cac1c595e1c75ae57ad5b9 Mon Sep 17 00:00:00 2001 From: Woo Date: Tue, 30 Apr 2024 12:36:02 -0500 Subject: [PATCH 24/93] Remove unneeded SVD files --- .../Source/I2C/i2c_reva_me30.svd | 1480 ----------------- .../Source/I2S/i2s_reva_me30.svd | 327 ---- .../Source/LPCMP/lpcmp_reva_me30.svd | 59 - .../Source/OWM/owm_reva_me30.svd | 237 --- .../Source/SYS/SVD/lpgcr_me30.svd | 127 -- 5 files changed, 2230 deletions(-) delete mode 100644 Libraries/PeriphDrivers/Source/I2C/i2c_reva_me30.svd delete mode 100644 Libraries/PeriphDrivers/Source/I2S/i2s_reva_me30.svd delete mode 100644 Libraries/PeriphDrivers/Source/LPCMP/lpcmp_reva_me30.svd delete mode 100644 Libraries/PeriphDrivers/Source/OWM/owm_reva_me30.svd delete mode 100644 Libraries/PeriphDrivers/Source/SYS/SVD/lpgcr_me30.svd diff --git a/Libraries/PeriphDrivers/Source/I2C/i2c_reva_me30.svd b/Libraries/PeriphDrivers/Source/I2C/i2c_reva_me30.svd deleted file mode 100644 index b49bf1fe78e..00000000000 --- a/Libraries/PeriphDrivers/Source/I2C/i2c_reva_me30.svd +++ /dev/null @@ -1,1480 +0,0 @@ - - - - I2C0 - Inter-Integrated Circuit. - I2C - 0x4001D000 - 32 - - 0x00 - 0x1000 - registers - - - I2C0 - I2C0 IRQ - 13 - - - - CTRL - Control Register0. - 0x00 - - - - EN - I2C Enable. - [0:0] - read-write - - - dis - Disable I2C. - 0 - - - en - enable I2C. - 1 - - - - - - MST_MODE - Master Mode Enable. - [1:1] - read-write - - - slave_mode - Slave Mode. - 0 - - - master_mode - Master Mode. - 1 - - - - - - GC_ADDR_EN - General Call Address Enable. - [2:2] - read-write - - - dis - Ignore Gneral Call Address. - 0 - - - en - Acknowledge general call address. - 1 - - - - - - IRXM_EN - Interactive Receive Mode. - [3:3] - read-write - - - dis - Disable Interactive Receive Mode. - 0 - - - en - Enable Interactive Receive Mode. - 1 - - - - - - IRXM_ACK - Data Acknowledge. This bit defines the acknowledge bit returned by the I2C receiver while IRXM = 1 HW forces ACK to 0 when IRXM = 0. - [4:4] - read-write - - - ack - return ACK (pulling SDA LOW). - 0 - - - nack - return NACK (leaving SDA HIGH). - 1 - - - - - - SCL_OUT - SCL Output. This bits control SCL output when SWOE =1. - [6:6] - read-write - - - drive_scl_low - Drive SCL low. - 0 - - - release_scl - Release SCL. - 1 - - - - - - SDA_OUT - SDA Output. This bits control SDA output when SWOE = 1. - [7:7] - read-write - - - drive_sda_low - Drive SDA low. - 0 - - - release_sda - Release SDA. - 1 - - - - - - SCL - SCL status. This bit reflects the logic gate of SCL signal. - [8:8] - read-only - - - - SDA - SDA status. THis bit reflects the logic gate of SDA signal. - [9:9] - read-only - - - - BB_EN - Software Output Enable. - [10:10] - read-write - - - outputs_disable - I2C Outputs SCLO and SDAO disabled. - 0 - - - outputs_enable - I2C Outputs SCLO and SDAO enabled. - 1 - - - - - - READ - Read. This bit reflects the R/W bit of an address match (AMI = 1) or general call match (GCI = 1). This bit is valid 3 cycles after the relevant interrupt bit is set. - [11:11] - read-only - - - write - Write. - 0 - - - read - Read. - 1 - - - - - - CLKSTR_DIS - This bit will disable slave clock stretching when set. - [12:12] - read-write - - - en - Slave clock stretching enabled. - 0 - - - dis - Slave clock stretching disabled. - 1 - - - - - - ONE_MST_MODE - SCL Push-Pull Mode. This bit controls whether SCL is operated in a the I2C standard open-drain mode, or in a non-standard push-pull mode where the Hi-Z output isreplaced with Drive-1. The non-standard mode should only be used when operating as a master and communicating with slaves that are guaranteed to never drive SCL low. - [13:13] - read-write - - - dis - Standard open-drain operation: - drive low for 0, Hi-Z for 1 - 0 - - - en - Non-standard push-pull operation: - drive low for 0, drive high for 1 - 1 - - - - - - HS_EN - High speed mode enable - [15:15] - read-write - - - - - STATUS - Status Register. - 0x04 - - - BUSY - Bus Status. - [0:0] - read-only - - - idle - I2C Bus Idle. - 0 - - - busy - I2C Bus Busy. - 1 - - - - - RX_EM - RX empty. - [1:1] - read-only - - - not_empty - Not Empty. - 0 - - - empty - Empty. - 1 - - - - - RX_FULL - RX Full. - [2:2] - read-only - - - not_full - Not Full. - 0 - - - full - Full. - 1 - - - - - TX_EM - TX Empty. - [3:3] - - - not_empty - Not Empty. - 0 - - - empty - Empty. - 1 - - - - - TX_FULL - TX Full. - [4:4] - - - not_empty - Not Empty. - 0 - - - empty - Empty. - 1 - - - - - MST_BUSY - Clock Mode. - [5:5] - read-only - - - not_actively_driving_scl_clock - Device not actively driving SCL clock cycles. - 0 - - - actively_driving_scl_clock - Device operating as master and actively driving SCL clock cycles. - 1 - - - - - - - INTFL0 - Interrupt Status Register. - 0x08 - - - DONE - Transfer Done Interrupt. - [0:0] - - INT_FL0_Done - - inactive - No Interrupt is Pending. - 0 - - - pending - An interrupt is pending. - 1 - - - - - IRXM - Interactive Receive Interrupt. - [1:1] - - - inactive - No Interrupt is Pending. - 0 - - - pending - An interrupt is pending. - 1 - - - - - GC_ADDR_MATCH - Slave General Call Address Match Interrupt. - [2:2] - - - inactive - No Interrupt is Pending. - 0 - - - pending - An interrupt is pending. - 1 - - - - - ADDR_MATCH - Slave Address Match Interrupt. - [3:3] - - - inactive - No Interrupt is Pending. - 0 - - - pending - An interrupt is pending. - 1 - - - - - RX_THD - Receive Threshold Interrupt. This bit is automaticcaly cleared when RX_FIFO is below the threshold level. - [4:4] - - - inactive - No interrupt is pending. - 0 - - - pending - An interrupt is pending. RX_FIFO equal or more bytes than the threshold. - 1 - - - - - TX_THD - Transmit Threshold Interrupt. This bit is automaticcaly cleared when TX_FIFO is above the threshold level. - [5:5] - - - inactive - No interrupt is pending. - 0 - - - pending - An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. - 1 - - - - - STOP - STOP Interrupt. - [6:6] - - - inactive - No interrupt is pending. - 0 - - - pending - An interrupt is pending. TX_FIFO has equal or less bytes than the threshold. - 1 - - - - - ADDR_ACK - Address Acknowledge Interrupt. - [7:7] - - - inactive - No Interrupt is Pending. - 0 - - - pending - An interrupt is pending. - 1 - - - - - ARB_ERR - Arbritation error Interrupt. - [8:8] - - - inactive - No Interrupt is Pending. - 0 - - - pending - An interrupt is pending. - 1 - - - - - TO_ERR - timeout Error Interrupt. - [9:9] - - - inactive - No Interrupt is Pending. - 0 - - - pending - An interrupt is pending. - 1 - - - - - ADDR_NACK_ERR - Address NACK Error Interrupt. - [10:10] - - - inactive - No Interrupt is Pending. - 0 - - - pending - An interrupt is pending. - 1 - - - - - DATA_ERR - Data NACK Error Interrupt. - [11:11] - - - inactive - No Interrupt is Pending. - 0 - - - pending - An interrupt is pending. - 1 - - - - - DNR_ERR - Do Not Respond Error Interrupt. - [12:12] - - - inactive - No Interrupt is Pending. - 0 - - - pending - An interrupt is pending. - 1 - - - - - START_ERR - Start Error Interrupt. - [13:13] - - - inactive - No Interrupt is Pending. - 0 - - - pending - An interrupt is pending. - 1 - - - - - STOP_ERR - Stop Error Interrupt. - [14:14] - - - inactive - No Interrupt is Pending. - 0 - - - pending - An interrupt is pending. - 1 - - - - - TX_LOCKOUT - Transmit Lock Out Interrupt. - [15:15] - - - MAMI - Multiple Address Match Interrupt - [21:16] - - - RD_ADDR_MATCH - Slave Read Address Match Interrupt - [22:22] - - - WR_ADDR_MATCH - Slave Write Address Match Interrupt - [23:23] - - - - - INTEN0 - Interrupt Enable Register. - 0x0C - read-write - - - DONE - Transfer Done Interrupt Enable. - [0:0] - read-write - - - dis - Interrupt disabled. - 0 - - - en - Interrupt enabled when DONE = 1. - 1 - - - - - IRXM - Description not available. - [1:1] - read-write - - - dis - Interrupt disabled. - 0 - - - en - Interrupt enabled when RX_MODE = 1. - 1 - - - - - GC_ADDR_MATCH - Slave mode general call address match received input enable. - [2:2] - read-write - - - dis - Interrupt disabled. - 0 - - - en - Interrupt enabled when GEN_CTRL_ADDR = 1. - 1 - - - - - ADDR_MATCH - Slave mode incoming address match interrupt. - [3:3] - read-write - - - dis - Interrupt disabled. - 0 - - - en - Interrupt enabled when ADDR_MATCH = 1. - 1 - - - - - RX_THD - RX FIFO Above Treshold Level Interrupt Enable. - [4:4] - read-write - - - dis - Interrupt disabled. - 0 - - - en - Interrupt enabled. - 1 - - - - - TX_THD - TX FIFO Below Treshold Level Interrupt Enable. - [5:5] - - - dis - Interrupt disabled. - 0 - - - en - Interrupt enabled. - 1 - - - - - STOP - Stop Interrupt Enable - [6:6] - read-write - - - dis - Interrupt disabled. - 0 - - - en - Interrupt enabled when STOP = 1. - 1 - - - - - ADDR_ACK - Received Address ACK from Slave Interrupt. - [7:7] - - - dis - Interrupt disabled. - 0 - - - en - Interrupt enabled. - 1 - - - - - ARB_ERR - Master Mode Arbitration Lost Interrupt. - [8:8] - - - dis - Interrupt disabled. - 0 - - - en - Interrupt enabled. - 1 - - - - - TO_ERR - Timeout Error Interrupt Enable. - [9:9] - - - dis - Interrupt disabled. - 0 - - - en - Interrupt enabled. - 1 - - - - - ADDR_NACK_ERR - Master Mode Address NACK Received Interrupt. - [10:10] - - - dis - Interrupt disabled. - 0 - - - en - Interrupt enabled. - 1 - - - - - DATA_ERR - Master Mode Data NACK Received Interrupt. - [11:11] - - - dis - Interrupt disabled. - 0 - - - en - Interrupt enabled. - 1 - - - - - DNR_ERR - Slave Mode Do Not Respond Interrupt. - [12:12] - - - dis - Interrupt disabled. - 0 - - - en - Interrupt enabled. - 1 - - - - - START_ERR - Out of Sequence START condition detected interrupt. - [13:13] - - - dis - Interrupt disabled. - 0 - - - en - Interrupt enabled. - 1 - - - - - STOP_ERR - Out of Sequence STOP condition detected interrupt. - [14:14] - - - dis - Interrupt disabled. - 0 - - - en - Interrupt enabled. - 1 - - - - - TX_LOCKOUT - TX FIFO Locked Out Interrupt. - [15:15] - - - MAMI - Multiple Address Match Interrupt - [21:16] - - - RD_ADDR_MATCH - Slave Read Address Match Interrupt - [22:22] - - - WR_ADDR_MATCH - Slave Write Address Match Interrupt - [23:23] - - - - - INTFL1 - Interrupt Status Register 1. - 0x10 - - - RX_OV - Receiver Overflow Interrupt. When operating as a slave receiver, this bit is set when you reach the first data bit and the RX FIFO and shift register are both full. - [0:0] - - - inactive - No Interrupt is Pending. - 0 - - - pending - An interrupt is pending. - 1 - - - - - TX_UN - Transmit Underflow Interrupt. When operating as a slave transmitter, this bit is set when you reach the first data bit and the TX FIFO is empty and the master is still asking for more data (i.e the master hasn't sent a NACK yet). - [1:1] - - - inactive - No Interrupt is Pending. - 0 - - - pending - An interrupt is pending. - 1 - - - - - START - START Condition Status Flag. - [2:2] - - - - - INTEN1 - Interrupt Staus Register 1. - 0x14 - read-write - - - RX_OV - Receiver Overflow Interrupt Enable. - [0:0] - - - dis - No Interrupt is Pending. - 0 - - - en - An interrupt is pending. - 1 - - - - - TX_UN - Transmit Underflow Interrupt Enable. - [1:1] - - - dis - No Interrupt is Pending. - 0 - - - en - An interrupt is pending. - 1 - - - - - START - START Condition Interrupt Enable. - [2:2] - - - - - FIFOLEN - FIFO Configuration Register. - 0x18 - - - RX_DEPTH - Receive FIFO Length. - [7:0] - read-only - - - TX_DEPTH - Transmit FIFO Length. - [15:8] - read-only - - - - - RXCTRL0 - Receive Control Register 0. - 0x1C - - - DNR - Do Not Respond. - [0:0] - - - respond - Always respond to address match. - 0 - - - not_respond_rx_fifo_empty - Do not respond to address match when RX_FIFO is not empty. - 1 - - - - - FLUSH - Receive FIFO Flush. This bit is automatically cleared to 0 after the operation. Setting this bit to 1 will affect RX_FIFO status. - [7:7] - - - not_flushed - FIFO not flushed. - 0 - - - flush - Flush RX_FIFO. - 1 - - - - - THD_LVL - Receive FIFO Threshold. These bits define the RX_FIFO interrupt threshold. - [11:8] - - - - - RXCTRL1 - Receive Control Register 1. - 0x20 - - - CNT - Receive Count Bits. These bits define the number of bytes to be received in a transaction, except for the case RXCNT = 0. RXCNT = 0 means 256 bytes to be received in a transaction. - [7:0] - - - LVL - Receive FIFO Count. These bits reflect the number of byte in the RX_FIFO. These bits are flushed when I2CEN = 0. - [11:8] - read-only - - - - - TXCTRL0 - Transmit Control Register 0. - 0x24 - - - PRELOAD_MODE - Transmit FIFO Preaload Mode. Setting this bit will allow for high speed application to preload the transmit FIFO prior to Slave Address Match. - [0:0] - - - TX_READY_MODE - Transmit FIFO Ready Manual Mode. - [1:1] - - - en - HW control of I2CTXRDY enabled. - 0 - - - dis - HW control of I2CTXRDY disabled. - 1 - - - - - GC_ADDR_FLUSH_DIS - TX FIFO General Call Address Match Auto Flush Disable. - [2:2] - - - en - Enabled. - 0 - - - dis - Disabled. - 1 - - - - - WR_ADDR_FLUSH_DIS - TX FIFO Slave Address Match Write Auto Flush Disable. - [3:3] - - - en - Enabled. - 0 - - - dis - Disabled. - 1 - - - - - RD_ADDR_FLUSH_DIS - TX FIFO Slave Address Match Read Auto Flush Disable. - [4:4] - - - en - Enabled. - 0 - - - dis - Disabled. - 1 - - - - - NACK_FLUSH_DIS - TX FIFO received NACK Auto Flush Disable. - [5:5] - - - en - Enabled. - 0 - - - dis - Disabled. - 1 - - - - - FLUSH - Transmit FIFO Flush. This bit is automatically cleared to 0 after the operation. - [7:7] - - - not_flushed - FIFO not flushed. - 0 - - - flush - Flush TX_FIFO. - 1 - - - - - THD_VAL - Transmit FIFO Threshold. These bits define the TX_FIFO interrupt threshold. - [11:8] - - - - - TXCTRL1 - Transmit Control Register 1. - 0x28 - - - PRELOAD_RDY - Transmit FIFO Preload Ready. - [0:0] - - - LAST - Transmit Last. - [1:1] - - - LVL - Transmit FIFO Count. These bits reflect the number of bytes in the TX_FIFO. - [11:8] - read-only - - - - - FIFO - Data Register. - 0x2C - - - DATA - Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location. - 0 - 8 - - - - - MSTCTRL - Master Control Register. - 0x30 - - - START - Setting this bit to 1 will start a master transfer. - [0:0] - - - RESTART - Setting this bit to 1 will generate a repeated START. - [1:1] - - - STOP - Setting this bit to 1 will generate a STOP condition. - [2:2] - - - EX_ADDR_EN - Slave Extend Address Select. - [7:7] - - - 7_bits_address - 7-bit address. - 0 - - - 10_bits_address - 10-bit address. - 1 - - - - - CODE - Master Code. - [10:8] - - - IGN_ACK - Master Ignore Acknowledge. - [12:12] - - - - - CLKLO - Clock Low Register. - 0x34 - - - LO - Clock low. In master mode, these bits define the SCL low period. In slave mode, these bits define the time SCL will be held low after data is outputted. - [8:0] - - - - - CLKHI - Clock high Register. - 0x38 - - - HI - Clock High. In master mode, these bits define the SCL high period. - [8:0] - - - - - HSCLK - Clock high Register. - 0x3C - - - LO - Clock Low. This field sets the Hs-Mode clock low count. In Slave mode, this is the time SCL is held low after data is output on SDA. - [7:0] - - - HI - Clock High. This field sets the Hs-Mode clock high count. In Slave mode, this is the time SCL is held high after data is output on SDA - [15:8] - - - - - TIMEOUT - Timeout Register - 0x40 - - - SCL_TO_VAL - Timeout - [15:0] - - - - - DMA - DMA Register. - 0x48 - - - TX_EN - TX channel enable. - [0:0] - - - dis - Disable. - 0 - - - en - Enable. - 1 - - - - - RX_EN - RX channel enable. - [1:1] - - - dis - Disable. - 0 - - - en - Enable. - 1 - - - - - - - 4 - 4 - SLAVE_MULTI[%s] - Slave Address Register. - SLAVE0 - 0x4C - 32 - read-write - - - ADDR - Slave Address. - [9:0] - - - DIS - Slave Disable. - [10:10] - - - EXT_ADDR_EN - Extended Address Select. - [15:15] - - - 7_bits_address - 7-bit address. - 0 - - - 10_bits_address - 10-bit address. - 1 - - - - - - - SLAVE0 - Slave Address Register. - 0x4C - - - SLAVE1 - Slave Address Register. - 0x50 - - - SLAVE2 - Slave Address Register. - 0x54 - - - SLAVE3 - Slave Address Register. - 0x58 - - - - - \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/I2S/i2s_reva_me30.svd b/Libraries/PeriphDrivers/Source/I2S/i2s_reva_me30.svd deleted file mode 100644 index 941e6e7cc82..00000000000 --- a/Libraries/PeriphDrivers/Source/I2S/i2s_reva_me30.svd +++ /dev/null @@ -1,327 +0,0 @@ - - - - I2S - Inter-IC Sound Interface. - I2S - 0x40060000 - 32 - - 0x00 - 0x1000 - registers - - - I2S - I2S IRQ - 99 - - - - CTRL0CH0 - Global mode channel. - 0x00 - - - LSB_FIRST - LSB Transmit Receive First. - [1:1] - read-write - - - PDM_FILT - PDM Filter. - [2:2] - read-write - - - PDM_EN - PDM Enable. - [3:3] - read-write - - - USEDDR - DDR. - [4:4] - read-write - - - PDM_INV - Invert PDM. - [5:5] - read-write - - - CH_MODE - SCK Select. - [7:6] - read-write - - - WS_POL - WS polarity select. - [8:8] - read-write - - - MSB_LOC - MSB location. - [9:9] - read-only - - - ALIGN - Align to MSB or LSB. - [10:10] - read-only - - - EXT_SEL - External SCK/WS selection. - [11:11] - read-write - - - STEREO - Stereo mode of I2S. - [13:12] - read-only - - - WSIZE - Data size when write to FIFO. - [15:14] - read-write - - - TX_EN - TX channel enable. - [16:16] - read-write - - - RX_EN - RX channel enable. - [17:17] - read-write - - - FLUSH - Flushes the TX/RX FIFO buffer. - [18:18] - read-write - - - RST - Write 1 to reset channel. - [19:19] - read-write - - - FIFO_LSB - Bit Field Control. - [20:20] - read-write - - - RX_THD_VAL - depth of receive FIFO for threshold interrupt generation. - [31:24] - read-write - - - - - CTRL1CH0 - Local channel Setup. - 0x10 - - - BITS_WORD - I2S word length. - [4:0] - read-write - - - EN - I2S clock enable. - [8:8] - read-write - - - SMP_SIZE - I2S sample size length. - [13:9] - read-write - - - CLKSEL - Select source clock for internal SCK mode. - [14:14] - read-write - - - ADJUST - LSB/MSB Justify. - [15:15] - read-write - - - CLKDIV - I2S clock frequency divisor. - [31:16] - read-write - - - - - FILTCH0 - Filter. - 0x20 - - - DMACH0 - DMA Control. - 0x30 - - - DMA_TX_THD_VAL - TX FIFO Level DMA Trigger. - [6:0] - read-write - - - DMA_TX_EN - TX DMA channel enable. - [7:7] - read-write - - - DMA_RX_THD_VAL - RX FIFO Level DMA Trigger. - [14:8] - read-write - - - DMA_RX_EN - RX DMA channel enable. - [15:15] - read-write - - - TX_LVL - Number of data word in the TX FIFO. - [23:16] - read-write - - - RX_LVL - Number of data word in the RX FIFO. - [31:24] - read-write - - - - - FIFOCH0 - I2S Fifo. - 0x40 - - - DATA - Load/unload location for TX and RX FIFO buffers. - [31:0] - read-write - - - - - INTFL - ISR Status. - 0x50 - - - RX_OV_CH0 - Status for RX FIFO Overrun interrupt. - [0:0] - read-write - - - RX_THD_CH0 - Status for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field. - [1:1] - read-write - - - TX_OB_CH0 - Status for interrupt when TX FIFO has only one byte remaining. - [2:2] - read-write - - - TX_HE_CH0 - Status for interrupt when TX FIFO is half empty. - [3:3] - read-write - - - - - INTEN - Interrupt Enable. - 0x54 - - - RX_OV_CH0 - Enable for RX FIFO Overrun interrupt. - [0:0] - read-write - - - RX_THD_CH0 - Enable for interrupt when RX FIFO reaches the number of bytes configured by the RXTHD field. - [1:1] - read-write - - - TX_OB_CH0 - Enable for interrupt when TX FIFO has only one byte remaining. - [2:2] - read-write - - - TX_HE_CH0 - Enable for interrupt when TX FIFO is half empty. - [3:3] - read-write - - - - - EXTSETUP - Ext Control. - 0x58 - - - EXT_BITS_WORD - Word Length for ch_mode. - [4:0] - read-write - - - - - WKEN - Wakeup Enable. - 0x5C - - - WKFL - Wakeup Flags. - 0x60 - - - - - \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/LPCMP/lpcmp_reva_me30.svd b/Libraries/PeriphDrivers/Source/LPCMP/lpcmp_reva_me30.svd deleted file mode 100644 index c6d4b776bd3..00000000000 --- a/Libraries/PeriphDrivers/Source/LPCMP/lpcmp_reva_me30.svd +++ /dev/null @@ -1,59 +0,0 @@ - - - - LPCMP - Low Power Comparator - 0x40088000 - - 0x00 - 0x400 - registers - - - LPCMP - Low Power Comparato - 103 - - - - 3 - 4 - CTRL[%s] - Comparator Control Register. - 0x00 - - - EN - Comparator Enable. - 0 - 1 - - - POL - Polarity Select - 5 - 1 - - - INTR_EN - IRQ Enable. - 6 - 1 - - - OUT - Raw Compartor Input. - 14 - 1 - - - INTR_FL - IRQ Flag - 15 - 1 - - - - - - \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/OWM/owm_reva_me30.svd b/Libraries/PeriphDrivers/Source/OWM/owm_reva_me30.svd deleted file mode 100644 index 8506606fbd7..00000000000 --- a/Libraries/PeriphDrivers/Source/OWM/owm_reva_me30.svd +++ /dev/null @@ -1,237 +0,0 @@ - - - - OWM - 1-Wire Master Interface. - 0x4003D000 - 32 - read-write - - 0 - 0x1000 - registers - - - OneWire - 67 - - - - - CTRL0 - 1-Wire Master Control Register. - 0x0000 - read-write - - - LL_EN - Enable Long Line Mode. - [0:0] - read-write - - - FPRESDET - Force Line During Presence Detect. - [1:1] - read-write - - - BB_EN - Bit Bang Enable. - [2:2] - read-write - - - EXT_PU_MODE - Provide an extra output control to control an external pullup. - [3:3] - read-write - - - EXT_PU_EN - Enable External Pullup. - [4:4] - read-write - - - SB_EN - Enable Single Bit TX/RX Mode. - [5:5] - read-write - - - OD - Enables overdrive speed for 1-Wire operations. - [6:6] - read-write - - - INT_PU_EN - Enable intenral pullup. - [7:7] - read-write - - - - - - CLKDIV - 1-Wire Master Clock Divisor. - 0x0004 - read-write - - - DIVISOR - Clock Divisor for 1Mhz. - [7:0] - read-write - - - - - - CTRL1 - 1-Wire Master Control/Status. - 0x0008 - read-write - - - RST - Start OW Reset. - [0:0] - read-write - - - SRA_EN - Enable SRA Mode. - [1:1] - read-write - - - BB_OUT_EN - Bit Bang Output Enable. - [2:2] - read-write - - - INPUT_ST - OW Input State. - [3:3] - read-only - - - OD_SPEC_ST - Overdrive Spec Mode. - [4:4] - read-only - - - PRESDET_ST - Presence Pulse Detected. - [7:7] - read-only - - - - - - DATA - 1-Wire Master Data Buffer. - 0x000C - read-write - - - DATA - TX/RX Buffer. - [7:0] - read-write - - - - - - INTFL - 1-Wire Master Interrupt Flags. - 0x0010 - read-write - - - RST_DONE - OW Reset Sequence Completed. - [0:0] - read-write - - - TX_EM - TX Data Empty Interrupt Flag. - [1:1] - read-write - - - RX_RDY - RX Data Ready Interrupt Flag - [2:2] - read-write - - - LINE_SHORT - OW Line Short Detected Interrupt Flag. - [3:3] - read-write - - - LINE_LOW - OW Line Low Detected Interrupt Flag. - [4:4] - read-write - - - - - - INTEN - 1-Wire Master Interrupt Enables. - 0x0014 - read-write - - - RST_DONE - OW Reset Sequence Completed. - [0:0] - read-write - oneToClear - - - TX_EM - Tx Data Empty Interrupt Enable. - [1:1] - read-write - oneToClear - - - RX_RDY - Rx Data Ready Interrupt Enable. - [2:2] - read-write - oneToClear - - - LINE_SHORT - OW Line Short Detected Interrupt Enable. - [3:3] - read-write - oneToClear - - - LINE_LOW - OW Line Low Detected Interrupt Enable. - [4:4] - read-write - oneToClear - - - - - - - \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/SYS/SVD/lpgcr_me30.svd b/Libraries/PeriphDrivers/Source/SYS/SVD/lpgcr_me30.svd deleted file mode 100644 index d7305e020bc..00000000000 --- a/Libraries/PeriphDrivers/Source/SYS/SVD/lpgcr_me30.svd +++ /dev/null @@ -1,127 +0,0 @@ - - - - LPGCR - Low Power Global Control. - 0x40080000 - - 0x00 - 0x400 - registers - - - - RST - Low Power Reset Register. - 0x08 - - - GPIO2 - Low Power GPIO 2 Reset. - 0 - 1 - - reset - read-write - - reset_done - Reset complete. - 0 - - - busy - Starts Reset or indicates reset in progress. - 1 - - - - - WDT1 - Low Power Watchdog Timer 1 Reset. - 1 - 1 - - - TMR4 - Low Power Timer 4 Reset. - 2 - 1 - - - TMR5 - Low Power Timer 5 Reset. - 3 - 1 - - - UART3 - Low Power UART 3 Reset. - 4 - 1 - - - LPCOMP - Low Power Comparator Reset. - 6 - 1 - - - - - PCLKDIS - Low Power Peripheral Clock Disable Register. - 0x0C - - - GPIO2 - Low Power GPIO 2 Clock Disable. - 0 - 1 - - - en - enable it. - 0 - - - dis - disable it. - 1 - - - - - WDT1 - Low Power Watchdog 1 Clock Disable. - 1 - 1 - - - TMR4 - Low Power Timer 4 Clock Disable. - 2 - 1 - - - TMR5 - Low Power Timer 5 Clock Disable. - 3 - 1 - - - UART3 - Low Power UART 3 Clock Disable. - 4 - 1 - - - LPCOMP - Low Power Comparator Clock Disable. - 6 - 1 - - - - - - From 3b029abfb173a0beaf22ca4c5e4c6be3e37969b6 Mon Sep 17 00:00:00 2001 From: Woo Date: Tue, 30 Apr 2024 12:54:51 -0500 Subject: [PATCH 25/93] Fix INRO clock freq and move SPC into SYS --- Libraries/CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h | 2 +- Libraries/PeriphDrivers/Source/{SPC => SYS/SVD/TZ}/spc_reva.svd | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename Libraries/PeriphDrivers/Source/{SPC => SYS/SVD/TZ}/spc_reva.svd (100%) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h index c5a0952fe14..981c23d80c7 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h @@ -44,7 +44,7 @@ extern "C" { Update if use of this oscillator requires precise timing.*/ /* NOTE: INRO was previously named NANORING */ #ifndef INRO_FREQ -#define INRO_FREQ 8000 +#define INRO_FREQ 100000 #endif #ifndef IPO_FREQ diff --git a/Libraries/PeriphDrivers/Source/SPC/spc_reva.svd b/Libraries/PeriphDrivers/Source/SYS/SVD/TZ/spc_reva.svd similarity index 100% rename from Libraries/PeriphDrivers/Source/SPC/spc_reva.svd rename to Libraries/PeriphDrivers/Source/SYS/SVD/TZ/spc_reva.svd From aa238cc72dd8b9fc9f2b24fffb7d2db9585b0b6c Mon Sep 17 00:00:00 2001 From: Woo Date: Tue, 30 Apr 2024 14:30:07 -0500 Subject: [PATCH 26/93] Add NSPC register --- .../Maxim/MAX32657/Include/max32657.svd | 26 +++++ .../Device/Maxim/MAX32657/Include/nspc_regs.h | 104 ++++++++++++++++++ .../Source/SYS/SVD/TZ/nspc_reva.svd | 29 +++++ 3 files changed, 159 insertions(+) create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/nspc_regs.h create mode 100644 Libraries/PeriphDrivers/Source/SYS/SVD/TZ/nspc_reva.svd diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd index 45022692810..592a2959317 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd @@ -9868,6 +9868,32 @@ + + NSPC + Non-Secure Privilege Controller. + 0x40090000 + + 0x00 + 0x1000 + registers + + + + APBPRIV + APB Tartet Privileged/Non-privileged PPC Access Register. + 0x0160 + + + PERIPH + Each bit configures the APB PPC to enforce the security access allowed for an individual peripheral. + 0 + 32 + + + + + + SPI SPI peripheral. diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/nspc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/nspc_regs.h new file mode 100644 index 00000000000..b5505f3d114 --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/nspc_regs.h @@ -0,0 +1,104 @@ +/** + * @file nspc_regs.h + * @brief Registers, Bit Masks and Bit Positions for the NSPC Peripheral Module. + * @note This file is @generated. + * @ingroup nspc_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_NSPC_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_NSPC_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup nspc + * @defgroup nspc_registers NSPC_Registers + * @brief Registers, Bit Masks and Bit Positions for the NSPC Peripheral Module. + * @details Non-Secure Privilege Controller. + */ + +/** + * @ingroup nspc_registers + * Structure type to access the NSPC Registers. + */ +typedef struct { + __R uint32_t rsv_0x0_0x15f[88]; + __IO uint32_t apbpriv; /**< \b 0x0160: NSPC APBPRIV Register */ +} mxc_nspc_regs_t; + +/* Register offsets for module NSPC */ +/** + * @ingroup nspc_registers + * @defgroup NSPC_Register_Offsets Register Offsets + * @brief NSPC Peripheral Register Offsets from the NSPC Base Peripheral Address. + * @{ + */ +#define MXC_R_NSPC_APBPRIV ((uint32_t)0x00000160UL) /**< Offset from NSPC Base Address: 0x0160 */ +/**@} end of group nspc_registers */ + +/** + * @ingroup nspc_registers + * @defgroup NSPC_APBPRIV NSPC_APBPRIV + * @brief APB Tartet Privileged/Non-privileged PPC Access Register. + * @{ + */ +#define MXC_F_NSPC_APBPRIV_PERIPH_POS 0 /**< APBPRIV_PERIPH Position */ +#define MXC_F_NSPC_APBPRIV_PERIPH ((uint32_t)(0xFFFFFFFFUL << MXC_F_NSPC_APBPRIV_PERIPH_POS)) /**< APBPRIV_PERIPH Mask */ + +/**@} end of group NSPC_APBPRIV_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_NSPC_REGS_H_ diff --git a/Libraries/PeriphDrivers/Source/SYS/SVD/TZ/nspc_reva.svd b/Libraries/PeriphDrivers/Source/SYS/SVD/TZ/nspc_reva.svd new file mode 100644 index 00000000000..844c25a71ad --- /dev/null +++ b/Libraries/PeriphDrivers/Source/SYS/SVD/TZ/nspc_reva.svd @@ -0,0 +1,29 @@ + + + + NSPC + Non-Secure Privilege Controller. + 0x40090000 + + 0x00 + 0x1000 + registers + + + + APBPRIV + APB Tartet Privileged/Non-privileged PPC Access Register. + 0x0160 + + + PERIPH + Each bit configures the APB PPC to enforce the security access allowed for an individual peripheral. + 0 + 32 + + + + + + + \ No newline at end of file From 01cda583a24155ccb7ba9daba5e1acb138119ced Mon Sep 17 00:00:00 2001 From: Jake Carter Date: Tue, 30 Apr 2024 17:47:28 -0600 Subject: [PATCH 27/93] Remove inclusion of lpgcr regs --- Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h | 1 - 1 file changed, 1 deletion(-) diff --git a/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h b/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h index 2bb366ac654..9586fb68d02 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h @@ -26,7 +26,6 @@ #include "mxc_device.h" #include "gcr_regs.h" -#include "lpgcr_regs.h" #ifdef __cplusplus extern "C" { From b085ffc2e7085f473df7f77896e550289ef9d02b Mon Sep 17 00:00:00 2001 From: Jake Carter Date: Tue, 30 Apr 2024 18:24:46 -0600 Subject: [PATCH 28/93] Add core_cm33.h to top-level device header --- Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h index 396c9128ffb..28245b51a61 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h @@ -149,6 +149,8 @@ typedef enum { #define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ #define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ +#include + /* ================================================================================ */ /* ================== Device Specific Memory Section ================== */ /* ================================================================================ */ From aa7e9ea1ff7337ac5f9850963a33c415f990bb86 Mon Sep 17 00:00:00 2001 From: Jake Carter Date: Tue, 30 Apr 2024 18:25:58 -0600 Subject: [PATCH 29/93] Add MXC_GPIO macros to top-level device header --- .../CMSIS/Device/Maxim/MAX32657/Include/max32657.h | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h index 28245b51a61..da1a488d282 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h @@ -383,6 +383,19 @@ typedef enum { #define MXC_CFG_GPIO_INSTANCES (1) #define MXC_CFG_GPIO_PINS_PORT (32) +/* Utility macros + +Note(JC): There is only 1 GPIO instance, but for driver compatibility these must be +implemented. + +For GET_IDX and GET_GPIO we return -1 so that other MXC_ASSERTs might error out. +For GET_IRQ we follow precedent and return the base 0 IRQn, which is the ICE unlock. +We may want to handle GET_IRQ better... +*/ +#define MXC_GPIO_GET_IDX(p) ((p) == MXC_GPIO0 ? 0 : -1) +#define MXC_GPIO_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0 : -1) +#define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO0_IRQn : (IRQn_Type)0) + /* Non-secure Mapping */ #define MXC_BASE_GPIO0_NS ((uint32_t)0x40008000UL) #define MXC_GPIO0_NS ((mxc_gpio_regs_t *)MXC_BASE_GPIO0_NS) From c76e74ce21a3a602594192a33094fab79124dc0d Mon Sep 17 00:00:00 2001 From: Jake Carter Date: Tue, 30 Apr 2024 18:50:12 -0600 Subject: [PATCH 30/93] Update mxc_sys.h with reset/pclkdis/clksel definitions --- .../PeriphDrivers/Include/MAX32657/mxc_sys.h | 126 ++++++------------ 1 file changed, 39 insertions(+), 87 deletions(-) diff --git a/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h b/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h index 9586fb68d02..def4ee9b925 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h @@ -40,117 +40,68 @@ extern "C" { /** @brief System reset0 and reset1 enumeration. Used in MXC_SYS_PeriphReset0 function */ typedef enum { - MXC_SYS_RESET0_DMA = MXC_F_GCR_RST0_DMA_POS, /**< Reset DMA */ - MXC_SYS_RESET0_WDT0 = MXC_F_GCR_RST0_WDT0_POS, /**< Reset WDT */ + MXC_SYS_RESET0_DMA0 = MXC_F_GCR_RST0_DMA0_POS, /**< Reset DMA0 */ + MXC_SYS_RESET0_WDT = MXC_F_GCR_RST0_WDT_POS, /**< Reset WDT */ MXC_SYS_RESET0_GPIO0 = MXC_F_GCR_RST0_GPIO0_POS, /**< Reset GPIO0 */ - MXC_SYS_RESET0_GPIO1 = MXC_F_GCR_RST0_GPIO1_POS, /**< Reset GPIO1 */ MXC_SYS_RESET0_TMR0 = MXC_F_GCR_RST0_TMR0_POS, /**< Reset TMR0 */ MXC_SYS_RESET0_TMR1 = MXC_F_GCR_RST0_TMR1_POS, /**< Reset TMR1 */ MXC_SYS_RESET0_TMR2 = MXC_F_GCR_RST0_TMR2_POS, /**< Reset TMR2 */ MXC_SYS_RESET0_TMR3 = MXC_F_GCR_RST0_TMR3_POS, /**< Reset TMR3 */ - MXC_SYS_RESET0_UART0 = MXC_F_GCR_RST0_UART0_POS, /**< Reset UART0 */ - MXC_SYS_RESET0_UART1 = MXC_F_GCR_RST0_UART1_POS, /**< Reset UART1 */ - MXC_SYS_RESET0_SPI1 = MXC_F_GCR_RST0_SPI1_POS, /**< Reset SPI1 */ - MXC_SYS_RESET0_I2C0 = MXC_F_GCR_RST0_I2C0_POS, /**< Reset I2C0 */ + MXC_SYS_RESET0_TMR4 = MXC_F_GCR_RST0_TMR4_POS, /**< Reset TMR4 */ + MXC_SYS_RESET0_TMR5 = MXC_F_GCR_RST0_TMR5_POS, /**< Reset TMR5 */ + MXC_SYS_RESET0_UART = MXC_F_GCR_RST0_UART_POS, /**< Reset UART0 */ + MXC_SYS_RESET0_SPI = MXC_F_GCR_RST0_SPI_POS, /**< Reset SPI */ + MXC_SYS_RESET0_I3C = MXC_F_GCR_RST0_I3C, /**< Reset I2C/I3C */ MXC_SYS_RESET0_RTC = MXC_F_GCR_RST0_RTC_POS, /**< Reset RTC */ - MXC_SYS_RESET0_SMPHR = MXC_F_GCR_RST0_SMPHR_POS, /**< Reset SMPHR */ + // MXC_SYS_RESET0_SMPHR = MXC_F_GCR_RST0_SMPHR_POS, /**< Reset SMPHR */ MXC_SYS_RESET0_TRNG = MXC_F_GCR_RST0_TRNG_POS, /**< Reset TRNG */ - MXC_SYS_RESET0_CNN = MXC_F_GCR_RST0_CNN_POS, /**< Reset CNN */ - MXC_SYS_RESET0_ADC = MXC_F_GCR_RST0_ADC_POS, /**< Reset ADC */ - MXC_SYS_RESET0_UART2 = MXC_F_GCR_RST0_UART2_POS, /**< Reset UART2 */ + MXC_SYS_RESET0_DMA1 = MXC_F_GCR_RST0_DMA1_POS, /**< Reset DMA0 */ MXC_SYS_RESET0_SOFT = MXC_F_GCR_RST0_SOFT_POS, /**< Soft reset */ MXC_SYS_RESET0_PERIPH = MXC_F_GCR_RST0_PERIPH_POS, /**< Peripheral reset */ MXC_SYS_RESET0_SYS = MXC_F_GCR_RST0_SYS_POS, /**< System reset */ /* RESET1 Below this line we add 32 to separate RESET0 and RESET1 */ - MXC_SYS_RESET1_I2C1 = (MXC_F_GCR_RST1_I2C1_POS + 32), /**< Reset I2C1 */ - MXC_SYS_RESET1_PT = (MXC_F_GCR_RST1_PT_POS + 32), /**< Reset PT */ - MXC_SYS_RESET1_OWM = (MXC_F_GCR_RST1_OWM_POS + 32), /**< Reset OWM */ MXC_SYS_RESET1_CRC = (MXC_F_GCR_RST1_CRC_POS + 32), /**< Reset CRC */ MXC_SYS_RESET1_AES = (MXC_F_GCR_RST1_AES_POS + 32), /**< Reset AES */ - MXC_SYS_RESET1_SMPHR = (MXC_F_GCR_RST1_SMPHR_POS + 32), /**< Reset SMPHR */ - MXC_SYS_RESET1_I2C2 = (MXC_F_GCR_RST1_I2C2_POS + 32), /**< Reset I2C2 */ - MXC_SYS_RESET1_I2S = (MXC_F_GCR_RST1_I2S_POS + 32), /**< Reset I2S*/ - // MXC_SYS_RESET1_BTLE = (MXC_F_GCR_RST1_BTLE_POS + 32), /**< Reset BTLE*/ - MXC_SYS_RESET1_DVS = (MXC_F_GCR_RST1_DVS_POS + 32), /**< Reset DVS */ - MXC_SYS_RESET1_SIMO = (MXC_F_GCR_RST1_SIMO_POS + 32), /**< Reset SIMO */ - MXC_SYS_RESET1_SPI0 = (MXC_F_GCR_RST1_SPI0_POS + 32), /**< Reset SPI0 */ - MXC_SYS_RESET1_CPU1 = (MXC_F_GCR_RST1_CPU1_POS + 32), /**< Reset CPU1 */ - /* LPGCR RESET Below this line we add 64 to separate LPGCR and GCR */ - MXC_SYS_RESET_GPIO2 = (MXC_F_LPGCR_RST_GPIO2_POS + 64), /**< Reset GPIO2 */ - MXC_SYS_RESET_WDT1 = (MXC_F_LPGCR_RST_WDT1_POS + 64), /**< Reset WDT1 */ - MXC_SYS_RESET_TMR4 = (MXC_F_LPGCR_RST_TMR4_POS + 64), /**< Reset TMR4 */ - MXC_SYS_RESET_TMR5 = (MXC_F_LPGCR_RST_TMR5_POS + 64), /**< Reset TMR5 */ - MXC_SYS_RESET_UART3 = (MXC_F_LPGCR_RST_UART3_POS + 64), /**< Reset UART3 */ - MXC_SYS_RESET_LPCOMP = (MXC_F_LPGCR_RST_LPCOMP_POS + 64), /**< Reset LPCOMP */ } mxc_sys_reset_t; /** @brief System clock disable enumeration. Used in MXC_SYS_ClockDisable and MXC_SYS_ClockEnable functions */ typedef enum { MXC_SYS_PERIPH_CLOCK_GPIO0 = - MXC_F_GCR_PCLKDIS0_GPIO0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_GPIO0 clock */ - MXC_SYS_PERIPH_CLOCK_GPIO1 = - MXC_F_GCR_PCLKDIS0_GPIO1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_GPIO1 clock */ - MXC_SYS_PERIPH_CLOCK_DMA = - MXC_F_GCR_PCLKDIS0_DMA_POS, /**< Disable MXC_F_GCR_PCLKDIS0_DMA clock */ - MXC_SYS_PERIPH_CLOCK_SPI1 = - MXC_F_GCR_PCLKDIS0_SPI1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_SPI1 clock */ - MXC_SYS_PERIPH_CLOCK_UART0 = - MXC_F_GCR_PCLKDIS0_UART0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART0 clock */ - MXC_SYS_PERIPH_CLOCK_UART1 = - MXC_F_GCR_PCLKDIS0_UART1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_UART1 clock */ - MXC_SYS_PERIPH_CLOCK_I2C0 = - MXC_F_GCR_PCLKDIS0_I2C0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C0 clock */ + MXC_F_GCR_PCLKDIS0_GPIO0_POS, /**< Disable GPIO0 clock */ + MXC_SYS_PERIPH_CLOCK_DMA0 = + MXC_F_GCR_PCLKDIS0_DMA0_POS, /**< Disable DMA0 clock */ + MXC_SYS_PERIPH_CLOCK_SPI = + MXC_F_GCR_PCLKDIS0_SPI_POS, /**< Disable SPI clock */ + MXC_SYS_PERIPH_CLOCK_UART = + MXC_F_GCR_PCLKDIS0_UART_POS, /**< Disable UART0 clock */ + MXC_SYS_PERIPH_CLOCK_I3C = + MXC_F_GCR_PCLKDIS0_I3C_POS, /**< Disable I2C/I3C clock */ MXC_SYS_PERIPH_CLOCK_TMR0 = - MXC_F_GCR_PCLKDIS0_TMR0_POS, /**< Disable MXC_F_GCR_PCLKDIS0_TMR0 clock */ + MXC_F_GCR_PCLKDIS0_TMR0_POS, /**< Disable TMR0 clock */ MXC_SYS_PERIPH_CLOCK_TMR1 = - MXC_F_GCR_PCLKDIS0_TMR1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_TMR1 clock */ + MXC_F_GCR_PCLKDIS0_TMR1_POS, /**< Disable TMR1 clock */ MXC_SYS_PERIPH_CLOCK_TMR2 = - MXC_F_GCR_PCLKDIS0_TMR2_POS, /**< Disable MXC_F_GCR_PCLKDIS0_TMR2 clock */ + MXC_F_GCR_PCLKDIS0_TMR2_POS, /**< Disable TMR2 clock */ MXC_SYS_PERIPH_CLOCK_TMR3 = - MXC_F_GCR_PCLKDIS0_TMR3_POS, /**< Disable MXC_F_GCR_PCLKDIS0_T3 clock */ - MXC_SYS_PERIPH_CLOCK_ADC = - MXC_F_GCR_PCLKDIS0_ADC_POS, /**< Disable MXC_F_GCR_PCLKDIS0_ADC clock */ - MXC_SYS_PERIPH_CLOCK_CNN = - MXC_F_GCR_PCLKDIS0_CNN_POS, /**< Disable MXC_F_GCR_PCLKDIS0_CNN clock */ - MXC_SYS_PERIPH_CLOCK_I2C1 = - MXC_F_GCR_PCLKDIS0_I2C1_POS, /**< Disable MXC_F_GCR_PCLKDIS0_I2C1 clock */ - MXC_SYS_PERIPH_CLOCK_PT = MXC_F_GCR_PCLKDIS0_PT_POS, /**< Disable MXC_F_GCR_PCLKDIS0_PT clock */ + MXC_F_GCR_PCLKDIS0_TMR3_POS, /**< Disable TMR3 clock */ + MXC_SYS_PERIPH_CLOCK_TMR4 = + MXC_F_GCR_PCLKDIS0_TMR4_POS, /**< Disable TMR4 clock */ + MXC_SYS_PERIPH_CLOCK_TMR5 = + MXC_F_GCR_PCLKDIS0_TMR5_POS, /**< Disable TMR4 clock */ /* PCLKDIS1 Below this line we add 32 to separate PCLKDIS0 and PCLKDIS1 */ - MXC_SYS_PERIPH_CLOCK_UART2 = - (MXC_F_GCR_PCLKDIS1_UART2_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_UART2 clock */ MXC_SYS_PERIPH_CLOCK_TRNG = - (MXC_F_GCR_PCLKDIS1_TRNG_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_TRNG clock */ - MXC_SYS_PERIPH_CLOCK_SMPHR = - (MXC_F_GCR_PCLKDIS1_SMPHR_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_SMPHR clock */ - MXC_SYS_PERIPH_CLOCK_OWIRE = - (MXC_F_GCR_PCLKDIS1_OWM_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_OWM clock */ + (MXC_F_GCR_PCLKDIS1_TRNG_POS + 32), /**< Disable TRNG clock */ + // MXC_SYS_PERIPH_CLOCK_SMPHR = + // (MXC_F_GCR_PCLKDIS1_SMPHR_POS + 32), /**< Disable SMPHR clock */ MXC_SYS_PERIPH_CLOCK_CRC = - (MXC_F_GCR_PCLKDIS1_CRC_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_CRC clock */ + (MXC_F_GCR_PCLKDIS1_CRC_POS + 32), /**< Disable CRC clock */ MXC_SYS_PERIPH_CLOCK_AES = - (MXC_F_GCR_PCLKDIS1_AES_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_AES clock */ - MXC_SYS_PERIPH_CLOCK_I2S = - (MXC_F_GCR_PCLKDIS1_I2S_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_I2S clock */ - MXC_SYS_PERIPH_CLOCK_SPI0 = - (MXC_F_GCR_PCLKDIS1_SPI0_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_SPI0 clock */ - MXC_SYS_PERIPH_CLOCK_I2C2 = - (MXC_F_GCR_PCLKDIS1_I2C2_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_I2C2 clock */ - MXC_SYS_PERIPH_CLOCK_WDT0 = - (MXC_F_GCR_PCLKDIS1_WDT0_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_WDT0 clock */ - MXC_SYS_PERIPH_CLOCK_CPU1 = - (MXC_F_GCR_PCLKDIS1_CPU1_POS + 32), /**< Disable MXC_F_GCR_PCLKDIS1_CPU1 clock */ - /* LPGCR PCLKDIS Below this line we add 64 to seperate GCR and LPGCR registers */ - MXC_SYS_PERIPH_CLOCK_GPIO2 = - (MXC_F_LPGCR_PCLKDIS_GPIO2_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_GPIO2 clock */ - MXC_SYS_PERIPH_CLOCK_WDT1 = - (MXC_F_LPGCR_PCLKDIS_WDT1_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_WDT1 clock */ - MXC_SYS_PERIPH_CLOCK_TMR4 = - (MXC_F_LPGCR_PCLKDIS_TMR4_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_TMR4 clock */ - MXC_SYS_PERIPH_CLOCK_TMR5 = - (MXC_F_LPGCR_PCLKDIS_TMR5_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_TMR5 clock */ - MXC_SYS_PERIPH_CLOCK_UART3 = - (MXC_F_LPGCR_PCLKDIS_UART3_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_UART3 clock */ - MXC_SYS_PERIPH_CLOCK_LPCOMP = - (MXC_F_LPGCR_PCLKDIS_LPCOMP_POS + 64), /**< Disable MXC_F_LPGCR_PCLKDIS_LPCOMP clock */ + (MXC_F_GCR_PCLKDIS1_AES_POS + 32), /**< Disable AES clock */ + // MXC_SYS_PERIPH_CLOCK_SPI = + // (MXC_F_GCR_PCLKDIS1_SPI_POS + 32), /**< Disable SPI clock */ + // TODO(JC): The SPI clock disable is defined in both PCLKDIS0 and PCLKDIS1 + MXC_SYS_PERIPH_CLOCK_WDT = + (MXC_F_GCR_PCLKDIS1_WDT_POS), /**< Disable WDT clock */ } mxc_sys_periph_clock_t; /** @brief Enumeration to select System Clock source */ @@ -167,8 +118,9 @@ typedef enum { MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO, /**< Select the Internal Nanoring Oscillator (INRO) */ MXC_SYS_CLOCK_ERTCO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO, /**< Select the External RTC Crystal Oscillator */ - MXC_SYS_CLOCK_EXTCLK = - MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK /**< Use the external system clock input */ + // MXC_SYS_CLOCK_EXTCLK = + // MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK /**< Use the external system clock input */ + // TODO(JC): ^^^ EXTCLK select is missing from gcr_regs.h (should be 0x7) } mxc_sys_system_clock_t; /** @brief Enumeration to set the System Clock divider */ From bd8b0fdcab48776b639e10275596fd9a495df0f7 Mon Sep 17 00:00:00 2001 From: Jake Carter Date: Tue, 30 Apr 2024 19:22:31 -0600 Subject: [PATCH 31/93] Add basic system implementation --- .../Device/Maxim/MAX32657/Include/max32657.h | 9 ++ .../Maxim/MAX32657/Source/system_max32657.c | 132 ++++++++++++++++++ 2 files changed, 141 insertions(+) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h index da1a488d282..35efa6c2eb9 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h @@ -31,6 +31,7 @@ #define MXC_NUMCORES 1 #include +#include "system_max32657.h" #ifndef FALSE #define FALSE (0) @@ -768,4 +769,12 @@ We may want to handle GET_IRQ better... #define MXC_SETFIELD(reg, mask, setting) ((reg) = ((reg) & ~(mask)) | ((setting) & (mask))) +/******************************************************************************/ +/* CPACR Definitions */ +/* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm33.h */ +#define SCB_CPACR_CP10_Pos 20 /*!< SCB CPACR: Coprocessor 10 Position */ +#define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos) /*!< SCB CPACR: Coprocessor 10 Mask */ +#define SCB_CPACR_CP11_Pos 22 /*!< SCB CPACR: Coprocessor 11 Position */ +#define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /*!< SCB CPACR: Coprocessor 11 Mask */ + #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX326657_INCLUDE_MAX32657_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c index 5b3c0874344..51078ce7a50 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c @@ -17,3 +17,135 @@ ******************************************************************************/ // TODO(ME30): System implementation + +#include "system_max32657.h" +#include "max32657.h" +#include "mxc_sys.h" +#include "icc.h" + +extern void (*const __isr_vector[])(void); +uint32_t SystemCoreClock = IPO_FREQ; // Part defaults to IPO on startup + +/* +The libc implementation from GCC 11+ depends on _getpid and _kill in some places. +There is no concept of processes/PIDs in the baremetal PeriphDrivers, therefore +we implement stub functions that return an error code to resolve linker warnings. +*/ +int _getpid(void) +{ + return E_NOT_SUPPORTED; +} + +int _kill(void) +{ + return E_NOT_SUPPORTED; +} + +__weak void SystemCoreClockUpdate(void) +{ + uint32_t base_freq, div, clk_src; + + // Get the clock source and frequency + clk_src = (MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_SEL); + switch (clk_src) { + case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO: + base_freq = IPO_FREQ; + break; + case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERFO: + base_freq = ERFO_FREQ; + break; + case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_INRO: + base_freq = INRO_FREQ; + break; + case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IBRO: + base_freq = IBRO_FREQ; + break; + case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO: + base_freq = ERTCO_FREQ; + break; + // case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK: + // base_freq = EXTCLK_FREQ; + // break; + // TODO(JC): ^^^ Uncomment when EXTCLK register definition is added + default: + // Codes 001 and 111 are reserved. + // This code should never execute, however, initialize to safe value. + base_freq = HIRC_FREQ; + break; + } + + // Get the clock divider + div = (MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_DIV) >> MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS; + + SystemCoreClock = base_freq >> div; +} + +/* This function is called before C runtime initialization and can be + * implemented by the application for early initializations. If a value other + * than '0' is returned, the C runtime initialization will be skipped. + * + * You may over-ride this function in your program by defining a custom + * PreInit(), but care should be taken to reproduce the initialization steps + * or a non-functional system may result. + */ +__weak int PreInit(void) +{ + // TODO(JC): No SIMO on this device, confirm nothing needs to be done here. + + return 0; +} + +/* This function is called before the Board_Init function. This weak + * implementation does nothing, but you may over-ride this function in your + * program if you want to configure the state of all pins prior to the + * application running. This is useful when using external tools (like a + * Pin Mux configuration tool) that generate code to initialize the pins. + */ +__weak void PinInit(void) +{ + /* Do nothing */ +} + +/* This function can be implemented by the application to initialize the board */ +__weak int Board_Init(void) +{ + /* Do nothing */ + return 0; +} + +/* This function is called just before control is transferred to main(). + * + * You may over-ride this function in your program by defining a custom + * SystemInit(), but care should be taken to reproduce the initialization + * steps or a non-functional system may result. + */ +__weak void SystemInit(void) +{ + /* Configure the interrupt controller to use the application vector table in */ + /* the application space */ +#if defined(__CC_ARM) || defined(__GNUC__) + /* IAR sets the VTOR pointer incorrectly and causes stack corruption */ + SCB->VTOR = (uint32_t)__isr_vector; +#endif /* __CC_ARM || __GNUC__ */ + + /* Make sure interrupts are enabled. */ + __enable_irq(); + + /* Enable instruction cache */ + MXC_ICC_Enable(MXC_ICC); + + /* Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11 */ + /* Grant full access, per "Table B3-24 CPACR bit assignments". */ + /* DDI0403D "ARMv7-M Architecture Reference Manual" */ + SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk; + __DSB(); + __ISB(); + + /* Change system clock source to the main high-speed clock */ + MXC_SYS_Clock_Select(MXC_SYS_CLOCK_IPO); + MXC_SYS_SetClockDiv(MXC_SYS_CLOCK_DIV_1); + SystemCoreClockUpdate(); + + PinInit(); + Board_Init(); +} \ No newline at end of file From e84319a67fad7e72792b8bdea4e90cb471d723e7 Mon Sep 17 00:00:00 2001 From: Jake Carter Date: Tue, 30 Apr 2024 19:28:04 -0600 Subject: [PATCH 32/93] Add MAX32657 Hello World --- Examples/MAX32657/Hello_World/.cproject | 81 ++++ Examples/MAX32657/Hello_World/.project | 26 ++ .../.settings/language.settings.xml | 15 + .../org.eclipse.cdt.codan.core.prefs | 93 +++++ .../.settings/org.eclipse.cdt.core.prefs | 15 + .../MAX32657/Hello_World/.vscode/README.md | 47 +++ .../Hello_World/.vscode/c_cpp_properties.json | 53 +++ .../MAX32657/Hello_World/.vscode/flash.gdb | 17 + .../MAX32657/Hello_World/.vscode/launch.json | 133 ++++++ .../Hello_World/.vscode/settings.json | 80 ++++ .../MAX32657/Hello_World/.vscode/tasks.json | 115 ++++++ .../MAX32657/Hello_World/Hello_World.launch | 62 +++ Examples/MAX32657/Hello_World/Makefile | 382 ++++++++++++++++++ Examples/MAX32657/Hello_World/README.md | 42 ++ Examples/MAX32657/Hello_World/main.c | 56 +++ Examples/MAX32657/Hello_World/project.mk | 10 + 16 files changed, 1227 insertions(+) create mode 100644 Examples/MAX32657/Hello_World/.cproject create mode 100644 Examples/MAX32657/Hello_World/.project create mode 100644 Examples/MAX32657/Hello_World/.settings/language.settings.xml create mode 100644 Examples/MAX32657/Hello_World/.settings/org.eclipse.cdt.codan.core.prefs create mode 100644 Examples/MAX32657/Hello_World/.settings/org.eclipse.cdt.core.prefs create mode 100755 Examples/MAX32657/Hello_World/.vscode/README.md create mode 100755 Examples/MAX32657/Hello_World/.vscode/c_cpp_properties.json create mode 100755 Examples/MAX32657/Hello_World/.vscode/flash.gdb create mode 100755 Examples/MAX32657/Hello_World/.vscode/launch.json create mode 100755 Examples/MAX32657/Hello_World/.vscode/settings.json create mode 100755 Examples/MAX32657/Hello_World/.vscode/tasks.json create mode 100644 Examples/MAX32657/Hello_World/Hello_World.launch create mode 100644 Examples/MAX32657/Hello_World/Makefile create mode 100644 Examples/MAX32657/Hello_World/README.md create mode 100644 Examples/MAX32657/Hello_World/main.c create mode 100644 Examples/MAX32657/Hello_World/project.mk diff --git a/Examples/MAX32657/Hello_World/.cproject b/Examples/MAX32657/Hello_World/.cproject new file mode 100644 index 00000000000..3a8a4199e81 --- /dev/null +++ b/Examples/MAX32657/Hello_World/.cproject @@ -0,0 +1,81 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Examples/MAX32657/Hello_World/.project b/Examples/MAX32657/Hello_World/.project new file mode 100644 index 00000000000..d21c0a970b7 --- /dev/null +++ b/Examples/MAX32657/Hello_World/.project @@ -0,0 +1,26 @@ + + + Hello_World + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + diff --git a/Examples/MAX32657/Hello_World/.settings/language.settings.xml b/Examples/MAX32657/Hello_World/.settings/language.settings.xml new file mode 100644 index 00000000000..d32717b6f37 --- /dev/null +++ b/Examples/MAX32657/Hello_World/.settings/language.settings.xml @@ -0,0 +1,15 @@ + + + + + + + + + + + + + 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+org.eclipse.cdt.codan.internal.checkers.UnusedFunctionDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused function declaration\\")",macro\=>true} +org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem=Warning +org.eclipse.cdt.codan.internal.checkers.UnusedStaticFunctionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused static function\\")",macro\=>true} +org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem=Warning +org.eclipse.cdt.codan.internal.checkers.UnusedVariableDeclarationProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Unused variable declaration in file scope\\")",macro\=>true,exceptions\=>("@(\#)","$Id")} +org.eclipse.cdt.codan.internal.checkers.UsingInHeaderProblem=-Warning +org.eclipse.cdt.codan.internal.checkers.UsingInHeaderProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Using directive in header\\")"} +org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem=Error +org.eclipse.cdt.codan.internal.checkers.VariableResolutionProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Symbol is not resolved\\")"} +org.eclipse.cdt.codan.internal.checkers.VirtualMethodCallProblem=-Error +org.eclipse.cdt.codan.internal.checkers.VirtualMethodCallProblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>true,RUN_ON_INC_BUILD\=>true,RUN_ON_FILE_OPEN\=>false,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>"@suppress(\\"Virtual method call in constructor/destructor\\")"} +org.eclipse.cdt.qt.core.qtproblem=Warning +org.eclipse.cdt.qt.core.qtproblem.params={launchModes\=>{RUN_ON_FULL_BUILD\=>false,RUN_ON_INC_BUILD\=>false,RUN_ON_FILE_OPEN\=>true,RUN_ON_FILE_SAVE\=>false,RUN_AS_YOU_TYPE\=>true,RUN_ON_DEMAND\=>true},suppression_comment\=>null} diff --git a/Examples/MAX32657/Hello_World/.settings/org.eclipse.cdt.core.prefs b/Examples/MAX32657/Hello_World/.settings/org.eclipse.cdt.core.prefs new file mode 100644 index 00000000000..7634acd5b10 --- /dev/null +++ b/Examples/MAX32657/Hello_World/.settings/org.eclipse.cdt.core.prefs @@ -0,0 +1,15 @@ +eclipse.preferences.version=1 +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/BOARD/delimiter=; +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/BOARD/operation=append +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/BOARD/value=EvKit_V1 +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/GCC_PREFIX/delimiter=; +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/GCC_PREFIX/operation=replace +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/GCC_PREFIX/value=arm-none-eabi- +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/PROJECT/delimiter=; +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/PROJECT/operation=append +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/PROJECT/value=Hello_World +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/TARGET/delimiter=; +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/TARGET/operation=append +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/TARGET/value=MAX32657 +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/append=true +environment/project/cdt.managedbuild.toolchain.gnu.cross.base.1028364529/appendContributed=true diff --git a/Examples/MAX32657/Hello_World/.vscode/README.md b/Examples/MAX32657/Hello_World/.vscode/README.md new file mode 100755 index 00000000000..5b355bd51c9 --- /dev/null +++ b/Examples/MAX32657/Hello_World/.vscode/README.md @@ -0,0 +1,47 @@ +# VSCode-Maxim + +_(If you're viewing this document from within Visual Studio Code you can press `CTRL+SHIFT+V` to open a Markdown preview window.)_ + +## Quick Links + +* [MSDK User Guide](https://analogdevicesinc.github.io/msdk/USERGUIDE/) +* [VSCode-Maxim Github](https://github.com/analogdevicesinc/VSCode-Maxim) + +## Introduction + +VSCode-Maxim is a set of [Visual Studio Code](https://code.visualstudio.com/) project configurations and utilities for enabling embedded development for [Analog Device's MSDK](https://github.com/analogdevicesinc/msdk) and the [MAX32xxx/MAX78xxx microcontrollers](https://www.analog.com/en/product-category/microcontrollers.html). + +The following features are supported: + +* Code editing with intellisense down to the register level +* Code compilation with the ability to easily re-target a project for different microcontrollers and boards +* Flashing programs +* GUI and command-line debugging + +## Dependencies + +* [Visual Studio Code](https://code.visualstudio.com/) + * [C/C++ VSCode Extension](https://marketplace.visualstudio.com/items?itemName=ms-vscode.cpptools) + * [Cortex-Debug Extension](https://marketplace.visualstudio.com/items?itemName=marus25.cortex-debug) +* [Analog Devices MSDK](https://analogdevicesinc.github.io/msdk/) + +## Installation + +Install the MSDK, then set `"MAXIM_PATH"` in your _user_ VS Code settings. + +See [Getting Started with Visual Studio Code](https://analogdevicesinc.github.io/msdk/USERGUIDE/#getting-started-with-visual-studio-code) in the MSDK User Guide for detailed instructions. + +## Usage + +See the [MSDK User Guide](https://analogdevicesinc.github.io/msdk/USERGUIDE/#visual-studio-code) for detailed usage info. + +## Issue Tracker + +Bug reports, feature requests, and contributions are welcome via the [issues](https://github.com/analogdevicesinc/VSCode-Maxim/issues) tracker on Github. + +New issues should contain _at minimum_ the following information: + +* Visual Studio Code version #s (see `Help -> About`) +* C/C++ Extension version # +* Target microcontroller and evaluation platform +* The projects `.vscode` folder and `Makefile` (where applicable). Standard compression formats such as `.zip`, `.rar`, `.tar.gz`, etc. are all acceptable. diff --git a/Examples/MAX32657/Hello_World/.vscode/c_cpp_properties.json b/Examples/MAX32657/Hello_World/.vscode/c_cpp_properties.json new file mode 100755 index 00000000000..dfbed47b581 --- /dev/null +++ b/Examples/MAX32657/Hello_World/.vscode/c_cpp_properties.json @@ -0,0 +1,53 @@ +{ + "configurations": [ + { + "name": "Win32", + "includePath": [ + "${default}" + ], + "defines": [ + "${default}" + ], + "intelliSenseMode": "gcc-arm", + "compilerPath": "${config:ARM_GCC_path}/bin/arm-none-eabi-gcc.exe", + "browse": { + "path": [ + "${default}" + ] + } + }, + { + "name": "Linux", + "includePath": [ + "${default}" + ], + "defines": [ + "${default}" + ], + "intelliSenseMode": "gcc-arm", + "compilerPath": "${config:ARM_GCC_path}/bin/arm-none-eabi-gcc", + "browse": { + "path": [ + "${default}" + ] + } + }, + { + "name": "Mac", + "includePath": [ + "${default}" + ], + "defines": [ + "${default}" + ], + "intelliSenseMode": "gcc-arm", + "compilerPath": "${config:ARM_GCC_path}/bin/arm-none-eabi-gcc", + "browse": { + "path": [ + "${default}" + ] + } + } + ], + "version": 4 +} \ No newline at end of file diff --git a/Examples/MAX32657/Hello_World/.vscode/flash.gdb b/Examples/MAX32657/Hello_World/.vscode/flash.gdb new file mode 100755 index 00000000000..8f22801a47d --- /dev/null +++ b/Examples/MAX32657/Hello_World/.vscode/flash.gdb @@ -0,0 +1,17 @@ +define flash_m4 + set architecture armv7e-m + set remotetimeout 10 + target remote | openocd -c "gdb_port pipe;log_output flash.log" -s $arg0/scripts -f interface/$arg1 -f target/$arg2 -c "init; reset halt" + load + compare-sections + monitor reset halt +end + +define flash_m4_run + set architecture armv7e-m + set remotetimeout 10 + target remote | openocd -c "gdb_port pipe;log_output flash.log" -s $arg0/scripts -f interface/$arg1 -f target/$arg2 -c "init; reset halt" + load + compare-sections + monitor resume +end diff --git a/Examples/MAX32657/Hello_World/.vscode/launch.json b/Examples/MAX32657/Hello_World/.vscode/launch.json new file mode 100755 index 00000000000..01fe5199048 --- /dev/null +++ b/Examples/MAX32657/Hello_World/.vscode/launch.json @@ -0,0 +1,133 @@ +{ + "configurations": [ + { + "name": "Debug Arm (Cortex-debug)", + "cwd":"${workspaceRoot}", + "executable": "${workspaceFolder}/build/${config:program_file}", + "loadFiles": ["${workspaceFolder}/build/${config:program_file}"], + "symbolFiles": [{ + "file": "${workspaceFolder}/build/${config:symbol_file}" + }], + "request": "launch", + "type": "cortex-debug", + "servertype": "openocd", + "linux": { + "gdbPath": "${config:ARM_GCC_path}/bin/arm-none-eabi-gdb", + "serverpath": "${config:OCD_path}/openocd", + }, + "windows": { + "gdbPath": "${config:ARM_GCC_path}/bin/arm-none-eabi-gdb.exe", + "serverpath": "${config:OCD_path}/openocd.exe", + }, + "osx": { + "gdbPath": "${config:ARM_GCC_path}/bin/arm-none-eabi-gdb", + "serverpath": "${config:OCD_path}/openocd", + }, + "searchDir": ["${config:OCD_path}/scripts"], + "configFiles": ["interface/${config:M4_OCD_interface_file}", "target/${config:M4_OCD_target_file}"], + "interface": "swd", + "runToEntryPoint": "main", + "svdFile": "${config:MAXIM_PATH}/Libraries/CMSIS/Device/Maxim/${config:target}/Include/${config:target}.svd" + }, + { + "name": "GDB (Arm M4)", + "type": "cppdbg", + "request": "launch", + "program": "${workspaceFolder}/build/${config:program_file}", + "args": [], + "stopAtEntry": true, + "cwd": "${workspaceFolder}", + "environment": [], + "externalConsole": false, + "MIMode": "gdb", + "linux": { + "miDebuggerPath": "${config:ARM_GCC_path}/bin/arm-none-eabi-gdb", + "debugServerPath": "${config:OCD_path}/openocd", + }, + "windows": { + "miDebuggerPath": "${config:ARM_GCC_path}/bin/arm-none-eabi-gdb.exe", + "debugServerPath": "${config:OCD_path}/openocd.exe", + }, + "osx": { + "miDebuggerPath": "${config:ARM_GCC_path}/bin/arm-none-eabi-gdb", + "debugServerPath": "${config:OCD_path}/bin/openocd", + }, + "logging": { + "exceptions": true, + "trace": false, + "traceResponse": false, + "engineLogging": false + }, + "miDebuggerServerAddress": "localhost:3333", + "debugServerArgs": "-s ${config:OCD_path}/scripts -f interface/${config:M4_OCD_interface_file} -f target/${config:M4_OCD_target_file} -c \"init; reset halt\"", + "serverStarted": "Info : Listening on port 3333 for gdb connections", + "filterStderr": true, + "targetArchitecture": "arm", + "customLaunchSetupCommands": [ + {"text":"-list-features"} + ], + "setupCommands": [ + { "text":"set logging overwrite on"}, + { "text":"set logging file debug-arm.log"}, + { "text":"set logging on"}, + { "text":"cd ${workspaceFolder}" }, + { "text":"exec-file build/${config:program_file}" }, + { "text":"symbol-file build/${config:symbol_file}" }, + { "text":"target remote localhost:3333" }, + { "text":"monitor reset halt" }, + { "text":"set $pc=Reset_Handler"}, + { "text":"b main" } + ] + }, + { + "name": "GDB (RISC-V)", + "type": "cppdbg", + "request": "launch", + "program": "${workspaceFolder}/buildrv/${config:program_file}", + "args": [], + "stopAtEntry": false, + "cwd": "${workspaceFolder}", + "environment": [], + "externalConsole": false, + "MIMode": "gdb", + "linux": { + "miDebuggerPath": "${config:xPack_GCC_path}/bin/riscv-none-elf-gdb", + "debugServerPath": "${config:OCD_path}/openocd", + }, + "windows": { + "miDebuggerPath": "${config:xPack_GCC_path}/bin/riscv-none-elf-gdb.exe", + "debugServerPath": "${config:OCD_path}/openocd.exe", + }, + "osx": { + "miDebuggerPath": "${config:xPack_GCC_path}/bin/riscv-none-elf-gdb", + "debugServerPath": "${config:OCD_path}/bin/openocd", + }, + "logging": { + "exceptions": true, + "trace": false, + "traceResponse": false, + "engineLogging": false + }, + "miDebuggerServerAddress": "localhost:3334", + "debugServerArgs": "-c \"gdb_port 3334\" -s ${config:OCD_path}/scripts -f interface/${config:RV_OCD_interface_file} -f target/${config:RV_OCD_target_file}", + "serverStarted": "Info : Listening on port 3334 for gdb connections", + "filterStderr": true, + "customLaunchSetupCommands": [ + {"text":"-list-features"} + ], + "targetArchitecture": "arm", + "setupCommands": [ + { "text":"set logging overwrite on"}, + { "text":"set logging file debug-riscv.log"}, + { "text":"set logging on"}, + { "text":"cd ${workspaceFolder}" }, + { "text": "set architecture riscv:rv32", "ignoreFailures": false }, + { "text":"exec-file build/${config:program_file}", "ignoreFailures": false }, + { "text":"symbol-file buildrv/${config:symbol_file}", "ignoreFailures": false }, + { "text":"target remote localhost:3334" }, + { "text":"b main" }, + { "text": "set $pc=Reset_Handler","ignoreFailures": false } + ] + } + ] +} diff --git a/Examples/MAX32657/Hello_World/.vscode/settings.json b/Examples/MAX32657/Hello_World/.vscode/settings.json new file mode 100755 index 00000000000..66194c6a77c --- /dev/null +++ b/Examples/MAX32657/Hello_World/.vscode/settings.json @@ -0,0 +1,80 @@ +{ + "terminal.integrated.env.windows": { + "Path":"${config:OCD_path};${config:ARM_GCC_path}/bin;${config:xPack_GCC_path}/bin;${config:MSYS_path}/usr/bin;${config:Make_path};${env:PATH}", + "MAXIM_PATH":"${config:MAXIM_PATH}" + }, + "terminal.integrated.defaultProfile.windows": "Command Prompt", + + "terminal.integrated.env.linux": { + "PATH":"${config:OCD_path}:${config:ARM_GCC_path}/bin:${config:xPack_GCC_path}/bin:${config:Make_path}:${env:PATH}", + "MAXIM_PATH":"${config:MAXIM_PATH}" + }, + "terminal.integrated.env.osx": { + "PATH":"${config:OCD_path}/bin:${config:ARM_GCC_path}/bin:${config:xPack_GCC_path}/bin:${config:Make_path}:${env:PATH}", + "MAXIM_PATH":"${config:MAXIM_PATH}" + }, + + "target":"MAX32657", + "board":"EvKit_V1", + + "project_name":"${workspaceFolderBasename}", + + "program_file":"${config:project_name}.elf", + "symbol_file":"${config:program_file}", + + "M4_OCD_interface_file":"cmsis-dap.cfg", + "M4_OCD_target_file":"max32657.cfg", + "RV_OCD_interface_file":"ftdi/olimex-arm-usb-ocd-h.cfg", + "RV_OCD_target_file":"${config:target}_riscv.cfg", + + "v_Arm_GCC":"10.3", + "v_xPack_GCC":"12.2.0-3.1", + + "OCD_path":"${config:MAXIM_PATH}/Tools/OpenOCD", + "ARM_GCC_path":"${config:MAXIM_PATH}/Tools/GNUTools/${config:v_Arm_GCC}", + "xPack_GCC_path":"${config:MAXIM_PATH}/Tools/xPack/riscv-none-elf-gcc/${config:v_xPack_GCC}", + "Make_path":"${config:MAXIM_PATH}/Tools/GNUTools/Make", + "MSYS_path":"${config:MAXIM_PATH}/Tools/MSYS2", + + "C_Cpp.default.includePath": [ + "${workspaceFolder}", + "${workspaceFolder}/**", + "${config:MAXIM_PATH}/Libraries/Boards/${config:target}/Include", + "${config:MAXIM_PATH}/Libraries/Boards/${config:target}/${config:board}/Include", + "${config:MAXIM_PATH}/Libraries/CMSIS/Device/Maxim/${config:target}/Include", + "${config:MAXIM_PATH}/Libraries/CMSIS/5.9.0/Core/Include", + "${config:MAXIM_PATH}/Libraries/CMSIS/Include", + "${config:ARM_GCC_path}/arm-none-eabi/include", + "${config:ARM_GCC_path}/lib/gcc/arm-none-eabi/${config:v_Arm_GCC}/include", + "${config:MAXIM_PATH}/Libraries/PeriphDrivers/Include/${config:target}", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/Camera", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/Display", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/Display/fonts", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/ExtMemory", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/LED", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/PMIC", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/PushButton", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/Touchscreen" + ], + "C_Cpp.default.browse.path": [ + "${workspaceFolder}", + "${config:MAXIM_PATH}/Libraries/Boards/${config:target}/Source", + "${config:MAXIM_PATH}/Libraries/Boards/${config:target}/${config:board}/Source", + "${config:MAXIM_PATH}/Libraries/PeriphDrivers/Source", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/Camera", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/Display", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/Display/fonts", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/LED", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/PMIC", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/PushButton", + "${config:MAXIM_PATH}/Libraries/MiscDrivers/Touchscreen", + "${config:MAXIM_PATH}/Libraries/MiscDrivers" + ], + "C_Cpp.default.defines": [ + + ], + "C_Cpp.default.forcedInclude": [ + "${workspaceFolder}/build/project_defines.h" + ] +} + diff --git a/Examples/MAX32657/Hello_World/.vscode/tasks.json b/Examples/MAX32657/Hello_World/.vscode/tasks.json new file mode 100755 index 00000000000..e95445e2b3e --- /dev/null +++ b/Examples/MAX32657/Hello_World/.vscode/tasks.json @@ -0,0 +1,115 @@ +{ + "version": "2.0.0", + "tasks": [ + { + "label": "build", + "type": "shell", + "command": "make -r -j 8 --output-sync=target --no-print-directory TARGET=${config:target} BOARD=${config:board} MAXIM_PATH=${config:MAXIM_PATH} MAKE=make PROJECT=${config:project_name}", + "osx":{ + "command": "source ~/.zshrc && make -r -j 8 --output-sync=target --no-print-directory TARGET=${config:target} BOARD=${config:board} MAXIM_PATH=${config:MAXIM_PATH} MAKE=make PROJECT=${config:project_name}" + }, + "group": "build", + "problemMatcher": [] + }, + { + "label": "clean", + "type": "shell", + "command": "make -j 8 clean --output-sync=target --no-print-directory TARGET=${config:target} BOARD=${config:board} MAXIM_PATH=${config:MAXIM_PATH} MAKE=make PROJECT=${config:project_name}", + "osx":{ + "command": "source ~/.zshrc && make -j 8 clean --output-sync=target --no-print-directory TARGET=${config:target} BOARD=${config:board} MAXIM_PATH=${config:MAXIM_PATH} MAKE=make PROJECT=${config:project_name}" + }, + "group": "build", + "problemMatcher": [] + }, + { + "label": "clean-periph", + "type": "shell", + "command": "make -j 8 distclean --output-sync=target --no-print-directory TARGET=${config:target} BOARD=${config:board} MAXIM_PATH=${config:MAXIM_PATH} MAKE=make PROJECT=${config:project_name}", + "osx":{ + "command": "source ~/.zshrc && make -j 8 distclean --output-sync=target --no-print-directory TARGET=${config:target} BOARD=${config:board} MAXIM_PATH=${config:MAXIM_PATH} MAKE=make PROJECT=${config:project_name}" + }, + "group": "build", + "problemMatcher": [] + }, + { + "label": "flash", + "type": "shell", + "command": "arm-none-eabi-gdb", + "args": [ + "--cd=\"${workspaceFolder}\"", + "--se=\"build/${config:program_file}\"", + "--symbols=build/${config:symbol_file}", + "-x=\"${workspaceFolder}/.vscode/flash.gdb\"", + "--ex=\"flash_m4 ${config:OCD_path} ${config:M4_OCD_interface_file} ${config:M4_OCD_target_file}\"", + "--batch" + ], + "group": "build", + "problemMatcher": [], + "dependsOn":["build"] + }, + { + "label": "flash & run", + "type": "shell", + "command": "arm-none-eabi-gdb", + "args": [ + "--cd=\"${workspaceFolder}\"", + "--se=\"build/${config:program_file}\"", + "--symbols=build/${config:symbol_file}", + "-x=\"${workspaceFolder}/.vscode/flash.gdb\"", + "--ex=\"flash_m4_run ${config:OCD_path} ${config:M4_OCD_interface_file} ${config:M4_OCD_target_file}\"", + "--batch" + ], + "group": "build", + "problemMatcher": [], + "dependsOn":["build"] + }, + { + "label": "erase flash", + "type": "shell", + "command": "openocd", + "args": [ + "-s", "${config:OCD_path}/scripts", + "-f", "interface/${config:M4_OCD_interface_file}", + "-f", "target/${config:M4_OCD_target_file}", + "-c", "\"init; reset halt; max32xxx mass_erase 0;\"", + "-c", "exit" + ], + "group":"build", + "problemMatcher": [], + "dependsOn":[] + }, + { + "label": "openocd (m4)", + "type": "shell", + "command": "openocd", + "args": [ + "-s", + "${config:OCD_path}/scripts", + "-f", + "interface/${config:M4_OCD_interface_file}", + "-f", + "target/${config:M4_OCD_target_file}", + "-c", + "\"init; reset halt\"" + ], + "problemMatcher": [], + "dependsOn":[] + }, + { + "label": "gdb (m4)", + "type": "shell", + "command": "arm-none-eabi-gdb", + "args": [ + "--ex=\"cd ${workspaceFolder}\"", + "--se=\"build/${config:program_file}\"", + "--symbols=build/${config:symbol_file}", + "--ex=\"target remote localhost:3333\"", + "--ex=\"monitor reset halt\"", + "--ex=\"b main\"", + "--ex=\"c\"" + ], + "problemMatcher": [], + "dependsOn":[] + }, + ] +} \ No newline at end of file diff --git a/Examples/MAX32657/Hello_World/Hello_World.launch b/Examples/MAX32657/Hello_World/Hello_World.launch new file mode 100644 index 00000000000..208feecdd1f --- /dev/null +++ b/Examples/MAX32657/Hello_World/Hello_World.launch @@ -0,0 +1,62 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Examples/MAX32657/Hello_World/Makefile b/Examples/MAX32657/Hello_World/Makefile new file mode 100644 index 00000000000..6c2b40a794a --- /dev/null +++ b/Examples/MAX32657/Hello_World/Makefile @@ -0,0 +1,382 @@ +############################################################################### + # + # Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + # Analog Devices, Inc.), + # Copyright (C) 2023-2024 Analog Devices, Inc. + # + # Licensed under the Apache License, Version 2.0 (the "License"); + # you may not use this file except in compliance with the License. + # You may obtain a copy of the License at + # + # http://www.apache.org/licenses/LICENSE-2.0 + # + # Unless required by applicable law or agreed to in writing, software + # distributed under the License is distributed on an "AS IS" BASIS, + # WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + # See the License for the specific language governing permissions and + # limitations under the License. + # + ############################################################################## + +# ** Readme! ** +# Don't edit this file! This is the core Makefile for a MaximSDK +# project. The available configuration options can be overridden +# in "project.mk", on the command-line, or with system environment +# variables. + +# See https://analogdevicesinc.github.io/msdk/USERGUIDE/#build-system +# for more detailed instructions on how to use this system. + +# The detailed instructions mentioned above are easier to read than +# this file, but the comments found in this file also outline the +# available configuration variables. This file is organized into +# sub-sections, some of which expose config variables. + + +# ******************************************************************************* +# Set the target microcontroller and board to compile for. + +# Every TARGET microcontroller has some Board Support Packages (BSPs) that are +# available for it under the MaximSDK/Libraries/Boards/TARGET folder. The BSP +# that gets selected is MaximSDK/Libraries/Boards/TARGET/BOARD. + +# Configuration Variables: +# - TARGET : Override the default target microcontroller. Ex: TARGET=MAX78000 +# - BOARD : Override the default BSP (case sensitive). Ex: BOARD=EvKit_V1, BOARD=FTHR_RevA + + +ifeq "$(TARGET)" "" +# Default target microcontroller +TARGET := MAX32657 +TARGET_UC := MAX32657 +TARGET_LC := max32657 +else +# "TARGET" has been overridden in the environment or on the command-line. +# We need to calculate an upper and lowercase version of the part number, +# because paths on Linux and MacOS are case-sensitive. +TARGET_UC := $(subst m,M,$(subst a,A,$(subst x,X,$(TARGET)))) +TARGET_LC := $(subst M,m,$(subst A,a,$(subst X,x,$(TARGET)))) +endif + +# Default board. +BOARD ?= EvKit_V1 + +# ******************************************************************************* +# Locate the MaximSDK + +# This Makefile needs to know where to find the MaximSDK, and the MAXIM_PATH variable +# should point to the root directory of the MaximSDK installation. Setting this manually +# is usually only required if you're working on the command-line. + +# If MAXIM_PATH is not specified, we assume the project still lives inside of the MaximSDK +# and move up from this project's original location. + +# Configuration Variables: +# - MAXIM_PATH : Tell this Makefile where to find the MaximSDK. Ex: MAXIM_PATH=C:/MaximSDK + + +ifneq "$(MAXIM_PATH)" "" +# Sanitize MAXIM_PATH for backslashes +MAXIM_PATH := $(subst \,/,$(MAXIM_PATH)) +# Locate some other useful paths... +LIBS_DIR := $(abspath $(MAXIM_PATH)/Libraries) +CMSIS_ROOT := $(LIBS_DIR)/CMSIS +endif + +# ******************************************************************************* +# Include project Makefile. We do this after formulating TARGET, BOARD, and MAXIM_PATH +# in case project.mk needs to reference those values. However, we also include +# this as early as possible in the Makefile so that it can append to or override +# the variables below. + + +PROJECTMK ?= $(abspath ./project.mk) +include $(PROJECTMK) +$(info Loaded project.mk) +# PROJECTMK is also used by implicit rules and other libraries to add project.mk as a watch file + +# ******************************************************************************* +# Final path sanitization and re-calculation. No options here. + +ifeq "$(MAXIM_PATH)" "" +# MAXIM_PATH is still not defined... +DEPTH := ../../../ +MAXIM_PATH := $(abspath $(DEPTH)) +$(warning Warning: MAXIM_PATH is not set! Set MAXIM_PATH in your environment or in project.mk to clear this warning.) +$(warning Warning: Attempting to use $(MAXIM_PATH) calculated from relative path) +else +# Sanitize MAXIM_PATH for backslashes +MAXIM_PATH := $(subst \,/,$(MAXIM_PATH)) +endif + +# Final recalculation of LIBS_DIR/CMSIS_ROOT +LIBS_DIR := $(abspath $(MAXIM_PATH)/Libraries) +CMSIS_ROOT := $(LIBS_DIR)/CMSIS + +# One final UC/LC check in case user set TARGET in project.mk +TARGET_UC := $(subst m,M,$(subst a,A,$(subst x,X,$(TARGET)))) +TARGET_LC := $(subst M,m,$(subst A,a,$(subst X,x,$(TARGET)))) + +export TARGET +export TARGET_UC +export TARGET_LC +export CMSIS_ROOT +# TODO: Remove dependency on exports for these variables. + +# ******************************************************************************* +# Set up search paths, and auto-detect all source code on those paths. + +# The following paths are searched by default, where "./" is the project directory. +# ./ +# |- *.h +# |- *.c +# |-include (optional) +# |- *.h +# |-src (optional) +# |- *.c + +# Configuration Variables: +# - VPATH : Tell this Makefile to search additional locations for source (.c) files. +# You should use the "+=" operator with this option. +# Ex: VPATH += your/new/path +# - IPATH : Tell this Makefile to search additional locations for header (.h) files. +# You should use the "+=" operator with this option. +# Ex: VPATH += your/new/path +# - SRCS : Tell this Makefile to explicitly add a source (.c) file to the build. +# This is really only useful if you want to add a source file that isn't +# on any VPATH, in which case you can add the full path to the file here. +# You should use the "+=" operator with this option. +# Ex: SRCS += your/specific/source/file.c +# - AUTOSEARCH : Set whether this Makefile should automatically detect .c files on +# VPATH and add them to the build. This is enabled by default. Set +# to 0 to disable. If autosearch is disabled, source files must be +# manually added to SRCS. +# Ex: AUTOSEARCH = 0 + + +# Where to find source files for this project. +VPATH += . +VPATH += src +VPATH := $(VPATH) + +# Where to find header files for this project +IPATH += . +IPATH += include +IPATH := $(IPATH) + +AUTOSEARCH ?= 1 +ifeq ($(AUTOSEARCH), 1) +# Auto-detect all C/C++ source files on VPATH +SRCS += $(wildcard $(addsuffix /*.c, $(VPATH))) +SRCS += $(wildcard $(addsuffix /*.cpp, $(VPATH))) +endif + +# Collapse SRCS before passing them on to the next stage +SRCS := $(SRCS) + +# ******************************************************************************* +# Set the output filename + +# Configuration Variables: +# - PROJECT : Override the default output filename. Ex: PROJECT=MyProject + + +# The default value creates a file named after the target micro. Ex: MAX78000.elf +PROJECT ?= $(TARGET_LC) + +# ******************************************************************************* +# Compiler options + +# Configuration Variables: +# - DEBUG : Set DEBUG=1 to build explicitly for debugging. This adds some additional +# symbols and sets -Og as the default optimization level. +# - MXC_OPTIMIZE_CFLAGS : Override the default compiler optimization level. +# Ex: MXC_OPTIMIZE_CFLAGS = -O2 +# - PROJ_CFLAGS : Add additional compiler flags to the build. +# You should use the "+=" operator with this option. +# Ex: PROJ_CFLAGS += -Wextra +# - MFLOAT_ABI : Set the floating point acceleration level. +# The only options are "hard", "soft", or "softfp". +# Ex: MFLOAT_ABI = hard +# - LINKERFILE : Override the default linkerfile. +# Ex: LINKERFILE = customlinkerfile.ld +# - LINKERPATH : Override the default search location for $(LINKERFILE) +# The default search location is $(CMSIS_ROOT)/Device/Maxim/$(TARGET_UC)/Source/GCC +# If $(LINKERFILE) cannot be found at this path, then the root project +# directory will be used as a fallback. + +# Select 'GCC' or 'IAR' compiler +ifeq "$(COMPILER)" "" +COMPILER := GCC +endif + +# Set default compiler optimization levels +ifeq "$(MAKECMDGOALS)" "release" +# Default optimization level for "release" builds (make release) +MXC_OPTIMIZE_CFLAGS ?= -O2 +DEBUG = 0 +endif + +ifeq ($(DEBUG),1) +# Optimizes for debugging as recommended +# by GNU for code-edit-debug cycles +# https://gcc.gnu.org/onlinedocs/gcc/Optimize-Options.html#Optimize-Options +MXC_OPTIMIZE_CFLAGS := -Og +endif + +# Default level if not building for release or explicitly for debug +MXC_OPTIMIZE_CFLAGS ?= -Og + +# Set compiler flags +PROJ_CFLAGS += -Wall # Enable warnings +PROJ_CFLAGS += -DMXC_ASSERT_ENABLE + +# Set hardware floating point acceleration. +# Options are: +# - hard +# - soft +# - softfp (default if MFLOAT_ABI is not set) +MFLOAT_ABI ?= softfp +# MFLOAT_ABI must be exported to other Makefiles +export MFLOAT_ABI + +# This path contains system-level intialization files for the target micro. Add to the build. +VPATH += $(CMSIS_ROOT)/Device/Maxim/$(TARGET_UC)/Source + +# ******************************************************************************* +# Secure Boot Tools (SBT) + +# This section integrates the Secure Boot Tools. It's intended for use with +# microcontrollers that have a secure bootloader. + +# Enabling SBT integration will add some special rules, such as "make sla", "make scpa", etc. + +# Configuration variables: +# SBT : Toggle SBT integration. Set to 1 to enable, or 0 +# to disable +# MAXIM_SBT_DIR : Specify the location of the SBT tool binaries. This defaults to +# Tools/SBT in the MaximSDK. The standalone SBT installer will override +# this via an environment variable. +# TARGET_SEC : Specify the part number to be passed into the SBT. This should match +# the secure variant part #. The default value will depend on TARGET. +# For example, TARGET=MAX32650 will result in TARGET_SEC=MAX32651, and +# the default selection happens in Tools/SBT/SBT-config. +# However, if there are multiple secure part #s for the target +# microcontroller this variable may need to be changed. + +SBT ?= 0 +ifeq ($(SBT), 1) +MAXIM_SBT_DIR ?= $(MAXIM_PATH)/Tools/SBT +MAXIM_SBT_DIR := $(subst \,/,$(MAXIM_SBT_DIR)) +# ^ Must sanitize path for \ on Windows, since this may come from an environment +# variable. + +export MAXIM_SBT_DIR # SBTs must have this environment variable defined to work + +# SBT-config.mk and SBT-rules.mk are included further down this Makefile. + +endif # SBT + +# ******************************************************************************* +# Default goal selection. This section allows you to override the default goal +# that will run if no targets are specified on the command-line. +# (ie. just running 'make' instead of 'make all') + +# Configuration variables: +# .DEFAULT_GOAL : Set the default goal if no targets were specified on the +# command-line +# ** "override" must be used with this variable. ** +# Ex: "override .DEFAULT_GOAL = mygoal" + +ifeq "$(.DEFAULT_GOAL)" "" +ifeq ($(SBT),1) +override .DEFAULT_GOAL := sla +else +override .DEFAULT_GOAL := all +endif +endif + +# Developer note: 'override' is used above for legacy Makefile compatibility. +# gcc.mk/gcc_riscv.mk need to hard-set 'all' internally, so this new system +# uses 'override' to come in over the top without breaking old projects. + +# It's also necessary to explicitly set MAKECMDGOALS... +ifeq "$(MAKECMDGOALS)" "" +MAKECMDGOALS:=$(.DEFAULT_GOAL) +endif + +# Enable colors when --sync-output is used. +# See https://www.gnu.org/software/make/manual/make.html#Terminal-Output (section 13.2) +ifneq ($(MAKE_TERMOUT),) +PROJ_CFLAGS += -fdiagnostics-color=always +endif + +ifneq ($(FORCE_COLOR),) +PROJ_CFLAGS += -fdiagnostics-color=always +endif + +# ******************************************************************************* +# Include SBT config. We need to do this here because it needs to know +# the current MAKECMDGOAL. +ifeq ($(SBT),1) +include $(MAXIM_PATH)/Tools/SBT/SBT-config.mk +endif + +# ******************************************************************************* +# Libraries + +# This section offers "toggle switches" to include or exclude the libraries that +# are available in the MaximSDK. Set a configuration variable to 1 to include the +# library in the build, or 0 to exclude. + +# Each library may also have its own library specific configuration variables. See +# Libraries/libs.mk for more details. + +# Configuration variables: +# - LIB_BOARD : Include the Board-Support Package (BSP) library. (Enabled by default) +# - LIB_PERIPHDRIVERS : Include the peripheral driver library. (Enabled by default) +# - LIB_CMSIS_DSP : Include the CMSIS-DSP library. +# - LIB_CORDIO : Include the Cordio BLE library +# - LIB_FCL : Include the Free Cryptographic Library (FCL) +# - LIB_FREERTOS : Include the FreeRTOS and FreeRTOS-Plus-CLI libraries +# - LIB_LC3 : Include the Low Complexity Communication Codec (LC3) library +# - LIB_LITTLEFS : Include the "little file system" (littleFS) library +# - LIB_LWIP : Include the lwIP library +# - LIB_MAXUSB : Include the MAXUSB library +# - LIB_SDHC : Include the SDHC library + +include $(LIBS_DIR)/libs.mk + + +# ******************************************************************************* +# Rules + +# Include the rules for building for this target. All other makefiles should be +# included before this one. +include $(CMSIS_ROOT)/Device/Maxim/$(TARGET_UC)/Source/$(COMPILER)/$(TARGET_LC).mk + +# Include the rules that integrate the SBTs. SBTs are a special case that must be +# include after the core gcc rules to extend them. +ifeq ($(SBT), 1) +include $(MAXIM_PATH)/Tools/SBT/SBT-rules.mk +endif + + +# Get .DEFAULT_GOAL working. +ifeq "$(MAKECMDGOALS)" "" +MAKECMDGOALS:=$(.DEFAULT_GOAL) +endif + + +all: +# Extend the functionality of the "all" recipe here + arm-none-eabi-size --format=berkeley $(BUILD_DIR)/$(PROJECT).elf + +libclean: + $(MAKE) -f ${PERIPH_DRIVER_DIR}/periphdriver.mk clean.periph + +clean: +# Extend the functionality of the "clean" recipe here + +# The rule to clean out all the build products. +distclean: clean libclean diff --git a/Examples/MAX32657/Hello_World/README.md b/Examples/MAX32657/Hello_World/README.md new file mode 100644 index 00000000000..cdff97576e7 --- /dev/null +++ b/Examples/MAX32657/Hello_World/README.md @@ -0,0 +1,42 @@ +## Description + +A basic getting started program. + +This version of Hello_World prints an incrementing count to the console UART and toggles a LED0 every 500 ms. + + +## Software + +### Project Usage + +Universal instructions on building, flashing, and debugging this project can be found in the **[MSDK User Guide](https://analogdevicesinc.github.io/msdk/USERGUIDE/)**. + +### Project-Specific Build Notes + +* This project comes pre-configured for the MAX32655EVKIT. See [Board Support Packages](https://analogdevicesinc.github.io/msdk/USERGUIDE/#board-support-packages) in the MSDK User Guide for instructions on changing the target board. + +## Required Connections +If using the MAX32655EVKIT (EvKit\_V1): +- Connect a USB cable between the PC and the CN1 (USB/PWR) connector. +- Connect pins JP4(RX_SEL) and JP5(TX_SEL) to RX0 and TX0 header. +- Open an terminal application on the PC and connect to the EV kit's console UART at 115200, 8-N-1. +- Close jumper JP2 (LED0 EN). +- Close jumper JP3 (LED1 EN). + +If using the MAX32655FTHR (FTHR\_Apps\_P1): +- Connect a USB cable between the PC and the J4 (USB/PWR) connector. +- Open an terminal application on the PC and connect to the board's console UART at 115200, 8-N-1. + +## Expected Output + +The Console UART of the device will output these messages: + +``` +Hello World! +count : 0 +count : 1 +count : 2 +count : 3 +``` + +You will also observe LED0 blinking at a rate of 2Hz. diff --git a/Examples/MAX32657/Hello_World/main.c b/Examples/MAX32657/Hello_World/main.c new file mode 100644 index 00000000000..5a4ce99ba9d --- /dev/null +++ b/Examples/MAX32657/Hello_World/main.c @@ -0,0 +1,56 @@ +/****************************************************************************** + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +/** + * @file main.c + * @brief Hello World! + * @details This example uses the UART to print to a terminal and flashes an LED. + */ + +/***** Includes *****/ +#include +#include +#include "mxc_device.h" +#include "led.h" +#include "pb.h" +#include "board.h" +#include "mxc_delay.h" + +/***** Definitions *****/ + +/***** Globals *****/ + +/***** Functions *****/ + +// ***************************************************************************** +int main(void) +{ + int count = 0; + + printf("Hello World!\n"); + + while (1) { + LED_On(LED_RED); + MXC_Delay(500000); + LED_Off(LED_RED); + MXC_Delay(500000); + printf("count = %d\n", count++); + } +} diff --git a/Examples/MAX32657/Hello_World/project.mk b/Examples/MAX32657/Hello_World/project.mk new file mode 100644 index 00000000000..c5bb8a2183b --- /dev/null +++ b/Examples/MAX32657/Hello_World/project.mk @@ -0,0 +1,10 @@ +# This file can be used to set build configuration +# variables. These variables are defined in a file called +# "Makefile" that is located next to this one. + +# For instructions on how to use this system, see +# https://analogdevicesinc.github.io/msdk/USERGUIDE/#build-system + +# ********************************************************** + +# Add your config here! From 05b71fc342d2f2686bda52dec63f89d45924c6d4 Mon Sep 17 00:00:00 2001 From: Jake Carter Date: Tue, 30 Apr 2024 19:28:23 -0600 Subject: [PATCH 33/93] Fix comment typo --- Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h index 35efa6c2eb9..67ac023cab0 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h @@ -604,7 +604,7 @@ We may want to handle GET_IRQ better... /******************************************************************************/ /* UART / Serial Port Interface */ #define MXC_UART_INSTANCES (1) -#define MXC_UART_FIFO_DEPTH (8) // TOD(ME30): Check this is correct. +#define MXC_UART_FIFO_DEPTH (8) // TODO(ME30): Check this is correct. /* Non-secure Mapping */ #define MXC_BASE_UART_NS ((uint32_t)0x40042000UL) From 1ddd3e7cda1551880bca83556cd95567a1406635 Mon Sep 17 00:00:00 2001 From: Jake Carter Date: Wed, 1 May 2024 12:03:40 -0600 Subject: [PATCH 34/93] Update readme --- Examples/MAX32657/Hello_World/README.md | 12 +----------- 1 file changed, 1 insertion(+), 11 deletions(-) diff --git a/Examples/MAX32657/Hello_World/README.md b/Examples/MAX32657/Hello_World/README.md index cdff97576e7..c64b76a6473 100644 --- a/Examples/MAX32657/Hello_World/README.md +++ b/Examples/MAX32657/Hello_World/README.md @@ -13,19 +13,9 @@ Universal instructions on building, flashing, and debugging this project can be ### Project-Specific Build Notes -* This project comes pre-configured for the MAX32655EVKIT. See [Board Support Packages](https://analogdevicesinc.github.io/msdk/USERGUIDE/#board-support-packages) in the MSDK User Guide for instructions on changing the target board. +* This project comes pre-configured for the MAX32657EVKIT. See [Board Support Packages](https://analogdevicesinc.github.io/msdk/USERGUIDE/#board-support-packages) in the MSDK User Guide for instructions on changing the target board. ## Required Connections -If using the MAX32655EVKIT (EvKit\_V1): -- Connect a USB cable between the PC and the CN1 (USB/PWR) connector. -- Connect pins JP4(RX_SEL) and JP5(TX_SEL) to RX0 and TX0 header. -- Open an terminal application on the PC and connect to the EV kit's console UART at 115200, 8-N-1. -- Close jumper JP2 (LED0 EN). -- Close jumper JP3 (LED1 EN). - -If using the MAX32655FTHR (FTHR\_Apps\_P1): -- Connect a USB cable between the PC and the J4 (USB/PWR) connector. -- Open an terminal application on the PC and connect to the board's console UART at 115200, 8-N-1. ## Expected Output From 19787250196471f1ef0522253f960190fd08f5a8 Mon Sep 17 00:00:00 2001 From: Jake Carter Date: Wed, 1 May 2024 15:39:14 -0600 Subject: [PATCH 35/93] Update ME30 linker script - Target secure memory regions by default (CPU boots into secure mode by default) - Update memory layout and sizes - Remove dual-core/shared/mailbox (single-core device) --- .../Maxim/MAX32657/Source/GCC/max32657.ld | 60 +++++++------------ 1 file changed, 20 insertions(+), 40 deletions(-) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.ld b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.ld index 695e2f01d09..72aae01c65d 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.ld +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.ld @@ -1,8 +1,6 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -19,9 +17,12 @@ ******************************************************************************/ MEMORY { - ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x00010000 /* 64kB ROM */ - FLASH (rx) : ORIGIN = 0x10000000, LENGTH = 0x00080000 /* 512KB Flash */ - SRAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020000 /* 128kB SRAM */ + ROM_S (rx) : ORIGIN = 0x00000000, LENGTH = 0x00010000 /* 64kB secure ROM (ROM always secure) */ + FLASH_NS (rx) : ORIGIN = 0x01000000, LENGTH = 0x00100000 /* 1MB non-secure Flash */ + SRAM_NS (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000 /* 256KB non-secure SRAM */ + FLASH_S (rx) : ORIGIN = 0x11000000, LENGTH = 0x00100000 /* 1MB secure Flash */ + FLASH_INFO_S (rx) : ORIGIN = 0x12000000, LENGTH = 0x00010000 /* 16KB secure Flash Info */ + SRAM_S (rwx) : ORIGIN = 0x30000000, LENGTH = 0x00040000 /* 256KB secure SRAM */ } SECTIONS { @@ -29,7 +30,7 @@ SECTIONS { { KEEP(*(.rom_vector)) *(.rom_handlers*) - } > ROM + } > ROM_S .text : { @@ -58,12 +59,12 @@ SECTIONS { /* C++ Exception handling */ KEEP(*(.eh_frame*)) _etext = .; - } > FLASH + } > FLASH_S .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH + } > FLASH_S /* Binary import */ .bin_storage : @@ -73,7 +74,7 @@ SECTIONS { KEEP(*(.bin_storage_img)) _bin_end_ = .; . = ALIGN(4); - } > FLASH + } > FLASH_S .rom_code : { @@ -81,7 +82,7 @@ SECTIONS { _sran_code = .; *(.rom_code_section) _esran_code = .; - } > ROM + } > ROM_S .flash_code : { @@ -89,7 +90,7 @@ SECTIONS { _sran_code = .; *(.flash_code_section) _esran_code = .; - } > FLASH + } > FLASH_S .sram_code : { @@ -97,7 +98,7 @@ SECTIONS { _sran_code = .; *(.sram_code_section) _esran_code = .; - } > SRAM + } > SRAM_S /* it's used for C++ exception handling */ /* we need to keep this to avoid overlapping */ @@ -106,7 +107,7 @@ SECTIONS { __exidx_start = .; *(.ARM.exidx* .gnu.linkonce.armexidx.*) __exidx_end = .; - } > FLASH + } > FLASH_S .data : { @@ -137,7 +138,7 @@ SECTIONS { PROVIDE_HIDDEN (__fini_array_end = .); _edata = ALIGN(., 4); - } > SRAM AT>FLASH + } > SRAM_S AT>FLASH_S __load_data = LOADADDR(.data); .bss : @@ -145,24 +146,12 @@ SECTIONS { . = ALIGN(4); _bss = .; *(.bss*) /*read-write zero initialized data: uninitialzed global variable*/ - *(COMMON) _ebss = ALIGN(., 4); - } > SRAM - - .shared : - { - . = ALIGN(4); - _shared = .; - *(.mailbox*) - . = ALIGN(4); - *(.shared*) /*read-write zero initialized data: uninitialzed global variable*/ - _eshared = ALIGN(., 4); - } > SRAM AT>FLASH - __shared_data = LOADADDR(.shared); + } > SRAM_S /* Set stack top to end of RAM, and stack limit move down by * size of stack_dummy section */ - __StackTop = ORIGIN(SRAM) + LENGTH(SRAM); + __StackTop = ORIGIN(SRAM_S) + LENGTH(SRAM_S); __StackLimit = __StackTop - SIZEOF(.stack_dummy); /* .stack_dummy section doesn't contains any symbols. It is only @@ -171,27 +160,18 @@ SECTIONS { .stack_dummy (COPY): { *(.stack*) - } > SRAM + } > SRAM_S .heap (COPY): { . = ALIGN(4); *(.heap*) __HeapLimit = ABSOLUTE(__StackLimit); - } > SRAM + } > SRAM_S PROVIDE(__stack = __StackTop); /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack") - /* Section used by RISCV loader projects. See RISCV_LOAD documentation in the build system. */ - .riscv_flash : - { - /* Align address to mod 256 with a small offset. This is required to match the flash page size.*/ - . = ALIGN(256); /* ALIGN operatator is used here. Note that (. & 0x1FFFFF00) was used in the past, but a strange bug was seen on Windows where the & did not behave as expected.*/ - . += 0x100; - _riscv_boot = .; - KEEP(*riscv.o (.text*)) - } > FLASH } From 68338cc6e44b0ede6192c4cec56be43e9e9c47e9 Mon Sep 17 00:00:00 2001 From: Jake Carter Date: Wed, 1 May 2024 15:40:28 -0600 Subject: [PATCH 36/93] Update .arch value for startup assembly file --- .../Maxim/MAX32657/Source/GCC/startup_max32657.S | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/startup_max32657.S b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/startup_max32657.S index 4bad29772e9..6d472f73a13 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/startup_max32657.S +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/startup_max32657.S @@ -19,15 +19,15 @@ ******************************************************************************/ .syntax unified - .arch armv8-m + .arch armv8-m.main .section .stack .align 3 #ifdef __STACK_SIZE .equ Stack_Size, __STACK_SIZE #else - // TODO: Update max stack size - .equ Stack_Size, 0x00001000 + // Default stack size (192KB) + .equ Stack_Size, 0x00030000 #endif .globl __StackTop .globl __StackLimit @@ -42,8 +42,8 @@ __StackTop: #ifdef __HEAP_SIZE .equ Heap_Size, __HEAP_SIZE #else - // TODO: Update max heap size - .equ Heap_Size, 0x00000C00 + // Default heap size (64KB) + .equ Heap_Size, 0x00010000 #endif .globl __HeapBase .globl __HeapLimit From 6f19ec6656398fc579716ed138ec1a50d50de07a Mon Sep 17 00:00:00 2001 From: Jake Carter Date: Wed, 1 May 2024 15:41:14 -0600 Subject: [PATCH 37/93] Add basic selector for secure/non-secure builds - Add MSECURITY_MODE build configuration variable - Defines MSECURITY_MODE_SECURE/MSECURITY_MODE_NONSECURE at compile time --- Libraries/CMSIS/Device/Maxim/GCC/gcc.mk | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/Libraries/CMSIS/Device/Maxim/GCC/gcc.mk b/Libraries/CMSIS/Device/Maxim/GCC/gcc.mk index d16eae97c2c..13406a0a04f 100644 --- a/Libraries/CMSIS/Device/Maxim/GCC/gcc.mk +++ b/Libraries/CMSIS/Device/Maxim/GCC/gcc.mk @@ -255,6 +255,26 @@ endif # - cortex-m33 MCPU ?= cortex-m4 +ifeq "$(MCPU)" "cortex-m33" +# Security mode for the target processor. +# Acceptable values are +# - SECURE +# - NONSECURE +# +# When "SECURE" is selected, the build system will link the program binary into the secure +# memory sections and map peripheral instances onto their corresponding secure +# address aliases. "MSECURITY_MODE_SECURE" will be defined at compile time. +# +# When "NONSCURE" is selected, the program binary will be linked into the non-secure memory +# sections and peripherals will be mapped onto the non-secure address aliases. +# It should be noted that the M33 will boot into secure mode by default, which has access to +# both the secure and non-secure addresses and aliases. "MSECURITY_MODE_NONSECURE" will be defined +# at compile time. +MSECURITY_MODE ?= SECURE + +PROJ_CFLAGS += -DMSECURITY_MODE_$(MSECURITY_MODE) +endif + # Float ABI options: # See https://gcc.gnu.org/onlinedocs/gcc/ARM-Options.html (-mfloat-abi) # Specifies which floating-point ABI to use. Permissible values are: ‘soft’, ‘softfp’ and ‘hard’. From e36207e1681a7eba39ce8649427160757fb2119d Mon Sep 17 00:00:00 2001 From: Jake Carter Date: Wed, 1 May 2024 16:19:33 -0600 Subject: [PATCH 38/93] Add MAX32657 periph driver files to build --- Libraries/PeriphDrivers/max32657_files.mk | 60 +++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/Libraries/PeriphDrivers/max32657_files.mk b/Libraries/PeriphDrivers/max32657_files.mk index afaccda46e3..9be6538cd3e 100644 --- a/Libraries/PeriphDrivers/max32657_files.mk +++ b/Libraries/PeriphDrivers/max32657_files.mk @@ -51,3 +51,63 @@ PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_assert.c PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_delay.c PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_lock.c +PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/AES +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/AES/aes_me30.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/AES/aes_revb.c + +PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/CRC +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/CRC/crc_me30.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/CRC/crc_reva.c + +PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/DMA +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/DMA/dma_me30.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/DMA/dma_reva.c + +PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/FLC +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/FLC/flc_common.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/FLC/flc_me30.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/FLC/flc_reva.c + +PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/GPIO +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/GPIO/gpio_common.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/GPIO/gpio_me30.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/GPIO/gpio_reva.c + +PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/ICC +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/ICC/icc_me30.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/ICC/icc_reva.c + +PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/LP +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/LP/lp_me30.c + +PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/RTC +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/RTC/rtc_me30.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/RTC/rtc_reva.c + +PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/SPI +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SPI/spi_me30.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SPI/spi_reva1.c + +PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/TMR +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/TMR/tmr_common.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/TMR/tmr_me30.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/TMR/tmr_revb.c + +PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/TRNG +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/TRNG/trng_me30.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/TRNG/trng_revb.c + +PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/UART +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/UART/uart_common.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/UART/uart_me30.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/UART/uart_reva.c + +PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/WDT +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_common.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_me30.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_reva.c + +PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/WUT +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WUT/wut_me30.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WUT/wut_reva.c + From 9f7bbfe13b9b115105a10fb7c70efe90a763bf26 Mon Sep 17 00:00:00 2001 From: Jake Carter Date: Wed, 1 May 2024 16:20:06 -0600 Subject: [PATCH 39/93] Implement top-level UART macros for secure/non-secure --- .../Device/Maxim/MAX32657/Include/max32657.h | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h index 67ac023cab0..cfff0a47210 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h @@ -59,6 +59,7 @@ /* ================================================================================ */ // clang-format off +// TODO(ME30): Secure vs non-secure interrupt vectors typedef enum { NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, @@ -617,11 +618,22 @@ We may want to handle GET_IRQ better... #define MXC_BASE_UART_S ((uint32_t)0x50042000UL) #define MXC_UART_S ((mxc_uart_regs_t *)MXC_BASE_UART_S) +#define MXC_UART_S_GET_UART(i) ((i) == 0 ? MXC_UART_S : 0) +#define MXC_UART_S_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0_S : 0) + +#ifdef MSECURITY_MODE_SECURE #define MXC_BASE_UART MXC_BASE_UART_S #define MXC_UART MXC_UART_S -#define MXC_UART_S_GET_UART(i) ((i) == 0 ? MXC_UART_S : 0) -#define MXC_UART_S_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0_S : 0) +#define MXC_UART_GET_UART(i) MXC_UART_S_GET_UART(i) +#endif + +#ifdef MSECURITY_MODE_NONSECURE +#define MXC_BASE_UART MXC_BASE_UART_NS +#define MXC_UART MXC_UART_NS + +#define MXC_UART_GET_UART(i) MXC_UART_NS_GET_UART(i) +#endif #define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : 0) #define MXC_UART_GET_IDX(p) ((p) == MXC_UART_NS ? 0 : (p) == MXC_UART_S ? 0 : -1) From df0e56640da75070e9561fed270a9d16dbe6ee7f Mon Sep 17 00:00:00 2001 From: Jake Carter Date: Wed, 1 May 2024 16:21:23 -0600 Subject: [PATCH 40/93] Update DMA drivers to handle multiple instances --- .../PeriphDrivers/Include/MAX32657/dma.h | 76 ++++++++++--------- .../PeriphDrivers/Include/MAX32657/mxc_sys.h | 2 - Libraries/PeriphDrivers/Source/DMA/dma_me30.c | 58 ++++++++++---- 3 files changed, 81 insertions(+), 55 deletions(-) diff --git a/Libraries/PeriphDrivers/Include/MAX32657/dma.h b/Libraries/PeriphDrivers/Include/MAX32657/dma.h index 747e5702681..fb9c43273ac 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/dma.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/dma.h @@ -187,6 +187,7 @@ typedef mxc_dma_srcdst_t (*mxc_dma_trans_chain_t)(mxc_dma_srcdst_t dest); /*************************/ /** * @brief Initialize DMA resources + * @param dma Pointer to DMA registers. * @details This initialization is required before using the DMA driver functions. * @note On default this function enables DMA peripheral clock. * if you wish to manage clock and gpio related things in upper level instead of here. @@ -194,15 +195,18 @@ typedef mxc_dma_srcdst_t (*mxc_dma_trans_chain_t)(mxc_dma_srcdst_t dest); * By this flag this function will remove clock and gpio related codes from file. * @return #E_NO_ERROR if successful */ -int MXC_DMA_Init(void); +int MXC_DMA_Init(mxc_dma_regs_t *dma); /** * @brief De-Initialize DMA resources. + * + * @param dma Pointer to DMA registers. */ -void MXC_DMA_DeInit(void); +void MXC_DMA_DeInit(mxc_dma_regs_t *dma); /** * @brief Request DMA channel + * @param dma Pointer to DMA registers. * @details Returns a handle to the first free DMA channel, which can be used via API calls * or direct access to channel registers using the MXC_DMA_GetCHRegs(int ch) function. * @return Non-negative channel handle (inclusive of zero). @@ -210,13 +214,13 @@ void MXC_DMA_DeInit(void); * @return #E_BAD_STATE DMA is not initialized, call MXC_DMA_Init() first. * @return #E_BUSY DMA is currently busy (locked), try again later. */ -int MXC_DMA_AcquireChannel(void); +int MXC_DMA_AcquireChannel(mxc_dma_regs_t *dma); /** * @brief Release DMA channel * @details Stops any DMA operation on the channel and returns it to the pool of free channels. * - * @param ch DMA channel to release + * @param ch channel handle to release * * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise */ @@ -260,6 +264,7 @@ int MXC_DMA_SetSrcDst(mxc_dma_srcdst_t srcdst); * * @return See \ref MXC_Error_Codes for a list of return values */ + int MXC_DMA_GetSrcDst(mxc_dma_srcdst_t *srcdst); /** @@ -280,11 +285,12 @@ int MXC_DMA_SetSrcReload(mxc_dma_srcdst_t srcdstReload); * * @return See \ref MXC_Error_Codes for a list of return values */ + int MXC_DMA_GetSrcReload(mxc_dma_srcdst_t *srcdstReload); /** * @brief Set channel interrupt callback - * @param ch DMA channel + * @param ch channel handle * @param callback Pointer to a function to call when the channel * interrupt flag is set and interrupts are enabled or * when DMA is shutdown by the driver. @@ -301,8 +307,8 @@ int MXC_DMA_GetSrcReload(mxc_dma_srcdst_t *srcdstReload); * reason is either #E_NO_ERROR for a DMA interrupt or #E_SHUTDOWN * if the DMA is being shutdown. * - * @return #E_BAD_PARAM if an unused or invalid channel handle, - * #E_NO_ERROR otherwise, \ref MXC_Error_Codes + * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR + * otherwise */ int MXC_DMA_SetCallback(int ch, void (*callback)(int, int)); @@ -311,7 +317,7 @@ int MXC_DMA_SetCallback(int ch, void (*callback)(int, int)); * @note Each channel has two interrupts (complete, and count to zero). * To enable complete, pass true for chdis. To enable count to zero, * pass true for ctz. - * @param ch DMA channel + * @param ch Channel Handle * @param chdis Enable channel complete interrupt * @param ctz Enable channel count to zero interrupt. * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise @@ -322,36 +328,32 @@ int MXC_DMA_SetChannelInterruptEn(int ch, bool chdis, bool ctz); * @brief Enable channel interrupt * @note Each channel has two interrupts (complete, and count to zero) which must also be enabled with MXC_DMA_SetChannelInterruptEn() - * @param ch DMA channel to enable interrupts for. + * @param ch channel handle * @param flags The flags to enable - * @return #E_BAD_PARAM if an unused or invalid channel handle, - * #E_NO_ERROR otherwise, \ref MXC_Error_Codes + * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise */ int MXC_DMA_ChannelEnableInt(int ch, int flags); /** * @brief Disable channel interrupt - * @param ch DMA channel to clear flags for. + * @param ch channel handle * @param flags The flags to disable - * @return #E_BAD_PARAM if an unused or invalid channel handle, - * #E_NO_ERROR otherwise, \ref MXC_Error_Codes + * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise */ int MXC_DMA_ChannelDisableInt(int ch, int flags); /** * @brief Read channel interrupt flags - * @param ch DMA channel to get interrupt status from. - * @return #E_BAD_PARAM if an unused or invalid channel handle, - * flags otherwise, \ref MXC_Error_Codes + * @param ch channel handle + * @return #E_BAD_PARAM if an unused or invalid channel handle, flags otherwise */ int MXC_DMA_ChannelGetFlags(int ch); /** * @brief Clear channel interrupt flags - * @param ch DMA channel to clear the interrupt flag for. + * @param ch channel handle * @param flags The flags to clear - * @return #E_BAD_PARAM if an unused or invalid channel handle, - * #E_NO_ERROR otherwise, \ref MXC_Error_Codes + * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise */ int MXC_DMA_ChannelClearFlags(int ch, int flags); @@ -359,40 +361,36 @@ int MXC_DMA_ChannelClearFlags(int ch, int flags); * @brief Enable channel interrupt * @note Each channel has two interrupts (complete, and count to zero) which must also be enabled with MXC_DMA_SetChannelInterruptEn() - * @param ch DMA channel to enable interrupts for. - * @return #E_BAD_PARAM if an unused or invalid channel handle, - * #E_NO_ERROR otherwise, \ref MXC_Error_Codes + * @param ch channel handle + * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise */ int MXC_DMA_EnableInt(int ch); /** * @brief Disable channel interrupt - * @param ch DMA channel to disable interrupts for. - * @return #E_BAD_PARAM if an unused or invalid channel handle, - * #E_NO_ERROR otherwise, \ref MXC_Error_Codes + * @param ch channel handle + * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise */ int MXC_DMA_DisableInt(int ch); /** * @brief Start transfer - * @param ch DMA channel - * @details Start the DMA channel transfer, assumes that MXC_DMA_SetSrcDstCnt() has been called beforehand. - * @return #E_BAD_PARAM if an unused or invalid channel handle, - * #E_NO_ERROR otherwise, \ref MXC_Error_Codes + * @param ch channel handle + * @note Start the DMA channel transfer, assumes that MXC_DMA_SetSrcDstCnt() has been called beforehand. + * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise */ int MXC_DMA_Start(int ch); /** * @brief Stop DMA transfer, irrespective of status (complete or in-progress) - * @param ch DMA channel - * @return #E_BAD_PARAM if an unused or invalid channel handle, - * #E_NO_ERROR otherwise, \ref MXC_Error_Codes + * @param ch channel handle + * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise */ int MXC_DMA_Stop(int ch); /** * @brief Get a pointer to the DMA channel registers - * @param ch DMA channel + * @param ch channel handle * @note If direct access to DMA channel registers is required, this * function can be used on a channel handle returned by MXC_DMA_AcquireChannel(). * @return NULL if an unused or invalid channel handle, or a valid pointer otherwise @@ -401,10 +399,11 @@ mxc_dma_ch_regs_t *MXC_DMA_GetCHRegs(int ch); /** * @brief Interrupt handler function + * @param dma Pointer to DMA registers. * @details Call this function as the ISR for each DMA channel under driver control. * Interrupt flags for channel ch will be automatically cleared before return. */ -void MXC_DMA_Handler(void); +void MXC_DMA_Handler(mxc_dma_regs_t *dma); /*************************/ /* High Level Functions */ @@ -415,6 +414,7 @@ void MXC_DMA_Handler(void); * @note The user must have the DMA interrupt enabled and call * MXC_DMA_Handler() from the ISR. * + * @param dma Pointer to DMA registers. * @param dest pointer to destination memory * @param src pointer to source memory * @param len number of bytes to copy @@ -422,20 +422,22 @@ void MXC_DMA_Handler(void); * * @return see \ref MXC_Error_Codes */ -int MXC_DMA_MemCpy(void *dest, void *src, int len, mxc_dma_complete_cb_t callback); +int MXC_DMA_MemCpy(mxc_dma_regs_t *dma, void *dest, void *src, int len, + mxc_dma_complete_cb_t callback); /** * @brief Performs a memcpy, using DMA, optionally asynchronous * @note The user must have the DMA interrupt enabled and call * MXC_DMA_Handler() from the ISR. * + * @param dma Pointer to DMA registers. * @param config The channel config struct * @param firstSrcDst The source, destination, and count for the first transfer * @param callback function is called when transfer is complete * * @return see \ref MXC_Error_Codes */ -int MXC_DMA_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, +int MXC_DMA_DoTransfer(mxc_dma_regs_t *dma, mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback); /** * For other functional uses of DMA (UART, SPI, etc) see the appropriate peripheral driver diff --git a/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h b/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h index def4ee9b925..9a50c8fd720 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h @@ -91,8 +91,6 @@ typedef enum { /* PCLKDIS1 Below this line we add 32 to separate PCLKDIS0 and PCLKDIS1 */ MXC_SYS_PERIPH_CLOCK_TRNG = (MXC_F_GCR_PCLKDIS1_TRNG_POS + 32), /**< Disable TRNG clock */ - // MXC_SYS_PERIPH_CLOCK_SMPHR = - // (MXC_F_GCR_PCLKDIS1_SMPHR_POS + 32), /**< Disable SMPHR clock */ MXC_SYS_PERIPH_CLOCK_CRC = (MXC_F_GCR_PCLKDIS1_CRC_POS + 32), /**< Disable CRC clock */ MXC_SYS_PERIPH_CLOCK_AES = diff --git a/Libraries/PeriphDrivers/Source/DMA/dma_me30.c b/Libraries/PeriphDrivers/Source/DMA/dma_me30.c index a0483bd536d..82a4c3ccc26 100644 --- a/Libraries/PeriphDrivers/Source/DMA/dma_me30.c +++ b/Libraries/PeriphDrivers/Source/DMA/dma_me30.c @@ -32,26 +32,50 @@ /****** Functions ******/ -int MXC_DMA_Init(void) +static mxc_dma_regs_t *getDMAInstance(int ch) +{ + if (ch < (MXC_DMA_CHANNELS / MXC_DMA_INSTANCES)) { + return MXC_DMA0; + } else if (ch >= (MXC_DMA_CHANNELS / MXC_DMA_INSTANCES) && ch < MXC_DMA_CHANNELS) { + return MXC_DMA1; + } + + return NULL; +} + +int MXC_DMA_Init(mxc_dma_regs_t *dma) { #ifndef MSDK_NO_GPIO_CLK_INIT - if (!MXC_SYS_IsClockEnabled(MXC_SYS_PERIPH_CLOCK_DMA)) { - MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_DMA); - MXC_SYS_Reset_Periph(MXC_SYS_RESET0_DMA); + switch (MXC_DMA_GET_IDX(dma)) { + case 0: + if (!MXC_SYS_IsClockEnabled(MXC_SYS_PERIPH_CLOCK_DMA0)) { + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_DMA0); + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_DMA0); + } + break; + case 1: + // TODO(ME30): PERIPH CLOCK register definitions missing for DMA1 + //if (!MXC_SYS_IsClockEnabled(MXC_SYS_PERIPH_CLOCK)) { + // MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_DMA1); + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_DMA1); + // } + break; + default: + return E_BAD_PARAM; } #endif - return MXC_DMA_RevA_Init((mxc_dma_reva_regs_t *)MXC_DMA); + return MXC_DMA_RevA_Init((mxc_dma_reva_regs_t *)dma); } -void MXC_DMA_DeInit(void) +void MXC_DMA_DeInit(mxc_dma_regs_t *dma) { - return MXC_DMA_RevA_DeInit((mxc_dma_reva_regs_t *)MXC_DMA); + return MXC_DMA_RevA_DeInit((mxc_dma_reva_regs_t *)dma); } int MXC_DMA_AcquireChannel(void) { - return MXC_DMA_RevA_AcquireChannel((mxc_dma_reva_regs_t *)MXC_DMA); + return MXC_DMA_RevA_AcquireChannel((mxc_dma_reva_regs_t *)dma); } int MXC_DMA_ReleaseChannel(int ch) @@ -121,12 +145,14 @@ int MXC_DMA_ChannelClearFlags(int ch, int flags) int MXC_DMA_EnableInt(int ch) { - return MXC_DMA_RevA_EnableInt((mxc_dma_reva_regs_t *)MXC_DMA, ch); + mxc_dma_regs_t *dma = getDMAInstance(ch); + return MXC_DMA_RevA_EnableInt((mxc_dma_reva_regs_t *)dma, ch); } int MXC_DMA_DisableInt(int ch) { - return MXC_DMA_RevA_DisableInt((mxc_dma_reva_regs_t *)MXC_DMA, ch); + mxc_dma_regs_t *dma = getDMAInstance(ch); + return MXC_DMA_RevA_DisableInt((mxc_dma_reva_regs_t *)dma, ch); } int MXC_DMA_Start(int ch) @@ -144,18 +170,18 @@ mxc_dma_ch_regs_t *MXC_DMA_GetCHRegs(int ch) return MXC_DMA_RevA_GetCHRegs(ch); } -void MXC_DMA_Handler(void) +void MXC_DMA_Handler(mxc_dma_regs_t *dma) { - MXC_DMA_RevA_Handler((mxc_dma_reva_regs_t *)MXC_DMA); + MXC_DMA_RevA_Handler((mxc_dma_reva_regs_t *)dma); } -int MXC_DMA_MemCpy(void *dest, void *src, int len, mxc_dma_complete_cb_t callback) +int MXC_DMA_MemCpy(mxc_dma_regs_t *dma, void *dest, void *src, int len, mxc_dma_complete_cb_t callback) { - return MXC_DMA_RevA_MemCpy((mxc_dma_reva_regs_t *)MXC_DMA, dest, src, len, callback); + return MXC_DMA_RevA_MemCpy((mxc_dma_reva_regs_t *)dma, dest, src, len, callback); } -int MXC_DMA_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, +int MXC_DMA_DoTransfer(mxc_dma_regs_t *dma, mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback) { - return MXC_DMA_RevA_DoTransfer((mxc_dma_reva_regs_t *)MXC_DMA, config, firstSrcDst, callback); + return MXC_DMA_RevA_DoTransfer((mxc_dma_reva_regs_t *)dma, config, firstSrcDst, callback); } From e61dab141e4b0538d69c4fd4c4b86b589d70f621 Mon Sep 17 00:00:00 2001 From: Jake Carter Date: Thu, 2 May 2024 15:56:59 -0600 Subject: [PATCH 41/93] Revert "Update DMA drivers to handle multiple instances" This reverts commit df0e56640da75070e9561fed270a9d16dbe6ee7f. --- .../PeriphDrivers/Include/MAX32657/dma.h | 76 +++++++++---------- .../PeriphDrivers/Include/MAX32657/mxc_sys.h | 2 + Libraries/PeriphDrivers/Source/DMA/dma_me30.c | 58 ++++---------- 3 files changed, 55 insertions(+), 81 deletions(-) diff --git a/Libraries/PeriphDrivers/Include/MAX32657/dma.h b/Libraries/PeriphDrivers/Include/MAX32657/dma.h index fb9c43273ac..747e5702681 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/dma.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/dma.h @@ -187,7 +187,6 @@ typedef mxc_dma_srcdst_t (*mxc_dma_trans_chain_t)(mxc_dma_srcdst_t dest); /*************************/ /** * @brief Initialize DMA resources - * @param dma Pointer to DMA registers. * @details This initialization is required before using the DMA driver functions. * @note On default this function enables DMA peripheral clock. * if you wish to manage clock and gpio related things in upper level instead of here. @@ -195,18 +194,15 @@ typedef mxc_dma_srcdst_t (*mxc_dma_trans_chain_t)(mxc_dma_srcdst_t dest); * By this flag this function will remove clock and gpio related codes from file. * @return #E_NO_ERROR if successful */ -int MXC_DMA_Init(mxc_dma_regs_t *dma); +int MXC_DMA_Init(void); /** * @brief De-Initialize DMA resources. - * - * @param dma Pointer to DMA registers. */ -void MXC_DMA_DeInit(mxc_dma_regs_t *dma); +void MXC_DMA_DeInit(void); /** * @brief Request DMA channel - * @param dma Pointer to DMA registers. * @details Returns a handle to the first free DMA channel, which can be used via API calls * or direct access to channel registers using the MXC_DMA_GetCHRegs(int ch) function. * @return Non-negative channel handle (inclusive of zero). @@ -214,13 +210,13 @@ void MXC_DMA_DeInit(mxc_dma_regs_t *dma); * @return #E_BAD_STATE DMA is not initialized, call MXC_DMA_Init() first. * @return #E_BUSY DMA is currently busy (locked), try again later. */ -int MXC_DMA_AcquireChannel(mxc_dma_regs_t *dma); +int MXC_DMA_AcquireChannel(void); /** * @brief Release DMA channel * @details Stops any DMA operation on the channel and returns it to the pool of free channels. * - * @param ch channel handle to release + * @param ch DMA channel to release * * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise */ @@ -264,7 +260,6 @@ int MXC_DMA_SetSrcDst(mxc_dma_srcdst_t srcdst); * * @return See \ref MXC_Error_Codes for a list of return values */ - int MXC_DMA_GetSrcDst(mxc_dma_srcdst_t *srcdst); /** @@ -285,12 +280,11 @@ int MXC_DMA_SetSrcReload(mxc_dma_srcdst_t srcdstReload); * * @return See \ref MXC_Error_Codes for a list of return values */ - int MXC_DMA_GetSrcReload(mxc_dma_srcdst_t *srcdstReload); /** * @brief Set channel interrupt callback - * @param ch channel handle + * @param ch DMA channel * @param callback Pointer to a function to call when the channel * interrupt flag is set and interrupts are enabled or * when DMA is shutdown by the driver. @@ -307,8 +301,8 @@ int MXC_DMA_GetSrcReload(mxc_dma_srcdst_t *srcdstReload); * reason is either #E_NO_ERROR for a DMA interrupt or #E_SHUTDOWN * if the DMA is being shutdown. * - * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR - * otherwise + * @return #E_BAD_PARAM if an unused or invalid channel handle, + * #E_NO_ERROR otherwise, \ref MXC_Error_Codes */ int MXC_DMA_SetCallback(int ch, void (*callback)(int, int)); @@ -317,7 +311,7 @@ int MXC_DMA_SetCallback(int ch, void (*callback)(int, int)); * @note Each channel has two interrupts (complete, and count to zero). * To enable complete, pass true for chdis. To enable count to zero, * pass true for ctz. - * @param ch Channel Handle + * @param ch DMA channel * @param chdis Enable channel complete interrupt * @param ctz Enable channel count to zero interrupt. * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise @@ -328,32 +322,36 @@ int MXC_DMA_SetChannelInterruptEn(int ch, bool chdis, bool ctz); * @brief Enable channel interrupt * @note Each channel has two interrupts (complete, and count to zero) which must also be enabled with MXC_DMA_SetChannelInterruptEn() - * @param ch channel handle + * @param ch DMA channel to enable interrupts for. * @param flags The flags to enable - * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise + * @return #E_BAD_PARAM if an unused or invalid channel handle, + * #E_NO_ERROR otherwise, \ref MXC_Error_Codes */ int MXC_DMA_ChannelEnableInt(int ch, int flags); /** * @brief Disable channel interrupt - * @param ch channel handle + * @param ch DMA channel to clear flags for. * @param flags The flags to disable - * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise + * @return #E_BAD_PARAM if an unused or invalid channel handle, + * #E_NO_ERROR otherwise, \ref MXC_Error_Codes */ int MXC_DMA_ChannelDisableInt(int ch, int flags); /** * @brief Read channel interrupt flags - * @param ch channel handle - * @return #E_BAD_PARAM if an unused or invalid channel handle, flags otherwise + * @param ch DMA channel to get interrupt status from. + * @return #E_BAD_PARAM if an unused or invalid channel handle, + * flags otherwise, \ref MXC_Error_Codes */ int MXC_DMA_ChannelGetFlags(int ch); /** * @brief Clear channel interrupt flags - * @param ch channel handle + * @param ch DMA channel to clear the interrupt flag for. * @param flags The flags to clear - * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise + * @return #E_BAD_PARAM if an unused or invalid channel handle, + * #E_NO_ERROR otherwise, \ref MXC_Error_Codes */ int MXC_DMA_ChannelClearFlags(int ch, int flags); @@ -361,36 +359,40 @@ int MXC_DMA_ChannelClearFlags(int ch, int flags); * @brief Enable channel interrupt * @note Each channel has two interrupts (complete, and count to zero) which must also be enabled with MXC_DMA_SetChannelInterruptEn() - * @param ch channel handle - * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise + * @param ch DMA channel to enable interrupts for. + * @return #E_BAD_PARAM if an unused or invalid channel handle, + * #E_NO_ERROR otherwise, \ref MXC_Error_Codes */ int MXC_DMA_EnableInt(int ch); /** * @brief Disable channel interrupt - * @param ch channel handle - * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise + * @param ch DMA channel to disable interrupts for. + * @return #E_BAD_PARAM if an unused or invalid channel handle, + * #E_NO_ERROR otherwise, \ref MXC_Error_Codes */ int MXC_DMA_DisableInt(int ch); /** * @brief Start transfer - * @param ch channel handle - * @note Start the DMA channel transfer, assumes that MXC_DMA_SetSrcDstCnt() has been called beforehand. - * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise + * @param ch DMA channel + * @details Start the DMA channel transfer, assumes that MXC_DMA_SetSrcDstCnt() has been called beforehand. + * @return #E_BAD_PARAM if an unused or invalid channel handle, + * #E_NO_ERROR otherwise, \ref MXC_Error_Codes */ int MXC_DMA_Start(int ch); /** * @brief Stop DMA transfer, irrespective of status (complete or in-progress) - * @param ch channel handle - * @return #E_BAD_PARAM if an unused or invalid channel handle, #E_NO_ERROR otherwise + * @param ch DMA channel + * @return #E_BAD_PARAM if an unused or invalid channel handle, + * #E_NO_ERROR otherwise, \ref MXC_Error_Codes */ int MXC_DMA_Stop(int ch); /** * @brief Get a pointer to the DMA channel registers - * @param ch channel handle + * @param ch DMA channel * @note If direct access to DMA channel registers is required, this * function can be used on a channel handle returned by MXC_DMA_AcquireChannel(). * @return NULL if an unused or invalid channel handle, or a valid pointer otherwise @@ -399,11 +401,10 @@ mxc_dma_ch_regs_t *MXC_DMA_GetCHRegs(int ch); /** * @brief Interrupt handler function - * @param dma Pointer to DMA registers. * @details Call this function as the ISR for each DMA channel under driver control. * Interrupt flags for channel ch will be automatically cleared before return. */ -void MXC_DMA_Handler(mxc_dma_regs_t *dma); +void MXC_DMA_Handler(void); /*************************/ /* High Level Functions */ @@ -414,7 +415,6 @@ void MXC_DMA_Handler(mxc_dma_regs_t *dma); * @note The user must have the DMA interrupt enabled and call * MXC_DMA_Handler() from the ISR. * - * @param dma Pointer to DMA registers. * @param dest pointer to destination memory * @param src pointer to source memory * @param len number of bytes to copy @@ -422,22 +422,20 @@ void MXC_DMA_Handler(mxc_dma_regs_t *dma); * * @return see \ref MXC_Error_Codes */ -int MXC_DMA_MemCpy(mxc_dma_regs_t *dma, void *dest, void *src, int len, - mxc_dma_complete_cb_t callback); +int MXC_DMA_MemCpy(void *dest, void *src, int len, mxc_dma_complete_cb_t callback); /** * @brief Performs a memcpy, using DMA, optionally asynchronous * @note The user must have the DMA interrupt enabled and call * MXC_DMA_Handler() from the ISR. * - * @param dma Pointer to DMA registers. * @param config The channel config struct * @param firstSrcDst The source, destination, and count for the first transfer * @param callback function is called when transfer is complete * * @return see \ref MXC_Error_Codes */ -int MXC_DMA_DoTransfer(mxc_dma_regs_t *dma, mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, +int MXC_DMA_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback); /** * For other functional uses of DMA (UART, SPI, etc) see the appropriate peripheral driver diff --git a/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h b/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h index 9a50c8fd720..def4ee9b925 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h @@ -91,6 +91,8 @@ typedef enum { /* PCLKDIS1 Below this line we add 32 to separate PCLKDIS0 and PCLKDIS1 */ MXC_SYS_PERIPH_CLOCK_TRNG = (MXC_F_GCR_PCLKDIS1_TRNG_POS + 32), /**< Disable TRNG clock */ + // MXC_SYS_PERIPH_CLOCK_SMPHR = + // (MXC_F_GCR_PCLKDIS1_SMPHR_POS + 32), /**< Disable SMPHR clock */ MXC_SYS_PERIPH_CLOCK_CRC = (MXC_F_GCR_PCLKDIS1_CRC_POS + 32), /**< Disable CRC clock */ MXC_SYS_PERIPH_CLOCK_AES = diff --git a/Libraries/PeriphDrivers/Source/DMA/dma_me30.c b/Libraries/PeriphDrivers/Source/DMA/dma_me30.c index 82a4c3ccc26..a0483bd536d 100644 --- a/Libraries/PeriphDrivers/Source/DMA/dma_me30.c +++ b/Libraries/PeriphDrivers/Source/DMA/dma_me30.c @@ -32,50 +32,26 @@ /****** Functions ******/ -static mxc_dma_regs_t *getDMAInstance(int ch) -{ - if (ch < (MXC_DMA_CHANNELS / MXC_DMA_INSTANCES)) { - return MXC_DMA0; - } else if (ch >= (MXC_DMA_CHANNELS / MXC_DMA_INSTANCES) && ch < MXC_DMA_CHANNELS) { - return MXC_DMA1; - } - - return NULL; -} - -int MXC_DMA_Init(mxc_dma_regs_t *dma) +int MXC_DMA_Init(void) { #ifndef MSDK_NO_GPIO_CLK_INIT - switch (MXC_DMA_GET_IDX(dma)) { - case 0: - if (!MXC_SYS_IsClockEnabled(MXC_SYS_PERIPH_CLOCK_DMA0)) { - MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_DMA0); - MXC_SYS_Reset_Periph(MXC_SYS_RESET0_DMA0); - } - break; - case 1: - // TODO(ME30): PERIPH CLOCK register definitions missing for DMA1 - //if (!MXC_SYS_IsClockEnabled(MXC_SYS_PERIPH_CLOCK)) { - // MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_DMA1); - MXC_SYS_Reset_Periph(MXC_SYS_RESET0_DMA1); - // } - break; - default: - return E_BAD_PARAM; + if (!MXC_SYS_IsClockEnabled(MXC_SYS_PERIPH_CLOCK_DMA)) { + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_DMA); + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_DMA); } #endif - return MXC_DMA_RevA_Init((mxc_dma_reva_regs_t *)dma); + return MXC_DMA_RevA_Init((mxc_dma_reva_regs_t *)MXC_DMA); } -void MXC_DMA_DeInit(mxc_dma_regs_t *dma) +void MXC_DMA_DeInit(void) { - return MXC_DMA_RevA_DeInit((mxc_dma_reva_regs_t *)dma); + return MXC_DMA_RevA_DeInit((mxc_dma_reva_regs_t *)MXC_DMA); } int MXC_DMA_AcquireChannel(void) { - return MXC_DMA_RevA_AcquireChannel((mxc_dma_reva_regs_t *)dma); + return MXC_DMA_RevA_AcquireChannel((mxc_dma_reva_regs_t *)MXC_DMA); } int MXC_DMA_ReleaseChannel(int ch) @@ -145,14 +121,12 @@ int MXC_DMA_ChannelClearFlags(int ch, int flags) int MXC_DMA_EnableInt(int ch) { - mxc_dma_regs_t *dma = getDMAInstance(ch); - return MXC_DMA_RevA_EnableInt((mxc_dma_reva_regs_t *)dma, ch); + return MXC_DMA_RevA_EnableInt((mxc_dma_reva_regs_t *)MXC_DMA, ch); } int MXC_DMA_DisableInt(int ch) { - mxc_dma_regs_t *dma = getDMAInstance(ch); - return MXC_DMA_RevA_DisableInt((mxc_dma_reva_regs_t *)dma, ch); + return MXC_DMA_RevA_DisableInt((mxc_dma_reva_regs_t *)MXC_DMA, ch); } int MXC_DMA_Start(int ch) @@ -170,18 +144,18 @@ mxc_dma_ch_regs_t *MXC_DMA_GetCHRegs(int ch) return MXC_DMA_RevA_GetCHRegs(ch); } -void MXC_DMA_Handler(mxc_dma_regs_t *dma) +void MXC_DMA_Handler(void) { - MXC_DMA_RevA_Handler((mxc_dma_reva_regs_t *)dma); + MXC_DMA_RevA_Handler((mxc_dma_reva_regs_t *)MXC_DMA); } -int MXC_DMA_MemCpy(mxc_dma_regs_t *dma, void *dest, void *src, int len, mxc_dma_complete_cb_t callback) +int MXC_DMA_MemCpy(void *dest, void *src, int len, mxc_dma_complete_cb_t callback) { - return MXC_DMA_RevA_MemCpy((mxc_dma_reva_regs_t *)dma, dest, src, len, callback); + return MXC_DMA_RevA_MemCpy((mxc_dma_reva_regs_t *)MXC_DMA, dest, src, len, callback); } -int MXC_DMA_DoTransfer(mxc_dma_regs_t *dma, mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, +int MXC_DMA_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback) { - return MXC_DMA_RevA_DoTransfer((mxc_dma_reva_regs_t *)dma, config, firstSrcDst, callback); + return MXC_DMA_RevA_DoTransfer((mxc_dma_reva_regs_t *)MXC_DMA, config, firstSrcDst, callback); } From 9644b4e4908da853107cee38a7ff4a39e7cda4fd Mon Sep 17 00:00:00 2001 From: Jake Carter Date: Thu, 2 May 2024 16:11:01 -0600 Subject: [PATCH 42/93] Use built-in -mcmse GCC flag for indicating secure builds - Add to max32657.h - Define "IS_SECURE_ENVIRONMENT" that uses GCC-provided definitions instead of our custom build-time one. Usage: #if IS_SECURE_ENVIRONMENT ... #endif --- Libraries/CMSIS/Device/Maxim/GCC/gcc.mk | 7 ++++++- .../CMSIS/Device/Maxim/MAX32657/Include/max32657.h | 10 ++++------ 2 files changed, 10 insertions(+), 7 deletions(-) diff --git a/Libraries/CMSIS/Device/Maxim/GCC/gcc.mk b/Libraries/CMSIS/Device/Maxim/GCC/gcc.mk index 13406a0a04f..48acf971c44 100644 --- a/Libraries/CMSIS/Device/Maxim/GCC/gcc.mk +++ b/Libraries/CMSIS/Device/Maxim/GCC/gcc.mk @@ -272,7 +272,12 @@ ifeq "$(MCPU)" "cortex-m33" # at compile time. MSECURITY_MODE ?= SECURE -PROJ_CFLAGS += -DMSECURITY_MODE_$(MSECURITY_MODE) +ifeq "$(MSECURITY_MODE)" "SECURE" +# Tell the compiler we are building a secure project. This is required to satisfy the requirements +# defined in "Armv8-M Security Extension: Requirements on Developments Tools" +# https://developer.arm.com/documentation/ecm0359818/latest +PROJ_CFLAGS += -mcmse +endif endif # Float ABI options: diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h index cfff0a47210..ce7f2cfb633 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h @@ -152,6 +152,8 @@ typedef enum { #define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ #include +#include +#define IS_SECURE_ENVIRONMENT (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)) /* ================================================================================ */ /* ================== Device Specific Memory Section ================== */ @@ -621,17 +623,13 @@ We may want to handle GET_IRQ better... #define MXC_UART_S_GET_UART(i) ((i) == 0 ? MXC_UART_S : 0) #define MXC_UART_S_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0_S : 0) -#ifdef MSECURITY_MODE_SECURE +#if IS_SECURE_ENVIRONMENT #define MXC_BASE_UART MXC_BASE_UART_S #define MXC_UART MXC_UART_S - #define MXC_UART_GET_UART(i) MXC_UART_S_GET_UART(i) -#endif - -#ifdef MSECURITY_MODE_NONSECURE +#else #define MXC_BASE_UART MXC_BASE_UART_NS #define MXC_UART MXC_UART_NS - #define MXC_UART_GET_UART(i) MXC_UART_NS_GET_UART(i) #endif From bc0648dcc3f2dc3319f3a0ea700234cc42cabc61 Mon Sep 17 00:00:00 2001 From: Jake Carter Date: Thu, 2 May 2024 16:28:40 -0600 Subject: [PATCH 43/93] Update ME30 DMA drivers and macros --- .../Device/Maxim/MAX32657/Include/max32657.h | 26 ++++++++++++++----- Libraries/PeriphDrivers/Source/DMA/dma_me30.c | 11 +++++--- 2 files changed, 28 insertions(+), 9 deletions(-) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h index ce7f2cfb633..c30c5af857d 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h @@ -560,25 +560,39 @@ We may want to handle GET_IRQ better... /* Non-secure Mapping */ #define MXC_BASE_DMA0_NS ((uint32_t)0x40028000UL) #define MXC_DMA0_NS ((mxc_dma_regs_t *)MXC_BASE_DMA0_NS) -/* DMA1 instance only for secure mode. */ +/* DMA0 instance only for secure mode. */ /* Secure Mapping */ +// TODO(ME30): Is there actuall a secure mapping for DMA0? #define MXC_BASE_DMA0_S ((uint32_t)0x50028000UL) #define MXC_DMA0_S ((mxc_dma_regs_t *)MXC_BASE_DMA0_S) #define MXC_BASE_DMA1_S ((uint32_t)0x50035000UL) #define MXC_DMA1_S ((mxc_dma_regs_t *)MXC_BASE_DMA1_S) #define MXC_BASE_DMA0 MXC_BASE_DMA0_S -#define MXC_DMA0 MXC_DMA0_S +#define MXC_DMA0 MXC_DMA0_NS #define MXC_BASE_DMA1 MXC_BASE_DMA1_S #define MXC_DMA1 MXC_DMA1_S +#if IS_SECURE_ENVIRONMENT +#define MXC_DMA MXC_DMA1_S +#define MXC_DMA_CH_GET_IRQ(i) \ + ((IRQn_Type)(((i) == 0) ? DMA1_CH0_IRQn : \ + ((i) == 1) ? DMA1_CH1_IRQn : \ + ((i) == 2) ? DMA1_CH2_IRQn : \ + ((i) == 3) ? DMA1_CH3_IRQn : \ + 0)) +#else +#define MXC_DMA MXC_DMA0_NS #define MXC_DMA_CH_GET_IRQ(i) \ - ((IRQn_Type)(((i) == 0) ? DMA0_IRQn : \ - ((i) == 1) ? DMA1_IRQn : \ - ((i) == 2) ? DMA2_IRQn : \ - ((i) == 3) ? DMA3_IRQn : \ + ((IRQn_Type)(((i) == 0) ? DMA0_CH0_IRQn : \ + ((i) == 1) ? DMA0_CH1_IRQn : \ + ((i) == 2) ? DMA0_CH2_IRQn : \ + ((i) == 3) ? DMA0_CH3_IRQn : \ 0)) +#endif + +#define MXC_DMA_GET_IDX(p) ((p) == MXC_DMA0 ? 0 : (p) == MXC_DMA1 ? 1 : -1) /******************************************************************************/ /* Flash Controller */ diff --git a/Libraries/PeriphDrivers/Source/DMA/dma_me30.c b/Libraries/PeriphDrivers/Source/DMA/dma_me30.c index a0483bd536d..bab48e3c5e9 100644 --- a/Libraries/PeriphDrivers/Source/DMA/dma_me30.c +++ b/Libraries/PeriphDrivers/Source/DMA/dma_me30.c @@ -35,10 +35,15 @@ int MXC_DMA_Init(void) { #ifndef MSDK_NO_GPIO_CLK_INIT - if (!MXC_SYS_IsClockEnabled(MXC_SYS_PERIPH_CLOCK_DMA)) { - MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_DMA); - MXC_SYS_Reset_Periph(MXC_SYS_RESET0_DMA); + if (MXC_DMA == MXC_DMA0 && !MXC_SYS_IsClockEnabled(MXC_SYS_PERIPH_CLOCK_DMA0)) { + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_DMA0); + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_DMA0); } + // TODO(ME30): There is no periph clock enable register for DMA1 atm + // else if (MXC_DMA == MXC_DMA1 && !MXC_SYS_IsClockEnabled(MXC_SYS_PERIPH_CLOCK_DMA1)) + // MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_DMA1); + // MXC_SYS_Reset_Periph(MXC_SYS_RESET0_DMA1); + // } #endif return MXC_DMA_RevA_Init((mxc_dma_reva_regs_t *)MXC_DMA); From 80b7343a9a203e82acf6717b1f93e950208232de Mon Sep 17 00:00:00 2001 From: Jake Carter Date: Thu, 2 May 2024 16:38:41 -0600 Subject: [PATCH 44/93] Update ME30 FLC drivers and macros --- .../Device/Maxim/MAX32657/Include/max32657.h | 4 + Libraries/PeriphDrivers/Source/FLC/flc_me30.c | 95 ++++--------------- 2 files changed, 24 insertions(+), 75 deletions(-) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h index c30c5af857d..1a6b87a7921 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h @@ -606,6 +606,10 @@ We may want to handle GET_IRQ better... #define MXC_BASE_FLC_S MXC_BASE_FLC #define MXC_FLC_S MXC_FLC +// Note(JC): There is only one flash instance, but some bottom-level RevX implementations +// depend on MXC_FLC_GET_FLC +#define MXC_FLC_GET_FLC(i) MXC_FLC + /******************************************************************************/ /* Internal Cache Controller */ #define MXC_ICC_INSTANCES (1) diff --git a/Libraries/PeriphDrivers/Source/FLC/flc_me30.c b/Libraries/PeriphDrivers/Source/FLC/flc_me30.c index 961a912434c..fa8f12b072e 100644 --- a/Libraries/PeriphDrivers/Source/FLC/flc_me30.c +++ b/Libraries/PeriphDrivers/Source/FLC/flc_me30.c @@ -27,7 +27,7 @@ #include "mcr_regs.h" // For ECCEN registers. //****************************************************************************** -void MXC_FLC_ME17_Flash_Operation(void) +void MXC_FLC_ME30_Flash_Operation(void) { /* This function should be called after modifying the contents of flash memory. @@ -44,10 +44,10 @@ void MXC_FLC_ME17_Flash_Operation(void) */ /* Flush all instruction caches */ - MXC_GCR->sysctrl |= MXC_F_GCR_SYSCTRL_ICC0_FLUSH; + MXC_GCR->sysctrl |= MXC_F_GCR_SYSCTRL_ICC_FLUSH; /* Wait for flush to complete */ - while (MXC_GCR->sysctrl & MXC_F_GCR_SYSCTRL_ICC0_FLUSH) {} + while (MXC_GCR->sysctrl & MXC_F_GCR_SYSCTRL_ICC_FLUSH) {} // Clear the line fill buffer by reading 2 pages from flash volatile uint32_t *line_addr; @@ -59,21 +59,7 @@ void MXC_FLC_ME17_Flash_Operation(void) } //****************************************************************************** -int MXC_FLC_ME17_GetByAddress(mxc_flc_regs_t **flc, uint32_t addr) -{ - if ((addr >= MXC_FLASH_MEM_BASE) && (addr < (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE))) { - *flc = MXC_FLC0; - } else if ((addr >= MXC_INFO_MEM_BASE) && (addr < (MXC_INFO_MEM_BASE + MXC_INFO_MEM_SIZE))) { - *flc = MXC_FLC0; - } else { - return E_BAD_PARAM; - } - - return E_NO_ERROR; -} - -//****************************************************************************** -int MXC_FLC_ME17_GetPhysicalAddress(uint32_t addr, uint32_t *result) +int MXC_FLC_ME30_GetPhysicalAddress(uint32_t addr, uint32_t *result) { if ((addr >= MXC_FLASH_MEM_BASE) && (addr < (MXC_FLASH_MEM_BASE + MXC_FLASH_MEM_SIZE))) { *result = addr & (MXC_FLASH_MEM_SIZE - 1); @@ -113,21 +99,15 @@ int MXC_FLC_PageErase(uint32_t address) { int err; uint32_t addr; - mxc_flc_regs_t *flc = NULL; - // Get FLC Instance - if ((err = MXC_FLC_ME17_GetByAddress(&flc, address)) != E_NO_ERROR) { + if ((err = MXC_FLC_ME30_GetPhysicalAddress(address, &addr)) < E_NO_ERROR) { return err; } - if ((err = MXC_FLC_ME17_GetPhysicalAddress(address, &addr)) < E_NO_ERROR) { - return err; - } - - err = MXC_FLC_RevA_PageErase((mxc_flc_reva_regs_t *)flc, addr); + err = MXC_FLC_RevA_PageErase((mxc_flc_reva_regs_t *)MXC_FLC, addr); // Flush the cache - MXC_FLC_ME17_Flash_Operation(); + MXC_FLC_ME30_Flash_Operation(); return err; } @@ -142,7 +122,6 @@ __attribute__((section(".flashprog"))) int MXC_FLC_Write128(uint32_t address, uint32_t *data) { int err; - mxc_flc_regs_t *flc = NULL; uint32_t addr; // Address checked if it is 128-bit aligned @@ -150,19 +129,14 @@ int MXC_FLC_Write128(uint32_t address, uint32_t *data) return E_BAD_PARAM; } - // Get FLC Instance - if ((err = MXC_FLC_ME17_GetByAddress(&flc, address)) != E_NO_ERROR) { + if ((err = MXC_FLC_ME30_GetPhysicalAddress(address, &addr)) < E_NO_ERROR) { return err; } - if ((err = MXC_FLC_ME17_GetPhysicalAddress(address, &addr)) < E_NO_ERROR) { - return err; - } - - err = MXC_FLC_RevA_Write128((mxc_flc_reva_regs_t *)flc, addr, data); + err = MXC_FLC_RevA_Write128((mxc_flc_reva_regs_t *)MXC_FLC, addr, data); // Flush the cache - MXC_FLC_ME17_Flash_Operation(); + MXC_FLC_ME30_Flash_Operation(); return err; } @@ -172,7 +146,6 @@ int MXC_FLC_Write32(uint32_t address, uint32_t data) { uint32_t addr, aligned; int err; - mxc_flc_regs_t *flc = NULL; // Address checked if it is byte addressable if (address & 0x3) { @@ -182,19 +155,14 @@ int MXC_FLC_Write32(uint32_t address, uint32_t data) // Align address to 128-bit word aligned = address & 0xfffffff0; - // Get FLC Instance - if ((err = MXC_FLC_ME17_GetByAddress(&flc, address)) != E_NO_ERROR) { + if ((err = MXC_FLC_ME30_GetPhysicalAddress(aligned, &addr)) < E_NO_ERROR) { return err; } - if ((err = MXC_FLC_ME17_GetPhysicalAddress(aligned, &addr)) < E_NO_ERROR) { - return err; - } - - err = MXC_FLC_RevA_Write32Using128((mxc_flc_reva_regs_t *)flc, address, data, addr); + err = MXC_FLC_RevA_Write32Using128((mxc_flc_reva_regs_t *)MXC_FLC, address, data, addr); // Flush the cache - MXC_FLC_ME17_Flash_Operation(); + MXC_FLC_ME30_Flash_Operation(); return err; } @@ -202,49 +170,26 @@ int MXC_FLC_Write32(uint32_t address, uint32_t data) //****************************************************************************** int MXC_FLC_MassErase(void) { - int err, i; - mxc_flc_regs_t *flc; - - for (i = 0; i < MXC_FLC_INSTANCES; i++) { - flc = MXC_FLC_GET_FLC(i); - - err = MXC_FLC_RevA_MassErase((mxc_flc_reva_regs_t *)flc); + int err; - // Flush the cache - MXC_FLC_ME17_Flash_Operation(); + err = MXC_FLC_RevA_MassErase((mxc_flc_reva_regs_t *)MXC_FLC); - if (err != E_NO_ERROR) { - return err; - } - } + // Flush the cache + MXC_FLC_ME30_Flash_Operation(); - return E_NO_ERROR; + return err; } //****************************************************************************** int MXC_FLC_UnlockInfoBlock(uint32_t address) { - int err; - mxc_flc_regs_t *flc; - - if ((err = MXC_FLC_ME17_GetByAddress(&flc, address)) != E_NO_ERROR) { - return err; - } - - return MXC_FLC_RevA_UnlockInfoBlock((mxc_flc_reva_regs_t *)flc, address); + return MXC_FLC_RevA_UnlockInfoBlock((mxc_flc_reva_regs_t *)MXC_FLC, address); } //****************************************************************************** int MXC_FLC_LockInfoBlock(uint32_t address) { - int err; - mxc_flc_regs_t *flc; - - if ((err = MXC_FLC_ME17_GetByAddress(&flc, address)) != E_NO_ERROR) { - return err; - } - - return MXC_FLC_RevA_LockInfoBlock((mxc_flc_reva_regs_t *)flc, address); + return MXC_FLC_RevA_LockInfoBlock((mxc_flc_reva_regs_t *)MXC_FLC, address); } //****************************************************************************** From 3910ebe40849dc821d8dbd4ab886ad8a711c6638 Mon Sep 17 00:00:00 2001 From: Jake Carter Date: Thu, 2 May 2024 16:49:13 -0600 Subject: [PATCH 45/93] Update ME30 GPIO drivers and macros --- .../Device/Maxim/MAX32657/Include/max32657.h | 29 ++- .../PeriphDrivers/Source/GPIO/gpio_me30.c | 246 +++--------------- 2 files changed, 56 insertions(+), 219 deletions(-) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h index 1a6b87a7921..6dc05068db9 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h @@ -387,19 +387,6 @@ typedef enum { #define MXC_CFG_GPIO_INSTANCES (1) #define MXC_CFG_GPIO_PINS_PORT (32) -/* Utility macros - -Note(JC): There is only 1 GPIO instance, but for driver compatibility these must be -implemented. - -For GET_IDX and GET_GPIO we return -1 so that other MXC_ASSERTs might error out. -For GET_IRQ we follow precedent and return the base 0 IRQn, which is the ICE unlock. -We may want to handle GET_IRQ better... -*/ -#define MXC_GPIO_GET_IDX(p) ((p) == MXC_GPIO0 ? 0 : -1) -#define MXC_GPIO_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0 : -1) -#define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO0_IRQn : (IRQn_Type)0) - /* Non-secure Mapping */ #define MXC_BASE_GPIO0_NS ((uint32_t)0x40008000UL) #define MXC_GPIO0_NS ((mxc_gpio_regs_t *)MXC_BASE_GPIO0_NS) @@ -412,7 +399,23 @@ We may want to handle GET_IRQ better... #define MXC_GPIO0_S ((mxc_gpio_regs_t *)MXC_BASE_GPIO0_S) #define MXC_BASE_GPIO0 MXC_BASE_GPIO0_S + +#if IS_SECURE_ENVIRONMENT #define MXC_GPIO0 MXC_GPIO0_S +#else +#define MXC_GPIO0 MXC_GPIO0_NS +#endif + +/* +Note(JC): There is only 1 GPIO instance, but for driver compatibility these must be +implemented. + +For GET_IRQ we follow precedent and return the base 0 IRQn, which is the ICE unlock. +We may want to handle GET_IRQ better... +*/ +#define MXC_GPIO_GET_IDX(p) ((p) == MXC_GPIO0 ? 0 : 0) +#define MXC_GPIO_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0 : 0) +#define MXC_GPIO_GET_IRQ(i) ((i) == 0 ? GPIO0_IRQn : (IRQn_Type)0) /******************************************************************************/ /* CRC */ diff --git a/Libraries/PeriphDrivers/Source/GPIO/gpio_me30.c b/Libraries/PeriphDrivers/Source/GPIO/gpio_me30.c index 5b3312315d7..bddc113d0b0 100644 --- a/Libraries/PeriphDrivers/Source/GPIO/gpio_me30.c +++ b/Libraries/PeriphDrivers/Source/GPIO/gpio_me30.c @@ -24,7 +24,6 @@ #include "gpio_reva.h" #include "gpio_common.h" #include "mxc_sys.h" -#include "lpgcr_regs.h" #include "mcr_regs.h" #include "pwrseq_regs.h" @@ -53,14 +52,6 @@ int MXC_GPIO_Init(uint32_t portmask) MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO0); } - if (portmask & 0x2) { - MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO1); - } - - if (portmask & 0x4) { - MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_GPIO2); - } - return MXC_GPIO_Common_Init(portmask); } @@ -70,14 +61,6 @@ int MXC_GPIO_Shutdown(uint32_t portmask) MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_GPIO0); } - if (portmask & 0x2) { - MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_GPIO1); - } - - if (portmask & 0x4) { - MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_GPIO2); - } - return E_NO_ERROR; } @@ -87,14 +70,6 @@ int MXC_GPIO_Reset(uint32_t portmask) MXC_SYS_Reset_Periph(MXC_SYS_RESET0_GPIO0); } - if (portmask & 0x2) { - MXC_SYS_Reset_Periph(MXC_SYS_RESET0_GPIO1); - } - - if (portmask & 0x4) { - MXC_SYS_Reset_Periph(MXC_SYS_RESET_GPIO2); - } - return E_NO_ERROR; } @@ -118,88 +93,46 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) return error; } - if (cfg->port == MXC_GPIO3) { - switch (cfg->func) { - case MXC_GPIO_FUNC_IN: - MXC_MCR->gpio3_ctrl &= ~(P30_OUT_EN(cfg->mask) | P31_OUT_EN(cfg->mask)); - MXC_MCR->outen &= ~(SQWAVE_OUT_EN(cfg->mask) | PDOWN_OUT_EN(cfg->mask)); - break; - - case MXC_GPIO_FUNC_OUT: - MXC_MCR->gpio3_ctrl |= P30_OUT_EN(cfg->mask) | P31_OUT_EN(cfg->mask); - MXC_MCR->outen &= ~(SQWAVE_OUT_EN(cfg->mask) | PDOWN_OUT_EN(cfg->mask)); - break; - - case MXC_GPIO_FUNC_ALT1: - MXC_MCR->gpio3_ctrl |= P30_OUT_EN(cfg->mask) | P31_OUT_EN(cfg->mask); - MXC_MCR->outen |= SQWAVE_OUT_EN(cfg->mask) | PDOWN_OUT_EN(cfg->mask); - break; - - default: - return E_NOT_SUPPORTED; - } - - switch (cfg->pad) { - case MXC_GPIO_PAD_NONE: - MXC_MCR->gpio3_ctrl |= P30_PULL_DIS(cfg->mask) | P31_PULL_DIS(cfg->mask); - break; - - case MXC_GPIO_PAD_PULL_UP: - case MXC_GPIO_PAD_WEAK_PULL_UP: - MXC_MCR->gpio3_ctrl |= P30_DATA_OUT(cfg->mask) | P31_DATA_OUT(cfg->mask); - MXC_MCR->gpio3_ctrl &= ~(P30_PULL_DIS(cfg->mask) | P31_PULL_DIS(cfg->mask)); - break; - - case MXC_GPIO_PAD_PULL_DOWN: - case MXC_GPIO_PAD_WEAK_PULL_DOWN: - MXC_MCR->gpio3_ctrl &= ~(P30_DATA_OUT(cfg->mask) | P31_DATA_OUT(cfg->mask)); - MXC_MCR->gpio3_ctrl &= ~(P30_PULL_DIS(cfg->mask) | P31_PULL_DIS(cfg->mask)); - break; - - default: - return E_NOT_SUPPORTED; - } - } else { - // Configure alternate function - error = MXC_GPIO_RevA_SetAF((mxc_gpio_reva_regs_t *)gpio, cfg->func, cfg->mask); - if (error != E_NO_ERROR) { - return error; - } - - // Configure the pad - switch (cfg->pad) { - case MXC_GPIO_PAD_NONE: - gpio->padctrl0 &= ~cfg->mask; - gpio->padctrl1 &= ~cfg->mask; - break; - - case MXC_GPIO_PAD_WEAK_PULL_UP: - gpio->padctrl0 |= cfg->mask; - gpio->padctrl1 &= ~cfg->mask; - gpio->ps &= ~cfg->mask; - break; - - case MXC_GPIO_PAD_PULL_UP: - gpio->padctrl0 |= cfg->mask; - gpio->padctrl1 &= ~cfg->mask; - gpio->ps |= cfg->mask; - break; - - case MXC_GPIO_PAD_WEAK_PULL_DOWN: - gpio->padctrl0 &= ~cfg->mask; - gpio->padctrl1 |= cfg->mask; - gpio->ps &= ~cfg->mask; - break; - - case MXC_GPIO_PAD_PULL_DOWN: - gpio->padctrl0 &= ~cfg->mask; - gpio->padctrl1 |= cfg->mask; - gpio->ps |= cfg->mask; - break; - - default: - return E_BAD_PARAM; - } + // Configure alternate function + error = MXC_GPIO_RevA_SetAF((mxc_gpio_reva_regs_t *)gpio, cfg->func, cfg->mask); + if (error != E_NO_ERROR) { + return error; + } + + // Configure the pad + // TODO(ME30): "ps" (weak vs strong pull-up/down select) register field missing + switch (cfg->pad) { + case MXC_GPIO_PAD_NONE: + gpio->padctrl0 &= ~cfg->mask; + gpio->padctrl1 &= ~cfg->mask; + break; + + case MXC_GPIO_PAD_WEAK_PULL_UP: + gpio->padctrl0 |= cfg->mask; + gpio->padctrl1 &= ~cfg->mask; + // gpio->ps &= ~cfg->mask; + break; + + case MXC_GPIO_PAD_PULL_UP: + gpio->padctrl0 |= cfg->mask; + gpio->padctrl1 &= ~cfg->mask; + // gpio->ps |= cfg->mask; + break; + + case MXC_GPIO_PAD_WEAK_PULL_DOWN: + gpio->padctrl0 &= ~cfg->mask; + gpio->padctrl1 |= cfg->mask; + // gpio->ps &= ~cfg->mask; + break; + + case MXC_GPIO_PAD_PULL_DOWN: + gpio->padctrl0 &= ~cfg->mask; + gpio->padctrl1 |= cfg->mask; + // gpio->ps |= cfg->mask; + break; + + default: + return E_BAD_PARAM; } // Configure the drive strength @@ -213,122 +146,54 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) /* ************************************************************************** */ uint32_t MXC_GPIO_InGet(mxc_gpio_regs_t *port, uint32_t mask) { - uint32_t in = 0; - - if (port == MXC_GPIO3) { - if (MXC_MCR->gpio3_ctrl & P30_DATA_IN(mask)) { - in |= MXC_GPIO_PIN_0; - } - - if (MXC_MCR->gpio3_ctrl & P31_DATA_IN(mask)) { - in |= MXC_GPIO_PIN_1; - } - - return in; - } - return MXC_GPIO_RevA_InGet((mxc_gpio_reva_regs_t *)port, mask); } /* ************************************************************************** */ void MXC_GPIO_OutSet(mxc_gpio_regs_t *port, uint32_t mask) { - if (port == MXC_GPIO3) { - MXC_MCR->gpio3_ctrl |= P30_DATA_OUT(mask) | P31_DATA_OUT(mask); - return; - } - MXC_GPIO_RevA_OutSet((mxc_gpio_reva_regs_t *)port, mask); } /* ************************************************************************** */ void MXC_GPIO_OutClr(mxc_gpio_regs_t *port, uint32_t mask) { - if (port == MXC_GPIO3) { - MXC_MCR->gpio3_ctrl &= ~(P30_DATA_OUT(mask) | P31_DATA_OUT(mask)); - return; - } - MXC_GPIO_RevA_OutClr((mxc_gpio_reva_regs_t *)port, mask); } /* ************************************************************************** */ uint32_t MXC_GPIO_OutGet(mxc_gpio_regs_t *port, uint32_t mask) { - uint32_t out = 0; - - if (port == MXC_GPIO3) { - if (MXC_MCR->gpio3_ctrl & P30_DATA_OUT(mask)) { - out |= MXC_GPIO_PIN_0; - } - - if (MXC_MCR->gpio3_ctrl & P31_DATA_OUT(mask)) { - out |= MXC_GPIO_PIN_1; - } - - return out; - } - return MXC_GPIO_RevA_OutGet((mxc_gpio_reva_regs_t *)port, mask); } /* ************************************************************************** */ void MXC_GPIO_OutPut(mxc_gpio_regs_t *port, uint32_t mask, uint32_t val) { - if (port == MXC_GPIO3) { - uint32_t gpio3_cp = MXC_MCR->gpio3_ctrl & ~(P30_DATA_OUT(mask) | P31_DATA_OUT(mask)); - - MXC_MCR->gpio3_ctrl = gpio3_cp | P30_DATA_OUT((mask & val)) | P31_DATA_OUT((mask & val)); - return; - } - MXC_GPIO_RevA_OutPut((mxc_gpio_reva_regs_t *)port, mask, val); } /* ************************************************************************** */ void MXC_GPIO_OutToggle(mxc_gpio_regs_t *port, uint32_t mask) { - if (port == MXC_GPIO3) { - MXC_MCR->gpio3_ctrl ^= P30_DATA_OUT(mask) | P31_DATA_OUT(mask); - return; - } - MXC_GPIO_RevA_OutToggle((mxc_gpio_reva_regs_t *)port, mask); } /* ************************************************************************** */ int MXC_GPIO_IntConfig(const mxc_gpio_cfg_t *cfg, mxc_gpio_int_pol_t pol) { - if (cfg->port == MXC_GPIO3) { - if (pol != MXC_GPIO_INT_BOTH) { - return E_NOT_SUPPORTED; - } - - return E_NO_ERROR; - } - return MXC_GPIO_RevA_IntConfig(cfg, pol); } /* ************************************************************************** */ void MXC_GPIO_EnableInt(mxc_gpio_regs_t *port, uint32_t mask) { - if (port == MXC_GPIO3) { - MXC_PWRSEQ->lpwken3 |= mask; - return; - } - MXC_GPIO_RevA_EnableInt((mxc_gpio_reva_regs_t *)port, mask); } /* ************************************************************************** */ void MXC_GPIO_DisableInt(mxc_gpio_regs_t *port, uint32_t mask) { - if (port == MXC_GPIO3) { - MXC_PWRSEQ->lpwken3 &= ~mask; - return; - } - MXC_GPIO_RevA_DisableInt((mxc_gpio_reva_regs_t *)port, mask); } @@ -347,67 +212,36 @@ void MXC_GPIO_Handler(unsigned int port) /* ************************************************************************** */ void MXC_GPIO_ClearFlags(mxc_gpio_regs_t *port, uint32_t flags) { - if (port == MXC_GPIO3) { - MXC_PWRSEQ->lpwkst3 = flags; - return; - } - MXC_GPIO_RevA_ClearFlags((mxc_gpio_reva_regs_t *)port, flags); } /* ************************************************************************** */ uint32_t MXC_GPIO_GetFlags(mxc_gpio_regs_t *port) { - if (port == MXC_GPIO3) { - return MXC_PWRSEQ->lpwkst3; - } - return MXC_GPIO_RevA_GetFlags((mxc_gpio_reva_regs_t *)port); } /* ************************************************************************** */ int MXC_GPIO_SetVSSEL(mxc_gpio_regs_t *port, mxc_gpio_vssel_t vssel, uint32_t mask) { - if (port == MXC_GPIO3) { - if (vssel == MXC_GPIO_VSSEL_VDDIO) { - return E_NOT_SUPPORTED; - } - - return E_NO_ERROR; - } - return MXC_GPIO_RevA_SetVSSEL((mxc_gpio_reva_regs_t *)port, vssel, mask); } /* ************************************************************************** */ void MXC_GPIO_SetWakeEn(mxc_gpio_regs_t *port, uint32_t mask) { - if (port == MXC_GPIO3) { - MXC_PWRSEQ->lpwken3 |= mask; - return; - } - MXC_GPIO_RevA_SetWakeEn((mxc_gpio_reva_regs_t *)port, mask); } /* ************************************************************************** */ void MXC_GPIO_ClearWakeEn(mxc_gpio_regs_t *port, uint32_t mask) { - if (port == MXC_GPIO3) { - MXC_PWRSEQ->lpwken3 &= ~mask; - return; - } - MXC_GPIO_RevA_ClearWakeEn((mxc_gpio_reva_regs_t *)port, mask); } /* ************************************************************************** */ uint32_t MXC_GPIO_GetWakeEn(mxc_gpio_regs_t *port) { - if (port == MXC_GPIO3) { - return MXC_PWRSEQ->lpwken3; - } - return MXC_GPIO_RevA_GetWakeEn((mxc_gpio_reva_regs_t *)port); } From c8fab7309ac07b63bf86bda7b6c470c49dc17afa Mon Sep 17 00:00:00 2001 From: Jake Carter Date: Thu, 2 May 2024 16:52:43 -0600 Subject: [PATCH 46/93] Update mem base/size macros --- .../CMSIS/Device/Maxim/MAX32657/Include/max32657.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h index 6dc05068db9..413f2af005d 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h @@ -179,6 +179,7 @@ typedef enum { #define MXC_SRAM_S_MEM_SIZE 0x00040000UL /* Secure Region name redefinitions for explicit use */ +#if IS_SECURE_ENVIRONMENT #define MXC_FLASH_MEM_BASE MXC_FLASH_S_MEM_BASE #define MXC_FLASH_PAGE_SIZE MXC_FLASH_S_PAGE_SIZE #define MXC_FLASH_MEM_SIZE MXC_FLASH_S_MEM_SIZE @@ -186,6 +187,15 @@ typedef enum { #define MXC_INFO_MEM_SIZE MXC_INFO_S_MEM_SIZE #define MXC_SRAM_MEM_BASE MXC_SRAM_S_MEM_BASE #define MXC_SRAM_MEM_SIZE MXC_SRAM_S_MEM_SIZE +#else +#define MXC_FLASH_MEM_BASE MXC_FLASH_NS_MEM_BASE +#define MXC_FLASH_PAGE_SIZE MXC_FLASH_NS_PAGE_SIZE +#define MXC_FLASH_MEM_SIZE MXC_FLASH_NS_MEM_SIZE +#define MXC_INFO_MEM_BASE MXC_INFO_NS_MEM_BASE +#define MXC_INFO_MEM_SIZE MXC_INFO_NS_MEM_SIZE +#define MXC_SRAM_MEM_BASE MXC_SRAM_NS_MEM_BASE +#define MXC_SRAM_MEM_SIZE MXC_SRAM_NS_MEM_SIZE +#endif /* ================================================================================ */ /* ================ Device Specific Peripheral Section ================ */ From 36cf4265500f251e449f0d7dd88b5e52b0b4dcac Mon Sep 17 00:00:00 2001 From: Jake Carter Date: Thu, 2 May 2024 16:53:24 -0600 Subject: [PATCH 47/93] Update GCR macros --- Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h index 413f2af005d..08fa30ae580 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h @@ -216,8 +216,11 @@ typedef enum { #define MXC_BASE_GCR_S ((uint32_t)0x50000000UL) #define MXC_GCR_S ((mxc_gcr_regs_t *)MXC_BASE_GCR_S) -#define MXC_BASE_GCR MXC_BASE_GCR_S +#if IS_SECURE_ENVIRONMENT #define MXC_GCR MXC_GCR_S +#else +#define MXC_GCR MXC_GCR_NS +#endif /******************************************************************************/ /* Non-battery backed SI Registers */ From d7a8087c244ed87f6ed0a1e05b7a18d01348f8b6 Mon Sep 17 00:00:00 2001 From: Jake Carter Date: Thu, 2 May 2024 17:13:28 -0600 Subject: [PATCH 48/93] Update secure vs non-secure macros for: - SIR - FCR - WDT - SVM - BOOST - TRIMSIR - RTC - WUT - PWRSEQ - MCR - AES - CRC - TMR - I3C - SPI - TRNG - BTLE --- .../Device/Maxim/MAX32657/Include/max32657.h | 153 +++++++++++------- 1 file changed, 94 insertions(+), 59 deletions(-) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h index 08fa30ae580..53e6036fabb 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h @@ -233,8 +233,11 @@ typedef enum { #define MXC_BASE_SIR_S ((uint32_t)0x50000400UL) #define MXC_SIR_S ((mxc_sir_regs_t *)MXC_BASE_SIR_S) -#define MXC_BASE_SIR MXC_BASE_SIR_S +#if IS_SECURE_ENVIRONMENT #define MXC_SIR MXC_SIR_S +#else +#define MXC_SIR MXC_SIR_NS +#endif /******************************************************************************/ /* Non-Battery Backed Function Control */ @@ -247,6 +250,12 @@ typedef enum { #define MXC_BASE_FCR_S ((uint32_t)0x50000800UL) #define MXC_FCR_S ((mxc_fcr_regs_t *)MXC_BASE_FCR_S) +#if IS_SECURE_ENVIRONMENT +#define MXC_FCR MXC_FCR_S +#else +#define MXC_FCR_NS +#endif + /******************************************************************************/ /* Windowed Watchdog Timer */ #define MXC_CFG_WDT_INSTANCES (1) @@ -259,8 +268,11 @@ typedef enum { #define MXC_BASE_WDT_S ((uint32_t)0x50003000UL) #define MXC_WDT_S ((mxc_wdt_regs_t *)MXC_BASE_WDT_S) -#define MXC_BASE_WDT MXC_BASE_WDT_S +#if IS_SECURE_ENVIRONMENT #define MXC_WDT MXC_WDT_S +#else +#define MXC_WDT MXC_WDT_NS +#endif /******************************************************************************/ /* SVM Controller */ @@ -273,8 +285,11 @@ typedef enum { #define MXC_BASE_SVM_S ((uint32_t)0x50004800UL) #define MXC_SVM_S //TODO(ME30): Add SVM controller registers. -#define MXC_BASE_SVM MXC_BASE_SVM_S -#define MXC_SVM //TODO(ME30): Add SVM controller registers. +#if IS_SECURE_ENVIRONMENT +#define MXC_SVM MXC_SVM_S //TODO(ME30): Add SVM controller registers +#else +#define MXC_SVM MXC_SVM_NS +#endif /******************************************************************************/ /* Boost Controller */ @@ -287,8 +302,11 @@ typedef enum { #define MXC_BASE_BOOST_S ((uint32_t)0x50004C00UL) #define MXC_BOOST_S //TODO(ME30): Add Boost controller registers. -#define MXC_BASE_BOOST MXC_BASE_BOOST_S -#define MXC_BOOST //TODO(ME30): Add Boost controller registers. +#if IS_SECURE_ENVIRONMENT +#define MXC_BOOST MXC_BOOST_S +#else +#define MXC_BOOST MXC_BOOST_NS +#endif /******************************************************************************/ /* Trim System Initalization Register */ @@ -301,8 +319,11 @@ typedef enum { #define MXC_BASE_TRIMSIR_S ((uint32_t)0x50005400UL) #define MXC_TRIMSIR_S ((mxc_trimsir_regs_t *)MXC_BASE_TRIMSIR_S) -#define MXC_BASE_TRIMSIR MXC_BASE_TRIMSIR_S +#if IS_SECURE_ENVIRONMENT #define MXC_TRIMSIR MXC_TRIMSIR_S +#else +#define MXC_TRIMSIR MXC_TRIMSIR_NS +#endif /******************************************************************************/ /* Real Time Clock */ @@ -315,8 +336,11 @@ typedef enum { #define MXC_BASE_RTC_S ((uint32_t)0x50006000UL) #define MXC_RTC_S ((mxc_rtc_regs_t *)MXC_BASE_RTC_S) -#define MXC_BASE_RTC MXC_BASE_RTC_S +#if IS_SECURE_ENVIRONMENT #define MXC_RTC MXC_RTC_S +#else +#define MXC_RTC MXC_RTC_NS +#endif /******************************************************************************/ /* Wake-Up Timer (WUT) */ @@ -334,10 +358,13 @@ typedef enum { #define MXC_BASE_WUT1_S ((uint32_t)0x50006600UL) #define MXC_WUT1_S ((mxc_wut_regs_t *)MXC_BASE_WUT1_S) -#define MXC_BASE_WUT0 MXC_BASE_WUT0_S +#if IS_SECURE_ENVIRONMENT #define MXC_WUT0 MXC_WUT0_S -#define MXC_BASE_WUT1 MXC_BASE_WUT1_S #define MXC_WUT1 MXC_WUT1_S +#else +#define MXC_WUT0 MXC_WUT0_NS +#define MXC_WUT1 MXC_WUT1_NS +#endif /******************************************************************************/ /* Power Sequencer */ @@ -350,8 +377,11 @@ typedef enum { #define MXC_BASE_PWRSEQ_S ((uint32_t)0x50006800UL) #define MXC_PWRSEQ_S ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ_S) -#define MXC_BASE_PWRSEQ MXC_BASE_PWRSEQ_S +#if IS_SECURE_ENVIRONMENT #define MXC_PWRSEQ MXC_PWRSEQ_S +#else +#define MXC_PWRSEQ MXC_PWRSEQ_NS +#endif /******************************************************************************/ /* Misc Control */ @@ -364,8 +394,11 @@ typedef enum { #define MXC_BASE_MCR_S ((uint32_t)0x50006C00UL) #define MXC_MCR_S ((mxc_mcr_regs_t *)MXC_BASE_MCR_S) -#define MXC_BASE_MCR MXC_BASE_MCR_S +#if IS_SECURE_ENVIRONMENT #define MXC_MCR MXC_MCR_S +#else +#define MXC_MCR MXC_MCR_S +#endif /******************************************************************************/ /* AES */ @@ -378,8 +411,11 @@ typedef enum { #define MXC_BASE_AES_S ((uint32_t)0x50007400UL) #define MXC_AES_S ((mxc_aes_regs_t *)MXC_BASE_AES_NS) -#define MXC_BASE_AES MXC_BASE_AES_S +#if IS_SECURE_ENVIRONMENT #define MXC_AES MXC_AES_S +#else +#define MXC_AES MXC_AES_NS +#endif /******************************************************************************/ /* AES Keys */ @@ -392,8 +428,11 @@ typedef enum { #define MXC_BASE_AESKEYS_S ((uint32_t)0x50007800UL) #define MXC_AESKEYS_S ((mxc_aeskeys_regs_t *)MXC_BASE_AESKEYS_S) -#define MXC_BASE_AESKEYS MXC_BASE_AESKEYS_S +#if IS_SECURE_ENVIRONMENT #define MXC_AESKEYS MXC_AESKEYS_S +#else +#define MXC_AESKEYS MXC_AESKEYS_NS +#endif /******************************************************************************/ /* GPIO */ @@ -441,8 +480,11 @@ We may want to handle GET_IRQ better... #define MXC_BASE_CRC_S ((uint32_t)0x5000F000UL) #define MXC_CRC_S ((mxc_crc_regs_t *)MXC_BASE_CRC_S) -#define MXC_BASE_CRC MXC_BASE_CRC_S +#if IS_SECURE_ENVIRONMENT #define MXC_CRC MXC_CRC_S +#else +#define MXC_CRC MXC_CRC_NS +#endif /******************************************************************************/ /* Timer */ @@ -498,35 +540,29 @@ We may want to handle GET_IRQ better... #define MXC_BASE_TMR5_S ((uint32_t)0x50081000UL) #define MXC_TMR5_S ((mxc_tmr_regs_t *)MXC_BASE_TMR5_S) -#define MXC_BASE_TMR0 MXC_BASE_TMR0_S +#if IS_SECURE_ENVIRONMENT #define MXC_TMR0 MXC_TMR0_S -#define MXC_BASE_TMR1 MXC_BASE_TMR1_S #define MXC_TMR1 MXC_TMR1_S -#define MXC_BASE_TMR2 MXC_BASE_TMR2_S #define MXC_TMR2 MXC_TMR2_S -#define MXC_BASE_TMR3 MXC_BASE_TMR3_S #define MXC_TMR3 MXC_TMR3_S -#define MXC_BASE_TMR4 MXC_BASE_TMR4_S #define MXC_TMR4 MXC_TMR4_S -#define MXC_BASE_TMR5 MXC_BASE_TMR5_S #define MXC_TMR5 MXC_TMR5_S - -#define MXC_TMR_S_GET_BASE(i) \ - ((i) == 0 ? MXC_BASE_TMR0_S : \ - (i) == 1 ? MXC_BASE_TMR1_S : \ - (i) == 2 ? MXC_BASE_TMR2_S : \ - (i) == 3 ? MXC_BASE_TMR3_S : \ - (i) == 4 ? MXC_BASE_TMR4_S : \ - (i) == 5 ? MXC_BASE_TMR5_S : \ - 0) +#else +#define MXC_TMR0 MXC_TMR0_NS +#define MXC_TMR1 MXC_TMR1_NS +#define MXC_TMR2 MXC_TMR2_NS +#define MXC_TMR3 MXC_TMR3_NS +#define MXC_TMR4 MXC_TMR4_NS +#define MXC_TMR5 MXC_TMR5_NS +#endif #define MXC_TMR_S_GET_TMR(i) \ - ((i) == 0 ? MXC_TMR0_S : \ - (i) == 1 ? MXC_TMR1_S : \ - (i) == 2 ? MXC_TMR2_S : \ - (i) == 3 ? MXC_TMR3_S : \ - (i) == 4 ? MXC_TMR4_S : \ - (i) == 5 ? MXC_TMR5_S : \ + ((i) == 0 ? MXC_TMR0 : \ + (i) == 1 ? MXC_TMR1 : \ + (i) == 2 ? MXC_TMR2 : \ + (i) == 3 ? MXC_TMR3 : \ + (i) == 4 ? MXC_TMR4 : \ + (i) == 5 ? MXC_TMR5 : \ 0) #define MXC_TMR_GET_IRQ(i) \ @@ -555,6 +591,8 @@ We may want to handle GET_IRQ better... /******************************************************************************/ /* I3C */ +#define MXC_I3C_FIFO_DEPTH (8) // TODO(ME30): Confirm this is correct. + /* Non-secure Mapping */ #define MXC_BASE_I3C_NS ((uint32_t)0x4001D000UL) #define MXC_I3C_NS ((mxc_i2c_regs_t *)MXC_BASE_I3C_NS) @@ -563,10 +601,11 @@ We may want to handle GET_IRQ better... #define MXC_BASE_I3C_S ((uint32_t)0x5001D000UL) #define MXC_I3C_S ((mxc_i2c_regs_t *)MXC_BASE_I3C_S) -#define MXC_BASE_I3C MXC_BASE_I2C_S +#if IS_SECURE_ENVIRONMENT #define MXC_I3C MXC_I3C_S - -#define MXC_I3C_FIFO_DEPTH (8) // TODO(ME30): Confirm this is correct. +#else +#define MXC_I3C MXC_I3C_NS +#endif /******************************************************************************/ /* DMA */ @@ -635,7 +674,6 @@ We may want to handle GET_IRQ better... #define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC_S) /* Added for consistency and explicitness */ -#define MXC_BASE_ICC_S MXC_BASE_ICC #define MXC_ICC_S MXC_ICC /******************************************************************************/ @@ -647,26 +685,17 @@ We may want to handle GET_IRQ better... #define MXC_BASE_UART_NS ((uint32_t)0x40042000UL) #define MXC_UART_NS ((mxc_uart_regs_t *)MXC_BASE_UART_NS) -#define MXC_UART_NS_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0_NS : 0) -#define MXC_UART_NS_GET_UART(i) ((i) == 0 ? MXC_UART_NS : 0) - /* Secure Mapping */ #define MXC_BASE_UART_S ((uint32_t)0x50042000UL) #define MXC_UART_S ((mxc_uart_regs_t *)MXC_BASE_UART_S) -#define MXC_UART_S_GET_UART(i) ((i) == 0 ? MXC_UART_S : 0) -#define MXC_UART_S_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0_S : 0) - #if IS_SECURE_ENVIRONMENT -#define MXC_BASE_UART MXC_BASE_UART_S #define MXC_UART MXC_UART_S -#define MXC_UART_GET_UART(i) MXC_UART_S_GET_UART(i) #else -#define MXC_BASE_UART MXC_BASE_UART_NS #define MXC_UART MXC_UART_NS -#define MXC_UART_GET_UART(i) MXC_UART_NS_GET_UART(i) #endif +#define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART : 0) #define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : 0) #define MXC_UART_GET_IDX(p) ((p) == MXC_UART_NS ? 0 : (p) == MXC_UART_S ? 0 : -1) @@ -687,12 +716,13 @@ We may want to handle GET_IRQ better... #define MXC_BASE_SPI_S ((uint32_t)0x50046000UL) #define MXC_SPI_S ((mxc_spi_regs_t *)MXC_BASE_SPI_S) -#define MXC_BASE_SPI MXC_BASE_SPI_S +#if IS_SECURE_ENVIRONMENT #define MXC_SPI MXC_SPI_S +#else +#define MXC_SPI MXC_SPI_NS +#endif -#define MXC_SPI_S_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI_S : 0) -#define MXC_SPI_S_GET_SPI(i) ((i) == 0 ? MXC_SPI_S : 0) - +#define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI : 0) #define MXC_SPI_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SPI_IRQn : 0) #define MXC_SPI_GET_IDX(p) ((p) == MXC_SPI_NS ? 0 : (p) == MXC_SPI_S ? 0 : -1) @@ -707,8 +737,11 @@ We may want to handle GET_IRQ better... #define MXC_BASE_TRNG_S ((uint32_t)0x5004D000UL) #define MXC_TRNG_S ((mxc_trng_regs_t *)MXC_BASE_TRNG_S) -#define MXC_BASE_TRNG MXC_BASE_TRNG_S +#if IS_SECURE_ENVIRONMENT #define MXC_TRNG MXC_TRNG_S +#else +#define MXC_TRNG MXC_TRNG_NS +#endif /******************************************************************************/ /* BTLE */ @@ -722,8 +755,12 @@ We may want to handle GET_IRQ better... #define MXC_BASE_BTLE_S ((uint32_t)0x50050000UL) #define MXC_BTLE_S // TODO(ME30): Add BTLE related registers? This section doesn't exist for ME17. -#define MXC_BASE_BTLE MXC_BASE_BTLE_S -#define MXC_BTLE // TODO(ME30): Does this have registers? +#if IS_SECURE_ENVIRONMENT +// TODO(ME30): Does this have registers? +#define MXC_BTLE MXC_BTLE_S +#else +#define MXC_BTLE MXC_BTLE_NS +#endif /******************************************************************************/ /* Secure Privilege Control (SPC TZ) */ @@ -731,8 +768,6 @@ We may want to handle GET_IRQ better... /* Secure Mapping Only */ #define MXC_BASE_SPC ((uint32_t)0x50090000UL) #define MXC_SPC // TODO(ME30): Does this have registers? - -#define MXC_BASE_SPC_S MXC_BASE_SPC #define MXC_SPC_S // TODO(ME30): Does this have registers? /******************************************************************************/ From e6cc041509dbbbaf71865a0f1871af3f58d2dead Mon Sep 17 00:00:00 2001 From: Jake Carter Date: Thu, 2 May 2024 17:30:01 -0600 Subject: [PATCH 49/93] Update ME30 SYS drivers --- .../PeriphDrivers/Include/MAX32657/mxc_sys.h | 3 +- Libraries/PeriphDrivers/Source/SYS/sys_me30.c | 161 ++++++------------ Libraries/PeriphDrivers/max32657_files.mk | 2 + 3 files changed, 52 insertions(+), 114 deletions(-) diff --git a/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h b/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h index def4ee9b925..4d0d93621d3 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h @@ -105,9 +105,8 @@ typedef enum { } mxc_sys_periph_clock_t; /** @brief Enumeration to select System Clock source */ +// TODO(ME30): CLKCTRL sysclk_sel values seem incorrect. typedef enum { - MXC_SYS_CLOCK_ISO = - MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ISO, /**< Select the Internal Secondary Oscillator (ISO) */ MXC_SYS_CLOCK_IPO = MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO, /**< Select the Internal Primary Oscillator (IPO) */ MXC_SYS_CLOCK_IBRO = diff --git a/Libraries/PeriphDrivers/Source/SYS/sys_me30.c b/Libraries/PeriphDrivers/Source/SYS/sys_me30.c index 4ad2ab85b67..e03cd7c5cfd 100644 --- a/Libraries/PeriphDrivers/Source/SYS/sys_me30.c +++ b/Libraries/PeriphDrivers/Source/SYS/sys_me30.c @@ -29,7 +29,6 @@ #include "mxc_assert.h" #include "mxc_sys.h" #include "mxc_delay.h" -#include "lpgcr_regs.h" #include "gcr_regs.h" #include "fcr_regs.h" #include "mcr_regs.h" @@ -61,14 +60,14 @@ extern uint32_t _binary_riscv_bin_start; int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum) { int err = E_NO_ERROR; - uint32_t *infoblock = (uint32_t *)MXC_INFO0_MEM_BASE; + uint32_t *infoblock = (uint32_t *)MXC_INFO_MEM_BASE; if (usn == NULL) { return E_NULL_PTR; } /* Read the USN from the info block */ - MXC_FLC_UnlockInfoBlock(MXC_INFO0_MEM_BASE); + MXC_FLC_UnlockInfoBlock(MXC_INFO_MEM_BASE); memset(usn, 0, MXC_SYS_USN_CHECKSUM_LEN); @@ -96,7 +95,7 @@ int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum) err = MXC_AES_Init(); if (err) { - MXC_FLC_LockInfoBlock(MXC_INFO0_MEM_BASE); + MXC_FLC_LockInfoBlock(MXC_INFO_MEM_BASE); return err; } @@ -114,7 +113,7 @@ int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum) err = MXC_AES_Generic(&aes_req); if (err) { - MXC_FLC_LockInfoBlock(MXC_INFO0_MEM_BASE); + MXC_FLC_LockInfoBlock(MXC_INFO_MEM_BASE); return err; } @@ -122,7 +121,7 @@ int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum) // Verify Checksum if (check_csum[0] != checksum[1] || check_csum[1] != checksum[0]) { - MXC_FLC_LockInfoBlock(MXC_INFO0_MEM_BASE); + MXC_FLC_LockInfoBlock(MXC_INFO_MEM_BASE); return E_INVALID; } } @@ -131,7 +130,7 @@ int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum) usn[11] = ((infoblock[3] & 0x7F800000) >> 23); usn[12] = ((infoblock[4] & 0x007F8000) >> 15); - MXC_FLC_LockInfoBlock(MXC_INFO0_MEM_BASE); + MXC_FLC_LockInfoBlock(MXC_INFO_MEM_BASE); return err; } @@ -146,10 +145,7 @@ int MXC_SYS_GetRevision(void) int MXC_SYS_IsClockEnabled(mxc_sys_periph_clock_t clock) { /* The mxc_sys_periph_clock_t enum uses enum values that are the offset by 32 and 64 for the perckcn1 register. */ - if (clock > 63) { - clock -= 64; - return !(MXC_LPGCR->pclkdis & (0x1 << clock)); - } else if (clock > 31) { + if (clock > 31) { clock -= 32; return !(MXC_GCR->pclkdis1 & (0x1 << clock)); } else { @@ -161,10 +157,7 @@ int MXC_SYS_IsClockEnabled(mxc_sys_periph_clock_t clock) void MXC_SYS_ClockDisable(mxc_sys_periph_clock_t clock) { /* The mxc_sys_periph_clock_t enum uses enum values that are the offset by 32 and 64 for the perckcn1 register. */ - if (clock > 63) { - clock -= 64; - MXC_LPGCR->pclkdis |= (0x1 << clock); - } else if (clock > 31) { + if (clock > 31) { clock -= 32; MXC_GCR->pclkdis1 |= (0x1 << clock); } else { @@ -176,10 +169,7 @@ void MXC_SYS_ClockDisable(mxc_sys_periph_clock_t clock) void MXC_SYS_ClockEnable(mxc_sys_periph_clock_t clock) { /* The mxc_sys_periph_clock_t enum uses enum values that are the offset by 32 and 64 for the perckcn1 register. */ - if (clock > 63) { - clock -= 64; - MXC_LPGCR->pclkdis &= ~(0x1 << clock); - } else if (clock > 31) { + if (clock > 31) { clock -= 32; MXC_GCR->pclkdis1 &= ~(0x1 << clock); } else { @@ -232,10 +222,11 @@ int MXC_SYS_ClockSourceEnable(mxc_sys_system_clock_t clock) return MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_IBRO_RDY); break; - case MXC_SYS_CLOCK_EXTCLK: - // No "RDY" bit to monitor, so just configure the GPIO - return MXC_GPIO_Config(&gpio_cfg_extclk); - break; + // TODO(ME30): EXTCLK is missing from register definitions + // case MXC_SYS_CLOCK_EXTCLK: + // // No "RDY" bit to monitor, so just configure the GPIO + // return MXC_GPIO_Config(&gpio_cfg_extclk); + // break; case MXC_SYS_CLOCK_INRO: // The 80k clock is always enabled @@ -243,20 +234,21 @@ int MXC_SYS_ClockSourceEnable(mxc_sys_system_clock_t clock) break; case MXC_SYS_CLOCK_ERFO: - MXC_GCR->btleldoctrl |= MXC_F_GCR_BTLELDOCTRL_LDOTXEN | MXC_F_GCR_BTLELDOCTRL_LDORXEN; + MXC_GCR->btleldoctrl |= MXC_F_GCR_BTLELDOCTRL_TX_EN | MXC_F_GCR_BTLELDOCTRL_RX_EN; /* Initialize kickstart circuit Select Kick start circuit clock source- IPO/ISO */ - MXC_FCR->erfoks = ((MXC_S_FCR_ERFOKS_KSCLKSEL_ISO) - /* Set Drive strengh - 0x1,0x2,0x3 */ - | ((0x1) << MXC_F_FCR_ERFOKS_KSERFODRIVER_POS) - /* Set kick count 1-127 */ - | (0x8) - /* Set double pulse length On/Off*/ - | (0 & MXC_F_FCR_ERFOKS_KSERFO2X) - /* Enable On/Off */ - | (MXC_F_FCR_ERFOKS_KSERFO_EN)); + // TODO(ME30): MXC_FCR missing ERFOKS definition + // MXC_FCR->erfoks = ((MXC_S_FCR_ERFOKS_KSCLKSEL_ISO) + // /* Set Drive strengh - 0x1,0x2,0x3 */ + // | ((0x1) << MXC_F_FCR_ERFOKS_KSERFODRIVER_POS) + // /* Set kick count 1-127 */ + // | (0x8) + // /* Set double pulse length On/Off*/ + // | (0 & MXC_F_FCR_ERFOKS_KSERFO2X) + // /* Enable On/Off */ + // | (MXC_F_FCR_ERFOKS_KSERFO_EN)); /* Enable ERFO */ MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_ERFO_EN; @@ -295,15 +287,16 @@ int MXC_SYS_ClockSourceDisable(mxc_sys_system_clock_t clock) MXC_GCR->clkctrl &= ~MXC_F_GCR_CLKCTRL_IBRO_EN; break; - case MXC_SYS_CLOCK_EXTCLK: - /* - There's not a great way to disable the external clock. - Deinitializing the GPIO here may have unintended consequences - for application code. - Selecting a different system clock source is sufficient - to "disable" the EXT_CLK source. - */ - break; + // TODO(ME30): Missing EXTCLK register definition + // case MXC_SYS_CLOCK_EXTCLK: + // /* + // There's not a great way to disable the external clock. + // Deinitializing the GPIO here may have unintended consequences + // for application code. + // Selecting a different system clock source is sufficient + // to "disable" the EXT_CLK source. + // */ + // break; case MXC_SYS_CLOCK_INRO: // The 80k clock is always enabled @@ -356,29 +349,11 @@ int MXC_SYS_Clock_Timeout(uint32_t ready) int MXC_SYS_Clock_Select(mxc_sys_system_clock_t clock) { uint32_t current_clock; - int err = E_NO_ERROR; // Save the current system clock current_clock = MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_SEL; switch (clock) { - case MXC_SYS_CLOCK_ISO: - - // Enable ISO clock - if (!(MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_ISO_EN)) { - MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_ISO_EN; - - // Check if ISO clock is ready - if (MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_ISO_RDY) != E_NO_ERROR) { - return E_TIME_OUT; - } - } - - // Set ISO clock as System Clock - MXC_SETFIELD(MXC_GCR->clkctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL, - MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ISO); - - break; case MXC_SYS_CLOCK_IPO: // Enable IPO clock @@ -415,20 +390,21 @@ int MXC_SYS_Clock_Select(mxc_sys_system_clock_t clock) break; - case MXC_SYS_CLOCK_EXTCLK: - /* - There's not "EXT_CLK RDY" bit for the ME17, so we'll - blindly enable (configure GPIO) the external clock every time. - */ - err = MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_EXTCLK); - if (err) - return err; + // TODO(ME30): Missing EXTCLK register definition + // case MXC_SYS_CLOCK_EXTCLK: + // /* + // There's not "EXT_CLK RDY" bit for the ME17, so we'll + // blindly enable (configure GPIO) the external clock every time. + // */ + // err = MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_EXTCLK); + // if (err) + // return err; - // Set EXT clock as System Clock - MXC_SETFIELD(MXC_GCR->clkctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL, - MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK); + // // Set EXT clock as System Clock + // MXC_SETFIELD(MXC_GCR->clkctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL, + // MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK); - break; + // break; case MXC_SYS_CLOCK_ERFO: @@ -514,11 +490,7 @@ mxc_sys_system_clock_div_t MXC_SYS_GetClockDiv(void) void MXC_SYS_Reset_Periph(mxc_sys_reset_t reset) { /* The mxc_sys_reset_t enum uses enum values that are the offset by 32 and 64 for the rst register. */ - if (reset > 63) { - reset -= 64; - MXC_LPGCR->rst = (0x1 << reset); - while (MXC_LPGCR->rst & (0x1 << reset)) {} - } else if (reset > 31) { + if (reset > 31) { reset -= 32; MXC_GCR->rst1 = (0x1 << reset); while (MXC_GCR->rst1 & (0x1 << reset)) {} @@ -528,41 +500,6 @@ void MXC_SYS_Reset_Periph(mxc_sys_reset_t reset) } } -/* ************************************************************************** */ -void MXC_SYS_RISCVRun(void) -{ - /* Disable the the RSCV */ - MXC_GCR->pclkdis1 |= MXC_F_GCR_PCLKDIS1_CPU1; - - /* Set the interrupt vector base address */ - MXC_FCR->urvbootaddr = (uint32_t)&_binary_riscv_bin_start; - - /* Power up the RSCV */ - MXC_GCR->pclkdis1 &= ~(MXC_F_GCR_PCLKDIS1_CPU1); - - /* CPU1 reset */ - MXC_GCR->rst1 |= MXC_F_GCR_RST1_CPU1; -} - -/* ************************************************************************** */ -void MXC_SYS_RISCVShutdown(void) -{ - /* Disable the the RSCV */ - MXC_GCR->pclkdis1 |= MXC_F_GCR_PCLKDIS1_CPU1; -} - -/* ************************************************************************** */ -uint32_t MXC_SYS_RiscVClockRate(void) -{ - // If in LPM mode and the PCLK is selected as the RV32 clock source, - if (((MXC_GCR->pm & MXC_F_GCR_PM_MODE) == MXC_S_GCR_PM_MODE_LPM) && - (MXC_PWRSEQ->lpcn & MXC_F_PWRSEQ_LPCN_LPMCLKSEL)) { - return ISO_FREQ; - } else { - return PeripheralClock; - } -} - /* ************************************************************************** */ int MXC_SYS_LockDAP_Permanent(void) { diff --git a/Libraries/PeriphDrivers/max32657_files.mk b/Libraries/PeriphDrivers/max32657_files.mk index 9be6538cd3e..9cc4233adba 100644 --- a/Libraries/PeriphDrivers/max32657_files.mk +++ b/Libraries/PeriphDrivers/max32657_files.mk @@ -50,6 +50,8 @@ PERIPH_DRIVER_INCLUDE_DIR += $(INCLUDE_DIR)/$(TARGET_UC)/ PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_assert.c PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_delay.c PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_lock.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/sys_me30.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/pins_me30.c PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/AES PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/AES/aes_me30.c From 1318192d4d08deb26a00caff6cd3fe6d6f341394 Mon Sep 17 00:00:00 2001 From: Jake Carter Date: Thu, 2 May 2024 17:30:17 -0600 Subject: [PATCH 50/93] Add ME30 pins file to build --- .../PeriphDrivers/Source/SYS/pins_me30.c | 126 ++++-------------- 1 file changed, 24 insertions(+), 102 deletions(-) diff --git a/Libraries/PeriphDrivers/Source/SYS/pins_me30.c b/Libraries/PeriphDrivers/Source/SYS/pins_me30.c index 79c0d33bc52..8b8e6b4afda 100644 --- a/Libraries/PeriphDrivers/Source/SYS/pins_me30.c +++ b/Libraries/PeriphDrivers/Source/SYS/pins_me30.c @@ -40,98 +40,31 @@ const mxc_gpio_cfg_t gpio_cfg_uart0_flow = { MXC_GPIO0, (MXC_GPIO_PIN_2 | MXC_GP MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; const mxc_gpio_cfg_t gpio_cfg_uart0_flow_disable = { MXC_GPIO0, (MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3), MXC_GPIO_FUNC_IN, MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_uart1 = { MXC_GPIO0, (MXC_GPIO_PIN_12 | MXC_GPIO_PIN_13), MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_uart1_flow = { MXC_GPIO0, (MXC_GPIO_PIN_14 | MXC_GPIO_PIN_15), MXC_GPIO_FUNC_ALT2, - MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_uart1_flow_disable = { MXC_GPIO0, (MXC_GPIO_PIN_14 | MXC_GPIO_PIN_15), MXC_GPIO_FUNC_IN, - MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_uart2 = { MXC_GPIO1, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1), MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_uart2_flow = { MXC_GPIO0, (MXC_GPIO_PIN_30 | MXC_GPIO_PIN_31), MXC_GPIO_FUNC_ALT2, - MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_uart2_flow_disable = { MXC_GPIO0, (MXC_GPIO_PIN_30 | MXC_GPIO_PIN_31), MXC_GPIO_FUNC_IN, - MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_uart3 = { MXC_GPIO2, (MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7), MXC_GPIO_FUNC_ALT2, - MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; - -const mxc_gpio_cfg_t antenna_ctrl0 = { MXC_GPIO1, (MXC_GPIO_PIN_8 | MXC_GPIO_PIN_9), MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t antenna_ctrl1 = { MXC_GPIO1, (MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7), MXC_GPIO_FUNC_ALT2, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +// const mxc_gpio_cfg_t antenna_ctrl0 = { MXC_GPIO1, (MXC_GPIO_PIN_8 | MXC_GPIO_PIN_9), MXC_GPIO_FUNC_ALT1, +// MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +// const mxc_gpio_cfg_t antenna_ctrl1 = { MXC_GPIO1, (MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7), MXC_GPIO_FUNC_ALT2, +// MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +// TODO(ME30): TMR pins // Timers are only defined once, depending on package, each timer could be mapped to other pins -const mxc_gpio_cfg_t gpio_cfg_tmr0 = { MXC_GPIO0, (MXC_GPIO_PIN_2), MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_tmr0b = { MXC_GPIO0, (MXC_GPIO_PIN_3), MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_tmr1 = { MXC_GPIO0, (MXC_GPIO_PIN_14), MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_tmr1b = { MXC_GPIO0, (MXC_GPIO_PIN_15), MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_tmr1_MapB = { MXC_GPIO0, (MXC_GPIO_PIN_20), MXC_GPIO_FUNC_ALT2, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_tmr2 = { MXC_GPIO0, (MXC_GPIO_PIN_26), MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_tmr2b = { MXC_GPIO0, (MXC_GPIO_PIN_27), MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_tmr3 = { MXC_GPIO1, (MXC_GPIO_PIN_6), MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_tmr3b = { MXC_GPIO1, (MXC_GPIO_PIN_7), MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; - -const mxc_gpio_cfg_t gpio_cfg_i2s0 = { MXC_GPIO1, (MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3 | MXC_GPIO_PIN_4 | MXC_GPIO_PIN_5), - MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; - -const mxc_gpio_cfg_t gpio_cfg_i2s0_clkext = { MXC_GPIO0, MXC_GPIO_PIN_14, MXC_GPIO_FUNC_ALT2, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; - -const mxc_gpio_cfg_t gpio_cfg_rtcsqw = { MXC_GPIO3, MXC_GPIO_PIN_1, MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIOH, MXC_GPIO_DRVSTR_0}; - -const mxc_gpio_cfg_t gpio_cfg_pt0 = { MXC_GPIO0, MXC_GPIO_PIN_18, MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_pt1 = { MXC_GPIO0, MXC_GPIO_PIN_19, MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_pt2 = { MXC_GPIO0, MXC_GPIO_PIN_16, MXC_GPIO_FUNC_ALT2, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_pt3 = { MXC_GPIO0, MXC_GPIO_PIN_17, MXC_GPIO_FUNC_ALT2, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; - -// 1-Wire pins need to be at 3.3V so that MXC_GPIO_VSSEL_VDDIOH is selected. -const mxc_gpio_cfg_t gpio_cfg_owm = { MXC_GPIO0, (MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7), MXC_GPIO_FUNC_ALT2, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIOH, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_owmb = { MXC_GPIO0, (MXC_GPIO_PIN_18 | MXC_GPIO_PIN_19), MXC_GPIO_FUNC_ALT2, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIOH, MXC_GPIO_DRVSTR_0 }; - -const mxc_gpio_cfg_t gpio_cfg_adc_ain0 = { MXC_GPIO2, MXC_GPIO_PIN_0, MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_adc_ain1 = { MXC_GPIO2, MXC_GPIO_PIN_1, MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_adc_ain2 = { MXC_GPIO2, MXC_GPIO_PIN_2, MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_adc_ain3 = { MXC_GPIO2, MXC_GPIO_PIN_3, MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_adc_ain4 = { MXC_GPIO2, MXC_GPIO_PIN_4, MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_adc_ain5 = { MXC_GPIO2, MXC_GPIO_PIN_5, MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_adc_ain6 = { MXC_GPIO2, MXC_GPIO_PIN_6, MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_adc_ain7 = { MXC_GPIO2, MXC_GPIO_PIN_7, MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; - -const mxc_gpio_cfg_t gpio_cfg_rv_jtag = { MXC_GPIO1, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1 | MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3), - MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; - -const mxc_gpio_cfg_t gpio_cfg_cmp0 = { MXC_GPIO2, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1), MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_cmp1 = { MXC_GPIO2, (MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3), MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_cmp2 = { MXC_GPIO2, (MXC_GPIO_PIN_4 | MXC_GPIO_PIN_5), MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_cmp3 = { MXC_GPIO2, (MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7), MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +// const mxc_gpio_cfg_t gpio_cfg_tmr0 = { MXC_GPIO0, (MXC_GPIO_PIN_2), MXC_GPIO_FUNC_ALT1, +// MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +// const mxc_gpio_cfg_t gpio_cfg_tmr0b = { MXC_GPIO0, (MXC_GPIO_PIN_3), MXC_GPIO_FUNC_ALT1, +// MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +// const mxc_gpio_cfg_t gpio_cfg_tmr1 = { MXC_GPIO0, (MXC_GPIO_PIN_14), MXC_GPIO_FUNC_ALT1, +// MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +// const mxc_gpio_cfg_t gpio_cfg_tmr1b = { MXC_GPIO0, (MXC_GPIO_PIN_15), MXC_GPIO_FUNC_ALT1, +// MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +// const mxc_gpio_cfg_t gpio_cfg_tmr1_MapB = { MXC_GPIO0, (MXC_GPIO_PIN_20), MXC_GPIO_FUNC_ALT2, +// MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +// const mxc_gpio_cfg_t gpio_cfg_tmr2 = { MXC_GPIO0, (MXC_GPIO_PIN_26), MXC_GPIO_FUNC_ALT1, +// MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +// const mxc_gpio_cfg_t gpio_cfg_tmr2b = { MXC_GPIO0, (MXC_GPIO_PIN_27), MXC_GPIO_FUNC_ALT1, +// MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +// const mxc_gpio_cfg_t gpio_cfg_tmr3 = { MXC_GPIO1, (MXC_GPIO_PIN_6), MXC_GPIO_FUNC_ALT1, +// MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +// const mxc_gpio_cfg_t gpio_cfg_tmr3b = { MXC_GPIO1, (MXC_GPIO_PIN_7), MXC_GPIO_FUNC_ALT1, +// MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; // SPI v2 Pin Definitions const mxc_gpio_cfg_t gpio_cfg_spi0_standard = { MXC_GPIO0, (MXC_GPIO_PIN_5 | MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7), @@ -143,21 +76,10 @@ const mxc_gpio_cfg_t gpio_cfg_spi0_dual = { MXC_GPIO0, (MXC_GPIO_PIN_5 | MXC_GPI const mxc_gpio_cfg_t gpio_cfg_spi0_quad = { MXC_GPIO0, (MXC_GPIO_PIN_5 | MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7 | MXC_GPIO_PIN_8 | MXC_GPIO_PIN_9), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_spi1_standard = { MXC_GPIO0, (MXC_GPIO_PIN_21 | MXC_GPIO_PIN_22 | MXC_GPIO_PIN_23), MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_spi1_3wire = { MXC_GPIO0, (MXC_GPIO_PIN_21 | MXC_GPIO_PIN_23), MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_spi1_dual = { MXC_GPIO0, (MXC_GPIO_PIN_21 | MXC_GPIO_PIN_22 | MXC_GPIO_PIN_23), - MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_spi1_quad = { MXC_GPIO0, (MXC_GPIO_PIN_21 | MXC_GPIO_PIN_22 | MXC_GPIO_PIN_23 | MXC_GPIO_PIN_24 | MXC_GPIO_PIN_25), - MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; - // SPI v2 Target Selects Pin Definitions const mxc_gpio_cfg_t gpio_cfg_spi0_ts0 = { MXC_GPIO0, MXC_GPIO_PIN_4, MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; const mxc_gpio_cfg_t gpio_cfg_spi0_ts1 = { MXC_GPIO0, MXC_GPIO_PIN_26, MXC_GPIO_FUNC_ALT2, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; const mxc_gpio_cfg_t gpio_cfg_spi0_ts2 = { MXC_GPIO0, MXC_GPIO_PIN_27, MXC_GPIO_FUNC_ALT2, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_spi1_ts0 = { MXC_GPIO0, MXC_GPIO_PIN_20, MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; \ No newline at end of file From 541738cbfc84582ee4f475fa1809cea596e80738 Mon Sep 17 00:00:00 2001 From: Jake Carter Date: Thu, 2 May 2024 17:35:23 -0600 Subject: [PATCH 51/93] Skip LP drivers --- Libraries/PeriphDrivers/max32657_files.mk | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Libraries/PeriphDrivers/max32657_files.mk b/Libraries/PeriphDrivers/max32657_files.mk index 9cc4233adba..c8ed1baecaf 100644 --- a/Libraries/PeriphDrivers/max32657_files.mk +++ b/Libraries/PeriphDrivers/max32657_files.mk @@ -79,8 +79,9 @@ PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/ICC PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/ICC/icc_me30.c PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/ICC/icc_reva.c -PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/LP -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/LP/lp_me30.c +# TODO(ME30): Add LP drivers back in when register files are provided +# PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/LP +# PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/LP/lp_me30.c PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/RTC PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/RTC/rtc_me30.c From 732872d000292524cb15cf64f0c3c3140c8e3ef2 Mon Sep 17 00:00:00 2001 From: Jake Carter Date: Thu, 2 May 2024 17:35:40 -0600 Subject: [PATCH 52/93] Update ME30 LP drivers --- Libraries/PeriphDrivers/Include/MAX32657/rtc.h | 4 ++-- Libraries/PeriphDrivers/Source/RTC/rtc_me30.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/Libraries/PeriphDrivers/Include/MAX32657/rtc.h b/Libraries/PeriphDrivers/Include/MAX32657/rtc.h index ad8c192a5f9..187e70ec417 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/rtc.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/rtc.h @@ -70,8 +70,8 @@ typedef enum { * @brief Bitmasks for each of the RTC's interrupt flags. */ typedef enum { - MXC_RTC_INT_FL_LONG = MXC_F_RTC_CTRL_TOD_ALARM, /**< Long-interval alarm interrupt flag */ - MXC_RTC_INT_FL_SHORT = MXC_F_RTC_CTRL_SSEC_ALARM, /**< Short-interval alarm interrupt flag */ + MXC_RTC_INT_FL_LONG = MXC_F_RTC_CTRL_TOD_ALARM_IF, /**< Long-interval alarm interrupt flag */ + MXC_RTC_INT_FL_SHORT = MXC_F_RTC_CTRL_SSEC_ALARM_IF, /**< Short-interval alarm interrupt flag */ MXC_RTC_INT_FL_READY = MXC_F_RTC_CTRL_RDY, /**< Timer ready interrupt flag */ } mxc_rtc_int_fl_t; diff --git a/Libraries/PeriphDrivers/Source/RTC/rtc_me30.c b/Libraries/PeriphDrivers/Source/RTC/rtc_me30.c index 6d6eefe2757..df0dac1d216 100644 --- a/Libraries/PeriphDrivers/Source/RTC/rtc_me30.c +++ b/Libraries/PeriphDrivers/Source/RTC/rtc_me30.c @@ -222,13 +222,13 @@ int MXC_RTC_TrimCrystal(void) /* Wait for an RTC edge */ MXC_RTC_ClearFlags(MXC_RTC_GetFlags()); - while (!(MXC_RTC->ctrl & MXC_F_RTC_CTRL_SSEC_ALARM)) {} + while (!(MXC_RTC->ctrl & MXC_F_RTC_CTRL_SSEC_ALARM_IF)) {} MXC_TMR_Start(MXC_TMR3); /* Wait for an RTC edge */ MXC_RTC_ClearFlags(MXC_RTC_GetFlags()); - while (!(MXC_RTC->ctrl & MXC_F_RTC_CTRL_SSEC_ALARM)) {} + while (!(MXC_RTC->ctrl & MXC_F_RTC_CTRL_SSEC_ALARM_IF)) {} /* Capture the TMR count and adjust for processing delay */ elapsed = MXC_TMR_GetCount(MXC_TMR3); From 8d0a66259a9fe82a18555b328a8c3e1b30b1fcc0 Mon Sep 17 00:00:00 2001 From: Jake Carter Date: Thu, 2 May 2024 17:39:58 -0600 Subject: [PATCH 53/93] Update ME30 SPI drivers --- Libraries/PeriphDrivers/Source/SPI/spi_me30.c | 164 +++++------------- 1 file changed, 48 insertions(+), 116 deletions(-) diff --git a/Libraries/PeriphDrivers/Source/SPI/spi_me30.c b/Libraries/PeriphDrivers/Source/SPI/spi_me30.c index da6225abb7b..b2e419561d2 100644 --- a/Libraries/PeriphDrivers/Source/SPI/spi_me30.c +++ b/Libraries/PeriphDrivers/Source/SPI/spi_me30.c @@ -66,9 +66,8 @@ int MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int quadModeUsed, int numS } // Configure GPIO for spi - if (spi == MXC_SPI1) { - MXC_SYS_Reset_Periph(MXC_SYS_RESET0_SPI1); - MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_SPI1); + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_SPI); + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_SPI); #if (TARGET != MAX78000 || TARGET_NUM == 32655) @@ -86,87 +85,37 @@ int MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int quadModeUsed, int numS } #endif - //clear mask - gpio_cfg_spi.mask = 0; + //clear mask + gpio_cfg_spi.mask = 0; - // check rest of the pins - if (pins.clock) { - gpio_cfg_spi.mask |= MXC_GPIO_PIN_23; - } - - if (pins.miso) { - gpio_cfg_spi.mask |= MXC_GPIO_PIN_22; - } - - if (pins.mosi) { - gpio_cfg_spi.mask |= MXC_GPIO_PIN_21; - } - - if (pins.sdio2) { - gpio_cfg_spi.mask |= MXC_GPIO_PIN_24; - } - - if (pins.sdio3) { - gpio_cfg_spi.mask |= MXC_GPIO_PIN_25; - } - - if (pins.ss0) { - gpio_cfg_spi.mask |= MXC_GPIO_PIN_20; - } - - gpio_cfg_spi.func = MXC_GPIO_FUNC_ALT1; -#ifdef MXC_SPI0 - } else if (spi == MXC_SPI0) { - MXC_SYS_Reset_Periph(MXC_SYS_RESET1_SPI0); - MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_SPI0); - - //Define pins - if (pins.ss1) { - gpio_cfg_spi.mask = MXC_GPIO_PIN_11; - gpio_cfg_spi.func = MXC_GPIO_FUNC_ALT2; - MXC_GPIO_Config(&gpio_cfg_spi); - } - - if (pins.ss2) { - gpio_cfg_spi.func = MXC_GPIO_FUNC_ALT2; - gpio_cfg_spi.mask = MXC_GPIO_PIN_10; - MXC_GPIO_Config(&gpio_cfg_spi); - } - - //clear mask - gpio_cfg_spi.mask = 0; - - // check rest of the pins - if (pins.clock) { - gpio_cfg_spi.mask |= MXC_GPIO_PIN_7; - } - - if (pins.miso) { - gpio_cfg_spi.mask |= MXC_GPIO_PIN_6; - } + // TODO(ME30): Validate pin assignments + // check rest of the pins + if (pins.clock) { + gpio_cfg_spi.mask |= MXC_GPIO_PIN_23; + } - if (pins.mosi) { - gpio_cfg_spi.mask |= MXC_GPIO_PIN_5; - } + if (pins.miso) { + gpio_cfg_spi.mask |= MXC_GPIO_PIN_22; + } - if (pins.sdio2) { - gpio_cfg_spi.mask |= MXC_GPIO_PIN_8; - } + if (pins.mosi) { + gpio_cfg_spi.mask |= MXC_GPIO_PIN_21; + } - if (pins.sdio3) { - gpio_cfg_spi.mask |= MXC_GPIO_PIN_9; - } + if (pins.sdio2) { + gpio_cfg_spi.mask |= MXC_GPIO_PIN_24; + } - if (pins.ss0) { - gpio_cfg_spi.mask |= MXC_GPIO_PIN_4; - } + if (pins.sdio3) { + gpio_cfg_spi.mask |= MXC_GPIO_PIN_25; + } - gpio_cfg_spi.func = MXC_GPIO_FUNC_ALT1; -#endif - } else { - return E_NO_DEVICE; + if (pins.ss0) { + gpio_cfg_spi.mask |= MXC_GPIO_PIN_20; } + gpio_cfg_spi.func = MXC_GPIO_FUNC_ALT1; + MXC_GPIO_Config(&gpio_cfg_spi); #else (void)pins; @@ -185,15 +134,7 @@ int MXC_SPI_Shutdown(mxc_spi_regs_t *spi) MXC_SPI_RevA1_Shutdown((mxc_spi_reva_regs_t *)spi); - if (spi == MXC_SPI1) { - MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SPI1); -#ifdef MXC_SPI0 - } else if (spi == MXC_SPI0) { - MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SPI0); -#endif - } else { - return E_NO_DEVICE; - } + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_SPI); return E_NO_ERROR; } @@ -207,42 +148,33 @@ int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t *spi) { int retval; - if (spi == MXC_SPI1) { - retval = PeripheralClock; -#ifdef MXC_SPI0 // SPI0 is not accessible from the RISC core. - } else if (spi == MXC_SPI0) { - int sys_clk = (MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_SEL) >> - MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS; - switch (sys_clk) { - case MXC_SYS_CLOCK_IPO: - retval = IPO_FREQ; - break; - case MXC_SYS_CLOCK_IBRO: - retval = IBRO_FREQ; - break; - case MXC_SYS_CLOCK_ISO: - retval = ISO_FREQ; - break; - case MXC_SYS_CLOCK_INRO: - retval = INRO_FREQ; - break; - case MXC_SYS_CLOCK_ERTCO: - retval = ERTCO_FREQ; - break; - case MXC_SYS_CLOCK_EXTCLK: - retval = EXTCLK_FREQ; - break; + // TODO(ME30): Validate this logic + int sys_clk = (MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_SEL) >> + MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS; + switch (sys_clk) { + case MXC_SYS_CLOCK_IPO: + retval = IPO_FREQ; + break; + case MXC_SYS_CLOCK_IBRO: + retval = IBRO_FREQ; + break; + case MXC_SYS_CLOCK_INRO: + retval = INRO_FREQ; + break; + case MXC_SYS_CLOCK_ERTCO: + retval = ERTCO_FREQ; + break; + // TODO(ME30): EXTCLK definition is missing from registers + // case MXC_SYS_CLOCK_EXTCLK: + // retval = EXTCLK_FREQ; + // break; #if TARGET_NUM == 32655 || TARGET_NUM == 32680 case MXC_SYS_CLOCK_ERFO: retval = ERFO_FREQ; break; #endif - default: - return E_BAD_STATE; - } -#endif // MXC_SPI0 - } else { - return E_BAD_PARAM; + default: + return E_BAD_STATE; } retval /= 2; From d441ff7ec0204284c5dbfe35889fd82d238ea37c Mon Sep 17 00:00:00 2001 From: Jake Carter Date: Thu, 2 May 2024 17:42:33 -0600 Subject: [PATCH 54/93] Update ME30 TMR drivers --- .../PeriphDrivers/Include/MAX32657/tmr.h | 2 +- Libraries/PeriphDrivers/Source/TMR/tmr_me30.c | 23 ++----------------- 2 files changed, 3 insertions(+), 22 deletions(-) diff --git a/Libraries/PeriphDrivers/Include/MAX32657/tmr.h b/Libraries/PeriphDrivers/Include/MAX32657/tmr.h index 89e3feb3760..9fd2c7d96ad 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/tmr.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/tmr.h @@ -137,10 +137,10 @@ typedef enum { /** * @brief Peripheral Clock settings */ +// TODO(ME30): TMR clock sources typedef enum { MXC_TMR_APB_CLK = 0, /**< PCLK */ MXC_TMR_EXT_CLK = 1, /**< External Clock */ - MXC_TMR_ISO_CLK = 2, /**< 60MHz Clock */ MXC_TMR_IBRO_CLK = 3, /**< 7.3728MHz Clock */ MXC_TMR_ERTCO_CLK = 4, /**< 32.768KHz Clock */ MXC_TMR_INRO_CLK = 5, /**< 8-30KHz Clock */ diff --git a/Libraries/PeriphDrivers/Source/TMR/tmr_me30.c b/Libraries/PeriphDrivers/Source/TMR/tmr_me30.c index 8c4404d6b6a..868caf34d47 100644 --- a/Libraries/PeriphDrivers/Source/TMR/tmr_me30.c +++ b/Libraries/PeriphDrivers/Source/TMR/tmr_me30.c @@ -19,7 +19,6 @@ #include "tmr.h" #include "tmr_revb.h" #include "tmr_common.h" -#include "lpgcr_regs.h" #include "stdbool.h" int MXC_TMR_Init(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg, bool init_pins) @@ -34,16 +33,6 @@ int MXC_TMR_Init(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg, bool init_pins) MXC_ASSERT(tmr_id >= 0); switch (cfg->clock) { - case MXC_TMR_ISO_CLK: - if (tmr_id > 3) { // Timers 4-5 do not support this clock source - return E_NOT_SUPPORTED; - } - - clockSource = MXC_TMR_CLK1; - MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_ISO); - MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, ISO_FREQ); - break; - case MXC_TMR_IBRO_CLK: if (tmr_id > 3) { // Timers 4-5 do not support this clock source return E_NOT_SUPPORTED; @@ -64,7 +53,6 @@ int MXC_TMR_Init(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg, bool init_pins) MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, (IBRO_FREQ / 8)); break; -#if (TARGET_NUM != 32680) case MXC_TMR_ERTCO_CLK: if (tmr_id == 4) { clockSource = MXC_TMR_CLK1; @@ -77,7 +65,6 @@ int MXC_TMR_Init(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg, bool init_pins) MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_ERTCO); MXC_TMR_RevB_SetClockSourceFreq((mxc_tmr_revb_regs_t *)tmr, ERTCO_FREQ); break; -#endif case MXC_TMR_INRO_CLK: if (tmr_id < 4) { // Timers 0-3 do not support this clock source @@ -154,12 +141,12 @@ int MXC_TMR_Init(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg, bool init_pins) break; case 4: - MXC_SYS_Reset_Periph(MXC_SYS_RESET_TMR4); + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TMR4); MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR4); break; case 5: - MXC_SYS_Reset_Periph(MXC_SYS_RESET_TMR5); + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_TMR5); MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TMR5); break; } @@ -265,19 +252,13 @@ uint32_t MXC_TMR_GetPeriod(mxc_tmr_regs_t *tmr, mxc_tmr_clock_t clock, uint32_t clockFrequency = PeripheralClock; break; - case MXC_TMR_ISO_CLK: - clockFrequency = ISO_FREQ; - break; - case MXC_TMR_IBRO_CLK: clockFrequency = IBRO_FREQ; break; -#if (TARGET_NUM != 32680) case MXC_TMR_ERTCO_CLK: clockFrequency = ERTCO_FREQ; break; -#endif default: break; From 58af5bcb3f5616d8d670e7648883997a35da3869 Mon Sep 17 00:00:00 2001 From: Jake Carter Date: Thu, 2 May 2024 17:43:20 -0600 Subject: [PATCH 55/93] Remove revision check from TRNG health test --- Libraries/PeriphDrivers/Source/TRNG/trng_me30.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/Libraries/PeriphDrivers/Source/TRNG/trng_me30.c b/Libraries/PeriphDrivers/Source/TRNG/trng_me30.c index 0875de46e2d..9d9725e5616 100644 --- a/Libraries/PeriphDrivers/Source/TRNG/trng_me30.c +++ b/Libraries/PeriphDrivers/Source/TRNG/trng_me30.c @@ -85,9 +85,5 @@ void MXC_TRNG_RandomAsync(uint8_t *data, uint32_t len, mxc_trng_complete_t callb int MXC_TRNG_HealthTest(void) { - if ((MXC_SYS_GetRevision() & 0xF0) == 0xA0) { // ME17 Rev. A does not support health tests. - return E_NOT_SUPPORTED; - } - return MXC_TRNG_RevB_HealthTest((mxc_trng_revb_regs_t *)MXC_TRNG); } From 1c753dcdf5089708d8e9697bf8560003a1097177 Mon Sep 17 00:00:00 2001 From: Jake Carter Date: Thu, 2 May 2024 17:56:19 -0600 Subject: [PATCH 56/93] Update ME30 UART drivers --- .../Device/Maxim/MAX32657/Include/max32657.h | 4 +- .../PeriphDrivers/Include/MAX32657/dma.h | 1 + .../PeriphDrivers/Include/MAX32657/uart.h | 306 +++++++------ .../PeriphDrivers/Source/UART/uart_me30.c | 401 +++++------------- 4 files changed, 276 insertions(+), 436 deletions(-) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h index 53e6036fabb..dba31a5a9f1 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h @@ -610,7 +610,9 @@ We may want to handle GET_IRQ better... /******************************************************************************/ /* DMA */ #define MXC_DMA_CHANNELS (4) -#define MXC_DMA_INSTANCES (2) +#define MXC_DMA_INSTANCES (1) +// ^ Note: We have 2 DMA instances in hardware, but they are secure vs non-secure +// instances. Therefore we treat the part as if there is only 1. /* Non-secure Mapping */ #define MXC_BASE_DMA0_NS ((uint32_t)0x40028000UL) diff --git a/Libraries/PeriphDrivers/Include/MAX32657/dma.h b/Libraries/PeriphDrivers/Include/MAX32657/dma.h index 747e5702681..ef471bb2ce4 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/dma.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/dma.h @@ -53,6 +53,7 @@ typedef enum { } mxc_dma_priority_t; /** @brief DMA request select */ +// TODO(ME30): Updated DMA reqsel typedef enum { MXC_DMA_REQUEST_MEMTOMEM = MXC_S_DMA_CTRL_REQUEST_MEMTOMEM, ///< Memory to Memory DMA Request Selection diff --git a/Libraries/PeriphDrivers/Include/MAX32657/uart.h b/Libraries/PeriphDrivers/Include/MAX32657/uart.h index 8acc38bb9b5..40e90877866 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/uart.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/uart.h @@ -1,11 +1,13 @@ /** * @file uart.h - * @brief Serial Peripheral Interface (UART) communications driver. + * @brief (UART) communications driver. */ /****************************************************************************** * - * Copyright (C) 2024 Analog Devices, Inc. + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -22,8 +24,8 @@ ******************************************************************************/ /* Define to prevent redundant inclusion */ -#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_UART_H_ -#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_UART_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32570_UART_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32570_UART_H_ /***** Definitions *****/ #include @@ -34,8 +36,6 @@ extern "C" { #endif -#define UART_EXTCLK_FREQ E_BAD_PARAM - /** * @defgroup uart UART * @ingroup periphlibs @@ -45,7 +45,7 @@ extern "C" { typedef struct _mxc_uart_req_t mxc_uart_req_t; /** * @brief The list of UART stop bit lengths supported - * + * */ typedef enum { MXC_UART_STOP_1, ///< UART Stop 1 clock cycle @@ -54,69 +54,67 @@ typedef enum { /** * @brief The list of UART Parity options supported - * + * */ typedef enum { MXC_UART_PARITY_DISABLE, ///< UART Parity Disabled + MXC_UART_PARITY_EVEN, ///< UART Parity Even + MXC_UART_PARITY_ODD, ///< UART Parity Odd + MXC_UART_PARITY_MARK, ///< UART Parity Mark + MXC_UART_PARITY_SPACE, ///< UART Parity Space MXC_UART_PARITY_EVEN_0, ///< UART Parity Even, 0 based MXC_UART_PARITY_EVEN_1, ///< UART Parity Even, 1 based MXC_UART_PARITY_ODD_0, ///< UART Parity Odd, 0 based MXC_UART_PARITY_ODD_1, ///< UART Parity Odd, 1 based + MXC_UART_PARITY_MARK_0, ///< UART Parity Mark, 0 based + MXC_UART_PARITY_MARK_1, ///< UART Parity Mark, 1 based + MXC_UART_PARITY_SPACE_0, ///< UART Parity Space, 0 based + MXC_UART_PARITY_SPACE_1, ///< UART Parity Space, 1 based } mxc_uart_parity_t; /** * @brief The list of UART flow control options supported - * + * */ typedef enum { MXC_UART_FLOW_DIS, ///< UART Flow Control Disabled - MXC_UART_FLOW_EN, ///< UART Flow Control Enabled + MXC_UART_FLOW_EN_LOW, ///< UART Flow Control Enabled, Active Low + MXC_UART_FLOW_EN_HIGH, ///< UART Flow Control Enabled, Active High } mxc_uart_flow_t; -/** - * @brief Clock settings */ -typedef enum { - /*Only available for UARTS 0-2*/ - MXC_UART_APB_CLK = 0, - /*Available for all UARTs*/ - MXC_UART_IBRO_CLK = 2, - /*ERTCO clock can only be used for UART3*/ - MXC_UART_ERTCO_CLK = 4, -} mxc_uart_clock_t; - /** * @brief The callback routine used to indicate the transaction has terminated. * - * @param req The details of the transaction. - * @param result See \ref MXC_Error_Codes for the list of error codes. + * @param req The details of the transaction. + * @param result See \ref MXC_Error_Codes for the list of error codes. */ typedef void (*mxc_uart_complete_cb_t)(mxc_uart_req_t *req, int result); /** * @brief The callback routine used to indicate the transaction has terminated. * - * @param req The details of the transaction. - * @param num The number of characters actually copied - * @param result See \ref MXC_Error_Codes for the list of error codes. + * @param req The details of the transaction. + * @param num The number of characters actually copied + * @param result See \ref MXC_Error_Codes for the list of error codes. */ typedef void (*mxc_uart_dma_complete_cb_t)(mxc_uart_req_t *req, int num, int result); /** - * @brief The information required to perform a complete UART transaction + * @brief The information required to perform a complete UART transaction. * - * @note This structure is used by blocking, async, and DMA based transactions. - * @note "callback" only needs to be initialized for interrupt driven (Async) and DMA transactions. + * This structure is used by blocking, async, and DMA based transactions. + * @note "callback" is only needed for interrupt driven (Async) and DMA transactions. */ struct _mxc_uart_req_t { mxc_uart_regs_t *uart; /// 8 bits, use two bytes per character - ///< and pad the MSB of the upper byte with zeros + uint8_t *txData; ///< Buffer containing transmit data. For character sizes + ///< < 8 bits, pad the MSB of each byte with zeros. For + ///< character sizes > 8 bits, use two bytes per character + ///< and pad the MSB of the upper byte with zeros uint8_t *rxData; ///< Buffer to store received data For character sizes - ///< < 8 bits, pad the MSB of each byte with zeros. For - ///< character sizes > 8 bits, use two bytes per character - ///< and pad the MSB of the upper byte with zeros + ///< < 8 bits, pad the MSB of each byte with zeros. For + ///< character sizes > 8 bits, use two bytes per character + ///< and pad the MSB of the upper byte with zeros uint32_t txLen; ///< Number of bytes to be sent from txData uint32_t rxLen; ///< Number of bytes to be stored in rxData volatile uint32_t txCnt; ///< Number of bytes actually transmitted from txData @@ -133,29 +131,25 @@ struct _mxc_uart_req_t { /** * @brief Initialize and enable UART peripheral. - * + * * This function initializes everything necessary to call a UART transaction function. * Some parameters are set to defaults as follows: * UART Data Size - 8 bits * UART Stop Bits - 1 bit * UART Parity - None * UART Flow Control - None - * + * UART Clock - 7.37MHz Clock (for baud > 7372800, PCLK is used) + * * These parameters can be modified after initialization using low level functions - * - * @note On default this function enables UART peripheral clock. - * if you wish to manage clock and gpio related things in upper level instead of here. - * Define MSDK_NO_GPIO_CLK_INIT flag in project.mk file. - * By this flag this function will remove clock and gpio related codes from file. - * - * @param uart Pointer to UART registers (selects the UART block used.) - * @param baud The requested clock frequency. The actual clock frequency - * will be returned by the function if successful. - * @param clock Clock source * - * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + * @param uart Pointer to UART registers (selects the UART block used.) + * @param baud The requested clock frequency. The actual clock frequency + * will be returned by the function if successful. + * + * @return If successful, the actual clock frequency is returned. Otherwise, see + * \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_Init(mxc_uart_regs_t *uart, unsigned int baud, mxc_uart_clock_t clock); +int MXC_UART_Init(mxc_uart_regs_t *uart, unsigned int baud); /** * @brief Disable and shutdown UART peripheral. @@ -183,14 +177,15 @@ int MXC_UART_ReadyForSleep(mxc_uart_regs_t *uart); /** * @brief Set the frequency of the UART interface. * - * @param uart Pointer to UART registers (selects the UART block used.) - * @param baud The desired baud rate - * @param clock Clock source + * + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param baud The desired baud rate * * @return Negative if error, otherwise actual speed set. See \ref * MXC_Error_Codes for the list of error return codes. */ -int MXC_UART_SetFrequency(mxc_uart_regs_t *uart, unsigned int baud, mxc_uart_clock_t clock); +int MXC_UART_SetFrequency(mxc_uart_regs_t *uart, unsigned int baud); /** * @brief Get the frequency of the UART interface. @@ -205,9 +200,9 @@ int MXC_UART_GetFrequency(mxc_uart_regs_t *uart); /** * @brief Sets the number of bits per character - * - * @param uart Pointer to UART registers (selects the UART block used.) - * @param dataSize The number of bits per character (5-8 bits/character are valid) + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param dataSize The number of bits per character (5-8 bits/character are valid) * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ @@ -215,9 +210,9 @@ int MXC_UART_SetDataSize(mxc_uart_regs_t *uart, int dataSize); /** * @brief Sets the number of stop bits sent at the end of a character - * - * @param uart Pointer to UART registers (selects the UART block used.) - * @param stopBits The number of stop bits used + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param stopBits The number of stop bits used * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ @@ -225,9 +220,9 @@ int MXC_UART_SetStopBits(mxc_uart_regs_t *uart, mxc_uart_stop_t stopBits); /** * @brief Sets the type of parity generation used - * - * @param uart Pointer to UART registers (selects the UART block used.) - * @param parity see \ref UART Parity Types for details + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param parity see \ref mxc_uart_parity_t UART Parity Types for details * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ @@ -235,10 +230,10 @@ int MXC_UART_SetParity(mxc_uart_regs_t *uart, mxc_uart_parity_t parity); /** * @brief Sets the flow control used - * - * @param uart Pointer to UART registers (selects the UART block used.) - * @param flowCtrl see \ref UART Flow Control Types for details - * @param rtsThreshold Number of bytes remaining in the RX FIFO when RTS is asserted + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param flowCtrl see \ref mxc_uart_flow_t UART Flow Control Types for details + * @param rtsThreshold Number of bytes remaining in the RX FIFO when RTS is asserted * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ @@ -246,24 +241,47 @@ int MXC_UART_SetFlowCtrl(mxc_uart_regs_t *uart, mxc_uart_flow_t flowCtrl, int rt /** * @brief Sets the clock source for the baud rate generator - * - * @param uart Pointer to UART registers (selects the UART block used.) - * @param clock Clock source * - * @return Actual baud rate if successful, otherwise see \ref MXC_Error_Codes + * @param uart Pointer to UART registers (selects the UART block used.) + * @param usePCLK Non-zero values will use the PCLK as the bit clock instead + * of the default 7.37MHz clock source. The baud rate generator + * will automatically be reconfigured to the closest possible + * baud rate. + * + * @return Actual baud rate if successful, otherwise see \ref MXC_Error_Codes * for a list of return codes. */ -int MXC_UART_SetClockSource(mxc_uart_regs_t *uart, mxc_uart_clock_t clock); +int MXC_UART_SetClockSource(mxc_uart_regs_t *uart, int usePCLK); + +/** + * @brief Enables or Disables the built-in null modem + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param nullModem Non-zero values will enable the null modem function, + * which swaps TXD/RXD and also swaps RTS/CTS, if used. + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_SetNullModem(mxc_uart_regs_t *uart, int nullModem); /* ************************************************************************* */ /* Low-level functions */ /* ************************************************************************* */ +/** + * @brief Transmits a Break Frame (all bits 0) + * + * @param uart Pointer to UART registers (selects the UART block used.) + * + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. + */ +int MXC_UART_SendBreak(mxc_uart_regs_t *uart); + /** * @brief Checks the UART Peripheral for an ongoing transmission * * @note This function is applicable in Master mode only - * + * * @param uart Pointer to UART registers (selects the UART block used.) * * @return Active/Inactive, see \ref MXC_Error_Codes for a list of return codes. @@ -280,44 +298,46 @@ int MXC_UART_GetActive(mxc_uart_regs_t *uart); int MXC_UART_AbortTransmission(mxc_uart_regs_t *uart); /** - * @brief Reads the next available character. If no character is available, this function - * will return an error. + * @brief Reads the next available character. This function will block until a character + * is available or a UART error occurs. * * @param uart Pointer to UART registers (selects the UART block used.) * * @return The character read, otherwise see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_ReadCharacterRaw(mxc_uart_regs_t *uart); +int MXC_UART_ReadCharacter(mxc_uart_regs_t *uart); /** - * @brief Writes a character on the UART. If the character cannot be written because the - * transmit FIFO is currently full, this function returns an error. + * @brief Writes a character on the UART. This function will block until the character + * has been placed in the TX FIFO or a UART error occurs. * * @param uart Pointer to UART registers (selects the UART block used.) * @param character The character to write * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_WriteCharacterRaw(mxc_uart_regs_t *uart, uint8_t character); +int MXC_UART_WriteCharacter(mxc_uart_regs_t *uart, uint8_t character); /** - * @brief Reads the next available character + * @brief Reads the next available character. If no character is available, this function + * will return an error. * * @param uart Pointer to UART registers (selects the UART block used.) * * @return The character read, otherwise see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_ReadCharacter(mxc_uart_regs_t *uart); +int MXC_UART_ReadCharacterRaw(mxc_uart_regs_t *uart); /** - * @brief Writes a character on the UART + * @brief Writes a character on the UART. If the character cannot be written because the + * transmit FIFO is currently full, this function returns an error. * * @param uart Pointer to UART registers (selects the UART block used.) - * @param character The character to write + * @param character The character to write * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_WriteCharacter(mxc_uart_regs_t *uart, uint8_t character); +int MXC_UART_WriteCharacterRaw(mxc_uart_regs_t *uart, uint8_t character); /** * @brief Reads the next available character @@ -326,7 +346,7 @@ int MXC_UART_WriteCharacter(mxc_uart_regs_t *uart, uint8_t character); * * @param uart Pointer to UART registers (selects the UART block used.) * @param buffer Buffer to store data in - * @param len Number of characters + * @param len Number of characters * * @return The character read, otherwise see \ref MXC_Error_Codes for a list of return codes. */ @@ -336,19 +356,19 @@ int MXC_UART_Read(mxc_uart_regs_t *uart, uint8_t *buffer, int *len); * @brief Writes a byte on the UART * * @param uart Pointer to UART registers (selects the UART block used.) - * @param byte The buffer of characters to write + * @param byte The buffer of characters to write * @param len The number of characters to write * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_Write(mxc_uart_regs_t *uart, const uint8_t *byte, int *len); +int MXC_UART_Write(mxc_uart_regs_t *uart, uint8_t *byte, int *len); /** * @brief Unloads bytes from the receive FIFO. * * @param uart Pointer to UART registers (selects the UART block used.) - * @param bytes The buffer to read the data into. - * @param len The number of bytes to read. + * @param bytes The buffer to read the data into. + * @param len The number of bytes to read. * * @return The number of bytes actually read. */ @@ -358,11 +378,11 @@ unsigned int MXC_UART_ReadRXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, un * @brief Unloads bytes from the receive FIFO user DMA for longer reads. * * @param uart Pointer to UART registers (selects the UART block used.) - * @param bytes The buffer to read the data into. - * @param len The number of bytes to read. - * @param callback The function to call when the read is complete + * @param bytes The buffer to read the data into. + * @param len The number of bytes to read. + * @param callback The function to call when the read is complete * - * @return See \ref MXC_ERROR_CODES for a list of return values + * @return See \ref MXC_Error_Codes for a list of return values */ int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len, mxc_uart_dma_complete_cb_t callback); @@ -380,25 +400,24 @@ unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart); * @brief Loads bytes into the transmit FIFO. * * @param uart Pointer to UART registers (selects the UART block used.) - * @param bytes The buffer containing the bytes to write - * @param len The number of bytes to write. + * @param bytes The buffer containing the bytes to write + * @param len The number of bytes to write. * * @return The number of bytes actually written. */ -unsigned int MXC_UART_WriteTXFIFO(mxc_uart_regs_t *uart, const unsigned char *bytes, - unsigned int len); +unsigned int MXC_UART_WriteTXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len); /** * @brief Loads bytes into the transmit FIFO using DMA for longer writes * * @param uart Pointer to UART registers (selects the UART block used.) - * @param bytes The buffer containing the bytes to write - * @param len The number of bytes to write. - * @param callback The function to call when the write is complete + * @param bytes The buffer containing the bytes to write + * @param len The number of bytes to write. + * @param callback The function to call when the write is complete * - * @return See \ref MXC_ERROR_CODES for a list of return values + * @return See \ref MXC_Error_Codes for a list of return values */ -int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, const unsigned char *bytes, unsigned int len, +int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len, mxc_uart_dma_complete_cb_t callback); /** @@ -430,18 +449,18 @@ int MXC_UART_ClearTXFIFO(mxc_uart_regs_t *uart); /** * @brief Set the receive threshold level. - * + * * @note RX FIFO Receive threshold. Smaller values will cause * interrupts to occur more often, but reduce the possibility * of losing data because of a FIFO overflow. Larger values - * will reduce the time required by the ISR, but increase the + * will reduce the time required by the ISR, but increase the * possibility of data loss. Passing an invalid value will - * cause the driver to use the value already set in the + * cause the driver to use the value already set in the * appropriate register. * * @param uart Pointer to UART registers (selects the UART block used.) - * @param numBytes The threshold level to set. This value must be - * between 0 and 8 inclusive. + * @param numBytes The threshold level to set. This value must be + * between 0 and 8 inclusive. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ @@ -449,27 +468,27 @@ int MXC_UART_SetRXThreshold(mxc_uart_regs_t *uart, unsigned int numBytes); /** * @brief Get the current receive threshold level. - * + * * @param uart Pointer to UART registers (selects the UART block used.) - * + * * @return The receive threshold value (in bytes). */ unsigned int MXC_UART_GetRXThreshold(mxc_uart_regs_t *uart); /** * @brief Set the transmit threshold level. - * + * * @note TX FIFO threshold. Smaller values will cause interrupts * to occur more often, but reduce the possibility of terminating * a transaction early in master mode, or transmitting invalid data * in slave mode. Larger values will reduce the time required by - * the ISR, but increase the possibility errors occurring. Passing - * an invalid value will cause the driver to use the value already + * the ISR, but increase the possibility errors occurring. Passing + * an invalid value will cause the driver to use the value already * set in the appropriate register. * * @param uart Pointer to UART registers (selects the UART block used.) - * @param numBytes The threshold level to set. This value must be - * between 0 and 8 inclusive. + * @param numBytes The threshold level to set. This value must be + * between 0 and 8 inclusive. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ @@ -477,9 +496,9 @@ int MXC_UART_SetTXThreshold(mxc_uart_regs_t *uart, unsigned int numBytes); /** * @brief Get the current transmit threshold level. - * + * * @param uart Pointer to UART registers (selects the UART block used.) - * + * * @return The transmit threshold value (in bytes). */ unsigned int MXC_UART_GetTXThreshold(mxc_uart_regs_t *uart); @@ -487,24 +506,24 @@ unsigned int MXC_UART_GetTXThreshold(mxc_uart_regs_t *uart); /** * @brief Gets the interrupt flags that are currently set * - * @note These functions should not be used while using non-blocking Transaction Level + * @note These functions should not be used while using non-blocking Transaction Level * functions (Async or DMA) * * @param uart Pointer to UART registers (selects the UART block used.) - * - * @return The interrupt flags + * + * @return The interrupt flags */ unsigned int MXC_UART_GetFlags(mxc_uart_regs_t *uart); /** * @brief Clears the interrupt flags that are currently set * - * @note These functions should not be used while using non-blocking Transaction Level + * @note These functions should not be used while using non-blocking Transaction Level * functions (Async or DMA) * * @param uart Pointer to UART registers (selects the UART block used.) * @param flags mask of flags to clear - * + * * @return See \ref MXC_Error_Codes for the list of error return codes. */ int MXC_UART_ClearFlags(mxc_uart_regs_t *uart, unsigned int flags); @@ -512,7 +531,7 @@ int MXC_UART_ClearFlags(mxc_uart_regs_t *uart, unsigned int flags); /** * @brief Enables specific interrupts * - * @note These functions should not be used while using non-blocking Transaction Level + * @note These functions should not be used while using non-blocking Transaction Level * functions (Async or DMA) * * @param uart Pointer to UART registers (selects the UART block used.) @@ -525,7 +544,7 @@ int MXC_UART_EnableInt(mxc_uart_regs_t *uart, unsigned int mask); /** * @brief Disables specific interrupts * - * @note These functions should not be used while using non-blocking Transaction Level + * @note These functions should not be used while using non-blocking Transaction Level * functions (Async or DMA) * * @param uart Pointer to UART registers (selects the UART block used.) @@ -539,7 +558,7 @@ int MXC_UART_DisableInt(mxc_uart_regs_t *uart, unsigned int mask); * @brief Gets the status flags that are currently set * * @param uart Pointer to UART registers (selects the UART block used.) - * + * * @return The status flags */ unsigned int MXC_UART_GetStatus(mxc_uart_regs_t *uart); @@ -549,13 +568,13 @@ unsigned int MXC_UART_GetStatus(mxc_uart_regs_t *uart); /* ************************************************************************* */ /** - * @brief Performs a blocking UART transaction. - * + * @brief Performs a blocking UART transaction. + * * @note Performs a blocking UART transaction as follows. * If tx_len is non-zero, transmit TX data * Once tx_len has been sent, if rx_len is non-zero, receive data * - * @param req Pointer to details of the transaction + * @param req Pointer to details of the transaction * * @return See \ref MXC_Error_Codes for the list of error return codes. */ @@ -563,11 +582,11 @@ int MXC_UART_Transaction(mxc_uart_req_t *req); /** * @brief Setup an interrupt-driven UART transaction - * + * * @note The TX FIFO will be filled with txData if necessary * Relevant interrupts will be enabled * - * @param req Pointer to details of the transaction + * @param req Pointer to details of the transaction * * @return See \ref MXC_Error_Codes for the list of error return codes. */ @@ -575,14 +594,14 @@ int MXC_UART_TransactionAsync(mxc_uart_req_t *req); /** * @brief Setup a DMA driven UART transaction - * + * * @note The TX FIFO will be filled with txData if necessary - * Relevant interrupts will be enabled - * The DMA channel indicated by the request will be set up to load/unload the FIFOs - * with as few interrupt-based events as possible. The channel will be reset and + * Relevant interrupts will be enabled. + * The DMA channel indicated by the request will be set up to load/unload the FIFOs + * with as few interrupt-based events as possible. The channel will be reset and * returned to the system at the end of the transaction. * - * @param req Pointer to details of the transaction + * @param req Pointer to details of the transaction * * @return See \ref MXC_Error_Codes for the list of error return codes. */ @@ -600,23 +619,27 @@ int MXC_UART_TransactionDMA(mxc_uart_req_t *req); void MXC_UART_DMACallback(int ch, int error); /** - * @brief Async callback + * @brief Async callback * - * @param uart The uart - * @param retVal The ret value + * @param uart The uart + * @param[in] retVal The ret value * * @return See \ref MXC_Error_Codes for the list of error return codes. */ int MXC_UART_AsyncCallback(mxc_uart_regs_t *uart, int retVal); +int MXC_UART_TxAsyncCallback(mxc_uart_regs_t *uart, int retVal); +int MXC_UART_RxAsyncCallback(mxc_uart_regs_t *uart, int retVal); /** * @brief stop any async callbacks * - * @param uart The uart + * @param uart The uart * * @return See \ref MXC_Error_Codes for the list of error return codes. */ int MXC_UART_AsyncStop(mxc_uart_regs_t *uart); +int MXC_UART_TxAsyncStop(mxc_uart_regs_t *uart); +int MXC_UART_RxAsyncStop(mxc_uart_regs_t *uart); /** * @brief Abort any asynchronous requests in progress. @@ -630,6 +653,8 @@ int MXC_UART_AsyncStop(mxc_uart_regs_t *uart); * @return See \ref MXC_Error_Codes for the list of error return codes. */ int MXC_UART_AbortAsync(mxc_uart_regs_t *uart); +int MXC_UART_TxAbortAsync(mxc_uart_regs_t *uart); +int MXC_UART_RxAbortAsync(mxc_uart_regs_t *uart); /** * @brief The processing function for asynchronous transactions. @@ -642,8 +667,8 @@ int MXC_UART_AbortAsync(mxc_uart_regs_t *uart); * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_UART_AsyncHandler(mxc_uart_regs_t *uart); +int MXC_UART_AsyncHandler(mxc_uart_regs_t *uart); /** * @brief Provide TXCount for asynchronous transactions.. * @@ -651,6 +676,7 @@ int MXC_UART_AsyncHandler(mxc_uart_regs_t *uart); * * @return Returns transmit bytes (in FIFO). */ + uint32_t MXC_UART_GetAsyncTXCount(mxc_uart_req_t *req); /** @@ -731,4 +757,4 @@ int MXC_UART_GetRXDMAChannel(mxc_uart_regs_t *uart); } #endif -#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_UART_H_ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32570_UART_H_ diff --git a/Libraries/PeriphDrivers/Source/UART/uart_me30.c b/Libraries/PeriphDrivers/Source/UART/uart_me30.c index 32b722c786c..83eb8202790 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_me30.c +++ b/Libraries/PeriphDrivers/Source/UART/uart_me30.c @@ -1,6 +1,8 @@ /****************************************************************************** * - * Copyright (C) 2024 Analog Devices, Inc. + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -20,29 +22,47 @@ #include "mxc_device.h" #include "mxc_pins.h" #include "mxc_assert.h" -#include "uart_revb.h" +#include "uart_reva.h" #include "uart_common.h" -#include "lpgcr_regs.h" #include "dma.h" void MXC_UART_DMACallback(int ch, int error) { - MXC_UART_RevB_DMACallback(ch, error); + MXC_UART_RevA_DMACallback(ch, error); } int MXC_UART_AsyncCallback(mxc_uart_regs_t *uart, int retVal) { - return MXC_UART_RevB_AsyncCallback((mxc_uart_revb_regs_t *)uart, retVal); + return MXC_UART_RevA_AsyncCallback((mxc_uart_reva_regs_t *)uart, retVal); +} + +int MXC_UART_TxAsyncCallback(mxc_uart_regs_t *uart, int retVal) +{ + return MXC_UART_RevA_TxAsyncCallback((mxc_uart_reva_regs_t *)uart, retVal); +} + +int MXC_UART_RxAsyncCallback(mxc_uart_regs_t *uart, int retVal) +{ + return MXC_UART_RevA_RxAsyncCallback((mxc_uart_reva_regs_t *)uart, retVal); } int MXC_UART_AsyncStop(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_AsyncStop((mxc_uart_revb_regs_t *)uart); + return MXC_UART_RevA_AsyncStop((mxc_uart_reva_regs_t *)uart); } -int MXC_UART_Init(mxc_uart_regs_t *uart, unsigned int baud, mxc_uart_clock_t clock) +int MXC_UART_TxAsyncStop(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevA_TxAsyncStop((mxc_uart_reva_regs_t *)uart); +} + +int MXC_UART_RxAsyncStop(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevA_RxAsyncStop((mxc_uart_reva_regs_t *)uart); +} + +int MXC_UART_Init(mxc_uart_regs_t *uart, unsigned int baud) { -#ifndef MSDK_NO_GPIO_CLK_INIT int retval; retval = MXC_UART_Shutdown(uart); @@ -51,261 +71,90 @@ int MXC_UART_Init(mxc_uart_regs_t *uart, unsigned int baud, mxc_uart_clock_t clo return retval; } - switch (clock) { -#if TARGET_NUM != 32680 - case MXC_UART_ERTCO_CLK: - MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_ERTCO); - break; -#endif - - case MXC_UART_IBRO_CLK: - MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_IBRO); - break; - - default: - break; - } - - switch (MXC_UART_GET_IDX(uart)) { - case 0: - MXC_GPIO_Config(&gpio_cfg_uart0); - MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_UART0); - break; - - case 1: - MXC_GPIO_Config(&gpio_cfg_uart1); - MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_UART1); - break; - - case 2: - MXC_GPIO_Config(&gpio_cfg_uart2); - MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_UART2); - break; - - case 3: - MXC_GPIO_Config(&gpio_cfg_uart3); - MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_UART3); - break; - - default: - return E_BAD_PARAM; - } -#endif // MSDK_NO_GPIO_CLK_INIT + MXC_GPIO_Config(&gpio_cfg_uart0); + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_UART); - return MXC_UART_RevB_Init((mxc_uart_revb_regs_t *)uart, baud, clock); + return MXC_UART_RevA_Init((mxc_uart_reva_regs_t *)uart, baud); } int MXC_UART_Shutdown(mxc_uart_regs_t *uart) { - switch (MXC_UART_GET_IDX(uart)) { - case 0: - MXC_SYS_Reset_Periph(MXC_SYS_RESET0_UART0); - MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_UART0); - break; - - case 1: - MXC_SYS_Reset_Periph(MXC_SYS_RESET0_UART1); - MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_UART1); - break; - - case 2: - MXC_SYS_Reset_Periph(MXC_SYS_RESET0_UART2); - MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_UART2); - break; - - case 3: - MXC_SYS_Reset_Periph(MXC_SYS_RESET_UART3); - MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_UART3); - break; - - default: - return E_BAD_PARAM; - } + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_UART); + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_UART); return E_NO_ERROR; } int MXC_UART_ReadyForSleep(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_ReadyForSleep((mxc_uart_revb_regs_t *)uart); + return MXC_UART_RevA_ReadyForSleep((mxc_uart_reva_regs_t *)uart); } -int MXC_UART_SetFrequency(mxc_uart_regs_t *uart, unsigned int baud, mxc_uart_clock_t clock) +int MXC_UART_SetFrequency(mxc_uart_regs_t *uart, unsigned int baud) { - int freq; - unsigned mod = 0; - unsigned clkDiv = 0; - - if (MXC_UART_GET_IDX(uart) < 0) { - return E_BAD_PARAM; - } - - // check if the uart is LPUART - if (uart == MXC_UART3) { - // OSR default value - uart->osr = 5; - - switch (clock) { - case MXC_UART_IBRO_CLK: - uart->ctrl |= MXC_S_UART_CTRL_BCLKSRC_PERIPHERAL_CLOCK; - clkDiv = ((IBRO_FREQ) / baud); - mod = ((IBRO_FREQ) % baud); - break; - - case MXC_UART_ERTCO_CLK: - // Only supports up to 9600 baud with ERTCO clock. - if (baud > 9600) { - return E_NOT_SUPPORTED; - } - - uart->ctrl |= MXC_S_UART_CTRL_BCLKSRC_EXTERNAL_CLOCK; - uart->ctrl |= MXC_F_UART_CTRL_FDM; - if (baud == 9600) { - clkDiv = 7; - mod = 0; - } else { - clkDiv = ((ERTCO_FREQ * 2) / baud); - mod = ((ERTCO_FREQ * 2) % baud); - } - - if (baud > 2400) { - uart->osr = 0; - } else { - uart->osr = 1; - } - break; - - default: - return E_BAD_PARAM; - } - - if (!clkDiv || mod > (baud / 2)) { - clkDiv++; - } - uart->clkdiv = clkDiv; - - freq = MXC_UART_GetFrequency(uart); - } else { - if (clock == MXC_UART_ERTCO_CLK) { - return E_BAD_PARAM; - } - - freq = MXC_UART_RevB_SetFrequency((mxc_uart_revb_regs_t *)uart, baud, clock); - } - - if (freq > 0) { - // Enable baud clock and wait for it to become ready. - uart->ctrl |= MXC_F_UART_CTRL_BCLKEN; - while (((uart->ctrl & MXC_F_UART_CTRL_BCLKRDY) >> MXC_F_UART_CTRL_BCLKRDY_POS) == 0) {} - } - - return freq; + return MXC_UART_RevA_SetFrequency((mxc_uart_reva_regs_t *)uart, baud); } int MXC_UART_GetFrequency(mxc_uart_regs_t *uart) { - int periphClock = 0; - - if (MXC_UART_GET_IDX(uart) < 0) { - return E_BAD_PARAM; - } - - // check if UART is LP UART - if (uart == MXC_UART3) { - if ((uart->ctrl & MXC_F_UART_CTRL_BCLKSRC) == - MXC_S_UART_REVB_CTRL_BCLKSRC_PERIPHERAL_CLOCK) { - periphClock = IBRO_FREQ; - } else if ((uart->ctrl & MXC_F_UART_CTRL_BCLKSRC) == - MXC_S_UART_REVB_CTRL_BCLKSRC_EXTERNAL_CLOCK) { - periphClock = ERTCO_FREQ * 2; - } else { - return E_NOT_SUPPORTED; - } - return (periphClock / uart->clkdiv); - } else { - return MXC_UART_RevB_GetFrequency((mxc_uart_revb_regs_t *)uart); - } + return MXC_UART_RevA_GetFrequency((mxc_uart_reva_regs_t *)uart); } int MXC_UART_SetDataSize(mxc_uart_regs_t *uart, int dataSize) { - return MXC_UART_RevB_SetDataSize((mxc_uart_revb_regs_t *)uart, dataSize); + return MXC_UART_RevA_SetDataSize((mxc_uart_reva_regs_t *)uart, dataSize); } int MXC_UART_SetStopBits(mxc_uart_regs_t *uart, mxc_uart_stop_t stopBits) { - return MXC_UART_RevB_SetStopBits((mxc_uart_revb_regs_t *)uart, stopBits); + return MXC_UART_RevA_SetStopBits((mxc_uart_reva_regs_t *)uart, stopBits); } int MXC_UART_SetParity(mxc_uart_regs_t *uart, mxc_uart_parity_t parity) { - return MXC_UART_RevB_SetParity((mxc_uart_revb_regs_t *)uart, parity); + return MXC_UART_RevA_SetParity((mxc_uart_reva_regs_t *)uart, parity); } int MXC_UART_SetFlowCtrl(mxc_uart_regs_t *uart, mxc_uart_flow_t flowCtrl, int rtsThreshold) { - if (flowCtrl == MXC_UART_FLOW_EN) { - switch (MXC_UART_GET_IDX(uart)) { - case 0: - MXC_GPIO_Config(&gpio_cfg_uart0_flow); - break; - - case 1: - MXC_GPIO_Config(&gpio_cfg_uart1_flow); - break; - - case 2: - MXC_GPIO_Config(&gpio_cfg_uart2_flow); - break; - - default: - return E_BAD_PARAM; - } - } else { - switch (MXC_UART_GET_IDX(uart)) { - case 0: - MXC_GPIO_Config(&gpio_cfg_uart0_flow_disable); - break; - - case 1: - MXC_GPIO_Config(&gpio_cfg_uart1_flow_disable); - break; - - case 2: - MXC_GPIO_Config(&gpio_cfg_uart2_flow_disable); - break; - - default: - return E_BAD_PARAM; - } - } + MXC_GPIO_Config(&gpio_cfg_uart0_flow); - return MXC_UART_RevB_SetFlowCtrl((mxc_uart_revb_regs_t *)uart, flowCtrl, rtsThreshold); + return MXC_UART_RevA_SetFlowCtrl((mxc_uart_reva_regs_t *)uart, flowCtrl, rtsThreshold); } -int MXC_UART_SetClockSource(mxc_uart_regs_t *uart, mxc_uart_clock_t clock) +int MXC_UART_SetClockSource(mxc_uart_regs_t *uart, int usePCLK) { - return MXC_UART_RevB_SetClockSource((mxc_uart_revb_regs_t *)uart, clock); + return MXC_UART_RevA_SetClockSource((mxc_uart_reva_regs_t *)uart, usePCLK); +} + +int MXC_UART_SetNullModem(mxc_uart_regs_t *uart, int nullModem) +{ + return MXC_UART_RevA_SetNullModem((mxc_uart_reva_regs_t *)uart, nullModem); +} + +int MXC_UART_SendBreak(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevA_SendBreak((mxc_uart_reva_regs_t *)uart); } int MXC_UART_GetActive(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_GetActive((mxc_uart_revb_regs_t *)uart); + return MXC_UART_RevA_GetActive((mxc_uart_reva_regs_t *)uart); } int MXC_UART_AbortTransmission(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_AbortTransmission((mxc_uart_revb_regs_t *)uart); + return MXC_UART_RevA_AbortTransmission((mxc_uart_reva_regs_t *)uart); } int MXC_UART_ReadCharacterRaw(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_ReadCharacterRaw((mxc_uart_revb_regs_t *)uart); + return MXC_UART_RevA_ReadCharacterRaw((mxc_uart_reva_regs_t *)uart); } int MXC_UART_WriteCharacterRaw(mxc_uart_regs_t *uart, uint8_t character) { - return MXC_UART_RevB_WriteCharacterRaw((mxc_uart_revb_regs_t *)uart, character); + return MXC_UART_RevA_WriteCharacterRaw((mxc_uart_reva_regs_t *)uart, character); } int MXC_UART_ReadCharacter(mxc_uart_regs_t *uart) @@ -320,176 +169,142 @@ int MXC_UART_WriteCharacter(mxc_uart_regs_t *uart, uint8_t character) int MXC_UART_Read(mxc_uart_regs_t *uart, uint8_t *buffer, int *len) { - return MXC_UART_RevB_Read((mxc_uart_revb_regs_t *)uart, buffer, len); + return MXC_UART_RevA_Read((mxc_uart_reva_regs_t *)uart, buffer, len); } -int MXC_UART_Write(mxc_uart_regs_t *uart, const uint8_t *byte, int *len) +int MXC_UART_Write(mxc_uart_regs_t *uart, uint8_t *byte, int *len) { - return MXC_UART_RevB_Write((mxc_uart_revb_regs_t *)uart, byte, len); + return MXC_UART_RevA_Write((mxc_uart_reva_regs_t *)uart, byte, len); } unsigned int MXC_UART_ReadRXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len) { - return MXC_UART_RevB_ReadRXFIFO((mxc_uart_revb_regs_t *)uart, bytes, len); + return MXC_UART_RevA_ReadRXFIFO((mxc_uart_reva_regs_t *)uart, bytes, len); } int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len, mxc_uart_dma_complete_cb_t callback) { mxc_dma_config_t config; + config.reqsel = MXC_DMA_REQUEST_UART0RX; // TODO(ME30): Updated DMA reqsel - int uart_num = MXC_UART_GET_IDX(uart); - - switch (uart_num) { - case 0: - config.reqsel = MXC_DMA_REQUEST_UART0RX; - break; - - case 1: - config.reqsel = MXC_DMA_REQUEST_UART1RX; - break; - - case 2: - config.reqsel = MXC_DMA_REQUEST_UART2RX; - break; - - case 3: - config.reqsel = MXC_DMA_REQUEST_UART3RX; - break; - - default: - return E_BAD_PARAM; - break; - } - - return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); + return MXC_UART_RevA_ReadRXFIFODMA((mxc_uart_reva_regs_t *)uart, MXC_DMA, bytes, len, callback, + config); } unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_GetRXFIFOAvailable((mxc_uart_revb_regs_t *)uart); + return MXC_UART_RevA_GetRXFIFOAvailable((mxc_uart_reva_regs_t *)uart); } -unsigned int MXC_UART_WriteTXFIFO(mxc_uart_regs_t *uart, const unsigned char *bytes, - unsigned int len) +unsigned int MXC_UART_WriteTXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len) { - return MXC_UART_RevB_WriteTXFIFO((mxc_uart_revb_regs_t *)uart, bytes, len); + return MXC_UART_RevA_WriteTXFIFO((mxc_uart_reva_regs_t *)uart, bytes, len); } -int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, const unsigned char *bytes, unsigned int len, +int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len, mxc_uart_dma_complete_cb_t callback) { mxc_dma_config_t config; + config.reqsel = MXC_DMA_REQUEST_UART0TX; // TODO(ME30): Updated DMA reqsel - int uart_num = MXC_UART_GET_IDX(uart); - switch (uart_num) { - case 0: - config.reqsel = MXC_DMA_REQUEST_UART0TX; - break; - - case 1: - config.reqsel = MXC_DMA_REQUEST_UART1TX; - break; - - case 2: - config.reqsel = MXC_DMA_REQUEST_UART2TX; - break; - - case 3: - config.reqsel = MXC_DMA_REQUEST_UART3TX; - break; - - default: - return E_BAD_PARAM; - break; - } - - return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); + return MXC_UART_RevA_WriteTXFIFODMA((mxc_uart_reva_regs_t *)uart, MXC_DMA, bytes, len, callback, + config); } unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_GetTXFIFOAvailable((mxc_uart_revb_regs_t *)uart); + return MXC_UART_RevA_GetTXFIFOAvailable((mxc_uart_reva_regs_t *)uart); } int MXC_UART_ClearRXFIFO(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_ClearRXFIFO((mxc_uart_revb_regs_t *)uart); + return MXC_UART_RevA_ClearRXFIFO((mxc_uart_reva_regs_t *)uart); } int MXC_UART_ClearTXFIFO(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_ClearTXFIFO((mxc_uart_revb_regs_t *)uart); + return MXC_UART_RevA_ClearTXFIFO((mxc_uart_reva_regs_t *)uart); } int MXC_UART_SetRXThreshold(mxc_uart_regs_t *uart, unsigned int numBytes) { - return MXC_UART_RevB_SetRXThreshold((mxc_uart_revb_regs_t *)uart, numBytes); + return MXC_UART_RevA_SetRXThreshold((mxc_uart_reva_regs_t *)uart, numBytes); } unsigned int MXC_UART_GetRXThreshold(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_GetRXThreshold((mxc_uart_revb_regs_t *)uart); + return MXC_UART_RevA_GetRXThreshold((mxc_uart_reva_regs_t *)uart); } int MXC_UART_SetTXThreshold(mxc_uart_regs_t *uart, unsigned int numBytes) { - return E_NOT_SUPPORTED; + return MXC_UART_RevA_SetTXThreshold((mxc_uart_reva_regs_t *)uart, numBytes); } unsigned int MXC_UART_GetTXThreshold(mxc_uart_regs_t *uart) { - return E_NOT_SUPPORTED; + return MXC_UART_RevA_GetTXThreshold((mxc_uart_reva_regs_t *)uart); } unsigned int MXC_UART_GetFlags(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_GetFlags((mxc_uart_revb_regs_t *)uart); + return MXC_UART_RevA_GetFlags((mxc_uart_reva_regs_t *)uart); } int MXC_UART_ClearFlags(mxc_uart_regs_t *uart, unsigned int flags) { - return MXC_UART_RevB_ClearFlags((mxc_uart_revb_regs_t *)uart, flags); + return MXC_UART_RevA_ClearFlags((mxc_uart_reva_regs_t *)uart, flags); } -int MXC_UART_EnableInt(mxc_uart_regs_t *uart, unsigned int intEn) +int MXC_UART_EnableInt(mxc_uart_regs_t *uart, unsigned int mask) { - return MXC_UART_RevB_EnableInt((mxc_uart_revb_regs_t *)uart, intEn); + return MXC_UART_RevA_EnableInt((mxc_uart_reva_regs_t *)uart, mask); } -int MXC_UART_DisableInt(mxc_uart_regs_t *uart, unsigned int intDis) +int MXC_UART_DisableInt(mxc_uart_regs_t *uart, unsigned int mask) { - return MXC_UART_RevB_DisableInt((mxc_uart_revb_regs_t *)uart, intDis); + return MXC_UART_RevA_DisableInt((mxc_uart_reva_regs_t *)uart, mask); } unsigned int MXC_UART_GetStatus(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_GetStatus((mxc_uart_revb_regs_t *)uart); + return MXC_UART_RevA_GetStatus((mxc_uart_reva_regs_t *)uart); } int MXC_UART_Transaction(mxc_uart_req_t *req) { - return MXC_UART_RevB_Transaction((mxc_uart_revb_req_t *)req); + return MXC_UART_RevA_Transaction((mxc_uart_reva_req_t *)req); } int MXC_UART_TransactionAsync(mxc_uart_req_t *req) { - return MXC_UART_RevB_TransactionAsync((mxc_uart_revb_req_t *)req); + return MXC_UART_RevA_TransactionAsync((mxc_uart_reva_req_t *)req); } int MXC_UART_TransactionDMA(mxc_uart_req_t *req) { - return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req); + return MXC_UART_RevA_TransactionDMA((mxc_uart_reva_req_t *)req, MXC_DMA); } int MXC_UART_AbortAsync(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_AbortAsync((mxc_uart_revb_regs_t *)uart); + return MXC_UART_RevA_AbortAsync((mxc_uart_reva_regs_t *)uart); +} + +int MXC_UART_TxAbortAsync(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevA_TxAbortAsync((mxc_uart_reva_regs_t *)uart); +} + +int MXC_UART_RxAbortAsync(mxc_uart_regs_t *uart) +{ + return MXC_UART_RevA_RxAbortAsync((mxc_uart_reva_regs_t *)uart); } int MXC_UART_AsyncHandler(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_AsyncHandler((mxc_uart_revb_regs_t *)uart); + return MXC_UART_RevA_AsyncHandler((mxc_uart_reva_regs_t *)uart); } uint32_t MXC_UART_GetAsyncTXCount(mxc_uart_req_t *req) @@ -504,25 +319,21 @@ uint32_t MXC_UART_GetAsyncRXCount(mxc_uart_req_t *req) int MXC_UART_SetAutoDMAHandlers(mxc_uart_regs_t *uart, bool enable) { - return MXC_UART_RevB_SetAutoDMAHandlers((mxc_uart_revb_regs_t *)uart, enable); + return MXC_UART_RevA_SetAutoDMAHandlers((mxc_uart_reva_regs_t *)uart, enable); } - int MXC_UART_SetTXDMAChannel(mxc_uart_regs_t *uart, unsigned int channel) { - return MXC_UART_RevB_SetTXDMAChannel((mxc_uart_revb_regs_t *)uart, channel); + return MXC_UART_RevA_SetTXDMAChannel((mxc_uart_reva_regs_t *)uart, channel); } - int MXC_UART_GetTXDMAChannel(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_GetTXDMAChannel((mxc_uart_revb_regs_t *)uart); + return MXC_UART_RevA_GetTXDMAChannel((mxc_uart_reva_regs_t *)uart); } - int MXC_UART_SetRXDMAChannel(mxc_uart_regs_t *uart, unsigned int channel) { - return MXC_UART_RevB_SetRXDMAChannel((mxc_uart_revb_regs_t *)uart, channel); + return MXC_UART_RevA_SetRXDMAChannel((mxc_uart_reva_regs_t *)uart, channel); } - int MXC_UART_GetRXDMAChannel(mxc_uart_regs_t *uart) { - return MXC_UART_RevB_GetTXDMAChannel((mxc_uart_revb_regs_t *)uart); + return MXC_UART_RevA_GetRXDMAChannel((mxc_uart_reva_regs_t *)uart); } From ed64a6d1f89d9b2393231b3a757d48defb2e8049 Mon Sep 17 00:00:00 2001 From: Jake Carter Date: Thu, 2 May 2024 18:01:19 -0600 Subject: [PATCH 57/93] Update ME30 WDT drivers --- Libraries/PeriphDrivers/Source/WDT/wdt_me30.c | 35 +++++-------------- 1 file changed, 9 insertions(+), 26 deletions(-) diff --git a/Libraries/PeriphDrivers/Source/WDT/wdt_me30.c b/Libraries/PeriphDrivers/Source/WDT/wdt_me30.c index 0c761e70c7e..8c1af1514bf 100644 --- a/Libraries/PeriphDrivers/Source/WDT/wdt_me30.c +++ b/Libraries/PeriphDrivers/Source/WDT/wdt_me30.c @@ -29,27 +29,22 @@ int MXC_WDT_Init(mxc_wdt_regs_t *wdt, mxc_wdt_cfg_t *cfg) { #ifndef MSDK_NO_GPIO_CLK_INIT - if (wdt == MXC_WDT0) { - MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_WDT0); - } else if (wdt == MXC_WDT1) { - MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_WDT1); + if (wdt == MXC_WDT) { + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_WDT); } else { return E_BAD_PARAM; } #endif - MXC_WDT_RevB_Init((mxc_wdt_revb_regs_t *)wdt, (mxc_wdt_revb_cfg_t *)cfg); - - return E_NO_ERROR; + return MXC_WDT_RevB_Init((mxc_wdt_revb_regs_t *)wdt, (mxc_wdt_revb_cfg_t *)cfg); } int MXC_WDT_Shutdown(mxc_wdt_regs_t *wdt) { - if (wdt == MXC_WDT0) { - MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_WDT0); - } else if (wdt == MXC_WDT1) { - MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_WDT1); - } else { + if (wdt == MXC_WDT) { + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_WDT); + } + else { return E_BAD_PARAM; } @@ -127,24 +122,12 @@ int MXC_WDT_SetClockSource(mxc_wdt_regs_t *wdt, mxc_wdt_clock_t clock_source) uint8_t idx = 0; uint8_t instance = 0; -#if TARGET_NUM == 32655 || TARGET_NUM == 78000 - mxc_wdt_clock_t clock_sources[2][8] = { + mxc_wdt_clock_t clock_sources[1][8] = { { MXC_WDT_PCLK, MXC_WDT_IBRO_CLK, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, - { MXC_WDT_IBRO_CLK, MXC_WDT_INRO_CLK, MXC_WDT_ERTCO_CLK, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } }; -#elif TARGET_NUM == 32680 - mxc_wdt_clock_t clock_sources[2][8] = { - { MXC_WDT_PCLK, MXC_WDT_IBRO_CLK, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }, - { MXC_WDT_IBRO_CLK, 0xFF, MXC_WDT_INRO_CLK, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF } - }; -#else -#error ME17 WDT driver does not support given target number. -#endif - if (wdt == MXC_WDT0) { + if (wdt == MXC_WDT) { instance = 0; - } else if (wdt == MXC_WDT1) { - instance = 1; } else { return E_BAD_PARAM; } From 4c9522a5ec8b79176ff8f158cc97ae82a7c7d404 Mon Sep 17 00:00:00 2001 From: Jake Carter Date: Thu, 2 May 2024 18:03:13 -0600 Subject: [PATCH 58/93] Misc final fixes --- Libraries/Boards/MAX32657/EvKit_V1/Source/board.c | 2 +- Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/Libraries/Boards/MAX32657/EvKit_V1/Source/board.c b/Libraries/Boards/MAX32657/EvKit_V1/Source/board.c index 4d02252ff00..f0bdcddf5e0 100644 --- a/Libraries/Boards/MAX32657/EvKit_V1/Source/board.c +++ b/Libraries/Boards/MAX32657/EvKit_V1/Source/board.c @@ -92,7 +92,7 @@ int Console_Init(void) { int err; - if ((err = MXC_UART_Init(ConsoleUart, CONSOLE_BAUD, MXC_UART_APB_CLK)) != E_NO_ERROR) { + if ((err = MXC_UART_Init(ConsoleUart, CONSOLE_BAUD)) != E_NO_ERROR) { return err; } diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h index dba31a5a9f1..b3b9c1b337a 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h @@ -672,7 +672,7 @@ We may want to handle GET_IRQ better... #define MXC_ICC_INSTANCES (1) /* Secure Mapping Only */ -#define MXC_BASE_ICC ((uint32_t)0x5002A000UL) +#define MXC_BASE_ICC_S ((uint32_t)0x5002A000UL) #define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC_S) /* Added for consistency and explicitness */ From bdd0ff3fb00436d68a9521e4f7b6bdab39a1a668 Mon Sep 17 00:00:00 2001 From: Jake Carter Date: Thu, 2 May 2024 18:14:31 -0600 Subject: [PATCH 59/93] Fix some build errors for non-secure builds --- .../CMSIS/Device/Maxim/MAX32657/Include/max32657.h | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h index b3b9c1b337a..065c785951e 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h @@ -173,26 +173,25 @@ typedef enum { #define MXC_FLASH_S_MEM_BASE 0x11000000UL #define MXC_FLASH_S_PAGE_SIZE 0x00002000UL #define MXC_FLASH_S_MEM_SIZE 0x00100000UL +/* Flash info is always in secure region */ #define MXC_INFO_S_MEM_BASE 0x12000000UL #define MXC_INFO_S_MEM_SIZE 0x00004000UL #define MXC_SRAM_S_MEM_BASE 0x30000000UL #define MXC_SRAM_S_MEM_SIZE 0x00040000UL -/* Secure Region name redefinitions for explicit use */ +#define MXC_INFO_MEM_BASE MXC_INFO_S_MEM_BASE +#define MXC_INFO_MEM_SIZE MXC_INFO_S_MEM_SIZE + #if IS_SECURE_ENVIRONMENT #define MXC_FLASH_MEM_BASE MXC_FLASH_S_MEM_BASE #define MXC_FLASH_PAGE_SIZE MXC_FLASH_S_PAGE_SIZE #define MXC_FLASH_MEM_SIZE MXC_FLASH_S_MEM_SIZE -#define MXC_INFO_MEM_BASE MXC_INFO_S_MEM_BASE -#define MXC_INFO_MEM_SIZE MXC_INFO_S_MEM_SIZE #define MXC_SRAM_MEM_BASE MXC_SRAM_S_MEM_BASE #define MXC_SRAM_MEM_SIZE MXC_SRAM_S_MEM_SIZE #else #define MXC_FLASH_MEM_BASE MXC_FLASH_NS_MEM_BASE #define MXC_FLASH_PAGE_SIZE MXC_FLASH_NS_PAGE_SIZE #define MXC_FLASH_MEM_SIZE MXC_FLASH_NS_MEM_SIZE -#define MXC_INFO_MEM_BASE MXC_INFO_NS_MEM_BASE -#define MXC_INFO_MEM_SIZE MXC_INFO_NS_MEM_SIZE #define MXC_SRAM_MEM_BASE MXC_SRAM_NS_MEM_BASE #define MXC_SRAM_MEM_SIZE MXC_SRAM_NS_MEM_SIZE #endif @@ -253,7 +252,7 @@ typedef enum { #if IS_SECURE_ENVIRONMENT #define MXC_FCR MXC_FCR_S #else -#define MXC_FCR_NS +#define MXC_FCR MXC_FCR_NS #endif /******************************************************************************/ From 4e9156e999a23ed16cbaa7125005362013771573 Mon Sep 17 00:00:00 2001 From: Jake Carter Date: Fri, 3 May 2024 14:25:22 -0600 Subject: [PATCH 60/93] Dynamically switch memory address ranges for secure/non-secure linkage --- Libraries/CMSIS/Device/Maxim/GCC/gcc.mk | 4 +++ .../Maxim/MAX32657/Source/GCC/max32657.ld | 34 +++++++++++-------- 2 files changed, 23 insertions(+), 15 deletions(-) diff --git a/Libraries/CMSIS/Device/Maxim/GCC/gcc.mk b/Libraries/CMSIS/Device/Maxim/GCC/gcc.mk index 48acf971c44..8b434adada0 100644 --- a/Libraries/CMSIS/Device/Maxim/GCC/gcc.mk +++ b/Libraries/CMSIS/Device/Maxim/GCC/gcc.mk @@ -277,6 +277,10 @@ ifeq "$(MSECURITY_MODE)" "SECURE" # defined in "Armv8-M Security Extension: Requirements on Developments Tools" # https://developer.arm.com/documentation/ecm0359818/latest PROJ_CFLAGS += -mcmse + +# Tell the linker we are building a secure project. This defines the "SECURE_LINK" symbol which the +# linker uses to set the secure FLASH/SRAM memory address ranges. +PROJ_LDFLAGS += -Xlinker --defsym=SECURE_LINK=1 endif endif diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.ld b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.ld index 72aae01c65d..6455e14f967 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.ld +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.ld @@ -18,12 +18,16 @@ MEMORY { ROM_S (rx) : ORIGIN = 0x00000000, LENGTH = 0x00010000 /* 64kB secure ROM (ROM always secure) */ - FLASH_NS (rx) : ORIGIN = 0x01000000, LENGTH = 0x00100000 /* 1MB non-secure Flash */ - SRAM_NS (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000 /* 256KB non-secure SRAM */ - FLASH_S (rx) : ORIGIN = 0x11000000, LENGTH = 0x00100000 /* 1MB secure Flash */ + FLASH (rx) : ORIGIN = DEFINED(SECURE_LINK) ? 0x11000000 : 0x01000000, LENGTH = 0x00100000 /* 1MB Flash */ FLASH_INFO_S (rx) : ORIGIN = 0x12000000, LENGTH = 0x00010000 /* 16KB secure Flash Info */ - SRAM_S (rwx) : ORIGIN = 0x30000000, LENGTH = 0x00040000 /* 256KB secure SRAM */ + SRAM (rwx) : ORIGIN = DEFINED(SECURE_LINK) ? 0x30000000 : 0x20000000, LENGTH = 0x00040000 /* 256KB SRAM */ } +/* Note(JC): "SECURE_LINK" is a symbol defined at link-time by Libraries/CMSIS/Device/Maxim/GCC/gcc.mk + * It's only defined for when building secure binaries (which is the default). + * When it's defined, the FLASH and SRAM memory addresses will use the secure ranges. Otherwise, the + * non-secure ranges will be used. This mechanism allows secure and non-secure binaries to be linked + * without having to maintain a separate copy of the linkerfile. + */ SECTIONS { .rom : @@ -59,12 +63,12 @@ SECTIONS { /* C++ Exception handling */ KEEP(*(.eh_frame*)) _etext = .; - } > FLASH_S + } > FLASH .ARM.extab : { *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH_S + } > FLASH /* Binary import */ .bin_storage : @@ -74,7 +78,7 @@ SECTIONS { KEEP(*(.bin_storage_img)) _bin_end_ = .; . = ALIGN(4); - } > FLASH_S + } > FLASH .rom_code : { @@ -90,7 +94,7 @@ SECTIONS { _sran_code = .; *(.flash_code_section) _esran_code = .; - } > FLASH_S + } > FLASH .sram_code : { @@ -98,7 +102,7 @@ SECTIONS { _sran_code = .; *(.sram_code_section) _esran_code = .; - } > SRAM_S + } > SRAM /* it's used for C++ exception handling */ /* we need to keep this to avoid overlapping */ @@ -107,7 +111,7 @@ SECTIONS { __exidx_start = .; *(.ARM.exidx* .gnu.linkonce.armexidx.*) __exidx_end = .; - } > FLASH_S + } > FLASH .data : { @@ -138,7 +142,7 @@ SECTIONS { PROVIDE_HIDDEN (__fini_array_end = .); _edata = ALIGN(., 4); - } > SRAM_S AT>FLASH_S + } > SRAM AT>FLASH __load_data = LOADADDR(.data); .bss : @@ -147,11 +151,11 @@ SECTIONS { _bss = .; *(.bss*) /*read-write zero initialized data: uninitialzed global variable*/ _ebss = ALIGN(., 4); - } > SRAM_S + } > SRAM /* Set stack top to end of RAM, and stack limit move down by * size of stack_dummy section */ - __StackTop = ORIGIN(SRAM_S) + LENGTH(SRAM_S); + __StackTop = ORIGIN(SRAM) + LENGTH(SRAM); __StackLimit = __StackTop - SIZEOF(.stack_dummy); /* .stack_dummy section doesn't contains any symbols. It is only @@ -160,14 +164,14 @@ SECTIONS { .stack_dummy (COPY): { *(.stack*) - } > SRAM_S + } > SRAM .heap (COPY): { . = ALIGN(4); *(.heap*) __HeapLimit = ABSOLUTE(__StackLimit); - } > SRAM_S + } > SRAM PROVIDE(__stack = __StackTop); From 7e7138e22f3773545bf4656c551dc76f94d58c4a Mon Sep 17 00:00:00 2001 From: Woo Date: Fri, 3 May 2024 16:05:45 -0500 Subject: [PATCH 61/93] Add TrustZone support to CMSIS files (secure mode only) --- .../Device/Maxim/MAX32657/Include/max32657.h | 162 ++- .../MAX32657/Include/partition_max32657.h | 1281 +++++++++++++++++ .../Maxim/MAX32657/Source/GCC/max32657.ld | 49 +- .../MAX32657/Source/GCC/startup_max32657.S | 193 ++- .../Maxim/MAX32657/Source/system_max32657.c | 77 +- 5 files changed, 1624 insertions(+), 138 deletions(-) create mode 100644 Libraries/CMSIS/Device/Maxim/MAX32657/Include/partition_max32657.h diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h index 065c785951e..3ca98d730fb 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h @@ -59,7 +59,6 @@ /* ================================================================================ */ // clang-format off -// TODO(ME30): Secure vs non-secure interrupt vectors typedef enum { NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, @@ -97,10 +96,10 @@ typedef enum { DMA0_CH1_IRQn, /* 0x21 0x0084 33: DMA0 Channel 1 */ DMA0_CH2_IRQn, /* 0x22 0x0088 34: DMA0 Channel 2 */ DMA0_CH3_IRQn, /* 0x23 0x008C 35: DMA0 Channel 3 */ - DMA1_CH0_IRQn, /* 0x24 0x0090 36: DMA1 Channel 0 */ - DMA1_CH1_IRQn, /* 0x25 0x0094 37: DMA1 Channel 1 */ - DMA1_CH2_IRQn, /* 0x26 0x0098 38: DMA1 CHannel 2 */ - DMA1_CH3_IRQn, /* 0x27 0x009C 39: DMA1 Channel 3 */ + DMA1_CH0_IRQn, /* 0x24 0x0090 36: DMA1 Channel 0 (Secure) */ + DMA1_CH1_IRQn, /* 0x25 0x0094 37: DMA1 Channel 1 (Secure) */ + DMA1_CH2_IRQn, /* 0x26 0x0098 38: DMA1 CHannel 2 (Secure) */ + DMA1_CH3_IRQn, /* 0x27 0x009C 39: DMA1 Channel 3 (Secure) */ WUT0_IRQn, /* 0x28 0x00A0 40: Wakeup Timer 0 */ WUT1_IRQn, /* 0x29 0x00A4 41: Wakeup TImer 1 */ GPIOWAKE_IRQn, /* 0x2A 0x00A8 42: GPIO Wakeup */ @@ -233,8 +232,10 @@ typedef enum { #define MXC_SIR_S ((mxc_sir_regs_t *)MXC_BASE_SIR_S) #if IS_SECURE_ENVIRONMENT +#define MXC_BASE_SIR MXC_BASE_SIR_S #define MXC_SIR MXC_SIR_S #else +#define MXC_BASE_SIR MXC_BASE_SIR_NS #define MXC_SIR MXC_SIR_NS #endif @@ -250,8 +251,10 @@ typedef enum { #define MXC_FCR_S ((mxc_fcr_regs_t *)MXC_BASE_FCR_S) #if IS_SECURE_ENVIRONMENT +#define MXC_BASE_FCR MXC_BASE_FCR_S #define MXC_FCR MXC_FCR_S #else +#define MXC_BASE_FCR MXC_BASE_FCR_NS #define MXC_FCR MXC_FCR_NS #endif @@ -268,8 +271,10 @@ typedef enum { #define MXC_WDT_S ((mxc_wdt_regs_t *)MXC_BASE_WDT_S) #if IS_SECURE_ENVIRONMENT +#define MXC_BASE_WDT MXC_BASE_WDT_S #define MXC_WDT MXC_WDT_S #else +#define MXC_BASE_WDT MXC_BASE_WDT_NS #define MXC_WDT MXC_WDT_NS #endif @@ -278,15 +283,17 @@ typedef enum { /* Non-secure Mapping */ #define MXC_BASE_SVM_NS ((uint32_t)0x40004800UL) -#define MXC_SVM_NS //TODO(ME30): Add SVM controller registers. +#define MXC_SVM_NS 0 //TODO(ME30): Add SVM controller registers. /* Secure Mapping */ #define MXC_BASE_SVM_S ((uint32_t)0x50004800UL) -#define MXC_SVM_S //TODO(ME30): Add SVM controller registers. +#define MXC_SVM_S 0 //TODO(ME30): Add SVM controller registers. #if IS_SECURE_ENVIRONMENT +#define MXC_BASE_SVM MXC_BASE_SVM_S #define MXC_SVM MXC_SVM_S //TODO(ME30): Add SVM controller registers #else +#define MXC_BASE_SVM MXC_BASE_SVM_NS #define MXC_SVM MXC_SVM_NS #endif @@ -295,15 +302,17 @@ typedef enum { /* Non-secure Mapping */ #define MXC_BASE_BOOST_NS ((uint32_t)0x40004C00UL) -#define MXC_BOOST_NS //TODO(ME30): Add Boost controller registers. +#define MXC_BOOST_NS 0 //TODO(ME30): Add Boost controller registers. /* Secure Mapping */ #define MXC_BASE_BOOST_S ((uint32_t)0x50004C00UL) -#define MXC_BOOST_S //TODO(ME30): Add Boost controller registers. +#define MXC_BOOST_S 0 //TODO(ME30): Add Boost controller registers. #if IS_SECURE_ENVIRONMENT +#define MXC_BASE_BOOST MXC_BASE_BOOST_S #define MXC_BOOST MXC_BOOST_S #else +#define MXC_BASE_BOOST MXC_BASE_BOOST_NS #define MXC_BOOST MXC_BOOST_NS #endif @@ -319,8 +328,10 @@ typedef enum { #define MXC_TRIMSIR_S ((mxc_trimsir_regs_t *)MXC_BASE_TRIMSIR_S) #if IS_SECURE_ENVIRONMENT +#define MXC_BASE_TRIMSIR MXC_BASE_TRIMSIR_S #define MXC_TRIMSIR MXC_TRIMSIR_S #else +#define MXC_BASE_TRIMSIR MXC_BASE_TRIMSIR_NS #define MXC_TRIMSIR MXC_TRIMSIR_NS #endif @@ -336,8 +347,10 @@ typedef enum { #define MXC_RTC_S ((mxc_rtc_regs_t *)MXC_BASE_RTC_S) #if IS_SECURE_ENVIRONMENT +#define MXC_BASE_RTC MXC_BASE_RTC_S #define MXC_RTC MXC_RTC_S #else +#define MXC_BASE_RTC MXC_BASE_RTC_NS #define MXC_RTC MXC_RTC_NS #endif @@ -358,10 +371,14 @@ typedef enum { #define MXC_WUT1_S ((mxc_wut_regs_t *)MXC_BASE_WUT1_S) #if IS_SECURE_ENVIRONMENT +#define MXC_BASE_WUT0 MXC_BASE_WUT0_S #define MXC_WUT0 MXC_WUT0_S +#define MXC_BASE_WUT1 MXC_BASE_WUT1_S #define MXC_WUT1 MXC_WUT1_S #else +#define MXC_BASE_WUT0 MXC_BASE_WUT0_NS #define MXC_WUT0 MXC_WUT0_NS +#define MXC_BASE_WUT1 MXC_BASE_WUT1_NS #define MXC_WUT1 MXC_WUT1_NS #endif @@ -377,8 +394,10 @@ typedef enum { #define MXC_PWRSEQ_S ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ_S) #if IS_SECURE_ENVIRONMENT +#define MXC_BASE_PWRSEQ MXC_BASE_PWRSEQ_S #define MXC_PWRSEQ MXC_PWRSEQ_S #else +#define MXC_BASE_PWRSEQ MXC_BASE_PWRSEQ_NS #define MXC_PWRSEQ MXC_PWRSEQ_NS #endif @@ -394,9 +413,11 @@ typedef enum { #define MXC_MCR_S ((mxc_mcr_regs_t *)MXC_BASE_MCR_S) #if IS_SECURE_ENVIRONMENT +#define MXC_BASE_MCR MXC_BASE_MCR_S #define MXC_MCR MXC_MCR_S #else -#define MXC_MCR MXC_MCR_S +#define MXC_BASE_MCR MXC_BASE_MCR_NS +#define MXC_MCR MXC_MCR_NS #endif /******************************************************************************/ @@ -411,8 +432,10 @@ typedef enum { #define MXC_AES_S ((mxc_aes_regs_t *)MXC_BASE_AES_NS) #if IS_SECURE_ENVIRONMENT +#define MXC_BASE_AES MXC_BASE_AES_S #define MXC_AES MXC_AES_S #else +#define MXC_BASE_AES MXC_BASE_AES_NS #define MXC_AES MXC_AES_NS #endif @@ -428,8 +451,10 @@ typedef enum { #define MXC_AESKEYS_S ((mxc_aeskeys_regs_t *)MXC_BASE_AESKEYS_S) #if IS_SECURE_ENVIRONMENT +#define MXC_BASE_AESKEYS MXC_BASE_AESKEYS_S #define MXC_AESKEYS MXC_AESKEYS_S #else +#define MXC_BASE_AESKEYS MXC_BASE_AESKEYS_NS #define MXC_AESKEYS MXC_AESKEYS_NS #endif @@ -452,8 +477,10 @@ typedef enum { #define MXC_BASE_GPIO0 MXC_BASE_GPIO0_S #if IS_SECURE_ENVIRONMENT +#define MXC_BASE_GPIO0 MXC_BASE_GPIO0_S #define MXC_GPIO0 MXC_GPIO0_S #else +#define MXC_BASE_GPIO0 MXC_BASE_GPIO0_NS #define MXC_GPIO0 MXC_GPIO0_NS #endif @@ -480,8 +507,10 @@ We may want to handle GET_IRQ better... #define MXC_CRC_S ((mxc_crc_regs_t *)MXC_BASE_CRC_S) #if IS_SECURE_ENVIRONMENT +#define MXC_BASE_CRC MXC_BASE_CRC_S #define MXC_CRC MXC_CRC_S #else +#define MXC_BASE_CRC MXC_BASE_CRC_NS #define MXC_CRC MXC_CRC_NS #endif @@ -507,24 +536,6 @@ We may want to handle GET_IRQ better... #define MXC_BASE_TMR5_NS ((uint32_t)0x40081000UL) #define MXC_TMR5_NS ((mxc_tmr_regs_t *)MXC_BASE_TMR5_NS) -#define MXC_TMR_NS_GET_BASE(i) \ - ((i) == 0 ? MXC_BASE_TMR0_NS : \ - (i) == 1 ? MXC_BASE_TMR1_NS : \ - (i) == 2 ? MXC_BASE_TMR2_NS : \ - (i) == 3 ? MXC_BASE_TMR3_NS : \ - (i) == 4 ? MXC_BASE_TMR4_NS : \ - (i) == 5 ? MXC_BASE_TMR5_NS : \ - 0) - -#define MXC_TMR_NS_GET_TMR(i) \ - ((i) == 0 ? MXC_TMR0_NS : \ - (i) == 1 ? MXC_TMR1_NS : \ - (i) == 2 ? MXC_TMR2_NS : \ - (i) == 3 ? MXC_TMR3_NS : \ - (i) == 4 ? MXC_TMR4_NS : \ - (i) == 5 ? MXC_TMR5_NS : \ - 0) - /* Secure Mapping */ #define MXC_BASE_TMR0_S ((uint32_t)0x50010000UL) #define MXC_TMR0_S ((mxc_tmr_regs_t *)MXC_BASE_TMR0_S) @@ -555,7 +566,16 @@ We may want to handle GET_IRQ better... #define MXC_TMR5 MXC_TMR5_NS #endif -#define MXC_TMR_S_GET_TMR(i) \ +#define MXC_TMR_GET_BASE(i) \ + ((i) == 0 ? MXC_BASE_TMR0 : \ + (i) == 1 ? MXC_BASE_TMR1 : \ + (i) == 2 ? MXC_BASE_TMR2 : \ + (i) == 3 ? MXC_BASE_TMR3 : \ + (i) == 4 ? MXC_BASE_TMR4 : \ + (i) == 5 ? MXC_BASE_TMR5 : \ + 0) + +#define MXC_TMR_GET_TMR(i) \ ((i) == 0 ? MXC_TMR0 : \ (i) == 1 ? MXC_TMR1 : \ (i) == 2 ? MXC_TMR2 : \ @@ -574,19 +594,13 @@ We may want to handle GET_IRQ better... 0) #define MXC_TMR_GET_IDX(p) \ - ((p) == MXC_TMR0_NS ? 0 : \ - (p) == MXC_TMR1_NS ? 1 : \ - (p) == MXC_TMR2_NS ? 2 : \ - (p) == MXC_TMR3_NS ? 3 : \ - (p) == MXC_TMR4_NS ? 4 : \ - (p) == MXC_TMR5_NS ? 5 : \ - (p) == MXC_TMR0_S ? 0 : \ - (p) == MXC_TMR1_S ? 1 : \ - (p) == MXC_TMR2_S ? 2 : \ - (p) == MXC_TMR3_S ? 3 : \ - (p) == MXC_TMR4_S ? 4 : \ - (p) == MXC_TMR5_S ? 5 : \ - -1) + ((p) == MXC_TMR0 ? 0 : \ + (p) == MXC_TMR1 ? 1 : \ + (p) == MXC_TMR2 ? 2 : \ + (p) == MXC_TMR3 ? 3 : \ + (p) == MXC_TMR4 ? 4 : \ + (p) == MXC_TMR5 ? 5 : \ + -1) /******************************************************************************/ /* I3C */ @@ -601,52 +615,70 @@ We may want to handle GET_IRQ better... #define MXC_I3C_S ((mxc_i2c_regs_t *)MXC_BASE_I3C_S) #if IS_SECURE_ENVIRONMENT +#define MXC_BASE_I3C MXC_BASE_I3C_S #define MXC_I3C MXC_I3C_S #else +#define MXC_BASE_I3C MXC_BASE_I3C_NS #define MXC_I3C MXC_I3C_NS #endif /******************************************************************************/ /* DMA */ #define MXC_DMA_CHANNELS (4) -#define MXC_DMA_INSTANCES (1) -// ^ Note: We have 2 DMA instances in hardware, but they are secure vs non-secure -// instances. Therefore we treat the part as if there is only 1. +#define MXC_DMA_INSTANCES (2) /* Non-secure Mapping */ #define MXC_BASE_DMA0_NS ((uint32_t)0x40028000UL) #define MXC_DMA0_NS ((mxc_dma_regs_t *)MXC_BASE_DMA0_NS) -/* DMA0 instance only for secure mode. */ /* Secure Mapping */ // TODO(ME30): Is there actuall a secure mapping for DMA0? +// -Yes, DMA0 can be accessed from secure mode. Realizing this, I think +// we would still have to define two DMA instances. +// DMA0 can only access the non-secure mappings of the peripherals, +// but DMA0 can be accessed in both Non-secure and Secure code. +// DMA1 can access both secure and non-secure addresses of the peripherals, +// but DMA1 can Only be accessed in Secure code. #define MXC_BASE_DMA0_S ((uint32_t)0x50028000UL) #define MXC_DMA0_S ((mxc_dma_regs_t *)MXC_BASE_DMA0_S) #define MXC_BASE_DMA1_S ((uint32_t)0x50035000UL) #define MXC_DMA1_S ((mxc_dma_regs_t *)MXC_BASE_DMA1_S) +#if IS_SECURE_ENVIRONMENT #define MXC_BASE_DMA0 MXC_BASE_DMA0_S -#define MXC_DMA0 MXC_DMA0_NS +#define MXC_DMA0 MXC_DMA0_S #define MXC_BASE_DMA1 MXC_BASE_DMA1_S #define MXC_DMA1 MXC_DMA1_S -#if IS_SECURE_ENVIRONMENT -#define MXC_DMA MXC_DMA1_S -#define MXC_DMA_CH_GET_IRQ(i) \ +#define MXC_DMA1_CH_GET_IRQ(i) \ ((IRQn_Type)(((i) == 0) ? DMA1_CH0_IRQn : \ ((i) == 1) ? DMA1_CH1_IRQn : \ ((i) == 2) ? DMA1_CH2_IRQn : \ ((i) == 3) ? DMA1_CH3_IRQn : \ 0)) + #else -#define MXC_DMA MXC_DMA0_NS -#define MXC_DMA_CH_GET_IRQ(i) \ +#define MXC_BASE_DMA0 MXC_BASE_DMA0_NS +#define MXC_DMA0 MXC_DMA0_NS +// TODO(DMA1): Not entirely show how to handle access to MXC_DMA1 in non-secure mode. +// A secure fault should be generated when non-secure code accesses +// a secure peripheral mapping, so it'd be best if a build time warning +// or error was thrown when using MXCX_DMA1. +#define MXC_BASE_DMA1 0 +#define MXC_DMA1 0 + +/* DMA1 IRQs not usable in Non-Secure state. */ +#define MXC_DMA1_CH_GET_IRQ(i) ((IRQn_Type)(0)) +#endif // IS_SECURE_ENVIRONMENT + +#define MXC_DMA_GET_BASE(i) ((i) == MXC_BASE_DMA0 ? 0 : (p) == MXC_BASE_DMA1 ? 1 : -1) + +#define MXC_DMA0_CH_GET_IRQ(i) \ ((IRQn_Type)(((i) == 0) ? DMA0_CH0_IRQn : \ ((i) == 1) ? DMA0_CH1_IRQn : \ ((i) == 2) ? DMA0_CH2_IRQn : \ ((i) == 3) ? DMA0_CH3_IRQn : \ 0)) -#endif #define MXC_DMA_GET_IDX(p) ((p) == MXC_DMA0 ? 0 : (p) == MXC_DMA1 ? 1 : -1) @@ -662,19 +694,22 @@ We may want to handle GET_IRQ better... #define MXC_BASE_FLC_S MXC_BASE_FLC #define MXC_FLC_S MXC_FLC -// Note(JC): There is only one flash instance, but some bottom-level RevX implementations -// depend on MXC_FLC_GET_FLC -#define MXC_FLC_GET_FLC(i) MXC_FLC +/** + * There is only one flash instance, but some bottom-level RevX implementations + * depend on MXC_FLC_GET_FLC + */ +#define MXC_FLC_GET_FLC(i) ((i) == 0 ? MXC_FLC : 0) /******************************************************************************/ /* Internal Cache Controller */ #define MXC_ICC_INSTANCES (1) /* Secure Mapping Only */ -#define MXC_BASE_ICC_S ((uint32_t)0x5002A000UL) +#define MXC_BASE_ICC ((uint32_t)0x5002A000UL) #define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC_S) /* Added for consistency and explicitness */ +#define MXC_BASE_ICC_S MXC_BASE_ICC #define MXC_ICC_S MXC_ICC /******************************************************************************/ @@ -691,11 +726,14 @@ We may want to handle GET_IRQ better... #define MXC_UART_S ((mxc_uart_regs_t *)MXC_BASE_UART_S) #if IS_SECURE_ENVIRONMENT +#define MXC_BASE_UART MXC_BASE_UART_S #define MXC_UART MXC_UART_S #else +#define MXC_BASE_UART MXC_BASE_UART_NS #define MXC_UART MXC_UART_NS #endif +#define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART : 0) #define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART : 0) #define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : 0) #define MXC_UART_GET_IDX(p) ((p) == MXC_UART_NS ? 0 : (p) == MXC_UART_S ? 0 : -1) @@ -710,19 +748,19 @@ We may want to handle GET_IRQ better... #define MXC_BASE_SPI_NS ((uint32_t)0x40046000UL) #define MXC_SPI_NS ((mxc_spi_regs_t *)MXC_BASE_SPI_NS) -#define MXC_SPI_NS_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI_NS : 0) -#define MXC_SPI_NS_GET_SPI(i) ((i) == 0 ? MXC_SPI_NS : 0) - /* Secure Mapping */ #define MXC_BASE_SPI_S ((uint32_t)0x50046000UL) #define MXC_SPI_S ((mxc_spi_regs_t *)MXC_BASE_SPI_S) #if IS_SECURE_ENVIRONMENT +#define MXC_BASE_SPI MXC_BASE_SPI_S #define MXC_SPI MXC_SPI_S #else +#define MXC_BASE_SPI MXC_BASE_SPI_S #define MXC_SPI MXC_SPI_NS #endif +#define MXC_SPI_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI : 0) #define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI : 0) #define MXC_SPI_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SPI_IRQn : 0) #define MXC_SPI_GET_IDX(p) ((p) == MXC_SPI_NS ? 0 : (p) == MXC_SPI_S ? 0 : -1) @@ -739,8 +777,10 @@ We may want to handle GET_IRQ better... #define MXC_TRNG_S ((mxc_trng_regs_t *)MXC_BASE_TRNG_S) #if IS_SECURE_ENVIRONMENT +#define MXC_BASE_TRNG MXC_BASE_TRNG_S #define MXC_TRNG MXC_TRNG_S #else +#define MXC_BASE_TRNG MXC_BASE_TRNG_NS #define MXC_TRNG MXC_TRNG_NS #endif @@ -758,8 +798,10 @@ We may want to handle GET_IRQ better... #if IS_SECURE_ENVIRONMENT // TODO(ME30): Does this have registers? +#define MXC_BASE_BTLE MXC_BASE_BTLE_S #define MXC_BTLE MXC_BTLE_S #else +#define MXC_BASE_BTLE MXC_BASE_BTLE_NS #define MXC_BTLE MXC_BTLE_NS #endif diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/partition_max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/partition_max32657.h new file mode 100644 index 00000000000..14b28a9312e --- /dev/null +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/partition_max32657.h @@ -0,0 +1,1281 @@ +/*************************************************************************//** + * @file partition_max32657.h + * @brief CMSIS-Core(M) Device Initial Setup for Secure/Non-Secure Zones for + * MAX32657 + * @version V1.0.0 + * @date 20. January 2021 + *****************************************************************************/ +/* + * Copyright (c) 2009-2021 Arm Limited. All rights reserved. + * + * Portions Copyright (C) 2024 Analog Devices, Inc. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_SOURCE_GCC_PARTITION_MAX32657_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_SOURCE_GCC_PARTITION_MAX32657_H_ + +#include "max32657.h" + +/* +//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- +*/ + +/* +// Enable SAU +// Value for SAU->CTRL register bit ENABLE +*/ +#define SAU_INIT_CTRL_ENABLE 1 + +/* +// When SAU is disabled +// <0=> All Memory is Secure +// <1=> All Memory is Non-Secure +// Value for SAU->CTRL register bit ALLNS +// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. +*/ +#define SAU_INIT_CTRL_ALLNS 0 + +/* +// +*/ + +/* +// Initialize Security Attribution Unit (SAU) Address Regions +// SAU configuration specifies regions to be one of: +// - Secure and Non-Secure Callable +// - Non-Secure +// Note: All memory regions not configured by SAU are Secure +*/ +/** + * Analog Devices, Inc. + * 4 Regions in the MAX32657. + * 1. Non-Secure Flash + * 2. Secure Flash + * 3. Non-Secure SRAM + * 4. Secure SRAM + * + * Finer grain control can be achieved depending on the application + * requirements by updating the regions of this file. + * + * Non-Secure Flash (1MB) 0x0100.0000 - 0x010F.FFFF + * Non-Secure SRAM0 (32kB) 0x2000.0000 - 0x2000.7FFF + * Non-Secure SRAM1 (32kB) 0x2000.8000 - 0x2000.FFFF + * Non-Secure SRAM2 (64kB) 0x2001.0000 - 0x2001.FFFF + * Non-Secure SRAM3 (64kB) 0x2002.0000 - 0x2002.FFFF + * Non-Secure SRAM4 (64kB) 0x2003.0000 - 0x2003.FFFF + * + * Secure Flash (1MB) 0x1100.0000 - 0x110F.FFFF + * Secure SRAM0 (32kB) 0x3000.0000 - 0x3000.7FFF + * Secure SRAM1 (32kB) 0x3000.8000 - 0x3000.FFFF + * Secure SRAM2 (64kB) 0x3001.0000 - 0x3001.FFFF + * Secure SRAM3 (64kB) 0x3002.0000 - 0x3002.FFFF + * Secure SRAM4 (64kB) 0x3003.0000 - 0x3003.FFFF + */ +#define SAU_REGIONS_MAX 4 /* Max. number of SAU regions */ + +/* +// Initialize SAU Region 0 (Secure Flash) +// Setup SAU Region 0 memory attributes +*/ +#define SAU_INIT_REGION0 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START0 0x11000000 /* start address of SAU region 0 (ROM) */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END0 0x110FFFFF /* end address of SAU region 0 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC0 1 +/* +// +*/ + +/* +// Initialize SAU Region 1 (Non-Secure Flash) +// Setup SAU Region 1 memory attributes +*/ +#define SAU_INIT_REGION1 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START1 0x01000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END1 0x010FFFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC1 0 +/* +// +*/ + +/* +// Initialize SAU Region 2 (Secure SRAM) +// Setup SAU Region 2 memory attributes +*/ +#define SAU_INIT_REGION2 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START2 0x30000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END2 0x3003FFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC2 1 +/* +// +*/ + +/* +// Initialize SAU Region 3 (Non-Secure SRAM) +// Setup SAU Region 3 memory attributes +*/ +#define SAU_INIT_REGION3 1 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START3 0x20000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END3 0x2003FFFF + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC3 0 +/* +// +*/ + +/* +// Initialize SAU Region 4 +// Setup SAU Region 4 memory attributes +*/ +#define SAU_INIT_REGION4 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC4 0 +/* +// +*/ + +/* +// Initialize SAU Region 5 +// Setup SAU Region 5 memory attributes +*/ +#define SAU_INIT_REGION5 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START5 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END5 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC5 0 +/* +// +*/ + +/* +// Initialize SAU Region 6 +// Setup SAU Region 6 memory attributes +*/ +#define SAU_INIT_REGION6 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START6 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END6 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC6 0 +/* +// +*/ + +/* +// Initialize SAU Region 7 +// Setup SAU Region 7 memory attributes +*/ +#define SAU_INIT_REGION7 0 + +/* +// Start Address <0-0xFFFFFFE0> +*/ +#define SAU_INIT_START7 0x00000000 + +/* +// End Address <0x1F-0xFFFFFFFF> +*/ +#define SAU_INIT_END7 0x00000000 + +/* +// Region is +// <0=>Non-Secure +// <1=>Secure, Non-Secure Callable +*/ +#define SAU_INIT_NSC7 0 +/* +// +*/ + +/* +// +*/ + +/* +// Setup behaviour of Sleep and Exception Handling +*/ +#define SCB_CSR_AIRCR_INIT 1 + +/* +// Deep Sleep can be enabled by +// <0=>Secure and Non-Secure state +// <1=>Secure state only +// Value for SCB->CSR register bit DEEPSLEEPS +*/ +#define SCB_CSR_DEEPSLEEPS_VAL 1 + +/* +// System reset request accessible from +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for SCB->AIRCR register bit SYSRESETREQS +*/ +#define SCB_AIRCR_SYSRESETREQS_VAL 1 + +/* +// Priority of Non-Secure exceptions is +// <0=> Not altered +// <1=> Lowered to 0x80-0xFF +// Value for SCB->AIRCR register bit PRIS +*/ +#define SCB_AIRCR_PRIS_VAL 1 + +/* +// BusFault, HardFault, and NMI target +// <0=> Secure state +// <1=> Non-Secure state +// Value for SCB->AIRCR register bit BFHFNMINS +*/ +#define SCB_AIRCR_BFHFNMINS_VAL 0 + +/* +// +*/ + +/* +// Setup behaviour of Floating Point and Vector Unit (FPU/MVE) +*/ +#define TZ_FPU_NS_USAGE 1 + +/* +// Floating Point and Vector Unit usage +// <0=> Secure state only +// <3=> Secure and Non-Secure state +// Value for SCB->NSACR register bits CP10, CP11 +*/ +#define SCB_NSACR_CP10_11_VAL 3 + +/* +// Treat floating-point registers as Secure +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit TS +*/ +#define FPU_FPCCR_TS_VAL 0 + +/* +// Clear on return (CLRONRET) accessibility +// <0=> Secure and Non-Secure state +// <1=> Secure state only +// Value for FPU->FPCCR register bit CLRONRETS +*/ +#define FPU_FPCCR_CLRONRETS_VAL 0 + +/* +// Clear floating-point caller saved registers on exception return +// <0=> Disabled +// <1=> Enabled +// Value for FPU->FPCCR register bit CLRONRET +*/ +#define FPU_FPCCR_CLRONRET_VAL 1 + +/* +// +*/ + +/* +// Setup Interrupt Target +*/ + +/* +// Initialize ITNS 0 (Interrupts 0..31) +*/ +#define NVIC_INIT_ITNS0 1 + +/* +// Interrupts 0..31 +// ICE Unlock <0=> Secure state <1=> Non-Secure state +// Watchdog Timer <0=> Secure state <1=> Non-Secure state +// Real Time Clock <0=> Secure state <1=> Non-Secure state +// True Random Number Generator <0=> Secure state <1=> Non-Secure state +// Timer 0 <0=> Secure state <1=> Non-Secure state +// Timer 1 <0=> Secure state <1=> Non-Secure state +// Timer 2 <0=> Secure state <1=> Non-Secure state +// Timer 3 <0=> Secure state <1=> Non-Secure state +// Timer 4 <0=> Secure state <1=> Non-Secure state +// Timer 5 <0=> Secure state <1=> Non-Secure state +// I3C <0=> Secure state <1=> Non-Secure state +// UART <0=> Secure state <1=> Non-Secure state +// SPI <0=> Secure state <1=> Non-Secure state +// Flash Controller <0=> Secure state <1=> Non-Secure state +// GPIO0 <0=> Secure state <1=> Non-Secure state +// Reserved (15) <0=> Secure state <1=> Non-Secure state +// DMA0 Channel 0 <0=> Secure state <1=> Non-Secure state +// DMA0 Channel 1 <0=> Secure state <1=> Non-Secure state +// DMA0 Channel 2 <0=> Secure state <1=> Non-Secure state +// DMA0 Channel 3 <0=> Secure state <1=> Non-Secure state +// DMA1 Channel 0 <0=> Secure state <1=> Non-Secure state +// DMA1 Channel 1 <0=> Secure state <1=> Non-Secure state +// DMA1 Channel 2 <0=> Secure state <1=> Non-Secure state +// DMA1 Channel 3 <0=> Secure state <1=> Non-Secure state +// Wakeup Timer 0 <0=> Secure state <1=> Non-Secure state +// Wakeup Timer 1 <0=> Secure state <1=> Non-Secure state +// GPIO Wake <0=> Secure state <1=> Non-Secure state +// CRC <0=> Secure state <1=> Non-Secure state +// AES <0=> Secure state <1=> Non-Secure state +// ERFO Ready <0=> Secure state <1=> Non-Secure state +// Boost Controller <0=> Secure state <1=> Non-Secure state +// ECC <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS0_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 1 (Interrupts 32..63) +*/ +#define NVIC_INIT_ITNS1 1 + +/* +// Interrupts 32..63 +// BTLE XXXX0 <0=> Secure state <1=> Non-Secure state +// BTLE XXXX1 <0=> Secure state <1=> Non-Secure state +// BTLE XXXX2 <0=> Secure state <1=> Non-Secure state +// BTLE XXXX3 <0=> Secure state <1=> Non-Secure state +// BTLE XXXX4 <0=> Secure state <1=> Non-Secure state +// BTLE XXXX5 <0=> Secure state <1=> Non-Secure state +// BTLE XXXX6 <0=> Secure state <1=> Non-Secure state +// BTLE XXXX7 <0=> Secure state <1=> Non-Secure state +// BTLE XXXX8 <0=> Secure state <1=> Non-Secure state +// BTLE XXXX9 <0=> Secure state <1=> Non-Secure state +// BTLE XXXXA <0=> Secure state <1=> Non-Secure state +// BTLE XXXXB <0=> Secure state <1=> Non-Secure state +// BTLE XXXXC <0=> Secure state <1=> Non-Secure state +// BTLE XXXXD <0=> Secure state <1=> Non-Secure state +// BTLE XXXXE <0=> Secure state <1=> Non-Secure state +// Reserved (47) <0=> Secure state <1=> Non-Secure state +// MPC Combined (Secure) <0=> Secure state <1=> Non-Secure state +// PPC Combined (Secure) <0=> Secure state <1=> Non-Secure state +// Reserved (50) <0=> Secure state <1=> Non-Secure state +// Reserved (51) <0=> Secure state <1=> Non-Secure state +// Reserved (52) <0=> Secure state <1=> Non-Secure state +// Reserved (53) <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS1_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 2 (Interrupts 64..95) +*/ +#define NVIC_INIT_ITNS2 0 + +/* +// Interrupts 64..95 +// Interrupt 64 <0=> Secure state <1=> Non-Secure state +// Interrupt 65 <0=> Secure state <1=> Non-Secure state +// Interrupt 66 <0=> Secure state <1=> Non-Secure state +// Interrupt 67 <0=> Secure state <1=> Non-Secure state +// Interrupt 68 <0=> Secure state <1=> Non-Secure state +// Interrupt 69 <0=> Secure state <1=> Non-Secure state +// Interrupt 70 <0=> Secure state <1=> Non-Secure state +// Interrupt 71 <0=> Secure state <1=> Non-Secure state +// Interrupt 72 <0=> Secure state <1=> Non-Secure state +// Interrupt 73 <0=> Secure state <1=> Non-Secure state +// Interrupt 74 <0=> Secure state <1=> Non-Secure state +// Interrupt 75 <0=> Secure state <1=> Non-Secure state +// Interrupt 76 <0=> Secure state <1=> Non-Secure state +// Interrupt 77 <0=> Secure state <1=> Non-Secure state +// Interrupt 78 <0=> Secure state <1=> Non-Secure state +// Interrupt 79 <0=> Secure state <1=> Non-Secure state +// Interrupt 80 <0=> Secure state <1=> Non-Secure state +// Interrupt 81 <0=> Secure state <1=> Non-Secure state +// Interrupt 82 <0=> Secure state <1=> Non-Secure state +// Interrupt 83 <0=> Secure state <1=> Non-Secure state +// Interrupt 84 <0=> Secure state <1=> Non-Secure state +// Interrupt 85 <0=> Secure state <1=> Non-Secure state +// Interrupt 86 <0=> Secure state <1=> Non-Secure state +// Interrupt 87 <0=> Secure state <1=> Non-Secure state +// Interrupt 88 <0=> Secure state <1=> Non-Secure state +// Interrupt 89 <0=> Secure state <1=> Non-Secure state +// Interrupt 90 <0=> Secure state <1=> Non-Secure state +// Interrupt 91 <0=> Secure state <1=> Non-Secure state +// Interrupt 92 <0=> Secure state <1=> Non-Secure state +// Interrupt 93 <0=> Secure state <1=> Non-Secure state +// Interrupt 94 <0=> Secure state <1=> Non-Secure state +// Interrupt 95 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS2_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 3 (Interrupts 96..127) +*/ +#define NVIC_INIT_ITNS3 0 + +/* +// Interrupts 96..127 +// Interrupt 96 <0=> Secure state <1=> Non-Secure state +// Interrupt 97 <0=> Secure state <1=> Non-Secure state +// Interrupt 98 <0=> Secure state <1=> Non-Secure state +// Interrupt 99 <0=> Secure state <1=> Non-Secure state +// Interrupt 100 <0=> Secure state <1=> Non-Secure state +// Interrupt 101 <0=> Secure state <1=> Non-Secure state +// Interrupt 102 <0=> Secure state <1=> Non-Secure state +// Interrupt 103 <0=> Secure state <1=> Non-Secure state +// Interrupt 104 <0=> Secure state <1=> Non-Secure state +// Interrupt 105 <0=> Secure state <1=> Non-Secure state +// Interrupt 106 <0=> Secure state <1=> Non-Secure state +// Interrupt 107 <0=> Secure state <1=> Non-Secure state +// Interrupt 108 <0=> Secure state <1=> Non-Secure state +// Interrupt 109 <0=> Secure state <1=> Non-Secure state +// Interrupt 110 <0=> Secure state <1=> Non-Secure state +// Interrupt 111 <0=> Secure state <1=> Non-Secure state +// Interrupt 112 <0=> Secure state <1=> Non-Secure state +// Interrupt 113 <0=> Secure state <1=> Non-Secure state +// Interrupt 114 <0=> Secure state <1=> Non-Secure state +// Interrupt 115 <0=> Secure state <1=> Non-Secure state +// Interrupt 116 <0=> Secure state <1=> Non-Secure state +// Interrupt 117 <0=> Secure state <1=> Non-Secure state +// Interrupt 118 <0=> Secure state <1=> Non-Secure state +// Interrupt 119 <0=> Secure state <1=> Non-Secure state +// Interrupt 120 <0=> Secure state <1=> Non-Secure state +// Interrupt 121 <0=> Secure state <1=> Non-Secure state +// Interrupt 122 <0=> Secure state <1=> Non-Secure state +// Interrupt 123 <0=> Secure state <1=> Non-Secure state +// Interrupt 124 <0=> Secure state <1=> Non-Secure state +// Interrupt 125 <0=> Secure state <1=> Non-Secure state +// Interrupt 126 <0=> Secure state <1=> Non-Secure state +// Interrupt 127 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS3_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 4 (Interrupts 128..159) +*/ +#define NVIC_INIT_ITNS4 0 + +/* +// Interrupts 128..159 +// Interrupt 128 <0=> Secure state <1=> Non-Secure state +// Interrupt 129 <0=> Secure state <1=> Non-Secure state +// Interrupt 130 <0=> Secure state <1=> Non-Secure state +// Interrupt 131 <0=> Secure state <1=> Non-Secure state +// Interrupt 132 <0=> Secure state <1=> Non-Secure state +// Interrupt 133 <0=> Secure state <1=> Non-Secure state +// Interrupt 134 <0=> Secure state <1=> Non-Secure state +// Interrupt 135 <0=> Secure state <1=> Non-Secure state +// Interrupt 136 <0=> Secure state <1=> Non-Secure state +// Interrupt 137 <0=> Secure state <1=> Non-Secure state +// Interrupt 138 <0=> Secure state <1=> Non-Secure state +// Interrupt 139 <0=> Secure state <1=> Non-Secure state +// Interrupt 140 <0=> Secure state <1=> Non-Secure state +// Interrupt 141 <0=> Secure state <1=> Non-Secure state +// Interrupt 142 <0=> Secure state <1=> Non-Secure state +// Interrupt 143 <0=> Secure state <1=> Non-Secure state +// Interrupt 144 <0=> Secure state <1=> Non-Secure state +// Interrupt 145 <0=> Secure state <1=> Non-Secure state +// Interrupt 146 <0=> Secure state <1=> Non-Secure state +// Interrupt 147 <0=> Secure state <1=> Non-Secure state +// Interrupt 148 <0=> Secure state <1=> Non-Secure state +// Interrupt 149 <0=> Secure state <1=> Non-Secure state +// Interrupt 150 <0=> Secure state <1=> Non-Secure state +// Interrupt 151 <0=> Secure state <1=> Non-Secure state +// Interrupt 152 <0=> Secure state <1=> Non-Secure state +// Interrupt 153 <0=> Secure state <1=> Non-Secure state +// Interrupt 154 <0=> Secure state <1=> Non-Secure state +// Interrupt 155 <0=> Secure state <1=> Non-Secure state +// Interrupt 156 <0=> Secure state <1=> Non-Secure state +// Interrupt 157 <0=> Secure state <1=> Non-Secure state +// Interrupt 158 <0=> Secure state <1=> Non-Secure state +// Interrupt 159 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS4_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 5 (Interrupts 160..191) +*/ +#define NVIC_INIT_ITNS5 0 + +/* +// Interrupts 160..191 +// Interrupt 160 <0=> Secure state <1=> Non-Secure state +// Interrupt 161 <0=> Secure state <1=> Non-Secure state +// Interrupt 162 <0=> Secure state <1=> Non-Secure state +// Interrupt 163 <0=> Secure state <1=> Non-Secure state +// Interrupt 164 <0=> Secure state <1=> Non-Secure state +// Interrupt 165 <0=> Secure state <1=> Non-Secure state +// Interrupt 166 <0=> Secure state <1=> Non-Secure state +// Interrupt 167 <0=> Secure state <1=> Non-Secure state +// Interrupt 168 <0=> Secure state <1=> Non-Secure state +// Interrupt 169 <0=> Secure state <1=> Non-Secure state +// Interrupt 170 <0=> Secure state <1=> Non-Secure state +// Interrupt 171 <0=> Secure state <1=> Non-Secure state +// Interrupt 172 <0=> Secure state <1=> Non-Secure state +// Interrupt 173 <0=> Secure state <1=> Non-Secure state +// Interrupt 174 <0=> Secure state <1=> Non-Secure state +// Interrupt 175 <0=> Secure state <1=> Non-Secure state +// Interrupt 176 <0=> Secure state <1=> Non-Secure state +// Interrupt 177 <0=> Secure state <1=> Non-Secure state +// Interrupt 178 <0=> Secure state <1=> Non-Secure state +// Interrupt 179 <0=> Secure state <1=> Non-Secure state +// Interrupt 180 <0=> Secure state <1=> Non-Secure state +// Interrupt 181 <0=> Secure state <1=> Non-Secure state +// Interrupt 182 <0=> Secure state <1=> Non-Secure state +// Interrupt 183 <0=> Secure state <1=> Non-Secure state +// Interrupt 184 <0=> Secure state <1=> Non-Secure state +// Interrupt 185 <0=> Secure state <1=> Non-Secure state +// Interrupt 186 <0=> Secure state <1=> Non-Secure state +// Interrupt 187 <0=> Secure state <1=> Non-Secure state +// Interrupt 188 <0=> Secure state <1=> Non-Secure state +// Interrupt 189 <0=> Secure state <1=> Non-Secure state +// Interrupt 190 <0=> Secure state <1=> Non-Secure state +// Interrupt 191 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS5_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 6 (Interrupts 192..223) +*/ +#define NVIC_INIT_ITNS6 0 + +/* +// Interrupts 192..223 +// Interrupt 192 <0=> Secure state <1=> Non-Secure state +// Interrupt 193 <0=> Secure state <1=> Non-Secure state +// Interrupt 194 <0=> Secure state <1=> Non-Secure state +// Interrupt 195 <0=> Secure state <1=> Non-Secure state +// Interrupt 196 <0=> Secure state <1=> Non-Secure state +// Interrupt 197 <0=> Secure state <1=> Non-Secure state +// Interrupt 198 <0=> Secure state <1=> Non-Secure state +// Interrupt 199 <0=> Secure state <1=> Non-Secure state +// Interrupt 200 <0=> Secure state <1=> Non-Secure state +// Interrupt 201 <0=> Secure state <1=> Non-Secure state +// Interrupt 202 <0=> Secure state <1=> Non-Secure state +// Interrupt 203 <0=> Secure state <1=> Non-Secure state +// Interrupt 204 <0=> Secure state <1=> Non-Secure state +// Interrupt 205 <0=> Secure state <1=> Non-Secure state +// Interrupt 206 <0=> Secure state <1=> Non-Secure state +// Interrupt 207 <0=> Secure state <1=> Non-Secure state +// Interrupt 208 <0=> Secure state <1=> Non-Secure state +// Interrupt 209 <0=> Secure state <1=> Non-Secure state +// Interrupt 210 <0=> Secure state <1=> Non-Secure state +// Interrupt 211 <0=> Secure state <1=> Non-Secure state +// Interrupt 212 <0=> Secure state <1=> Non-Secure state +// Interrupt 213 <0=> Secure state <1=> Non-Secure state +// Interrupt 214 <0=> Secure state <1=> Non-Secure state +// Interrupt 215 <0=> Secure state <1=> Non-Secure state +// Interrupt 216 <0=> Secure state <1=> Non-Secure state +// Interrupt 217 <0=> Secure state <1=> Non-Secure state +// Interrupt 218 <0=> Secure state <1=> Non-Secure state +// Interrupt 219 <0=> Secure state <1=> Non-Secure state +// Interrupt 220 <0=> Secure state <1=> Non-Secure state +// Interrupt 221 <0=> Secure state <1=> Non-Secure state +// Interrupt 222 <0=> Secure state <1=> Non-Secure state +// Interrupt 223 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS6_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 7 (Interrupts 224..255) +*/ +#define NVIC_INIT_ITNS7 0 + +/* +// Interrupts 224..255 +// Interrupt 224 <0=> Secure state <1=> Non-Secure state +// Interrupt 225 <0=> Secure state <1=> Non-Secure state +// Interrupt 226 <0=> Secure state <1=> Non-Secure state +// Interrupt 227 <0=> Secure state <1=> Non-Secure state +// Interrupt 228 <0=> Secure state <1=> Non-Secure state +// Interrupt 229 <0=> Secure state <1=> Non-Secure state +// Interrupt 230 <0=> Secure state <1=> Non-Secure state +// Interrupt 231 <0=> Secure state <1=> Non-Secure state +// Interrupt 232 <0=> Secure state <1=> Non-Secure state +// Interrupt 233 <0=> Secure state <1=> Non-Secure state +// Interrupt 234 <0=> Secure state <1=> Non-Secure state +// Interrupt 235 <0=> Secure state <1=> Non-Secure state +// Interrupt 236 <0=> Secure state <1=> Non-Secure state +// Interrupt 237 <0=> Secure state <1=> Non-Secure state +// Interrupt 238 <0=> Secure state <1=> Non-Secure state +// Interrupt 239 <0=> Secure state <1=> Non-Secure state +// Interrupt 240 <0=> Secure state <1=> Non-Secure state +// Interrupt 241 <0=> Secure state <1=> Non-Secure state +// Interrupt 242 <0=> Secure state <1=> Non-Secure state +// Interrupt 243 <0=> Secure state <1=> Non-Secure state +// Interrupt 244 <0=> Secure state <1=> Non-Secure state +// Interrupt 245 <0=> Secure state <1=> Non-Secure state +// Interrupt 246 <0=> Secure state <1=> Non-Secure state +// Interrupt 247 <0=> Secure state <1=> Non-Secure state +// Interrupt 248 <0=> Secure state <1=> Non-Secure state +// Interrupt 249 <0=> Secure state <1=> Non-Secure state +// Interrupt 250 <0=> Secure state <1=> Non-Secure state +// Interrupt 251 <0=> Secure state <1=> Non-Secure state +// Interrupt 252 <0=> Secure state <1=> Non-Secure state +// Interrupt 253 <0=> Secure state <1=> Non-Secure state +// Interrupt 254 <0=> Secure state <1=> Non-Secure state +// Interrupt 255 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS7_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 8 (Interrupts 256..287) +*/ +#define NVIC_INIT_ITNS8 0 + +/* +// Interrupts 256..287 +// Interrupt 256 <0=> Secure state <1=> Non-Secure state +// Interrupt 257 <0=> Secure state <1=> Non-Secure state +// Interrupt 258 <0=> Secure state <1=> Non-Secure state +// Interrupt 259 <0=> Secure state <1=> Non-Secure state +// Interrupt 260 <0=> Secure state <1=> Non-Secure state +// Interrupt 261 <0=> Secure state <1=> Non-Secure state +// Interrupt 262 <0=> Secure state <1=> Non-Secure state +// Interrupt 263 <0=> Secure state <1=> Non-Secure state +// Interrupt 264 <0=> Secure state <1=> Non-Secure state +// Interrupt 265 <0=> Secure state <1=> Non-Secure state +// Interrupt 266 <0=> Secure state <1=> Non-Secure state +// Interrupt 267 <0=> Secure state <1=> Non-Secure state +// Interrupt 268 <0=> Secure state <1=> Non-Secure state +// Interrupt 269 <0=> Secure state <1=> Non-Secure state +// Interrupt 270 <0=> Secure state <1=> Non-Secure state +// Interrupt 271 <0=> Secure state <1=> Non-Secure state +// Interrupt 272 <0=> Secure state <1=> Non-Secure state +// Interrupt 273 <0=> Secure state <1=> Non-Secure state +// Interrupt 274 <0=> Secure state <1=> Non-Secure state +// Interrupt 275 <0=> Secure state <1=> Non-Secure state +// Interrupt 276 <0=> Secure state <1=> Non-Secure state +// Interrupt 277 <0=> Secure state <1=> Non-Secure state +// Interrupt 278 <0=> Secure state <1=> Non-Secure state +// Interrupt 279 <0=> Secure state <1=> Non-Secure state +// Interrupt 280 <0=> Secure state <1=> Non-Secure state +// Interrupt 281 <0=> Secure state <1=> Non-Secure state +// Interrupt 282 <0=> Secure state <1=> Non-Secure state +// Interrupt 283 <0=> Secure state <1=> Non-Secure state +// Interrupt 284 <0=> Secure state <1=> Non-Secure state +// Interrupt 285 <0=> Secure state <1=> Non-Secure state +// Interrupt 286 <0=> Secure state <1=> Non-Secure state +// Interrupt 287 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS8_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 9 (Interrupts 288..319) +*/ +#define NVIC_INIT_ITNS9 0 + +/* +// Interrupts 288..319 +// Interrupt 288 <0=> Secure state <1=> Non-Secure state +// Interrupt 289 <0=> Secure state <1=> Non-Secure state +// Interrupt 290 <0=> Secure state <1=> Non-Secure state +// Interrupt 291 <0=> Secure state <1=> Non-Secure state +// Interrupt 292 <0=> Secure state <1=> Non-Secure state +// Interrupt 293 <0=> Secure state <1=> Non-Secure state +// Interrupt 294 <0=> Secure state <1=> Non-Secure state +// Interrupt 295 <0=> Secure state <1=> Non-Secure state +// Interrupt 296 <0=> Secure state <1=> Non-Secure state +// Interrupt 297 <0=> Secure state <1=> Non-Secure state +// Interrupt 298 <0=> Secure state <1=> Non-Secure state +// Interrupt 299 <0=> Secure state <1=> Non-Secure state +// Interrupt 300 <0=> Secure state <1=> Non-Secure state +// Interrupt 301 <0=> Secure state <1=> Non-Secure state +// Interrupt 302 <0=> Secure state <1=> Non-Secure state +// Interrupt 303 <0=> Secure state <1=> Non-Secure state +// Interrupt 304 <0=> Secure state <1=> Non-Secure state +// Interrupt 305 <0=> Secure state <1=> Non-Secure state +// Interrupt 306 <0=> Secure state <1=> Non-Secure state +// Interrupt 307 <0=> Secure state <1=> Non-Secure state +// Interrupt 308 <0=> Secure state <1=> Non-Secure state +// Interrupt 309 <0=> Secure state <1=> Non-Secure state +// Interrupt 310 <0=> Secure state <1=> Non-Secure state +// Interrupt 311 <0=> Secure state <1=> Non-Secure state +// Interrupt 312 <0=> Secure state <1=> Non-Secure state +// Interrupt 313 <0=> Secure state <1=> Non-Secure state +// Interrupt 314 <0=> Secure state <1=> Non-Secure state +// Interrupt 315 <0=> Secure state <1=> Non-Secure state +// Interrupt 316 <0=> Secure state <1=> Non-Secure state +// Interrupt 317 <0=> Secure state <1=> Non-Secure state +// Interrupt 318 <0=> Secure state <1=> Non-Secure state +// Interrupt 319 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS9_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 10 (Interrupts 320..351) +*/ +#define NVIC_INIT_ITNS10 0 + +/* +// Interrupts 320..351 +// Interrupt 320 <0=> Secure state <1=> Non-Secure state +// Interrupt 321 <0=> Secure state <1=> Non-Secure state +// Interrupt 322 <0=> Secure state <1=> Non-Secure state +// Interrupt 323 <0=> Secure state <1=> Non-Secure state +// Interrupt 324 <0=> Secure state <1=> Non-Secure state +// Interrupt 325 <0=> Secure state <1=> Non-Secure state +// Interrupt 326 <0=> Secure state <1=> Non-Secure state +// Interrupt 327 <0=> Secure state <1=> Non-Secure state +// Interrupt 328 <0=> Secure state <1=> Non-Secure state +// Interrupt 329 <0=> Secure state <1=> Non-Secure state +// Interrupt 330 <0=> Secure state <1=> Non-Secure state +// Interrupt 331 <0=> Secure state <1=> Non-Secure state +// Interrupt 332 <0=> Secure state <1=> Non-Secure state +// Interrupt 333 <0=> Secure state <1=> Non-Secure state +// Interrupt 334 <0=> Secure state <1=> Non-Secure state +// Interrupt 335 <0=> Secure state <1=> Non-Secure state +// Interrupt 336 <0=> Secure state <1=> Non-Secure state +// Interrupt 337 <0=> Secure state <1=> Non-Secure state +// Interrupt 338 <0=> Secure state <1=> Non-Secure state +// Interrupt 339 <0=> Secure state <1=> Non-Secure state +// Interrupt 340 <0=> Secure state <1=> Non-Secure state +// Interrupt 341 <0=> Secure state <1=> Non-Secure state +// Interrupt 342 <0=> Secure state <1=> Non-Secure state +// Interrupt 343 <0=> Secure state <1=> Non-Secure state +// Interrupt 344 <0=> Secure state <1=> Non-Secure state +// Interrupt 345 <0=> Secure state <1=> Non-Secure state +// Interrupt 346 <0=> Secure state <1=> Non-Secure state +// Interrupt 347 <0=> Secure state <1=> Non-Secure state +// Interrupt 348 <0=> Secure state <1=> Non-Secure state +// Interrupt 349 <0=> Secure state <1=> Non-Secure state +// Interrupt 350 <0=> Secure state <1=> Non-Secure state +// Interrupt 351 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS10_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 11 (Interrupts 352..383) +*/ +#define NVIC_INIT_ITNS11 0 + +/* +// Interrupts 352..383 +// Interrupt 352 <0=> Secure state <1=> Non-Secure state +// Interrupt 353 <0=> Secure state <1=> Non-Secure state +// Interrupt 354 <0=> Secure state <1=> Non-Secure state +// Interrupt 355 <0=> Secure state <1=> Non-Secure state +// Interrupt 356 <0=> Secure state <1=> Non-Secure state +// Interrupt 357 <0=> Secure state <1=> Non-Secure state +// Interrupt 358 <0=> Secure state <1=> Non-Secure state +// Interrupt 359 <0=> Secure state <1=> Non-Secure state +// Interrupt 360 <0=> Secure state <1=> Non-Secure state +// Interrupt 361 <0=> Secure state <1=> Non-Secure state +// Interrupt 362 <0=> Secure state <1=> Non-Secure state +// Interrupt 363 <0=> Secure state <1=> Non-Secure state +// Interrupt 364 <0=> Secure state <1=> Non-Secure state +// Interrupt 365 <0=> Secure state <1=> Non-Secure state +// Interrupt 366 <0=> Secure state <1=> Non-Secure state +// Interrupt 367 <0=> Secure state <1=> Non-Secure state +// Interrupt 368 <0=> Secure state <1=> Non-Secure state +// Interrupt 369 <0=> Secure state <1=> Non-Secure state +// Interrupt 370 <0=> Secure state <1=> Non-Secure state +// Interrupt 371 <0=> Secure state <1=> Non-Secure state +// Interrupt 372 <0=> Secure state <1=> Non-Secure state +// Interrupt 373 <0=> Secure state <1=> Non-Secure state +// Interrupt 374 <0=> Secure state <1=> Non-Secure state +// Interrupt 375 <0=> Secure state <1=> Non-Secure state +// Interrupt 376 <0=> Secure state <1=> Non-Secure state +// Interrupt 377 <0=> Secure state <1=> Non-Secure state +// Interrupt 378 <0=> Secure state <1=> Non-Secure state +// Interrupt 379 <0=> Secure state <1=> Non-Secure state +// Interrupt 380 <0=> Secure state <1=> Non-Secure state +// Interrupt 381 <0=> Secure state <1=> Non-Secure state +// Interrupt 382 <0=> Secure state <1=> Non-Secure state +// Interrupt 383 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS11_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 12 (Interrupts 384..415) +*/ +#define NVIC_INIT_ITNS12 0 + +/* +// Interrupts 384..415 +// Interrupt 384 <0=> Secure state <1=> Non-Secure state +// Interrupt 385 <0=> Secure state <1=> Non-Secure state +// Interrupt 386 <0=> Secure state <1=> Non-Secure state +// Interrupt 387 <0=> Secure state <1=> Non-Secure state +// Interrupt 388 <0=> Secure state <1=> Non-Secure state +// Interrupt 389 <0=> Secure state <1=> Non-Secure state +// Interrupt 390 <0=> Secure state <1=> Non-Secure state +// Interrupt 391 <0=> Secure state <1=> Non-Secure state +// Interrupt 392 <0=> Secure state <1=> Non-Secure state +// Interrupt 393 <0=> Secure state <1=> Non-Secure state +// Interrupt 394 <0=> Secure state <1=> Non-Secure state +// Interrupt 395 <0=> Secure state <1=> Non-Secure state +// Interrupt 396 <0=> Secure state <1=> Non-Secure state +// Interrupt 397 <0=> Secure state <1=> Non-Secure state +// Interrupt 398 <0=> Secure state <1=> Non-Secure state +// Interrupt 399 <0=> Secure state <1=> Non-Secure state +// Interrupt 400 <0=> Secure state <1=> Non-Secure state +// Interrupt 401 <0=> Secure state <1=> Non-Secure state +// Interrupt 402 <0=> Secure state <1=> Non-Secure state +// Interrupt 403 <0=> Secure state <1=> Non-Secure state +// Interrupt 404 <0=> Secure state <1=> Non-Secure state +// Interrupt 405 <0=> Secure state <1=> Non-Secure state +// Interrupt 406 <0=> Secure state <1=> Non-Secure state +// Interrupt 407 <0=> Secure state <1=> Non-Secure state +// Interrupt 408 <0=> Secure state <1=> Non-Secure state +// Interrupt 409 <0=> Secure state <1=> Non-Secure state +// Interrupt 410 <0=> Secure state <1=> Non-Secure state +// Interrupt 411 <0=> Secure state <1=> Non-Secure state +// Interrupt 412 <0=> Secure state <1=> Non-Secure state +// Interrupt 413 <0=> Secure state <1=> Non-Secure state +// Interrupt 414 <0=> Secure state <1=> Non-Secure state +// Interrupt 415 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS12_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 13 (Interrupts 416..447) +*/ +#define NVIC_INIT_ITNS13 0 + +/* +// Interrupts 416..447 +// Interrupt 416 <0=> Secure state <1=> Non-Secure state +// Interrupt 417 <0=> Secure state <1=> Non-Secure state +// Interrupt 418 <0=> Secure state <1=> Non-Secure state +// Interrupt 419 <0=> Secure state <1=> Non-Secure state +// Interrupt 420 <0=> Secure state <1=> Non-Secure state +// Interrupt 421 <0=> Secure state <1=> Non-Secure state +// Interrupt 422 <0=> Secure state <1=> Non-Secure state +// Interrupt 423 <0=> Secure state <1=> Non-Secure state +// Interrupt 424 <0=> Secure state <1=> Non-Secure state +// Interrupt 425 <0=> Secure state <1=> Non-Secure state +// Interrupt 426 <0=> Secure state <1=> Non-Secure state +// Interrupt 427 <0=> Secure state <1=> Non-Secure state +// Interrupt 428 <0=> Secure state <1=> Non-Secure state +// Interrupt 429 <0=> Secure state <1=> Non-Secure state +// Interrupt 430 <0=> Secure state <1=> Non-Secure state +// Interrupt 431 <0=> Secure state <1=> Non-Secure state +// Interrupt 432 <0=> Secure state <1=> Non-Secure state +// Interrupt 433 <0=> Secure state <1=> Non-Secure state +// Interrupt 434 <0=> Secure state <1=> Non-Secure state +// Interrupt 435 <0=> Secure state <1=> Non-Secure state +// Interrupt 436 <0=> Secure state <1=> Non-Secure state +// Interrupt 437 <0=> Secure state <1=> Non-Secure state +// Interrupt 438 <0=> Secure state <1=> Non-Secure state +// Interrupt 439 <0=> Secure state <1=> Non-Secure state +// Interrupt 440 <0=> Secure state <1=> Non-Secure state +// Interrupt 441 <0=> Secure state <1=> Non-Secure state +// Interrupt 442 <0=> Secure state <1=> Non-Secure state +// Interrupt 443 <0=> Secure state <1=> Non-Secure state +// Interrupt 444 <0=> Secure state <1=> Non-Secure state +// Interrupt 445 <0=> Secure state <1=> Non-Secure state +// Interrupt 446 <0=> Secure state <1=> Non-Secure state +// Interrupt 447 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS13_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 14 (Interrupts 448..479) +*/ +#define NVIC_INIT_ITNS14 0 + +/* +// Interrupts 448..479 +// Interrupt 448 <0=> Secure state <1=> Non-Secure state +// Interrupt 449 <0=> Secure state <1=> Non-Secure state +// Interrupt 450 <0=> Secure state <1=> Non-Secure state +// Interrupt 451 <0=> Secure state <1=> Non-Secure state +// Interrupt 452 <0=> Secure state <1=> Non-Secure state +// Interrupt 453 <0=> Secure state <1=> Non-Secure state +// Interrupt 454 <0=> Secure state <1=> Non-Secure state +// Interrupt 455 <0=> Secure state <1=> Non-Secure state +// Interrupt 456 <0=> Secure state <1=> Non-Secure state +// Interrupt 457 <0=> Secure state <1=> Non-Secure state +// Interrupt 458 <0=> Secure state <1=> Non-Secure state +// Interrupt 459 <0=> Secure state <1=> Non-Secure state +// Interrupt 460 <0=> Secure state <1=> Non-Secure state +// Interrupt 461 <0=> Secure state <1=> Non-Secure state +// Interrupt 462 <0=> Secure state <1=> Non-Secure state +// Interrupt 463 <0=> Secure state <1=> Non-Secure state +// Interrupt 464 <0=> Secure state <1=> Non-Secure state +// Interrupt 465 <0=> Secure state <1=> Non-Secure state +// Interrupt 466 <0=> Secure state <1=> Non-Secure state +// Interrupt 467 <0=> Secure state <1=> Non-Secure state +// Interrupt 468 <0=> Secure state <1=> Non-Secure state +// Interrupt 469 <0=> Secure state <1=> Non-Secure state +// Interrupt 470 <0=> Secure state <1=> Non-Secure state +// Interrupt 471 <0=> Secure state <1=> Non-Secure state +// Interrupt 472 <0=> Secure state <1=> Non-Secure state +// Interrupt 473 <0=> Secure state <1=> Non-Secure state +// Interrupt 474 <0=> Secure state <1=> Non-Secure state +// Interrupt 475 <0=> Secure state <1=> Non-Secure state +// Interrupt 476 <0=> Secure state <1=> Non-Secure state +// Interrupt 477 <0=> Secure state <1=> Non-Secure state +// Interrupt 478 <0=> Secure state <1=> Non-Secure state +// Interrupt 479 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS14_VAL 0x00000000 + +/* +// +*/ + +/* +// Initialize ITNS 15 (Interrupts 480..511) +*/ +#define NVIC_INIT_ITNS15 0 + +/* +// Interrupts 480..511 +// Interrupt 480 <0=> Secure state <1=> Non-Secure state +// Interrupt 481 <0=> Secure state <1=> Non-Secure state +// Interrupt 482 <0=> Secure state <1=> Non-Secure state +// Interrupt 483 <0=> Secure state <1=> Non-Secure state +// Interrupt 484 <0=> Secure state <1=> Non-Secure state +// Interrupt 485 <0=> Secure state <1=> Non-Secure state +// Interrupt 486 <0=> Secure state <1=> Non-Secure state +// Interrupt 487 <0=> Secure state <1=> Non-Secure state +// Interrupt 488 <0=> Secure state <1=> Non-Secure state +// Interrupt 489 <0=> Secure state <1=> Non-Secure state +// Interrupt 490 <0=> Secure state <1=> Non-Secure state +// Interrupt 491 <0=> Secure state <1=> Non-Secure state +// Interrupt 492 <0=> Secure state <1=> Non-Secure state +// Interrupt 493 <0=> Secure state <1=> Non-Secure state +// Interrupt 494 <0=> Secure state <1=> Non-Secure state +// Interrupt 495 <0=> Secure state <1=> Non-Secure state +// Interrupt 496 <0=> Secure state <1=> Non-Secure state +// Interrupt 497 <0=> Secure state <1=> Non-Secure state +// Interrupt 498 <0=> Secure state <1=> Non-Secure state +// Interrupt 499 <0=> Secure state <1=> Non-Secure state +// Interrupt 500 <0=> Secure state <1=> Non-Secure state +// Interrupt 501 <0=> Secure state <1=> Non-Secure state +// Interrupt 502 <0=> Secure state <1=> Non-Secure state +// Interrupt 503 <0=> Secure state <1=> Non-Secure state +// Interrupt 504 <0=> Secure state <1=> Non-Secure state +// Interrupt 505 <0=> Secure state <1=> Non-Secure state +// Interrupt 506 <0=> Secure state <1=> Non-Secure state +// Interrupt 507 <0=> Secure state <1=> Non-Secure state +// Interrupt 508 <0=> Secure state <1=> Non-Secure state +// Interrupt 509 <0=> Secure state <1=> Non-Secure state +// Interrupt 510 <0=> Secure state <1=> Non-Secure state +// Interrupt 511 <0=> Secure state <1=> Non-Secure state +*/ +#define NVIC_INIT_ITNS15_VAL 0x00000000 + +/* +// +*/ + +/* +// +*/ + + + +/* + max 128 SAU regions. + SAU regions are defined in partition.h + */ + +#define SAU_INIT_REGION(n) \ + SAU->RNR = (n & SAU_RNR_REGION_Msk); \ + SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ + SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ + ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U + +/** + \brief Setup a SAU Region + \details Writes the region information contained in SAU_Region to the + registers SAU_RNR, SAU_RBAR, and SAU_RLAR + */ +__STATIC_INLINE void TZ_SAU_Setup (void) +{ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + + #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) + SAU_INIT_REGION(0); + #endif + + #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) + SAU_INIT_REGION(1); + #endif + + #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) + SAU_INIT_REGION(2); + #endif + + #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) + SAU_INIT_REGION(3); + #endif + + #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) + SAU_INIT_REGION(4); + #endif + + #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) + SAU_INIT_REGION(5); + #endif + + #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) + SAU_INIT_REGION(6); + #endif + + #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) + SAU_INIT_REGION(7); + #endif + + /* repeat this for all possible SAU regions */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + + + #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) + SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | + ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; + #endif + + #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) + SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | + ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); + + SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | + SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | + ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | + ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | + ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | + ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); + #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ + + #if (((defined (__FPU_USED) && (__FPU_USED == 1U)) || \ + (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \ + (defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U))) + + SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | + ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); + + FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | + ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | + ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | + ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); + #endif + + #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) + NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; + #endif + + #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) + NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; + #endif + + #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) + NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; + #endif + + #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) + NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; + #endif + + #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) + NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; + #endif + + #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) + NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; + #endif + + #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) + NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; + #endif + + #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) + NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; + #endif + + #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) + NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; + #endif + + #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) + NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; + #endif + + #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) + NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; + #endif + + #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) + NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; + #endif + + #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) + NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; + #endif + + #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) + NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; + #endif + + #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) + NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; + #endif + + #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) + NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; + #endif + + /* repeat this for all possible ITNS elements */ + +} + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_SOURCE_PARTITION_MAX32657_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.ld b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.ld index 72aae01c65d..4f79ad5bb70 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.ld +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.ld @@ -36,7 +36,7 @@ SECTIONS { { _text = .; KEEP(*(.isr_vector)) - EXCLUDE_FILE (*riscv.o) *(.text*) /* Program code (exclude RISCV code) */ + *(.text*) /* Program code */ *(.rodata*) /* read-only data: "const" */ KEEP(*(.init)) @@ -61,19 +61,20 @@ SECTIONS { _etext = .; } > FLASH_S - .ARM.extab : + /* + * Secure Gatway (SG) veneers. + * All SG veneers are placed in the special output section .gnu.sgstubs. + */ + .gnu.sgstubs : { - *(.ARM.extab* .gnu.linkonce.armextab.*) + _sg_veneers = .; + KEEP(*(.gnu.sgstubs*)) + _esg_veneers = .; } > FLASH_S - /* Binary import */ - .bin_storage : + .ARM.extab : { - FILL(0xFF) - _bin_start_ = .; - KEEP(*(.bin_storage_img)) - _bin_end_ = .; - . = ALIGN(4); + *(.ARM.extab* .gnu.linkonce.armextab.*) } > FLASH_S .rom_code : @@ -149,17 +150,34 @@ SECTIONS { _ebss = ALIGN(., 4); } > SRAM_S - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ + /** + * Stack Seal section is required for secure builds. Stack sealing protects + * secure stack from illegal access by non-secure code. + */ + .stackseal (COPY): + { + . = ALIGN(8); + __StackSeal = .; + . = . + 8; + . = ALIGN(8); + } > SRAM_S + + /** + * Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section. + */ __StackTop = ORIGIN(SRAM_S) + LENGTH(SRAM_S); __StackLimit = __StackTop - SIZEOF(.stack_dummy); - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ + /** + * .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later. + */ .stack_dummy (COPY): { *(.stack*) + *(.stackseal*) } > SRAM_S .heap (COPY): @@ -173,5 +191,4 @@ SECTIONS { /* Check if data + heap + stack exceeds RAM limit */ ASSERT(__StackLimit >= _ebss, "region RAM overflowed with stack") - } diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/startup_max32657.S b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/startup_max32657.S index 6d472f73a13..2a4348f73c2 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/startup_max32657.S +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/startup_max32657.S @@ -24,26 +24,31 @@ .section .stack .align 3 #ifdef __STACK_SIZE - .equ Stack_Size, __STACK_SIZE + .equ Stack_Size, __STACK_SIZE #else // Default stack size (192KB) - .equ Stack_Size, 0x00030000 + .equ Stack_Size, 0x00030000 #endif .globl __StackTop .globl __StackLimit +#if IS_SECURE_ENVIRONMENT + // __StackSeal defined in linker script + .equ __STACK_SEAL, __StackSeal + .globl __StackSeal +#endif __StackLimit: .space Stack_Size - .size __StackLimit, . - __StackLimit + .size __StackLimit, . - __StackLimit __StackTop: - .size __StackTop, . - __StackTop + .size __StackTop, . - __StackTop .section .heap .align 3 #ifdef __HEAP_SIZE - .equ Heap_Size, __HEAP_SIZE + .equ Heap_Size, __HEAP_SIZE #else // Default heap size (64KB) - .equ Heap_Size, 0x00010000 + .equ Heap_Size, 0x00010000 #endif .globl __HeapBase .globl __HeapLimit @@ -60,26 +65,84 @@ __HeapLimit: .align 9 /* must be aligned to 512 byte boundary. VTOR requirement */ .globl __isr_vector __isr_vector: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long MemManage_Handler /* MPU Fault Handler */ - .long BusFault_Handler /* Bus Fault Handler */ - .long UsageFault_Handler /* Usage Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long DebugMon_Handler /* Debug Monitor Handler */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - // TODO: Add device-specific interrupt table - /* Device-specific Interrupts */ - .long RSVXX_IRQHandler /* 0xXX 0xXXXX XX: Reserved */ + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* Device-specific Interrupts */ + /* CMSIS Interrupt Number */ + /* |||| || */ + /* |||| Offset || */ + /* vvvv vvvvvv vv */ + + .long ICE_IRQHandler /* 0x10 0x0040 16: ICE Unlock */ + .long WDT_IRQHandler /* 0x11 0x0044 17: Watchdog Timer */ + .long RTC_IRQHandler /* 0x12 0x0048 18: RTC */ + .long TRNG_IRQHandler /* 0x13 0x004C 19: True Random Number Generator */ + .long TMR0_IRQHandler /* 0x14 0x0050 20: Timer 0 */ + .long TMR1_IRQHandler /* 0x15 0x0054 21: Timer 1 */ + .long TMR2_IRQHandler /* 0x16 0x0058 22: Timer 2 */ + .long TMR3_IRQHandler /* 0x17 0x005C 23: Timer 3 */ + .long TMR4_IRQHandler /* 0x18 0x0060 24: Timer 4 */ + .long TMR5_IRQHandler /* 0x19 0x0064 25: Timer 5 */ + .long I3C_IRQHandler /* 0x1A 0x0068 26: I3C */ + .long UART_IRQHandler /* 0x1B 0x006C 27: UART */ + .long SPI_IRQHandler /* 0x1C 0x0070 28: SPI */ + .long FLC_IRQHandler /* 0x1D 0x0074 29: FLC */ + .long GPIO0_IRQHandler /* 0x1E 0x0078 30: GPIO0 */ + .long RSV15_IRQHandler /* 0x1F 0x007C 31: Reserved */ + .long DMA0_CH0_IRQHandler /* 0x20 0x0080 32: DMA0 Channel 0 */ + .long DMA0_CH1_IRQHandler /* 0x21 0x0084 33: DMA0 Channel 1 */ + .long DMA0_CH2_IRQHandler /* 0x22 0x0088 34: DMA0 Channel 2 */ + .long DMA0_CH3_IRQHandler /* 0x23 0x008C 35: DMA0 Channel 3 */ + .long DMA1_CH0_IRQHandler /* 0x24 0x0090 36: DMA1 Channel 0 */ + .long DMA1_CH1_IRQHandler /* 0x25 0x0094 37: DMA1 Channel 1 */ + .long DMA1_CH2_IRQHandler /* 0x26 0x0098 38: DMA1 Channel 2 */ + .long DMA1_CH3_IRQHandler /* 0x27 0x009C 39: DMA1 Channel 3 */ + .long WUT0_IRQHandler /* 0x28 0x00A0 40: Wakeup Timer 0 */ + .long WUT1_IRQHandler /* 0x29 0x00A4 41: Wakeup Timer 1 */ + .long GPIOWAKE_IRQHandler /* 0x2A 0x00A8 42: GPIO Wakeup */ + .long CRC_IRQHandler /* 0x2B 0x00AC 43: CRC */ + .long AES_IRQHandler /* 0x2C 0x00B0 44: AES */ + .long ERFO_IRQHandler /* 0x2D 0x00B4 45: ERFO Ready */ + .long BOOST_IRQHandler /* 0x2E 0x00B8 46: Boost Controller */ + .long ECC_IRQHandler /* 0x2F 0x00BC 47: ECC */ +/* TODO(Bluetooth): Confirm BTLE IRQ Handler Names */ + .long BTLE_XXXX0_IRQHandler /* 0x30 0x00C0 48: BTLE XXXX0 */ + .long BTLE_XXXX1_IRQHandler /* 0x31 0x00C4 49: BTLE XXXX1 */ + .long BTLE_XXXX2_IRQHandler /* 0x32 0x00C8 50: BTLE XXXX2 */ + .long BTLE_XXXX3_IRQHandler /* 0x33 0x00CC 51: BTLE XXXX3 */ + .long BTLE_XXXX4_IRQHandler /* 0x34 0x00D0 52: BTLE XXXX4 */ + .long BTLE_XXXX5_IRQHandler /* 0x35 0x00D4 53: BTLE XXXX5 */ + .long BTLE_XXXX6_IRQHandler /* 0x36 0x00D8 54: BTLE XXXX6 */ + .long BTLE_XXXX7_IRQHandler /* 0x37 0x00DC 55: BTLE XXXX7 */ + .long BTLE_XXXX8_IRQHandler /* 0x38 0x00E0 56: BTLE XXXX8 */ + .long BTLE_XXXX9_IRQHandler /* 0x39 0x00E4 57: BTLE XXXX9 */ + .long BTLE_XXXXA_IRQHandler /* 0x3A 0x00E8 58: BTLE XXXXA */ + .long BTLE_XXXXB_IRQHandler /* 0x3B 0x00EC 59: BTLE XXXXB */ + .long BTLE_XXXXC_IRQHandler /* 0x3C 0x00F0 60: BTLE XXXXC */ + .long BTLE_XXXXD_IRQHandler /* 0x3D 0x00F4 61: BTLE XXXXD */ + .long BTLE_XXXXE_IRQHandler /* 0x3E 0x00F8 62: BTLE XXXXE */ + .long RSV47_IRQHandler /* 0x3F 0x00FC 63: Reserved */ + .long MPC_IRQHandler /* 0x40 0x0100 64: MPC Combined (Secure) */ + .long PPC_IRQHandler /* 0x44 0x0104 65: PPC Combined (Secure) */ + .long RSV50_IRQHandler /* 0x48 0x0108 66: Reserved */ + .long RSV51_IRQHandler /* 0x49 0x010C 67: Reserved */ + .long RSV52_IRQHandler /* 0x4A 0x0110 68: Reserved */ + .long RSV53_IRQHandler /* 0x4B 0x0114 69: Reserved */ .text .thumb @@ -91,6 +154,19 @@ Reset_Handler: ldr r0, =__StackTop mov sp, r0 +#if IS_SECURE_ENVIRONMENT + /* Set limit on Main and Process SP */ + ldr r0, =__STACK_LIMIT + msr msplim, r0 + msr psplim, r0 + + /* Set up Stack Sealing - using predefined stack seal value */ + ldr r0, =__STACK_SEAL + ldr r1, =0xFEF5EDA5U + /* Store seal value twice as a double word for redundancy */ + strd r1, r1, [r0, #0] +#endif + /* PreInit runs before any RAM initialization. Example usage: DDR setup, etc. */ ldr r0, =PreInit blx r0 @@ -177,7 +253,6 @@ Reset_Handler: .size \handler_name, . - \handler_name .endm - // TODO: Update to match arch-specific handlers above def_irq_handler NMI_Handler def_irq_handler HardFault_Handler def_irq_handler MemManage_Handler @@ -189,7 +264,65 @@ Reset_Handler: def_irq_handler SysTick_Handler def_irq_handler Default_Handler - // TODO: Add default device-specific handlers to match above - /* Device-specific Interrupts */ - def_irq_handler RSVXX_IRQHandler /* 0xXX 0xXXXX XX: Reserved */ + /* Device-specific Interrupts */ + /* CMSIS Interrupt Number */ + /* |||| || */ + /* |||| Offset || */ + /* vvvv vvvvvv vv */ + + def_irq_handler ICE_IRQHandler /* 0x10 0x0040 16: ICE Unlock */ + def_irq_handler WDT_IRQHandler /* 0x11 0x0044 17: Watchdog Timer */ + def_irq_handler RTC_IRQHandler /* 0x12 0x0048 18: RTC */ + def_irq_handler TRNG_IRQHandler /* 0x13 0x004C 19: True Random Number Generator */ + def_irq_handler TMR0_IRQHandler /* 0x14 0x0050 20: Timer 0 */ + def_irq_handler TMR1_IRQHandler /* 0x15 0x0054 21: Timer 1 */ + def_irq_handler TMR2_IRQHandler /* 0x16 0x0058 22: Timer 2 */ + def_irq_handler TMR3_IRQHandler /* 0x17 0x005C 23: Timer 3 */ + def_irq_handler TMR4_IRQHandler /* 0x18 0x0060 24: Timer 4 */ + def_irq_handler TMR5_IRQHandler /* 0x19 0x0064 25: Timer 5 */ + def_irq_handler I3C_IRQHandler /* 0x1A 0x0068 26: I3C */ + def_irq_handler UART_IRQHandler /* 0x1B 0x006C 27: UART */ + def_irq_handler SPI_IRQHandler /* 0x1C 0x0070 28: SPI */ + def_irq_handler FLC_IRQHandler /* 0x1D 0x0074 29: FLC */ + def_irq_handler GPIO0_IRQHandler /* 0x1E 0x0078 30: GPIO0 */ + def_irq_handler RSV15_IRQHandler /* 0x1F 0x007C 31: Reserved */ + def_irq_handler DMA0_CH0_IRQHandler /* 0x20 0x0080 32: DMA0 Channel 0 */ + def_irq_handler DMA0_CH1_IRQHandler /* 0x21 0x0084 33: DMA0 Channel 1 */ + def_irq_handler DMA0_CH2_IRQHandler /* 0x22 0x0088 34: DMA0 Channel 2 */ + def_irq_handler DMA0_CH3_IRQHandler /* 0x23 0x008C 35: DMA0 Channel 3 */ + def_irq_handler DMA1_CH0_IRQHandler /* 0x24 0x0090 36: DMA1 Channel 0 */ + def_irq_handler DMA1_CH1_IRQHandler /* 0x25 0x0094 37: DMA1 Channel 1 */ + def_irq_handler DMA1_CH2_IRQHandler /* 0x26 0x0098 38: DMA1 Channel 2 */ + def_irq_handler DMA1_CH3_IRQHandler /* 0x27 0x009C 39: DMA1 Channel 3 */ + def_irq_handler WUT0_IRQHandler /* 0x28 0x00A0 40: Wakeup Timer 0 */ + def_irq_handler WUT1_IRQHandler /* 0x29 0x00A4 41: Wakeup Timer 1 */ + def_irq_handler GPIOWAKE_IRQHandler /* 0x2A 0x00A8 42: GPIO Wakeup */ + def_irq_handler CRC_IRQHandler /* 0x2B 0x00AC 43: CRC */ + def_irq_handler AES_IRQHandler /* 0x2C 0x00B0 44: AES */ + def_irq_handler ERFO_IRQHandler /* 0x2D 0x00B4 45: ERFO Ready */ + def_irq_handler BOOST_IRQHandler /* 0x2E 0x00B8 46: Boost Controller */ + def_irq_handler ECC_IRQHandler /* 0x2F 0x00BC 47: ECC */ +/* TODO(Bluetooth): Confirm BTLE IRQ Handler Names */ + def_irq_handler BTLE_XXXX0_IRQHandler /* 0x30 0x00C0 48: BTLE XXXX0 */ + def_irq_handler BTLE_XXXX1_IRQHandler /* 0x31 0x00C4 49: BTLE XXXX1 */ + def_irq_handler BTLE_XXXX2_IRQHandler /* 0x32 0x00C8 50: BTLE XXXX2 */ + def_irq_handler BTLE_XXXX3_IRQHandler /* 0x33 0x00CC 51: BTLE XXXX3 */ + def_irq_handler BTLE_XXXX4_IRQHandler /* 0x34 0x00D0 52: BTLE XXXX4 */ + def_irq_handler BTLE_XXXX5_IRQHandler /* 0x35 0x00D4 53: BTLE XXXX5 */ + def_irq_handler BTLE_XXXX6_IRQHandler /* 0x36 0x00D8 54: BTLE XXXX6 */ + def_irq_handler BTLE_XXXX7_IRQHandler /* 0x37 0x00DC 55: BTLE XXXX7 */ + def_irq_handler BTLE_XXXX8_IRQHandler /* 0x38 0x00E0 56: BTLE XXXX8 */ + def_irq_handler BTLE_XXXX9_IRQHandler /* 0x39 0x00E4 57: BTLE XXXX9 */ + def_irq_handler BTLE_XXXXA_IRQHandler /* 0x3A 0x00E8 58: BTLE XXXXA */ + def_irq_handler BTLE_XXXXB_IRQHandler /* 0x3B 0x00EC 59: BTLE XXXXB */ + def_irq_handler BTLE_XXXXC_IRQHandler /* 0x3C 0x00F0 60: BTLE XXXXC */ + def_irq_handler BTLE_XXXXD_IRQHandler /* 0x3D 0x00F4 61: BTLE XXXXD */ + def_irq_handler BTLE_XXXXE_IRQHandler /* 0x3E 0x00F8 62: BTLE XXXXE */ + def_irq_handler RSV47_IRQHandler /* 0x3F 0x00FC 63: Reserved */ + def_irq_handler MPC_IRQHandler /* 0x40 0x0100 64: MPC Combined (Secure) */ + def_irq_handler PPC_IRQHandler /* 0x44 0x0104 65: PPC Combined (Secure) */ + def_irq_handler RSV50_IRQHandler /* 0x48 0x0108 66: Reserved */ + def_irq_handler RSV51_IRQHandler /* 0x49 0x010C 67: Reserved */ + def_irq_handler RSV52_IRQHandler /* 0x4A 0x0110 68: Reserved */ + def_irq_handler RSV53_IRQHandler /* 0x4B 0x0114 69: Reserved */ .end diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c index 51078ce7a50..652790d2796 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c @@ -16,20 +16,23 @@ * ******************************************************************************/ -// TODO(ME30): System implementation - -#include "system_max32657.h" -#include "max32657.h" +#include +#include +#include #include "mxc_sys.h" -#include "icc.h" +#include "max32657.h" +#include "system_max32657.h" +#include "partition_max32657.h" +#include "gcr_regs.h" extern void (*const __isr_vector[])(void); -uint32_t SystemCoreClock = IPO_FREQ; // Part defaults to IPO on startup + +uint32_t SystemCoreClock = IPO_FREQ; /* -The libc implementation from GCC 11+ depends on _getpid and _kill in some places. -There is no concept of processes/PIDs in the baremetal PeriphDrivers, therefore -we implement stub functions that return an error code to resolve linker warnings. + The libc implementation from GCC 11+ depends on _getpid and _kill in some places. + There is no concept of processes/PIDs in the baremetal PeriphDrivers, therefore + we implement stub functions that return an error code to resolve linker warnings. */ int _getpid(void) { @@ -47,7 +50,7 @@ __weak void SystemCoreClockUpdate(void) // Get the clock source and frequency clk_src = (MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_SEL); - switch (clk_src) { + switch (clk_src) { case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO: base_freq = IPO_FREQ; break; @@ -56,15 +59,12 @@ __weak void SystemCoreClockUpdate(void) break; case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_INRO: base_freq = INRO_FREQ; - break; + break; case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IBRO: base_freq = IBRO_FREQ; break; - case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO: - base_freq = ERTCO_FREQ; - break; - // case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK: - // base_freq = EXTCLK_FREQ; + // case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO: + // base_freq = ERTCO_FREQ; // break; // TODO(JC): ^^^ Uncomment when EXTCLK register definition is added default: @@ -90,8 +90,9 @@ __weak void SystemCoreClockUpdate(void) */ __weak int PreInit(void) { - // TODO(JC): No SIMO on this device, confirm nothing needs to be done here. - + /* Do nothing */ + // TODO(JC): No SIMO on this device, confirm nothing needs to be done here. + // (SW): Correct, different power HW. return 0; } @@ -121,26 +122,38 @@ __weak int Board_Init(void) */ __weak void SystemInit(void) { - /* Configure the interrupt controller to use the application vector table in */ - /* the application space */ -#if defined(__CC_ARM) || defined(__GNUC__) - /* IAR sets the VTOR pointer incorrectly and causes stack corruption */ + +#if defined(__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) SCB->VTOR = (uint32_t)__isr_vector; -#endif /* __CC_ARM || __GNUC__ */ +#endif /* __VTOR_PRESENT check */ - /* Make sure interrupts are enabled. */ - __enable_irq(); +#if (__FPU_PRESENT == 1U) + /* Enable FPU - coprocessor slots 10 & 11 full access */ + SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk; +#endif /* __FPU_PRESENT check */ - /* Enable instruction cache */ - MXC_ICC_Enable(MXC_ICC); + /* + Enable Unaligned Access Trapping to throw an exception when there is an + unaligned memory access while unaligned access support is disabled. + + Note: ARMv8-M without the Main Extension disables unaligned access by default. + */ +#if defined(UNALIGNED_SUPPORT_DISABLE) || defined(__ARM_FEATURE_UNALIGNED) + SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk; +#endif + + /* Security Extension Features */ +#if IS_SECURE_ENVIRONMENT + /* Settings for TrustZone SAU setup are defined in partitions_max32657.h */ + TZ_SAU_Setup(); +#endif /* TrustZone */ - /* Enable FPU on Cortex-M4, which occupies coprocessor slots 10 & 11 */ - /* Grant full access, per "Table B3-24 CPACR bit assignments". */ - /* DDI0403D "ARMv7-M Architecture Reference Manual" */ - SCB->CPACR |= SCB_CPACR_CP10_Msk | SCB_CPACR_CP11_Msk; __DSB(); __ISB(); + /* Enable interrupts */ + __enable_irq(); + /* Change system clock source to the main high-speed clock */ MXC_SYS_Clock_Select(MXC_SYS_CLOCK_IPO); MXC_SYS_SetClockDiv(MXC_SYS_CLOCK_DIV_1); @@ -148,4 +161,4 @@ __weak void SystemInit(void) PinInit(); Board_Init(); -} \ No newline at end of file +} From 553d1a2ccf6497f09fc12bb24d1eb81154bdc165 Mon Sep 17 00:00:00 2001 From: Woo Date: Fri, 3 May 2024 16:12:38 -0500 Subject: [PATCH 62/93] Push unsavbed changes in system_max32657.h --- Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c index 652790d2796..4e052bde544 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c @@ -27,7 +27,7 @@ extern void (*const __isr_vector[])(void); -uint32_t SystemCoreClock = IPO_FREQ; +uint32_t SystemCoreClock = IPO_FREQ; // Part defaults to IPO on startup /* The libc implementation from GCC 11+ depends on _getpid and _kill in some places. @@ -122,7 +122,6 @@ __weak int Board_Init(void) */ __weak void SystemInit(void) { - #if defined(__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) SCB->VTOR = (uint32_t)__isr_vector; #endif /* __VTOR_PRESENT check */ From 89ea2be0c2b0e5bf0e9ae3be5848f13837546489 Mon Sep 17 00:00:00 2001 From: Woo Date: Fri, 3 May 2024 18:26:50 -0500 Subject: [PATCH 63/93] Sync SYS, PWRSEQ, and CRC registers to register doc (initial) --- .../Device/Maxim/MAX32657/Include/crc_regs.h | 5 +- .../Device/Maxim/MAX32657/Include/fcr_regs.h | 121 +- .../Device/Maxim/MAX32657/Include/gcr_regs.h | 123 +- .../Maxim/MAX32657/Include/max32657.svd | 5359 ++--------------- .../Device/Maxim/MAX32657/Include/mcr_regs.h | 228 +- .../Maxim/MAX32657/Include/pwrseq_regs.h | 1235 +--- .../Device/Maxim/MAX32657/Include/sir_regs.h | 45 +- .../PeriphDrivers/Source/CRC/crc_reva.svd | 8 +- .../PeriphDrivers/Source/LP/pwrseq_me30.svd | 3073 +--------- .../PeriphDrivers/Source/SYS/SVD/fcr_me30.svd | 320 +- .../PeriphDrivers/Source/SYS/SVD/gcr_me30.svd | 1273 +--- .../PeriphDrivers/Source/SYS/SVD/mcr_me30.svd | 329 +- .../PeriphDrivers/Source/SYS/SVD/sir_me30.svd | 112 +- 13 files changed, 761 insertions(+), 11470 deletions(-) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/crc_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/crc_regs.h index fe26a3df145..1cbe04b2618 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/crc_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/crc_regs.h @@ -75,9 +75,10 @@ typedef struct { __IO uint32_t ctrl; /**< \b 0x0000: CRC CTRL Register */ union { __IO uint32_t datain32; /**< \b 0x0004: CRC DATAIN32 Register */ - __IO uint16_t datain16[2]; /**< \b 0x0004: CRC DATAIN16 Register */ - __IO uint8_t datain8[4]; /**< \b 0x0004: CRC DATAIN8 Register */ + __IO uint16_t datain16; /**< \b 0x0004: CRC DATAIN16 Register */ + __IO uint8_t datain8; /**< \b 0x0004: CRC DATAIN8 Register */ }; + __R uint8_t rsv_0x5_0x7[3]; __IO uint32_t poly; /**< \b 0x0008: CRC POLY Register */ __IO uint32_t val; /**< \b 0x000C: CRC VAL Register */ } mxc_crc_regs_t; diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h index f9badfb8265..01f4cd18d34 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h @@ -78,8 +78,6 @@ typedef struct { __IO uint32_t fctrl3; /**< \b 0x0C: FCR FCTRL3 Register */ __R uint32_t rsv_0x10_0x17[2]; __IO uint32_t erfoks; /**< \b 0x18: FCR ERFOKS Register */ - __R uint32_t rsv_0x1c_0x23[2]; - __IO uint32_t flvfilt; /**< \b 0x24: FCR FLVFILT Register */ } mxc_fcr_regs_t; /* Register offsets for module FCR */ @@ -94,7 +92,6 @@ typedef struct { #define MXC_R_FCR_FCTRL2 ((uint32_t)0x00000008UL) /**< Offset from FCR Base Address: 0x0008 */ #define MXC_R_FCR_FCTRL3 ((uint32_t)0x0000000CUL) /**< Offset from FCR Base Address: 0x000C */ #define MXC_R_FCR_ERFOKS ((uint32_t)0x00000018UL) /**< Offset from FCR Base Address: 0x0018 */ -#define MXC_R_FCR_FLVFILT ((uint32_t)0x00000024UL) /**< Offset from FCR Base Address: 0x0024 */ /**@} end of group fcr_registers */ /** @@ -103,49 +100,17 @@ typedef struct { * @brief Register 0. * @{ */ -#define MXC_F_FCR_FCTRL0_BTLELDOTX_POS 0 /**< FCTRL0_BTLELDOTX Position */ -#define MXC_F_FCR_FCTRL0_BTLELDOTX ((uint32_t)(0x1FUL << MXC_F_FCR_FCTRL0_BTLELDOTX_POS)) /**< FCTRL0_BTLELDOTX Mask */ -#define MXC_V_FCR_FCTRL0_BTLELDOTX_SYS ((uint32_t)0x0UL) /**< FCTRL0_BTLELDOTX_SYS Value */ -#define MXC_S_FCR_FCTRL0_BTLELDOTX_SYS (MXC_V_FCR_FCTRL0_BTLELDOTX_SYS << MXC_F_FCR_FCTRL0_BTLELDOTX_POS) /**< FCTRL0_BTLELDOTX_SYS Setting */ -#define MXC_V_FCR_FCTRL0_BTLELDOTX_DIG ((uint32_t)0x1UL) /**< FCTRL0_BTLELDOTX_DIG Value */ -#define MXC_S_FCR_FCTRL0_BTLELDOTX_DIG (MXC_V_FCR_FCTRL0_BTLELDOTX_DIG << MXC_F_FCR_FCTRL0_BTLELDOTX_POS) /**< FCTRL0_BTLELDOTX_DIG Setting */ +#define MXC_F_FCR_FCTRL0_BTLELDO_TX_POS 0 /**< FCTRL0_BTLELDO_TX Position */ +#define MXC_F_FCR_FCTRL0_BTLELDO_TX ((uint32_t)(0x1FUL << MXC_F_FCR_FCTRL0_BTLELDO_TX_POS)) /**< FCTRL0_BTLELDO_TX Mask */ -#define MXC_F_FCR_FCTRL0_BTLELDORX_POS 8 /**< FCTRL0_BTLELDORX Position */ -#define MXC_F_FCR_FCTRL0_BTLELDORX ((uint32_t)(0x1FUL << MXC_F_FCR_FCTRL0_BTLELDORX_POS)) /**< FCTRL0_BTLELDORX Mask */ -#define MXC_V_FCR_FCTRL0_BTLELDORX_SYS ((uint32_t)0x0UL) /**< FCTRL0_BTLELDORX_SYS Value */ -#define MXC_S_FCR_FCTRL0_BTLELDORX_SYS (MXC_V_FCR_FCTRL0_BTLELDORX_SYS << MXC_F_FCR_FCTRL0_BTLELDORX_POS) /**< FCTRL0_BTLELDORX_SYS Setting */ -#define MXC_V_FCR_FCTRL0_BTLELDORX_DIG ((uint32_t)0x1UL) /**< FCTRL0_BTLELDORX_DIG Value */ -#define MXC_S_FCR_FCTRL0_BTLELDORX_DIG (MXC_V_FCR_FCTRL0_BTLELDORX_DIG << MXC_F_FCR_FCTRL0_BTLELDORX_POS) /**< FCTRL0_BTLELDORX_DIG Setting */ +#define MXC_F_FCR_FCTRL0_BTLELDO_RX_POS 8 /**< FCTRL0_BTLELDO_RX Position */ +#define MXC_F_FCR_FCTRL0_BTLELDO_RX ((uint32_t)(0x1FUL << MXC_F_FCR_FCTRL0_BTLELDO_RX_POS)) /**< FCTRL0_BTLELDO_RX Mask */ -#define MXC_F_FCR_FCTRL0_I2C0DGEN0_POS 20 /**< FCTRL0_I2C0DGEN0 Position */ -#define MXC_F_FCR_FCTRL0_I2C0DGEN0 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0DGEN0_POS)) /**< FCTRL0_I2C0DGEN0 Mask */ +#define MXC_F_FCR_FCTRL0_I3CDGEN0_POS 20 /**< FCTRL0_I3CDGEN0 Position */ +#define MXC_F_FCR_FCTRL0_I3CDGEN0 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I3CDGEN0_POS)) /**< FCTRL0_I3CDGEN0 Mask */ -#define MXC_F_FCR_FCTRL0_I2C0DGEN1_POS 21 /**< FCTRL0_I2C0DGEN1 Position */ -#define MXC_F_FCR_FCTRL0_I2C0DGEN1 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C0DGEN1_POS)) /**< FCTRL0_I2C0DGEN1 Mask */ - -#define MXC_F_FCR_FCTRL0_I2C1DGEN0_POS 22 /**< FCTRL0_I2C1DGEN0 Position */ -#define MXC_F_FCR_FCTRL0_I2C1DGEN0 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1DGEN0_POS)) /**< FCTRL0_I2C1DGEN0 Mask */ - -#define MXC_F_FCR_FCTRL0_I2C1DGEN1_POS 23 /**< FCTRL0_I2C1DGEN1 Position */ -#define MXC_F_FCR_FCTRL0_I2C1DGEN1 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C1DGEN1_POS)) /**< FCTRL0_I2C1DGEN1 Mask */ - -#define MXC_F_FCR_FCTRL0_I2C2ADGEN0_POS 24 /**< FCTRL0_I2C2ADGEN0 Position */ -#define MXC_F_FCR_FCTRL0_I2C2ADGEN0 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2ADGEN0_POS)) /**< FCTRL0_I2C2ADGEN0 Mask */ - -#define MXC_F_FCR_FCTRL0_I2C2ADGEN1_POS 25 /**< FCTRL0_I2C2ADGEN1 Position */ -#define MXC_F_FCR_FCTRL0_I2C2ADGEN1 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2ADGEN1_POS)) /**< FCTRL0_I2C2ADGEN1 Mask */ - -#define MXC_F_FCR_FCTRL0_I2C2BDGEN0_POS 26 /**< FCTRL0_I2C2BDGEN0 Position */ -#define MXC_F_FCR_FCTRL0_I2C2BDGEN0 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2BDGEN0_POS)) /**< FCTRL0_I2C2BDGEN0 Mask */ - -#define MXC_F_FCR_FCTRL0_I2C2BDGEN1_POS 27 /**< FCTRL0_I2C2BDGEN1 Position */ -#define MXC_F_FCR_FCTRL0_I2C2BDGEN1 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2BDGEN1_POS)) /**< FCTRL0_I2C2BDGEN1 Mask */ - -#define MXC_F_FCR_FCTRL0_I2C2CDGEN0_POS 28 /**< FCTRL0_I2C2CDGEN0 Position */ -#define MXC_F_FCR_FCTRL0_I2C2CDGEN0 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2CDGEN0_POS)) /**< FCTRL0_I2C2CDGEN0 Mask */ - -#define MXC_F_FCR_FCTRL0_I2C2CDGEN1_POS 29 /**< FCTRL0_I2C2CDGEN1 Position */ -#define MXC_F_FCR_FCTRL0_I2C2CDGEN1 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I2C2CDGEN1_POS)) /**< FCTRL0_I2C2CDGEN1 Mask */ +#define MXC_F_FCR_FCTRL0_I3CDGEN1_POS 21 /**< FCTRL0_I3CDGEN1 Position */ +#define MXC_F_FCR_FCTRL0_I3CDGEN1 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I3CDGEN1_POS)) /**< FCTRL0_I3CDGEN1 Mask */ /**@} end of group FCR_FCTRL0_Register */ @@ -173,8 +138,8 @@ typedef struct { #define MXC_F_FCR_FCTRL1_MU_POS 8 /**< FCTRL1_MU Position */ #define MXC_F_FCR_FCTRL1_MU ((uint32_t)(0xFFFUL << MXC_F_FCR_FCTRL1_MU_POS)) /**< FCTRL1_MU Mask */ -#define MXC_F_FCR_FCTRL1_AC_TRIM_POS 23 /**< FCTRL1_AC_TRIM Position */ -#define MXC_F_FCR_FCTRL1_AC_TRIM ((uint32_t)(0x1FFUL << MXC_F_FCR_FCTRL1_AC_TRIM_POS)) /**< FCTRL1_AC_TRIM Mask */ +#define MXC_F_FCR_FCTRL1_AC_TRIM_OUT_POS 23 /**< FCTRL1_AC_TRIM_OUT Position */ +#define MXC_F_FCR_FCTRL1_AC_TRIM_OUT ((uint32_t)(0x1FFUL << MXC_F_FCR_FCTRL1_AC_TRIM_OUT_POS)) /**< FCTRL1_AC_TRIM_OUT Mask */ /**@} end of group FCR_FCTRL1_Register */ @@ -184,32 +149,8 @@ typedef struct { * @brief Register 2. * @{ */ -#define MXC_F_FCR_FCTRL2_NFC_FWD_EN_POS 0 /**< FCTRL2_NFC_FWD_EN Position */ -#define MXC_F_FCR_FCTRL2_NFC_FWD_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL2_NFC_FWD_EN_POS)) /**< FCTRL2_NFC_FWD_EN Mask */ - -#define MXC_F_FCR_FCTRL2_NFC_CLK_EN_POS 1 /**< FCTRL2_NFC_CLK_EN Position */ -#define MXC_F_FCR_FCTRL2_NFC_CLK_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL2_NFC_CLK_EN_POS)) /**< FCTRL2_NFC_CLK_EN Mask */ - -#define MXC_F_FCR_FCTRL2_NFC_FWD_TX_DATA_OVR_POS 2 /**< FCTRL2_NFC_FWD_TX_DATA_OVR Position */ -#define MXC_F_FCR_FCTRL2_NFC_FWD_TX_DATA_OVR ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL2_NFC_FWD_TX_DATA_OVR_POS)) /**< FCTRL2_NFC_FWD_TX_DATA_OVR Mask */ - -#define MXC_F_FCR_FCTRL2_XO_EN_DGL_POS 3 /**< FCTRL2_XO_EN_DGL Position */ -#define MXC_F_FCR_FCTRL2_XO_EN_DGL ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL2_XO_EN_DGL_POS)) /**< FCTRL2_XO_EN_DGL Mask */ - -#define MXC_F_FCR_FCTRL2_RX_BIAS_PD_POS 4 /**< FCTRL2_RX_BIAS_PD Position */ -#define MXC_F_FCR_FCTRL2_RX_BIAS_PD ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL2_RX_BIAS_PD_POS)) /**< FCTRL2_RX_BIAS_PD Mask */ - -#define MXC_F_FCR_FCTRL2_RX_BIAS_EN_POS 5 /**< FCTRL2_RX_BIAS_EN Position */ -#define MXC_F_FCR_FCTRL2_RX_BIAS_EN ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL2_RX_BIAS_EN_POS)) /**< FCTRL2_RX_BIAS_EN Mask */ - -#define MXC_F_FCR_FCTRL2_RX_TM_VBG_VABUS_POS 6 /**< FCTRL2_RX_TM_VBG_VABUS Position */ -#define MXC_F_FCR_FCTRL2_RX_TM_VBG_VABUS ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL2_RX_TM_VBG_VABUS_POS)) /**< FCTRL2_RX_TM_VBG_VABUS Mask */ - -#define MXC_F_FCR_FCTRL2_RX_TM_BIAS_POS 7 /**< FCTRL2_RX_TM_BIAS Position */ -#define MXC_F_FCR_FCTRL2_RX_TM_BIAS ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL2_RX_TM_BIAS_POS)) /**< FCTRL2_RX_TM_BIAS Mask */ - -#define MXC_F_FCR_FCTRL2_NFC_FWD_DOUT_POS 8 /**< FCTRL2_NFC_FWD_DOUT Position */ -#define MXC_F_FCR_FCTRL2_NFC_FWD_DOUT ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL2_NFC_FWD_DOUT_POS)) /**< FCTRL2_NFC_FWD_DOUT Mask */ +#define MXC_F_FCR_FCTRL2_AC_INIT_TRIM_POS 0 /**< FCTRL2_AC_INIT_TRIM Position */ +#define MXC_F_FCR_FCTRL2_AC_INIT_TRIM ((uint32_t)(0x1FFUL << MXC_F_FCR_FCTRL2_AC_INIT_TRIM_POS)) /**< FCTRL2_AC_INIT_TRIM Mask */ /**@} end of group FCR_FCTRL2_Register */ @@ -219,8 +160,11 @@ typedef struct { * @brief Register 3. * @{ */ -#define MXC_F_FCR_FCTRL3_DONECNT_POS 0 /**< FCTRL3_DONECNT Position */ -#define MXC_F_FCR_FCTRL3_DONECNT ((uint32_t)(0xFFUL << MXC_F_FCR_FCTRL3_DONECNT_POS)) /**< FCTRL3_DONECNT Mask */ +#define MXC_F_FCR_FCTRL3_AC_RUNTIME_POS 0 /**< FCTRL3_AC_RUNTIME Position */ +#define MXC_F_FCR_FCTRL3_AC_RUNTIME ((uint32_t)(0xFFUL << MXC_F_FCR_FCTRL3_AC_RUNTIME_POS)) /**< FCTRL3_AC_RUNTIME Mask */ + +#define MXC_F_FCR_FCTRL3_AC_DIV_POS 8 /**< FCTRL3_AC_DIV Position */ +#define MXC_F_FCR_FCTRL3_AC_DIV ((uint32_t)(0x1FFFUL << MXC_F_FCR_FCTRL3_AC_DIV_POS)) /**< FCTRL3_AC_DIV Mask */ /**@} end of group FCR_FCTRL3_Register */ @@ -230,27 +174,26 @@ typedef struct { * @brief ERFO Kick Start Register. * @{ */ -#define MXC_F_FCR_ERFOKS_GP_POS 0 /**< ERFOKS_GP Position */ -#define MXC_F_FCR_ERFOKS_GP ((uint32_t)(0xFFFFFFFFUL << MXC_F_FCR_ERFOKS_GP_POS)) /**< ERFOKS_GP Mask */ +#define MXC_F_FCR_ERFOKS_CNT_POS 0 /**< ERFOKS_CNT Position */ +#define MXC_F_FCR_ERFOKS_CNT ((uint32_t)(0x7FUL << MXC_F_FCR_ERFOKS_CNT_POS)) /**< ERFOKS_CNT Mask */ -/**@} end of group FCR_ERFOKS_Register */ +#define MXC_F_FCR_ERFOKS_EN_POS 7 /**< ERFOKS_EN Position */ +#define MXC_F_FCR_ERFOKS_EN ((uint32_t)(0x1UL << MXC_F_FCR_ERFOKS_EN_POS)) /**< ERFOKS_EN Mask */ -/** - * @ingroup fcr_registers - * @defgroup FCR_FLVFILT FCR_FLVFILT - * @brief Flash Low Voltage Filter Control Register. - * @{ - */ -#define MXC_F_FCR_FLVFILT_NUM_POS 0 /**< FLVFILT_NUM Position */ -#define MXC_F_FCR_FLVFILT_NUM ((uint32_t)(0xFFUL << MXC_F_FCR_FLVFILT_NUM_POS)) /**< FLVFILT_NUM Mask */ +#define MXC_F_FCR_ERFOKS_DRVSTR_POS 8 /**< ERFOKS_DRVSTR Position */ +#define MXC_F_FCR_ERFOKS_DRVSTR ((uint32_t)(0x7UL << MXC_F_FCR_ERFOKS_DRVSTR_POS)) /**< ERFOKS_DRVSTR Mask */ -#define MXC_F_FCR_FLVFILT_RATE_POS 8 /**< FLVFILT_RATE Position */ -#define MXC_F_FCR_FLVFILT_RATE ((uint32_t)(0xFFUL << MXC_F_FCR_FLVFILT_RATE_POS)) /**< FLVFILT_RATE Mask */ +#define MXC_F_FCR_ERFOKS_X2_PLEN_POS 11 /**< ERFOKS_X2_PLEN Position */ +#define MXC_F_FCR_ERFOKS_X2_PLEN ((uint32_t)(0x1UL << MXC_F_FCR_ERFOKS_X2_PLEN_POS)) /**< ERFOKS_X2_PLEN Mask */ -#define MXC_F_FCR_FLVFILT_DELAY_POS 16 /**< FLVFILT_DELAY Position */ -#define MXC_F_FCR_FLVFILT_DELAY ((uint32_t)(0xFFUL << MXC_F_FCR_FLVFILT_DELAY_POS)) /**< FLVFILT_DELAY Mask */ +#define MXC_F_FCR_ERFOKS_CLKSEL_POS 12 /**< ERFOKS_CLKSEL Position */ +#define MXC_F_FCR_ERFOKS_CLKSEL ((uint32_t)(0x3UL << MXC_F_FCR_ERFOKS_CLKSEL_POS)) /**< ERFOKS_CLKSEL Mask */ +#define MXC_V_FCR_ERFOKS_CLKSEL_NO_CLK ((uint32_t)0x0UL) /**< ERFOKS_CLKSEL_NO_CLK Value */ +#define MXC_S_FCR_ERFOKS_CLKSEL_NO_CLK (MXC_V_FCR_ERFOKS_CLKSEL_NO_CLK << MXC_F_FCR_ERFOKS_CLKSEL_POS) /**< ERFOKS_CLKSEL_NO_CLK Setting */ +#define MXC_V_FCR_ERFOKS_CLKSEL_IPO ((uint32_t)0x3UL) /**< ERFOKS_CLKSEL_IPO Value */ +#define MXC_S_FCR_ERFOKS_CLKSEL_IPO (MXC_V_FCR_ERFOKS_CLKSEL_IPO << MXC_F_FCR_ERFOKS_CLKSEL_POS) /**< ERFOKS_CLKSEL_IPO Setting */ -/**@} end of group FCR_FLVFILT_Register */ +/**@} end of group FCR_ERFOKS_Register */ #ifdef __cplusplus } diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h index 9877604cad3..9eece4d2c39 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h @@ -96,10 +96,6 @@ typedef struct { __IO uint32_t eccaddr; /**< \b 0x70: GCR ECCADDR Register */ __IO uint32_t btleldoctrl; /**< \b 0x74: GCR BTLELDOCTRL Register */ __IO uint32_t btleldodly; /**< \b 0x78: GCR BTLELDODLY Register */ - __R uint32_t rsv_0x7c; - __IO uint32_t flvrst; /**< \b 0x80: GCR FLVRST Register */ - __IO uint32_t flvclkctrl; /**< \b 0x84: GCR FLVCLKCTRL Register */ - __IO uint32_t flvstat; /**< \b 0x88: GCR FLVSTAT Register */ } mxc_gcr_regs_t; /* Register offsets for module GCR */ @@ -128,9 +124,6 @@ typedef struct { #define MXC_R_GCR_ECCADDR ((uint32_t)0x00000070UL) /**< Offset from GCR Base Address: 0x0070 */ #define MXC_R_GCR_BTLELDOCTRL ((uint32_t)0x00000074UL) /**< Offset from GCR Base Address: 0x0074 */ #define MXC_R_GCR_BTLELDODLY ((uint32_t)0x00000078UL) /**< Offset from GCR Base Address: 0x0078 */ -#define MXC_R_GCR_FLVRST ((uint32_t)0x00000080UL) /**< Offset from GCR Base Address: 0x0080 */ -#define MXC_R_GCR_FLVCLKCTRL ((uint32_t)0x00000084UL) /**< Offset from GCR Base Address: 0x0084 */ -#define MXC_R_GCR_FLVSTAT ((uint32_t)0x00000088UL) /**< Offset from GCR Base Address: 0x0088 */ /**@} end of group gcr_registers */ /** @@ -139,22 +132,6 @@ typedef struct { * @brief System Control. * @{ */ -#define MXC_F_GCR_SYSCTRL_BSTAP_EN_POS 0 /**< SYSCTRL_BSTAP_EN Position */ -#define MXC_F_GCR_SYSCTRL_BSTAP_EN ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_BSTAP_EN_POS)) /**< SYSCTRL_BSTAP_EN Mask */ - -#define MXC_F_GCR_SYSCTRL_SBUSARB_POS 1 /**< SYSCTRL_SBUSARB Position */ -#define MXC_F_GCR_SYSCTRL_SBUSARB ((uint32_t)(0x3UL << MXC_F_GCR_SYSCTRL_SBUSARB_POS)) /**< SYSCTRL_SBUSARB Mask */ -#define MXC_V_GCR_SYSCTRL_SBUSARB_FIX ((uint32_t)0x0UL) /**< SYSCTRL_SBUSARB_FIX Value */ -#define MXC_S_GCR_SYSCTRL_SBUSARB_FIX (MXC_V_GCR_SYSCTRL_SBUSARB_FIX << MXC_F_GCR_SYSCTRL_SBUSARB_POS) /**< SYSCTRL_SBUSARB_FIX Setting */ -#define MXC_V_GCR_SYSCTRL_SBUSARB_ROUND ((uint32_t)0x1UL) /**< SYSCTRL_SBUSARB_ROUND Value */ -#define MXC_S_GCR_SYSCTRL_SBUSARB_ROUND (MXC_V_GCR_SYSCTRL_SBUSARB_ROUND << MXC_F_GCR_SYSCTRL_SBUSARB_POS) /**< SYSCTRL_SBUSARB_ROUND Setting */ - -#define MXC_F_GCR_SYSCTRL_FLASH_PAGE_FLIP_POS 4 /**< SYSCTRL_FLASH_PAGE_FLIP Position */ -#define MXC_F_GCR_SYSCTRL_FLASH_PAGE_FLIP ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_FLASH_PAGE_FLIP_POS)) /**< SYSCTRL_FLASH_PAGE_FLIP Mask */ - -#define MXC_F_GCR_SYSCTRL_FPU_DIS_POS 5 /**< SYSCTRL_FPU_DIS Position */ -#define MXC_F_GCR_SYSCTRL_FPU_DIS ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_FPU_DIS_POS)) /**< SYSCTRL_FPU_DIS Mask */ - #define MXC_F_GCR_SYSCTRL_ICC_FLUSH_POS 6 /**< SYSCTRL_ICC_FLUSH Position */ #define MXC_F_GCR_SYSCTRL_ICC_FLUSH ((uint32_t)(0x1UL << MXC_F_GCR_SYSCTRL_ICC_FLUSH_POS)) /**< SYSCTRL_ICC_FLUSH Mask */ @@ -240,17 +217,6 @@ typedef struct { * @brief Clock Control. * @{ */ -#define MXC_F_GCR_CLKCTRL_PCLK_DIV_POS 3 /**< CLKCTRL_PCLK_DIV Position */ -#define MXC_F_GCR_CLKCTRL_PCLK_DIV ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_PCLK_DIV_POS)) /**< CLKCTRL_PCLK_DIV Mask */ -#define MXC_V_GCR_CLKCTRL_PCLK_DIV_DIV1 ((uint32_t)0x0UL) /**< CLKCTRL_PCLK_DIV_DIV1 Value */ -#define MXC_S_GCR_CLKCTRL_PCLK_DIV_DIV1 (MXC_V_GCR_CLKCTRL_PCLK_DIV_DIV1 << MXC_F_GCR_CLKCTRL_PCLK_DIV_POS) /**< CLKCTRL_PCLK_DIV_DIV1 Setting */ -#define MXC_V_GCR_CLKCTRL_PCLK_DIV_DIV2 ((uint32_t)0x1UL) /**< CLKCTRL_PCLK_DIV_DIV2 Value */ -#define MXC_S_GCR_CLKCTRL_PCLK_DIV_DIV2 (MXC_V_GCR_CLKCTRL_PCLK_DIV_DIV2 << MXC_F_GCR_CLKCTRL_PCLK_DIV_POS) /**< CLKCTRL_PCLK_DIV_DIV2 Setting */ -#define MXC_V_GCR_CLKCTRL_PCLK_DIV_DIV4 ((uint32_t)0x2UL) /**< CLKCTRL_PCLK_DIV_DIV4 Value */ -#define MXC_S_GCR_CLKCTRL_PCLK_DIV_DIV4 (MXC_V_GCR_CLKCTRL_PCLK_DIV_DIV4 << MXC_F_GCR_CLKCTRL_PCLK_DIV_POS) /**< CLKCTRL_PCLK_DIV_DIV4 Setting */ -#define MXC_V_GCR_CLKCTRL_PCLK_DIV_DIV8 ((uint32_t)0x3UL) /**< CLKCTRL_PCLK_DIV_DIV8 Value */ -#define MXC_S_GCR_CLKCTRL_PCLK_DIV_DIV8 (MXC_V_GCR_CLKCTRL_PCLK_DIV_DIV8 << MXC_F_GCR_CLKCTRL_PCLK_DIV_POS) /**< CLKCTRL_PCLK_DIV_DIV8 Setting */ - #define MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS 6 /**< CLKCTRL_SYSCLK_DIV Position */ #define MXC_F_GCR_CLKCTRL_SYSCLK_DIV ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_SYSCLK_DIV_POS)) /**< CLKCTRL_SYSCLK_DIV Mask */ #define MXC_V_GCR_CLKCTRL_SYSCLK_DIV_DIV1 ((uint32_t)0x0UL) /**< CLKCTRL_SYSCLK_DIV_DIV1 Value */ @@ -272,18 +238,18 @@ typedef struct { #define MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS 9 /**< CLKCTRL_SYSCLK_SEL Position */ #define MXC_F_GCR_CLKCTRL_SYSCLK_SEL ((uint32_t)(0x7UL << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS)) /**< CLKCTRL_SYSCLK_SEL Mask */ -#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ISO ((uint32_t)0x0UL) /**< CLKCTRL_SYSCLK_SEL_ISO Value */ -#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ISO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ISO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_ISO Setting */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO ((uint32_t)0x0UL) /**< CLKCTRL_SYSCLK_SEL_IPO Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_IPO Setting */ #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO ((uint32_t)0x2UL) /**< CLKCTRL_SYSCLK_SEL_ERFO Value */ #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERFO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERFO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_ERFO Setting */ #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO ((uint32_t)0x3UL) /**< CLKCTRL_SYSCLK_SEL_INRO Value */ #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_INRO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_INRO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_INRO Setting */ -#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO ((uint32_t)0x4UL) /**< CLKCTRL_SYSCLK_SEL_IPO Value */ -#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IPO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IPO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_IPO Setting */ #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO ((uint32_t)0x5UL) /**< CLKCTRL_SYSCLK_SEL_IBRO Value */ #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IBRO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_IBRO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_IBRO Setting */ #define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO ((uint32_t)0x6UL) /**< CLKCTRL_SYSCLK_SEL_ERTCO Value */ #define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_ERTCO << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_ERTCO Setting */ +#define MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK ((uint32_t)0x7UL) /**< CLKCTRL_SYSCLK_SEL_EXTCLK Value */ +#define MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK (MXC_V_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK << MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS) /**< CLKCTRL_SYSCLK_SEL_EXTCLK Setting */ #define MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS 13 /**< CLKCTRL_SYSCLK_RDY Position */ #define MXC_F_GCR_CLKCTRL_SYSCLK_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_SYSCLK_RDY_POS)) /**< CLKCTRL_SYSCLK_RDY Mask */ @@ -294,7 +260,7 @@ typedef struct { #define MXC_F_GCR_CLKCTRL_ERTCO_EN_POS 17 /**< CLKCTRL_ERTCO_EN Position */ #define MXC_F_GCR_CLKCTRL_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERTCO_EN_POS)) /**< CLKCTRL_ERTCO_EN Mask */ -#define MXC_F_GCR_CLKCTRL_IPO_EN_POS 18 /**< CLKCTRL_IPO_EN Position */ +#define MXC_F_GCR_CLKCTRL_IPO_EN_POS 19 /**< CLKCTRL_IPO_EN Position */ #define MXC_F_GCR_CLKCTRL_IPO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_EN_POS)) /**< CLKCTRL_IPO_EN Mask */ #define MXC_F_GCR_CLKCTRL_IBRO_EN_POS 20 /**< CLKCTRL_IBRO_EN Position */ @@ -309,7 +275,7 @@ typedef struct { #define MXC_F_GCR_CLKCTRL_ERTCO_RDY_POS 25 /**< CLKCTRL_ERTCO_RDY Position */ #define MXC_F_GCR_CLKCTRL_ERTCO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERTCO_RDY_POS)) /**< CLKCTRL_ERTCO_RDY Mask */ -#define MXC_F_GCR_CLKCTRL_IPO_RDY_POS 28 /**< CLKCTRL_IPO_RDY Position */ +#define MXC_F_GCR_CLKCTRL_IPO_RDY_POS 26 /**< CLKCTRL_IPO_RDY Position */ #define MXC_F_GCR_CLKCTRL_IPO_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_RDY_POS)) /**< CLKCTRL_IPO_RDY Mask */ #define MXC_F_GCR_CLKCTRL_IBRO_RDY_POS 28 /**< CLKCTRL_IBRO_RDY Position */ @@ -330,12 +296,10 @@ typedef struct { #define MXC_F_GCR_PM_MODE ((uint32_t)(0xFUL << MXC_F_GCR_PM_MODE_POS)) /**< PM_MODE Mask */ #define MXC_V_GCR_PM_MODE_ACTIVE ((uint32_t)0x0UL) /**< PM_MODE_ACTIVE Value */ #define MXC_S_GCR_PM_MODE_ACTIVE (MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_ACTIVE Setting */ -#define MXC_V_GCR_PM_MODE_DEEPSLEEP ((uint32_t)0x2UL) /**< PM_MODE_DEEPSLEEP Value */ -#define MXC_S_GCR_PM_MODE_DEEPSLEEP (MXC_V_GCR_PM_MODE_DEEPSLEEP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_DEEPSLEEP Setting */ -#define MXC_V_GCR_PM_MODE_SHUTDOWN ((uint32_t)0x3UL) /**< PM_MODE_SHUTDOWN Value */ -#define MXC_S_GCR_PM_MODE_SHUTDOWN (MXC_V_GCR_PM_MODE_SHUTDOWN << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_SHUTDOWN Setting */ -#define MXC_V_GCR_PM_MODE_BACKUP ((uint32_t)0x4UL) /**< PM_MODE_BACKUP Value */ +#define MXC_V_GCR_PM_MODE_BACKUP ((uint32_t)0x9UL) /**< PM_MODE_BACKUP Value */ #define MXC_S_GCR_PM_MODE_BACKUP (MXC_V_GCR_PM_MODE_BACKUP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_BACKUP Setting */ +#define MXC_V_GCR_PM_MODE_PDM ((uint32_t)0xAUL) /**< PM_MODE_PDM Value */ +#define MXC_S_GCR_PM_MODE_PDM (MXC_V_GCR_PM_MODE_PDM << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_PDM Setting */ #define MXC_F_GCR_PM_GPIO_WE_POS 4 /**< PM_GPIO_WE Position */ #define MXC_F_GCR_PM_GPIO_WE ((uint32_t)(0x1UL << MXC_F_GCR_PM_GPIO_WE_POS)) /**< PM_GPIO_WE Mask */ @@ -360,6 +324,17 @@ typedef struct { #define MXC_F_GCR_PCLKDIV_ADCFRQ_POS 10 /**< PCLKDIV_ADCFRQ Position */ #define MXC_F_GCR_PCLKDIV_ADCFRQ ((uint32_t)(0xFUL << MXC_F_GCR_PCLKDIV_ADCFRQ_POS)) /**< PCLKDIV_ADCFRQ Mask */ +#define MXC_F_GCR_PCLKDIV_AONCLKDIV_POS 14 /**< PCLKDIV_AONCLKDIV Position */ +#define MXC_F_GCR_PCLKDIV_AONCLKDIV ((uint32_t)(0x3UL << MXC_F_GCR_PCLKDIV_AONCLKDIV_POS)) /**< PCLKDIV_AONCLKDIV Mask */ +#define MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV4 ((uint32_t)0x0UL) /**< PCLKDIV_AONCLKDIV_DIV4 Value */ +#define MXC_S_GCR_PCLKDIV_AONCLKDIV_DIV4 (MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV4 << MXC_F_GCR_PCLKDIV_AONCLKDIV_POS) /**< PCLKDIV_AONCLKDIV_DIV4 Setting */ +#define MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV8 ((uint32_t)0x1UL) /**< PCLKDIV_AONCLKDIV_DIV8 Value */ +#define MXC_S_GCR_PCLKDIV_AONCLKDIV_DIV8 (MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV8 << MXC_F_GCR_PCLKDIV_AONCLKDIV_POS) /**< PCLKDIV_AONCLKDIV_DIV8 Setting */ +#define MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV16 ((uint32_t)0x2UL) /**< PCLKDIV_AONCLKDIV_DIV16 Value */ +#define MXC_S_GCR_PCLKDIV_AONCLKDIV_DIV16 (MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV16 << MXC_F_GCR_PCLKDIV_AONCLKDIV_POS) /**< PCLKDIV_AONCLKDIV_DIV16 Setting */ +#define MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV32 ((uint32_t)0x3UL) /**< PCLKDIV_AONCLKDIV_DIV32 Value */ +#define MXC_S_GCR_PCLKDIV_AONCLKDIV_DIV32 (MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV32 << MXC_F_GCR_PCLKDIV_AONCLKDIV_POS) /**< PCLKDIV_AONCLKDIV_DIV32 Setting */ + /**@} end of group GCR_PCLKDIV_Register */ /** @@ -544,7 +519,7 @@ typedef struct { * @brief ECC Interrupt Enable Register * @{ */ -#define MXC_F_GCR_ECCINTEN_FLASH_POS 0 /**< ECCINTEN_FLASH Position */ +#define MXC_F_GCR_ECCINTEN_FLASH_POS 11 /**< ECCINTEN_FLASH Position */ #define MXC_F_GCR_ECCINTEN_FLASH ((uint32_t)(0x1UL << MXC_F_GCR_ECCINTEN_FLASH_POS)) /**< ECCINTEN_FLASH Mask */ /**@} end of group GCR_ECCINTEN_Register */ @@ -642,62 +617,6 @@ typedef struct { /**@} end of group GCR_BTLELDODLY_Register */ -/** - * @ingroup gcr_registers - * @defgroup GCR_FLVRST GCR_FLVRST - * @brief Flash Low Voltage Reset Control Register - * @{ - */ -#define MXC_F_GCR_FLVRST_EN_POS 0 /**< FLVRST_EN Position */ -#define MXC_F_GCR_FLVRST_EN ((uint32_t)(0x1UL << MXC_F_GCR_FLVRST_EN_POS)) /**< FLVRST_EN Mask */ - -/**@} end of group GCR_FLVRST_Register */ - -/** - * @ingroup gcr_registers - * @defgroup GCR_FLVCLKCTRL GCR_FLVCLKCTRL - * @brief Flash Low Voltage Clock Control Register - * @{ - */ -#define MXC_F_GCR_FLVCLKCTRL_DIV_POS 0 /**< FLVCLKCTRL_DIV Position */ -#define MXC_F_GCR_FLVCLKCTRL_DIV ((uint32_t)(0x3UL << MXC_F_GCR_FLVCLKCTRL_DIV_POS)) /**< FLVCLKCTRL_DIV Mask */ -#define MXC_V_GCR_FLVCLKCTRL_DIV_512 ((uint32_t)0x0UL) /**< FLVCLKCTRL_DIV_512 Value */ -#define MXC_S_GCR_FLVCLKCTRL_DIV_512 (MXC_V_GCR_FLVCLKCTRL_DIV_512 << MXC_F_GCR_FLVCLKCTRL_DIV_POS) /**< FLVCLKCTRL_DIV_512 Setting */ -#define MXC_V_GCR_FLVCLKCTRL_DIV_256 ((uint32_t)0x1UL) /**< FLVCLKCTRL_DIV_256 Value */ -#define MXC_S_GCR_FLVCLKCTRL_DIV_256 (MXC_V_GCR_FLVCLKCTRL_DIV_256 << MXC_F_GCR_FLVCLKCTRL_DIV_POS) /**< FLVCLKCTRL_DIV_256 Setting */ -#define MXC_V_GCR_FLVCLKCTRL_DIV_128 ((uint32_t)0x2UL) /**< FLVCLKCTRL_DIV_128 Value */ -#define MXC_S_GCR_FLVCLKCTRL_DIV_128 (MXC_V_GCR_FLVCLKCTRL_DIV_128 << MXC_F_GCR_FLVCLKCTRL_DIV_POS) /**< FLVCLKCTRL_DIV_128 Setting */ -#define MXC_V_GCR_FLVCLKCTRL_DIV_64 ((uint32_t)0x3UL) /**< FLVCLKCTRL_DIV_64 Value */ -#define MXC_S_GCR_FLVCLKCTRL_DIV_64 (MXC_V_GCR_FLVCLKCTRL_DIV_64 << MXC_F_GCR_FLVCLKCTRL_DIV_POS) /**< FLVCLKCTRL_DIV_64 Setting */ - -/**@} end of group GCR_FLVCLKCTRL_Register */ - -/** - * @ingroup gcr_registers - * @defgroup GCR_FLVSTAT GCR_FLVSTAT - * @brief Flash Low Voltage Status Register - * @{ - */ -#define MXC_F_GCR_FLVSTAT_FLV_POS 0 /**< FLVSTAT_FLV Position */ -#define MXC_F_GCR_FLVSTAT_FLV ((uint32_t)(0x1UL << MXC_F_GCR_FLVSTAT_FLV_POS)) /**< FLVSTAT_FLV Mask */ - -#define MXC_F_GCR_FLVSTAT_ONES_POS 6 /**< FLVSTAT_ONES Position */ -#define MXC_F_GCR_FLVSTAT_ONES ((uint32_t)(0x1UL << MXC_F_GCR_FLVSTAT_ONES_POS)) /**< FLVSTAT_ONES Mask */ - -#define MXC_F_GCR_FLVSTAT_ZEROS_POS 7 /**< FLVSTAT_ZEROS Position */ -#define MXC_F_GCR_FLVSTAT_ZEROS ((uint32_t)(0x1UL << MXC_F_GCR_FLVSTAT_ZEROS_POS)) /**< FLVSTAT_ZEROS Mask */ - -#define MXC_F_GCR_FLVSTAT_ONES_FL_POS 14 /**< FLVSTAT_ONES_FL Position */ -#define MXC_F_GCR_FLVSTAT_ONES_FL ((uint32_t)(0x1UL << MXC_F_GCR_FLVSTAT_ONES_FL_POS)) /**< FLVSTAT_ONES_FL Mask */ - -#define MXC_F_GCR_FLVSTAT_ZEROS_FL_POS 15 /**< FLVSTAT_ZEROS_FL Position */ -#define MXC_F_GCR_FLVSTAT_ZEROS_FL ((uint32_t)(0x1UL << MXC_F_GCR_FLVSTAT_ZEROS_FL_POS)) /**< FLVSTAT_ZEROS_FL Mask */ - -#define MXC_F_GCR_FLVSTAT_BUF_POS 16 /**< FLVSTAT_BUF Position */ -#define MXC_F_GCR_FLVSTAT_BUF ((uint32_t)(0x3FFUL << MXC_F_GCR_FLVSTAT_BUF_POS)) /**< FLVSTAT_BUF Mask */ - -/**@} end of group GCR_FLVSTAT_Register */ - #ifdef __cplusplus } #endif diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd index 592a2959317..2321cf6fd1e 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd @@ -361,9 +361,7 @@ - 2 - 2 - DATAIN16[%s] + DATAIN16 CRC Data Input 0x0004 16 @@ -379,9 +377,7 @@ - 4 - 1 - DATAIN8[%s] + DATAIN8 CRC Data Input 0x0004 8 @@ -1154,171 +1150,21 @@ read-write - USBCLKSEL - USB External Core Clock Select. - 16 - 1 - - - sys - Generated clock from system clock. - 0 - - - dig - Digital clock from a GPIO. - 1 - - - - - I2C0DGEN0 - I2C0 SDA Glitch Filter Enable. - 20 - 1 - - - dis - Filter disabled. - 0 - - - en - Filter enabled. - 1 - - - - - I2C0DGEN1 - I2C0 SCL Glitch Filter Enable. - 21 - 1 - - - dis - Filter disabled. - 0 - - - en - Filter enabled. - 1 - - - - - I2C1DGEN0 - I2C1 SDA Glitch Filter Enable. - 22 - 1 - - - dis - Filter disabled. - 0 - - - en - Filter enabled. - 1 - - - - - I2C1DGEN1 - I2C1 SCL Glitch Filter Enable. - 23 - 1 - - - dis - Filter disabled. - 0 - - - en - Filter enabled. - 1 - - - - - I2C2ADGEN0 - I2C2 AF2 SDA Glitch Filter Enable. - 24 - 1 - - - dis - Filter disabled. - 0 - - - en - Filter enabled. - 1 - - - - - I2C2ADGEN1 - I2C2 AF2 SCL Glitch Filter Enable. - 25 - 1 - - - dis - Filter disabled. - 0 - - - en - Filter enabled. - 1 - - - - - I2C2BDGEN0 - I2C2 AF3 SDA Glitch Filter Enable. - 26 - 1 - - - dis - Filter disabled. - 0 - - - en - Filter enabled. - 1 - - + BTLELDO_TX + BTLE LDO TX Trim. + 0 + 5 - I2C2BDGEN1 - I2C2 AF3 SCL Glitch Filter Enable. - 27 - 1 - - - dis - Filter disabled. - 0 - - - en - Filter enabled. - 1 - - + BTLELDO_RX + BTLE LDO RX Trim. + 8 + 5 - I2C2CDGEN0 - I2C2 AF4 SDA Glitch Filter Enable - 28 + I3CDGEN0 + I3C SDA Glitch Filter Enable. + 20 1 @@ -1334,9 +1180,9 @@ - I2C2CDGEN1 - I2C2 AF4 SCL Glitch Filter Enable - 29 + I3CDGEN1 + I3C SCL Glitch Filter Enable. + 21 1 @@ -1444,8 +1290,8 @@ 12 - AC_TRIM - 150MHz HFIO Auto Calibration Trim + AC_TRIM_OUT + IPO Auto Calibration Trim 23 9 @@ -1458,58 +1304,10 @@ read-write - NFC_FWD_EN - Enabled FWD mode for NFC block + AC_INIT_TRIM + IPO Trim Automatic Calibration Initial Trim. 0 - 1 - - - NFC_CLK_EN - Enabled the NFC blocks clock divider in Analog - 1 - 1 - - - NFC_FWD_TX_DATA_OVR - FWD input for NFC block - 2 - 1 - - - XO_EN_DGL - TBD - 3 - 1 - - - RX_BIAS_PD - Power down enable for NFC receiver analog block - 4 - 1 - - - RX_BIAS_EN - Enable the NFC receiver analog blocks - 5 - 1 - - - RX_TM_VBG_VABUS - TBD - 6 - 1 - - - RX_TM_BIAS - TBD - 7 - 1 - - - NFC_FWD_DOUT - FWD output from FNC block - 8 - 1 + 9 @@ -1520,70 +1318,66 @@ read-write - DONECNT - Auto-calibration Done Counter Setting. + AC_RUNTIME + IPO Trim Autocal Run Time 0 8 - - - - GP - General Purpose Register. - 0x1C - read-write - - GP - General Purpose. - 0 - 32 + AC_DIV + IPO Trim Automatic Calibration Divide Factor. + 8 + 13 - MSRTRIM - MSR Trim Register. - 0x20 + ERFOKS + ERFO Kick Start Register. + 0x18 read-write - R1 - MSR Trim R1. + CNT + Kick Start ERFO Counter. 0 - 2 + 7 - R2 - MSR Trim R2. - 2 - 3 + EN + Kick Start ERFO Enable. + 7 + 1 - - - - FLVFILT - Flash Low Voltage Filter Control Register. - 0x24 - read-write - - NUM - Defines the number of consecutive samples of FLV status that must be good for ROM to continue. - 0 - 8 + DRVSTR + Kick Start ERFO Drive Strength. + 8 + 3 - RATE - Defines the rate for ROM sampling of the FLV status. - 8 - 8 + X2_PLEN + ERFO Kick Start Enable Double Pulse Length. + 11 + 1 - DELAY - Defines the delay from change in system clock divider until ROM begins filtering process of the FLV status. - 16 - 8 + CLKSEL + Kick Start Clock Select for ERFO + 12 + 2 + + + NO_CLK + No kick start clock. + 0 + + + IPO + IPO. + 3 + + @@ -1925,187 +1719,55 @@ 0xFFFFFFFE - BSTAP_EN - Boundary Scan TAP enable. When enabled, the JTAG port is connected to the Boundary Scan TAP. Otherwise, the port is connected to the ARM ICE function. This bit is reset by the POR. Reset value and access depend on the part number. - 0 + ICC_FLUSH + Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. + 6 1 - dis - Boundary Scan TAP port disabled. + normal + Normal Code Cache Operation 0 - en - Boundary Scan TAP port enabled. + flush + Code Caches and CPU instruction buffer are flushed 1 - SBUSARB - System bus abritration scheme. These bits are used to select between Fixed-burst abritration and Round-Robin scheme. The Round-Robin scheme is selected by default. These bits are reset by the system reset. - 1 - 2 + CCHK + Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. + 13 + 1 - fix - Fixed Burst abritration. + complete + No operation/complete. 0 - round - Round-robin scheme. + start + Start operation. 1 - FLASH_PAGE_FLIP - Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer. - 4 + CHKRES + ROM Checksum Result. This bit is only valid when the checksum is done and CCHK0 bit is cleared.. + 15 1 - normal - Physical layout matches logical layout. + pass + ROM Checksum Correct. 0 - swapped - Bottom half mapped to logical top half and vice versa. - 1 - - - - - FPU_DIS - Cortex M4 Floating Point Disable This bit is used to disable the floating-point unit of the Cortex-M4. - 5 - 1 - - - ICC_FLUSH - Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. - 6 - 1 - - - normal - Normal Code Cache Operation - 0 - - - flush - Code Caches and CPU instruction buffer are flushed - 1 - - - - - SRCC_FLUSH - Data Cache Flush. The system cache (s) will be flushed when this bit is set. - 7 - 1 - - - normal - Normal System Cache Operation - 0 - - - flush - System Cache is flushed - 1 - - - - - SRCC_DIS - Data Cache Disable. The system cache (s) will be completely disabled when this bit is set. - 9 - 1 - - - en - Is enabled. - 0 - - - dis - Is Disabled. - 1 - - - - - CHKRES1 - ROM1 Checksum Result. This bit is only valid when the checksum is done and CCHK1 bit is cleared.. - 11 - 1 - - - complete - No operation/complete. - 0 - - - start - Start operation. - 1 - - - - - CCHK1 - Compute ROM1 Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. - 12 - 1 - - - complete - No operation/complete. - 0 - - - start - Start operation. - 1 - - - - - CCHK0 - Compute ROM0 Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. - 13 - 1 - - - complete - No operation/complete. - 0 - - - start - Start operation. - 1 - - - - - CHKRES0 - ROM0 Checksum Result. This bit is only valid when the checksum is done and CCHK0 bit is cleared.. - 15 - 1 - - - pass - ROM Checksum Correct. - 0 - - - fail - ROM Checksum Fail. + fail + ROM Checksum Fail. 1 @@ -2124,156 +1786,114 @@ 0x04 - DMA + DMA0 DMA Reset. 0 1 - - WDT0 + + WDT Watchdog Timer Reset. 1 1 - + GPIO0 GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states. 2 1 - - GPIO1 - GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states. - 3 - 1 - - + TMR0 - Timer0 Reset. Setting this bit to 1 resets Timer 0 blocks. + Timer0 Reset. 5 1 - + TMR1 - Timer1 Reset. Setting this bit to 1 resets Timer 1 blocks. + Timer1 Reset. 6 1 - + TMR2 - Timer2 Reset. Setting this bit to 1 resets Timer 2 blocks. + Timer2 Reset. 7 1 - + TMR3 - Timer3 Reset. Setting this bit to 1 resets Timer 3 blocks. + Timer3 Reset. 8 1 - + TMR4 - Timer4 Reset. Setting this bit to 1 resets Timer 4 blocks. + Timer4 Reset. 9 1 - + TMR5 - Timer5 Reset. Setting this bit to 1 resets Timer 5 blocks. + Timer5 Reset. 10 1 - - UART0 - UART0 Reset. Setting this bit to 1 resets all UART 0 blocks. + + UART + UART Reset. 11 1 - - UART1 - UART1 Reset. Setting this bit to 1 resets all UART 1 blocks. - 12 - 1 - - - SPI0 - SPI0 Reset. Setting this bit to 1 resets all SPI 0 blocks. + + SPI + SPI Reset. 13 1 - - SPI1 - SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks. - 14 - 1 - - - SPI2 - SPI2 Reset. Setting this bit to 1 resets all SPI 2 blocks. - 15 - 1 - - - I2C0 - I2C0 Reset. + + I3C + I3C Reset. 16 1 - + RTC Real Time Clock Reset. 17 1 - - TMR6 - Timer6 Reset. Setting this bit to 1 resets Timer 6 blocks. - 20 - 1 - - - TMR7 - Timer7 Reset. Setting this bit to 1 resets Timer 7 blocks. - 21 - 1 - - - SEMA - Semaphore Reset. - 22 + + BTLE + BTLE Reset. + 18 1 - + TRNG - TODO(5-2-2023): Remove this bit before release. TRNG Reset. Setting this bit resets the TRNG block. + TRNG Reset. 24 1 - - ADC - Analog to Digital Reset. - 26 - 1 - - - UART2 - UART2 Reset. Setting this bit to 1 resets all UART 2 blocks. - 28 + + DMA1 + DMA1 Reset. + 27 1 - + SOFT Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer. 29 1 - + PERIPH Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset. 30 1 - + SYS System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer. 31 @@ -2287,34 +1907,6 @@ 0x08 0x00000008 - - PCLK_DIV - PCLK Divider. - 3 - 3 - - - div1 - Divide by 1. - 0 - - - div2 - Divide by 2. - 1 - - - div4 - Divide by 4. - 2 - - - div8 - Divide by 8. - 3 - - - SYSCLK_DIV Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0. @@ -2370,8 +1962,8 @@ 3 - ISO - Internal Secondary Oscilatior Clock + IPO + The internal Primary oscillator is used for the system clock. 0 @@ -2384,11 +1976,6 @@ 8kHz Internal Nano Ring Oscillator is used for the system clock. 3 - - IPO - The internal Primary oscillator is used for the system clock. - 4 - IBRO The internal Baud Rate oscillator is used for the system clock. @@ -2399,6 +1986,11 @@ 32kHz is used for the system clock. 6 + + EXTCLK + External Clock. + 7 + @@ -2420,34 +2012,6 @@ - - IPO_DIV - IPO clock divider - 14 - 2 - - - DIV1 - Divide 1. - 0 - - - DIV2 - Divide 2. - 1 - - - DIV4 - Divide 4. - 2 - - - DIV8 - Divide 8. - 3 - - - ERFO_EN 27MHz Crystal Oscillator Enable. @@ -2472,15 +2036,9 @@ 17 1 - - ISO_EN - 60MHz High Frequency Internal Reference Clock Enable. - 18 - 1 - IPO_EN - 96MHz High Frequency Internal Reference Clock Enable. + 50MHz High Frequency Internal Reference Clock Enable. 19 1 @@ -2521,16 +2079,10 @@ 25 1 - - ISO_RDY - 60MHz ISO Ready. - 26 - 1 - IPO_RDY Internal Primary Oscillator Ready. - 27 + 26 1 @@ -2556,27 +2108,22 @@ MODE Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode. 0 - 3 + 4 active Active Mode. 0 - - deepsleep - DeepSleep Mode. - 2 - - - shutdown - Shutdown Mode. - 3 - backup Backup Mode. - 4 + 9 + + + PDM + DeepSleep Mode. + 10 @@ -2593,129 +2140,56 @@ 1 - USB_WE - USB Wake Up Enable. This bit enables USB activity as wakeup source. - 6 + WUT_WE + Enable Wakeup Timer as wakeup source. + 7 1 - ERFO_PD - Radio Frequency oscilator Crystal Power Down. This bit selects the power state in DEEPSLEEP mode. - 12 + ERFO_BP + XTAL Bypass + 20 1 - active - Mode is Active. + normal + Normal 0 - deepsleep - Powered down in DEEPSLEEP. + bypass + Bypass 1 + + + + PCLKDIV + Peripheral Clock Divider. + 0x18 + - ISO_PD - Internal Secondary Oscilator Power Down. This bit selects the power state in DEEPSLEEP mode. - 15 - 1 + ADCFRQ + ADC clock Frequency. These bits define the ADC clock frequency. FADC = FPCLK / (ADCFRQ). + 10 + 4 + + + AONCLKDIV + Always-ON (AON) domain Clock Divider. These bits define the AON domain clock divider. + 14 + 2 - active - Mode is Active. + DIV4 + PCLK divide by 4. 0 - deepsleep - Powered down in DEEPSLEEP. - 1 - - - - - IPO_PD - Internal Primary Oscilatory power down. This bit selects the power state in DEEPSLEEP mode. - 16 - 1 - - - active - Mode is Active. - 0 - - - deepsleep - Powered down in DEEPSLEEP. - 1 - - - - - IBRO_PD - Internal Baud Rate Oscillator power down. This bit selects the power state in DEEPSLEEP mode. - 17 - 1 - - - active - Mode is Active. - 0 - - - deepsleep - Powered down in DEEPSLEEP. - 1 - - - - - ERFO_BP - XTAL Bypass - 20 - 1 - - - normal - Normal - 0 - - - bypass - Bypass - 1 - - - - - - - PCLKDIV - Peripheral Clock Divider. - 0x18 - 0x00000001 - - - ADCFRQ - ADC clock Frequency. These bits define the ADC clock frequency. FADC = FPCLK / (ADCFRQ). - 10 - 4 - - - AONCLKDIV - Always-ON (AON) domain Clock Divider. These bits define the AON domain clock divider. - 14 - 2 - - - DIV4 - PCLK divide by 4. - 0 - - - DIV8 - PCLK divide by 8. + DIV8 + PCLK divide by 8. 1 @@ -2756,50 +2230,26 @@ - GPIO1 - GPIO1 Disable. - 1 - 1 - - - DMA - DMA Disable. + DMA0 + DMA0 Disable. 5 1 - SPI0 - SPI 0 Disable. + SPI + SPI Disable. 6 1 - SPI1 - SPI 1 Disable. - 7 - 1 - - - SPI2 - SPI 2 Disable. - 8 - 1 - - - UART0 - UART 0 Disable. + UART + UART Disable. 9 1 - UART1 - UART 1 Disable. - 10 - 1 - - - I2C0 - I2C 0 Disable. + I3C + I3C Disable. 13 1 @@ -2839,36 +2289,6 @@ 20 1 - - ADC - ADC Disable. - 23 - 1 - - - TMR6 - Timer 6 Disable. - 24 - 1 - - - TMR7 - Timer 7 Disable. - 25 - 1 - - - I2C1 - I2C 1 Disable. - 28 - 1 - - - PT - PT Clock Disable. - 29 - 1 - @@ -2882,138 +2302,6 @@ 0 3 - - SRAM_WS - SRAM Wait State Enable - 4 - 1 - - - ROM1_WS - ROM1 Wait State Enable - 7 - 1 - - - RAM0_WS - System RAM 0 Wait State Enable - 8 - 1 - - - RAM1_WS - System RAM 1 Wait State Enable - 9 - 1 - - - RAM2_WS - System RAM 2 Wait State Enable - 10 - 1 - - - RAM3_WS - System RAM 3 Wait State Enable - 11 - 1 - - - RAM4_WS - System RAM 4 Wait State Enable - 12 - 1 - - - RAM5_WS - System RAM 5 Wait State Enable - 13 - 1 - - - RAM0LS_EN - System RAM 0 Light Sleep Mode. - 16 - 1 - - - active - RAM is active. - 0 - - - light_sleep - RAM is in Light Sleep mode. - 1 - - - - - RAM1LS_EN - System RAM 1 Light Sleep Mode. - 17 - 1 - - - RAM2LS_EN - System RAM 2 Light Sleep Mode. - 18 - 1 - - - RAM3LS_EN - System RAM 3 Light Sleep Mode. - 19 - 1 - - - RAM4LS_EN - System RAM 4 Light Sleep Mode. - 20 - 1 - - - RAM5LS_EN - System RAM 5 Light Sleep Mode. - 21 - 1 - - - ICCLS_EN - ICache RAM Light Sleep Mode. - 24 - 1 - - - ICCXIPLS_EN - ICACHE-XIP RAM Light Sleep Mode. - 25 - 1 - - - SRCCLS_EN - SysCache RAM Light Sleep Mode. - 26 - 1 - - - USBLS_EN - USB FIFO Light Sleep Mode. - 28 - 1 - - - ROM0LS_EN - ROM0 Light Sleep Mode. - 29 - 1 - - - ROM1LS_EN - ROM1 Light Sleep Mode. - 30 - 1 - @@ -3022,7 +2310,7 @@ 0x2C - RAM0 + SRAM0 System RAM Block 0. 0 1 @@ -3039,70 +2327,34 @@ - - RAM1 + + SRAM1 System RAM Block 1. 1 1 - - RAM2 + + SRAM2 System RAM Block 2. 2 1 - - RAM3 + + SRAM3 System RAM Block 3. 3 1 - - RAM4 + + SRAM4 System RAM Block 4. 4 1 - - RAM5 - System RAM Block 5. - 5 - 1 - - - RAM6 - System RAM Block 6. - 6 - 1 - - + ICC - Instruction Cache. - 8 - 1 - - - ICCXIP - Instruction Cache XIP Data and Tag Ram zeroizatoin. - 9 - 1 - - - SRCCDATA - System Cache Data Ram Zeroization. - 10 - 1 - - - SRCCTAG - System Cache Tag Zeroization. - 11 - 1 - - - USBFIFO - USB FIFO Zeroization. - 13 + Internal Cache. + 5 1 @@ -3130,264 +2382,72 @@ + + + + RST1 + Reset 1. + 0x44 + - CODEAUTHERR - Code Authentication Error Flag. This bit indicates a code authentication error has occured in XiP interface. - 1 + CRC + CRC Reset. + 9 + 1 + + + AES + AES Reset. + 10 1 - - - norm - Normal Operating Condition. - 0 - - - code - Code Integrity Error. - 1 - - + + + + PCLKDIS1 + Peripheral Clock Disable. + 0x48 + - DATAAUTHERR - Data Authentication Error Flag. This bit indicates a data authentication error has occured in XiP interface. + TRNG + TRNG Clock Disable. 2 1 - norm - Normal Operating Condition. + en + Enable. 0 - code - Code Integrity Error. + dis + Disable. 1 - - SCMEMF - System Cache Memory Fault Flag. This bit indicates a memory fault has occured in the System Cache while receiving data from the Hyperbus Interface. - 5 - 1 - - - norm - Normal Operating Condition. - 0 - - - memory - Memory Fault. - 1 - - - - - - - RST1 - Reset 1. - 0x44 - - - I2C1 - I2C1 Reset. - 0 - 1 - - - PT - PT Reset. - 1 - 1 - - - OWIRE - OWIRE Reset. - 7 - 1 - - - WDT1 - WDT1 Reset. - 8 - 1 - - - CRC - CRC Reset. - 9 - 1 - - - AES - AES Reset. - 10 - 1 - - - I2S - I2S Reset. - 13 - 1 - - - AC - AC Reset. - 14 - 1 - - - SEMA - Semaphore Reset. - 16 - 1 - - - I2C2 - I2C2 Reset. - 17 - 1 - - - UART3 - UART3 Reset. - 18 - 1 - - - UART4 - UART4 Reset. - 19 - 1 - - - UART5 - UART5 Reset. - 20 - 1 - - - - - PCLKDIS1 - Peripheral Clock Disable. - 0x48 - - - BTLE - Bluetooth Clock Disable. - 0 - 1 - - - en - Enable. - 0 - - - dis - Disable. - 1 - - - - - UART2 - UART2 Disable. - 1 - 1 - - - en - Enable. - 0 - - - dis - Disable. - 1 - - - - - TRNG - TRNG Disable. - 2 - 1 - - - WDT0 - WDT0 Clock Disable - 4 - 1 - - - WDT1 - WDT1 Clock Disable - 5 - 1 - - - SRCC - System Cache Clock Disable. - 7 - 1 - - - SEMA - Semaphore Clock Disable. - 9 - 1 - - - OWIRE - One-Wire Clock Disable. - 13 - 1 - - - CRC - CRC Clock Disable. - 14 + + CRC + CRC Disable. + 14 1 - + AES - AES Clock Disable. + AES Clock Disable 15 1 - - I2S - I2S Clock Disable. + + SPI + SPI Clock Disable 16 1 - - I2C2 - I2C2 Clock Disable - 21 - 1 - - - UART3 - UART3 Clock Disable - 22 - 1 - - - UART4 - UART4 Clock Disable - 23 - 1 - - - UART5 - UART5 Clock Disable - 24 + + WDT + WDT Clock Disable + 27 1 @@ -3398,14 +2458,14 @@ 0x4C - DMA - Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode. + DMA0 + Enable DMA0 event. When this bit is set, a DMA0 event will cause an RXEV event to wake the CPU from WFE sleep mode. 0 1 - RX - Enable RXEV pin event. When this bit is set, a logic high of GPIO0[24] will cause an RXEV event to wake the CPU from WFE sleep mode. + DMA1 + Enable DMA1 event. When this bit is set, a DMA1 event will cause an RXEV event to wake the CPU from WFE sleep mode. 1 1 @@ -3454,31 +2514,6 @@ - - CIE - Code Integrity Error Interrupt Enable. - 1 - 1 - - - SCMF - System Cache Memory Fault Interrupt Enable. - 5 - 1 - - - - - IPOCNT - IPO Warmup Count Register. - 0x58 - - - WMUPCNT - TBD - 0 - 10 - @@ -3486,121 +2521,12 @@ ECC Error Register 0x64 - - RAM0 - ECC System RAM0 Error Flag. Write 1 to clear. - 0 - 1 - - - RAM1 - ECC System RAM1 Error Flag. Write 1 to clear. - 1 - 1 - - - RAM2 - ECC System RAM2 Error Flag. Write 1 to clear. - 2 - 1 - - - RAM3 - ECC System RAM3 Error Flag. Write 1 to clear. - 3 - 1 - - - RAM4 - ECC System RAM4 Error Flag. Write 1 to clear. - 4 - 1 - - - RAM5 - ECC System RAM5 Error Flag. Write 1 to clear. - 5 - 1 - - - ICC - ECC Icache0 Error Flag. Write 1 to clear. - 8 - 1 - - - ICCXIP - ECC SFCC Instruction Cache Error Flag. Write 1 to clear. - 10 - 1 - FLASH - ECC Flash0 Error Flag. Write 1 to clear. - 11 - 1 - - - - - ECCCED - ECC Not Double Error Detect Register - 0x68 - - - RAM0 - ECC System RAM0 Error Flag. Write 1 to clear. + ECC Flash Error Flag. Write 1 to clear. 0 1 - - RAM1 - ECC System RAM1 Not Double Error Detect. Write 1 to clear. - 1 - 1 - - - RAM2 - ECC System RAM2 Not Double Error Detect. Write 1 to clear. - 2 - 1 - - - RAM3 - ECC System RAM3 Not Double Error Detect. Write 1 to clear. - 3 - 1 - - - RAM4 - ECC System RAM4 Not Double Error Detect. Write 1 to clear. - 4 - 1 - - - RAM5 - ECC System RAM5 Not Double Error Detect. Write 1 to clear. - 5 - 1 - - - ICC - ECC Icache0 Not Double Error Detect. Write 1 to clear. - 8 - 1 - - - ICCXIP - ECC IcacheXIP Not Double Error Detect. Write 1 to clear. - 10 - 1 - - - FLASH - ECC Flash0 Not Double Error Detect. Write 1 to clear. - 11 - 1 - @@ -3608,54 +2534,6 @@ ECC Interrupt Enable Register 0x6C - - RAM0 - ECC System RAM0 Interrupt Enable. - 0 - 1 - - - RAM1 - ECC System RAM1 Interrupt Enable. - 1 - 1 - - - RAM2 - ECC System RAM2 Interrupt Enable. - 2 - 1 - - - RAM3 - ECC System RAM3 Interrupt Enable. - 3 - 1 - - - RAM4 - ECC System RAM4 Interrupt Enable. - 4 - 1 - - - RAM5 - ECC System RAM5 Interrupt Enable. - 5 - 1 - - - ICC - ECC Icache0 Interrupt Enable. - 8 - 1 - - - ICCXIP - ECC IcacheXIP Interrupt Enable. - 10 - 1 - FLASH ECC Flash0 Interrupt Enable. @@ -3823,97 +2701,6 @@ - - FLVRST - Flash Low Voltage Reset Control Register - 0x80 - - - EN - Flash Low Voltage Reset Enable. - 0 - 1 - - - - - FLVCLKCTRL - Flash Low Voltage Clock Control Register - 0x84 - - - DIV - Flash Low Voltage Clock Divider Select. - 0 - 2 - - - 512 - Divide 512. - 0 - - - 256 - Divide 256 - 1 - - - 128 - Divide 128 - 2 - - - 64 - Divide 64 - 3 - - - - - - - FLVSTAT - Flash Low Voltage Status Register - 0x88 - - - FLV - Live Flash Low Voltage Detect Status. - 0 - 1 - - - ONES - FLV Buffer contains all ones if supply is above safe operating range. - 6 - 1 - - - ZEROS - FLV Buffer contains all zeros if supply is below safe operating voltage. - 7 - 1 - - - ONES_FL - Sticky version of ONES status. Write 1 to clear. - 14 - 1 - - - ZEROS_FL - Sticky version of ZEROS status. Write 1 to clear. - 15 - 1 - - - BUF - 10 Sample History of FLV status. - 16 - 10 - - - @@ -4870,40 +3657,9 @@ 0x00 - RAM0 - ECC System RAM0 Enable. - 0 - 1 - - - dis - disabled. - 0 - - - en - enabled. - 1 - - - - - - - IPOTRIM - IPO Manual Trim Register - 0x04 - - - VAL - Manual Trim Value. + FLASH + ECC Flash Enable. 0 - 8 - - - RANGE - Trim Range Select. - 8 1 @@ -4927,60 +3683,11 @@ - - CMP_CTRL - Comparator Control Register. - 0x0C - - - EN - Comparator Enable. - 0 - 1 - - - POL - Polarity Select - 5 - 1 - - - INTR_EN - IRQ Enable. - 6 - 1 - - - OUT - Comparator Output State. - 14 - 1 - - - INTR_FL - IRQ Flag - 15 - 1 - - - CTRL Control Register 0x10 - - CMP_HYST - Comparator hysteresis control. - 0 - 2 - - - INRO_EN - INRO Enable. - 2 - 1 - ERTCO_EN ERTCO Enable. @@ -4988,3438 +3695,230 @@ 1 - IBRO_EN - IBRO Enable. - 4 - 1 - - - ERTCO_LP_EN + ERTCO_IN_EN Enable 32K Oscillator input. 5 1 - - PADPUP_RST - Enable the Reset Pad Pull Up Resistors - 9 - 1 - - - 1m - 1MOhm Pullup - 0 - - - 25k - 25kOhm Pullup. - 1 - - - - - PADVDDIOHSEL_RST - Reset VIDDIOH Select. - 10 - 1 - - - - - RTCRST - Reset Register. - 0x18 - - - RTC - RTC Reset. - 0 - 1 - - - - - RTCTRIM - RTC Trim Register. - 0x1C - - - X1 - RTC Trim X1. - 0 - 5 - - - X2 - RTC Trim X2. - 8 - 5 - - GPIO3_CTRL - GPIO3 Pin Control Register. + GPIO1_CTRL + GPIO1 Pin Control Register. 0x20 - P30_OUT - GPIO3 Pin 0 Data Output. + P1_0_OUT + GPIO1 Pin 0 Data Output. 0 1 - P30_OUTEN - GPIO3 Pin 0 Output Enable. + P1_0_OUTEN + GPIO1 Pin 0 Output Enable. 1 1 - P30_PUPEN - GPIO3 Pin 0 Pull-up Enable. + P1_0_PUPEN + GPIO1 Pin 0 Pull-up Enable. 2 1 - P30_IN - GPIO3 Pin 0 Input Status. + P1_0_IN + GPIO1 Pin 0 Input Status. 3 1 - P31_OUT - GPIO3 Pin 1 Data Output. + P1_1_OUT + GPIO1 Pin 1 Data Output. 4 1 - P31_OUTEN - GPIO3 Pin 1 Output Enable. + P1_1_OUTEN + GPIO1 Pin 1 Output Enable. 5 1 - P31_PUPEN - GPIO3 Pin 1 Pull-up Enable. + P1_1_PUPEN + GPIO1 Pin 1 Pull-up Enable. 6 1 - P31_IN - GPIO3 Pin 1 Input Status. + P1_1_IN + GPIO1 Pin 1 Input Status. 7 1 - LDOCTRL - LDO Control Register. - 0x60 + RTCTRIM + User RTC Trim Register. + 0x24 - 0P9V_EN - LDO 0.9V Enable. + X2 + RTC X2 Trim. 0 - 1 + 5 + + + X1 + RTC X1 Trim. + 5 + 5 + + + + + PWRSEQ + Power Sequencer / Low Power Control Register. + 0x40006800 + + 0x00 + 0x400 + registers + + - PWRMONST - LDO Control Register. - 0x64 - - - PORZ_VLOSS - Sticky bit indicating power-on status of core power domains of VDDIO, VDDIOH, VCOR - 0 - 1 - - - PORZ_VBAT - Sticky bit indicating power-on status of the battery. - 1 - 1 - - - PORZ_VBB - Sticky bit indicating power-on status of the VBB. - 2 - 1 - - - PORZ_VDDCA - Sticky bit indicating power-on status of VAON_SW supply. - 4 - 1 - - - PORZ_VDDCB - Sticky bit indicating power-on status of VCORE_PAD supply. - 5 - 1 - - - PORZ_VDDA - Sticky bit indicating power-on status of VDDA (for analog) supply. - 6 - 1 - - - PORZ_VDDB - Sticky bit indicating power-on status of VDDB (for USB) supply. - 7 - 1 - - - RSTZ_VDDCB - Sticky bit indicating reset condition on VCORE supply. - 9 - 1 - - - RSTZ_VDDA - Sticky bit indicating reset condition on VDDA (analog) supply. - 10 - 1 - - - RSTZ_VDDB - Sticky bit indicating reset condition on VDDB (USB) supply. - 11 - 1 - - - RSTZ_VDDIO - Sticky bit indicating reset condition on VDDIO supply. - 12 - 1 - - - RSTZ_VDDIOH - Sticky bit indicating reset condition on VDDIOH supply. - 13 - 1 - - - RSTZ_VBB - Sticky bit indicating reset condition on VBB supply. - 14 - 1 - - - RSTZ_LDO0P9V - Sticky bit indicating reset condition on 0.9V USB supply. - 16 - 1 - - - RSTZ_VDDCA - Sticky bit indicating reset condition on VCORE in Analog supply. - 17 - 1 - - - RSTZ_VCOREHV - Sticky bit indicating high voltage reset condition on VCORE supply. - 18 - 1 - - - RSTZ_VDDIOHV - Sticky bit indicating high voltage reset condition on VDDIO supply. - 19 - 1 - - - RSTZ_VDDIOHHV - Sticky bit indicating high voltage reset condition on VDDIOH supply. - 20 - 1 - - - RSTZ_VNFCRX - Sticky bit indicating reset condition on VNFCRX supply. - 21 - 1 - - - RSTZ_VNFCTX - Sticky bit indicating reset condition on VNFCTX supply. - 22 - 1 - - - RSTZ_VNFC1V - Sticky bit indicating reset condition on VNFC1V supply. - 23 - 1 - - - - - - - - PWRSEQ - Power Sequencer / Low Power Control Register. - 0x40006800 - - 0x00 - 0x400 - registers - - - - LPCTRL - Low Power Control Register. - 0x00 + LPCTRL + Low Power Control Register. + 0x00 RAMRET_EN - System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. - 0 - 4 - - - OVR - Operating Voltage Range - 4 - 2 - - - 1_1V - 1.1V - 2 - - - - - RETREG_EN - Retention Regulator Enable. This bit controls the retention regulator in BACKUP mode. - 8 - 1 - - - dis - Disabled. - 0 - - - en - Enabled. - 1 - - - - - FASTWK_EN - Fast Wake-Up Mode. This bit enables fast wake-up from DeepSleep mode. (5uS typical). - 10 - 1 - - - dis - Disabled. - 0 - - - en - Enabled. - 1 - - - - - BG_DIS - Bandgap OFF. This controls the System Bandgap in DeepSleep mode. - 11 - 1 - - - on - Bandgap is always ON. - 0 - - - off - Bandgap is OFF in DeepSleep mode (default). - 1 - - - - - PORVDDCMON_DIS - VDDC (VCore) Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDC supply in DeepSleep and BACKUP mode. - 12 - 1 - - - VDDIOHHVMON_DIS - VDDIOH High Voltage Monitor Disable. This bit controls the power monitor on VDDIOH supply in all operating modes. - 17 - 1 - - - VDDIOHVMON_DIS - VDDIO High Voltage Monitor Disable. This bit controls the power monitor on VDDIO supply in all operating modes. - 18 - 1 - - - VCOREHVMON_DIS - VCORE High Voltage Monitor Disable. This bit controls the power monitor on VCORE supply in all operating modes. - 19 - 1 - - - VDDCMON_DIS - VDDC (Vcore) Monitor Disable. This bit controls the power monitor on the VCore supply in all operating modes. - 20 - 1 - - - en - Enable if Bandgap is ON (default) - 0 - - - dis - Disabled. - 1 - - - - - VRTCMON_DIS - VRTC Monitor Disable. This bit controls the power monitor on the Always-On Supply in all operating modes. - 21 - 1 - - - en - Enable if Bandgap is ON (default) - 0 - - - dis - Disabled. - 1 - - - - - VDDAMON_DIS - VDDA Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes. - 22 - 1 - - - en - Enable if Bandgap is ON (default) - 0 - - - dis - Disabled. - 1 - - - - - VDDIOMON_DIS - VDDIO Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes. - 23 - 1 - - - en - Enable if Bandgap is ON (default) - 0 - - - dis - Disabled. - 1 - - - - - VDDIOHMON_DIS - VDDIOH Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes. - 24 - 1 - - - en - Enable if Bandgap is ON (default) - 0 - - - dis - Disabled. - 1 - - - - - VDDBMON_DIS - VDDB Monitor Disable. This bit controls the Power-On Reset monitor on VDDB supply in all operating mods. - 27 - 1 - - - dis - Disabled. - 0 - - - en - Enabled. - 1 - - - - - - - LPWKFL0 - Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO0. - 0x04 - - - ALL - Wakeup Flags. - 0 - 31 - - - - - LPWKEN0 - Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0. - 0x08 - - - ALL - Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. - 0 - 31 - - - - - LPWKFL1 - Low Power I/O Wakeup Status Register 1. This register indicates the low power wakeup status for GPIO1. - 0x0C - - - LPWKEN1 - Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup functionality for GPIO1. - 0x10 - - - LPWKFL2 - Low Power I/O Wakeup Status Register 2. This register indicates the low power wakeup status for GPIO2. - 0x14 - - - LPWKEN2 - Low Power I/O Wakeup Enable Register 2. This register enables low power wakeup functionality for GPIO2. - 0x18 - - - LPWKFL3 - Low Power I/O Wakeup Status Register 3. This register indicates the low power wakeup status for GPIO3. - 0x1C - - - LPWKEN3 - Low Power I/O Wakeup Enable Register 3. This register enables low power wakeup functionality for GPIO3. - 0x20 - - - LPPWKFL - Low Power Peripheral Wakeup Status Register. - 0x30 - - - USBLS - USB UTMI Linestate Detect Wakeup Flag (write one to clear). One or both of these bits will be set when the USB bus activity causes the linestate to change and the device to wake while USB wakeup is enabled using PMLUSBWKEN. - 0 - 2 - - - AINCOMP0 - Analog Input Comparator Wakeup Flag. - 4 - 1 - - - USBVBUS - USB VBUS Detect Wakeup Flag (write one to clear). This bit will be set when the USB power supply is powered on or powered off. - 2 - 1 - - - BACKUP - Battery Back Wakeup Flag (write one to clear). This bit will be set when exiting Battery Backup Mode. - 16 - 1 - - - RSTDET - Reset Detect Wakeup Flag (write one to clear). This bit will be set when the external reset causes wakeup - 17 - 1 - - - - - LPPWKEN - Low Power Peripheral Wakeup Enable Register. - 0x34 - - - USBLS - USB UTMI Linestate Detect Wakeup Enable. These bits allow wakeup from the corresponding USB linestate signal (s) on transition (s) from low to high or high to low when PM.USBWKEN is set. - 0 - 2 - - - USBVBUS - USB VBUS Detect Wakeup Enable. This bit allows wakeup from the USB power supply on or off status. - 2 - 1 - - - AINCOMP0 - AINCOMP0 Wakeup Enable. This bit allows wakeup from the AINCOMP0. - 4 - 1 - - - WDT0 - WDT0 Wakeup Enable. This bit allows wakeup from the WDT0. - 8 - 1 - - - WDT1 - WDT1 Wakeup Enable. This bit allows wakeup from the WDT1. - 9 - 1 - - - CPU1 - CPU1 Wakeup Enable. This bit allows wakeup from the CPU1. - 10 - 1 - - - TMR0 - TMR0 Wakeup Enable. This bit allows wakeup from the TMR0. - 11 - 1 - - - TMR1 - TMR1 Wakeup Enable. This bit allows wakeup from the TMR1. - 12 - 1 - - - TMR2 - TMR2 Wakeup Enable. This bit allows wakeup from the TMR2. - 13 - 1 - - - TMR3 - TMR3 Wakeup Enable. This bit allows wakeup from the TMR3. - 14 - 1 - - - TMR4 - TMR4 Wakeup Enable. This bit allows wakeup from the TMR4. - 15 - 1 - - - TMR5 - TMR5 Wakeup Enable. This bit allows wakeup from the TMR5. - 16 - 1 - - - UART0 - UART0 Wakeup Enable. This bit allows wakeup from the UART0. - 17 - 1 - - - UART1 - UART1 Wakeup Enable. This bit allows wakeup from the UART1. - 18 - 1 - - - UART2 - UART2 Wakeup Enable. This bit allows wakeup from the UART2. - 19 - 1 - - - UART3 - UART3 Wakeup Enable. This bit allows wakeup from the UART3. - 20 - 1 - - - I2C0 - I2C0 Wakeup Enable. This bit allows wakeup from the I2C0. - 21 - 1 - - - I2C1 - I2C1 Wakeup Enable. This bit allows wakeup from the I2C1. - 22 - 1 - - - I2C2 - I2C2 Wakeup Enable. This bit allows wakeup from the I2C2. - 23 - 1 - - - I2S - I2S Wakeup Enable. This bit allows wakeup from the I2S. - 24 - 1 - - - SPI1 - SPI1 Wakeup Enable. This bit allows wakeup from the SPI1. - 25 - 1 - - - LPCMP - LPCMP Wakeup Enable. This bit allows wakeup from the LPCMP. - 26 - 1 - - - - - LPMEMSD - Low Power Memory Shutdown Control. - 0x40 - - - RAM0 - System RAM block 0 Shut Down. - 0 - 1 - - - normal - Normal Operating Mode. - 0 - - - shutdown - Shutdown Mode. - 1 - - - - - RAM1 - System RAM block 1 Shut Down. - 1 - 1 - - - normal - Normal Operating Mode. - 0 - - - shutdown - Shutdown Mode. - 1 - - - - - RAM2 - System RAM block 2 Shut Down. - 2 - 1 - - - normal - Normal Operating Mode. - 0 - - - shutdown - Shutdown Mode. - 1 - - - - - RAM3 - System RAM block 3 Shut Down. - 3 - 1 - - - normal - Normal Operating Mode. - 0 - - - shutdown - Shutdown Mode. - 1 - - - - - RAM4 - System RAM block 4 Shut Down. - 4 - 1 - - - normal - Normal Operating Mode. - 0 - - - shutdown - Shutdown Mode. - 1 - - - - - RAM5 - System RAM block 5 Shut Down. - 5 - 1 - - - normal - Normal Operating Mode. - 0 - - - shutdown - Shutdown Mode. - 1 - - - - - ICC - Instruction Cache RAM Shut Down. - 7 - 1 - - - normal - Normal Operating Mode. - 0 - - - shutdown - Shutdown Mode. - 1 - - - - - ICCXIP - XiP Instruction Cache RAM Shut Down. - 8 - 1 - - - normal - Normal Operating Mode. - 0 - - - shutdown - Shutdown Mode. - 1 - - - - - SRCC - System Cache RAM Shut Down. - 9 - 1 - - - normal - Normal Operating Mode. - 0 - - - shutdown - Shutdown Mode. - 1 - - - - - USBFIFO - USB FIFO Shut Down. - 11 - 1 - - - normal - Normal Operating Mode. - 0 - - - shutdown - Shutdown Mode. - 1 - - - - - ROM0 - ROM0 Shut Down. (CPU0 ROM) - 12 - 1 - - - normal - Normal Operating Mode. - 0 - - - shutdown - Shutdown Mode. - 1 - - - - - MEU - MEU MEM Shut Down. - 13 - 1 - - - normal - Normal Operating Mode. - 0 - - - shutdown - Shutdown Mode. - 1 - - - - - ROM1 - ROM1 Shut Down. - 15 - 1 - - - normal - Normal Operating Mode. - 0 - - - shutdown - Shutdown Mode. - 1 - - - - - - - LPVDDPD - Low Power VDD Domain Power Down Control. - 0x44 - - - BTLE - Power Down. - 1 - 1 - - - - - GP0 - General Purpose Register 0 - 0x48 - - - GP1 - General Purpose Register 1 - 0x4C - - - LPWKPOL0A - Low Power Wakeup Polarity Select for GPIO0. - 0x50 - - - 0 - Polarity Select for Wakeup Events for Pin 0. - 0 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 1 - Polarity Select for Wakeup Events for Pin 1. - 2 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 2 - Polarity Select for Wakeup Events for Pin 2. - 4 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 3 - Polarity Select for Wakeup Events for Pin 3. - 6 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 4 - Polarity Select for Wakeup Events for Pin 4. - 8 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 5 - Polarity Select for Wakeup Events for Pin 5. - 10 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 6 - Polarity Select for Wakeup Events for Pin 6. - 12 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 7 - Polarity Select for Wakeup Events for Pin 7. - 14 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 8 - Polarity Select for Wakeup Events for Pin 8. - 16 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 9 - Polarity Select for Wakeup Events for Pin 9. - 18 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 10 - Polarity Select for Wakeup Events for Pin 10. - 20 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 11 - Polarity Select for Wakeup Events for Pin 11. - 22 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 12 - Polarity Select for Wakeup Events for Pin 12. - 24 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 13 - Polarity Select for Wakeup Events for Pin 13. - 26 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 14 - Polarity Select for Wakeup Events for Pin 14. - 28 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 15 - Polarity Select for Wakeup Events for Pin 15. - 30 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - - - LPWKPOL0B - Low Power Wakeup Polarity Select for GPIO0. - 0x54 - - - 16 - Polarity Select for Wakeup Events for Pin 16. - 0 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 17 - Polarity Select for Wakeup Events for Pin 17. - 2 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 18 - Polarity Select for Wakeup Events for Pin 18. - 4 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 19 - Polarity Select for Wakeup Events for Pin 19. - 6 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 20 - Polarity Select for Wakeup Events for Pin 20. - 8 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 21 - Polarity Select for Wakeup Events for Pin 21. - 10 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 22 - Polarity Select for Wakeup Events for Pin 22. - 12 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 23 - Polarity Select for Wakeup Events for Pin 23. - 14 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 24 - Polarity Select for Wakeup Events for Pin 24. - 16 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 25 - Polarity Select for Wakeup Events for Pin 25. - 18 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 26 - Polarity Select for Wakeup Events for Pin 26. - 20 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 27 - Polarity Select for Wakeup Events for Pin 27. - 22 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 28 - Polarity Select for Wakeup Events for Pin 28. - 24 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 29 - Polarity Select for Wakeup Events for Pin 29. - 26 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 30 - Polarity Select for Wakeup Events for Pin 30. - 28 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 31 - Polarity Select for Wakeup Events for Pin 31. - 30 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - - - LPWKPOL1A - Low Power Wakeup Polarity Select for GPIO1. - 0x58 - - - 0 - Polarity Select for Wakeup Events for Pin 0. - 0 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 1 - Polarity Select for Wakeup Events for Pin 1. - 2 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 2 - Polarity Select for Wakeup Events for Pin 2. - 4 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 3 - Polarity Select for Wakeup Events for Pin 3. - 6 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 4 - Polarity Select for Wakeup Events for Pin 4. - 8 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 5 - Polarity Select for Wakeup Events for Pin 5. - 10 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 6 - Polarity Select for Wakeup Events for Pin 6. - 12 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 7 - Polarity Select for Wakeup Events for Pin 7. - 14 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 8 - Polarity Select for Wakeup Events for Pin 8. - 16 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 9 - Polarity Select for Wakeup Events for Pin 9. - 18 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 10 - Polarity Select for Wakeup Events for Pin 10. - 20 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 11 - Polarity Select for Wakeup Events for Pin 11. - 22 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 12 - Polarity Select for Wakeup Events for Pin 12. - 24 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 13 - Polarity Select for Wakeup Events for Pin 13. - 26 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 14 - Polarity Select for Wakeup Events for Pin 14. - 28 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 15 - Polarity Select for Wakeup Events for Pin 15. - 30 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - - - LPWKPOL1B - Low Power Wakeup Polarity Select for GPIO1. - 0x5C - - - 16 - Polarity Select for Wakeup Events for Pin 16. - 0 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 17 - Polarity Select for Wakeup Events for Pin 17. - 2 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 18 - Polarity Select for Wakeup Events for Pin 18. - 4 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 19 - Polarity Select for Wakeup Events for Pin 19. - 6 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 20 - Polarity Select for Wakeup Events for Pin 20. - 8 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 21 - Polarity Select for Wakeup Events for Pin 21. - 10 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 22 - Polarity Select for Wakeup Events for Pin 22. - 12 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 23 - Polarity Select for Wakeup Events for Pin 23. - 14 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 24 - Polarity Select for Wakeup Events for Pin 24. - 16 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 25 - Polarity Select for Wakeup Events for Pin 25. - 18 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 26 - Polarity Select for Wakeup Events for Pin 26. - 20 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 27 - Polarity Select for Wakeup Events for Pin 27. - 22 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 28 - Polarity Select for Wakeup Events for Pin 28. - 24 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 29 - Polarity Select for Wakeup Events for Pin 29. - 26 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 30 - Polarity Select for Wakeup Events for Pin 30. - 28 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 31 - Polarity Select for Wakeup Events for Pin 31. - 30 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - - - LPWKPOL2A - Low Power Wakeup Polarity Select for GPIO2. - 0x60 - - - 0 - Polarity Select for Wakeup Events for Pin 0. - 0 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 1 - Polarity Select for Wakeup Events for Pin 1. - 2 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 2 - Polarity Select for Wakeup Events for Pin 2. - 4 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 3 - Polarity Select for Wakeup Events for Pin 3. - 6 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 4 - Polarity Select for Wakeup Events for Pin 4. - 8 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 5 - Polarity Select for Wakeup Events for Pin 5. - 10 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 6 - Polarity Select for Wakeup Events for Pin 6. - 12 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 7 - Polarity Select for Wakeup Events for Pin 7. - 14 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 8 - Polarity Select for Wakeup Events for Pin 8. - 16 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 9 - Polarity Select for Wakeup Events for Pin 9. - 18 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 10 - Polarity Select for Wakeup Events for Pin 10. - 20 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 11 - Polarity Select for Wakeup Events for Pin 11. - 22 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 12 - Polarity Select for Wakeup Events for Pin 12. - 24 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 13 - Polarity Select for Wakeup Events for Pin 13. - 26 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 14 - Polarity Select for Wakeup Events for Pin 14. - 28 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 15 - Polarity Select for Wakeup Events for Pin 15. - 30 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - - - LPWKPOL2B - Low Power Wakeup Polarity Select for GPIO2. - 0x64 - - - 16 - Polarity Select for Wakeup Events for Pin 16. - 0 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 17 - Polarity Select for Wakeup Events for Pin 17. - 2 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 18 - Polarity Select for Wakeup Events for Pin 18. - 4 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 19 - Polarity Select for Wakeup Events for Pin 19. - 6 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 20 - Polarity Select for Wakeup Events for Pin 20. - 8 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 21 - Polarity Select for Wakeup Events for Pin 21. - 10 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 22 - Polarity Select for Wakeup Events for Pin 22. - 12 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 23 - Polarity Select for Wakeup Events for Pin 23. - 14 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 24 - Polarity Select for Wakeup Events for Pin 24. - 16 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 25 - Polarity Select for Wakeup Events for Pin 25. - 18 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 26 - Polarity Select for Wakeup Events for Pin 26. - 20 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 27 - Polarity Select for Wakeup Events for Pin 27. - 22 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 28 - Polarity Select for Wakeup Events for Pin 28. - 24 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 29 - Polarity Select for Wakeup Events for Pin 29. - 26 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 30 - Polarity Select for Wakeup Events for Pin 30. - 28 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 31 - Polarity Select for Wakeup Events for Pin 31. - 30 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - - - LPWKPOL3 - Low Power Wakeup Polarity Select for GPIO3. - 0x68 - - - 0 - Polarity Select for Wakeup Events for Pin 0. + System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 0 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - + 5 - 1 - Polarity Select for Wakeup Events for Pin 1. - 2 - 2 + FAST + Fast mode. + 8 + 1 - BOTH_EDGES - Both Edges. + dis + Disabled. 0 - RISING - Rising Edge. + en + Enabled. 1 - - FALLING - Falling Edge. - 2 - - 2 - Polarity Select for Wakeup Events for Pin 2. - 4 - 2 + BG_DIS + Bandgap OFF. This controls the System Bandgap in DeepSleep mode. + 11 + 1 - BOTH_EDGES - Both Edges. + on + Bandgap is always ON. 0 - RISING - Rising Edge. + off + Bandgap is OFF in DeepSleep mode (default). 1 - - FALLING - Falling Edge. - 2 - - 3 - Polarity Select for Wakeup Events for Pin 3. - 6 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - + LPWKFL_CLR + LP wakeup flag register clear. + 31 + 1 + + + + LPWKFL0 + Low Power I/O Wakeup Status Register 0. This register indicates the low power wakeup status for GPIO0. + 0x04 + - 4 - Polarity Select for Wakeup Events for Pin 4. - 8 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - + PINS + Wakeup Flags. + 0 + 12 + + + + LPWKEN0 + Low Power I/O Wakeup Enable Register 0. This register enables low power wakeup functionality for GPIO0. + 0x08 + - 5 - Polarity Select for Wakeup Events for Pin 5. - 10 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - + PINS + Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. + 0 + 12 + + + + LPWKFL1 + Low Power I/O Wakeup Status Register 1. This register indicates the low power wakeup status for GPIO1. + 0x0C + - 6 - Polarity Select for Wakeup Events for Pin 6. - 12 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - + PINS + Wakeup Flags. + 0 + 12 + + + + LPWKEN1 + Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup functionality for GPIO1. + 0x10 + - 7 - Polarity Select for Wakeup Events for Pin 7. - 14 + PINS + Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. + 0 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - + + LPPWST + Low Power Peripheral Wakeup Status Register. + 0x30 + + + RESET + Reset Detected Wakeup Flag. + 17 + 1 + + + + + GP0 + General Purpose Register 0 + 0x48 + + + GP1 + General Purpose Register 1 + 0x4C + @@ -9451,84 +4950,6 @@ - - BTLELDOTRIM - BTLE LDO Trim register. - 0x48 - read-write - - - TX - TX LDO trim value. - 0 - 5 - read-write - - - RX - RX LDO trim value. - 8 - 5 - read-write - - - - - FSTAT - funcstat register. - 0x100 - read-only - - - FPU - FPU Function. - 0 - 1 - - - no - 0 - - - yes - 1 - - - - - ADC - 10-bit Sigma Delta ADC. - 2 - 1 - - - no - 0 - - - yes - 1 - - - - - SEMA - Semaphore function. - 7 - 1 - - - no - 0 - - - yes - 1 - - - - - SFSTAT Security function status register. @@ -9536,42 +4957,16 @@ read-only - SECBOOT + SECBOOT_EN Security Boot. 0 1 - TRNG - TRNG Function. - 2 - 1 - - - no - 0 - - - yes - 1 - - - - - AES - AES Block. - 3 + SECEXT_EN + M33 SecExt Function Enable. + 1 1 - - - no - 0 - - - yes - 1 - - diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mcr_regs.h index 30a97da0147..1b30d94627d 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mcr_regs.h @@ -73,17 +73,13 @@ extern "C" { */ typedef struct { __IO uint32_t eccen; /**< \b 0x00: MCR ECCEN Register */ - __IO uint32_t ipotrim; /**< \b 0x04: MCR IPOTRIM Register */ + __R uint32_t rsv_0x4; __IO uint32_t outen; /**< \b 0x08: MCR OUTEN Register */ - __IO uint32_t cmp_ctrl; /**< \b 0x0C: MCR CMP_CTRL Register */ + __R uint32_t rsv_0xc; __IO uint32_t ctrl; /**< \b 0x10: MCR CTRL Register */ - __R uint32_t rsv_0x14; - __IO uint32_t rtcrst; /**< \b 0x18: MCR RTCRST Register */ - __IO uint32_t rtctrim; /**< \b 0x1C: MCR RTCTRIM Register */ - __IO uint32_t gpio3_ctrl; /**< \b 0x20: MCR GPIO3_CTRL Register */ - __R uint32_t rsv_0x24_0x5f[15]; - __IO uint32_t ldoctrl; /**< \b 0x60: MCR LDOCTRL Register */ - __IO uint32_t pwrmonst; /**< \b 0x64: MCR PWRMONST Register */ + __R uint32_t rsv_0x14_0x1f[3]; + __IO uint32_t gpio1_ctrl; /**< \b 0x20: MCR GPIO1_CTRL Register */ + __IO uint32_t rtctrim; /**< \b 0x24: MCR RTCTRIM Register */ } mxc_mcr_regs_t; /* Register offsets for module MCR */ @@ -94,15 +90,10 @@ typedef struct { * @{ */ #define MXC_R_MCR_ECCEN ((uint32_t)0x00000000UL) /**< Offset from MCR Base Address: 0x0000 */ -#define MXC_R_MCR_IPOTRIM ((uint32_t)0x00000004UL) /**< Offset from MCR Base Address: 0x0004 */ #define MXC_R_MCR_OUTEN ((uint32_t)0x00000008UL) /**< Offset from MCR Base Address: 0x0008 */ -#define MXC_R_MCR_CMP_CTRL ((uint32_t)0x0000000CUL) /**< Offset from MCR Base Address: 0x000C */ #define MXC_R_MCR_CTRL ((uint32_t)0x00000010UL) /**< Offset from MCR Base Address: 0x0010 */ -#define MXC_R_MCR_RTCRST ((uint32_t)0x00000018UL) /**< Offset from MCR Base Address: 0x0018 */ -#define MXC_R_MCR_RTCTRIM ((uint32_t)0x0000001CUL) /**< Offset from MCR Base Address: 0x001C */ -#define MXC_R_MCR_GPIO3_CTRL ((uint32_t)0x00000020UL) /**< Offset from MCR Base Address: 0x0020 */ -#define MXC_R_MCR_LDOCTRL ((uint32_t)0x00000060UL) /**< Offset from MCR Base Address: 0x0060 */ -#define MXC_R_MCR_PWRMONST ((uint32_t)0x00000064UL) /**< Offset from MCR Base Address: 0x0064 */ +#define MXC_R_MCR_GPIO1_CTRL ((uint32_t)0x00000020UL) /**< Offset from MCR Base Address: 0x0020 */ +#define MXC_R_MCR_RTCTRIM ((uint32_t)0x00000024UL) /**< Offset from MCR Base Address: 0x0024 */ /**@} end of group mcr_registers */ /** @@ -111,25 +102,11 @@ typedef struct { * @brief ECC Enable Register * @{ */ -#define MXC_F_MCR_ECCEN_RAM0_POS 0 /**< ECCEN_RAM0 Position */ -#define MXC_F_MCR_ECCEN_RAM0 ((uint32_t)(0x1UL << MXC_F_MCR_ECCEN_RAM0_POS)) /**< ECCEN_RAM0 Mask */ +#define MXC_F_MCR_ECCEN_FLASH_POS 0 /**< ECCEN_FLASH Position */ +#define MXC_F_MCR_ECCEN_FLASH ((uint32_t)(0x1UL << MXC_F_MCR_ECCEN_FLASH_POS)) /**< ECCEN_FLASH Mask */ /**@} end of group MCR_ECCEN_Register */ -/** - * @ingroup mcr_registers - * @defgroup MCR_IPOTRIM MCR_IPOTRIM - * @brief IPO Manual Trim Register - * @{ - */ -#define MXC_F_MCR_IPOTRIM_VAL_POS 0 /**< IPOTRIM_VAL Position */ -#define MXC_F_MCR_IPOTRIM_VAL ((uint32_t)(0xFFUL << MXC_F_MCR_IPOTRIM_VAL_POS)) /**< IPOTRIM_VAL Mask */ - -#define MXC_F_MCR_IPOTRIM_RANGE_POS 8 /**< IPOTRIM_RANGE Position */ -#define MXC_F_MCR_IPOTRIM_RANGE ((uint32_t)(0x1UL << MXC_F_MCR_IPOTRIM_RANGE_POS)) /**< IPOTRIM_RANGE Mask */ - -/**@} end of group MCR_IPOTRIM_Register */ - /** * @ingroup mcr_registers * @defgroup MCR_OUTEN MCR_OUTEN @@ -144,196 +121,65 @@ typedef struct { /**@} end of group MCR_OUTEN_Register */ -/** - * @ingroup mcr_registers - * @defgroup MCR_CMP_CTRL MCR_CMP_CTRL - * @brief Comparator Control Register. - * @{ - */ -#define MXC_F_MCR_CMP_CTRL_EN_POS 0 /**< CMP_CTRL_EN Position */ -#define MXC_F_MCR_CMP_CTRL_EN ((uint32_t)(0x1UL << MXC_F_MCR_CMP_CTRL_EN_POS)) /**< CMP_CTRL_EN Mask */ - -#define MXC_F_MCR_CMP_CTRL_POL_POS 5 /**< CMP_CTRL_POL Position */ -#define MXC_F_MCR_CMP_CTRL_POL ((uint32_t)(0x1UL << MXC_F_MCR_CMP_CTRL_POL_POS)) /**< CMP_CTRL_POL Mask */ - -#define MXC_F_MCR_CMP_CTRL_INTR_EN_POS 6 /**< CMP_CTRL_INTR_EN Position */ -#define MXC_F_MCR_CMP_CTRL_INTR_EN ((uint32_t)(0x1UL << MXC_F_MCR_CMP_CTRL_INTR_EN_POS)) /**< CMP_CTRL_INTR_EN Mask */ - -#define MXC_F_MCR_CMP_CTRL_OUT_POS 14 /**< CMP_CTRL_OUT Position */ -#define MXC_F_MCR_CMP_CTRL_OUT ((uint32_t)(0x1UL << MXC_F_MCR_CMP_CTRL_OUT_POS)) /**< CMP_CTRL_OUT Mask */ - -#define MXC_F_MCR_CMP_CTRL_INTR_FL_POS 15 /**< CMP_CTRL_INTR_FL Position */ -#define MXC_F_MCR_CMP_CTRL_INTR_FL ((uint32_t)(0x1UL << MXC_F_MCR_CMP_CTRL_INTR_FL_POS)) /**< CMP_CTRL_INTR_FL Mask */ - -/**@} end of group MCR_CMP_CTRL_Register */ - /** * @ingroup mcr_registers * @defgroup MCR_CTRL MCR_CTRL * @brief Control Register * @{ */ -#define MXC_F_MCR_CTRL_CMP_HYST_POS 0 /**< CTRL_CMP_HYST Position */ -#define MXC_F_MCR_CTRL_CMP_HYST ((uint32_t)(0x3UL << MXC_F_MCR_CTRL_CMP_HYST_POS)) /**< CTRL_CMP_HYST Mask */ - -#define MXC_F_MCR_CTRL_INRO_EN_POS 2 /**< CTRL_INRO_EN Position */ -#define MXC_F_MCR_CTRL_INRO_EN ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_INRO_EN_POS)) /**< CTRL_INRO_EN Mask */ - #define MXC_F_MCR_CTRL_ERTCO_EN_POS 3 /**< CTRL_ERTCO_EN Position */ #define MXC_F_MCR_CTRL_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_ERTCO_EN_POS)) /**< CTRL_ERTCO_EN Mask */ -#define MXC_F_MCR_CTRL_IBRO_EN_POS 4 /**< CTRL_IBRO_EN Position */ -#define MXC_F_MCR_CTRL_IBRO_EN ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_IBRO_EN_POS)) /**< CTRL_IBRO_EN Mask */ - -#define MXC_F_MCR_CTRL_ERTCO_LP_EN_POS 5 /**< CTRL_ERTCO_LP_EN Position */ -#define MXC_F_MCR_CTRL_ERTCO_LP_EN ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_ERTCO_LP_EN_POS)) /**< CTRL_ERTCO_LP_EN Mask */ - -#define MXC_F_MCR_CTRL_PADPUP_RST_POS 9 /**< CTRL_PADPUP_RST Position */ -#define MXC_F_MCR_CTRL_PADPUP_RST ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_PADPUP_RST_POS)) /**< CTRL_PADPUP_RST Mask */ - -#define MXC_F_MCR_CTRL_PADVDDIOHSEL_RST_POS 10 /**< CTRL_PADVDDIOHSEL_RST Position */ -#define MXC_F_MCR_CTRL_PADVDDIOHSEL_RST ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_PADVDDIOHSEL_RST_POS)) /**< CTRL_PADVDDIOHSEL_RST Mask */ +#define MXC_F_MCR_CTRL_ERTCO_IN_EN_POS 5 /**< CTRL_ERTCO_IN_EN Position */ +#define MXC_F_MCR_CTRL_ERTCO_IN_EN ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_ERTCO_IN_EN_POS)) /**< CTRL_ERTCO_IN_EN Mask */ /**@} end of group MCR_CTRL_Register */ /** * @ingroup mcr_registers - * @defgroup MCR_RTCRST MCR_RTCRST - * @brief Reset Register. - * @{ - */ -#define MXC_F_MCR_RTCRST_RTC_POS 0 /**< RTCRST_RTC Position */ -#define MXC_F_MCR_RTCRST_RTC ((uint32_t)(0x1UL << MXC_F_MCR_RTCRST_RTC_POS)) /**< RTCRST_RTC Mask */ - -/**@} end of group MCR_RTCRST_Register */ - -/** - * @ingroup mcr_registers - * @defgroup MCR_RTCTRIM MCR_RTCTRIM - * @brief RTC Trim Register. - * @{ - */ -#define MXC_F_MCR_RTCTRIM_X1_POS 0 /**< RTCTRIM_X1 Position */ -#define MXC_F_MCR_RTCTRIM_X1 ((uint32_t)(0x1FUL << MXC_F_MCR_RTCTRIM_X1_POS)) /**< RTCTRIM_X1 Mask */ - -#define MXC_F_MCR_RTCTRIM_X2_POS 8 /**< RTCTRIM_X2 Position */ -#define MXC_F_MCR_RTCTRIM_X2 ((uint32_t)(0x1FUL << MXC_F_MCR_RTCTRIM_X2_POS)) /**< RTCTRIM_X2 Mask */ - -/**@} end of group MCR_RTCTRIM_Register */ - -/** - * @ingroup mcr_registers - * @defgroup MCR_GPIO3_CTRL MCR_GPIO3_CTRL - * @brief GPIO3 Pin Control Register. + * @defgroup MCR_GPIO1_CTRL MCR_GPIO1_CTRL + * @brief GPIO1 Pin Control Register. * @{ */ -#define MXC_F_MCR_GPIO3_CTRL_P30_OUT_POS 0 /**< GPIO3_CTRL_P30_OUT Position */ -#define MXC_F_MCR_GPIO3_CTRL_P30_OUT ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P30_OUT_POS)) /**< GPIO3_CTRL_P30_OUT Mask */ +#define MXC_F_MCR_GPIO1_CTRL_P1_0_OUT_POS 0 /**< GPIO1_CTRL_P1_0_OUT Position */ +#define MXC_F_MCR_GPIO1_CTRL_P1_0_OUT ((uint32_t)(0x1UL << MXC_F_MCR_GPIO1_CTRL_P1_0_OUT_POS)) /**< GPIO1_CTRL_P1_0_OUT Mask */ -#define MXC_F_MCR_GPIO3_CTRL_P30_OUTEN_POS 1 /**< GPIO3_CTRL_P30_OUTEN Position */ -#define MXC_F_MCR_GPIO3_CTRL_P30_OUTEN ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P30_OUTEN_POS)) /**< GPIO3_CTRL_P30_OUTEN Mask */ +#define MXC_F_MCR_GPIO1_CTRL_P1_0_OUTEN_POS 1 /**< GPIO1_CTRL_P1_0_OUTEN Position */ +#define MXC_F_MCR_GPIO1_CTRL_P1_0_OUTEN ((uint32_t)(0x1UL << MXC_F_MCR_GPIO1_CTRL_P1_0_OUTEN_POS)) /**< GPIO1_CTRL_P1_0_OUTEN Mask */ -#define MXC_F_MCR_GPIO3_CTRL_P30_PUPEN_POS 2 /**< GPIO3_CTRL_P30_PUPEN Position */ -#define MXC_F_MCR_GPIO3_CTRL_P30_PUPEN ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P30_PUPEN_POS)) /**< GPIO3_CTRL_P30_PUPEN Mask */ +#define MXC_F_MCR_GPIO1_CTRL_P1_0_PUPEN_POS 2 /**< GPIO1_CTRL_P1_0_PUPEN Position */ +#define MXC_F_MCR_GPIO1_CTRL_P1_0_PUPEN ((uint32_t)(0x1UL << MXC_F_MCR_GPIO1_CTRL_P1_0_PUPEN_POS)) /**< GPIO1_CTRL_P1_0_PUPEN Mask */ -#define MXC_F_MCR_GPIO3_CTRL_P30_IN_POS 3 /**< GPIO3_CTRL_P30_IN Position */ -#define MXC_F_MCR_GPIO3_CTRL_P30_IN ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P30_IN_POS)) /**< GPIO3_CTRL_P30_IN Mask */ +#define MXC_F_MCR_GPIO1_CTRL_P1_0_IN_POS 3 /**< GPIO1_CTRL_P1_0_IN Position */ +#define MXC_F_MCR_GPIO1_CTRL_P1_0_IN ((uint32_t)(0x1UL << MXC_F_MCR_GPIO1_CTRL_P1_0_IN_POS)) /**< GPIO1_CTRL_P1_0_IN Mask */ -#define MXC_F_MCR_GPIO3_CTRL_P31_OUT_POS 4 /**< GPIO3_CTRL_P31_OUT Position */ -#define MXC_F_MCR_GPIO3_CTRL_P31_OUT ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P31_OUT_POS)) /**< GPIO3_CTRL_P31_OUT Mask */ +#define MXC_F_MCR_GPIO1_CTRL_P1_1_OUT_POS 4 /**< GPIO1_CTRL_P1_1_OUT Position */ +#define MXC_F_MCR_GPIO1_CTRL_P1_1_OUT ((uint32_t)(0x1UL << MXC_F_MCR_GPIO1_CTRL_P1_1_OUT_POS)) /**< GPIO1_CTRL_P1_1_OUT Mask */ -#define MXC_F_MCR_GPIO3_CTRL_P31_OUTEN_POS 5 /**< GPIO3_CTRL_P31_OUTEN Position */ -#define MXC_F_MCR_GPIO3_CTRL_P31_OUTEN ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P31_OUTEN_POS)) /**< GPIO3_CTRL_P31_OUTEN Mask */ +#define MXC_F_MCR_GPIO1_CTRL_P1_1_OUTEN_POS 5 /**< GPIO1_CTRL_P1_1_OUTEN Position */ +#define MXC_F_MCR_GPIO1_CTRL_P1_1_OUTEN ((uint32_t)(0x1UL << MXC_F_MCR_GPIO1_CTRL_P1_1_OUTEN_POS)) /**< GPIO1_CTRL_P1_1_OUTEN Mask */ -#define MXC_F_MCR_GPIO3_CTRL_P31_PUPEN_POS 6 /**< GPIO3_CTRL_P31_PUPEN Position */ -#define MXC_F_MCR_GPIO3_CTRL_P31_PUPEN ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P31_PUPEN_POS)) /**< GPIO3_CTRL_P31_PUPEN Mask */ +#define MXC_F_MCR_GPIO1_CTRL_P1_1_PUPEN_POS 6 /**< GPIO1_CTRL_P1_1_PUPEN Position */ +#define MXC_F_MCR_GPIO1_CTRL_P1_1_PUPEN ((uint32_t)(0x1UL << MXC_F_MCR_GPIO1_CTRL_P1_1_PUPEN_POS)) /**< GPIO1_CTRL_P1_1_PUPEN Mask */ -#define MXC_F_MCR_GPIO3_CTRL_P31_IN_POS 7 /**< GPIO3_CTRL_P31_IN Position */ -#define MXC_F_MCR_GPIO3_CTRL_P31_IN ((uint32_t)(0x1UL << MXC_F_MCR_GPIO3_CTRL_P31_IN_POS)) /**< GPIO3_CTRL_P31_IN Mask */ +#define MXC_F_MCR_GPIO1_CTRL_P1_1_IN_POS 7 /**< GPIO1_CTRL_P1_1_IN Position */ +#define MXC_F_MCR_GPIO1_CTRL_P1_1_IN ((uint32_t)(0x1UL << MXC_F_MCR_GPIO1_CTRL_P1_1_IN_POS)) /**< GPIO1_CTRL_P1_1_IN Mask */ -/**@} end of group MCR_GPIO3_CTRL_Register */ +/**@} end of group MCR_GPIO1_CTRL_Register */ /** * @ingroup mcr_registers - * @defgroup MCR_LDOCTRL MCR_LDOCTRL - * @brief LDO Control Register. - * @{ - */ -#define MXC_F_MCR_LDOCTRL_0P9V_EN_POS 0 /**< LDOCTRL_0P9V_EN Position */ -#define MXC_F_MCR_LDOCTRL_0P9V_EN ((uint32_t)(0x1UL << MXC_F_MCR_LDOCTRL_0P9V_EN_POS)) /**< LDOCTRL_0P9V_EN Mask */ - -/**@} end of group MCR_LDOCTRL_Register */ - -/** - * @ingroup mcr_registers - * @defgroup MCR_PWRMONST MCR_PWRMONST - * @brief LDO Control Register. + * @defgroup MCR_RTCTRIM MCR_RTCTRIM + * @brief User RTC Trim Register. * @{ */ -#define MXC_F_MCR_PWRMONST_PORZ_VLOSS_POS 0 /**< PWRMONST_PORZ_VLOSS Position */ -#define MXC_F_MCR_PWRMONST_PORZ_VLOSS ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_PORZ_VLOSS_POS)) /**< PWRMONST_PORZ_VLOSS Mask */ - -#define MXC_F_MCR_PWRMONST_PORZ_VBAT_POS 1 /**< PWRMONST_PORZ_VBAT Position */ -#define MXC_F_MCR_PWRMONST_PORZ_VBAT ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_PORZ_VBAT_POS)) /**< PWRMONST_PORZ_VBAT Mask */ - -#define MXC_F_MCR_PWRMONST_PORZ_VBB_POS 2 /**< PWRMONST_PORZ_VBB Position */ -#define MXC_F_MCR_PWRMONST_PORZ_VBB ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_PORZ_VBB_POS)) /**< PWRMONST_PORZ_VBB Mask */ - -#define MXC_F_MCR_PWRMONST_PORZ_VDDCA_POS 4 /**< PWRMONST_PORZ_VDDCA Position */ -#define MXC_F_MCR_PWRMONST_PORZ_VDDCA ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_PORZ_VDDCA_POS)) /**< PWRMONST_PORZ_VDDCA Mask */ - -#define MXC_F_MCR_PWRMONST_PORZ_VDDCB_POS 5 /**< PWRMONST_PORZ_VDDCB Position */ -#define MXC_F_MCR_PWRMONST_PORZ_VDDCB ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_PORZ_VDDCB_POS)) /**< PWRMONST_PORZ_VDDCB Mask */ - -#define MXC_F_MCR_PWRMONST_PORZ_VDDA_POS 6 /**< PWRMONST_PORZ_VDDA Position */ -#define MXC_F_MCR_PWRMONST_PORZ_VDDA ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_PORZ_VDDA_POS)) /**< PWRMONST_PORZ_VDDA Mask */ - -#define MXC_F_MCR_PWRMONST_PORZ_VDDB_POS 7 /**< PWRMONST_PORZ_VDDB Position */ -#define MXC_F_MCR_PWRMONST_PORZ_VDDB ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_PORZ_VDDB_POS)) /**< PWRMONST_PORZ_VDDB Mask */ - -#define MXC_F_MCR_PWRMONST_RSTZ_VDDCB_POS 9 /**< PWRMONST_RSTZ_VDDCB Position */ -#define MXC_F_MCR_PWRMONST_RSTZ_VDDCB ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VDDCB_POS)) /**< PWRMONST_RSTZ_VDDCB Mask */ - -#define MXC_F_MCR_PWRMONST_RSTZ_VDDA_POS 10 /**< PWRMONST_RSTZ_VDDA Position */ -#define MXC_F_MCR_PWRMONST_RSTZ_VDDA ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VDDA_POS)) /**< PWRMONST_RSTZ_VDDA Mask */ - -#define MXC_F_MCR_PWRMONST_RSTZ_VDDB_POS 11 /**< PWRMONST_RSTZ_VDDB Position */ -#define MXC_F_MCR_PWRMONST_RSTZ_VDDB ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VDDB_POS)) /**< PWRMONST_RSTZ_VDDB Mask */ - -#define MXC_F_MCR_PWRMONST_RSTZ_VDDIO_POS 12 /**< PWRMONST_RSTZ_VDDIO Position */ -#define MXC_F_MCR_PWRMONST_RSTZ_VDDIO ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VDDIO_POS)) /**< PWRMONST_RSTZ_VDDIO Mask */ - -#define MXC_F_MCR_PWRMONST_RSTZ_VDDIOH_POS 13 /**< PWRMONST_RSTZ_VDDIOH Position */ -#define MXC_F_MCR_PWRMONST_RSTZ_VDDIOH ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VDDIOH_POS)) /**< PWRMONST_RSTZ_VDDIOH Mask */ - -#define MXC_F_MCR_PWRMONST_RSTZ_VBB_POS 14 /**< PWRMONST_RSTZ_VBB Position */ -#define MXC_F_MCR_PWRMONST_RSTZ_VBB ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VBB_POS)) /**< PWRMONST_RSTZ_VBB Mask */ - -#define MXC_F_MCR_PWRMONST_RSTZ_LDO0P9V_POS 16 /**< PWRMONST_RSTZ_LDO0P9V Position */ -#define MXC_F_MCR_PWRMONST_RSTZ_LDO0P9V ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_LDO0P9V_POS)) /**< PWRMONST_RSTZ_LDO0P9V Mask */ - -#define MXC_F_MCR_PWRMONST_RSTZ_VDDCA_POS 17 /**< PWRMONST_RSTZ_VDDCA Position */ -#define MXC_F_MCR_PWRMONST_RSTZ_VDDCA ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VDDCA_POS)) /**< PWRMONST_RSTZ_VDDCA Mask */ - -#define MXC_F_MCR_PWRMONST_RSTZ_VCOREHV_POS 18 /**< PWRMONST_RSTZ_VCOREHV Position */ -#define MXC_F_MCR_PWRMONST_RSTZ_VCOREHV ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VCOREHV_POS)) /**< PWRMONST_RSTZ_VCOREHV Mask */ - -#define MXC_F_MCR_PWRMONST_RSTZ_VDDIOHV_POS 19 /**< PWRMONST_RSTZ_VDDIOHV Position */ -#define MXC_F_MCR_PWRMONST_RSTZ_VDDIOHV ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VDDIOHV_POS)) /**< PWRMONST_RSTZ_VDDIOHV Mask */ - -#define MXC_F_MCR_PWRMONST_RSTZ_VDDIOHHV_POS 20 /**< PWRMONST_RSTZ_VDDIOHHV Position */ -#define MXC_F_MCR_PWRMONST_RSTZ_VDDIOHHV ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VDDIOHHV_POS)) /**< PWRMONST_RSTZ_VDDIOHHV Mask */ - -#define MXC_F_MCR_PWRMONST_RSTZ_VNFCRX_POS 21 /**< PWRMONST_RSTZ_VNFCRX Position */ -#define MXC_F_MCR_PWRMONST_RSTZ_VNFCRX ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VNFCRX_POS)) /**< PWRMONST_RSTZ_VNFCRX Mask */ - -#define MXC_F_MCR_PWRMONST_RSTZ_VNFCTX_POS 22 /**< PWRMONST_RSTZ_VNFCTX Position */ -#define MXC_F_MCR_PWRMONST_RSTZ_VNFCTX ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VNFCTX_POS)) /**< PWRMONST_RSTZ_VNFCTX Mask */ +#define MXC_F_MCR_RTCTRIM_X2_POS 0 /**< RTCTRIM_X2 Position */ +#define MXC_F_MCR_RTCTRIM_X2 ((uint32_t)(0x1FUL << MXC_F_MCR_RTCTRIM_X2_POS)) /**< RTCTRIM_X2 Mask */ -#define MXC_F_MCR_PWRMONST_RSTZ_VNFC1V_POS 23 /**< PWRMONST_RSTZ_VNFC1V Position */ -#define MXC_F_MCR_PWRMONST_RSTZ_VNFC1V ((uint32_t)(0x1UL << MXC_F_MCR_PWRMONST_RSTZ_VNFC1V_POS)) /**< PWRMONST_RSTZ_VNFC1V Mask */ +#define MXC_F_MCR_RTCTRIM_X1_POS 5 /**< RTCTRIM_X1 Position */ +#define MXC_F_MCR_RTCTRIM_X1 ((uint32_t)(0x1FUL << MXC_F_MCR_RTCTRIM_X1_POS)) /**< RTCTRIM_X1 Mask */ -/**@} end of group MCR_PWRMONST_Register */ +/**@} end of group MCR_RTCTRIM_Register */ #ifdef __cplusplus } diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/pwrseq_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/pwrseq_regs.h index 77b5a1a141d..d09bcc8d6f9 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/pwrseq_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/pwrseq_regs.h @@ -77,25 +77,11 @@ typedef struct { __IO uint32_t lpwken0; /**< \b 0x08: PWRSEQ LPWKEN0 Register */ __IO uint32_t lpwkfl1; /**< \b 0x0C: PWRSEQ LPWKFL1 Register */ __IO uint32_t lpwken1; /**< \b 0x10: PWRSEQ LPWKEN1 Register */ - __IO uint32_t lpwkfl2; /**< \b 0x14: PWRSEQ LPWKFL2 Register */ - __IO uint32_t lpwken2; /**< \b 0x18: PWRSEQ LPWKEN2 Register */ - __IO uint32_t lpwkfl3; /**< \b 0x1C: PWRSEQ LPWKFL3 Register */ - __IO uint32_t lpwken3; /**< \b 0x20: PWRSEQ LPWKEN3 Register */ - __R uint32_t rsv_0x24_0x2f[3]; - __IO uint32_t lppwkfl; /**< \b 0x30: PWRSEQ LPPWKFL Register */ - __IO uint32_t lppwken; /**< \b 0x34: PWRSEQ LPPWKEN Register */ - __R uint32_t rsv_0x38_0x3f[2]; - __IO uint32_t lpmemsd; /**< \b 0x40: PWRSEQ LPMEMSD Register */ - __IO uint32_t lpvddpd; /**< \b 0x44: PWRSEQ LPVDDPD Register */ + __R uint32_t rsv_0x14_0x2f[7]; + __IO uint32_t lppwst; /**< \b 0x30: PWRSEQ LPPWST Register */ + __R uint32_t rsv_0x34_0x47[5]; __IO uint32_t gp0; /**< \b 0x48: PWRSEQ GP0 Register */ __IO uint32_t gp1; /**< \b 0x4C: PWRSEQ GP1 Register */ - __IO uint32_t lpwkpol0a; /**< \b 0x50: PWRSEQ LPWKPOL0A Register */ - __IO uint32_t lpwkpol0b; /**< \b 0x54: PWRSEQ LPWKPOL0B Register */ - __IO uint32_t lpwkpol1a; /**< \b 0x58: PWRSEQ LPWKPOL1A Register */ - __IO uint32_t lpwkpol1b; /**< \b 0x5C: PWRSEQ LPWKPOL1B Register */ - __IO uint32_t lpwkpol2a; /**< \b 0x60: PWRSEQ LPWKPOL2A Register */ - __IO uint32_t lpwkpol2b; /**< \b 0x64: PWRSEQ LPWKPOL2B Register */ - __IO uint32_t lpwkpol3; /**< \b 0x68: PWRSEQ LPWKPOL3 Register */ } mxc_pwrseq_regs_t; /* Register offsets for module PWRSEQ */ @@ -110,23 +96,9 @@ typedef struct { #define MXC_R_PWRSEQ_LPWKEN0 ((uint32_t)0x00000008UL) /**< Offset from PWRSEQ Base Address: 0x0008 */ #define MXC_R_PWRSEQ_LPWKFL1 ((uint32_t)0x0000000CUL) /**< Offset from PWRSEQ Base Address: 0x000C */ #define MXC_R_PWRSEQ_LPWKEN1 ((uint32_t)0x00000010UL) /**< Offset from PWRSEQ Base Address: 0x0010 */ -#define MXC_R_PWRSEQ_LPWKFL2 ((uint32_t)0x00000014UL) /**< Offset from PWRSEQ Base Address: 0x0014 */ -#define MXC_R_PWRSEQ_LPWKEN2 ((uint32_t)0x00000018UL) /**< Offset from PWRSEQ Base Address: 0x0018 */ -#define MXC_R_PWRSEQ_LPWKFL3 ((uint32_t)0x0000001CUL) /**< Offset from PWRSEQ Base Address: 0x001C */ -#define MXC_R_PWRSEQ_LPWKEN3 ((uint32_t)0x00000020UL) /**< Offset from PWRSEQ Base Address: 0x0020 */ -#define MXC_R_PWRSEQ_LPPWKFL ((uint32_t)0x00000030UL) /**< Offset from PWRSEQ Base Address: 0x0030 */ -#define MXC_R_PWRSEQ_LPPWKEN ((uint32_t)0x00000034UL) /**< Offset from PWRSEQ Base Address: 0x0034 */ -#define MXC_R_PWRSEQ_LPMEMSD ((uint32_t)0x00000040UL) /**< Offset from PWRSEQ Base Address: 0x0040 */ -#define MXC_R_PWRSEQ_LPVDDPD ((uint32_t)0x00000044UL) /**< Offset from PWRSEQ Base Address: 0x0044 */ +#define MXC_R_PWRSEQ_LPPWST ((uint32_t)0x00000030UL) /**< Offset from PWRSEQ Base Address: 0x0030 */ #define MXC_R_PWRSEQ_GP0 ((uint32_t)0x00000048UL) /**< Offset from PWRSEQ Base Address: 0x0048 */ #define MXC_R_PWRSEQ_GP1 ((uint32_t)0x0000004CUL) /**< Offset from PWRSEQ Base Address: 0x004C */ -#define MXC_R_PWRSEQ_LPWKPOL0A ((uint32_t)0x00000050UL) /**< Offset from PWRSEQ Base Address: 0x0050 */ -#define MXC_R_PWRSEQ_LPWKPOL0B ((uint32_t)0x00000054UL) /**< Offset from PWRSEQ Base Address: 0x0054 */ -#define MXC_R_PWRSEQ_LPWKPOL1A ((uint32_t)0x00000058UL) /**< Offset from PWRSEQ Base Address: 0x0058 */ -#define MXC_R_PWRSEQ_LPWKPOL1B ((uint32_t)0x0000005CUL) /**< Offset from PWRSEQ Base Address: 0x005C */ -#define MXC_R_PWRSEQ_LPWKPOL2A ((uint32_t)0x00000060UL) /**< Offset from PWRSEQ Base Address: 0x0060 */ -#define MXC_R_PWRSEQ_LPWKPOL2B ((uint32_t)0x00000064UL) /**< Offset from PWRSEQ Base Address: 0x0064 */ -#define MXC_R_PWRSEQ_LPWKPOL3 ((uint32_t)0x00000068UL) /**< Offset from PWRSEQ Base Address: 0x0068 */ /**@} end of group pwrseq_registers */ /** @@ -136,51 +108,16 @@ typedef struct { * @{ */ #define MXC_F_PWRSEQ_LPCTRL_RAMRET_EN_POS 0 /**< LPCTRL_RAMRET_EN Position */ -#define MXC_F_PWRSEQ_LPCTRL_RAMRET_EN ((uint32_t)(0xFUL << MXC_F_PWRSEQ_LPCTRL_RAMRET_EN_POS)) /**< LPCTRL_RAMRET_EN Mask */ +#define MXC_F_PWRSEQ_LPCTRL_RAMRET_EN ((uint32_t)(0x1FUL << MXC_F_PWRSEQ_LPCTRL_RAMRET_EN_POS)) /**< LPCTRL_RAMRET_EN Mask */ -#define MXC_F_PWRSEQ_LPCTRL_OVR_POS 4 /**< LPCTRL_OVR Position */ -#define MXC_F_PWRSEQ_LPCTRL_OVR ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPCTRL_OVR_POS)) /**< LPCTRL_OVR Mask */ -#define MXC_V_PWRSEQ_LPCTRL_OVR_1_1V ((uint32_t)0x2UL) /**< LPCTRL_OVR_1_1V Value */ -#define MXC_S_PWRSEQ_LPCTRL_OVR_1_1V (MXC_V_PWRSEQ_LPCTRL_OVR_1_1V << MXC_F_PWRSEQ_LPCTRL_OVR_POS) /**< LPCTRL_OVR_1_1V Setting */ - -#define MXC_F_PWRSEQ_LPCTRL_RETREG_EN_POS 8 /**< LPCTRL_RETREG_EN Position */ -#define MXC_F_PWRSEQ_LPCTRL_RETREG_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_RETREG_EN_POS)) /**< LPCTRL_RETREG_EN Mask */ - -#define MXC_F_PWRSEQ_LPCTRL_FASTWK_EN_POS 10 /**< LPCTRL_FASTWK_EN Position */ -#define MXC_F_PWRSEQ_LPCTRL_FASTWK_EN ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_FASTWK_EN_POS)) /**< LPCTRL_FASTWK_EN Mask */ +#define MXC_F_PWRSEQ_LPCTRL_FAST_POS 8 /**< LPCTRL_FAST Position */ +#define MXC_F_PWRSEQ_LPCTRL_FAST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_FAST_POS)) /**< LPCTRL_FAST Mask */ #define MXC_F_PWRSEQ_LPCTRL_BG_DIS_POS 11 /**< LPCTRL_BG_DIS Position */ #define MXC_F_PWRSEQ_LPCTRL_BG_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_BG_DIS_POS)) /**< LPCTRL_BG_DIS Mask */ -#define MXC_F_PWRSEQ_LPCTRL_PORVDDCMON_DIS_POS 12 /**< LPCTRL_PORVDDCMON_DIS Position */ -#define MXC_F_PWRSEQ_LPCTRL_PORVDDCMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_PORVDDCMON_DIS_POS)) /**< LPCTRL_PORVDDCMON_DIS Mask */ - -#define MXC_F_PWRSEQ_LPCTRL_VDDIOHHVMON_DIS_POS 17 /**< LPCTRL_VDDIOHHVMON_DIS Position */ -#define MXC_F_PWRSEQ_LPCTRL_VDDIOHHVMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VDDIOHHVMON_DIS_POS)) /**< LPCTRL_VDDIOHHVMON_DIS Mask */ - -#define MXC_F_PWRSEQ_LPCTRL_VDDIOHVMON_DIS_POS 18 /**< LPCTRL_VDDIOHVMON_DIS Position */ -#define MXC_F_PWRSEQ_LPCTRL_VDDIOHVMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VDDIOHVMON_DIS_POS)) /**< LPCTRL_VDDIOHVMON_DIS Mask */ - -#define MXC_F_PWRSEQ_LPCTRL_VCOREHVMON_DIS_POS 19 /**< LPCTRL_VCOREHVMON_DIS Position */ -#define MXC_F_PWRSEQ_LPCTRL_VCOREHVMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VCOREHVMON_DIS_POS)) /**< LPCTRL_VCOREHVMON_DIS Mask */ - -#define MXC_F_PWRSEQ_LPCTRL_VDDCMON_DIS_POS 20 /**< LPCTRL_VDDCMON_DIS Position */ -#define MXC_F_PWRSEQ_LPCTRL_VDDCMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VDDCMON_DIS_POS)) /**< LPCTRL_VDDCMON_DIS Mask */ - -#define MXC_F_PWRSEQ_LPCTRL_VRTCMON_DIS_POS 21 /**< LPCTRL_VRTCMON_DIS Position */ -#define MXC_F_PWRSEQ_LPCTRL_VRTCMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VRTCMON_DIS_POS)) /**< LPCTRL_VRTCMON_DIS Mask */ - -#define MXC_F_PWRSEQ_LPCTRL_VDDAMON_DIS_POS 22 /**< LPCTRL_VDDAMON_DIS Position */ -#define MXC_F_PWRSEQ_LPCTRL_VDDAMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VDDAMON_DIS_POS)) /**< LPCTRL_VDDAMON_DIS Mask */ - -#define MXC_F_PWRSEQ_LPCTRL_VDDIOMON_DIS_POS 23 /**< LPCTRL_VDDIOMON_DIS Position */ -#define MXC_F_PWRSEQ_LPCTRL_VDDIOMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VDDIOMON_DIS_POS)) /**< LPCTRL_VDDIOMON_DIS Mask */ - -#define MXC_F_PWRSEQ_LPCTRL_VDDIOHMON_DIS_POS 24 /**< LPCTRL_VDDIOHMON_DIS Position */ -#define MXC_F_PWRSEQ_LPCTRL_VDDIOHMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VDDIOHMON_DIS_POS)) /**< LPCTRL_VDDIOHMON_DIS Mask */ - -#define MXC_F_PWRSEQ_LPCTRL_VDDBMON_DIS_POS 27 /**< LPCTRL_VDDBMON_DIS Position */ -#define MXC_F_PWRSEQ_LPCTRL_VDDBMON_DIS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_VDDBMON_DIS_POS)) /**< LPCTRL_VDDBMON_DIS Mask */ +#define MXC_F_PWRSEQ_LPCTRL_LPWKFL_CLR_POS 31 /**< LPCTRL_LPWKFL_CLR Position */ +#define MXC_F_PWRSEQ_LPCTRL_LPWKFL_CLR ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_LPWKFL_CLR_POS)) /**< LPCTRL_LPWKFL_CLR Mask */ /**@} end of group PWRSEQ_LPCTRL_Register */ @@ -191,8 +128,8 @@ typedef struct { * wakeup status for GPIO0. * @{ */ -#define MXC_F_PWRSEQ_LPWKFL0_ALL_POS 0 /**< LPWKFL0_ALL Position */ -#define MXC_F_PWRSEQ_LPWKFL0_ALL ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRSEQ_LPWKFL0_ALL_POS)) /**< LPWKFL0_ALL Mask */ +#define MXC_F_PWRSEQ_LPWKFL0_PINS_POS 0 /**< LPWKFL0_PINS Position */ +#define MXC_F_PWRSEQ_LPWKFL0_PINS ((uint32_t)(0xFFFUL << MXC_F_PWRSEQ_LPWKFL0_PINS_POS)) /**< LPWKFL0_PINS Mask */ /**@} end of group PWRSEQ_LPWKFL0_Register */ @@ -203,1157 +140,45 @@ typedef struct { * functionality for GPIO0. * @{ */ -#define MXC_F_PWRSEQ_LPWKEN0_ALL_POS 0 /**< LPWKEN0_ALL Position */ -#define MXC_F_PWRSEQ_LPWKEN0_ALL ((uint32_t)(0x7FFFFFFFUL << MXC_F_PWRSEQ_LPWKEN0_ALL_POS)) /**< LPWKEN0_ALL Mask */ +#define MXC_F_PWRSEQ_LPWKEN0_PINS_POS 0 /**< LPWKEN0_PINS Position */ +#define MXC_F_PWRSEQ_LPWKEN0_PINS ((uint32_t)(0xFFFUL << MXC_F_PWRSEQ_LPWKEN0_PINS_POS)) /**< LPWKEN0_PINS Mask */ /**@} end of group PWRSEQ_LPWKEN0_Register */ /** * @ingroup pwrseq_registers - * @defgroup PWRSEQ_LPPWKFL PWRSEQ_LPPWKFL - * @brief Low Power Peripheral Wakeup Status Register. - * @{ - */ -#define MXC_F_PWRSEQ_LPPWKFL_USBLS_POS 0 /**< LPPWKFL_USBLS Position */ -#define MXC_F_PWRSEQ_LPPWKFL_USBLS ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPPWKFL_USBLS_POS)) /**< LPPWKFL_USBLS Mask */ - -#define MXC_F_PWRSEQ_LPPWKFL_AINCOMP0_POS 4 /**< LPPWKFL_AINCOMP0 Position */ -#define MXC_F_PWRSEQ_LPPWKFL_AINCOMP0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKFL_AINCOMP0_POS)) /**< LPPWKFL_AINCOMP0 Mask */ - -#define MXC_F_PWRSEQ_LPPWKFL_USBVBUS_POS 2 /**< LPPWKFL_USBVBUS Position */ -#define MXC_F_PWRSEQ_LPPWKFL_USBVBUS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKFL_USBVBUS_POS)) /**< LPPWKFL_USBVBUS Mask */ - -#define MXC_F_PWRSEQ_LPPWKFL_BACKUP_POS 16 /**< LPPWKFL_BACKUP Position */ -#define MXC_F_PWRSEQ_LPPWKFL_BACKUP ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKFL_BACKUP_POS)) /**< LPPWKFL_BACKUP Mask */ - -#define MXC_F_PWRSEQ_LPPWKFL_RSTDET_POS 17 /**< LPPWKFL_RSTDET Position */ -#define MXC_F_PWRSEQ_LPPWKFL_RSTDET ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKFL_RSTDET_POS)) /**< LPPWKFL_RSTDET Mask */ - -/**@} end of group PWRSEQ_LPPWKFL_Register */ - -/** - * @ingroup pwrseq_registers - * @defgroup PWRSEQ_LPPWKEN PWRSEQ_LPPWKEN - * @brief Low Power Peripheral Wakeup Enable Register. - * @{ - */ -#define MXC_F_PWRSEQ_LPPWKEN_USBLS_POS 0 /**< LPPWKEN_USBLS Position */ -#define MXC_F_PWRSEQ_LPPWKEN_USBLS ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPPWKEN_USBLS_POS)) /**< LPPWKEN_USBLS Mask */ - -#define MXC_F_PWRSEQ_LPPWKEN_USBVBUS_POS 2 /**< LPPWKEN_USBVBUS Position */ -#define MXC_F_PWRSEQ_LPPWKEN_USBVBUS ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_USBVBUS_POS)) /**< LPPWKEN_USBVBUS Mask */ - -#define MXC_F_PWRSEQ_LPPWKEN_AINCOMP0_POS 4 /**< LPPWKEN_AINCOMP0 Position */ -#define MXC_F_PWRSEQ_LPPWKEN_AINCOMP0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_AINCOMP0_POS)) /**< LPPWKEN_AINCOMP0 Mask */ - -#define MXC_F_PWRSEQ_LPPWKEN_WDT0_POS 8 /**< LPPWKEN_WDT0 Position */ -#define MXC_F_PWRSEQ_LPPWKEN_WDT0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_WDT0_POS)) /**< LPPWKEN_WDT0 Mask */ - -#define MXC_F_PWRSEQ_LPPWKEN_WDT1_POS 9 /**< LPPWKEN_WDT1 Position */ -#define MXC_F_PWRSEQ_LPPWKEN_WDT1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_WDT1_POS)) /**< LPPWKEN_WDT1 Mask */ - -#define MXC_F_PWRSEQ_LPPWKEN_CPU1_POS 10 /**< LPPWKEN_CPU1 Position */ -#define MXC_F_PWRSEQ_LPPWKEN_CPU1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_CPU1_POS)) /**< LPPWKEN_CPU1 Mask */ - -#define MXC_F_PWRSEQ_LPPWKEN_TMR0_POS 11 /**< LPPWKEN_TMR0 Position */ -#define MXC_F_PWRSEQ_LPPWKEN_TMR0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_TMR0_POS)) /**< LPPWKEN_TMR0 Mask */ - -#define MXC_F_PWRSEQ_LPPWKEN_TMR1_POS 12 /**< LPPWKEN_TMR1 Position */ -#define MXC_F_PWRSEQ_LPPWKEN_TMR1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_TMR1_POS)) /**< LPPWKEN_TMR1 Mask */ - -#define MXC_F_PWRSEQ_LPPWKEN_TMR2_POS 13 /**< LPPWKEN_TMR2 Position */ -#define MXC_F_PWRSEQ_LPPWKEN_TMR2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_TMR2_POS)) /**< LPPWKEN_TMR2 Mask */ - -#define MXC_F_PWRSEQ_LPPWKEN_TMR3_POS 14 /**< LPPWKEN_TMR3 Position */ -#define MXC_F_PWRSEQ_LPPWKEN_TMR3 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_TMR3_POS)) /**< LPPWKEN_TMR3 Mask */ - -#define MXC_F_PWRSEQ_LPPWKEN_TMR4_POS 15 /**< LPPWKEN_TMR4 Position */ -#define MXC_F_PWRSEQ_LPPWKEN_TMR4 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_TMR4_POS)) /**< LPPWKEN_TMR4 Mask */ - -#define MXC_F_PWRSEQ_LPPWKEN_TMR5_POS 16 /**< LPPWKEN_TMR5 Position */ -#define MXC_F_PWRSEQ_LPPWKEN_TMR5 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_TMR5_POS)) /**< LPPWKEN_TMR5 Mask */ - -#define MXC_F_PWRSEQ_LPPWKEN_UART0_POS 17 /**< LPPWKEN_UART0 Position */ -#define MXC_F_PWRSEQ_LPPWKEN_UART0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_UART0_POS)) /**< LPPWKEN_UART0 Mask */ - -#define MXC_F_PWRSEQ_LPPWKEN_UART1_POS 18 /**< LPPWKEN_UART1 Position */ -#define MXC_F_PWRSEQ_LPPWKEN_UART1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_UART1_POS)) /**< LPPWKEN_UART1 Mask */ - -#define MXC_F_PWRSEQ_LPPWKEN_UART2_POS 19 /**< LPPWKEN_UART2 Position */ -#define MXC_F_PWRSEQ_LPPWKEN_UART2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_UART2_POS)) /**< LPPWKEN_UART2 Mask */ - -#define MXC_F_PWRSEQ_LPPWKEN_UART3_POS 20 /**< LPPWKEN_UART3 Position */ -#define MXC_F_PWRSEQ_LPPWKEN_UART3 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_UART3_POS)) /**< LPPWKEN_UART3 Mask */ - -#define MXC_F_PWRSEQ_LPPWKEN_I2C0_POS 21 /**< LPPWKEN_I2C0 Position */ -#define MXC_F_PWRSEQ_LPPWKEN_I2C0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_I2C0_POS)) /**< LPPWKEN_I2C0 Mask */ - -#define MXC_F_PWRSEQ_LPPWKEN_I2C1_POS 22 /**< LPPWKEN_I2C1 Position */ -#define MXC_F_PWRSEQ_LPPWKEN_I2C1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_I2C1_POS)) /**< LPPWKEN_I2C1 Mask */ - -#define MXC_F_PWRSEQ_LPPWKEN_I2C2_POS 23 /**< LPPWKEN_I2C2 Position */ -#define MXC_F_PWRSEQ_LPPWKEN_I2C2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_I2C2_POS)) /**< LPPWKEN_I2C2 Mask */ - -#define MXC_F_PWRSEQ_LPPWKEN_I2S_POS 24 /**< LPPWKEN_I2S Position */ -#define MXC_F_PWRSEQ_LPPWKEN_I2S ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_I2S_POS)) /**< LPPWKEN_I2S Mask */ - -#define MXC_F_PWRSEQ_LPPWKEN_SPI1_POS 25 /**< LPPWKEN_SPI1 Position */ -#define MXC_F_PWRSEQ_LPPWKEN_SPI1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_SPI1_POS)) /**< LPPWKEN_SPI1 Mask */ - -#define MXC_F_PWRSEQ_LPPWKEN_LPCMP_POS 26 /**< LPPWKEN_LPCMP Position */ -#define MXC_F_PWRSEQ_LPPWKEN_LPCMP ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWKEN_LPCMP_POS)) /**< LPPWKEN_LPCMP Mask */ - -/**@} end of group PWRSEQ_LPPWKEN_Register */ - -/** - * @ingroup pwrseq_registers - * @defgroup PWRSEQ_LPMEMSD PWRSEQ_LPMEMSD - * @brief Low Power Memory Shutdown Control. + * @defgroup PWRSEQ_LPWKFL1 PWRSEQ_LPWKFL1 + * @brief Low Power I/O Wakeup Status Register 1. This register indicates the low power + * wakeup status for GPIO1. * @{ */ -#define MXC_F_PWRSEQ_LPMEMSD_RAM0_POS 0 /**< LPMEMSD_RAM0 Position */ -#define MXC_F_PWRSEQ_LPMEMSD_RAM0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM0_POS)) /**< LPMEMSD_RAM0 Mask */ +#define MXC_F_PWRSEQ_LPWKFL1_PINS_POS 0 /**< LPWKFL1_PINS Position */ +#define MXC_F_PWRSEQ_LPWKFL1_PINS ((uint32_t)(0xFFFUL << MXC_F_PWRSEQ_LPWKFL1_PINS_POS)) /**< LPWKFL1_PINS Mask */ -#define MXC_F_PWRSEQ_LPMEMSD_RAM1_POS 1 /**< LPMEMSD_RAM1 Position */ -#define MXC_F_PWRSEQ_LPMEMSD_RAM1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM1_POS)) /**< LPMEMSD_RAM1 Mask */ - -#define MXC_F_PWRSEQ_LPMEMSD_RAM2_POS 2 /**< LPMEMSD_RAM2 Position */ -#define MXC_F_PWRSEQ_LPMEMSD_RAM2 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM2_POS)) /**< LPMEMSD_RAM2 Mask */ - -#define MXC_F_PWRSEQ_LPMEMSD_RAM3_POS 3 /**< LPMEMSD_RAM3 Position */ -#define MXC_F_PWRSEQ_LPMEMSD_RAM3 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM3_POS)) /**< LPMEMSD_RAM3 Mask */ - -#define MXC_F_PWRSEQ_LPMEMSD_RAM4_POS 4 /**< LPMEMSD_RAM4 Position */ -#define MXC_F_PWRSEQ_LPMEMSD_RAM4 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM4_POS)) /**< LPMEMSD_RAM4 Mask */ - -#define MXC_F_PWRSEQ_LPMEMSD_RAM5_POS 5 /**< LPMEMSD_RAM5 Position */ -#define MXC_F_PWRSEQ_LPMEMSD_RAM5 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_RAM5_POS)) /**< LPMEMSD_RAM5 Mask */ - -#define MXC_F_PWRSEQ_LPMEMSD_ICC_POS 7 /**< LPMEMSD_ICC Position */ -#define MXC_F_PWRSEQ_LPMEMSD_ICC ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ICC_POS)) /**< LPMEMSD_ICC Mask */ - -#define MXC_F_PWRSEQ_LPMEMSD_ICCXIP_POS 8 /**< LPMEMSD_ICCXIP Position */ -#define MXC_F_PWRSEQ_LPMEMSD_ICCXIP ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ICCXIP_POS)) /**< LPMEMSD_ICCXIP Mask */ - -#define MXC_F_PWRSEQ_LPMEMSD_SRCC_POS 9 /**< LPMEMSD_SRCC Position */ -#define MXC_F_PWRSEQ_LPMEMSD_SRCC ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_SRCC_POS)) /**< LPMEMSD_SRCC Mask */ - -#define MXC_F_PWRSEQ_LPMEMSD_USBFIFO_POS 11 /**< LPMEMSD_USBFIFO Position */ -#define MXC_F_PWRSEQ_LPMEMSD_USBFIFO ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_USBFIFO_POS)) /**< LPMEMSD_USBFIFO Mask */ - -#define MXC_F_PWRSEQ_LPMEMSD_ROM0_POS 12 /**< LPMEMSD_ROM0 Position */ -#define MXC_F_PWRSEQ_LPMEMSD_ROM0 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ROM0_POS)) /**< LPMEMSD_ROM0 Mask */ - -#define MXC_F_PWRSEQ_LPMEMSD_MEU_POS 13 /**< LPMEMSD_MEU Position */ -#define MXC_F_PWRSEQ_LPMEMSD_MEU ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_MEU_POS)) /**< LPMEMSD_MEU Mask */ - -#define MXC_F_PWRSEQ_LPMEMSD_ROM1_POS 15 /**< LPMEMSD_ROM1 Position */ -#define MXC_F_PWRSEQ_LPMEMSD_ROM1 ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPMEMSD_ROM1_POS)) /**< LPMEMSD_ROM1 Mask */ - -/**@} end of group PWRSEQ_LPMEMSD_Register */ +/**@} end of group PWRSEQ_LPWKFL1_Register */ /** * @ingroup pwrseq_registers - * @defgroup PWRSEQ_LPVDDPD PWRSEQ_LPVDDPD - * @brief Low Power VDD Domain Power Down Control. + * @defgroup PWRSEQ_LPWKEN1 PWRSEQ_LPWKEN1 + * @brief Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup + * functionality for GPIO1. * @{ */ -#define MXC_F_PWRSEQ_LPVDDPD_BTLE_POS 1 /**< LPVDDPD_BTLE Position */ -#define MXC_F_PWRSEQ_LPVDDPD_BTLE ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPVDDPD_BTLE_POS)) /**< LPVDDPD_BTLE Mask */ +#define MXC_F_PWRSEQ_LPWKEN1_PINS_POS 0 /**< LPWKEN1_PINS Position */ +#define MXC_F_PWRSEQ_LPWKEN1_PINS ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKEN1_PINS_POS)) /**< LPWKEN1_PINS Mask */ -/**@} end of group PWRSEQ_LPVDDPD_Register */ +/**@} end of group PWRSEQ_LPWKEN1_Register */ /** * @ingroup pwrseq_registers - * @defgroup PWRSEQ_LPWKPOL0A PWRSEQ_LPWKPOL0A - * @brief Low Power Wakeup Polarity Select for GPIO0. - * @{ - */ -#define MXC_F_PWRSEQ_LPWKPOL0A_0_POS 0 /**< LPWKPOL0A_0 Position */ -#define MXC_F_PWRSEQ_LPWKPOL0A_0 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0A_0_POS)) /**< LPWKPOL0A_0 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL0A_0_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0A_0_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_0_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0A_0_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0A_0_POS) /**< LPWKPOL0A_0_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0A_0_RISING ((uint32_t)0x1UL) /**< LPWKPOL0A_0_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_0_RISING (MXC_V_PWRSEQ_LPWKPOL0A_0_RISING << MXC_F_PWRSEQ_LPWKPOL0A_0_POS) /**< LPWKPOL0A_0_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0A_0_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0A_0_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_0_FALLING (MXC_V_PWRSEQ_LPWKPOL0A_0_FALLING << MXC_F_PWRSEQ_LPWKPOL0A_0_POS) /**< LPWKPOL0A_0_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL0A_1_POS 2 /**< LPWKPOL0A_1 Position */ -#define MXC_F_PWRSEQ_LPWKPOL0A_1 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0A_1_POS)) /**< LPWKPOL0A_1 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL0A_1_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0A_1_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_1_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0A_1_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0A_1_POS) /**< LPWKPOL0A_1_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0A_1_RISING ((uint32_t)0x1UL) /**< LPWKPOL0A_1_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_1_RISING (MXC_V_PWRSEQ_LPWKPOL0A_1_RISING << MXC_F_PWRSEQ_LPWKPOL0A_1_POS) /**< LPWKPOL0A_1_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0A_1_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0A_1_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_1_FALLING (MXC_V_PWRSEQ_LPWKPOL0A_1_FALLING << MXC_F_PWRSEQ_LPWKPOL0A_1_POS) /**< LPWKPOL0A_1_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL0A_2_POS 4 /**< LPWKPOL0A_2 Position */ -#define MXC_F_PWRSEQ_LPWKPOL0A_2 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0A_2_POS)) /**< LPWKPOL0A_2 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL0A_2_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0A_2_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_2_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0A_2_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0A_2_POS) /**< LPWKPOL0A_2_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0A_2_RISING ((uint32_t)0x1UL) /**< LPWKPOL0A_2_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_2_RISING (MXC_V_PWRSEQ_LPWKPOL0A_2_RISING << MXC_F_PWRSEQ_LPWKPOL0A_2_POS) /**< LPWKPOL0A_2_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0A_2_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0A_2_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_2_FALLING (MXC_V_PWRSEQ_LPWKPOL0A_2_FALLING << MXC_F_PWRSEQ_LPWKPOL0A_2_POS) /**< LPWKPOL0A_2_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL0A_3_POS 6 /**< LPWKPOL0A_3 Position */ -#define MXC_F_PWRSEQ_LPWKPOL0A_3 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0A_3_POS)) /**< LPWKPOL0A_3 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL0A_3_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0A_3_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_3_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0A_3_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0A_3_POS) /**< LPWKPOL0A_3_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0A_3_RISING ((uint32_t)0x1UL) /**< LPWKPOL0A_3_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_3_RISING (MXC_V_PWRSEQ_LPWKPOL0A_3_RISING << MXC_F_PWRSEQ_LPWKPOL0A_3_POS) /**< LPWKPOL0A_3_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0A_3_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0A_3_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_3_FALLING (MXC_V_PWRSEQ_LPWKPOL0A_3_FALLING << MXC_F_PWRSEQ_LPWKPOL0A_3_POS) /**< LPWKPOL0A_3_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL0A_4_POS 8 /**< LPWKPOL0A_4 Position */ -#define MXC_F_PWRSEQ_LPWKPOL0A_4 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0A_4_POS)) /**< LPWKPOL0A_4 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL0A_4_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0A_4_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_4_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0A_4_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0A_4_POS) /**< LPWKPOL0A_4_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0A_4_RISING ((uint32_t)0x1UL) /**< LPWKPOL0A_4_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_4_RISING (MXC_V_PWRSEQ_LPWKPOL0A_4_RISING << MXC_F_PWRSEQ_LPWKPOL0A_4_POS) /**< LPWKPOL0A_4_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0A_4_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0A_4_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_4_FALLING (MXC_V_PWRSEQ_LPWKPOL0A_4_FALLING << MXC_F_PWRSEQ_LPWKPOL0A_4_POS) /**< LPWKPOL0A_4_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL0A_5_POS 10 /**< LPWKPOL0A_5 Position */ -#define MXC_F_PWRSEQ_LPWKPOL0A_5 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0A_5_POS)) /**< LPWKPOL0A_5 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL0A_5_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0A_5_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_5_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0A_5_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0A_5_POS) /**< LPWKPOL0A_5_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0A_5_RISING ((uint32_t)0x1UL) /**< LPWKPOL0A_5_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_5_RISING (MXC_V_PWRSEQ_LPWKPOL0A_5_RISING << MXC_F_PWRSEQ_LPWKPOL0A_5_POS) /**< LPWKPOL0A_5_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0A_5_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0A_5_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_5_FALLING (MXC_V_PWRSEQ_LPWKPOL0A_5_FALLING << MXC_F_PWRSEQ_LPWKPOL0A_5_POS) /**< LPWKPOL0A_5_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL0A_6_POS 12 /**< LPWKPOL0A_6 Position */ -#define MXC_F_PWRSEQ_LPWKPOL0A_6 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0A_6_POS)) /**< LPWKPOL0A_6 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL0A_6_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0A_6_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_6_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0A_6_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0A_6_POS) /**< LPWKPOL0A_6_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0A_6_RISING ((uint32_t)0x1UL) /**< LPWKPOL0A_6_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_6_RISING (MXC_V_PWRSEQ_LPWKPOL0A_6_RISING << MXC_F_PWRSEQ_LPWKPOL0A_6_POS) /**< LPWKPOL0A_6_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0A_6_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0A_6_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_6_FALLING (MXC_V_PWRSEQ_LPWKPOL0A_6_FALLING << MXC_F_PWRSEQ_LPWKPOL0A_6_POS) /**< LPWKPOL0A_6_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL0A_7_POS 14 /**< LPWKPOL0A_7 Position */ -#define MXC_F_PWRSEQ_LPWKPOL0A_7 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0A_7_POS)) /**< LPWKPOL0A_7 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL0A_7_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0A_7_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_7_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0A_7_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0A_7_POS) /**< LPWKPOL0A_7_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0A_7_RISING ((uint32_t)0x1UL) /**< LPWKPOL0A_7_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_7_RISING (MXC_V_PWRSEQ_LPWKPOL0A_7_RISING << MXC_F_PWRSEQ_LPWKPOL0A_7_POS) /**< LPWKPOL0A_7_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0A_7_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0A_7_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_7_FALLING (MXC_V_PWRSEQ_LPWKPOL0A_7_FALLING << MXC_F_PWRSEQ_LPWKPOL0A_7_POS) /**< LPWKPOL0A_7_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL0A_8_POS 16 /**< LPWKPOL0A_8 Position */ -#define MXC_F_PWRSEQ_LPWKPOL0A_8 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0A_8_POS)) /**< LPWKPOL0A_8 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL0A_8_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0A_8_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_8_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0A_8_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0A_8_POS) /**< LPWKPOL0A_8_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0A_8_RISING ((uint32_t)0x1UL) /**< LPWKPOL0A_8_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_8_RISING (MXC_V_PWRSEQ_LPWKPOL0A_8_RISING << MXC_F_PWRSEQ_LPWKPOL0A_8_POS) /**< LPWKPOL0A_8_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0A_8_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0A_8_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_8_FALLING (MXC_V_PWRSEQ_LPWKPOL0A_8_FALLING << MXC_F_PWRSEQ_LPWKPOL0A_8_POS) /**< LPWKPOL0A_8_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL0A_9_POS 18 /**< LPWKPOL0A_9 Position */ -#define MXC_F_PWRSEQ_LPWKPOL0A_9 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0A_9_POS)) /**< LPWKPOL0A_9 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL0A_9_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0A_9_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_9_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0A_9_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0A_9_POS) /**< LPWKPOL0A_9_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0A_9_RISING ((uint32_t)0x1UL) /**< LPWKPOL0A_9_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_9_RISING (MXC_V_PWRSEQ_LPWKPOL0A_9_RISING << MXC_F_PWRSEQ_LPWKPOL0A_9_POS) /**< LPWKPOL0A_9_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0A_9_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0A_9_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_9_FALLING (MXC_V_PWRSEQ_LPWKPOL0A_9_FALLING << MXC_F_PWRSEQ_LPWKPOL0A_9_POS) /**< LPWKPOL0A_9_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL0A_10_POS 20 /**< LPWKPOL0A_10 Position */ -#define MXC_F_PWRSEQ_LPWKPOL0A_10 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0A_10_POS)) /**< LPWKPOL0A_10 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL0A_10_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0A_10_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_10_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0A_10_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0A_10_POS) /**< LPWKPOL0A_10_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0A_10_RISING ((uint32_t)0x1UL) /**< LPWKPOL0A_10_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_10_RISING (MXC_V_PWRSEQ_LPWKPOL0A_10_RISING << MXC_F_PWRSEQ_LPWKPOL0A_10_POS) /**< LPWKPOL0A_10_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0A_10_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0A_10_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_10_FALLING (MXC_V_PWRSEQ_LPWKPOL0A_10_FALLING << MXC_F_PWRSEQ_LPWKPOL0A_10_POS) /**< LPWKPOL0A_10_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL0A_11_POS 22 /**< LPWKPOL0A_11 Position */ -#define MXC_F_PWRSEQ_LPWKPOL0A_11 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0A_11_POS)) /**< LPWKPOL0A_11 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL0A_11_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0A_11_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_11_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0A_11_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0A_11_POS) /**< LPWKPOL0A_11_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0A_11_RISING ((uint32_t)0x1UL) /**< LPWKPOL0A_11_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_11_RISING (MXC_V_PWRSEQ_LPWKPOL0A_11_RISING << MXC_F_PWRSEQ_LPWKPOL0A_11_POS) /**< LPWKPOL0A_11_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0A_11_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0A_11_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_11_FALLING (MXC_V_PWRSEQ_LPWKPOL0A_11_FALLING << MXC_F_PWRSEQ_LPWKPOL0A_11_POS) /**< LPWKPOL0A_11_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL0A_12_POS 24 /**< LPWKPOL0A_12 Position */ -#define MXC_F_PWRSEQ_LPWKPOL0A_12 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0A_12_POS)) /**< LPWKPOL0A_12 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL0A_12_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0A_12_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_12_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0A_12_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0A_12_POS) /**< LPWKPOL0A_12_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0A_12_RISING ((uint32_t)0x1UL) /**< LPWKPOL0A_12_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_12_RISING (MXC_V_PWRSEQ_LPWKPOL0A_12_RISING << MXC_F_PWRSEQ_LPWKPOL0A_12_POS) /**< LPWKPOL0A_12_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0A_12_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0A_12_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_12_FALLING (MXC_V_PWRSEQ_LPWKPOL0A_12_FALLING << MXC_F_PWRSEQ_LPWKPOL0A_12_POS) /**< LPWKPOL0A_12_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL0A_13_POS 26 /**< LPWKPOL0A_13 Position */ -#define MXC_F_PWRSEQ_LPWKPOL0A_13 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0A_13_POS)) /**< LPWKPOL0A_13 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL0A_13_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0A_13_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_13_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0A_13_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0A_13_POS) /**< LPWKPOL0A_13_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0A_13_RISING ((uint32_t)0x1UL) /**< LPWKPOL0A_13_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_13_RISING (MXC_V_PWRSEQ_LPWKPOL0A_13_RISING << MXC_F_PWRSEQ_LPWKPOL0A_13_POS) /**< LPWKPOL0A_13_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0A_13_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0A_13_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_13_FALLING (MXC_V_PWRSEQ_LPWKPOL0A_13_FALLING << MXC_F_PWRSEQ_LPWKPOL0A_13_POS) /**< LPWKPOL0A_13_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL0A_14_POS 28 /**< LPWKPOL0A_14 Position */ -#define MXC_F_PWRSEQ_LPWKPOL0A_14 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0A_14_POS)) /**< LPWKPOL0A_14 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL0A_14_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0A_14_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_14_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0A_14_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0A_14_POS) /**< LPWKPOL0A_14_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0A_14_RISING ((uint32_t)0x1UL) /**< LPWKPOL0A_14_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_14_RISING (MXC_V_PWRSEQ_LPWKPOL0A_14_RISING << MXC_F_PWRSEQ_LPWKPOL0A_14_POS) /**< LPWKPOL0A_14_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0A_14_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0A_14_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_14_FALLING (MXC_V_PWRSEQ_LPWKPOL0A_14_FALLING << MXC_F_PWRSEQ_LPWKPOL0A_14_POS) /**< LPWKPOL0A_14_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL0A_15_POS 30 /**< LPWKPOL0A_15 Position */ -#define MXC_F_PWRSEQ_LPWKPOL0A_15 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0A_15_POS)) /**< LPWKPOL0A_15 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL0A_15_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0A_15_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_15_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0A_15_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0A_15_POS) /**< LPWKPOL0A_15_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0A_15_RISING ((uint32_t)0x1UL) /**< LPWKPOL0A_15_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_15_RISING (MXC_V_PWRSEQ_LPWKPOL0A_15_RISING << MXC_F_PWRSEQ_LPWKPOL0A_15_POS) /**< LPWKPOL0A_15_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0A_15_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0A_15_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0A_15_FALLING (MXC_V_PWRSEQ_LPWKPOL0A_15_FALLING << MXC_F_PWRSEQ_LPWKPOL0A_15_POS) /**< LPWKPOL0A_15_FALLING Setting */ - -/**@} end of group PWRSEQ_LPWKPOL0A_Register */ - -/** - * @ingroup pwrseq_registers - * @defgroup PWRSEQ_LPWKPOL0B PWRSEQ_LPWKPOL0B - * @brief Low Power Wakeup Polarity Select for GPIO0. - * @{ - */ -#define MXC_F_PWRSEQ_LPWKPOL0B_16_POS 0 /**< LPWKPOL0B_16 Position */ -#define MXC_F_PWRSEQ_LPWKPOL0B_16 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0B_16_POS)) /**< LPWKPOL0B_16 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL0B_16_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0B_16_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_16_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0B_16_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0B_16_POS) /**< LPWKPOL0B_16_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0B_16_RISING ((uint32_t)0x1UL) /**< LPWKPOL0B_16_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_16_RISING (MXC_V_PWRSEQ_LPWKPOL0B_16_RISING << MXC_F_PWRSEQ_LPWKPOL0B_16_POS) /**< LPWKPOL0B_16_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0B_16_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0B_16_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_16_FALLING (MXC_V_PWRSEQ_LPWKPOL0B_16_FALLING << MXC_F_PWRSEQ_LPWKPOL0B_16_POS) /**< LPWKPOL0B_16_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL0B_17_POS 2 /**< LPWKPOL0B_17 Position */ -#define MXC_F_PWRSEQ_LPWKPOL0B_17 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0B_17_POS)) /**< LPWKPOL0B_17 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL0B_17_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0B_17_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_17_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0B_17_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0B_17_POS) /**< LPWKPOL0B_17_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0B_17_RISING ((uint32_t)0x1UL) /**< LPWKPOL0B_17_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_17_RISING (MXC_V_PWRSEQ_LPWKPOL0B_17_RISING << MXC_F_PWRSEQ_LPWKPOL0B_17_POS) /**< LPWKPOL0B_17_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0B_17_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0B_17_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_17_FALLING (MXC_V_PWRSEQ_LPWKPOL0B_17_FALLING << MXC_F_PWRSEQ_LPWKPOL0B_17_POS) /**< LPWKPOL0B_17_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL0B_18_POS 4 /**< LPWKPOL0B_18 Position */ -#define MXC_F_PWRSEQ_LPWKPOL0B_18 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0B_18_POS)) /**< LPWKPOL0B_18 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL0B_18_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0B_18_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_18_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0B_18_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0B_18_POS) /**< LPWKPOL0B_18_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0B_18_RISING ((uint32_t)0x1UL) /**< LPWKPOL0B_18_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_18_RISING (MXC_V_PWRSEQ_LPWKPOL0B_18_RISING << MXC_F_PWRSEQ_LPWKPOL0B_18_POS) /**< LPWKPOL0B_18_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0B_18_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0B_18_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_18_FALLING (MXC_V_PWRSEQ_LPWKPOL0B_18_FALLING << MXC_F_PWRSEQ_LPWKPOL0B_18_POS) /**< LPWKPOL0B_18_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL0B_19_POS 6 /**< LPWKPOL0B_19 Position */ -#define MXC_F_PWRSEQ_LPWKPOL0B_19 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0B_19_POS)) /**< LPWKPOL0B_19 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL0B_19_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0B_19_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_19_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0B_19_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0B_19_POS) /**< LPWKPOL0B_19_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0B_19_RISING ((uint32_t)0x1UL) /**< LPWKPOL0B_19_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_19_RISING (MXC_V_PWRSEQ_LPWKPOL0B_19_RISING << MXC_F_PWRSEQ_LPWKPOL0B_19_POS) /**< LPWKPOL0B_19_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0B_19_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0B_19_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_19_FALLING (MXC_V_PWRSEQ_LPWKPOL0B_19_FALLING << MXC_F_PWRSEQ_LPWKPOL0B_19_POS) /**< LPWKPOL0B_19_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL0B_20_POS 8 /**< LPWKPOL0B_20 Position */ -#define MXC_F_PWRSEQ_LPWKPOL0B_20 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0B_20_POS)) /**< LPWKPOL0B_20 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL0B_20_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0B_20_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_20_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0B_20_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0B_20_POS) /**< LPWKPOL0B_20_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0B_20_RISING ((uint32_t)0x1UL) /**< LPWKPOL0B_20_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_20_RISING (MXC_V_PWRSEQ_LPWKPOL0B_20_RISING << MXC_F_PWRSEQ_LPWKPOL0B_20_POS) /**< LPWKPOL0B_20_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0B_20_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0B_20_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_20_FALLING (MXC_V_PWRSEQ_LPWKPOL0B_20_FALLING << MXC_F_PWRSEQ_LPWKPOL0B_20_POS) /**< LPWKPOL0B_20_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL0B_21_POS 10 /**< LPWKPOL0B_21 Position */ -#define MXC_F_PWRSEQ_LPWKPOL0B_21 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0B_21_POS)) /**< LPWKPOL0B_21 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL0B_21_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0B_21_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_21_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0B_21_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0B_21_POS) /**< LPWKPOL0B_21_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0B_21_RISING ((uint32_t)0x1UL) /**< LPWKPOL0B_21_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_21_RISING (MXC_V_PWRSEQ_LPWKPOL0B_21_RISING << MXC_F_PWRSEQ_LPWKPOL0B_21_POS) /**< LPWKPOL0B_21_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0B_21_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0B_21_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_21_FALLING (MXC_V_PWRSEQ_LPWKPOL0B_21_FALLING << MXC_F_PWRSEQ_LPWKPOL0B_21_POS) /**< LPWKPOL0B_21_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL0B_22_POS 12 /**< LPWKPOL0B_22 Position */ -#define MXC_F_PWRSEQ_LPWKPOL0B_22 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0B_22_POS)) /**< LPWKPOL0B_22 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL0B_22_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0B_22_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_22_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0B_22_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0B_22_POS) /**< LPWKPOL0B_22_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0B_22_RISING ((uint32_t)0x1UL) /**< LPWKPOL0B_22_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_22_RISING (MXC_V_PWRSEQ_LPWKPOL0B_22_RISING << MXC_F_PWRSEQ_LPWKPOL0B_22_POS) /**< LPWKPOL0B_22_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0B_22_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0B_22_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_22_FALLING (MXC_V_PWRSEQ_LPWKPOL0B_22_FALLING << MXC_F_PWRSEQ_LPWKPOL0B_22_POS) /**< LPWKPOL0B_22_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL0B_23_POS 14 /**< LPWKPOL0B_23 Position */ -#define MXC_F_PWRSEQ_LPWKPOL0B_23 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0B_23_POS)) /**< LPWKPOL0B_23 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL0B_23_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0B_23_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_23_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0B_23_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0B_23_POS) /**< LPWKPOL0B_23_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0B_23_RISING ((uint32_t)0x1UL) /**< LPWKPOL0B_23_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_23_RISING (MXC_V_PWRSEQ_LPWKPOL0B_23_RISING << MXC_F_PWRSEQ_LPWKPOL0B_23_POS) /**< LPWKPOL0B_23_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0B_23_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0B_23_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_23_FALLING (MXC_V_PWRSEQ_LPWKPOL0B_23_FALLING << MXC_F_PWRSEQ_LPWKPOL0B_23_POS) /**< LPWKPOL0B_23_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL0B_24_POS 16 /**< LPWKPOL0B_24 Position */ -#define MXC_F_PWRSEQ_LPWKPOL0B_24 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0B_24_POS)) /**< LPWKPOL0B_24 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL0B_24_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0B_24_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_24_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0B_24_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0B_24_POS) /**< LPWKPOL0B_24_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0B_24_RISING ((uint32_t)0x1UL) /**< LPWKPOL0B_24_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_24_RISING (MXC_V_PWRSEQ_LPWKPOL0B_24_RISING << MXC_F_PWRSEQ_LPWKPOL0B_24_POS) /**< LPWKPOL0B_24_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0B_24_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0B_24_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_24_FALLING (MXC_V_PWRSEQ_LPWKPOL0B_24_FALLING << MXC_F_PWRSEQ_LPWKPOL0B_24_POS) /**< LPWKPOL0B_24_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL0B_25_POS 18 /**< LPWKPOL0B_25 Position */ -#define MXC_F_PWRSEQ_LPWKPOL0B_25 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0B_25_POS)) /**< LPWKPOL0B_25 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL0B_25_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0B_25_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_25_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0B_25_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0B_25_POS) /**< LPWKPOL0B_25_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0B_25_RISING ((uint32_t)0x1UL) /**< LPWKPOL0B_25_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_25_RISING (MXC_V_PWRSEQ_LPWKPOL0B_25_RISING << MXC_F_PWRSEQ_LPWKPOL0B_25_POS) /**< LPWKPOL0B_25_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0B_25_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0B_25_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_25_FALLING (MXC_V_PWRSEQ_LPWKPOL0B_25_FALLING << MXC_F_PWRSEQ_LPWKPOL0B_25_POS) /**< LPWKPOL0B_25_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL0B_26_POS 20 /**< LPWKPOL0B_26 Position */ -#define MXC_F_PWRSEQ_LPWKPOL0B_26 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0B_26_POS)) /**< LPWKPOL0B_26 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL0B_26_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0B_26_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_26_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0B_26_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0B_26_POS) /**< LPWKPOL0B_26_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0B_26_RISING ((uint32_t)0x1UL) /**< LPWKPOL0B_26_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_26_RISING (MXC_V_PWRSEQ_LPWKPOL0B_26_RISING << MXC_F_PWRSEQ_LPWKPOL0B_26_POS) /**< LPWKPOL0B_26_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0B_26_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0B_26_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_26_FALLING (MXC_V_PWRSEQ_LPWKPOL0B_26_FALLING << MXC_F_PWRSEQ_LPWKPOL0B_26_POS) /**< LPWKPOL0B_26_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL0B_27_POS 22 /**< LPWKPOL0B_27 Position */ -#define MXC_F_PWRSEQ_LPWKPOL0B_27 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0B_27_POS)) /**< LPWKPOL0B_27 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL0B_27_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0B_27_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_27_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0B_27_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0B_27_POS) /**< LPWKPOL0B_27_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0B_27_RISING ((uint32_t)0x1UL) /**< LPWKPOL0B_27_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_27_RISING (MXC_V_PWRSEQ_LPWKPOL0B_27_RISING << MXC_F_PWRSEQ_LPWKPOL0B_27_POS) /**< LPWKPOL0B_27_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0B_27_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0B_27_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_27_FALLING (MXC_V_PWRSEQ_LPWKPOL0B_27_FALLING << MXC_F_PWRSEQ_LPWKPOL0B_27_POS) /**< LPWKPOL0B_27_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL0B_28_POS 24 /**< LPWKPOL0B_28 Position */ -#define MXC_F_PWRSEQ_LPWKPOL0B_28 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0B_28_POS)) /**< LPWKPOL0B_28 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL0B_28_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0B_28_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_28_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0B_28_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0B_28_POS) /**< LPWKPOL0B_28_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0B_28_RISING ((uint32_t)0x1UL) /**< LPWKPOL0B_28_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_28_RISING (MXC_V_PWRSEQ_LPWKPOL0B_28_RISING << MXC_F_PWRSEQ_LPWKPOL0B_28_POS) /**< LPWKPOL0B_28_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0B_28_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0B_28_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_28_FALLING (MXC_V_PWRSEQ_LPWKPOL0B_28_FALLING << MXC_F_PWRSEQ_LPWKPOL0B_28_POS) /**< LPWKPOL0B_28_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL0B_29_POS 26 /**< LPWKPOL0B_29 Position */ -#define MXC_F_PWRSEQ_LPWKPOL0B_29 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0B_29_POS)) /**< LPWKPOL0B_29 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL0B_29_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0B_29_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_29_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0B_29_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0B_29_POS) /**< LPWKPOL0B_29_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0B_29_RISING ((uint32_t)0x1UL) /**< LPWKPOL0B_29_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_29_RISING (MXC_V_PWRSEQ_LPWKPOL0B_29_RISING << MXC_F_PWRSEQ_LPWKPOL0B_29_POS) /**< LPWKPOL0B_29_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0B_29_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0B_29_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_29_FALLING (MXC_V_PWRSEQ_LPWKPOL0B_29_FALLING << MXC_F_PWRSEQ_LPWKPOL0B_29_POS) /**< LPWKPOL0B_29_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL0B_30_POS 28 /**< LPWKPOL0B_30 Position */ -#define MXC_F_PWRSEQ_LPWKPOL0B_30 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0B_30_POS)) /**< LPWKPOL0B_30 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL0B_30_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0B_30_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_30_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0B_30_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0B_30_POS) /**< LPWKPOL0B_30_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0B_30_RISING ((uint32_t)0x1UL) /**< LPWKPOL0B_30_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_30_RISING (MXC_V_PWRSEQ_LPWKPOL0B_30_RISING << MXC_F_PWRSEQ_LPWKPOL0B_30_POS) /**< LPWKPOL0B_30_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0B_30_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0B_30_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_30_FALLING (MXC_V_PWRSEQ_LPWKPOL0B_30_FALLING << MXC_F_PWRSEQ_LPWKPOL0B_30_POS) /**< LPWKPOL0B_30_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL0B_31_POS 30 /**< LPWKPOL0B_31 Position */ -#define MXC_F_PWRSEQ_LPWKPOL0B_31 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL0B_31_POS)) /**< LPWKPOL0B_31 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL0B_31_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL0B_31_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_31_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL0B_31_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL0B_31_POS) /**< LPWKPOL0B_31_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0B_31_RISING ((uint32_t)0x1UL) /**< LPWKPOL0B_31_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_31_RISING (MXC_V_PWRSEQ_LPWKPOL0B_31_RISING << MXC_F_PWRSEQ_LPWKPOL0B_31_POS) /**< LPWKPOL0B_31_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL0B_31_FALLING ((uint32_t)0x2UL) /**< LPWKPOL0B_31_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL0B_31_FALLING (MXC_V_PWRSEQ_LPWKPOL0B_31_FALLING << MXC_F_PWRSEQ_LPWKPOL0B_31_POS) /**< LPWKPOL0B_31_FALLING Setting */ - -/**@} end of group PWRSEQ_LPWKPOL0B_Register */ - -/** - * @ingroup pwrseq_registers - * @defgroup PWRSEQ_LPWKPOL1A PWRSEQ_LPWKPOL1A - * @brief Low Power Wakeup Polarity Select for GPIO1. - * @{ - */ -#define MXC_F_PWRSEQ_LPWKPOL1A_0_POS 0 /**< LPWKPOL1A_0 Position */ -#define MXC_F_PWRSEQ_LPWKPOL1A_0 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1A_0_POS)) /**< LPWKPOL1A_0 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL1A_0_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1A_0_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_0_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1A_0_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1A_0_POS) /**< LPWKPOL1A_0_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1A_0_RISING ((uint32_t)0x1UL) /**< LPWKPOL1A_0_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_0_RISING (MXC_V_PWRSEQ_LPWKPOL1A_0_RISING << MXC_F_PWRSEQ_LPWKPOL1A_0_POS) /**< LPWKPOL1A_0_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1A_0_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1A_0_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_0_FALLING (MXC_V_PWRSEQ_LPWKPOL1A_0_FALLING << MXC_F_PWRSEQ_LPWKPOL1A_0_POS) /**< LPWKPOL1A_0_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL1A_1_POS 2 /**< LPWKPOL1A_1 Position */ -#define MXC_F_PWRSEQ_LPWKPOL1A_1 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1A_1_POS)) /**< LPWKPOL1A_1 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL1A_1_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1A_1_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_1_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1A_1_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1A_1_POS) /**< LPWKPOL1A_1_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1A_1_RISING ((uint32_t)0x1UL) /**< LPWKPOL1A_1_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_1_RISING (MXC_V_PWRSEQ_LPWKPOL1A_1_RISING << MXC_F_PWRSEQ_LPWKPOL1A_1_POS) /**< LPWKPOL1A_1_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1A_1_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1A_1_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_1_FALLING (MXC_V_PWRSEQ_LPWKPOL1A_1_FALLING << MXC_F_PWRSEQ_LPWKPOL1A_1_POS) /**< LPWKPOL1A_1_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL1A_2_POS 4 /**< LPWKPOL1A_2 Position */ -#define MXC_F_PWRSEQ_LPWKPOL1A_2 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1A_2_POS)) /**< LPWKPOL1A_2 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL1A_2_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1A_2_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_2_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1A_2_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1A_2_POS) /**< LPWKPOL1A_2_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1A_2_RISING ((uint32_t)0x1UL) /**< LPWKPOL1A_2_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_2_RISING (MXC_V_PWRSEQ_LPWKPOL1A_2_RISING << MXC_F_PWRSEQ_LPWKPOL1A_2_POS) /**< LPWKPOL1A_2_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1A_2_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1A_2_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_2_FALLING (MXC_V_PWRSEQ_LPWKPOL1A_2_FALLING << MXC_F_PWRSEQ_LPWKPOL1A_2_POS) /**< LPWKPOL1A_2_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL1A_3_POS 6 /**< LPWKPOL1A_3 Position */ -#define MXC_F_PWRSEQ_LPWKPOL1A_3 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1A_3_POS)) /**< LPWKPOL1A_3 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL1A_3_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1A_3_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_3_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1A_3_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1A_3_POS) /**< LPWKPOL1A_3_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1A_3_RISING ((uint32_t)0x1UL) /**< LPWKPOL1A_3_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_3_RISING (MXC_V_PWRSEQ_LPWKPOL1A_3_RISING << MXC_F_PWRSEQ_LPWKPOL1A_3_POS) /**< LPWKPOL1A_3_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1A_3_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1A_3_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_3_FALLING (MXC_V_PWRSEQ_LPWKPOL1A_3_FALLING << MXC_F_PWRSEQ_LPWKPOL1A_3_POS) /**< LPWKPOL1A_3_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL1A_4_POS 8 /**< LPWKPOL1A_4 Position */ -#define MXC_F_PWRSEQ_LPWKPOL1A_4 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1A_4_POS)) /**< LPWKPOL1A_4 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL1A_4_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1A_4_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_4_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1A_4_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1A_4_POS) /**< LPWKPOL1A_4_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1A_4_RISING ((uint32_t)0x1UL) /**< LPWKPOL1A_4_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_4_RISING (MXC_V_PWRSEQ_LPWKPOL1A_4_RISING << MXC_F_PWRSEQ_LPWKPOL1A_4_POS) /**< LPWKPOL1A_4_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1A_4_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1A_4_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_4_FALLING (MXC_V_PWRSEQ_LPWKPOL1A_4_FALLING << MXC_F_PWRSEQ_LPWKPOL1A_4_POS) /**< LPWKPOL1A_4_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL1A_5_POS 10 /**< LPWKPOL1A_5 Position */ -#define MXC_F_PWRSEQ_LPWKPOL1A_5 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1A_5_POS)) /**< LPWKPOL1A_5 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL1A_5_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1A_5_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_5_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1A_5_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1A_5_POS) /**< LPWKPOL1A_5_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1A_5_RISING ((uint32_t)0x1UL) /**< LPWKPOL1A_5_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_5_RISING (MXC_V_PWRSEQ_LPWKPOL1A_5_RISING << MXC_F_PWRSEQ_LPWKPOL1A_5_POS) /**< LPWKPOL1A_5_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1A_5_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1A_5_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_5_FALLING (MXC_V_PWRSEQ_LPWKPOL1A_5_FALLING << MXC_F_PWRSEQ_LPWKPOL1A_5_POS) /**< LPWKPOL1A_5_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL1A_6_POS 12 /**< LPWKPOL1A_6 Position */ -#define MXC_F_PWRSEQ_LPWKPOL1A_6 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1A_6_POS)) /**< LPWKPOL1A_6 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL1A_6_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1A_6_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_6_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1A_6_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1A_6_POS) /**< LPWKPOL1A_6_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1A_6_RISING ((uint32_t)0x1UL) /**< LPWKPOL1A_6_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_6_RISING (MXC_V_PWRSEQ_LPWKPOL1A_6_RISING << MXC_F_PWRSEQ_LPWKPOL1A_6_POS) /**< LPWKPOL1A_6_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1A_6_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1A_6_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_6_FALLING (MXC_V_PWRSEQ_LPWKPOL1A_6_FALLING << MXC_F_PWRSEQ_LPWKPOL1A_6_POS) /**< LPWKPOL1A_6_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL1A_7_POS 14 /**< LPWKPOL1A_7 Position */ -#define MXC_F_PWRSEQ_LPWKPOL1A_7 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1A_7_POS)) /**< LPWKPOL1A_7 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL1A_7_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1A_7_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_7_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1A_7_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1A_7_POS) /**< LPWKPOL1A_7_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1A_7_RISING ((uint32_t)0x1UL) /**< LPWKPOL1A_7_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_7_RISING (MXC_V_PWRSEQ_LPWKPOL1A_7_RISING << MXC_F_PWRSEQ_LPWKPOL1A_7_POS) /**< LPWKPOL1A_7_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1A_7_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1A_7_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_7_FALLING (MXC_V_PWRSEQ_LPWKPOL1A_7_FALLING << MXC_F_PWRSEQ_LPWKPOL1A_7_POS) /**< LPWKPOL1A_7_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL1A_8_POS 16 /**< LPWKPOL1A_8 Position */ -#define MXC_F_PWRSEQ_LPWKPOL1A_8 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1A_8_POS)) /**< LPWKPOL1A_8 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL1A_8_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1A_8_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_8_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1A_8_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1A_8_POS) /**< LPWKPOL1A_8_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1A_8_RISING ((uint32_t)0x1UL) /**< LPWKPOL1A_8_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_8_RISING (MXC_V_PWRSEQ_LPWKPOL1A_8_RISING << MXC_F_PWRSEQ_LPWKPOL1A_8_POS) /**< LPWKPOL1A_8_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1A_8_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1A_8_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_8_FALLING (MXC_V_PWRSEQ_LPWKPOL1A_8_FALLING << MXC_F_PWRSEQ_LPWKPOL1A_8_POS) /**< LPWKPOL1A_8_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL1A_9_POS 18 /**< LPWKPOL1A_9 Position */ -#define MXC_F_PWRSEQ_LPWKPOL1A_9 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1A_9_POS)) /**< LPWKPOL1A_9 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL1A_9_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1A_9_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_9_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1A_9_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1A_9_POS) /**< LPWKPOL1A_9_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1A_9_RISING ((uint32_t)0x1UL) /**< LPWKPOL1A_9_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_9_RISING (MXC_V_PWRSEQ_LPWKPOL1A_9_RISING << MXC_F_PWRSEQ_LPWKPOL1A_9_POS) /**< LPWKPOL1A_9_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1A_9_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1A_9_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_9_FALLING (MXC_V_PWRSEQ_LPWKPOL1A_9_FALLING << MXC_F_PWRSEQ_LPWKPOL1A_9_POS) /**< LPWKPOL1A_9_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL1A_10_POS 20 /**< LPWKPOL1A_10 Position */ -#define MXC_F_PWRSEQ_LPWKPOL1A_10 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1A_10_POS)) /**< LPWKPOL1A_10 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL1A_10_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1A_10_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_10_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1A_10_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1A_10_POS) /**< LPWKPOL1A_10_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1A_10_RISING ((uint32_t)0x1UL) /**< LPWKPOL1A_10_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_10_RISING (MXC_V_PWRSEQ_LPWKPOL1A_10_RISING << MXC_F_PWRSEQ_LPWKPOL1A_10_POS) /**< LPWKPOL1A_10_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1A_10_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1A_10_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_10_FALLING (MXC_V_PWRSEQ_LPWKPOL1A_10_FALLING << MXC_F_PWRSEQ_LPWKPOL1A_10_POS) /**< LPWKPOL1A_10_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL1A_11_POS 22 /**< LPWKPOL1A_11 Position */ -#define MXC_F_PWRSEQ_LPWKPOL1A_11 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1A_11_POS)) /**< LPWKPOL1A_11 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL1A_11_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1A_11_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_11_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1A_11_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1A_11_POS) /**< LPWKPOL1A_11_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1A_11_RISING ((uint32_t)0x1UL) /**< LPWKPOL1A_11_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_11_RISING (MXC_V_PWRSEQ_LPWKPOL1A_11_RISING << MXC_F_PWRSEQ_LPWKPOL1A_11_POS) /**< LPWKPOL1A_11_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1A_11_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1A_11_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_11_FALLING (MXC_V_PWRSEQ_LPWKPOL1A_11_FALLING << MXC_F_PWRSEQ_LPWKPOL1A_11_POS) /**< LPWKPOL1A_11_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL1A_12_POS 24 /**< LPWKPOL1A_12 Position */ -#define MXC_F_PWRSEQ_LPWKPOL1A_12 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1A_12_POS)) /**< LPWKPOL1A_12 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL1A_12_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1A_12_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_12_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1A_12_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1A_12_POS) /**< LPWKPOL1A_12_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1A_12_RISING ((uint32_t)0x1UL) /**< LPWKPOL1A_12_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_12_RISING (MXC_V_PWRSEQ_LPWKPOL1A_12_RISING << MXC_F_PWRSEQ_LPWKPOL1A_12_POS) /**< LPWKPOL1A_12_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1A_12_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1A_12_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_12_FALLING (MXC_V_PWRSEQ_LPWKPOL1A_12_FALLING << MXC_F_PWRSEQ_LPWKPOL1A_12_POS) /**< LPWKPOL1A_12_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL1A_13_POS 26 /**< LPWKPOL1A_13 Position */ -#define MXC_F_PWRSEQ_LPWKPOL1A_13 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1A_13_POS)) /**< LPWKPOL1A_13 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL1A_13_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1A_13_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_13_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1A_13_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1A_13_POS) /**< LPWKPOL1A_13_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1A_13_RISING ((uint32_t)0x1UL) /**< LPWKPOL1A_13_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_13_RISING (MXC_V_PWRSEQ_LPWKPOL1A_13_RISING << MXC_F_PWRSEQ_LPWKPOL1A_13_POS) /**< LPWKPOL1A_13_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1A_13_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1A_13_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_13_FALLING (MXC_V_PWRSEQ_LPWKPOL1A_13_FALLING << MXC_F_PWRSEQ_LPWKPOL1A_13_POS) /**< LPWKPOL1A_13_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL1A_14_POS 28 /**< LPWKPOL1A_14 Position */ -#define MXC_F_PWRSEQ_LPWKPOL1A_14 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1A_14_POS)) /**< LPWKPOL1A_14 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL1A_14_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1A_14_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_14_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1A_14_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1A_14_POS) /**< LPWKPOL1A_14_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1A_14_RISING ((uint32_t)0x1UL) /**< LPWKPOL1A_14_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_14_RISING (MXC_V_PWRSEQ_LPWKPOL1A_14_RISING << MXC_F_PWRSEQ_LPWKPOL1A_14_POS) /**< LPWKPOL1A_14_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1A_14_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1A_14_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_14_FALLING (MXC_V_PWRSEQ_LPWKPOL1A_14_FALLING << MXC_F_PWRSEQ_LPWKPOL1A_14_POS) /**< LPWKPOL1A_14_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL1A_15_POS 30 /**< LPWKPOL1A_15 Position */ -#define MXC_F_PWRSEQ_LPWKPOL1A_15 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1A_15_POS)) /**< LPWKPOL1A_15 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL1A_15_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1A_15_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_15_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1A_15_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1A_15_POS) /**< LPWKPOL1A_15_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1A_15_RISING ((uint32_t)0x1UL) /**< LPWKPOL1A_15_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_15_RISING (MXC_V_PWRSEQ_LPWKPOL1A_15_RISING << MXC_F_PWRSEQ_LPWKPOL1A_15_POS) /**< LPWKPOL1A_15_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1A_15_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1A_15_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1A_15_FALLING (MXC_V_PWRSEQ_LPWKPOL1A_15_FALLING << MXC_F_PWRSEQ_LPWKPOL1A_15_POS) /**< LPWKPOL1A_15_FALLING Setting */ - -/**@} end of group PWRSEQ_LPWKPOL1A_Register */ - -/** - * @ingroup pwrseq_registers - * @defgroup PWRSEQ_LPWKPOL1B PWRSEQ_LPWKPOL1B - * @brief Low Power Wakeup Polarity Select for GPIO1. - * @{ - */ -#define MXC_F_PWRSEQ_LPWKPOL1B_16_POS 0 /**< LPWKPOL1B_16 Position */ -#define MXC_F_PWRSEQ_LPWKPOL1B_16 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1B_16_POS)) /**< LPWKPOL1B_16 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL1B_16_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1B_16_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_16_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1B_16_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1B_16_POS) /**< LPWKPOL1B_16_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1B_16_RISING ((uint32_t)0x1UL) /**< LPWKPOL1B_16_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_16_RISING (MXC_V_PWRSEQ_LPWKPOL1B_16_RISING << MXC_F_PWRSEQ_LPWKPOL1B_16_POS) /**< LPWKPOL1B_16_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1B_16_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1B_16_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_16_FALLING (MXC_V_PWRSEQ_LPWKPOL1B_16_FALLING << MXC_F_PWRSEQ_LPWKPOL1B_16_POS) /**< LPWKPOL1B_16_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL1B_17_POS 2 /**< LPWKPOL1B_17 Position */ -#define MXC_F_PWRSEQ_LPWKPOL1B_17 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1B_17_POS)) /**< LPWKPOL1B_17 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL1B_17_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1B_17_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_17_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1B_17_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1B_17_POS) /**< LPWKPOL1B_17_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1B_17_RISING ((uint32_t)0x1UL) /**< LPWKPOL1B_17_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_17_RISING (MXC_V_PWRSEQ_LPWKPOL1B_17_RISING << MXC_F_PWRSEQ_LPWKPOL1B_17_POS) /**< LPWKPOL1B_17_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1B_17_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1B_17_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_17_FALLING (MXC_V_PWRSEQ_LPWKPOL1B_17_FALLING << MXC_F_PWRSEQ_LPWKPOL1B_17_POS) /**< LPWKPOL1B_17_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL1B_18_POS 4 /**< LPWKPOL1B_18 Position */ -#define MXC_F_PWRSEQ_LPWKPOL1B_18 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1B_18_POS)) /**< LPWKPOL1B_18 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL1B_18_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1B_18_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_18_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1B_18_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1B_18_POS) /**< LPWKPOL1B_18_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1B_18_RISING ((uint32_t)0x1UL) /**< LPWKPOL1B_18_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_18_RISING (MXC_V_PWRSEQ_LPWKPOL1B_18_RISING << MXC_F_PWRSEQ_LPWKPOL1B_18_POS) /**< LPWKPOL1B_18_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1B_18_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1B_18_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_18_FALLING (MXC_V_PWRSEQ_LPWKPOL1B_18_FALLING << MXC_F_PWRSEQ_LPWKPOL1B_18_POS) /**< LPWKPOL1B_18_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL1B_19_POS 6 /**< LPWKPOL1B_19 Position */ -#define MXC_F_PWRSEQ_LPWKPOL1B_19 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1B_19_POS)) /**< LPWKPOL1B_19 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL1B_19_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1B_19_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_19_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1B_19_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1B_19_POS) /**< LPWKPOL1B_19_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1B_19_RISING ((uint32_t)0x1UL) /**< LPWKPOL1B_19_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_19_RISING (MXC_V_PWRSEQ_LPWKPOL1B_19_RISING << MXC_F_PWRSEQ_LPWKPOL1B_19_POS) /**< LPWKPOL1B_19_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1B_19_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1B_19_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_19_FALLING (MXC_V_PWRSEQ_LPWKPOL1B_19_FALLING << MXC_F_PWRSEQ_LPWKPOL1B_19_POS) /**< LPWKPOL1B_19_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL1B_20_POS 8 /**< LPWKPOL1B_20 Position */ -#define MXC_F_PWRSEQ_LPWKPOL1B_20 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1B_20_POS)) /**< LPWKPOL1B_20 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL1B_20_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1B_20_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_20_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1B_20_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1B_20_POS) /**< LPWKPOL1B_20_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1B_20_RISING ((uint32_t)0x1UL) /**< LPWKPOL1B_20_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_20_RISING (MXC_V_PWRSEQ_LPWKPOL1B_20_RISING << MXC_F_PWRSEQ_LPWKPOL1B_20_POS) /**< LPWKPOL1B_20_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1B_20_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1B_20_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_20_FALLING (MXC_V_PWRSEQ_LPWKPOL1B_20_FALLING << MXC_F_PWRSEQ_LPWKPOL1B_20_POS) /**< LPWKPOL1B_20_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL1B_21_POS 10 /**< LPWKPOL1B_21 Position */ -#define MXC_F_PWRSEQ_LPWKPOL1B_21 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1B_21_POS)) /**< LPWKPOL1B_21 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL1B_21_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1B_21_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_21_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1B_21_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1B_21_POS) /**< LPWKPOL1B_21_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1B_21_RISING ((uint32_t)0x1UL) /**< LPWKPOL1B_21_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_21_RISING (MXC_V_PWRSEQ_LPWKPOL1B_21_RISING << MXC_F_PWRSEQ_LPWKPOL1B_21_POS) /**< LPWKPOL1B_21_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1B_21_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1B_21_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_21_FALLING (MXC_V_PWRSEQ_LPWKPOL1B_21_FALLING << MXC_F_PWRSEQ_LPWKPOL1B_21_POS) /**< LPWKPOL1B_21_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL1B_22_POS 12 /**< LPWKPOL1B_22 Position */ -#define MXC_F_PWRSEQ_LPWKPOL1B_22 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1B_22_POS)) /**< LPWKPOL1B_22 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL1B_22_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1B_22_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_22_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1B_22_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1B_22_POS) /**< LPWKPOL1B_22_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1B_22_RISING ((uint32_t)0x1UL) /**< LPWKPOL1B_22_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_22_RISING (MXC_V_PWRSEQ_LPWKPOL1B_22_RISING << MXC_F_PWRSEQ_LPWKPOL1B_22_POS) /**< LPWKPOL1B_22_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1B_22_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1B_22_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_22_FALLING (MXC_V_PWRSEQ_LPWKPOL1B_22_FALLING << MXC_F_PWRSEQ_LPWKPOL1B_22_POS) /**< LPWKPOL1B_22_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL1B_23_POS 14 /**< LPWKPOL1B_23 Position */ -#define MXC_F_PWRSEQ_LPWKPOL1B_23 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1B_23_POS)) /**< LPWKPOL1B_23 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL1B_23_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1B_23_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_23_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1B_23_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1B_23_POS) /**< LPWKPOL1B_23_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1B_23_RISING ((uint32_t)0x1UL) /**< LPWKPOL1B_23_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_23_RISING (MXC_V_PWRSEQ_LPWKPOL1B_23_RISING << MXC_F_PWRSEQ_LPWKPOL1B_23_POS) /**< LPWKPOL1B_23_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1B_23_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1B_23_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_23_FALLING (MXC_V_PWRSEQ_LPWKPOL1B_23_FALLING << MXC_F_PWRSEQ_LPWKPOL1B_23_POS) /**< LPWKPOL1B_23_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL1B_24_POS 16 /**< LPWKPOL1B_24 Position */ -#define MXC_F_PWRSEQ_LPWKPOL1B_24 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1B_24_POS)) /**< LPWKPOL1B_24 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL1B_24_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1B_24_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_24_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1B_24_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1B_24_POS) /**< LPWKPOL1B_24_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1B_24_RISING ((uint32_t)0x1UL) /**< LPWKPOL1B_24_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_24_RISING (MXC_V_PWRSEQ_LPWKPOL1B_24_RISING << MXC_F_PWRSEQ_LPWKPOL1B_24_POS) /**< LPWKPOL1B_24_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1B_24_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1B_24_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_24_FALLING (MXC_V_PWRSEQ_LPWKPOL1B_24_FALLING << MXC_F_PWRSEQ_LPWKPOL1B_24_POS) /**< LPWKPOL1B_24_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL1B_25_POS 18 /**< LPWKPOL1B_25 Position */ -#define MXC_F_PWRSEQ_LPWKPOL1B_25 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1B_25_POS)) /**< LPWKPOL1B_25 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL1B_25_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1B_25_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_25_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1B_25_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1B_25_POS) /**< LPWKPOL1B_25_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1B_25_RISING ((uint32_t)0x1UL) /**< LPWKPOL1B_25_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_25_RISING (MXC_V_PWRSEQ_LPWKPOL1B_25_RISING << MXC_F_PWRSEQ_LPWKPOL1B_25_POS) /**< LPWKPOL1B_25_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1B_25_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1B_25_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_25_FALLING (MXC_V_PWRSEQ_LPWKPOL1B_25_FALLING << MXC_F_PWRSEQ_LPWKPOL1B_25_POS) /**< LPWKPOL1B_25_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL1B_26_POS 20 /**< LPWKPOL1B_26 Position */ -#define MXC_F_PWRSEQ_LPWKPOL1B_26 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1B_26_POS)) /**< LPWKPOL1B_26 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL1B_26_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1B_26_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_26_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1B_26_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1B_26_POS) /**< LPWKPOL1B_26_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1B_26_RISING ((uint32_t)0x1UL) /**< LPWKPOL1B_26_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_26_RISING (MXC_V_PWRSEQ_LPWKPOL1B_26_RISING << MXC_F_PWRSEQ_LPWKPOL1B_26_POS) /**< LPWKPOL1B_26_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1B_26_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1B_26_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_26_FALLING (MXC_V_PWRSEQ_LPWKPOL1B_26_FALLING << MXC_F_PWRSEQ_LPWKPOL1B_26_POS) /**< LPWKPOL1B_26_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL1B_27_POS 22 /**< LPWKPOL1B_27 Position */ -#define MXC_F_PWRSEQ_LPWKPOL1B_27 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1B_27_POS)) /**< LPWKPOL1B_27 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL1B_27_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1B_27_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_27_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1B_27_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1B_27_POS) /**< LPWKPOL1B_27_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1B_27_RISING ((uint32_t)0x1UL) /**< LPWKPOL1B_27_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_27_RISING (MXC_V_PWRSEQ_LPWKPOL1B_27_RISING << MXC_F_PWRSEQ_LPWKPOL1B_27_POS) /**< LPWKPOL1B_27_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1B_27_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1B_27_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_27_FALLING (MXC_V_PWRSEQ_LPWKPOL1B_27_FALLING << MXC_F_PWRSEQ_LPWKPOL1B_27_POS) /**< LPWKPOL1B_27_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL1B_28_POS 24 /**< LPWKPOL1B_28 Position */ -#define MXC_F_PWRSEQ_LPWKPOL1B_28 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1B_28_POS)) /**< LPWKPOL1B_28 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL1B_28_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1B_28_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_28_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1B_28_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1B_28_POS) /**< LPWKPOL1B_28_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1B_28_RISING ((uint32_t)0x1UL) /**< LPWKPOL1B_28_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_28_RISING (MXC_V_PWRSEQ_LPWKPOL1B_28_RISING << MXC_F_PWRSEQ_LPWKPOL1B_28_POS) /**< LPWKPOL1B_28_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1B_28_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1B_28_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_28_FALLING (MXC_V_PWRSEQ_LPWKPOL1B_28_FALLING << MXC_F_PWRSEQ_LPWKPOL1B_28_POS) /**< LPWKPOL1B_28_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL1B_29_POS 26 /**< LPWKPOL1B_29 Position */ -#define MXC_F_PWRSEQ_LPWKPOL1B_29 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1B_29_POS)) /**< LPWKPOL1B_29 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL1B_29_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1B_29_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_29_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1B_29_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1B_29_POS) /**< LPWKPOL1B_29_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1B_29_RISING ((uint32_t)0x1UL) /**< LPWKPOL1B_29_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_29_RISING (MXC_V_PWRSEQ_LPWKPOL1B_29_RISING << MXC_F_PWRSEQ_LPWKPOL1B_29_POS) /**< LPWKPOL1B_29_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1B_29_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1B_29_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_29_FALLING (MXC_V_PWRSEQ_LPWKPOL1B_29_FALLING << MXC_F_PWRSEQ_LPWKPOL1B_29_POS) /**< LPWKPOL1B_29_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL1B_30_POS 28 /**< LPWKPOL1B_30 Position */ -#define MXC_F_PWRSEQ_LPWKPOL1B_30 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1B_30_POS)) /**< LPWKPOL1B_30 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL1B_30_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1B_30_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_30_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1B_30_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1B_30_POS) /**< LPWKPOL1B_30_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1B_30_RISING ((uint32_t)0x1UL) /**< LPWKPOL1B_30_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_30_RISING (MXC_V_PWRSEQ_LPWKPOL1B_30_RISING << MXC_F_PWRSEQ_LPWKPOL1B_30_POS) /**< LPWKPOL1B_30_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1B_30_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1B_30_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_30_FALLING (MXC_V_PWRSEQ_LPWKPOL1B_30_FALLING << MXC_F_PWRSEQ_LPWKPOL1B_30_POS) /**< LPWKPOL1B_30_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL1B_31_POS 30 /**< LPWKPOL1B_31 Position */ -#define MXC_F_PWRSEQ_LPWKPOL1B_31 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL1B_31_POS)) /**< LPWKPOL1B_31 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL1B_31_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL1B_31_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_31_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL1B_31_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL1B_31_POS) /**< LPWKPOL1B_31_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1B_31_RISING ((uint32_t)0x1UL) /**< LPWKPOL1B_31_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_31_RISING (MXC_V_PWRSEQ_LPWKPOL1B_31_RISING << MXC_F_PWRSEQ_LPWKPOL1B_31_POS) /**< LPWKPOL1B_31_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL1B_31_FALLING ((uint32_t)0x2UL) /**< LPWKPOL1B_31_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL1B_31_FALLING (MXC_V_PWRSEQ_LPWKPOL1B_31_FALLING << MXC_F_PWRSEQ_LPWKPOL1B_31_POS) /**< LPWKPOL1B_31_FALLING Setting */ - -/**@} end of group PWRSEQ_LPWKPOL1B_Register */ - -/** - * @ingroup pwrseq_registers - * @defgroup PWRSEQ_LPWKPOL2A PWRSEQ_LPWKPOL2A - * @brief Low Power Wakeup Polarity Select for GPIO2. - * @{ - */ -#define MXC_F_PWRSEQ_LPWKPOL2A_0_POS 0 /**< LPWKPOL2A_0 Position */ -#define MXC_F_PWRSEQ_LPWKPOL2A_0 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2A_0_POS)) /**< LPWKPOL2A_0 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL2A_0_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2A_0_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_0_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2A_0_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2A_0_POS) /**< LPWKPOL2A_0_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2A_0_RISING ((uint32_t)0x1UL) /**< LPWKPOL2A_0_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_0_RISING (MXC_V_PWRSEQ_LPWKPOL2A_0_RISING << MXC_F_PWRSEQ_LPWKPOL2A_0_POS) /**< LPWKPOL2A_0_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2A_0_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2A_0_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_0_FALLING (MXC_V_PWRSEQ_LPWKPOL2A_0_FALLING << MXC_F_PWRSEQ_LPWKPOL2A_0_POS) /**< LPWKPOL2A_0_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL2A_1_POS 2 /**< LPWKPOL2A_1 Position */ -#define MXC_F_PWRSEQ_LPWKPOL2A_1 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2A_1_POS)) /**< LPWKPOL2A_1 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL2A_1_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2A_1_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_1_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2A_1_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2A_1_POS) /**< LPWKPOL2A_1_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2A_1_RISING ((uint32_t)0x1UL) /**< LPWKPOL2A_1_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_1_RISING (MXC_V_PWRSEQ_LPWKPOL2A_1_RISING << MXC_F_PWRSEQ_LPWKPOL2A_1_POS) /**< LPWKPOL2A_1_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2A_1_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2A_1_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_1_FALLING (MXC_V_PWRSEQ_LPWKPOL2A_1_FALLING << MXC_F_PWRSEQ_LPWKPOL2A_1_POS) /**< LPWKPOL2A_1_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL2A_2_POS 4 /**< LPWKPOL2A_2 Position */ -#define MXC_F_PWRSEQ_LPWKPOL2A_2 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2A_2_POS)) /**< LPWKPOL2A_2 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL2A_2_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2A_2_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_2_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2A_2_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2A_2_POS) /**< LPWKPOL2A_2_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2A_2_RISING ((uint32_t)0x1UL) /**< LPWKPOL2A_2_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_2_RISING (MXC_V_PWRSEQ_LPWKPOL2A_2_RISING << MXC_F_PWRSEQ_LPWKPOL2A_2_POS) /**< LPWKPOL2A_2_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2A_2_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2A_2_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_2_FALLING (MXC_V_PWRSEQ_LPWKPOL2A_2_FALLING << MXC_F_PWRSEQ_LPWKPOL2A_2_POS) /**< LPWKPOL2A_2_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL2A_3_POS 6 /**< LPWKPOL2A_3 Position */ -#define MXC_F_PWRSEQ_LPWKPOL2A_3 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2A_3_POS)) /**< LPWKPOL2A_3 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL2A_3_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2A_3_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_3_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2A_3_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2A_3_POS) /**< LPWKPOL2A_3_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2A_3_RISING ((uint32_t)0x1UL) /**< LPWKPOL2A_3_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_3_RISING (MXC_V_PWRSEQ_LPWKPOL2A_3_RISING << MXC_F_PWRSEQ_LPWKPOL2A_3_POS) /**< LPWKPOL2A_3_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2A_3_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2A_3_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_3_FALLING (MXC_V_PWRSEQ_LPWKPOL2A_3_FALLING << MXC_F_PWRSEQ_LPWKPOL2A_3_POS) /**< LPWKPOL2A_3_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL2A_4_POS 8 /**< LPWKPOL2A_4 Position */ -#define MXC_F_PWRSEQ_LPWKPOL2A_4 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2A_4_POS)) /**< LPWKPOL2A_4 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL2A_4_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2A_4_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_4_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2A_4_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2A_4_POS) /**< LPWKPOL2A_4_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2A_4_RISING ((uint32_t)0x1UL) /**< LPWKPOL2A_4_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_4_RISING (MXC_V_PWRSEQ_LPWKPOL2A_4_RISING << MXC_F_PWRSEQ_LPWKPOL2A_4_POS) /**< LPWKPOL2A_4_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2A_4_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2A_4_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_4_FALLING (MXC_V_PWRSEQ_LPWKPOL2A_4_FALLING << MXC_F_PWRSEQ_LPWKPOL2A_4_POS) /**< LPWKPOL2A_4_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL2A_5_POS 10 /**< LPWKPOL2A_5 Position */ -#define MXC_F_PWRSEQ_LPWKPOL2A_5 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2A_5_POS)) /**< LPWKPOL2A_5 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL2A_5_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2A_5_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_5_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2A_5_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2A_5_POS) /**< LPWKPOL2A_5_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2A_5_RISING ((uint32_t)0x1UL) /**< LPWKPOL2A_5_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_5_RISING (MXC_V_PWRSEQ_LPWKPOL2A_5_RISING << MXC_F_PWRSEQ_LPWKPOL2A_5_POS) /**< LPWKPOL2A_5_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2A_5_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2A_5_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_5_FALLING (MXC_V_PWRSEQ_LPWKPOL2A_5_FALLING << MXC_F_PWRSEQ_LPWKPOL2A_5_POS) /**< LPWKPOL2A_5_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL2A_6_POS 12 /**< LPWKPOL2A_6 Position */ -#define MXC_F_PWRSEQ_LPWKPOL2A_6 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2A_6_POS)) /**< LPWKPOL2A_6 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL2A_6_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2A_6_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_6_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2A_6_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2A_6_POS) /**< LPWKPOL2A_6_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2A_6_RISING ((uint32_t)0x1UL) /**< LPWKPOL2A_6_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_6_RISING (MXC_V_PWRSEQ_LPWKPOL2A_6_RISING << MXC_F_PWRSEQ_LPWKPOL2A_6_POS) /**< LPWKPOL2A_6_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2A_6_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2A_6_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_6_FALLING (MXC_V_PWRSEQ_LPWKPOL2A_6_FALLING << MXC_F_PWRSEQ_LPWKPOL2A_6_POS) /**< LPWKPOL2A_6_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL2A_7_POS 14 /**< LPWKPOL2A_7 Position */ -#define MXC_F_PWRSEQ_LPWKPOL2A_7 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2A_7_POS)) /**< LPWKPOL2A_7 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL2A_7_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2A_7_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_7_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2A_7_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2A_7_POS) /**< LPWKPOL2A_7_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2A_7_RISING ((uint32_t)0x1UL) /**< LPWKPOL2A_7_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_7_RISING (MXC_V_PWRSEQ_LPWKPOL2A_7_RISING << MXC_F_PWRSEQ_LPWKPOL2A_7_POS) /**< LPWKPOL2A_7_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2A_7_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2A_7_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_7_FALLING (MXC_V_PWRSEQ_LPWKPOL2A_7_FALLING << MXC_F_PWRSEQ_LPWKPOL2A_7_POS) /**< LPWKPOL2A_7_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL2A_8_POS 16 /**< LPWKPOL2A_8 Position */ -#define MXC_F_PWRSEQ_LPWKPOL2A_8 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2A_8_POS)) /**< LPWKPOL2A_8 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL2A_8_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2A_8_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_8_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2A_8_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2A_8_POS) /**< LPWKPOL2A_8_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2A_8_RISING ((uint32_t)0x1UL) /**< LPWKPOL2A_8_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_8_RISING (MXC_V_PWRSEQ_LPWKPOL2A_8_RISING << MXC_F_PWRSEQ_LPWKPOL2A_8_POS) /**< LPWKPOL2A_8_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2A_8_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2A_8_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_8_FALLING (MXC_V_PWRSEQ_LPWKPOL2A_8_FALLING << MXC_F_PWRSEQ_LPWKPOL2A_8_POS) /**< LPWKPOL2A_8_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL2A_9_POS 18 /**< LPWKPOL2A_9 Position */ -#define MXC_F_PWRSEQ_LPWKPOL2A_9 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2A_9_POS)) /**< LPWKPOL2A_9 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL2A_9_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2A_9_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_9_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2A_9_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2A_9_POS) /**< LPWKPOL2A_9_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2A_9_RISING ((uint32_t)0x1UL) /**< LPWKPOL2A_9_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_9_RISING (MXC_V_PWRSEQ_LPWKPOL2A_9_RISING << MXC_F_PWRSEQ_LPWKPOL2A_9_POS) /**< LPWKPOL2A_9_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2A_9_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2A_9_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_9_FALLING (MXC_V_PWRSEQ_LPWKPOL2A_9_FALLING << MXC_F_PWRSEQ_LPWKPOL2A_9_POS) /**< LPWKPOL2A_9_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL2A_10_POS 20 /**< LPWKPOL2A_10 Position */ -#define MXC_F_PWRSEQ_LPWKPOL2A_10 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2A_10_POS)) /**< LPWKPOL2A_10 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL2A_10_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2A_10_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_10_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2A_10_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2A_10_POS) /**< LPWKPOL2A_10_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2A_10_RISING ((uint32_t)0x1UL) /**< LPWKPOL2A_10_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_10_RISING (MXC_V_PWRSEQ_LPWKPOL2A_10_RISING << MXC_F_PWRSEQ_LPWKPOL2A_10_POS) /**< LPWKPOL2A_10_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2A_10_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2A_10_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_10_FALLING (MXC_V_PWRSEQ_LPWKPOL2A_10_FALLING << MXC_F_PWRSEQ_LPWKPOL2A_10_POS) /**< LPWKPOL2A_10_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL2A_11_POS 22 /**< LPWKPOL2A_11 Position */ -#define MXC_F_PWRSEQ_LPWKPOL2A_11 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2A_11_POS)) /**< LPWKPOL2A_11 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL2A_11_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2A_11_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_11_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2A_11_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2A_11_POS) /**< LPWKPOL2A_11_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2A_11_RISING ((uint32_t)0x1UL) /**< LPWKPOL2A_11_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_11_RISING (MXC_V_PWRSEQ_LPWKPOL2A_11_RISING << MXC_F_PWRSEQ_LPWKPOL2A_11_POS) /**< LPWKPOL2A_11_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2A_11_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2A_11_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_11_FALLING (MXC_V_PWRSEQ_LPWKPOL2A_11_FALLING << MXC_F_PWRSEQ_LPWKPOL2A_11_POS) /**< LPWKPOL2A_11_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL2A_12_POS 24 /**< LPWKPOL2A_12 Position */ -#define MXC_F_PWRSEQ_LPWKPOL2A_12 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2A_12_POS)) /**< LPWKPOL2A_12 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL2A_12_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2A_12_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_12_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2A_12_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2A_12_POS) /**< LPWKPOL2A_12_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2A_12_RISING ((uint32_t)0x1UL) /**< LPWKPOL2A_12_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_12_RISING (MXC_V_PWRSEQ_LPWKPOL2A_12_RISING << MXC_F_PWRSEQ_LPWKPOL2A_12_POS) /**< LPWKPOL2A_12_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2A_12_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2A_12_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_12_FALLING (MXC_V_PWRSEQ_LPWKPOL2A_12_FALLING << MXC_F_PWRSEQ_LPWKPOL2A_12_POS) /**< LPWKPOL2A_12_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL2A_13_POS 26 /**< LPWKPOL2A_13 Position */ -#define MXC_F_PWRSEQ_LPWKPOL2A_13 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2A_13_POS)) /**< LPWKPOL2A_13 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL2A_13_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2A_13_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_13_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2A_13_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2A_13_POS) /**< LPWKPOL2A_13_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2A_13_RISING ((uint32_t)0x1UL) /**< LPWKPOL2A_13_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_13_RISING (MXC_V_PWRSEQ_LPWKPOL2A_13_RISING << MXC_F_PWRSEQ_LPWKPOL2A_13_POS) /**< LPWKPOL2A_13_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2A_13_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2A_13_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_13_FALLING (MXC_V_PWRSEQ_LPWKPOL2A_13_FALLING << MXC_F_PWRSEQ_LPWKPOL2A_13_POS) /**< LPWKPOL2A_13_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL2A_14_POS 28 /**< LPWKPOL2A_14 Position */ -#define MXC_F_PWRSEQ_LPWKPOL2A_14 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2A_14_POS)) /**< LPWKPOL2A_14 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL2A_14_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2A_14_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_14_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2A_14_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2A_14_POS) /**< LPWKPOL2A_14_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2A_14_RISING ((uint32_t)0x1UL) /**< LPWKPOL2A_14_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_14_RISING (MXC_V_PWRSEQ_LPWKPOL2A_14_RISING << MXC_F_PWRSEQ_LPWKPOL2A_14_POS) /**< LPWKPOL2A_14_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2A_14_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2A_14_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_14_FALLING (MXC_V_PWRSEQ_LPWKPOL2A_14_FALLING << MXC_F_PWRSEQ_LPWKPOL2A_14_POS) /**< LPWKPOL2A_14_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL2A_15_POS 30 /**< LPWKPOL2A_15 Position */ -#define MXC_F_PWRSEQ_LPWKPOL2A_15 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2A_15_POS)) /**< LPWKPOL2A_15 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL2A_15_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2A_15_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_15_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2A_15_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2A_15_POS) /**< LPWKPOL2A_15_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2A_15_RISING ((uint32_t)0x1UL) /**< LPWKPOL2A_15_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_15_RISING (MXC_V_PWRSEQ_LPWKPOL2A_15_RISING << MXC_F_PWRSEQ_LPWKPOL2A_15_POS) /**< LPWKPOL2A_15_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2A_15_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2A_15_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2A_15_FALLING (MXC_V_PWRSEQ_LPWKPOL2A_15_FALLING << MXC_F_PWRSEQ_LPWKPOL2A_15_POS) /**< LPWKPOL2A_15_FALLING Setting */ - -/**@} end of group PWRSEQ_LPWKPOL2A_Register */ - -/** - * @ingroup pwrseq_registers - * @defgroup PWRSEQ_LPWKPOL2B PWRSEQ_LPWKPOL2B - * @brief Low Power Wakeup Polarity Select for GPIO2. - * @{ - */ -#define MXC_F_PWRSEQ_LPWKPOL2B_16_POS 0 /**< LPWKPOL2B_16 Position */ -#define MXC_F_PWRSEQ_LPWKPOL2B_16 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2B_16_POS)) /**< LPWKPOL2B_16 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL2B_16_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2B_16_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_16_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2B_16_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2B_16_POS) /**< LPWKPOL2B_16_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2B_16_RISING ((uint32_t)0x1UL) /**< LPWKPOL2B_16_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_16_RISING (MXC_V_PWRSEQ_LPWKPOL2B_16_RISING << MXC_F_PWRSEQ_LPWKPOL2B_16_POS) /**< LPWKPOL2B_16_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2B_16_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2B_16_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_16_FALLING (MXC_V_PWRSEQ_LPWKPOL2B_16_FALLING << MXC_F_PWRSEQ_LPWKPOL2B_16_POS) /**< LPWKPOL2B_16_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL2B_17_POS 2 /**< LPWKPOL2B_17 Position */ -#define MXC_F_PWRSEQ_LPWKPOL2B_17 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2B_17_POS)) /**< LPWKPOL2B_17 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL2B_17_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2B_17_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_17_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2B_17_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2B_17_POS) /**< LPWKPOL2B_17_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2B_17_RISING ((uint32_t)0x1UL) /**< LPWKPOL2B_17_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_17_RISING (MXC_V_PWRSEQ_LPWKPOL2B_17_RISING << MXC_F_PWRSEQ_LPWKPOL2B_17_POS) /**< LPWKPOL2B_17_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2B_17_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2B_17_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_17_FALLING (MXC_V_PWRSEQ_LPWKPOL2B_17_FALLING << MXC_F_PWRSEQ_LPWKPOL2B_17_POS) /**< LPWKPOL2B_17_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL2B_18_POS 4 /**< LPWKPOL2B_18 Position */ -#define MXC_F_PWRSEQ_LPWKPOL2B_18 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2B_18_POS)) /**< LPWKPOL2B_18 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL2B_18_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2B_18_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_18_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2B_18_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2B_18_POS) /**< LPWKPOL2B_18_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2B_18_RISING ((uint32_t)0x1UL) /**< LPWKPOL2B_18_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_18_RISING (MXC_V_PWRSEQ_LPWKPOL2B_18_RISING << MXC_F_PWRSEQ_LPWKPOL2B_18_POS) /**< LPWKPOL2B_18_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2B_18_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2B_18_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_18_FALLING (MXC_V_PWRSEQ_LPWKPOL2B_18_FALLING << MXC_F_PWRSEQ_LPWKPOL2B_18_POS) /**< LPWKPOL2B_18_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL2B_19_POS 6 /**< LPWKPOL2B_19 Position */ -#define MXC_F_PWRSEQ_LPWKPOL2B_19 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2B_19_POS)) /**< LPWKPOL2B_19 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL2B_19_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2B_19_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_19_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2B_19_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2B_19_POS) /**< LPWKPOL2B_19_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2B_19_RISING ((uint32_t)0x1UL) /**< LPWKPOL2B_19_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_19_RISING (MXC_V_PWRSEQ_LPWKPOL2B_19_RISING << MXC_F_PWRSEQ_LPWKPOL2B_19_POS) /**< LPWKPOL2B_19_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2B_19_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2B_19_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_19_FALLING (MXC_V_PWRSEQ_LPWKPOL2B_19_FALLING << MXC_F_PWRSEQ_LPWKPOL2B_19_POS) /**< LPWKPOL2B_19_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL2B_20_POS 8 /**< LPWKPOL2B_20 Position */ -#define MXC_F_PWRSEQ_LPWKPOL2B_20 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2B_20_POS)) /**< LPWKPOL2B_20 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL2B_20_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2B_20_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_20_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2B_20_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2B_20_POS) /**< LPWKPOL2B_20_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2B_20_RISING ((uint32_t)0x1UL) /**< LPWKPOL2B_20_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_20_RISING (MXC_V_PWRSEQ_LPWKPOL2B_20_RISING << MXC_F_PWRSEQ_LPWKPOL2B_20_POS) /**< LPWKPOL2B_20_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2B_20_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2B_20_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_20_FALLING (MXC_V_PWRSEQ_LPWKPOL2B_20_FALLING << MXC_F_PWRSEQ_LPWKPOL2B_20_POS) /**< LPWKPOL2B_20_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL2B_21_POS 10 /**< LPWKPOL2B_21 Position */ -#define MXC_F_PWRSEQ_LPWKPOL2B_21 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2B_21_POS)) /**< LPWKPOL2B_21 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL2B_21_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2B_21_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_21_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2B_21_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2B_21_POS) /**< LPWKPOL2B_21_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2B_21_RISING ((uint32_t)0x1UL) /**< LPWKPOL2B_21_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_21_RISING (MXC_V_PWRSEQ_LPWKPOL2B_21_RISING << MXC_F_PWRSEQ_LPWKPOL2B_21_POS) /**< LPWKPOL2B_21_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2B_21_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2B_21_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_21_FALLING (MXC_V_PWRSEQ_LPWKPOL2B_21_FALLING << MXC_F_PWRSEQ_LPWKPOL2B_21_POS) /**< LPWKPOL2B_21_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL2B_22_POS 12 /**< LPWKPOL2B_22 Position */ -#define MXC_F_PWRSEQ_LPWKPOL2B_22 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2B_22_POS)) /**< LPWKPOL2B_22 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL2B_22_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2B_22_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_22_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2B_22_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2B_22_POS) /**< LPWKPOL2B_22_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2B_22_RISING ((uint32_t)0x1UL) /**< LPWKPOL2B_22_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_22_RISING (MXC_V_PWRSEQ_LPWKPOL2B_22_RISING << MXC_F_PWRSEQ_LPWKPOL2B_22_POS) /**< LPWKPOL2B_22_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2B_22_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2B_22_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_22_FALLING (MXC_V_PWRSEQ_LPWKPOL2B_22_FALLING << MXC_F_PWRSEQ_LPWKPOL2B_22_POS) /**< LPWKPOL2B_22_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL2B_23_POS 14 /**< LPWKPOL2B_23 Position */ -#define MXC_F_PWRSEQ_LPWKPOL2B_23 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2B_23_POS)) /**< LPWKPOL2B_23 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL2B_23_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2B_23_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_23_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2B_23_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2B_23_POS) /**< LPWKPOL2B_23_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2B_23_RISING ((uint32_t)0x1UL) /**< LPWKPOL2B_23_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_23_RISING (MXC_V_PWRSEQ_LPWKPOL2B_23_RISING << MXC_F_PWRSEQ_LPWKPOL2B_23_POS) /**< LPWKPOL2B_23_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2B_23_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2B_23_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_23_FALLING (MXC_V_PWRSEQ_LPWKPOL2B_23_FALLING << MXC_F_PWRSEQ_LPWKPOL2B_23_POS) /**< LPWKPOL2B_23_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL2B_24_POS 16 /**< LPWKPOL2B_24 Position */ -#define MXC_F_PWRSEQ_LPWKPOL2B_24 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2B_24_POS)) /**< LPWKPOL2B_24 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL2B_24_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2B_24_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_24_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2B_24_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2B_24_POS) /**< LPWKPOL2B_24_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2B_24_RISING ((uint32_t)0x1UL) /**< LPWKPOL2B_24_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_24_RISING (MXC_V_PWRSEQ_LPWKPOL2B_24_RISING << MXC_F_PWRSEQ_LPWKPOL2B_24_POS) /**< LPWKPOL2B_24_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2B_24_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2B_24_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_24_FALLING (MXC_V_PWRSEQ_LPWKPOL2B_24_FALLING << MXC_F_PWRSEQ_LPWKPOL2B_24_POS) /**< LPWKPOL2B_24_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL2B_25_POS 18 /**< LPWKPOL2B_25 Position */ -#define MXC_F_PWRSEQ_LPWKPOL2B_25 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2B_25_POS)) /**< LPWKPOL2B_25 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL2B_25_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2B_25_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_25_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2B_25_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2B_25_POS) /**< LPWKPOL2B_25_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2B_25_RISING ((uint32_t)0x1UL) /**< LPWKPOL2B_25_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_25_RISING (MXC_V_PWRSEQ_LPWKPOL2B_25_RISING << MXC_F_PWRSEQ_LPWKPOL2B_25_POS) /**< LPWKPOL2B_25_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2B_25_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2B_25_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_25_FALLING (MXC_V_PWRSEQ_LPWKPOL2B_25_FALLING << MXC_F_PWRSEQ_LPWKPOL2B_25_POS) /**< LPWKPOL2B_25_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL2B_26_POS 20 /**< LPWKPOL2B_26 Position */ -#define MXC_F_PWRSEQ_LPWKPOL2B_26 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2B_26_POS)) /**< LPWKPOL2B_26 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL2B_26_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2B_26_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_26_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2B_26_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2B_26_POS) /**< LPWKPOL2B_26_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2B_26_RISING ((uint32_t)0x1UL) /**< LPWKPOL2B_26_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_26_RISING (MXC_V_PWRSEQ_LPWKPOL2B_26_RISING << MXC_F_PWRSEQ_LPWKPOL2B_26_POS) /**< LPWKPOL2B_26_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2B_26_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2B_26_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_26_FALLING (MXC_V_PWRSEQ_LPWKPOL2B_26_FALLING << MXC_F_PWRSEQ_LPWKPOL2B_26_POS) /**< LPWKPOL2B_26_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL2B_27_POS 22 /**< LPWKPOL2B_27 Position */ -#define MXC_F_PWRSEQ_LPWKPOL2B_27 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2B_27_POS)) /**< LPWKPOL2B_27 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL2B_27_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2B_27_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_27_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2B_27_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2B_27_POS) /**< LPWKPOL2B_27_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2B_27_RISING ((uint32_t)0x1UL) /**< LPWKPOL2B_27_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_27_RISING (MXC_V_PWRSEQ_LPWKPOL2B_27_RISING << MXC_F_PWRSEQ_LPWKPOL2B_27_POS) /**< LPWKPOL2B_27_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2B_27_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2B_27_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_27_FALLING (MXC_V_PWRSEQ_LPWKPOL2B_27_FALLING << MXC_F_PWRSEQ_LPWKPOL2B_27_POS) /**< LPWKPOL2B_27_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL2B_28_POS 24 /**< LPWKPOL2B_28 Position */ -#define MXC_F_PWRSEQ_LPWKPOL2B_28 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2B_28_POS)) /**< LPWKPOL2B_28 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL2B_28_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2B_28_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_28_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2B_28_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2B_28_POS) /**< LPWKPOL2B_28_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2B_28_RISING ((uint32_t)0x1UL) /**< LPWKPOL2B_28_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_28_RISING (MXC_V_PWRSEQ_LPWKPOL2B_28_RISING << MXC_F_PWRSEQ_LPWKPOL2B_28_POS) /**< LPWKPOL2B_28_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2B_28_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2B_28_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_28_FALLING (MXC_V_PWRSEQ_LPWKPOL2B_28_FALLING << MXC_F_PWRSEQ_LPWKPOL2B_28_POS) /**< LPWKPOL2B_28_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL2B_29_POS 26 /**< LPWKPOL2B_29 Position */ -#define MXC_F_PWRSEQ_LPWKPOL2B_29 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2B_29_POS)) /**< LPWKPOL2B_29 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL2B_29_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2B_29_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_29_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2B_29_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2B_29_POS) /**< LPWKPOL2B_29_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2B_29_RISING ((uint32_t)0x1UL) /**< LPWKPOL2B_29_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_29_RISING (MXC_V_PWRSEQ_LPWKPOL2B_29_RISING << MXC_F_PWRSEQ_LPWKPOL2B_29_POS) /**< LPWKPOL2B_29_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2B_29_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2B_29_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_29_FALLING (MXC_V_PWRSEQ_LPWKPOL2B_29_FALLING << MXC_F_PWRSEQ_LPWKPOL2B_29_POS) /**< LPWKPOL2B_29_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL2B_30_POS 28 /**< LPWKPOL2B_30 Position */ -#define MXC_F_PWRSEQ_LPWKPOL2B_30 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2B_30_POS)) /**< LPWKPOL2B_30 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL2B_30_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2B_30_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_30_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2B_30_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2B_30_POS) /**< LPWKPOL2B_30_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2B_30_RISING ((uint32_t)0x1UL) /**< LPWKPOL2B_30_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_30_RISING (MXC_V_PWRSEQ_LPWKPOL2B_30_RISING << MXC_F_PWRSEQ_LPWKPOL2B_30_POS) /**< LPWKPOL2B_30_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2B_30_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2B_30_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_30_FALLING (MXC_V_PWRSEQ_LPWKPOL2B_30_FALLING << MXC_F_PWRSEQ_LPWKPOL2B_30_POS) /**< LPWKPOL2B_30_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL2B_31_POS 30 /**< LPWKPOL2B_31 Position */ -#define MXC_F_PWRSEQ_LPWKPOL2B_31 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL2B_31_POS)) /**< LPWKPOL2B_31 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL2B_31_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL2B_31_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_31_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL2B_31_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL2B_31_POS) /**< LPWKPOL2B_31_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2B_31_RISING ((uint32_t)0x1UL) /**< LPWKPOL2B_31_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_31_RISING (MXC_V_PWRSEQ_LPWKPOL2B_31_RISING << MXC_F_PWRSEQ_LPWKPOL2B_31_POS) /**< LPWKPOL2B_31_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL2B_31_FALLING ((uint32_t)0x2UL) /**< LPWKPOL2B_31_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL2B_31_FALLING (MXC_V_PWRSEQ_LPWKPOL2B_31_FALLING << MXC_F_PWRSEQ_LPWKPOL2B_31_POS) /**< LPWKPOL2B_31_FALLING Setting */ - -/**@} end of group PWRSEQ_LPWKPOL2B_Register */ - -/** - * @ingroup pwrseq_registers - * @defgroup PWRSEQ_LPWKPOL3 PWRSEQ_LPWKPOL3 - * @brief Low Power Wakeup Polarity Select for GPIO3. + * @defgroup PWRSEQ_LPPWST PWRSEQ_LPPWST + * @brief Low Power Peripheral Wakeup Status Register. * @{ */ -#define MXC_F_PWRSEQ_LPWKPOL3_0_POS 0 /**< LPWKPOL3_0 Position */ -#define MXC_F_PWRSEQ_LPWKPOL3_0 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL3_0_POS)) /**< LPWKPOL3_0 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL3_0_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL3_0_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL3_0_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL3_0_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL3_0_POS) /**< LPWKPOL3_0_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL3_0_RISING ((uint32_t)0x1UL) /**< LPWKPOL3_0_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL3_0_RISING (MXC_V_PWRSEQ_LPWKPOL3_0_RISING << MXC_F_PWRSEQ_LPWKPOL3_0_POS) /**< LPWKPOL3_0_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL3_0_FALLING ((uint32_t)0x2UL) /**< LPWKPOL3_0_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL3_0_FALLING (MXC_V_PWRSEQ_LPWKPOL3_0_FALLING << MXC_F_PWRSEQ_LPWKPOL3_0_POS) /**< LPWKPOL3_0_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL3_1_POS 2 /**< LPWKPOL3_1 Position */ -#define MXC_F_PWRSEQ_LPWKPOL3_1 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL3_1_POS)) /**< LPWKPOL3_1 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL3_1_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL3_1_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL3_1_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL3_1_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL3_1_POS) /**< LPWKPOL3_1_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL3_1_RISING ((uint32_t)0x1UL) /**< LPWKPOL3_1_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL3_1_RISING (MXC_V_PWRSEQ_LPWKPOL3_1_RISING << MXC_F_PWRSEQ_LPWKPOL3_1_POS) /**< LPWKPOL3_1_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL3_1_FALLING ((uint32_t)0x2UL) /**< LPWKPOL3_1_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL3_1_FALLING (MXC_V_PWRSEQ_LPWKPOL3_1_FALLING << MXC_F_PWRSEQ_LPWKPOL3_1_POS) /**< LPWKPOL3_1_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL3_2_POS 4 /**< LPWKPOL3_2 Position */ -#define MXC_F_PWRSEQ_LPWKPOL3_2 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL3_2_POS)) /**< LPWKPOL3_2 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL3_2_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL3_2_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL3_2_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL3_2_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL3_2_POS) /**< LPWKPOL3_2_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL3_2_RISING ((uint32_t)0x1UL) /**< LPWKPOL3_2_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL3_2_RISING (MXC_V_PWRSEQ_LPWKPOL3_2_RISING << MXC_F_PWRSEQ_LPWKPOL3_2_POS) /**< LPWKPOL3_2_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL3_2_FALLING ((uint32_t)0x2UL) /**< LPWKPOL3_2_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL3_2_FALLING (MXC_V_PWRSEQ_LPWKPOL3_2_FALLING << MXC_F_PWRSEQ_LPWKPOL3_2_POS) /**< LPWKPOL3_2_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL3_3_POS 6 /**< LPWKPOL3_3 Position */ -#define MXC_F_PWRSEQ_LPWKPOL3_3 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL3_3_POS)) /**< LPWKPOL3_3 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL3_3_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL3_3_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL3_3_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL3_3_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL3_3_POS) /**< LPWKPOL3_3_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL3_3_RISING ((uint32_t)0x1UL) /**< LPWKPOL3_3_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL3_3_RISING (MXC_V_PWRSEQ_LPWKPOL3_3_RISING << MXC_F_PWRSEQ_LPWKPOL3_3_POS) /**< LPWKPOL3_3_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL3_3_FALLING ((uint32_t)0x2UL) /**< LPWKPOL3_3_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL3_3_FALLING (MXC_V_PWRSEQ_LPWKPOL3_3_FALLING << MXC_F_PWRSEQ_LPWKPOL3_3_POS) /**< LPWKPOL3_3_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL3_4_POS 8 /**< LPWKPOL3_4 Position */ -#define MXC_F_PWRSEQ_LPWKPOL3_4 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL3_4_POS)) /**< LPWKPOL3_4 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL3_4_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL3_4_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL3_4_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL3_4_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL3_4_POS) /**< LPWKPOL3_4_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL3_4_RISING ((uint32_t)0x1UL) /**< LPWKPOL3_4_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL3_4_RISING (MXC_V_PWRSEQ_LPWKPOL3_4_RISING << MXC_F_PWRSEQ_LPWKPOL3_4_POS) /**< LPWKPOL3_4_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL3_4_FALLING ((uint32_t)0x2UL) /**< LPWKPOL3_4_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL3_4_FALLING (MXC_V_PWRSEQ_LPWKPOL3_4_FALLING << MXC_F_PWRSEQ_LPWKPOL3_4_POS) /**< LPWKPOL3_4_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL3_5_POS 10 /**< LPWKPOL3_5 Position */ -#define MXC_F_PWRSEQ_LPWKPOL3_5 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL3_5_POS)) /**< LPWKPOL3_5 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL3_5_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL3_5_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL3_5_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL3_5_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL3_5_POS) /**< LPWKPOL3_5_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL3_5_RISING ((uint32_t)0x1UL) /**< LPWKPOL3_5_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL3_5_RISING (MXC_V_PWRSEQ_LPWKPOL3_5_RISING << MXC_F_PWRSEQ_LPWKPOL3_5_POS) /**< LPWKPOL3_5_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL3_5_FALLING ((uint32_t)0x2UL) /**< LPWKPOL3_5_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL3_5_FALLING (MXC_V_PWRSEQ_LPWKPOL3_5_FALLING << MXC_F_PWRSEQ_LPWKPOL3_5_POS) /**< LPWKPOL3_5_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL3_6_POS 12 /**< LPWKPOL3_6 Position */ -#define MXC_F_PWRSEQ_LPWKPOL3_6 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL3_6_POS)) /**< LPWKPOL3_6 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL3_6_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL3_6_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL3_6_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL3_6_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL3_6_POS) /**< LPWKPOL3_6_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL3_6_RISING ((uint32_t)0x1UL) /**< LPWKPOL3_6_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL3_6_RISING (MXC_V_PWRSEQ_LPWKPOL3_6_RISING << MXC_F_PWRSEQ_LPWKPOL3_6_POS) /**< LPWKPOL3_6_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL3_6_FALLING ((uint32_t)0x2UL) /**< LPWKPOL3_6_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL3_6_FALLING (MXC_V_PWRSEQ_LPWKPOL3_6_FALLING << MXC_F_PWRSEQ_LPWKPOL3_6_POS) /**< LPWKPOL3_6_FALLING Setting */ - -#define MXC_F_PWRSEQ_LPWKPOL3_7_POS 14 /**< LPWKPOL3_7 Position */ -#define MXC_F_PWRSEQ_LPWKPOL3_7 ((uint32_t)(0x3UL << MXC_F_PWRSEQ_LPWKPOL3_7_POS)) /**< LPWKPOL3_7 Mask */ -#define MXC_V_PWRSEQ_LPWKPOL3_7_BOTH_EDGES ((uint32_t)0x0UL) /**< LPWKPOL3_7_BOTH_EDGES Value */ -#define MXC_S_PWRSEQ_LPWKPOL3_7_BOTH_EDGES (MXC_V_PWRSEQ_LPWKPOL3_7_BOTH_EDGES << MXC_F_PWRSEQ_LPWKPOL3_7_POS) /**< LPWKPOL3_7_BOTH_EDGES Setting */ -#define MXC_V_PWRSEQ_LPWKPOL3_7_RISING ((uint32_t)0x1UL) /**< LPWKPOL3_7_RISING Value */ -#define MXC_S_PWRSEQ_LPWKPOL3_7_RISING (MXC_V_PWRSEQ_LPWKPOL3_7_RISING << MXC_F_PWRSEQ_LPWKPOL3_7_POS) /**< LPWKPOL3_7_RISING Setting */ -#define MXC_V_PWRSEQ_LPWKPOL3_7_FALLING ((uint32_t)0x2UL) /**< LPWKPOL3_7_FALLING Value */ -#define MXC_S_PWRSEQ_LPWKPOL3_7_FALLING (MXC_V_PWRSEQ_LPWKPOL3_7_FALLING << MXC_F_PWRSEQ_LPWKPOL3_7_POS) /**< LPWKPOL3_7_FALLING Setting */ +#define MXC_F_PWRSEQ_LPPWST_RESET_POS 17 /**< LPPWST_RESET Position */ +#define MXC_F_PWRSEQ_LPPWST_RESET ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_RESET_POS)) /**< LPPWST_RESET Mask */ -/**@} end of group PWRSEQ_LPWKPOL3_Register */ +/**@} end of group PWRSEQ_LPPWST_Register */ #ifdef __cplusplus } diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sir_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sir_regs.h index 995328c05c0..400ce986434 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sir_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sir_regs.h @@ -74,10 +74,7 @@ extern "C" { typedef struct { __I uint32_t sistat; /**< \b 0x00: SIR SISTAT Register */ __I uint32_t addr; /**< \b 0x04: SIR ADDR Register */ - __R uint32_t rsv_0x8_0x47[16]; - __IO uint32_t btleldotrim; /**< \b 0x48: SIR BTLELDOTRIM Register */ - __R uint32_t rsv_0x4c_0xff[45]; - __I uint32_t fstat; /**< \b 0x100: SIR FSTAT Register */ + __R uint32_t rsv_0x8_0x103[63]; __I uint32_t sfstat; /**< \b 0x104: SIR SFSTAT Register */ } mxc_sir_regs_t; @@ -90,8 +87,6 @@ typedef struct { */ #define MXC_R_SIR_SISTAT ((uint32_t)0x00000000UL) /**< Offset from SIR Base Address: 0x0000 */ #define MXC_R_SIR_ADDR ((uint32_t)0x00000004UL) /**< Offset from SIR Base Address: 0x0004 */ -#define MXC_R_SIR_BTLELDOTRIM ((uint32_t)0x00000048UL) /**< Offset from SIR Base Address: 0x0048 */ -#define MXC_R_SIR_FSTAT ((uint32_t)0x00000100UL) /**< Offset from SIR Base Address: 0x0100 */ #define MXC_R_SIR_SFSTAT ((uint32_t)0x00000104UL) /**< Offset from SIR Base Address: 0x0104 */ /**@} end of group sir_registers */ @@ -122,45 +117,17 @@ typedef struct { /**@} end of group SIR_ADDR_Register */ -/** - * @ingroup sir_registers - * @defgroup SIR_BTLELDOTRIM SIR_BTLELDOTRIM - * @brief BTLE LDO Trim register. - * @{ - */ -#define MXC_F_SIR_BTLELDOTRIM_TX_POS 0 /**< BTLELDOTRIM_TX Position */ -#define MXC_F_SIR_BTLELDOTRIM_TX ((uint32_t)(0x1FUL << MXC_F_SIR_BTLELDOTRIM_TX_POS)) /**< BTLELDOTRIM_TX Mask */ - -#define MXC_F_SIR_BTLELDOTRIM_RX_POS 8 /**< BTLELDOTRIM_RX Position */ -#define MXC_F_SIR_BTLELDOTRIM_RX ((uint32_t)(0x1FUL << MXC_F_SIR_BTLELDOTRIM_RX_POS)) /**< BTLELDOTRIM_RX Mask */ - -/**@} end of group SIR_BTLELDOTRIM_Register */ - -/** - * @ingroup sir_registers - * @defgroup SIR_FSTAT SIR_FSTAT - * @brief Function Status register. - * @{ - */ -#define MXC_F_SIR_FSTAT_FPU_POS 0 /**< FSTAT_FPU Position */ -#define MXC_F_SIR_FSTAT_FPU ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_FPU_POS)) /**< FSTAT_FPU Mask */ - -#define MXC_F_SIR_FSTAT_ADC_POS 2 /**< FSTAT_ADC Position */ -#define MXC_F_SIR_FSTAT_ADC ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_ADC_POS)) /**< FSTAT_ADC Mask */ - -#define MXC_F_SIR_FSTAT_SEMA_POS 7 /**< FSTAT_SEMA Position */ -#define MXC_F_SIR_FSTAT_SEMA ((uint32_t)(0x1UL << MXC_F_SIR_FSTAT_SEMA_POS)) /**< FSTAT_SEMA Mask */ - -/**@} end of group SIR_FSTAT_Register */ - /** * @ingroup sir_registers * @defgroup SIR_SFSTAT SIR_SFSTAT * @brief Security function status register. * @{ */ -#define MXC_F_SIR_SFSTAT_SECBOOT_POS 0 /**< SFSTAT_SECBOOT Position */ -#define MXC_F_SIR_SFSTAT_SECBOOT ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_SECBOOT_POS)) /**< SFSTAT_SECBOOT Mask */ +#define MXC_F_SIR_SFSTAT_SECBOOT_EN_POS 0 /**< SFSTAT_SECBOOT_EN Position */ +#define MXC_F_SIR_SFSTAT_SECBOOT_EN ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_SECBOOT_EN_POS)) /**< SFSTAT_SECBOOT_EN Mask */ + +#define MXC_F_SIR_SFSTAT_SECEXT_EN_POS 1 /**< SFSTAT_SECEXT_EN Position */ +#define MXC_F_SIR_SFSTAT_SECEXT_EN ((uint32_t)(0x1UL << MXC_F_SIR_SFSTAT_SECEXT_EN_POS)) /**< SFSTAT_SECEXT_EN Mask */ /**@} end of group SIR_SFSTAT_Register */ diff --git a/Libraries/PeriphDrivers/Source/CRC/crc_reva.svd b/Libraries/PeriphDrivers/Source/CRC/crc_reva.svd index 0ac8fba30dd..f6c9dee7bb6 100644 --- a/Libraries/PeriphDrivers/Source/CRC/crc_reva.svd +++ b/Libraries/PeriphDrivers/Source/CRC/crc_reva.svd @@ -69,9 +69,7 @@ - 2 - 2 - DATAIN16[%s] + DATAIN16 CRC Data Input 0x0004 16 @@ -87,9 +85,7 @@ - 4 - 1 - DATAIN8[%s] + DATAIN8 CRC Data Input 0x0004 8 diff --git a/Libraries/PeriphDrivers/Source/LP/pwrseq_me30.svd b/Libraries/PeriphDrivers/Source/LP/pwrseq_me30.svd index 3f6b4a158fa..3ace90f01b1 100644 --- a/Libraries/PeriphDrivers/Source/LP/pwrseq_me30.svd +++ b/Libraries/PeriphDrivers/Source/LP/pwrseq_me30.svd @@ -19,24 +19,11 @@ RAMRET_EN System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 0 - 4 + 5 - OVR - Operating Voltage Range - 4 - 2 - - - 1_1V - 1.1V - 2 - - - - - RETREG_EN - Retention Regulator Enable. This bit controls the retention regulator in BACKUP mode. + FAST + Fast mode. 8 1 @@ -52,24 +39,6 @@ - - FASTWK_EN - Fast Wake-Up Mode. This bit enables fast wake-up from DeepSleep mode. (5uS typical). - 10 - 1 - - - dis - Disabled. - 0 - - - en - Enabled. - 1 - - - BG_DIS Bandgap OFF. This controls the System Bandgap in DeepSleep mode. @@ -89,136 +58,10 @@ - PORVDDCMON_DIS - VDDC (VCore) Power-On Reset Monitor Disable. This bit controls the Power-On Reset monitor on VDDC supply in DeepSleep and BACKUP mode. - 12 - 1 - - - VDDIOHHVMON_DIS - VDDIOH High Voltage Monitor Disable. This bit controls the power monitor on VDDIOH supply in all operating modes. - 17 - 1 - - - VDDIOHVMON_DIS - VDDIO High Voltage Monitor Disable. This bit controls the power monitor on VDDIO supply in all operating modes. - 18 - 1 - - - VCOREHVMON_DIS - VCORE High Voltage Monitor Disable. This bit controls the power monitor on VCORE supply in all operating modes. - 19 - 1 - - - VDDCMON_DIS - VDDC (Vcore) Monitor Disable. This bit controls the power monitor on the VCore supply in all operating modes. - 20 - 1 - - - en - Enable if Bandgap is ON (default) - 0 - - - dis - Disabled. - 1 - - - - - VRTCMON_DIS - VRTC Monitor Disable. This bit controls the power monitor on the Always-On Supply in all operating modes. - 21 - 1 - - - en - Enable if Bandgap is ON (default) - 0 - - - dis - Disabled. - 1 - - - - - VDDAMON_DIS - VDDA Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes. - 22 - 1 - - - en - Enable if Bandgap is ON (default) - 0 - - - dis - Disabled. - 1 - - - - - VDDIOMON_DIS - VDDIO Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes. - 23 - 1 - - - en - Enable if Bandgap is ON (default) - 0 - - - dis - Disabled. - 1 - - - - - VDDIOHMON_DIS - VDDIOH Monitor Disable. This bit controls the power monitor of the Analog Supply in all operating modes. - 24 - 1 - - - en - Enable if Bandgap is ON (default) - 0 - - - dis - Disabled. - 1 - - - - - VDDBMON_DIS - VDDB Monitor Disable. This bit controls the Power-On Reset monitor on VDDB supply in all operating mods. - 27 + LPWKFL_CLR + LP wakeup flag register clear. + 31 1 - - - dis - Disabled. - 0 - - - en - Enabled. - 1 - - @@ -228,10 +71,10 @@ 0x04 - ALL + PINS Wakeup Flags. 0 - 31 + 12 @@ -241,471 +84,50 @@ 0x08 - ALL + PINS Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. 0 - 31 + 12 - + LPWKFL1 Low Power I/O Wakeup Status Register 1. This register indicates the low power wakeup status for GPIO1. 0x0C + + + PINS + Wakeup Flags. + 0 + 12 + + - + LPWKEN1 Low Power I/O Wakeup Enable Register 1. This register enables low power wakeup functionality for GPIO1. 0x10 - - - LPWKFL2 - Low Power I/O Wakeup Status Register 2. This register indicates the low power wakeup status for GPIO2. - 0x14 - - - LPWKEN2 - Low Power I/O Wakeup Enable Register 2. This register enables low power wakeup functionality for GPIO2. - 0x18 - - - LPWKFL3 - Low Power I/O Wakeup Status Register 3. This register indicates the low power wakeup status for GPIO3. - 0x1C - - - LPWKEN3 - Low Power I/O Wakeup Enable Register 3. This register enables low power wakeup functionality for GPIO3. - 0x20 - - - LPPWKFL - Low Power Peripheral Wakeup Status Register. - 0x30 - USBLS - USB UTMI Linestate Detect Wakeup Flag (write one to clear). One or both of these bits will be set when the USB bus activity causes the linestate to change and the device to wake while USB wakeup is enabled using PMLUSBWKEN. + PINS + Enable wakeup. These bits allow wakeup from the corresponding GPIO pin (s) on transition (s) from low to high or high to low when PM.GPIOWKEN is set. Wakeup status is indicated in PPWKST register. 0 2 - - AINCOMP0 - Analog Input Comparator Wakeup Flag. - 4 - 1 - - - USBVBUS - USB VBUS Detect Wakeup Flag (write one to clear). This bit will be set when the USB power supply is powered on or powered off. - 2 - 1 - - - BACKUP - Battery Back Wakeup Flag (write one to clear). This bit will be set when exiting Battery Backup Mode. - 16 - 1 - - - RSTDET - Reset Detect Wakeup Flag (write one to clear). This bit will be set when the external reset causes wakeup - 17 - 1 - - LPPWKEN - Low Power Peripheral Wakeup Enable Register. - 0x34 + LPPWST + Low Power Peripheral Wakeup Status Register. + 0x30 - USBLS - USB UTMI Linestate Detect Wakeup Enable. These bits allow wakeup from the corresponding USB linestate signal (s) on transition (s) from low to high or high to low when PM.USBWKEN is set. - 0 - 2 - - - USBVBUS - USB VBUS Detect Wakeup Enable. This bit allows wakeup from the USB power supply on or off status. - 2 - 1 - - - AINCOMP0 - AINCOMP0 Wakeup Enable. This bit allows wakeup from the AINCOMP0. - 4 - 1 - - - WDT0 - WDT0 Wakeup Enable. This bit allows wakeup from the WDT0. - 8 - 1 - - - WDT1 - WDT1 Wakeup Enable. This bit allows wakeup from the WDT1. - 9 - 1 - - - CPU1 - CPU1 Wakeup Enable. This bit allows wakeup from the CPU1. - 10 - 1 - - - TMR0 - TMR0 Wakeup Enable. This bit allows wakeup from the TMR0. - 11 - 1 - - - TMR1 - TMR1 Wakeup Enable. This bit allows wakeup from the TMR1. - 12 - 1 - - - TMR2 - TMR2 Wakeup Enable. This bit allows wakeup from the TMR2. - 13 - 1 - - - TMR3 - TMR3 Wakeup Enable. This bit allows wakeup from the TMR3. - 14 - 1 - - - TMR4 - TMR4 Wakeup Enable. This bit allows wakeup from the TMR4. - 15 - 1 - - - TMR5 - TMR5 Wakeup Enable. This bit allows wakeup from the TMR5. - 16 - 1 - - - UART0 - UART0 Wakeup Enable. This bit allows wakeup from the UART0. + RESET + Reset Detected Wakeup Flag. 17 1 - - UART1 - UART1 Wakeup Enable. This bit allows wakeup from the UART1. - 18 - 1 - - - UART2 - UART2 Wakeup Enable. This bit allows wakeup from the UART2. - 19 - 1 - - - UART3 - UART3 Wakeup Enable. This bit allows wakeup from the UART3. - 20 - 1 - - - I2C0 - I2C0 Wakeup Enable. This bit allows wakeup from the I2C0. - 21 - 1 - - - I2C1 - I2C1 Wakeup Enable. This bit allows wakeup from the I2C1. - 22 - 1 - - - I2C2 - I2C2 Wakeup Enable. This bit allows wakeup from the I2C2. - 23 - 1 - - - I2S - I2S Wakeup Enable. This bit allows wakeup from the I2S. - 24 - 1 - - - SPI1 - SPI1 Wakeup Enable. This bit allows wakeup from the SPI1. - 25 - 1 - - - LPCMP - LPCMP Wakeup Enable. This bit allows wakeup from the LPCMP. - 26 - 1 - - - - - LPMEMSD - Low Power Memory Shutdown Control. - 0x40 - - - RAM0 - System RAM block 0 Shut Down. - 0 - 1 - - - normal - Normal Operating Mode. - 0 - - - shutdown - Shutdown Mode. - 1 - - - - - RAM1 - System RAM block 1 Shut Down. - 1 - 1 - - - normal - Normal Operating Mode. - 0 - - - shutdown - Shutdown Mode. - 1 - - - - - RAM2 - System RAM block 2 Shut Down. - 2 - 1 - - - normal - Normal Operating Mode. - 0 - - - shutdown - Shutdown Mode. - 1 - - - - - RAM3 - System RAM block 3 Shut Down. - 3 - 1 - - - normal - Normal Operating Mode. - 0 - - - shutdown - Shutdown Mode. - 1 - - - - - RAM4 - System RAM block 4 Shut Down. - 4 - 1 - - - normal - Normal Operating Mode. - 0 - - - shutdown - Shutdown Mode. - 1 - - - - - RAM5 - System RAM block 5 Shut Down. - 5 - 1 - - - normal - Normal Operating Mode. - 0 - - - shutdown - Shutdown Mode. - 1 - - - - - ICC - Instruction Cache RAM Shut Down. - 7 - 1 - - - normal - Normal Operating Mode. - 0 - - - shutdown - Shutdown Mode. - 1 - - - - - ICCXIP - XiP Instruction Cache RAM Shut Down. - 8 - 1 - - - normal - Normal Operating Mode. - 0 - - - shutdown - Shutdown Mode. - 1 - - - - - SRCC - System Cache RAM Shut Down. - 9 - 1 - - - normal - Normal Operating Mode. - 0 - - - shutdown - Shutdown Mode. - 1 - - - - - USBFIFO - USB FIFO Shut Down. - 11 - 1 - - - normal - Normal Operating Mode. - 0 - - - shutdown - Shutdown Mode. - 1 - - - - - ROM0 - ROM0 Shut Down. (CPU0 ROM) - 12 - 1 - - - normal - Normal Operating Mode. - 0 - - - shutdown - Shutdown Mode. - 1 - - - - - MEU - MEU MEM Shut Down. - 13 - 1 - - - normal - Normal Operating Mode. - 0 - - - shutdown - Shutdown Mode. - 1 - - - - - ROM1 - ROM1 Shut Down. - 15 - 1 - - - normal - Normal Operating Mode. - 0 - - - shutdown - Shutdown Mode. - 1 - - - - - - - LPVDDPD - Low Power VDD Domain Power Down Control. - 0x44 - - - BTLE - Power Down. - 1 - 1 - @@ -718,2447 +140,6 @@ General Purpose Register 1 0x4C - - LPWKPOL0A - Low Power Wakeup Polarity Select for GPIO0. - 0x50 - - - 0 - Polarity Select for Wakeup Events for Pin 0. - 0 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 1 - Polarity Select for Wakeup Events for Pin 1. - 2 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 2 - Polarity Select for Wakeup Events for Pin 2. - 4 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 3 - Polarity Select for Wakeup Events for Pin 3. - 6 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 4 - Polarity Select for Wakeup Events for Pin 4. - 8 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 5 - Polarity Select for Wakeup Events for Pin 5. - 10 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 6 - Polarity Select for Wakeup Events for Pin 6. - 12 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 7 - Polarity Select for Wakeup Events for Pin 7. - 14 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 8 - Polarity Select for Wakeup Events for Pin 8. - 16 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 9 - Polarity Select for Wakeup Events for Pin 9. - 18 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 10 - Polarity Select for Wakeup Events for Pin 10. - 20 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 11 - Polarity Select for Wakeup Events for Pin 11. - 22 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 12 - Polarity Select for Wakeup Events for Pin 12. - 24 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 13 - Polarity Select for Wakeup Events for Pin 13. - 26 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 14 - Polarity Select for Wakeup Events for Pin 14. - 28 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 15 - Polarity Select for Wakeup Events for Pin 15. - 30 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - - - LPWKPOL0B - Low Power Wakeup Polarity Select for GPIO0. - 0x54 - - - 16 - Polarity Select for Wakeup Events for Pin 16. - 0 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 17 - Polarity Select for Wakeup Events for Pin 17. - 2 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 18 - Polarity Select for Wakeup Events for Pin 18. - 4 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 19 - Polarity Select for Wakeup Events for Pin 19. - 6 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 20 - Polarity Select for Wakeup Events for Pin 20. - 8 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 21 - Polarity Select for Wakeup Events for Pin 21. - 10 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 22 - Polarity Select for Wakeup Events for Pin 22. - 12 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 23 - Polarity Select for Wakeup Events for Pin 23. - 14 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 24 - Polarity Select for Wakeup Events for Pin 24. - 16 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 25 - Polarity Select for Wakeup Events for Pin 25. - 18 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 26 - Polarity Select for Wakeup Events for Pin 26. - 20 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 27 - Polarity Select for Wakeup Events for Pin 27. - 22 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 28 - Polarity Select for Wakeup Events for Pin 28. - 24 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 29 - Polarity Select for Wakeup Events for Pin 29. - 26 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 30 - Polarity Select for Wakeup Events for Pin 30. - 28 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 31 - Polarity Select for Wakeup Events for Pin 31. - 30 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - - - LPWKPOL1A - Low Power Wakeup Polarity Select for GPIO1. - 0x58 - - - 0 - Polarity Select for Wakeup Events for Pin 0. - 0 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 1 - Polarity Select for Wakeup Events for Pin 1. - 2 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 2 - Polarity Select for Wakeup Events for Pin 2. - 4 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 3 - Polarity Select for Wakeup Events for Pin 3. - 6 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 4 - Polarity Select for Wakeup Events for Pin 4. - 8 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 5 - Polarity Select for Wakeup Events for Pin 5. - 10 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 6 - Polarity Select for Wakeup Events for Pin 6. - 12 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 7 - Polarity Select for Wakeup Events for Pin 7. - 14 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 8 - Polarity Select for Wakeup Events for Pin 8. - 16 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 9 - Polarity Select for Wakeup Events for Pin 9. - 18 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 10 - Polarity Select for Wakeup Events for Pin 10. - 20 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 11 - Polarity Select for Wakeup Events for Pin 11. - 22 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 12 - Polarity Select for Wakeup Events for Pin 12. - 24 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 13 - Polarity Select for Wakeup Events for Pin 13. - 26 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 14 - Polarity Select for Wakeup Events for Pin 14. - 28 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 15 - Polarity Select for Wakeup Events for Pin 15. - 30 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - - - LPWKPOL1B - Low Power Wakeup Polarity Select for GPIO1. - 0x5C - - - 16 - Polarity Select for Wakeup Events for Pin 16. - 0 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 17 - Polarity Select for Wakeup Events for Pin 17. - 2 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 18 - Polarity Select for Wakeup Events for Pin 18. - 4 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 19 - Polarity Select for Wakeup Events for Pin 19. - 6 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 20 - Polarity Select for Wakeup Events for Pin 20. - 8 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 21 - Polarity Select for Wakeup Events for Pin 21. - 10 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 22 - Polarity Select for Wakeup Events for Pin 22. - 12 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 23 - Polarity Select for Wakeup Events for Pin 23. - 14 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 24 - Polarity Select for Wakeup Events for Pin 24. - 16 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 25 - Polarity Select for Wakeup Events for Pin 25. - 18 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 26 - Polarity Select for Wakeup Events for Pin 26. - 20 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 27 - Polarity Select for Wakeup Events for Pin 27. - 22 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 28 - Polarity Select for Wakeup Events for Pin 28. - 24 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 29 - Polarity Select for Wakeup Events for Pin 29. - 26 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 30 - Polarity Select for Wakeup Events for Pin 30. - 28 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 31 - Polarity Select for Wakeup Events for Pin 31. - 30 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - - - LPWKPOL2A - Low Power Wakeup Polarity Select for GPIO2. - 0x60 - - - 0 - Polarity Select for Wakeup Events for Pin 0. - 0 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 1 - Polarity Select for Wakeup Events for Pin 1. - 2 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 2 - Polarity Select for Wakeup Events for Pin 2. - 4 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 3 - Polarity Select for Wakeup Events for Pin 3. - 6 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 4 - Polarity Select for Wakeup Events for Pin 4. - 8 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 5 - Polarity Select for Wakeup Events for Pin 5. - 10 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 6 - Polarity Select for Wakeup Events for Pin 6. - 12 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 7 - Polarity Select for Wakeup Events for Pin 7. - 14 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 8 - Polarity Select for Wakeup Events for Pin 8. - 16 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 9 - Polarity Select for Wakeup Events for Pin 9. - 18 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 10 - Polarity Select for Wakeup Events for Pin 10. - 20 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 11 - Polarity Select for Wakeup Events for Pin 11. - 22 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 12 - Polarity Select for Wakeup Events for Pin 12. - 24 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 13 - Polarity Select for Wakeup Events for Pin 13. - 26 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 14 - Polarity Select for Wakeup Events for Pin 14. - 28 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 15 - Polarity Select for Wakeup Events for Pin 15. - 30 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - - - LPWKPOL2B - Low Power Wakeup Polarity Select for GPIO2. - 0x64 - - - 16 - Polarity Select for Wakeup Events for Pin 16. - 0 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 17 - Polarity Select for Wakeup Events for Pin 17. - 2 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 18 - Polarity Select for Wakeup Events for Pin 18. - 4 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 19 - Polarity Select for Wakeup Events for Pin 19. - 6 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 20 - Polarity Select for Wakeup Events for Pin 20. - 8 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 21 - Polarity Select for Wakeup Events for Pin 21. - 10 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 22 - Polarity Select for Wakeup Events for Pin 22. - 12 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 23 - Polarity Select for Wakeup Events for Pin 23. - 14 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 24 - Polarity Select for Wakeup Events for Pin 24. - 16 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 25 - Polarity Select for Wakeup Events for Pin 25. - 18 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 26 - Polarity Select for Wakeup Events for Pin 26. - 20 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 27 - Polarity Select for Wakeup Events for Pin 27. - 22 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 28 - Polarity Select for Wakeup Events for Pin 28. - 24 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 29 - Polarity Select for Wakeup Events for Pin 29. - 26 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 30 - Polarity Select for Wakeup Events for Pin 30. - 28 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 31 - Polarity Select for Wakeup Events for Pin 31. - 30 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - - - LPWKPOL3 - Low Power Wakeup Polarity Select for GPIO3. - 0x68 - - - 0 - Polarity Select for Wakeup Events for Pin 0. - 0 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 1 - Polarity Select for Wakeup Events for Pin 1. - 2 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 2 - Polarity Select for Wakeup Events for Pin 2. - 4 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 3 - Polarity Select for Wakeup Events for Pin 3. - 6 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 4 - Polarity Select for Wakeup Events for Pin 4. - 8 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 5 - Polarity Select for Wakeup Events for Pin 5. - 10 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 6 - Polarity Select for Wakeup Events for Pin 6. - 12 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - 7 - Polarity Select for Wakeup Events for Pin 7. - 14 - 2 - - - BOTH_EDGES - Both Edges. - 0 - - - RISING - Rising Edge. - 1 - - - FALLING - Falling Edge. - 2 - - - - - diff --git a/Libraries/PeriphDrivers/Source/SYS/SVD/fcr_me30.svd b/Libraries/PeriphDrivers/Source/SYS/SVD/fcr_me30.svd index eab7c51a325..2a8d1e3840a 100644 --- a/Libraries/PeriphDrivers/Source/SYS/SVD/fcr_me30.svd +++ b/Libraries/PeriphDrivers/Source/SYS/SVD/fcr_me30.svd @@ -17,171 +17,21 @@ read-write - USBCLKSEL - USB External Core Clock Select. - 16 - 1 - - - sys - Generated clock from system clock. - 0 - - - dig - Digital clock from a GPIO. - 1 - - - - - I2C0DGEN0 - I2C0 SDA Glitch Filter Enable. - 20 - 1 - - - dis - Filter disabled. - 0 - - - en - Filter enabled. - 1 - - - - - I2C0DGEN1 - I2C0 SCL Glitch Filter Enable. - 21 - 1 - - - dis - Filter disabled. - 0 - - - en - Filter enabled. - 1 - - - - - I2C1DGEN0 - I2C1 SDA Glitch Filter Enable. - 22 - 1 - - - dis - Filter disabled. - 0 - - - en - Filter enabled. - 1 - - - - - I2C1DGEN1 - I2C1 SCL Glitch Filter Enable. - 23 - 1 - - - dis - Filter disabled. - 0 - - - en - Filter enabled. - 1 - - - - - I2C2ADGEN0 - I2C2 AF2 SDA Glitch Filter Enable. - 24 - 1 - - - dis - Filter disabled. - 0 - - - en - Filter enabled. - 1 - - - - - I2C2ADGEN1 - I2C2 AF2 SCL Glitch Filter Enable. - 25 - 1 - - - dis - Filter disabled. - 0 - - - en - Filter enabled. - 1 - - - - - I2C2BDGEN0 - I2C2 AF3 SDA Glitch Filter Enable. - 26 - 1 - - - dis - Filter disabled. - 0 - - - en - Filter enabled. - 1 - - + BTLELDO_TX + BTLE LDO TX Trim. + 0 + 5 - I2C2BDGEN1 - I2C2 AF3 SCL Glitch Filter Enable. - 27 - 1 - - - dis - Filter disabled. - 0 - - - en - Filter enabled. - 1 - - + BTLELDO_RX + BTLE LDO RX Trim. + 8 + 5 - I2C2CDGEN0 - I2C2 AF4 SDA Glitch Filter Enable - 28 + I3CDGEN0 + I3C SDA Glitch Filter Enable. + 20 1 @@ -197,9 +47,9 @@ - I2C2CDGEN1 - I2C2 AF4 SCL Glitch Filter Enable - 29 + I3CDGEN1 + I3C SCL Glitch Filter Enable. + 21 1 @@ -307,8 +157,8 @@ 12 - AC_TRIM - 150MHz HFIO Auto Calibration Trim + AC_TRIM_OUT + IPO Auto Calibration Trim 23 9 @@ -321,58 +171,10 @@ read-write - NFC_FWD_EN - Enabled FWD mode for NFC block + AC_INIT_TRIM + IPO Trim Automatic Calibration Initial Trim. 0 - 1 - - - NFC_CLK_EN - Enabled the NFC blocks clock divider in Analog - 1 - 1 - - - NFC_FWD_TX_DATA_OVR - FWD input for NFC block - 2 - 1 - - - XO_EN_DGL - TBD - 3 - 1 - - - RX_BIAS_PD - Power down enable for NFC receiver analog block - 4 - 1 - - - RX_BIAS_EN - Enable the NFC receiver analog blocks - 5 - 1 - - - RX_TM_VBG_VABUS - TBD - 6 - 1 - - - RX_TM_BIAS - TBD - 7 - 1 - - - NFC_FWD_DOUT - FWD output from FNC block - 8 - 1 + 9 @@ -383,70 +185,66 @@ read-write - DONECNT - Auto-calibration Done Counter Setting. + AC_RUNTIME + IPO Trim Autocal Run Time 0 8 - - - - GP - General Purpose Register. - 0x1C - read-write - - GP - General Purpose. - 0 - 32 + AC_DIV + IPO Trim Automatic Calibration Divide Factor. + 8 + 13 - MSRTRIM - MSR Trim Register. - 0x20 + ERFOKS + ERFO Kick Start Register. + 0x18 read-write - R1 - MSR Trim R1. + CNT + Kick Start ERFO Counter. 0 - 2 + 7 - R2 - MSR Trim R2. - 2 - 3 + EN + Kick Start ERFO Enable. + 7 + 1 - - - - FLVFILT - Flash Low Voltage Filter Control Register. - 0x24 - read-write - - NUM - Defines the number of consecutive samples of FLV status that must be good for ROM to continue. - 0 - 8 + DRVSTR + Kick Start ERFO Drive Strength. + 8 + 3 - RATE - Defines the rate for ROM sampling of the FLV status. - 8 - 8 + X2_PLEN + ERFO Kick Start Enable Double Pulse Length. + 11 + 1 - DELAY - Defines the delay from change in system clock divider until ROM begins filtering process of the FLV status. - 16 - 8 + CLKSEL + Kick Start Clock Select for ERFO + 12 + 2 + + + NO_CLK + No kick start clock. + 0 + + + IPO + IPO. + 3 + + diff --git a/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me30.svd b/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me30.svd index 56fe920d300..09cbee89064 100644 --- a/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me30.svd +++ b/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me30.svd @@ -16,66 +16,6 @@ 0x00 0xFFFFFFFE - - BSTAP_EN - Boundary Scan TAP enable. When enabled, the JTAG port is connected to the Boundary Scan TAP. Otherwise, the port is connected to the ARM ICE function. This bit is reset by the POR. Reset value and access depend on the part number. - 0 - 1 - - - dis - Boundary Scan TAP port disabled. - 0 - - - en - Boundary Scan TAP port enabled. - 1 - - - - - SBUSARB - System bus abritration scheme. These bits are used to select between Fixed-burst abritration and Round-Robin scheme. The Round-Robin scheme is selected by default. These bits are reset by the system reset. - 1 - 2 - - - fix - Fixed Burst abritration. - 0 - - - round - Round-robin scheme. - 1 - - - - - FLASH_PAGE_FLIP - Flips the Flash bottom and top halves. (Depending on the total flash size, each half is either 256K or 512K). Initiating a flash page flip will cause a flush of both the data buffer on the DCODE bus and the internal instruction buffer. - 4 - 1 - - - normal - Physical layout matches logical layout. - 0 - - - swapped - Bottom half mapped to logical top half and vice versa. - 1 - - - - - FPU_DIS - Cortex M4 Floating Point Disable This bit is used to disable the floating-point unit of the Cortex-M4. - 5 - 1 - ICC_FLUSH Code Cache Flush. This bit is used to flush the code caches and the instruction buffer of the Cortex-M4. @@ -95,80 +35,8 @@ - SRCC_FLUSH - Data Cache Flush. The system cache (s) will be flushed when this bit is set. - 7 - 1 - - - normal - Normal System Cache Operation - 0 - - - flush - System Cache is flushed - 1 - - - - - SRCC_DIS - Data Cache Disable. The system cache (s) will be completely disabled when this bit is set. - 9 - 1 - - - en - Is enabled. - 0 - - - dis - Is Disabled. - 1 - - - - - CHKRES1 - ROM1 Checksum Result. This bit is only valid when the checksum is done and CCHK1 bit is cleared.. - 11 - 1 - - - complete - No operation/complete. - 0 - - - start - Start operation. - 1 - - - - - CCHK1 - Compute ROM1 Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. - 12 - 1 - - - complete - No operation/complete. - 0 - - - start - Start operation. - 1 - - - - - CCHK0 - Compute ROM0 Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. + CCHK + Compute ROM Checksum. This bit is self-cleared when calculation is completed. Once set, software clearing this bit is ignored and the bit will remain set until the operation is completed. 13 1 @@ -185,8 +53,8 @@ - CHKRES0 - ROM0 Checksum Result. This bit is only valid when the checksum is done and CCHK0 bit is cleared.. + CHKRES + ROM Checksum Result. This bit is only valid when the checksum is done and CCHK0 bit is cleared.. 15 1 @@ -216,156 +84,114 @@ 0x04 - DMA + DMA0 DMA Reset. 0 1 - - WDT0 + + WDT Watchdog Timer Reset. 1 1 - + GPIO0 GPIO0 Reset. Setting this bit to 1 resets GPIO0 pins to their default states. 2 1 - - GPIO1 - GPIO1 Reset. Setting this bit to 1 resets GPIO1 pins to their default states. - 3 - 1 - - + TMR0 - Timer0 Reset. Setting this bit to 1 resets Timer 0 blocks. + Timer0 Reset. 5 1 - + TMR1 - Timer1 Reset. Setting this bit to 1 resets Timer 1 blocks. + Timer1 Reset. 6 1 - + TMR2 - Timer2 Reset. Setting this bit to 1 resets Timer 2 blocks. + Timer2 Reset. 7 1 - + TMR3 - Timer3 Reset. Setting this bit to 1 resets Timer 3 blocks. + Timer3 Reset. 8 1 - + TMR4 - Timer4 Reset. Setting this bit to 1 resets Timer 4 blocks. + Timer4 Reset. 9 1 - + TMR5 - Timer5 Reset. Setting this bit to 1 resets Timer 5 blocks. + Timer5 Reset. 10 1 - - UART0 - UART0 Reset. Setting this bit to 1 resets all UART 0 blocks. + + UART + UART Reset. 11 1 - - UART1 - UART1 Reset. Setting this bit to 1 resets all UART 1 blocks. - 12 - 1 - - - SPI0 - SPI0 Reset. Setting this bit to 1 resets all SPI 0 blocks. + + SPI + SPI Reset. 13 1 - - SPI1 - SPI1 Reset. Setting this bit to 1 resets all SPI 1 blocks. - 14 - 1 - - - SPI2 - SPI2 Reset. Setting this bit to 1 resets all SPI 2 blocks. - 15 - 1 - - - I2C0 - I2C0 Reset. + + I3C + I3C Reset. 16 1 - + RTC Real Time Clock Reset. 17 1 - - TMR6 - Timer6 Reset. Setting this bit to 1 resets Timer 6 blocks. - 20 - 1 - - - TMR7 - Timer7 Reset. Setting this bit to 1 resets Timer 7 blocks. - 21 - 1 - - - SEMA - Semaphore Reset. - 22 + + BTLE + BTLE Reset. + 18 1 - + TRNG - TODO(5-2-2023): Remove this bit before release. TRNG Reset. Setting this bit resets the TRNG block. + TRNG Reset. 24 1 - - ADC - Analog to Digital Reset. - 26 - 1 - - - UART2 - UART2 Reset. Setting this bit to 1 resets all UART 2 blocks. - 28 + + DMA1 + DMA1 Reset. + 27 1 - + SOFT Soft Reset. Setting this bit to 1 resets everything except the CPU and the watchdog timer. 29 1 - + PERIPH Peripheral Reset. Setting this bit to 1 resets all peripherals. The CPU core, the watchdog timer, and all GPIO pins are unaffected by this reset. 30 1 - + SYS System Reset. Setting this bit to 1 resets the CPU core and all peripherals, including the watchdog timer. 31 @@ -379,34 +205,6 @@ 0x08 0x00000008 - - PCLK_DIV - PCLK Divider. - 3 - 3 - - - div1 - Divide by 1. - 0 - - - div2 - Divide by 2. - 1 - - - div4 - Divide by 4. - 2 - - - div8 - Divide by 8. - 3 - - - SYSCLK_DIV Prescaler Select. This 3 bit field sets the system operating frequency by controlling the prescaler that divides the output of the PLL0. @@ -462,8 +260,8 @@ 3 - ISO - Internal Secondary Oscilatior Clock + IPO + The internal Primary oscillator is used for the system clock. 0 @@ -476,11 +274,6 @@ 8kHz Internal Nano Ring Oscillator is used for the system clock. 3 - - IPO - The internal Primary oscillator is used for the system clock. - 4 - IBRO The internal Baud Rate oscillator is used for the system clock. @@ -491,6 +284,11 @@ 32kHz is used for the system clock. 6 + + EXTCLK + External Clock. + 7 + @@ -512,34 +310,6 @@ - - IPO_DIV - IPO clock divider - 14 - 2 - - - DIV1 - Divide 1. - 0 - - - DIV2 - Divide 2. - 1 - - - DIV4 - Divide 4. - 2 - - - DIV8 - Divide 8. - 3 - - - ERFO_EN 27MHz Crystal Oscillator Enable. @@ -564,15 +334,9 @@ 17 1 - - ISO_EN - 60MHz High Frequency Internal Reference Clock Enable. - 18 - 1 - IPO_EN - 96MHz High Frequency Internal Reference Clock Enable. + 50MHz High Frequency Internal Reference Clock Enable. 19 1 @@ -613,16 +377,10 @@ 25 1 - - ISO_RDY - 60MHz ISO Ready. - 26 - 1 - IPO_RDY Internal Primary Oscillator Ready. - 27 + 26 1 @@ -648,27 +406,22 @@ MODE Operating Mode. This two bit field selects the current operating mode for the device. Note that code execution only occurs during ACTIVE mode. 0 - 3 + 4 active Active Mode. 0 - - deepsleep - DeepSleep Mode. - 2 - - - shutdown - Shutdown Mode. - 3 - backup Backup Mode. - 4 + 9 + + + PDM + DeepSleep Mode. + 10 @@ -685,135 +438,62 @@ 1 - USB_WE - USB Wake Up Enable. This bit enables USB activity as wakeup source. - 6 + WUT_WE + Enable Wakeup Timer as wakeup source. + 7 1 - ERFO_PD - Radio Frequency oscilator Crystal Power Down. This bit selects the power state in DEEPSLEEP mode. - 12 + ERFO_BP + XTAL Bypass + 20 1 - active - Mode is Active. + normal + Normal 0 - deepsleep - Powered down in DEEPSLEEP. + bypass + Bypass 1 + + + + PCLKDIV + Peripheral Clock Divider. + 0x18 + + + ADCFRQ + ADC clock Frequency. These bits define the ADC clock frequency. FADC = FPCLK / (ADCFRQ). + 10 + 4 + - ISO_PD - Internal Secondary Oscilator Power Down. This bit selects the power state in DEEPSLEEP mode. - 15 - 1 + AONCLKDIV + Always-ON (AON) domain Clock Divider. These bits define the AON domain clock divider. + 14 + 2 - active - Mode is Active. + DIV4 + PCLK divide by 4. 0 - deepsleep - Powered down in DEEPSLEEP. + DIV8 + PCLK divide by 8. 1 - - - - IPO_PD - Internal Primary Oscilatory power down. This bit selects the power state in DEEPSLEEP mode. - 16 - 1 - - active - Mode is Active. - 0 - - - deepsleep - Powered down in DEEPSLEEP. - 1 - - - - - IBRO_PD - Internal Baud Rate Oscillator power down. This bit selects the power state in DEEPSLEEP mode. - 17 - 1 - - - active - Mode is Active. - 0 - - - deepsleep - Powered down in DEEPSLEEP. - 1 - - - - - ERFO_BP - XTAL Bypass - 20 - 1 - - - normal - Normal - 0 - - - bypass - Bypass - 1 - - - - - - - PCLKDIV - Peripheral Clock Divider. - 0x18 - 0x00000001 - - - ADCFRQ - ADC clock Frequency. These bits define the ADC clock frequency. FADC = FPCLK / (ADCFRQ). - 10 - 4 - - - AONCLKDIV - Always-ON (AON) domain Clock Divider. These bits define the AON domain clock divider. - 14 - 2 - - - DIV4 - PCLK divide by 4. - 0 - - - DIV8 - PCLK divide by 8. - 1 - - - DIV16 - PCLK divide by 16. - 2 + DIV16 + PCLK divide by 16. + 2 DIV32 @@ -848,50 +528,26 @@ - GPIO1 - GPIO1 Disable. - 1 - 1 - - - DMA - DMA Disable. + DMA0 + DMA0 Disable. 5 1 - SPI0 - SPI 0 Disable. + SPI + SPI Disable. 6 1 - SPI1 - SPI 1 Disable. - 7 - 1 - - - SPI2 - SPI 2 Disable. - 8 - 1 - - - UART0 - UART 0 Disable. + UART + UART Disable. 9 1 - UART1 - UART 1 Disable. - 10 - 1 - - - I2C0 - I2C 0 Disable. + I3C + I3C Disable. 13 1 @@ -931,36 +587,6 @@ 20 1 - - ADC - ADC Disable. - 23 - 1 - - - TMR6 - Timer 6 Disable. - 24 - 1 - - - TMR7 - Timer 7 Disable. - 25 - 1 - - - I2C1 - I2C 1 Disable. - 28 - 1 - - - PT - PT Clock Disable. - 29 - 1 - @@ -974,138 +600,6 @@ 0 3 - - SRAM_WS - SRAM Wait State Enable - 4 - 1 - - - ROM1_WS - ROM1 Wait State Enable - 7 - 1 - - - RAM0_WS - System RAM 0 Wait State Enable - 8 - 1 - - - RAM1_WS - System RAM 1 Wait State Enable - 9 - 1 - - - RAM2_WS - System RAM 2 Wait State Enable - 10 - 1 - - - RAM3_WS - System RAM 3 Wait State Enable - 11 - 1 - - - RAM4_WS - System RAM 4 Wait State Enable - 12 - 1 - - - RAM5_WS - System RAM 5 Wait State Enable - 13 - 1 - - - RAM0LS_EN - System RAM 0 Light Sleep Mode. - 16 - 1 - - - active - RAM is active. - 0 - - - light_sleep - RAM is in Light Sleep mode. - 1 - - - - - RAM1LS_EN - System RAM 1 Light Sleep Mode. - 17 - 1 - - - RAM2LS_EN - System RAM 2 Light Sleep Mode. - 18 - 1 - - - RAM3LS_EN - System RAM 3 Light Sleep Mode. - 19 - 1 - - - RAM4LS_EN - System RAM 4 Light Sleep Mode. - 20 - 1 - - - RAM5LS_EN - System RAM 5 Light Sleep Mode. - 21 - 1 - - - ICCLS_EN - ICache RAM Light Sleep Mode. - 24 - 1 - - - ICCXIPLS_EN - ICACHE-XIP RAM Light Sleep Mode. - 25 - 1 - - - SRCCLS_EN - SysCache RAM Light Sleep Mode. - 26 - 1 - - - USBLS_EN - USB FIFO Light Sleep Mode. - 28 - 1 - - - ROM0LS_EN - ROM0 Light Sleep Mode. - 29 - 1 - - - ROM1LS_EN - ROM1 Light Sleep Mode. - 30 - 1 - @@ -1114,7 +608,7 @@ 0x2C - RAM0 + SRAM0 System RAM Block 0. 0 1 @@ -1131,70 +625,34 @@ - - RAM1 + + SRAM1 System RAM Block 1. 1 1 - - RAM2 + + SRAM2 System RAM Block 2. 2 1 - - RAM3 + + SRAM3 System RAM Block 3. 3 1 - - RAM4 + + SRAM4 System RAM Block 4. 4 1 - - RAM5 - System RAM Block 5. - 5 - 1 - - - RAM6 - System RAM Block 6. - 6 - 1 - - + ICC - Instruction Cache. - 8 - 1 - - - ICCXIP - Instruction Cache XIP Data and Tag Ram zeroizatoin. - 9 - 1 - - - SRCCDATA - System Cache Data Ram Zeroization. - 10 - 1 - - - SRCCTAG - System Cache Tag Zeroization. - 11 - 1 - - - USBFIFO - USB FIFO Zeroization. - 13 + Internal Cache. + 5 1 @@ -1222,60 +680,6 @@ - - CODEAUTHERR - Code Authentication Error Flag. This bit indicates a code authentication error has occured in XiP interface. - 1 - 1 - - - norm - Normal Operating Condition. - 0 - - - code - Code Integrity Error. - 1 - - - - - DATAAUTHERR - Data Authentication Error Flag. This bit indicates a data authentication error has occured in XiP interface. - 2 - 1 - - - norm - Normal Operating Condition. - 0 - - - code - Code Integrity Error. - 1 - - - - - SCMEMF - System Cache Memory Fault Flag. This bit indicates a memory fault has occured in the System Cache while receiving data from the Hyperbus Interface. - 5 - 1 - - - norm - Normal Operating Condition. - 0 - - - memory - Memory Fault. - 1 - - - @@ -1284,83 +688,17 @@ 0x44 - I2C1 - I2C1 Reset. - 0 - 1 - - - PT - PT Reset. - 1 - 1 - - - OWIRE - OWIRE Reset. - 7 - 1 - - - WDT1 - WDT1 Reset. - 8 - 1 - - CRC CRC Reset. 9 1 - + AES AES Reset. 10 1 - - I2S - I2S Reset. - 13 - 1 - - - AC - AC Reset. - 14 - 1 - - - SEMA - Semaphore Reset. - 16 - 1 - - - I2C2 - I2C2 Reset. - 17 - 1 - - - UART3 - UART3 Reset. - 18 - 1 - - - UART4 - UART4 Reset. - 19 - 1 - - - UART5 - UART5 Reset. - 20 - 1 - @@ -1369,27 +707,9 @@ 0x48 - BTLE - Bluetooth Clock Disable. - 0 - 1 - - - en - Enable. - 0 - - - dis - Disable. - 1 - - - - - UART2 - UART2 Disable. - 1 + TRNG + TRNG Clock Disable. + 2 1 @@ -1404,82 +724,28 @@ - - TRNG - TRNG Disable. - 2 - 1 - - - WDT0 - WDT0 Clock Disable - 4 - 1 - - - WDT1 - WDT1 Clock Disable - 5 - 1 - - - SRCC - System Cache Clock Disable. - 7 - 1 - - - SEMA - Semaphore Clock Disable. - 9 - 1 - - - OWIRE - One-Wire Clock Disable. - 13 - 1 - - + CRC - CRC Clock Disable. + CRC Disable. 14 1 - + AES - AES Clock Disable. + AES Clock Disable 15 1 - - I2S - I2S Clock Disable. + + SPI + SPI Clock Disable 16 1 - - I2C2 - I2C2 Clock Disable - 21 - 1 - - - UART3 - UART3 Clock Disable - 22 - 1 - - - UART4 - UART4 Clock Disable - 23 - 1 - - - UART5 - UART5 Clock Disable - 24 + + WDT + WDT Clock Disable + 27 1 @@ -1490,14 +756,14 @@ 0x4C - DMA - Enable DMA event. When this bit is set, a DMA event will cause an RXEV event to wake the CPU from WFE sleep mode. + DMA0 + Enable DMA0 event. When this bit is set, a DMA0 event will cause an RXEV event to wake the CPU from WFE sleep mode. 0 1 - RX - Enable RXEV pin event. When this bit is set, a logic high of GPIO0[24] will cause an RXEV event to wake the CPU from WFE sleep mode. + DMA1 + Enable DMA1 event. When this bit is set, a DMA1 event will cause an RXEV event to wake the CPU from WFE sleep mode. 1 1 @@ -1546,31 +812,6 @@ - - CIE - Code Integrity Error Interrupt Enable. - 1 - 1 - - - SCMF - System Cache Memory Fault Interrupt Enable. - 5 - 1 - - - - - IPOCNT - IPO Warmup Count Register. - 0x58 - - - WMUPCNT - TBD - 0 - 10 - @@ -1578,121 +819,12 @@ ECC Error Register 0x64 - - RAM0 - ECC System RAM0 Error Flag. Write 1 to clear. - 0 - 1 - - - RAM1 - ECC System RAM1 Error Flag. Write 1 to clear. - 1 - 1 - - - RAM2 - ECC System RAM2 Error Flag. Write 1 to clear. - 2 - 1 - - - RAM3 - ECC System RAM3 Error Flag. Write 1 to clear. - 3 - 1 - - - RAM4 - ECC System RAM4 Error Flag. Write 1 to clear. - 4 - 1 - - - RAM5 - ECC System RAM5 Error Flag. Write 1 to clear. - 5 - 1 - - - ICC - ECC Icache0 Error Flag. Write 1 to clear. - 8 - 1 - - - ICCXIP - ECC SFCC Instruction Cache Error Flag. Write 1 to clear. - 10 - 1 - FLASH - ECC Flash0 Error Flag. Write 1 to clear. - 11 - 1 - - - - - ECCCED - ECC Not Double Error Detect Register - 0x68 - - - RAM0 - ECC System RAM0 Error Flag. Write 1 to clear. + ECC Flash Error Flag. Write 1 to clear. 0 1 - - RAM1 - ECC System RAM1 Not Double Error Detect. Write 1 to clear. - 1 - 1 - - - RAM2 - ECC System RAM2 Not Double Error Detect. Write 1 to clear. - 2 - 1 - - - RAM3 - ECC System RAM3 Not Double Error Detect. Write 1 to clear. - 3 - 1 - - - RAM4 - ECC System RAM4 Not Double Error Detect. Write 1 to clear. - 4 - 1 - - - RAM5 - ECC System RAM5 Not Double Error Detect. Write 1 to clear. - 5 - 1 - - - ICC - ECC Icache0 Not Double Error Detect. Write 1 to clear. - 8 - 1 - - - ICCXIP - ECC IcacheXIP Not Double Error Detect. Write 1 to clear. - 10 - 1 - - - FLASH - ECC Flash0 Not Double Error Detect. Write 1 to clear. - 11 - 1 - @@ -1700,54 +832,6 @@ ECC Interrupt Enable Register 0x6C - - RAM0 - ECC System RAM0 Interrupt Enable. - 0 - 1 - - - RAM1 - ECC System RAM1 Interrupt Enable. - 1 - 1 - - - RAM2 - ECC System RAM2 Interrupt Enable. - 2 - 1 - - - RAM3 - ECC System RAM3 Interrupt Enable. - 3 - 1 - - - RAM4 - ECC System RAM4 Interrupt Enable. - 4 - 1 - - - RAM5 - ECC System RAM5 Interrupt Enable. - 5 - 1 - - - ICC - ECC Icache0 Interrupt Enable. - 8 - 1 - - - ICCXIP - ECC IcacheXIP Interrupt Enable. - 10 - 1 - FLASH ECC Flash0 Interrupt Enable. @@ -1915,97 +999,6 @@ - - FLVRST - Flash Low Voltage Reset Control Register - 0x80 - - - EN - Flash Low Voltage Reset Enable. - 0 - 1 - - - - - FLVCLKCTRL - Flash Low Voltage Clock Control Register - 0x84 - - - DIV - Flash Low Voltage Clock Divider Select. - 0 - 2 - - - 512 - Divide 512. - 0 - - - 256 - Divide 256 - 1 - - - 128 - Divide 128 - 2 - - - 64 - Divide 64 - 3 - - - - - - - FLVSTAT - Flash Low Voltage Status Register - 0x88 - - - FLV - Live Flash Low Voltage Detect Status. - 0 - 1 - - - ONES - FLV Buffer contains all ones if supply is above safe operating range. - 6 - 1 - - - ZEROS - FLV Buffer contains all zeros if supply is below safe operating voltage. - 7 - 1 - - - ONES_FL - Sticky version of ONES status. Write 1 to clear. - 14 - 1 - - - ZEROS_FL - Sticky version of ZEROS status. Write 1 to clear. - 15 - 1 - - - BUF - 10 Sample History of FLV status. - 16 - 10 - - - \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/SYS/SVD/mcr_me30.svd b/Libraries/PeriphDrivers/Source/SYS/SVD/mcr_me30.svd index 070e1b59547..24efc05e758 100644 --- a/Libraries/PeriphDrivers/Source/SYS/SVD/mcr_me30.svd +++ b/Libraries/PeriphDrivers/Source/SYS/SVD/mcr_me30.svd @@ -16,41 +16,10 @@ 0x00 - RAM0 - ECC System RAM0 Enable. + FLASH + ECC Flash Enable. 0 1 - - - dis - disabled. - 0 - - - en - enabled. - 1 - - - - - - - IPOTRIM - IPO Manual Trim Register - 0x04 - - - VAL - Manual Trim Value. - 0 - 8 - - - RANGE - Trim Range Select. - 8 - 1 @@ -73,60 +42,11 @@ - - CMP_CTRL - Comparator Control Register. - 0x0C - - - EN - Comparator Enable. - 0 - 1 - - - POL - Polarity Select - 5 - 1 - - - INTR_EN - IRQ Enable. - 6 - 1 - - - OUT - Comparator Output State. - 14 - 1 - - - INTR_FL - IRQ Flag - 15 - 1 - - - CTRL Control Register 0x10 - - CMP_HYST - Comparator hysteresis control. - 0 - 2 - - - INRO_EN - INRO Enable. - 2 - 1 - ERTCO_EN ERTCO Enable. @@ -134,273 +54,84 @@ 1 - IBRO_EN - IBRO Enable. - 4 - 1 - - - ERTCO_LP_EN + ERTCO_IN_EN Enable 32K Oscillator input. 5 1 - - PADPUP_RST - Enable the Reset Pad Pull Up Resistors - 9 - 1 - - - 1m - 1MOhm Pullup - 0 - - - 25k - 25kOhm Pullup. - 1 - - - - - PADVDDIOHSEL_RST - Reset VIDDIOH Select. - 10 - 1 - - RTCRST - Reset Register. - 0x18 - - - RTC - RTC Reset. - 0 - 1 - - - - - RTCTRIM - RTC Trim Register. - 0x1C - - - X1 - RTC Trim X1. - 0 - 5 - - - X2 - RTC Trim X2. - 8 - 5 - - - - - GPIO3_CTRL - GPIO3 Pin Control Register. + GPIO1_CTRL + GPIO1 Pin Control Register. 0x20 - P30_OUT - GPIO3 Pin 0 Data Output. + P1_0_OUT + GPIO1 Pin 0 Data Output. 0 1 - P30_OUTEN - GPIO3 Pin 0 Output Enable. + P1_0_OUTEN + GPIO1 Pin 0 Output Enable. 1 1 - P30_PUPEN - GPIO3 Pin 0 Pull-up Enable. + P1_0_PUPEN + GPIO1 Pin 0 Pull-up Enable. 2 1 - P30_IN - GPIO3 Pin 0 Input Status. + P1_0_IN + GPIO1 Pin 0 Input Status. 3 1 - P31_OUT - GPIO3 Pin 1 Data Output. + P1_1_OUT + GPIO1 Pin 1 Data Output. 4 1 - P31_OUTEN - GPIO3 Pin 1 Output Enable. + P1_1_OUTEN + GPIO1 Pin 1 Output Enable. 5 1 - P31_PUPEN - GPIO3 Pin 1 Pull-up Enable. + P1_1_PUPEN + GPIO1 Pin 1 Pull-up Enable. 6 1 - P31_IN - GPIO3 Pin 1 Input Status. + P1_1_IN + GPIO1 Pin 1 Input Status. 7 1 - LDOCTRL - LDO Control Register. - 0x60 - - - 0P9V_EN - LDO 0.9V Enable. - 0 - 1 - - - - - PWRMONST - LDO Control Register. - 0x64 + RTCTRIM + User RTC Trim Register. + 0x24 - PORZ_VLOSS - Sticky bit indicating power-on status of core power domains of VDDIO, VDDIOH, VCOR + X2 + RTC X2 Trim. 0 - 1 - - - PORZ_VBAT - Sticky bit indicating power-on status of the battery. - 1 - 1 - - - PORZ_VBB - Sticky bit indicating power-on status of the VBB. - 2 - 1 - - - PORZ_VDDCA - Sticky bit indicating power-on status of VAON_SW supply. - 4 - 1 + 5 - PORZ_VDDCB - Sticky bit indicating power-on status of VCORE_PAD supply. + X1 + RTC X1 Trim. 5 - 1 - - - PORZ_VDDA - Sticky bit indicating power-on status of VDDA (for analog) supply. - 6 - 1 - - - PORZ_VDDB - Sticky bit indicating power-on status of VDDB (for USB) supply. - 7 - 1 - - - RSTZ_VDDCB - Sticky bit indicating reset condition on VCORE supply. - 9 - 1 - - - RSTZ_VDDA - Sticky bit indicating reset condition on VDDA (analog) supply. - 10 - 1 - - - RSTZ_VDDB - Sticky bit indicating reset condition on VDDB (USB) supply. - 11 - 1 - - - RSTZ_VDDIO - Sticky bit indicating reset condition on VDDIO supply. - 12 - 1 - - - RSTZ_VDDIOH - Sticky bit indicating reset condition on VDDIOH supply. - 13 - 1 - - - RSTZ_VBB - Sticky bit indicating reset condition on VBB supply. - 14 - 1 - - - RSTZ_LDO0P9V - Sticky bit indicating reset condition on 0.9V USB supply. - 16 - 1 - - - RSTZ_VDDCA - Sticky bit indicating reset condition on VCORE in Analog supply. - 17 - 1 - - - RSTZ_VCOREHV - Sticky bit indicating high voltage reset condition on VCORE supply. - 18 - 1 - - - RSTZ_VDDIOHV - Sticky bit indicating high voltage reset condition on VDDIO supply. - 19 - 1 - - - RSTZ_VDDIOHHV - Sticky bit indicating high voltage reset condition on VDDIOH supply. - 20 - 1 - - - RSTZ_VNFCRX - Sticky bit indicating reset condition on VNFCRX supply. - 21 - 1 - - - RSTZ_VNFCTX - Sticky bit indicating reset condition on VNFCTX supply. - 22 - 1 - - - RSTZ_VNFC1V - Sticky bit indicating reset condition on VNFC1V supply. - 23 - 1 + 5 diff --git a/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me30.svd b/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me30.svd index ea62f38cbb2..84216c88245 100644 --- a/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me30.svd +++ b/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me30.svd @@ -72,84 +72,6 @@ - - BTLELDOTRIM - BTLE LDO Trim register. - 0x48 - read-write - - - TX - TX LDO trim value. - 0 - 5 - read-write - - - RX - RX LDO trim value. - 8 - 5 - read-write - - - - - FSTAT - funcstat register. - 0x100 - read-only - - - FPU - FPU Function. - 0 - 1 - - - no - 0 - - - yes - 1 - - - - - ADC - 10-bit Sigma Delta ADC. - 2 - 1 - - - no - 0 - - - yes - 1 - - - - - SEMA - Semaphore function. - 7 - 1 - - - no - 0 - - - yes - 1 - - - - - SFSTAT Security function status register. @@ -157,42 +79,16 @@ read-only - SECBOOT + SECBOOT_EN Security Boot. 0 1 - TRNG - TRNG Function. - 2 - 1 - - - no - 0 - - - yes - 1 - - - - - AES - AES Block. - 3 + SECEXT_EN + M33 SecExt Function Enable. + 1 1 - - - no - 0 - - - yes - 1 - - From c877fe8c9e7bfc7ceb43c35543ce637f65f42779 Mon Sep 17 00:00:00 2001 From: Woo Date: Mon, 6 May 2024 11:11:05 -0500 Subject: [PATCH 64/93] Fix extclk settings --- .../CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c index 4e052bde544..960bb98bf57 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c @@ -16,6 +16,7 @@ * ******************************************************************************/ +#include #include #include #include @@ -63,8 +64,11 @@ __weak void SystemCoreClockUpdate(void) case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_IBRO: base_freq = IBRO_FREQ; break; - // case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO: - // base_freq = ERTCO_FREQ; + case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_ERTCO: + base_freq = ERTCO_FREQ; + break; + // case MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK: + // base_freq = EXTCLK_FREQ; // break; // TODO(JC): ^^^ Uncomment when EXTCLK register definition is added default: From 470eda04f3a5fb0cae7e2860b8f7287110549052 Mon Sep 17 00:00:00 2001 From: Woo Date: Mon, 6 May 2024 11:34:47 -0500 Subject: [PATCH 65/93] Remove syntax error --- Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.ld | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.ld b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.ld index 8856c41f36b..c75c977f343 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.ld +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.ld @@ -185,7 +185,7 @@ SECTIONS { */ .stack_dummy (COPY): { - *(.stack*)\ + *(.stack*) #if SECURE_LINK *(.stackseal*) #endif From 68206e2d1b0319a18a4c3c68b26b1a65927c3cd4 Mon Sep 17 00:00:00 2001 From: Woo Date: Mon, 6 May 2024 11:39:48 -0500 Subject: [PATCH 66/93] Add DMA instance number separation with secure vs non-secure builds --- Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h index 3ca98d730fb..7bd345d82db 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h @@ -625,7 +625,11 @@ We may want to handle GET_IRQ better... /******************************************************************************/ /* DMA */ #define MXC_DMA_CHANNELS (4) +#if IS_SECURE_ENVIRONMENT #define MXC_DMA_INSTANCES (2) +#else +#define MXC_DMA_INSTANCES (1) +#endif /* Non-secure Mapping */ #define MXC_BASE_DMA0_NS ((uint32_t)0x40028000UL) From b50f1ae80f3dc9e19f96ad495b4ba445e35930aa Mon Sep 17 00:00:00 2001 From: Woo Date: Mon, 6 May 2024 16:49:02 -0500 Subject: [PATCH 67/93] Reorganize DMA handling --- Libraries/CMSIS/Device/Maxim/GCC/gcc.mk | 2 + .../Device/Maxim/MAX32657/Include/max32657.h | 30 ++++++------ .../MAX32657/Include/partition_max32657.h | 4 ++ .../Maxim/MAX32657/Source/GCC/max32657.ld | 10 +--- .../PeriphDrivers/Include/MAX32657/aes.h | 10 ++-- .../PeriphDrivers/Include/MAX32657/crc.h | 5 +- .../PeriphDrivers/Include/MAX32657/dma.h | 27 +++++++--- .../PeriphDrivers/Include/MAX32657/spi.h | 9 ++-- .../PeriphDrivers/Include/MAX32657/uart.h | 14 ++++-- Libraries/PeriphDrivers/Source/AES/aes_ai87.c | 4 +- Libraries/PeriphDrivers/Source/AES/aes_me12.c | 4 +- Libraries/PeriphDrivers/Source/AES/aes_me15.c | 4 +- Libraries/PeriphDrivers/Source/AES/aes_me17.c | 4 +- Libraries/PeriphDrivers/Source/AES/aes_me21.c | 4 +- Libraries/PeriphDrivers/Source/AES/aes_me30.c | 13 ++--- Libraries/PeriphDrivers/Source/AES/aes_revb.c | 39 ++++++++++++--- Libraries/PeriphDrivers/Source/AES/aes_revb.h | 7 +-- Libraries/PeriphDrivers/Source/CRC/crc_ai87.c | 2 +- Libraries/PeriphDrivers/Source/CRC/crc_me15.c | 2 +- Libraries/PeriphDrivers/Source/CRC/crc_me17.c | 2 +- Libraries/PeriphDrivers/Source/CRC/crc_me30.c | 5 +- Libraries/PeriphDrivers/Source/CRC/crc_reva.c | 17 ++++++- Libraries/PeriphDrivers/Source/CRC/crc_reva.h | 3 +- Libraries/PeriphDrivers/Source/DMA/dma_me30.c | 39 ++++++++------- Libraries/PeriphDrivers/Source/DMA/dma_reva.c | 12 ++++- Libraries/PeriphDrivers/Source/SPI/spi_me30.c | 10 ++-- .../PeriphDrivers/Source/SPI/spi_reva1.c | 22 ++++++++- Libraries/PeriphDrivers/Source/SYS/sys_me30.c | 5 +- .../PeriphDrivers/Source/UART/uart_me30.c | 12 ++--- .../PeriphDrivers/Source/UART/uart_reva.c | 49 ++++++++++++++----- 30 files changed, 247 insertions(+), 123 deletions(-) diff --git a/Libraries/CMSIS/Device/Maxim/GCC/gcc.mk b/Libraries/CMSIS/Device/Maxim/GCC/gcc.mk index 8b434adada0..873d657f568 100644 --- a/Libraries/CMSIS/Device/Maxim/GCC/gcc.mk +++ b/Libraries/CMSIS/Device/Maxim/GCC/gcc.mk @@ -278,6 +278,8 @@ ifeq "$(MSECURITY_MODE)" "SECURE" # https://developer.arm.com/documentation/ecm0359818/latest PROJ_CFLAGS += -mcmse +PROJ_AFLAGS += -DIS_SECURE_ENVRIONMENT + # Tell the linker we are building a secure project. This defines the "SECURE_LINK" symbol which the # linker uses to set the secure FLASH/SRAM memory address ranges. PROJ_LDFLAGS += -Xlinker --defsym=SECURE_LINK=1 diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h index 7bd345d82db..24a89242cdd 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h @@ -474,8 +474,6 @@ typedef enum { #define MXC_BASE_GPIO0_S ((uint32_t)0x50008000UL) #define MXC_GPIO0_S ((mxc_gpio_regs_t *)MXC_BASE_GPIO0_S) -#define MXC_BASE_GPIO0 MXC_BASE_GPIO0_S - #if IS_SECURE_ENVIRONMENT #define MXC_BASE_GPIO0 MXC_BASE_GPIO0_S #define MXC_GPIO0 MXC_GPIO0_S @@ -654,11 +652,15 @@ We may want to handle GET_IRQ better... #define MXC_BASE_DMA1 MXC_BASE_DMA1_S #define MXC_DMA1 MXC_DMA1_S -#define MXC_DMA1_CH_GET_IRQ(i) \ - ((IRQn_Type)(((i) == 0) ? DMA1_CH0_IRQn : \ - ((i) == 1) ? DMA1_CH1_IRQn : \ - ((i) == 2) ? DMA1_CH2_IRQn : \ - ((i) == 3) ? DMA1_CH3_IRQn : \ +#define MXC_DMA_CH_GET_IRQ(p, i) \ + ((IRQn_Type)(((p) == MXC_DMA0 && (i) == 0) ? DMA0_CH0_IRQn : \ + ((p) == MXC_DMA0 && (i) == 1) ? DMA0_CH1_IRQn : \ + ((p) == MXC_DMA0 && (i) == 2) ? DMA0_CH2_IRQn : \ + ((p) == MXC_DMA0 && (i) == 3) ? DMA0_CH3_IRQn : \ + ((p) == MXC_DMA1 && (i) == 0) ? DMA1_CH0_IRQn : \ + ((p) == MXC_DMA1 && (i) == 1) ? DMA1_CH1_IRQn : \ + ((p) == MXC_DMA1 && (i) == 2) ? DMA1_CH2_IRQn : \ + ((p) == MXC_DMA1 && (i) == 3) ? DMA1_CH3_IRQn : \ 0)) #else @@ -672,18 +674,16 @@ We may want to handle GET_IRQ better... #define MXC_DMA1 0 /* DMA1 IRQs not usable in Non-Secure state. */ -#define MXC_DMA1_CH_GET_IRQ(i) ((IRQn_Type)(0)) +#define MXC_DMA_CH_GET_IRQ(p, i) \ + ((IRQn_Type)(((p) == MXC_DMA0 && (i) == 0) ? DMA0_CH0_IRQn : \ + ((p) == MXC_DMA0 && (i) == 1) ? DMA0_CH1_IRQn : \ + ((p) == MXC_DMA0 && (i) == 2) ? DMA0_CH2_IRQn : \ + ((p) == MXC_DMA0 && (i) == 3) ? DMA0_CH3_IRQn : \ + 0)) #endif // IS_SECURE_ENVIRONMENT #define MXC_DMA_GET_BASE(i) ((i) == MXC_BASE_DMA0 ? 0 : (p) == MXC_BASE_DMA1 ? 1 : -1) -#define MXC_DMA0_CH_GET_IRQ(i) \ - ((IRQn_Type)(((i) == 0) ? DMA0_CH0_IRQn : \ - ((i) == 1) ? DMA0_CH1_IRQn : \ - ((i) == 2) ? DMA0_CH2_IRQn : \ - ((i) == 3) ? DMA0_CH3_IRQn : \ - 0)) - #define MXC_DMA_GET_IDX(p) ((p) == MXC_DMA0 ? 0 : (p) == MXC_DMA1 ? 1 : -1) /******************************************************************************/ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/partition_max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/partition_max32657.h index 14b28a9312e..5b9fed2bedf 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/partition_max32657.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/partition_max32657.h @@ -30,6 +30,8 @@ #include "max32657.h" +#if IS_SECURE_ENVIRONMENT + /* //-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- */ @@ -1278,4 +1280,6 @@ __STATIC_INLINE void TZ_SAU_Setup (void) } +#endif // IS_SECURE_EVIRONMENT + #endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_SOURCE_PARTITION_MAX32657_H_ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.ld b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.ld index c75c977f343..7a02a14948e 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.ld +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.ld @@ -70,14 +70,12 @@ SECTIONS { * Secure Gatway (SG) veneers. * All SG veneers are placed in the special output section .gnu.sgstubs. */ -#if SECURE_LINK .gnu.sgstubs : { _sg_veneers = .; - KEEP(*(.gnu.sgstubs*)) + *(.gnu.sgstubs*) _esg_veneers = .; } > FLASH -#endif .ARM.extab : { @@ -161,7 +159,6 @@ SECTIONS { * Stack Seal section is required for secure builds. Stack sealing protects * secure stack from illegal access by non-secure code. */ -#if SECURE_LINK .stackseal (COPY): { . = ALIGN(8); @@ -169,7 +166,6 @@ SECTIONS { . = . + 8; . = ALIGN(8); } > SRAM -#endif /** * Set stack top to end of RAM, and stack limit move down by @@ -185,10 +181,8 @@ SECTIONS { */ .stack_dummy (COPY): { - *(.stack*) -#if SECURE_LINK + KEEP(*(.stack*)) *(.stackseal*) -#endif } > SRAM .heap (COPY): diff --git a/Libraries/PeriphDrivers/Include/MAX32657/aes.h b/Libraries/PeriphDrivers/Include/MAX32657/aes.h index 7f51f371c1b..806df3abbbc 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/aes.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/aes.h @@ -27,6 +27,7 @@ /***** Includes *****/ #include "aes_regs.h" #include "aeskeys_regs.h" +#include "dma_regs.h" #ifdef __cplusplus extern "C" { @@ -89,9 +90,10 @@ typedef struct _mxc_aes_cipher_req_t { /** * @brief Enable portions of the AES * + * @param dma DMA instance used for AES * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_AES_Init(void); +int MXC_AES_Init(mxc_dma_regs_t *dma); /** * @brief Enable AES Interrupts @@ -213,18 +215,20 @@ int MXC_AES_Decrypt(mxc_aes_req_t *req); * * @param src_addr source address * @param len number of words of data + * @param dma DMA instance to configue for AES * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_AES_TXDMAConfig(void *src_addr, int len); +int MXC_AES_TXDMAConfig(void *src_addr, int len, mxc_dma_regs_t *dma); /** * @brief Perform AES RX using DMA. Configures DMA request and receives data from AES FIFO. * * @param dest_addr destination address * @param len number of words of data + * @param dma DMA instance to configure for AES * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_AES_RXDMAConfig(void *dest_addr, int len); +int MXC_AES_RXDMAConfig(void *dest_addr, int len, mxc_dma_regs_t *dma); /** * @brief Perform encryption or decryption using DMA diff --git a/Libraries/PeriphDrivers/Include/MAX32657/crc.h b/Libraries/PeriphDrivers/Include/MAX32657/crc.h index 35218bf1f23..f80ed216122 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/crc.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/crc.h @@ -26,6 +26,7 @@ /***** Includes *****/ #include "crc_regs.h" +#include "dma_regs.h" #ifdef __cplusplus extern "C" { @@ -63,10 +64,10 @@ typedef enum { CRC_LSB_FIRST, CRC_MSB_FIRST } mxc_crc_bitorder_t; /** * @brief Enable portions of the CRC * - * + * @param dma DMA Instance used for CRC calculation * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_CRC_Init(void); +int MXC_CRC_Init(mxc_dma_regs_t *dma); /** * @brief Disable and reset portions of the CRC diff --git a/Libraries/PeriphDrivers/Include/MAX32657/dma.h b/Libraries/PeriphDrivers/Include/MAX32657/dma.h index ef471bb2ce4..44fd184aeb7 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/dma.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/dma.h @@ -193,25 +193,30 @@ typedef mxc_dma_srcdst_t (*mxc_dma_trans_chain_t)(mxc_dma_srcdst_t dest); * if you wish to manage clock and gpio related things in upper level instead of here. * Define MSDK_NO_GPIO_CLK_INIT flag in project.mk file. * By this flag this function will remove clock and gpio related codes from file. + * @param dma Pointer to selected DMA instance's registers. + * * @return #E_NO_ERROR if successful */ -int MXC_DMA_Init(void); +int MXC_DMA_Init(mxc_dma_regs_t *dma); /** * @brief De-Initialize DMA resources. + * + * @param dma Pointer to selected DMA instance's registers. */ -void MXC_DMA_DeInit(void); +void MXC_DMA_DeInit(mxc_dma_regs_t *dma); /** * @brief Request DMA channel * @details Returns a handle to the first free DMA channel, which can be used via API calls * or direct access to channel registers using the MXC_DMA_GetCHRegs(int ch) function. + * @param dma Pointer to selected DMA instance's registers. * @return Non-negative channel handle (inclusive of zero). * @return #E_NONE_AVAIL All channels in use. * @return #E_BAD_STATE DMA is not initialized, call MXC_DMA_Init() first. * @return #E_BUSY DMA is currently busy (locked), try again later. */ -int MXC_DMA_AcquireChannel(void); +int MXC_DMA_AcquireChannel(mxc_dma_regs_t *dma); /** * @brief Release DMA channel @@ -360,19 +365,21 @@ int MXC_DMA_ChannelClearFlags(int ch, int flags); * @brief Enable channel interrupt * @note Each channel has two interrupts (complete, and count to zero) which must also be enabled with MXC_DMA_SetChannelInterruptEn() + * @param dma DMA instance used for the DMA channel registers. * @param ch DMA channel to enable interrupts for. * @return #E_BAD_PARAM if an unused or invalid channel handle, * #E_NO_ERROR otherwise, \ref MXC_Error_Codes */ -int MXC_DMA_EnableInt(int ch); +int MXC_DMA_EnableInt(mxc_dma_regs_t *dma, int ch); /** * @brief Disable channel interrupt + * @param dma DMA instance used for the DMA channel registers. * @param ch DMA channel to disable interrupts for. * @return #E_BAD_PARAM if an unused or invalid channel handle, * #E_NO_ERROR otherwise, \ref MXC_Error_Codes */ -int MXC_DMA_DisableInt(int ch); +int MXC_DMA_DisableInt(mxc_dma_regs_t *dma, int ch); /** * @brief Start transfer @@ -402,10 +409,11 @@ mxc_dma_ch_regs_t *MXC_DMA_GetCHRegs(int ch); /** * @brief Interrupt handler function + * @param dma Pointer to DMA registers. * @details Call this function as the ISR for each DMA channel under driver control. * Interrupt flags for channel ch will be automatically cleared before return. */ -void MXC_DMA_Handler(void); +void MXC_DMA_Handler(mxc_dma_regs_t *dma); /*************************/ /* High Level Functions */ @@ -416,6 +424,7 @@ void MXC_DMA_Handler(void); * @note The user must have the DMA interrupt enabled and call * MXC_DMA_Handler() from the ISR. * + * @param dma Pointer to DMA registers. * @param dest pointer to destination memory * @param src pointer to source memory * @param len number of bytes to copy @@ -423,20 +432,22 @@ void MXC_DMA_Handler(void); * * @return see \ref MXC_Error_Codes */ -int MXC_DMA_MemCpy(void *dest, void *src, int len, mxc_dma_complete_cb_t callback); +int MXC_DMA_MemCpy(mxc_dma_regs_t *dma, void *dest, void *src, int len, + mxc_dma_complete_cb_t callback); /** * @brief Performs a memcpy, using DMA, optionally asynchronous * @note The user must have the DMA interrupt enabled and call * MXC_DMA_Handler() from the ISR. * + * @param dma Pointer to DMA registers. * @param config The channel config struct * @param firstSrcDst The source, destination, and count for the first transfer * @param callback function is called when transfer is complete * * @return see \ref MXC_Error_Codes */ -int MXC_DMA_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, +int MXC_DMA_DoTransfer(mxc_dma_regs_t *dma, mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback); /** * For other functional uses of DMA (UART, SPI, etc) see the appropriate peripheral driver diff --git a/Libraries/PeriphDrivers/Include/MAX32657/spi.h b/Libraries/PeriphDrivers/Include/MAX32657/spi.h index de855f2cb0e..7ddde948670 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/spi.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/spi.h @@ -32,6 +32,7 @@ #include "gpio.h" #include "mxc_pins.h" #include "mxc_lock.h" +#include "dma_regs.h" #ifdef __cplusplus extern "C" { @@ -595,11 +596,12 @@ int MXC_SPI_MasterTransactionAsync(mxc_spi_req_t *req); * possible. The channel will be reset and returned to the system at the end of * the transaction. * - * @param req Pointer to details of the transaction + * @param req Pointer to details of the transaction + * @param dma DMA instance to use for SPI DMA * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req); +int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req, mxc_dma_regs_t *dma); /** * @brief Performs a blocking SPI transaction. @@ -642,10 +644,11 @@ int MXC_SPI_SlaveTransactionAsync(mxc_spi_req_t *req); * the transaction. * * @param req Pointer to details of the transaction + * @param dma DMA instance to use for SPI DMA * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req); +int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req, mxc_dma_regs_t *dma); /** * @brief Sets the TX data to transmit as a 'dummy' byte diff --git a/Libraries/PeriphDrivers/Include/MAX32657/uart.h b/Libraries/PeriphDrivers/Include/MAX32657/uart.h index 40e90877866..523b80f8e0b 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/uart.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/uart.h @@ -31,6 +31,7 @@ #include #include "uart_regs.h" #include "mxc_sys.h" +#include "dma_regs.h" #ifdef __cplusplus extern "C" { @@ -377,14 +378,15 @@ unsigned int MXC_UART_ReadRXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, un /** * @brief Unloads bytes from the receive FIFO user DMA for longer reads. * - * @param uart Pointer to UART registers (selects the UART block used.) + * @param uart Pointer to UART registers (selects the UART block used). + * @param dma Pointer to DMA registers (selects the DMA block used for UART DMA). * @param bytes The buffer to read the data into. * @param len The number of bytes to read. * @param callback The function to call when the read is complete * * @return See \ref MXC_Error_Codes for a list of return values */ -int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len, +int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, mxc_dma_regs_t *dma, unsigned char *bytes, unsigned int len, mxc_uart_dma_complete_cb_t callback); /** @@ -410,14 +412,15 @@ unsigned int MXC_UART_WriteTXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, u /** * @brief Loads bytes into the transmit FIFO using DMA for longer writes * - * @param uart Pointer to UART registers (selects the UART block used.) + * @param uart Pointer to UART registers (selects the UART block used). + * @param dma Pointer to DMA registers (selects the DMA block used for UART DMA). * @param bytes The buffer containing the bytes to write * @param len The number of bytes to write. * @param callback The function to call when the write is complete * * @return See \ref MXC_Error_Codes for a list of return values */ -int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len, +int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, mxc_dma_regs_t *dma, unsigned char *bytes, unsigned int len, mxc_uart_dma_complete_cb_t callback); /** @@ -602,10 +605,11 @@ int MXC_UART_TransactionAsync(mxc_uart_req_t *req); * returned to the system at the end of the transaction. * * @param req Pointer to details of the transaction + * @param dma Pointer to DMA registers used for UART DMA * * @return See \ref MXC_Error_Codes for the list of error return codes. */ -int MXC_UART_TransactionDMA(mxc_uart_req_t *req); +int MXC_UART_TransactionDMA(mxc_uart_req_t *req, mxc_dma_regs_t *dma); /** * @brief The processing function for DMA transactions. diff --git a/Libraries/PeriphDrivers/Source/AES/aes_ai87.c b/Libraries/PeriphDrivers/Source/AES/aes_ai87.c index 594d86119ce..ba60f951604 100644 --- a/Libraries/PeriphDrivers/Source/AES/aes_ai87.c +++ b/Libraries/PeriphDrivers/Source/AES/aes_ai87.c @@ -138,12 +138,12 @@ int MXC_AES_Decrypt(mxc_aes_req_t *req) int MXC_AES_TXDMAConfig(void *src_addr, int len) { - return MXC_AES_RevB_TXDMAConfig(src_addr, len); + return MXC_AES_RevB_TXDMAConfig(src_addr, len, MXC_DMA); } int MXC_AES_RXDMAConfig(void *dest_addr, int len) { - return MXC_AES_RevB_RXDMAConfig(dest_addr, len); + return MXC_AES_RevB_RXDMAConfig(dest_addr, len, MXC_DMA); } int MXC_AES_GenericAsync(mxc_aes_req_t *req, uint8_t enc) diff --git a/Libraries/PeriphDrivers/Source/AES/aes_me12.c b/Libraries/PeriphDrivers/Source/AES/aes_me12.c index 87e6b35cb25..60c6eaeeb21 100644 --- a/Libraries/PeriphDrivers/Source/AES/aes_me12.c +++ b/Libraries/PeriphDrivers/Source/AES/aes_me12.c @@ -131,12 +131,12 @@ int MXC_AES_Decrypt(mxc_aes_req_t *req) int MXC_AES_TXDMAConfig(void *src_addr, int len) { - return MXC_AES_RevB_TXDMAConfig(src_addr, len); + return MXC_AES_RevB_TXDMAConfig(src_addr, len, MXC_DMA); } int MXC_AES_RXDMAConfig(void *dest_addr, int len) { - return MXC_AES_RevB_RXDMAConfig(dest_addr, len); + return MXC_AES_RevB_RXDMAConfig(dest_addr, len, MXC_DMA); } int MXC_AES_GenericAsync(mxc_aes_req_t *req, uint8_t enc) diff --git a/Libraries/PeriphDrivers/Source/AES/aes_me15.c b/Libraries/PeriphDrivers/Source/AES/aes_me15.c index d35812e0d27..60ecf1ead79 100644 --- a/Libraries/PeriphDrivers/Source/AES/aes_me15.c +++ b/Libraries/PeriphDrivers/Source/AES/aes_me15.c @@ -155,12 +155,12 @@ int MXC_AES_Decrypt(mxc_aes_req_t *req) int MXC_AES_TXDMAConfig(void *src_addr, int len) { - return MXC_AES_RevB_TXDMAConfig(src_addr, len); + return MXC_AES_RevB_TXDMAConfig(src_addr, len, MXC_DMA); } int MXC_AES_RXDMAConfig(void *dest_addr, int len) { - return MXC_AES_RevB_RXDMAConfig(dest_addr, len); + return MXC_AES_RevB_RXDMAConfig(dest_addr, len, MXC_DMA); } int MXC_AES_GenericAsync(mxc_aes_req_t *req, uint8_t enc) diff --git a/Libraries/PeriphDrivers/Source/AES/aes_me17.c b/Libraries/PeriphDrivers/Source/AES/aes_me17.c index 27ac05bc04a..1cbca9635a9 100644 --- a/Libraries/PeriphDrivers/Source/AES/aes_me17.c +++ b/Libraries/PeriphDrivers/Source/AES/aes_me17.c @@ -132,12 +132,12 @@ int MXC_AES_Decrypt(mxc_aes_req_t *req) int MXC_AES_TXDMAConfig(void *src_addr, int len) { - return MXC_AES_RevB_TXDMAConfig(src_addr, len); + return MXC_AES_RevB_TXDMAConfig(src_addr, len, MXC_DMA); } int MXC_AES_RXDMAConfig(void *dest_addr, int len) { - return MXC_AES_RevB_RXDMAConfig(dest_addr, len); + return MXC_AES_RevB_RXDMAConfig(dest_addr, len, MXC_DMA); } int MXC_AES_GenericAsync(mxc_aes_req_t *req, uint8_t enc) diff --git a/Libraries/PeriphDrivers/Source/AES/aes_me21.c b/Libraries/PeriphDrivers/Source/AES/aes_me21.c index 1eaf61ca5e1..cfb340482a9 100644 --- a/Libraries/PeriphDrivers/Source/AES/aes_me21.c +++ b/Libraries/PeriphDrivers/Source/AES/aes_me21.c @@ -126,12 +126,12 @@ int MXC_AES_Decrypt(mxc_aes_req_t *req) int MXC_AES_TXDMAConfig(void *src_addr, int len) { - return MXC_AES_RevB_TXDMAConfig(src_addr, len); + return MXC_AES_RevB_TXDMAConfig(src_addr, len, MXC_DMA); } int MXC_AES_RXDMAConfig(void *dest_addr, int len) { - return MXC_AES_RevB_RXDMAConfig(dest_addr, len); + return MXC_AES_RevB_RXDMAConfig(dest_addr, len, MXC_DMA); } int MXC_AES_GenericAsync(mxc_aes_req_t *req, uint8_t enc) diff --git a/Libraries/PeriphDrivers/Source/AES/aes_me30.c b/Libraries/PeriphDrivers/Source/AES/aes_me30.c index 63603f4cf83..575f8abedf6 100644 --- a/Libraries/PeriphDrivers/Source/AES/aes_me30.c +++ b/Libraries/PeriphDrivers/Source/AES/aes_me30.c @@ -23,19 +23,20 @@ #include "aes_revb.h" #include "trng.h" #include "trng_revb.h" +#include "dma.h" /* ************************************************************************* */ /* Global Control/Configuration functions */ /* ************************************************************************* */ -int MXC_AES_Init(void) +int MXC_AES_Init(mxc_dma_regs_t *dma) { #ifndef MSDK_NO_GPIO_CLK_INIT MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_AES); MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TRNG); #endif - return MXC_AES_RevB_Init((mxc_aes_revb_regs_t *)MXC_AES); + return MXC_AES_RevB_Init((mxc_aes_revb_regs_t *)MXC_AES, dma); } void MXC_AES_EnableInt(uint32_t interrupt) @@ -123,14 +124,14 @@ int MXC_AES_Decrypt(mxc_aes_req_t *req) return MXC_AES_RevB_Decrypt((mxc_aes_revb_regs_t *)MXC_AES, (mxc_aes_revb_req_t *)req); } -int MXC_AES_TXDMAConfig(void *src_addr, int len) +int MXC_AES_TXDMAConfig(void *src_addr, int len, mxc_dma_regs_t *dma) { - return MXC_AES_RevB_TXDMAConfig(src_addr, len); + return MXC_AES_RevB_TXDMAConfig(src_addr, len, dma); } -int MXC_AES_RXDMAConfig(void *dest_addr, int len) +int MXC_AES_RXDMAConfig(void *dest_addr, int len, mxc_dma_regs_t *dma) { - return MXC_AES_RevB_RXDMAConfig(dest_addr, len); + return MXC_AES_RevB_RXDMAConfig(dest_addr, len, dma); } int MXC_AES_GenericAsync(mxc_aes_req_t *req, uint8_t enc) diff --git a/Libraries/PeriphDrivers/Source/AES/aes_revb.c b/Libraries/PeriphDrivers/Source/AES/aes_revb.c index 240b8b6f21a..77ce01370f1 100644 --- a/Libraries/PeriphDrivers/Source/AES/aes_revb.c +++ b/Libraries/PeriphDrivers/Source/AES/aes_revb.c @@ -33,6 +33,7 @@ /* **** Variable Declaration **** */ typedef struct { uint8_t enc; + mxc_dma_regs_t *dma; uint8_t channelRX; uint8_t channelTX; uint32_t remain; @@ -62,7 +63,7 @@ memcpy32r(uint32_t *dst, const uint32_t *src, unsigned int len) } } -int MXC_AES_RevB_Init(mxc_aes_revb_regs_t *aes) +int MXC_AES_RevB_Init(mxc_aes_revb_regs_t *aes, mxc_dma_regs_t *dma) { aes->ctrl = 0x00; @@ -70,6 +71,8 @@ int MXC_AES_RevB_Init(mxc_aes_revb_regs_t *aes) aes->ctrl |= MXC_F_AES_REVB_CTRL_EN; + dma_state.dma = dma; + return E_NO_ERROR; } @@ -226,7 +229,7 @@ int MXC_AES_RevB_Decrypt(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req) return MXC_AES_RevB_Generic(aes, req); } -int MXC_AES_RevB_TXDMAConfig(void *src_addr, int len) +int MXC_AES_RevB_TXDMAConfig(void *src_addr, int len, mxc_dma_regs_t *dma) { uint8_t channel; mxc_dma_config_t config; @@ -240,9 +243,16 @@ int MXC_AES_RevB_TXDMAConfig(void *src_addr, int len) return E_BAD_PARAM; } +#if (TARGET_NUM == 32657) + MXC_DMA_Init(dma); + + channel = MXC_DMA_AcquireChannel(dma); +#else MXC_DMA_Init(); channel = MXC_DMA_AcquireChannel(); +#endif + dma_state.channelTX = channel; config.reqsel = MXC_DMA_REQUEST_AESTX; @@ -269,7 +279,12 @@ int MXC_AES_RevB_TXDMAConfig(void *src_addr, int len) MXC_DMA_ConfigChannel(config, srcdst); MXC_DMA_SetCallback(channel, MXC_AES_RevB_DMACallback); +#if (TARGET_NUM == 32657) + MXC_DMA_EnableInt(dma, channel); +#else MXC_DMA_EnableInt(channel); +#endif + MXC_DMA_Start(channel); //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; MXC_DMA_SetChannelInterruptEn(channel, 0, 1); @@ -277,7 +292,7 @@ int MXC_AES_RevB_TXDMAConfig(void *src_addr, int len) return E_NO_ERROR; } -int MXC_AES_RevB_RXDMAConfig(void *dest_addr, int len) +int MXC_AES_RevB_RXDMAConfig(void *dest_addr, int len, mxc_dma_regs_t *dma) { if (dest_addr == NULL) { return E_NULL_PTR; @@ -291,9 +306,16 @@ int MXC_AES_RevB_RXDMAConfig(void *dest_addr, int len) mxc_dma_config_t config; mxc_dma_srcdst_t srcdst; +#if (TARGET_NUM == 32657) + MXC_DMA_Init(dma); + + channel = MXC_DMA_AcquireChannel(dma); +#else MXC_DMA_Init(); channel = MXC_DMA_AcquireChannel(); +#endif + dma_state.channelRX = channel; config.reqsel = MXC_DMA_REQUEST_AESRX; @@ -320,7 +342,12 @@ int MXC_AES_RevB_RXDMAConfig(void *dest_addr, int len) MXC_DMA_ConfigChannel(config, srcdst); MXC_DMA_SetCallback(channel, MXC_AES_RevB_DMACallback); +#if (TARGET_NUM == 32657) + MXC_DMA_EnableInt(dma, channel); +#else MXC_DMA_EnableInt(channel); +#endif + MXC_DMA_Start(channel); //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; MXC_DMA_SetChannelInterruptEn(channel, 0, 1); @@ -359,7 +386,7 @@ int MXC_AES_RevB_GenericAsync(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req, aes->ctrl |= MXC_F_AES_REVB_CTRL_DMA_RX_EN; //Enable AES DMA aes->ctrl |= MXC_F_AES_REVB_CTRL_DMA_TX_EN; //Enable AES DMA - if (MXC_AES_RevB_TXDMAConfig(dma_state.inputText, dma_state.remain) != E_NO_ERROR) { + if (MXC_AES_RevB_TXDMAConfig(dma_state.inputText, dma_state.remain, dma_state.dma) != E_NO_ERROR) { return E_BAD_PARAM; } @@ -385,7 +412,7 @@ void MXC_AES_RevB_DMACallback(int ch, int error) if (dma_state.remain < 4) { MXC_AES_Start(); } - MXC_AES_RevB_RXDMAConfig(dma_state.outputText, dma_state.remain); + MXC_AES_RevB_RXDMAConfig(dma_state.outputText, dma_state.remain, dma_state.dma); } else if (dma_state.channelRX == ch) { if (dma_state.remain > 4) { dma_state.remain -= 4; @@ -394,7 +421,7 @@ void MXC_AES_RevB_DMACallback(int ch, int error) } MXC_DMA_ReleaseChannel(dma_state.channelRX); if (dma_state.remain > 0) { - MXC_AES_RevB_TXDMAConfig(dma_state.inputText, dma_state.remain); + MXC_AES_RevB_TXDMAConfig(dma_state.inputText, dma_state.remain, dma_state.dma); } } } diff --git a/Libraries/PeriphDrivers/Source/AES/aes_revb.h b/Libraries/PeriphDrivers/Source/AES/aes_revb.h index 3f00bda64c1..0c8b318a7c3 100644 --- a/Libraries/PeriphDrivers/Source/AES/aes_revb.h +++ b/Libraries/PeriphDrivers/Source/AES/aes_revb.h @@ -26,6 +26,7 @@ #include "aes_revb_regs.h" #include "aeskeys_revb_regs.h" #include "trng_revb_regs.h" +#include "dma.h" /** * @brief Enumeration type to select AES key @@ -60,7 +61,7 @@ typedef struct _mxc_aes_revb_cipher_req_t { mxc_aes_complete_t callback; ///< Callback function } mxc_aes_revb_req_t; -int MXC_AES_RevB_Init(mxc_aes_revb_regs_t *aes); +int MXC_AES_RevB_Init(mxc_aes_revb_regs_t *aes, mxc_dma_regs_t *dma); void MXC_AES_RevB_EnableInt(mxc_aes_revb_regs_t *aes, uint32_t interrupt); void MXC_AES_RevB_DisableInt(mxc_aes_revb_regs_t *aes, uint32_t interrupt); int MXC_AES_RevB_IsBusy(mxc_aes_revb_regs_t *aes); @@ -76,8 +77,8 @@ void MXC_AES_RevB_ClearFlags(mxc_aes_revb_regs_t *aes, uint32_t flags); int MXC_AES_RevB_Generic(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req); int MXC_AES_RevB_Encrypt(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req); int MXC_AES_RevB_Decrypt(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req); -int MXC_AES_RevB_TXDMAConfig(void *src_addr, int len); -int MXC_AES_RevB_RXDMAConfig(void *dest_addr, int len); +int MXC_AES_RevB_TXDMAConfig(void *src_addr, int len, mxc_dma_regs_t *dma); +int MXC_AES_RevB_RXDMAConfig(void *dest_addr, int len, mxc_dma_regs_t *dma); int MXC_AES_RevB_GenericAsync(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req, uint8_t enc); int MXC_AES_RevB_EncryptAsync(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req); int MXC_AES_RevB_DecryptAsync(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req); diff --git a/Libraries/PeriphDrivers/Source/CRC/crc_ai87.c b/Libraries/PeriphDrivers/Source/CRC/crc_ai87.c index 8e09e2dc81c..e75000fe5fc 100644 --- a/Libraries/PeriphDrivers/Source/CRC/crc_ai87.c +++ b/Libraries/PeriphDrivers/Source/CRC/crc_ai87.c @@ -36,7 +36,7 @@ int MXC_CRC_Init(void) MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_CRC); #endif - MXC_CRC_RevA_Init((mxc_crc_reva_regs_t *)MXC_CRC); + MXC_CRC_RevA_Init((mxc_crc_reva_regs_t *)MXC_CRC, MXC_DMA); return E_NO_ERROR; } diff --git a/Libraries/PeriphDrivers/Source/CRC/crc_me15.c b/Libraries/PeriphDrivers/Source/CRC/crc_me15.c index 8e09e2dc81c..e75000fe5fc 100644 --- a/Libraries/PeriphDrivers/Source/CRC/crc_me15.c +++ b/Libraries/PeriphDrivers/Source/CRC/crc_me15.c @@ -36,7 +36,7 @@ int MXC_CRC_Init(void) MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_CRC); #endif - MXC_CRC_RevA_Init((mxc_crc_reva_regs_t *)MXC_CRC); + MXC_CRC_RevA_Init((mxc_crc_reva_regs_t *)MXC_CRC, MXC_DMA); return E_NO_ERROR; } diff --git a/Libraries/PeriphDrivers/Source/CRC/crc_me17.c b/Libraries/PeriphDrivers/Source/CRC/crc_me17.c index 8e09e2dc81c..e75000fe5fc 100644 --- a/Libraries/PeriphDrivers/Source/CRC/crc_me17.c +++ b/Libraries/PeriphDrivers/Source/CRC/crc_me17.c @@ -36,7 +36,7 @@ int MXC_CRC_Init(void) MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_CRC); #endif - MXC_CRC_RevA_Init((mxc_crc_reva_regs_t *)MXC_CRC); + MXC_CRC_RevA_Init((mxc_crc_reva_regs_t *)MXC_CRC, MXC_DMA); return E_NO_ERROR; } diff --git a/Libraries/PeriphDrivers/Source/CRC/crc_me30.c b/Libraries/PeriphDrivers/Source/CRC/crc_me30.c index cf4819eb767..1d1bcf41eb9 100644 --- a/Libraries/PeriphDrivers/Source/CRC/crc_me30.c +++ b/Libraries/PeriphDrivers/Source/CRC/crc_me30.c @@ -23,18 +23,19 @@ #include "crc.h" #include "crc_reva.h" +#include "dma.h" /* ************************************************************************* */ /* Global Control/Configuration functions */ /* ************************************************************************* */ -int MXC_CRC_Init(void) +int MXC_CRC_Init(mxc_dma_regs_t *dma) { #ifndef MSDK_NO_GPIO_CLK_INIT MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_CRC); #endif - MXC_CRC_RevA_Init((mxc_crc_reva_regs_t *)MXC_CRC); + MXC_CRC_RevA_Init((mxc_crc_reva_regs_t *)MXC_CRC, dma); return E_NO_ERROR; } diff --git a/Libraries/PeriphDrivers/Source/CRC/crc_reva.c b/Libraries/PeriphDrivers/Source/CRC/crc_reva.c index 4cdb5e5ebb3..a84b553ab89 100644 --- a/Libraries/PeriphDrivers/Source/CRC/crc_reva.c +++ b/Libraries/PeriphDrivers/Source/CRC/crc_reva.c @@ -33,13 +33,16 @@ /***** Global Variables *****/ static mxc_crc_reva_req_t *CRCreq; +static mxc_dma_regs_t *CRCdma; /* ************************************************************************* */ /* Global Control/Configuration functions */ /* ************************************************************************* */ -int MXC_CRC_RevA_Init(mxc_crc_reva_regs_t *crc) +int MXC_CRC_RevA_Init(mxc_crc_reva_regs_t *crc, mxc_dma_regs_t *dma) { + CRCdma = dma; + crc->ctrl = 0x00; crc->val = 0xFFFFFFFF; return E_NO_ERROR; @@ -160,9 +163,15 @@ int MXC_CRC_RevA_ComputeAsync(mxc_crc_reva_regs_t *crc, mxc_crc_reva_req_t *req) CRCreq = req; +#if (TARGET_NUM == 32657) + MXC_DMA_Init(CRCdma); + + channel = MXC_DMA_AcquireChannel(CRCdma); +#else MXC_DMA_Init(); channel = MXC_DMA_AcquireChannel(); +#endif config.reqsel = MXC_DMA_REQUEST_CRCTX; @@ -183,7 +192,13 @@ int MXC_CRC_RevA_ComputeAsync(mxc_crc_reva_regs_t *crc, mxc_crc_reva_req_t *req) MXC_DMA_ConfigChannel(config, srcdst); MXC_DMA_SetCallback(channel, MXC_CRC_Handler); + +#if (TARGET_NUM == 32657) + MXC_DMA_EnableInt(CRCdma, channel); +#else MXC_DMA_EnableInt(channel); +#endif + MXC_DMA_Start(channel); //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; MXC_DMA_SetChannelInterruptEn(channel, 0, 1); diff --git a/Libraries/PeriphDrivers/Source/CRC/crc_reva.h b/Libraries/PeriphDrivers/Source/CRC/crc_reva.h index d4a06efee33..8e2c46f9b34 100644 --- a/Libraries/PeriphDrivers/Source/CRC/crc_reva.h +++ b/Libraries/PeriphDrivers/Source/CRC/crc_reva.h @@ -23,6 +23,7 @@ #include "crc.h" #include "crc_reva_regs.h" +#include "dma.h" /***** CRC Definitions *****/ /** @@ -41,7 +42,7 @@ typedef struct _mxc_crc_reva_req_t { */ typedef enum { CRC_REVA_LSB_FIRST, CRC_REVA_MSB_FIRST } mxc_crc_reva_bitorder_t; -int MXC_CRC_RevA_Init(mxc_crc_reva_regs_t *crc); +int MXC_CRC_RevA_Init(mxc_crc_reva_regs_t *crc, mxc_dma_regs_t *dma); int MXC_CRC_RevA_Shutdown(mxc_crc_reva_regs_t *crc); int MXC_CRC_RevA_Handler(int ch, int error); void MXC_CRC_RevA_SetDirection(mxc_crc_reva_regs_t *crc, mxc_crc_reva_bitorder_t bitOrder); diff --git a/Libraries/PeriphDrivers/Source/DMA/dma_me30.c b/Libraries/PeriphDrivers/Source/DMA/dma_me30.c index bab48e3c5e9..d0359eaa1da 100644 --- a/Libraries/PeriphDrivers/Source/DMA/dma_me30.c +++ b/Libraries/PeriphDrivers/Source/DMA/dma_me30.c @@ -32,31 +32,33 @@ /****** Functions ******/ -int MXC_DMA_Init(void) +int MXC_DMA_Init(mxc_dma_regs_t *dma) { #ifndef MSDK_NO_GPIO_CLK_INIT - if (MXC_DMA == MXC_DMA0 && !MXC_SYS_IsClockEnabled(MXC_SYS_PERIPH_CLOCK_DMA0)) { + if (dma == MXC_DMA0 && !MXC_SYS_IsClockEnabled(MXC_SYS_PERIPH_CLOCK_DMA0)) { MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_DMA0); MXC_SYS_Reset_Periph(MXC_SYS_RESET0_DMA0); } // TODO(ME30): There is no periph clock enable register for DMA1 atm - // else if (MXC_DMA == MXC_DMA1 && !MXC_SYS_IsClockEnabled(MXC_SYS_PERIPH_CLOCK_DMA1)) + // -Added but it's in feat/ME30 branch. + // Uncomment when merged. + // else if (dma == MXC_DMA1 && !MXC_SYS_IsClockEnabled(MXC_SYS_PERIPH_CLOCK_DMA1)) // MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_DMA1); // MXC_SYS_Reset_Periph(MXC_SYS_RESET0_DMA1); // } #endif - return MXC_DMA_RevA_Init((mxc_dma_reva_regs_t *)MXC_DMA); + return MXC_DMA_RevA_Init((mxc_dma_reva_regs_t *)dma); } -void MXC_DMA_DeInit(void) +void MXC_DMA_DeInit(mxc_dma_regs_t *dma) { - return MXC_DMA_RevA_DeInit((mxc_dma_reva_regs_t *)MXC_DMA); + return MXC_DMA_RevA_DeInit((mxc_dma_reva_regs_t *)dma); } -int MXC_DMA_AcquireChannel(void) +int MXC_DMA_AcquireChannel(mxc_dma_regs_t *dma) { - return MXC_DMA_RevA_AcquireChannel((mxc_dma_reva_regs_t *)MXC_DMA); + return MXC_DMA_RevA_AcquireChannel((mxc_dma_reva_regs_t *)dma); } int MXC_DMA_ReleaseChannel(int ch) @@ -124,14 +126,15 @@ int MXC_DMA_ChannelClearFlags(int ch, int flags) return MXC_DMA_RevA_ChannelClearFlags(ch, flags); } -int MXC_DMA_EnableInt(int ch) +// TODO(DMA): Check ME14 becasue you can only get ME14 intrs from MXC_DMA0. +int MXC_DMA_EnableInt(mxc_dma_regs_t *dma, int ch) { - return MXC_DMA_RevA_EnableInt((mxc_dma_reva_regs_t *)MXC_DMA, ch); + return MXC_DMA_RevA_EnableInt((mxc_dma_reva_regs_t *)dma, ch); } -int MXC_DMA_DisableInt(int ch) +int MXC_DMA_DisableInt(mxc_dma_regs_t *dma, int ch) { - return MXC_DMA_RevA_DisableInt((mxc_dma_reva_regs_t *)MXC_DMA, ch); + return MXC_DMA_RevA_DisableInt((mxc_dma_reva_regs_t *)dma, ch); } int MXC_DMA_Start(int ch) @@ -149,18 +152,18 @@ mxc_dma_ch_regs_t *MXC_DMA_GetCHRegs(int ch) return MXC_DMA_RevA_GetCHRegs(ch); } -void MXC_DMA_Handler(void) +void MXC_DMA_Handler(mxc_dma_regs_t *dma) { - MXC_DMA_RevA_Handler((mxc_dma_reva_regs_t *)MXC_DMA); + MXC_DMA_RevA_Handler((mxc_dma_reva_regs_t *)dma); } -int MXC_DMA_MemCpy(void *dest, void *src, int len, mxc_dma_complete_cb_t callback) +int MXC_DMA_MemCpy(mxc_dma_regs_t *dma, void *dest, void *src, int len, mxc_dma_complete_cb_t callback) { - return MXC_DMA_RevA_MemCpy((mxc_dma_reva_regs_t *)MXC_DMA, dest, src, len, callback); + return MXC_DMA_RevA_MemCpy((mxc_dma_reva_regs_t *)dma, dest, src, len, callback); } -int MXC_DMA_DoTransfer(mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, +int MXC_DMA_DoTransfer(mxc_dma_regs_t *dma, mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback) { - return MXC_DMA_RevA_DoTransfer((mxc_dma_reva_regs_t *)MXC_DMA, config, firstSrcDst, callback); + return MXC_DMA_RevA_DoTransfer((mxc_dma_reva_regs_t *)dma, config, firstSrcDst, callback); } diff --git a/Libraries/PeriphDrivers/Source/DMA/dma_reva.c b/Libraries/PeriphDrivers/Source/DMA/dma_reva.c index 6b8ac9a8436..05ba7bbbf89 100644 --- a/Libraries/PeriphDrivers/Source/DMA/dma_reva.c +++ b/Libraries/PeriphDrivers/Source/DMA/dma_reva.c @@ -470,7 +470,7 @@ int MXC_DMA_RevA_MemCpy(mxc_dma_reva_regs_t *dma, void *dest, void *src, int len mxc_dma_srcdst_t transfer; int channel; -#if TARGET_NUM == 32665 +#if (TARGET_NUM == 32665 || TARGET_NUM == 32657) channel = MXC_DMA_AcquireChannel((mxc_dma_regs_t *)dma); #else channel = MXC_DMA_AcquireChannel(); @@ -500,7 +500,11 @@ int MXC_DMA_RevA_MemCpy(mxc_dma_reva_regs_t *dma, void *dest, void *src, int len return retval; } +#if (TARGET_NUM == 32657) + retval = MXC_DMA_EnableInt((mxc_dma_regs_t *)dma, channel); +#else retval = MXC_DMA_EnableInt(channel); +#endif if (retval != E_NO_ERROR) { return retval; @@ -535,7 +539,7 @@ int MXC_DMA_RevA_DoTransfer(mxc_dma_reva_regs_t *dma, mxc_dma_config_t config, { int retval, channel; -#if TARGET_NUM == 32665 +#if (TARGET_NUM == 32665 || TARGET_NUM == 32657) channel = MXC_DMA_AcquireChannel((mxc_dma_regs_t *)dma); #else channel = MXC_DMA_AcquireChannel(); @@ -553,7 +557,11 @@ int MXC_DMA_RevA_DoTransfer(mxc_dma_reva_regs_t *dma, mxc_dma_config_t config, return retval; } +#if (TARGET_NUM == 32657) + retval = MXC_DMA_EnableInt((mxc_dma_regs_t *)dma, channel); +#else retval = MXC_DMA_EnableInt(channel); +#endif if (retval != E_NO_ERROR) { return retval; diff --git a/Libraries/PeriphDrivers/Source/SPI/spi_me30.c b/Libraries/PeriphDrivers/Source/SPI/spi_me30.c index b2e419561d2..3d75b2bcd37 100644 --- a/Libraries/PeriphDrivers/Source/SPI/spi_me30.c +++ b/Libraries/PeriphDrivers/Source/SPI/spi_me30.c @@ -337,7 +337,7 @@ int MXC_SPI_MasterTransactionAsync(mxc_spi_req_t *req) return MXC_SPI_RevA1_MasterTransactionAsync((mxc_spi_reva_req_t *)req); } -int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req) +int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req, mxc_dma_regs_t *dma) { int reqselTx = -1; int reqselRx = -1; @@ -377,8 +377,7 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req) } } - return MXC_SPI_RevA1_MasterTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, - MXC_DMA); + return MXC_SPI_RevA1_MasterTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, dma); } int MXC_SPI_SlaveTransaction(mxc_spi_req_t *req) @@ -391,7 +390,7 @@ int MXC_SPI_SlaveTransactionAsync(mxc_spi_req_t *req) return MXC_SPI_RevA1_SlaveTransactionAsync((mxc_spi_reva_req_t *)req); } -int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req) +int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req, mxc_dma_regs_t *dma) { int reqselTx = -1; int reqselRx = -1; @@ -433,8 +432,7 @@ int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req) } } - return MXC_SPI_RevA1_SlaveTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, - MXC_DMA); + return MXC_SPI_RevA1_SlaveTransactionDMA((mxc_spi_reva_req_t *)req, reqselTx, reqselRx, dma); } int MXC_SPI_SetDefaultTXData(mxc_spi_regs_t *spi, unsigned int defaultTXData) diff --git a/Libraries/PeriphDrivers/Source/SPI/spi_reva1.c b/Libraries/PeriphDrivers/Source/SPI/spi_reva1.c index 4c7fd64e6dc..74b8871e5f3 100644 --- a/Libraries/PeriphDrivers/Source/SPI/spi_reva1.c +++ b/Libraries/PeriphDrivers/Source/SPI/spi_reva1.c @@ -952,7 +952,7 @@ int MXC_SPI_RevA1_MasterTransactionDMA(mxc_spi_reva_req_t *req, int reqselTx, in // for non-MT mode do this setup every time, for MT mode only first time if ((states[spi_num].mtMode == 0) || ((states[spi_num].mtMode == 1) && (states[spi_num].mtFirstTrans == 1))) { -#if TARGET_NUM == 32665 +#if (TARGET_NUM == 32665 || TARGET_NUM == 32657) MXC_DMA_Init(dma); states[spi_num].channelTx = MXC_DMA_AcquireChannel(dma); states[spi_num].channelRx = MXC_DMA_AcquireChannel(dma); @@ -1009,7 +1009,13 @@ int MXC_SPI_RevA1_MasterTransactionDMA(mxc_spi_reva_req_t *req, int reqselTx, in //tx if (req->txData != NULL && !tx_is_complete) { MXC_DMA_SetCallback(states[spi_num].channelTx, MXC_SPI_RevA1_DMACallback); + +#if (TARGET_NUM == 32657) + MXC_DMA_EnableInt(dma, states[spi_num].channelTx); +#else MXC_DMA_EnableInt(states[spi_num].channelTx); +#endif + config.reqsel = (mxc_dma_reqsel_t)reqselTx; config.ch = states[spi_num].channelTx; advConfig.ch = states[spi_num].channelTx; @@ -1049,7 +1055,13 @@ int MXC_SPI_RevA1_MasterTransactionDMA(mxc_spi_reva_req_t *req, int reqselTx, in // rx if (req->rxData != NULL && !rx_is_complete) { MXC_DMA_SetCallback(states[spi_num].channelRx, MXC_SPI_RevA1_DMACallback); + +#if (TARGET_NUM == 32657) + MXC_DMA_EnableInt(dma, states[spi_num].channelRx); +#else MXC_DMA_EnableInt(states[spi_num].channelRx); +#endif + config.reqsel = (mxc_dma_reqsel_t)reqselRx; config.ch = states[spi_num].channelRx; config.srcinc_en = 0; @@ -1160,7 +1172,7 @@ int MXC_SPI_RevA1_SlaveTransactionDMA(mxc_spi_reva_req_t *req, int reqselTx, int // for non-MT mode do this setup every time, for MT mode only first time if ((states[spi_num].mtMode == 0) || ((states[spi_num].mtMode == 1) && (states[spi_num].mtFirstTrans == 1))) { -#if TARGET_NUM == 32665 +#if (TARGET_NUM == 32665 || TARGET_NUM == 32657) MXC_DMA_Init(dma); states[spi_num].channelTx = MXC_DMA_AcquireChannel(dma); states[spi_num].channelRx = MXC_DMA_AcquireChannel(dma); @@ -1180,8 +1192,14 @@ int MXC_SPI_RevA1_SlaveTransactionDMA(mxc_spi_reva_req_t *req, int reqselTx, int MXC_DMA_SetCallback(states[spi_num].channelTx, MXC_SPI_RevA1_DMACallback); MXC_DMA_SetCallback(states[spi_num].channelRx, MXC_SPI_RevA1_DMACallback); + +#if (TARGET_NUM == 32657) + MXC_DMA_EnableInt(dma, states[spi_num].channelTx); + MXC_DMA_EnableInt(dma, states[spi_num].channelRx); +#else MXC_DMA_EnableInt(states[spi_num].channelTx); MXC_DMA_EnableInt(states[spi_num].channelRx); +#endif } bits = MXC_SPI_GetDataSize((mxc_spi_regs_t *)req->spi); diff --git a/Libraries/PeriphDrivers/Source/SYS/sys_me30.c b/Libraries/PeriphDrivers/Source/SYS/sys_me30.c index e03cd7c5cfd..78e09ee40bc 100644 --- a/Libraries/PeriphDrivers/Source/SYS/sys_me30.c +++ b/Libraries/PeriphDrivers/Source/SYS/sys_me30.c @@ -93,7 +93,10 @@ int MXC_SYS_GetUSN(uint8_t *usn, uint8_t *checksum) checksum[0] = ((infoblock[3] & 0x7F800000) >> 23); checksum[1] = ((infoblock[4] & 0x007F8000) >> 15); - err = MXC_AES_Init(); + // Info block only accessible for secure code. + // Use Secure DMA1. + // TODO(DMA): Figure out access to "secure" functions when in non-secure code. + err = MXC_AES_Init(MXC_DMA1); if (err) { MXC_FLC_LockInfoBlock(MXC_INFO_MEM_BASE); return err; diff --git a/Libraries/PeriphDrivers/Source/UART/uart_me30.c b/Libraries/PeriphDrivers/Source/UART/uart_me30.c index 83eb8202790..303d21c973a 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_me30.c +++ b/Libraries/PeriphDrivers/Source/UART/uart_me30.c @@ -182,13 +182,13 @@ unsigned int MXC_UART_ReadRXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, un return MXC_UART_RevA_ReadRXFIFO((mxc_uart_reva_regs_t *)uart, bytes, len); } -int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len, +int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, mxc_dma_regs_t *dma, unsigned char *bytes, unsigned int len, mxc_uart_dma_complete_cb_t callback) { mxc_dma_config_t config; config.reqsel = MXC_DMA_REQUEST_UART0RX; // TODO(ME30): Updated DMA reqsel - return MXC_UART_RevA_ReadRXFIFODMA((mxc_uart_reva_regs_t *)uart, MXC_DMA, bytes, len, callback, + return MXC_UART_RevA_ReadRXFIFODMA((mxc_uart_reva_regs_t *)uart, dma, bytes, len, callback, config); } @@ -202,13 +202,13 @@ unsigned int MXC_UART_WriteTXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, u return MXC_UART_RevA_WriteTXFIFO((mxc_uart_reva_regs_t *)uart, bytes, len); } -int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len, +int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, mxc_dma_regs_t *dma, unsigned char *bytes, unsigned int len, mxc_uart_dma_complete_cb_t callback) { mxc_dma_config_t config; config.reqsel = MXC_DMA_REQUEST_UART0TX; // TODO(ME30): Updated DMA reqsel - return MXC_UART_RevA_WriteTXFIFODMA((mxc_uart_reva_regs_t *)uart, MXC_DMA, bytes, len, callback, + return MXC_UART_RevA_WriteTXFIFODMA((mxc_uart_reva_regs_t *)uart, dma, bytes, len, callback, config); } @@ -282,9 +282,9 @@ int MXC_UART_TransactionAsync(mxc_uart_req_t *req) return MXC_UART_RevA_TransactionAsync((mxc_uart_reva_req_t *)req); } -int MXC_UART_TransactionDMA(mxc_uart_req_t *req) +int MXC_UART_TransactionDMA(mxc_uart_req_t *req, mxc_dma_regs_t *dma) { - return MXC_UART_RevA_TransactionDMA((mxc_uart_reva_req_t *)req, MXC_DMA); + return MXC_UART_RevA_TransactionDMA((mxc_uart_reva_req_t *)req, dma); } int MXC_UART_AbortAsync(mxc_uart_regs_t *uart) diff --git a/Libraries/PeriphDrivers/Source/UART/uart_reva.c b/Libraries/PeriphDrivers/Source/UART/uart_reva.c index 2256afe35a1..5ba07b5c3e4 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_reva.c +++ b/Libraries/PeriphDrivers/Source/UART/uart_reva.c @@ -48,6 +48,7 @@ typedef struct { int channelTx; int channelRx; bool auto_dma_handlers; + mxc_dma_regs_t *dma; } uart_reva_req_state_t; uart_reva_req_state_t states[MXC_UART_INSTANCES]; @@ -99,6 +100,7 @@ int MXC_UART_RevA_Init(mxc_uart_reva_regs_t *uart, unsigned int baud) states[i].tx_req = NULL; states[i].rx_req = NULL; states[i].auto_dma_handlers = false; + states[i].dma = NULL; return E_NO_ERROR; } @@ -502,7 +504,13 @@ unsigned int MXC_UART_RevA_ReadRXFIFO(mxc_uart_reva_regs_t *uart, unsigned char return read; } -#if MXC_DMA_INSTANCES > 1 + +// TODO(DMA): Replaced the DMA instance number check to the only +// parts affected by this. Our DMA drivers probably +// needs a rework to handle multiple instances because +// the ME14's DMA drivers are very limited with +// the DMA instance selection. +#if (TARGET_NUM == 32665 || TARGET_NUM == 32657) void MXC_UART_RevA_DMA0_Handler(void) { @@ -522,19 +530,21 @@ DMA instance. void MXC_UART_RevA_DMA_SetupAutoHandlers(mxc_dma_regs_t *dma_instance, unsigned int channel) { #ifdef __arm__ - NVIC_EnableIRQ(MXC_DMA_CH_GET_IRQ(channel)); +#if (TARGET_NUM == 32665 || TARGET_NUM == 32657) + NVIC_EnableIRQ(MXC_DMA_CH_GET_IRQ(dma_instance, channel)); -#if MXC_DMA_INSTANCES > 1 /* (JC): This is not the cleanest or most scalable way to do this, but I tried defining default handler's in the system file. Some complications make this the most attractive short-term option. We could handle multiple DMA instances better in the DMA API (See the mismatch between the size of "dma_resource" array and the number of channels per instance, to start)*/ if (dma_instance == MXC_DMA0) { - MXC_NVIC_SetVector(MXC_DMA_CH_GET_IRQ(channel), MXC_UART_RevA_DMA0_Handler); + MXC_NVIC_SetVector(MXC_DMA_CH_GET_IRQ(dma_instance, channel), MXC_UART_RevA_DMA0_Handler); } else if (dma_instance == MXC_DMA1) { - MXC_NVIC_SetVector(MXC_DMA_CH_GET_IRQ(channel), MXC_UART_RevA_DMA1_Handler); + MXC_NVIC_SetVector(MXC_DMA_CH_GET_IRQ(dma_instance, channel), MXC_UART_RevA_DMA1_Handler); } #else + NVIC_EnableIRQ(MXC_DMA_CH_GET_IRQ(channel)); + // Only one DMA instance, we can point direct to MXC_DMA_Handler MXC_NVIC_SetVector(MXC_DMA_CH_GET_IRQ(channel), MXC_DMA_Handler); #endif // MXC_DMA_INSTANCES > 1 @@ -560,7 +570,7 @@ int MXC_UART_RevA_ReadRXFIFODMA(mxc_uart_reva_regs_t *uart, mxc_dma_regs_t *dma, if (states[uart_num].auto_dma_handlers && states[uart_num].channelRx < 0) { /* Acquire channel if we don't have one already */ -#if MXC_DMA_INSTANCES > 1 +#if MXC_DMA_INSTANCES > 1 || TARGET_NUM == 32657 channel = MXC_DMA_AcquireChannel(dma); #else channel = MXC_DMA_AcquireChannel(); @@ -591,7 +601,13 @@ int MXC_UART_RevA_ReadRXFIFODMA(mxc_uart_reva_regs_t *uart, mxc_dma_regs_t *dma, MXC_DMA_ConfigChannel(config, srcdst); MXC_DMA_SetCallback(channel, MXC_UART_DMACallback); + +#if (TARGET_NUM == 32657) + MXC_DMA_EnableInt(dma, channel); +#else MXC_DMA_EnableInt(channel); +#endif + MXC_DMA_Start(channel); //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; MXC_DMA_SetChannelInterruptEn(channel, 0, 1); @@ -679,7 +695,7 @@ unsigned int MXC_UART_RevA_WriteTXFIFODMA(mxc_uart_reva_regs_t *uart, mxc_dma_re if (states[uart_num].auto_dma_handlers && states[uart_num].channelTx < 0) { /* Acquire channel if we don't have one already */ -#if TARGET_NUM == 32665 +#if (TARGET_NUM == 32665 || TARGET_NUM == 32657) channel = MXC_DMA_AcquireChannel(dma); #else channel = MXC_DMA_AcquireChannel(); @@ -708,7 +724,13 @@ unsigned int MXC_UART_RevA_WriteTXFIFODMA(mxc_uart_reva_regs_t *uart, mxc_dma_re MXC_DMA_ConfigChannel(config, srcdst); MXC_DMA_SetCallback(channel, MXC_UART_DMACallback); + +#if (TARGET_NUM == 32657) + MXC_DMA_EnableInt(dma, channel); +#else MXC_DMA_EnableInt(channel); +#endif + MXC_DMA_Start(channel); //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; MXC_DMA_SetChannelInterruptEn(channel, 0, 1); @@ -951,6 +973,9 @@ int MXC_UART_RevA_TransactionDMA(mxc_uart_reva_req_t *req, mxc_dma_regs_t *dma) { int uart_num = MXC_UART_GET_IDX((mxc_uart_regs_t *)(req->uart)); + // Save DMA instance for DMA Callback. + states[uart_num].dma = dma; + if (req->txLen) { if (req->txData == NULL) { return E_BAD_PARAM; @@ -976,7 +1001,7 @@ int MXC_UART_RevA_TransactionDMA(mxc_uart_reva_req_t *req, mxc_dma_regs_t *dma) (req->uart)->dma |= (2 << MXC_F_UART_REVA_DMA_TXDMA_LEVEL_POS); // Set TX DMA threshold to 2 bytes -#if TARGET_NUM == 32665 +#if (TARGET_NUM == 32665 || TARGET_NUM == 32657) MXC_DMA_Init(dma); #else MXC_DMA_Init(); @@ -990,7 +1015,7 @@ int MXC_UART_RevA_TransactionDMA(mxc_uart_reva_req_t *req, mxc_dma_regs_t *dma) if ((req->txData != NULL) && (req->txLen)) { /* Save TX req, the DMA handler will use this later. */ states[uart_num].tx_req = req; -#if TARGET_NUM == 32665 +#if (TARGET_NUM == 32665 || TARGET_NUM == 32657) if (MXC_UART_WriteTXFIFODMA((mxc_uart_regs_t *)(req->uart), dma, req->txData, req->txLen, NULL) != E_NO_ERROR) { return E_BAD_PARAM; @@ -1005,7 +1030,7 @@ int MXC_UART_RevA_TransactionDMA(mxc_uart_reva_req_t *req, mxc_dma_regs_t *dma) if ((req->rxData != NULL) && (req->rxLen)) { states[uart_num].rx_req = req; -#if TARGET_NUM == 32665 +#if (TARGET_NUM == 32665 || TARGET_NUM == 32657) if (MXC_UART_ReadRXFIFODMA((mxc_uart_regs_t *)(req->uart), dma, req->rxData, req->rxLen, NULL) != E_NO_ERROR) { return E_BAD_PARAM; @@ -1029,7 +1054,7 @@ void MXC_UART_RevA_DMACallback(int ch, int error) if (states[i].channelTx == ch) { /* Populate txLen. The number of "remainder" bytes is what's left on the DMA channel's count register. */ - states[i].tx_req->txCnt = states[i].tx_req->txLen - MXC_DMA->ch[ch].cnt; + states[i].tx_req->txCnt = states[i].tx_req->txLen - states[i].dma->ch[ch].cnt; temp_req = states[i].tx_req; @@ -1051,7 +1076,7 @@ void MXC_UART_RevA_DMACallback(int ch, int error) break; } else if (states[i].channelRx == ch) { /* Same as above, but for RX */ - states[i].rx_req->rxCnt = states[i].rx_req->rxLen - MXC_DMA->ch[ch].cnt; + states[i].rx_req->rxCnt = states[i].rx_req->rxLen - states[i].dma->ch[ch].cnt; temp_req = states[i].rx_req; if (states[i].auto_dma_handlers) { MXC_DMA_ReleaseChannel(ch); From fd6d3aa3458926c286b244429ada698439b40721 Mon Sep 17 00:00:00 2001 From: Woo Date: Mon, 6 May 2024 16:51:42 -0500 Subject: [PATCH 68/93] Add comment to enable ICC after testing --- Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c index 960bb98bf57..417f887b2ab 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c @@ -157,6 +157,9 @@ __weak void SystemInit(void) /* Enable interrupts */ __enable_irq(); + // TODO(ICC): Enable the internal cache controller after testing. + // MXC_ICC_Enable(); + /* Change system clock source to the main high-speed clock */ MXC_SYS_Clock_Select(MXC_SYS_CLOCK_IPO); MXC_SYS_SetClockDiv(MXC_SYS_CLOCK_DIV_1); From af0a35ee51e78c96d564431cc0f5890bafe377eb Mon Sep 17 00:00:00 2001 From: Woo Date: Tue, 7 May 2024 10:04:58 -0500 Subject: [PATCH 69/93] Removed CRYPTO_FREQ legacy definition warning and limit default Stack and Heap sizes --- .../CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h | 6 ------ .../Device/Maxim/MAX32657/Source/GCC/startup_max32657.S | 8 ++++---- 2 files changed, 4 insertions(+), 10 deletions(-) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h index 981c23d80c7..a0a5f81ca15 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/system_max32657.h @@ -29,12 +29,6 @@ extern "C" { Define clocks *----------------------------------------------------------------------------*/ -/* NOTE: HIRC was previously named CRYPTO */ -#ifdef CRYPTO_FREQ -#warning WARNING: CRYPTO_FREQ does not exist in MAX78000, replace with HIRC_FREQ! -#define HIRC_FREQ CRYPTO_FREQ -#endif - /* NOTE: EXTCLK needs to be defined by user based on the clock they supply */ #ifndef EXTCLK_FREQ #define EXTCLK_FREQ 75000000 diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/startup_max32657.S b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/startup_max32657.S index 2a4348f73c2..7bc5785f1a1 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/startup_max32657.S +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/startup_max32657.S @@ -26,8 +26,8 @@ #ifdef __STACK_SIZE .equ Stack_Size, __STACK_SIZE #else - // Default stack size (192KB) - .equ Stack_Size, 0x00030000 + // Default stack size + .equ Stack_Size, 0x00001000 #endif .globl __StackTop .globl __StackLimit @@ -47,8 +47,8 @@ __StackTop: #ifdef __HEAP_SIZE .equ Heap_Size, __HEAP_SIZE #else - // Default heap size (64KB) - .equ Heap_Size, 0x00010000 + // Default heap size + .equ Heap_Size, 0x00000C00 #endif .globl __HeapBase .globl __HeapLimit From d1247dda8af394a39c577bde058de29590e5dba6 Mon Sep 17 00:00:00 2001 From: Woo Date: Tue, 7 May 2024 13:28:27 -0500 Subject: [PATCH 70/93] Fix TMR4/5 mappings --- Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h index 24a89242cdd..967c7248e0e 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h @@ -529,9 +529,9 @@ We may want to handle GET_IRQ better... #define MXC_TMR2_NS ((mxc_tmr_regs_t *)MXC_BASE_TMR2_NS) #define MXC_BASE_TMR3_NS ((uint32_t)0x40013000UL) #define MXC_TMR3_NS ((mxc_tmr_regs_t *)MXC_BASE_TMR3_NS) -#define MXC_BASE_TMR4_NS ((uint32_t)0x40080C00UL) +#define MXC_BASE_TMR4_NS ((uint32_t)0x40014000UL) #define MXC_TMR4_NS ((mxc_tmr_regs_t *)MXC_BASE_TMR4_NS) -#define MXC_BASE_TMR5_NS ((uint32_t)0x40081000UL) +#define MXC_BASE_TMR5_NS ((uint32_t)0x40015000UL) #define MXC_TMR5_NS ((mxc_tmr_regs_t *)MXC_BASE_TMR5_NS) /* Secure Mapping */ @@ -543,9 +543,9 @@ We may want to handle GET_IRQ better... #define MXC_TMR2_S ((mxc_tmr_regs_t *)MXC_BASE_TMR2_S) #define MXC_BASE_TMR3_S ((uint32_t)0x50013000UL) #define MXC_TMR3_S ((mxc_tmr_regs_t *)MXC_BASE_TMR3_S) -#define MXC_BASE_TMR4_S ((uint32_t)0x50080C00UL) +#define MXC_BASE_TMR4_S ((uint32_t)0x50014000UL) #define MXC_TMR4_S ((mxc_tmr_regs_t *)MXC_BASE_TMR4_S) -#define MXC_BASE_TMR5_S ((uint32_t)0x50081000UL) +#define MXC_BASE_TMR5_S ((uint32_t)0x50015000UL) #define MXC_TMR5_S ((mxc_tmr_regs_t *)MXC_BASE_TMR5_S) #if IS_SECURE_ENVIRONMENT From 217e1feeaa3b36d805670c5ba28a274ced25058f Mon Sep 17 00:00:00 2001 From: Woo Date: Tue, 7 May 2024 13:45:40 -0500 Subject: [PATCH 71/93] Add Secure Fault Handler --- Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h | 1 + .../CMSIS/Device/Maxim/MAX32657/Source/GCC/startup_max32657.S | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h index 967c7248e0e..1e918e4d372 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h @@ -65,6 +65,7 @@ typedef enum { MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, + SecureFault_IRQn = -9, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/startup_max32657.S b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/startup_max32657.S index 7bc5785f1a1..2fe3954e105 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/startup_max32657.S +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/startup_max32657.S @@ -72,7 +72,7 @@ __isr_vector: .long MemManage_Handler /* MPU Fault Handler */ .long BusFault_Handler /* Bus Fault Handler */ .long UsageFault_Handler /* Usage Fault Handler */ - .long 0 /* Reserved */ + .long SecureFault_Handler /* Secure Fault Handler */ .long 0 /* Reserved */ .long 0 /* Reserved */ .long 0 /* Reserved */ @@ -258,6 +258,7 @@ Reset_Handler: def_irq_handler MemManage_Handler def_irq_handler BusFault_Handler def_irq_handler UsageFault_Handler + def_irq_handler SecureFault_Handler def_irq_handler SVC_Handler def_irq_handler DebugMon_Handler def_irq_handler PendSV_Handler From bee600f869a0a58d955cf4fed29b40be618ea48e Mon Sep 17 00:00:00 2001 From: Woo Date: Wed, 8 May 2024 10:26:11 -0500 Subject: [PATCH 72/93] Initial update for ME30 pins --- .../PeriphDrivers/Include/MAX32657/mxc_pins.h | 75 +++-------------- Libraries/PeriphDrivers/Source/RTC/rtc_me30.c | 3 +- .../PeriphDrivers/Source/SYS/pins_me30.c | 82 +++++++++---------- .../PeriphDrivers/Source/UART/uart_me30.c | 6 +- 4 files changed, 56 insertions(+), 110 deletions(-) diff --git a/Libraries/PeriphDrivers/Include/MAX32657/mxc_pins.h b/Libraries/PeriphDrivers/Include/MAX32657/mxc_pins.h index c16d1399521..ee29193192a 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/mxc_pins.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/mxc_pins.h @@ -28,82 +28,33 @@ /***** Global Variables *****/ // Predefined GPIO Configurations -extern const mxc_gpio_cfg_t gpio_cfg_extclk; -extern const mxc_gpio_cfg_t gpio_cfg_i2c0; -extern const mxc_gpio_cfg_t gpio_cfg_i2c1; -extern const mxc_gpio_cfg_t gpio_cfg_i2c2; -extern const mxc_gpio_cfg_t gpio_cfg_i2c2b; -extern const mxc_gpio_cfg_t gpio_cfg_i2c2c; +extern const mxc_gpio_cfg_t gpio_cfg_i3c; -extern const mxc_gpio_cfg_t gpio_cfg_uart0; -extern const mxc_gpio_cfg_t gpio_cfg_uart0_flow; -extern const mxc_gpio_cfg_t gpio_cfg_uart0_flow_disable; -extern const mxc_gpio_cfg_t gpio_cfg_uart1; -extern const mxc_gpio_cfg_t gpio_cfg_uart1_flow; -extern const mxc_gpio_cfg_t gpio_cfg_uart1_flow_disable; -extern const mxc_gpio_cfg_t gpio_cfg_uart2; -extern const mxc_gpio_cfg_t gpio_cfg_uart2_flow; -extern const mxc_gpio_cfg_t gpio_cfg_uart2_flow_disable; -extern const mxc_gpio_cfg_t gpio_cfg_uart3; - -extern const mxc_gpio_cfg_t antenna_ctrl0; -extern const mxc_gpio_cfg_t antenna_ctrl1; +extern const mxc_gpio_cfg_t gpio_cfg_uart; // Timers are only defined once, depending on package, each timer could be mapped to other pins extern const mxc_gpio_cfg_t gpio_cfg_tmr0; extern const mxc_gpio_cfg_t gpio_cfg_tmr1; extern const mxc_gpio_cfg_t gpio_cfg_tmr2; extern const mxc_gpio_cfg_t gpio_cfg_tmr3; +extern const mxc_gpio_cfg_t gpio_cfg_tmr4; +extern const mxc_gpio_cfg_t gpio_cfg_tmr5; extern const mxc_gpio_cfg_t gpio_cfg_tmr0b; extern const mxc_gpio_cfg_t gpio_cfg_tmr1b; -extern const mxc_gpio_cfg_t gpio_cfg_tmr1_MapB; extern const mxc_gpio_cfg_t gpio_cfg_tmr2b; extern const mxc_gpio_cfg_t gpio_cfg_tmr3b; - -extern const mxc_gpio_cfg_t gpio_cfg_i2s0; -extern const mxc_gpio_cfg_t gpio_cfg_i2s0_clkext; - -extern const mxc_gpio_cfg_t gpio_cfg_owm; -extern const mxc_gpio_cfg_t gpio_cfg_owmb; - -extern const mxc_gpio_cfg_t gpio_cfg_rtcsqw; -extern const mxc_gpio_cfg_t gpio_cfg_rtcsqwb; - -extern const mxc_gpio_cfg_t gpio_cfg_pt0; -extern const mxc_gpio_cfg_t gpio_cfg_pt1; -extern const mxc_gpio_cfg_t gpio_cfg_pt2; -extern const mxc_gpio_cfg_t gpio_cfg_pt3; - -extern const mxc_gpio_cfg_t gpio_cfg_adc_ain0; -extern const mxc_gpio_cfg_t gpio_cfg_adc_ain1; -extern const mxc_gpio_cfg_t gpio_cfg_adc_ain2; -extern const mxc_gpio_cfg_t gpio_cfg_adc_ain3; -extern const mxc_gpio_cfg_t gpio_cfg_adc_ain4; -extern const mxc_gpio_cfg_t gpio_cfg_adc_ain5; -extern const mxc_gpio_cfg_t gpio_cfg_adc_ain6; -extern const mxc_gpio_cfg_t gpio_cfg_adc_ain7; - -extern const mxc_gpio_cfg_t gpio_cfg_rv_jtag; - -extern const mxc_gpio_cfg_t gpio_cfg_cmp0; -extern const mxc_gpio_cfg_t gpio_cfg_cmp1; -extern const mxc_gpio_cfg_t gpio_cfg_cmp2; -extern const mxc_gpio_cfg_t gpio_cfg_cmp3; +extern const mxc_gpio_cfg_t gpio_cfg_tmr4b; +extern const mxc_gpio_cfg_t gpio_cfg_tmr5b; // SPI v2 Pin Definitions -extern const mxc_gpio_cfg_t gpio_cfg_spi0_standard; -extern const mxc_gpio_cfg_t gpio_cfg_spi0_3wire; -extern const mxc_gpio_cfg_t gpio_cfg_spi0_dual; -extern const mxc_gpio_cfg_t gpio_cfg_spi0_quad; -extern const mxc_gpio_cfg_t gpio_cfg_spi1_standard; -extern const mxc_gpio_cfg_t gpio_cfg_spi1_3wire; -extern const mxc_gpio_cfg_t gpio_cfg_spi1_dual; -extern const mxc_gpio_cfg_t gpio_cfg_spi1_quad; +extern const mxc_gpio_cfg_t gpio_cfg_spi_standard; +extern const mxc_gpio_cfg_t gpio_cfg_spi_3wire; +extern const mxc_gpio_cfg_t gpio_cfg_spi_dual; +extern const mxc_gpio_cfg_t gpio_cfg_spi_quad; // SPI v2 Target Selects Pin Definitions -extern const mxc_gpio_cfg_t gpio_cfg_spi0_ts0; -extern const mxc_gpio_cfg_t gpio_cfg_spi0_ts1; -extern const mxc_gpio_cfg_t gpio_cfg_spi0_ts2; -extern const mxc_gpio_cfg_t gpio_cfg_spi1_ts0; +extern const mxc_gpio_cfg_t gpio_cfg_spi_ts0; +extern const mxc_gpio_cfg_t gpio_cfg_spi_ts1; +extern const mxc_gpio_cfg_t gpio_cfg_spi_ts2; #endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_MXC_PINS_H_ diff --git a/Libraries/PeriphDrivers/Source/RTC/rtc_me30.c b/Libraries/PeriphDrivers/Source/RTC/rtc_me30.c index df0dac1d216..c8fe6636bf6 100644 --- a/Libraries/PeriphDrivers/Source/RTC/rtc_me30.c +++ b/Libraries/PeriphDrivers/Source/RTC/rtc_me30.c @@ -84,7 +84,8 @@ int MXC_RTC_Init(uint32_t sec, uint16_t ssec) int MXC_RTC_SquareWaveStart(mxc_rtc_freq_sel_t ft) { - MXC_GPIO_Config(&gpio_cfg_rtcsqw); + // TODO(RTC): Use MCR registers for GPIO Port 1 configuration. + MXC_MCR->outen |= MXC_F_MCR_OUTEN_SQWOUT_EN; return MXC_RTC_RevA_SquareWave((mxc_rtc_reva_regs_t *)MXC_RTC, MXC_RTC_REVA_SQUARE_WAVE_ENABLED, diff --git a/Libraries/PeriphDrivers/Source/SYS/pins_me30.c b/Libraries/PeriphDrivers/Source/SYS/pins_me30.c index 8b8e6b4afda..8bd7a5be81f 100644 --- a/Libraries/PeriphDrivers/Source/SYS/pins_me30.c +++ b/Libraries/PeriphDrivers/Source/SYS/pins_me30.c @@ -24,62 +24,58 @@ /***** Global Variables *****/ // clang-format off -const mxc_gpio_cfg_t gpio_cfg_extclk = { MXC_GPIO0, (MXC_GPIO_PIN_12 | MXC_GPIO_PIN_13), MXC_GPIO_FUNC_ALT2, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; - -const mxc_gpio_cfg_t gpio_cfg_i2c0 = { MXC_GPIO0, (MXC_GPIO_PIN_10 | MXC_GPIO_PIN_11), MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_i2c1 = { MXC_GPIO0, (MXC_GPIO_PIN_16 | MXC_GPIO_PIN_17), MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_i2c2 = { MXC_GPIO0, (MXC_GPIO_PIN_30 | MXC_GPIO_PIN_31), MXC_GPIO_FUNC_ALT1, +// P0.0 - I3C SCL +// P0.1 - I3C SDA +const mxc_gpio_cfg_t gpio_cfg_i3c = { MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_uart0 = { MXC_GPIO0, (MXC_GPIO_PIN_0 | MXC_GPIO_PIN_1), MXC_GPIO_FUNC_ALT1, +// P0.5 - UART RX +// P0.9 - UART TX +const mxc_gpio_cfg_t gpio_cfg_uart = { MXC_GPIO0, (MXC_GPIO_PIN_5 | MXC_GPIO_PIN_9), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_uart0_flow = { MXC_GPIO0, (MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3), MXC_GPIO_FUNC_ALT2, - MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_uart0_flow_disable = { MXC_GPIO0, (MXC_GPIO_PIN_2 | MXC_GPIO_PIN_3), MXC_GPIO_FUNC_IN, - MXC_GPIO_PAD_WEAK_PULL_UP, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -// const mxc_gpio_cfg_t antenna_ctrl0 = { MXC_GPIO1, (MXC_GPIO_PIN_8 | MXC_GPIO_PIN_9), MXC_GPIO_FUNC_ALT1, -// MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -// const mxc_gpio_cfg_t antenna_ctrl1 = { MXC_GPIO1, (MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7), MXC_GPIO_FUNC_ALT2, -// MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -// TODO(ME30): TMR pins // Timers are only defined once, depending on package, each timer could be mapped to other pins -// const mxc_gpio_cfg_t gpio_cfg_tmr0 = { MXC_GPIO0, (MXC_GPIO_PIN_2), MXC_GPIO_FUNC_ALT1, -// MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -// const mxc_gpio_cfg_t gpio_cfg_tmr0b = { MXC_GPIO0, (MXC_GPIO_PIN_3), MXC_GPIO_FUNC_ALT1, -// MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -// const mxc_gpio_cfg_t gpio_cfg_tmr1 = { MXC_GPIO0, (MXC_GPIO_PIN_14), MXC_GPIO_FUNC_ALT1, -// MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -// const mxc_gpio_cfg_t gpio_cfg_tmr1b = { MXC_GPIO0, (MXC_GPIO_PIN_15), MXC_GPIO_FUNC_ALT1, -// MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -// const mxc_gpio_cfg_t gpio_cfg_tmr1_MapB = { MXC_GPIO0, (MXC_GPIO_PIN_20), MXC_GPIO_FUNC_ALT2, -// MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -// const mxc_gpio_cfg_t gpio_cfg_tmr2 = { MXC_GPIO0, (MXC_GPIO_PIN_26), MXC_GPIO_FUNC_ALT1, -// MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -// const mxc_gpio_cfg_t gpio_cfg_tmr2b = { MXC_GPIO0, (MXC_GPIO_PIN_27), MXC_GPIO_FUNC_ALT1, -// MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -// const mxc_gpio_cfg_t gpio_cfg_tmr3 = { MXC_GPIO1, (MXC_GPIO_PIN_6), MXC_GPIO_FUNC_ALT1, -// MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -// const mxc_gpio_cfg_t gpio_cfg_tmr3b = { MXC_GPIO1, (MXC_GPIO_PIN_7), MXC_GPIO_FUNC_ALT1, -// MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_tmr0 = { MXC_GPIO0, (MXC_GPIO_PIN_0), MXC_GPIO_FUNC_ALT2, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_tmr0b = { MXC_GPIO0, (MXC_GPIO_PIN_5), MXC_GPIO_FUNC_ALT2, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_tmr1 = { MXC_GPIO0, (MXC_GPIO_PIN_1), MXC_GPIO_FUNC_ALT2, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_tmr1b = { MXC_GPIO0, (MXC_GPIO_PIN_9), MXC_GPIO_FUNC_ALT2, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_tmr2 = { MXC_GPIO0, (MXC_GPIO_PIN_10), MXC_GPIO_FUNC_ALT2, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_tmr3 = { MXC_GPIO0, (MXC_GPIO_PIN_2), MXC_GPIO_FUNC_ALT2, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_tmr3b = { MXC_GPIO0, (MXC_GPIO_PIN_7), MXC_GPIO_FUNC_ALT2, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_tmr4 = { MXC_GPIO0, (MXC_GPIO_PIN_3), MXC_GPIO_FUNC_ALT2, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_tmr4b = { MXC_GPIO0, (MXC_GPIO_PIN_6), MXC_GPIO_FUNC_ALT2, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_tmr5 = { MXC_GPIO0, (MXC_GPIO_PIN_4), MXC_GPIO_FUNC_ALT2, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; +const mxc_gpio_cfg_t gpio_cfg_tmr5b = { MXC_GPIO0, (MXC_GPIO_PIN_11), MXC_GPIO_FUNC_ALT2, + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; // SPI v2 Pin Definitions -const mxc_gpio_cfg_t gpio_cfg_spi0_standard = { MXC_GPIO0, (MXC_GPIO_PIN_5 | MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7), +// P0.2 - SPI SDO (COTI) +// P0.4 - SPI SDI (CITO) +// P0.6 - SPI CLK +const mxc_gpio_cfg_t gpio_cfg_spi_standard = { MXC_GPIO0, (MXC_GPIO_PIN_2 | MXC_GPIO_PIN_4 | MXC_GPIO_PIN_6), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_spi0_3wire = { MXC_GPIO0, (MXC_GPIO_PIN_5 | MXC_GPIO_PIN_7), MXC_GPIO_FUNC_ALT1, +const mxc_gpio_cfg_t gpio_cfg_spi_3wire = { MXC_GPIO0, (MXC_GPIO_PIN_2 | MXC_GPIO_PIN_6), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_spi0_dual = { MXC_GPIO0, (MXC_GPIO_PIN_5 | MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7), MXC_GPIO_FUNC_ALT1, +const mxc_gpio_cfg_t gpio_cfg_spi_dual = { MXC_GPIO0, (MXC_GPIO_PIN_2 | MXC_GPIO_PIN_4 | MXC_GPIO_PIN_6), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_spi0_quad = { MXC_GPIO0, (MXC_GPIO_PIN_5 | MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7 | MXC_GPIO_PIN_8 | MXC_GPIO_PIN_9), +// TODO(SPI): Is quad mode supported? +const mxc_gpio_cfg_t gpio_cfg_spi_quad = { MXC_GPIO0, (MXC_GPIO_PIN_5 | MXC_GPIO_PIN_6 | MXC_GPIO_PIN_7 | MXC_GPIO_PIN_8 | MXC_GPIO_PIN_9), MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; // SPI v2 Target Selects Pin Definitions -const mxc_gpio_cfg_t gpio_cfg_spi0_ts0 = { MXC_GPIO0, MXC_GPIO_PIN_4, MXC_GPIO_FUNC_ALT1, +const mxc_gpio_cfg_t gpio_cfg_spi_ts0 = { MXC_GPIO0, MXC_GPIO_PIN_3, MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_spi0_ts1 = { MXC_GPIO0, MXC_GPIO_PIN_26, MXC_GPIO_FUNC_ALT2, +const mxc_gpio_cfg_t gpio_cfg_spi_ts1 = { MXC_GPIO0, MXC_GPIO_PIN_7, MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; -const mxc_gpio_cfg_t gpio_cfg_spi0_ts2 = { MXC_GPIO0, MXC_GPIO_PIN_27, MXC_GPIO_FUNC_ALT2, +const mxc_gpio_cfg_t gpio_cfg_spi_ts2 = { MXC_GPIO0, MXC_GPIO_PIN_8, MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; \ No newline at end of file diff --git a/Libraries/PeriphDrivers/Source/UART/uart_me30.c b/Libraries/PeriphDrivers/Source/UART/uart_me30.c index 303d21c973a..4225b8b4506 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_me30.c +++ b/Libraries/PeriphDrivers/Source/UART/uart_me30.c @@ -71,7 +71,7 @@ int MXC_UART_Init(mxc_uart_regs_t *uart, unsigned int baud) return retval; } - MXC_GPIO_Config(&gpio_cfg_uart0); + MXC_GPIO_Config(&gpio_cfg_uart); MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_UART); return MXC_UART_RevA_Init((mxc_uart_reva_regs_t *)uart, baud); @@ -117,9 +117,7 @@ int MXC_UART_SetParity(mxc_uart_regs_t *uart, mxc_uart_parity_t parity) int MXC_UART_SetFlowCtrl(mxc_uart_regs_t *uart, mxc_uart_flow_t flowCtrl, int rtsThreshold) { - MXC_GPIO_Config(&gpio_cfg_uart0_flow); - - return MXC_UART_RevA_SetFlowCtrl((mxc_uart_reva_regs_t *)uart, flowCtrl, rtsThreshold); + return E_NOT_SUPPORTED; } int MXC_UART_SetClockSource(mxc_uart_regs_t *uart, int usePCLK) From 6ba97ce37ee6e4792c80b35db027723a5f18c6fb Mon Sep 17 00:00:00 2001 From: Woo Date: Wed, 8 May 2024 14:12:58 -0500 Subject: [PATCH 73/93] Switch to UART RevB, update MCR_CTRL register, fix build errors --- .../Device/Maxim/MAX32657/Include/max32657.h | 2 +- .../Maxim/MAX32657/Include/max32657.svd | 6 +- .../Device/Maxim/MAX32657/Include/mcr_regs.h | 4 +- .../PeriphDrivers/Include/MAX32657/dma.h | 4 +- .../PeriphDrivers/Include/MAX32657/uart.h | 314 ++++++++---------- .../PeriphDrivers/Source/SYS/SVD/mcr_me30.svd | 6 +- .../PeriphDrivers/Source/UART/uart_me30.c | 238 +++++++------ .../PeriphDrivers/Source/UART/uart_reva.c | 2 + .../PeriphDrivers/Source/UART/uart_revb.c | 94 +++++- .../PeriphDrivers/Source/UART/uart_revb.h | 6 +- Libraries/PeriphDrivers/max32657_files.mk | 4 +- 11 files changed, 383 insertions(+), 297 deletions(-) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h index 1e918e4d372..9af4c582050 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h @@ -740,7 +740,7 @@ We may want to handle GET_IRQ better... #define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART : 0) #define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART : 0) -#define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : 0) +#define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART_IRQn : 0) #define MXC_UART_GET_IDX(p) ((p) == MXC_UART_NS ? 0 : (p) == MXC_UART_S ? 0 : -1) /******************************************************************************/ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd index 2321cf6fd1e..9b47aea4649 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd @@ -3690,13 +3690,13 @@ ERTCO_EN - ERTCO Enable. + Enable ERTCO 4KHz. 3 1 - ERTCO_IN_EN - Enable 32K Oscillator input. + ERTCO_32KHZ_EN + Enable ERTCO 32KHz while ERTCO_EN. 5 1 diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mcr_regs.h index 1b30d94627d..e019ecbf94b 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mcr_regs.h @@ -130,8 +130,8 @@ typedef struct { #define MXC_F_MCR_CTRL_ERTCO_EN_POS 3 /**< CTRL_ERTCO_EN Position */ #define MXC_F_MCR_CTRL_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_ERTCO_EN_POS)) /**< CTRL_ERTCO_EN Mask */ -#define MXC_F_MCR_CTRL_ERTCO_IN_EN_POS 5 /**< CTRL_ERTCO_IN_EN Position */ -#define MXC_F_MCR_CTRL_ERTCO_IN_EN ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_ERTCO_IN_EN_POS)) /**< CTRL_ERTCO_IN_EN Mask */ +#define MXC_F_MCR_CTRL_ERTCO_32KHZ_EN_POS 5 /**< CTRL_ERTCO_32KHZ_EN Position */ +#define MXC_F_MCR_CTRL_ERTCO_32KHZ_EN ((uint32_t)(0x1UL << MXC_F_MCR_CTRL_ERTCO_32KHZ_EN_POS)) /**< CTRL_ERTCO_32KHZ_EN Mask */ /**@} end of group MCR_CTRL_Register */ diff --git a/Libraries/PeriphDrivers/Include/MAX32657/dma.h b/Libraries/PeriphDrivers/Include/MAX32657/dma.h index 44fd184aeb7..be679420abf 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/dma.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/dma.h @@ -59,7 +59,7 @@ typedef enum { MXC_S_DMA_CTRL_REQUEST_MEMTOMEM, ///< Memory to Memory DMA Request Selection MXC_DMA_REQUEST_SPI1RX = MXC_S_DMA_CTRL_REQUEST_SPI1RX, ///< SPI1 Receive DMA Request Selection MXC_DMA_REQUEST_SPI0RX = MXC_S_DMA_CTRL_REQUEST_SPI0RX, ///< SPI0 Receive DMA Request Selection - MXC_DMA_REQUEST_UART0RX = + MXC_DMA_REQUEST_UARTRX = MXC_S_DMA_CTRL_REQUEST_UART0RX, ///< UART0 Receive DMA Request Selection MXC_DMA_REQUEST_UART1RX = MXC_S_DMA_CTRL_REQUEST_UART1RX, ///< UART1 Receive DMA Request Selection @@ -75,7 +75,7 @@ typedef enum { MXC_DMA_REQUEST_I2SRX = MXC_S_DMA_CTRL_REQUEST_I2SRX, ///< I2S Receive DMA Request Selection MXC_DMA_REQUEST_SPI1TX = MXC_S_DMA_CTRL_REQUEST_SPI1TX, ///< SPI1 Transmit DMA Request Selection MXC_DMA_REQUEST_SPI0TX = MXC_S_DMA_CTRL_REQUEST_SPI0TX, ///< SPI0 Transmit DMA Request Selection - MXC_DMA_REQUEST_UART0TX = + MXC_DMA_REQUEST_UARTTX = MXC_S_DMA_CTRL_REQUEST_UART0TX, ///< UART0 Transmit DMA Request Selection MXC_DMA_REQUEST_UART1TX = MXC_S_DMA_CTRL_REQUEST_UART1TX, ///< UART1 Transmit DMA Request Selection diff --git a/Libraries/PeriphDrivers/Include/MAX32657/uart.h b/Libraries/PeriphDrivers/Include/MAX32657/uart.h index 523b80f8e0b..e070b9f2f63 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/uart.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/uart.h @@ -1,6 +1,6 @@ /** * @file uart.h - * @brief (UART) communications driver. + * @brief Serial Peripheral Interface (UART) communications driver. */ /****************************************************************************** @@ -24,19 +24,21 @@ ******************************************************************************/ /* Define to prevent redundant inclusion */ -#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32570_UART_H_ -#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32570_UART_H_ +#ifndef LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_UART_H_ +#define LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_UART_H_ /***** Definitions *****/ #include -#include "uart_regs.h" #include "mxc_sys.h" +#include "uart_regs.h" #include "dma_regs.h" #ifdef __cplusplus extern "C" { #endif +#define UART_EXTCLK_FREQ E_BAD_PARAM + /** * @defgroup uart UART * @ingroup periphlibs @@ -46,7 +48,7 @@ extern "C" { typedef struct _mxc_uart_req_t mxc_uart_req_t; /** * @brief The list of UART stop bit lengths supported - * + * */ typedef enum { MXC_UART_STOP_1, ///< UART Stop 1 clock cycle @@ -55,67 +57,69 @@ typedef enum { /** * @brief The list of UART Parity options supported - * + * */ typedef enum { MXC_UART_PARITY_DISABLE, ///< UART Parity Disabled - MXC_UART_PARITY_EVEN, ///< UART Parity Even - MXC_UART_PARITY_ODD, ///< UART Parity Odd - MXC_UART_PARITY_MARK, ///< UART Parity Mark - MXC_UART_PARITY_SPACE, ///< UART Parity Space MXC_UART_PARITY_EVEN_0, ///< UART Parity Even, 0 based MXC_UART_PARITY_EVEN_1, ///< UART Parity Even, 1 based MXC_UART_PARITY_ODD_0, ///< UART Parity Odd, 0 based MXC_UART_PARITY_ODD_1, ///< UART Parity Odd, 1 based - MXC_UART_PARITY_MARK_0, ///< UART Parity Mark, 0 based - MXC_UART_PARITY_MARK_1, ///< UART Parity Mark, 1 based - MXC_UART_PARITY_SPACE_0, ///< UART Parity Space, 0 based - MXC_UART_PARITY_SPACE_1, ///< UART Parity Space, 1 based } mxc_uart_parity_t; /** * @brief The list of UART flow control options supported - * + * */ typedef enum { MXC_UART_FLOW_DIS, ///< UART Flow Control Disabled - MXC_UART_FLOW_EN_LOW, ///< UART Flow Control Enabled, Active Low - MXC_UART_FLOW_EN_HIGH, ///< UART Flow Control Enabled, Active High + MXC_UART_FLOW_EN, ///< UART Flow Control Enabled } mxc_uart_flow_t; +/** + * @brief Clock settings */ +typedef enum { + /*Only available for UARTS 0-2*/ + MXC_UART_APB_CLK = 0, + /*Available for all UARTs*/ + MXC_UART_IBRO_CLK = 2, + /*ERTCO clock can only be used for UART3*/ + MXC_UART_ERTCO_CLK = 4, +} mxc_uart_clock_t; + /** * @brief The callback routine used to indicate the transaction has terminated. * - * @param req The details of the transaction. - * @param result See \ref MXC_Error_Codes for the list of error codes. + * @param req The details of the transaction. + * @param result See \ref MXC_Error_Codes for the list of error codes. */ typedef void (*mxc_uart_complete_cb_t)(mxc_uart_req_t *req, int result); /** * @brief The callback routine used to indicate the transaction has terminated. * - * @param req The details of the transaction. - * @param num The number of characters actually copied - * @param result See \ref MXC_Error_Codes for the list of error codes. + * @param req The details of the transaction. + * @param num The number of characters actually copied + * @param result See \ref MXC_Error_Codes for the list of error codes. */ typedef void (*mxc_uart_dma_complete_cb_t)(mxc_uart_req_t *req, int num, int result); /** - * @brief The information required to perform a complete UART transaction. + * @brief The information required to perform a complete UART transaction * - * This structure is used by blocking, async, and DMA based transactions. - * @note "callback" is only needed for interrupt driven (Async) and DMA transactions. + * @note This structure is used by blocking, async, and DMA based transactions. + * @note "callback" only needs to be initialized for interrupt driven (Async) and DMA transactions. */ struct _mxc_uart_req_t { mxc_uart_regs_t *uart; /// 8 bits, use two bytes per character - ///< and pad the MSB of the upper byte with zeros + const uint8_t *txData; ///< Buffer containing transmit data. For character sizes + ///< < 8 bits, pad the MSB of each byte with zeros. For + ///< character sizes > 8 bits, use two bytes per character + ///< and pad the MSB of the upper byte with zeros uint8_t *rxData; ///< Buffer to store received data For character sizes - ///< < 8 bits, pad the MSB of each byte with zeros. For - ///< character sizes > 8 bits, use two bytes per character - ///< and pad the MSB of the upper byte with zeros + ///< < 8 bits, pad the MSB of each byte with zeros. For + ///< character sizes > 8 bits, use two bytes per character + ///< and pad the MSB of the upper byte with zeros uint32_t txLen; ///< Number of bytes to be sent from txData uint32_t rxLen; ///< Number of bytes to be stored in rxData volatile uint32_t txCnt; ///< Number of bytes actually transmitted from txData @@ -132,25 +136,29 @@ struct _mxc_uart_req_t { /** * @brief Initialize and enable UART peripheral. - * + * * This function initializes everything necessary to call a UART transaction function. * Some parameters are set to defaults as follows: * UART Data Size - 8 bits * UART Stop Bits - 1 bit * UART Parity - None * UART Flow Control - None - * UART Clock - 7.37MHz Clock (for baud > 7372800, PCLK is used) - * + * * These parameters can be modified after initialization using low level functions + * + * @note On default this function enables UART peripheral clock. + * if you wish to manage clock and gpio related things in upper level instead of here. + * Define MSDK_NO_GPIO_CLK_INIT flag in project.mk file. + * By this flag this function will remove clock and gpio related codes from file. + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param baud The requested clock frequency. The actual clock frequency + * will be returned by the function if successful. + * @param clock Clock source * - * @param uart Pointer to UART registers (selects the UART block used.) - * @param baud The requested clock frequency. The actual clock frequency - * will be returned by the function if successful. - * - * @return If successful, the actual clock frequency is returned. Otherwise, see - * \ref MXC_Error_Codes for a list of return codes. + * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_Init(mxc_uart_regs_t *uart, unsigned int baud); +int MXC_UART_Init(mxc_uart_regs_t *uart, unsigned int baud, mxc_uart_clock_t clock); /** * @brief Disable and shutdown UART peripheral. @@ -178,15 +186,14 @@ int MXC_UART_ReadyForSleep(mxc_uart_regs_t *uart); /** * @brief Set the frequency of the UART interface. * - * - * - * @param uart Pointer to UART registers (selects the UART block used.) - * @param baud The desired baud rate + * @param uart Pointer to UART registers (selects the UART block used.) + * @param baud The desired baud rate + * @param clock Clock source * * @return Negative if error, otherwise actual speed set. See \ref * MXC_Error_Codes for the list of error return codes. */ -int MXC_UART_SetFrequency(mxc_uart_regs_t *uart, unsigned int baud); +int MXC_UART_SetFrequency(mxc_uart_regs_t *uart, unsigned int baud, mxc_uart_clock_t clock); /** * @brief Get the frequency of the UART interface. @@ -201,9 +208,9 @@ int MXC_UART_GetFrequency(mxc_uart_regs_t *uart); /** * @brief Sets the number of bits per character - * - * @param uart Pointer to UART registers (selects the UART block used.) - * @param dataSize The number of bits per character (5-8 bits/character are valid) + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param dataSize The number of bits per character (5-8 bits/character are valid) * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ @@ -211,9 +218,9 @@ int MXC_UART_SetDataSize(mxc_uart_regs_t *uart, int dataSize); /** * @brief Sets the number of stop bits sent at the end of a character - * - * @param uart Pointer to UART registers (selects the UART block used.) - * @param stopBits The number of stop bits used + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param stopBits The number of stop bits used * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ @@ -221,9 +228,9 @@ int MXC_UART_SetStopBits(mxc_uart_regs_t *uart, mxc_uart_stop_t stopBits); /** * @brief Sets the type of parity generation used - * - * @param uart Pointer to UART registers (selects the UART block used.) - * @param parity see \ref mxc_uart_parity_t UART Parity Types for details + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param parity see \ref UART Parity Types for details * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ @@ -231,10 +238,10 @@ int MXC_UART_SetParity(mxc_uart_regs_t *uart, mxc_uart_parity_t parity); /** * @brief Sets the flow control used - * - * @param uart Pointer to UART registers (selects the UART block used.) - * @param flowCtrl see \ref mxc_uart_flow_t UART Flow Control Types for details - * @param rtsThreshold Number of bytes remaining in the RX FIFO when RTS is asserted + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param flowCtrl see \ref UART Flow Control Types for details + * @param rtsThreshold Number of bytes remaining in the RX FIFO when RTS is asserted * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ @@ -242,47 +249,24 @@ int MXC_UART_SetFlowCtrl(mxc_uart_regs_t *uart, mxc_uart_flow_t flowCtrl, int rt /** * @brief Sets the clock source for the baud rate generator + * + * @param uart Pointer to UART registers (selects the UART block used.) + * @param clock Clock source * - * @param uart Pointer to UART registers (selects the UART block used.) - * @param usePCLK Non-zero values will use the PCLK as the bit clock instead - * of the default 7.37MHz clock source. The baud rate generator - * will automatically be reconfigured to the closest possible - * baud rate. - * - * @return Actual baud rate if successful, otherwise see \ref MXC_Error_Codes + * @return Actual baud rate if successful, otherwise see \ref MXC_Error_Codes * for a list of return codes. */ -int MXC_UART_SetClockSource(mxc_uart_regs_t *uart, int usePCLK); - -/** - * @brief Enables or Disables the built-in null modem - * - * @param uart Pointer to UART registers (selects the UART block used.) - * @param nullModem Non-zero values will enable the null modem function, - * which swaps TXD/RXD and also swaps RTS/CTS, if used. - * - * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. - */ -int MXC_UART_SetNullModem(mxc_uart_regs_t *uart, int nullModem); +int MXC_UART_SetClockSource(mxc_uart_regs_t *uart, mxc_uart_clock_t clock); /* ************************************************************************* */ /* Low-level functions */ /* ************************************************************************* */ -/** - * @brief Transmits a Break Frame (all bits 0) - * - * @param uart Pointer to UART registers (selects the UART block used.) - * - * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. - */ -int MXC_UART_SendBreak(mxc_uart_regs_t *uart); - /** * @brief Checks the UART Peripheral for an ongoing transmission * * @note This function is applicable in Master mode only - * + * * @param uart Pointer to UART registers (selects the UART block used.) * * @return Active/Inactive, see \ref MXC_Error_Codes for a list of return codes. @@ -299,46 +283,44 @@ int MXC_UART_GetActive(mxc_uart_regs_t *uart); int MXC_UART_AbortTransmission(mxc_uart_regs_t *uart); /** - * @brief Reads the next available character. This function will block until a character - * is available or a UART error occurs. + * @brief Reads the next available character. If no character is available, this function + * will return an error. * * @param uart Pointer to UART registers (selects the UART block used.) * * @return The character read, otherwise see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_ReadCharacter(mxc_uart_regs_t *uart); +int MXC_UART_ReadCharacterRaw(mxc_uart_regs_t *uart); /** - * @brief Writes a character on the UART. This function will block until the character - * has been placed in the TX FIFO or a UART error occurs. + * @brief Writes a character on the UART. If the character cannot be written because the + * transmit FIFO is currently full, this function returns an error. * * @param uart Pointer to UART registers (selects the UART block used.) * @param character The character to write * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_WriteCharacter(mxc_uart_regs_t *uart, uint8_t character); +int MXC_UART_WriteCharacterRaw(mxc_uart_regs_t *uart, uint8_t character); /** - * @brief Reads the next available character. If no character is available, this function - * will return an error. + * @brief Reads the next available character * * @param uart Pointer to UART registers (selects the UART block used.) * * @return The character read, otherwise see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_ReadCharacterRaw(mxc_uart_regs_t *uart); +int MXC_UART_ReadCharacter(mxc_uart_regs_t *uart); /** - * @brief Writes a character on the UART. If the character cannot be written because the - * transmit FIFO is currently full, this function returns an error. + * @brief Writes a character on the UART * * @param uart Pointer to UART registers (selects the UART block used.) - * @param character The character to write + * @param character The character to write * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_WriteCharacterRaw(mxc_uart_regs_t *uart, uint8_t character); +int MXC_UART_WriteCharacter(mxc_uart_regs_t *uart, uint8_t character); /** * @brief Reads the next available character @@ -347,7 +329,7 @@ int MXC_UART_WriteCharacterRaw(mxc_uart_regs_t *uart, uint8_t character); * * @param uart Pointer to UART registers (selects the UART block used.) * @param buffer Buffer to store data in - * @param len Number of characters + * @param len Number of characters * * @return The character read, otherwise see \ref MXC_Error_Codes for a list of return codes. */ @@ -357,19 +339,19 @@ int MXC_UART_Read(mxc_uart_regs_t *uart, uint8_t *buffer, int *len); * @brief Writes a byte on the UART * * @param uart Pointer to UART registers (selects the UART block used.) - * @param byte The buffer of characters to write + * @param byte The buffer of characters to write * @param len The number of characters to write * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ -int MXC_UART_Write(mxc_uart_regs_t *uart, uint8_t *byte, int *len); +int MXC_UART_Write(mxc_uart_regs_t *uart, const uint8_t *byte, int *len); /** * @brief Unloads bytes from the receive FIFO. * * @param uart Pointer to UART registers (selects the UART block used.) - * @param bytes The buffer to read the data into. - * @param len The number of bytes to read. + * @param bytes The buffer to read the data into. + * @param len The number of bytes to read. * * @return The number of bytes actually read. */ @@ -378,13 +360,13 @@ unsigned int MXC_UART_ReadRXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, un /** * @brief Unloads bytes from the receive FIFO user DMA for longer reads. * - * @param uart Pointer to UART registers (selects the UART block used). - * @param dma Pointer to DMA registers (selects the DMA block used for UART DMA). - * @param bytes The buffer to read the data into. - * @param len The number of bytes to read. - * @param callback The function to call when the read is complete + * @param uart Pointer to UART registers (selects the UART block used). + * @param dma Pointer to DMA registers to use for UART DMA. + * @param bytes The buffer to read the data into. + * @param len The number of bytes to read. + * @param callback The function to call when the read is complete * - * @return See \ref MXC_Error_Codes for a list of return values + * @return See \ref MXC_ERROR_CODES for a list of return values */ int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, mxc_dma_regs_t *dma, unsigned char *bytes, unsigned int len, mxc_uart_dma_complete_cb_t callback); @@ -402,25 +384,26 @@ unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart); * @brief Loads bytes into the transmit FIFO. * * @param uart Pointer to UART registers (selects the UART block used.) - * @param bytes The buffer containing the bytes to write - * @param len The number of bytes to write. + * @param bytes The buffer containing the bytes to write + * @param len The number of bytes to write. * * @return The number of bytes actually written. */ -unsigned int MXC_UART_WriteTXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len); +unsigned int MXC_UART_WriteTXFIFO(mxc_uart_regs_t *uart, const unsigned char *bytes, + unsigned int len); /** * @brief Loads bytes into the transmit FIFO using DMA for longer writes * - * @param uart Pointer to UART registers (selects the UART block used). - * @param dma Pointer to DMA registers (selects the DMA block used for UART DMA). - * @param bytes The buffer containing the bytes to write - * @param len The number of bytes to write. - * @param callback The function to call when the write is complete + * @param uart Pointer to UART registers (selects the UART block used). + * @param dma Pointer to DMA registers to use for UART DMA. + * @param bytes The buffer containing the bytes to write + * @param len The number of bytes to write. + * @param callback The function to call when the write is complete * - * @return See \ref MXC_Error_Codes for a list of return values + * @return See \ref MXC_ERROR_CODES for a list of return values */ -int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, mxc_dma_regs_t *dma, unsigned char *bytes, unsigned int len, +int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, mxc_dma_regs_t *dma, const unsigned char *bytes, unsigned int len, mxc_uart_dma_complete_cb_t callback); /** @@ -452,18 +435,18 @@ int MXC_UART_ClearTXFIFO(mxc_uart_regs_t *uart); /** * @brief Set the receive threshold level. - * + * * @note RX FIFO Receive threshold. Smaller values will cause * interrupts to occur more often, but reduce the possibility * of losing data because of a FIFO overflow. Larger values - * will reduce the time required by the ISR, but increase the + * will reduce the time required by the ISR, but increase the * possibility of data loss. Passing an invalid value will - * cause the driver to use the value already set in the + * cause the driver to use the value already set in the * appropriate register. * * @param uart Pointer to UART registers (selects the UART block used.) - * @param numBytes The threshold level to set. This value must be - * between 0 and 8 inclusive. + * @param numBytes The threshold level to set. This value must be + * between 0 and 8 inclusive. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ @@ -471,27 +454,27 @@ int MXC_UART_SetRXThreshold(mxc_uart_regs_t *uart, unsigned int numBytes); /** * @brief Get the current receive threshold level. - * + * * @param uart Pointer to UART registers (selects the UART block used.) - * + * * @return The receive threshold value (in bytes). */ unsigned int MXC_UART_GetRXThreshold(mxc_uart_regs_t *uart); /** * @brief Set the transmit threshold level. - * + * * @note TX FIFO threshold. Smaller values will cause interrupts * to occur more often, but reduce the possibility of terminating * a transaction early in master mode, or transmitting invalid data * in slave mode. Larger values will reduce the time required by - * the ISR, but increase the possibility errors occurring. Passing - * an invalid value will cause the driver to use the value already + * the ISR, but increase the possibility errors occurring. Passing + * an invalid value will cause the driver to use the value already * set in the appropriate register. * * @param uart Pointer to UART registers (selects the UART block used.) - * @param numBytes The threshold level to set. This value must be - * between 0 and 8 inclusive. + * @param numBytes The threshold level to set. This value must be + * between 0 and 8 inclusive. * * @return Success/Fail, see \ref MXC_Error_Codes for a list of return codes. */ @@ -499,9 +482,9 @@ int MXC_UART_SetTXThreshold(mxc_uart_regs_t *uart, unsigned int numBytes); /** * @brief Get the current transmit threshold level. - * + * * @param uart Pointer to UART registers (selects the UART block used.) - * + * * @return The transmit threshold value (in bytes). */ unsigned int MXC_UART_GetTXThreshold(mxc_uart_regs_t *uart); @@ -509,24 +492,24 @@ unsigned int MXC_UART_GetTXThreshold(mxc_uart_regs_t *uart); /** * @brief Gets the interrupt flags that are currently set * - * @note These functions should not be used while using non-blocking Transaction Level + * @note These functions should not be used while using non-blocking Transaction Level * functions (Async or DMA) * * @param uart Pointer to UART registers (selects the UART block used.) - * - * @return The interrupt flags + * + * @return The interrupt flags */ unsigned int MXC_UART_GetFlags(mxc_uart_regs_t *uart); /** * @brief Clears the interrupt flags that are currently set * - * @note These functions should not be used while using non-blocking Transaction Level + * @note These functions should not be used while using non-blocking Transaction Level * functions (Async or DMA) * * @param uart Pointer to UART registers (selects the UART block used.) * @param flags mask of flags to clear - * + * * @return See \ref MXC_Error_Codes for the list of error return codes. */ int MXC_UART_ClearFlags(mxc_uart_regs_t *uart, unsigned int flags); @@ -534,7 +517,7 @@ int MXC_UART_ClearFlags(mxc_uart_regs_t *uart, unsigned int flags); /** * @brief Enables specific interrupts * - * @note These functions should not be used while using non-blocking Transaction Level + * @note These functions should not be used while using non-blocking Transaction Level * functions (Async or DMA) * * @param uart Pointer to UART registers (selects the UART block used.) @@ -547,7 +530,7 @@ int MXC_UART_EnableInt(mxc_uart_regs_t *uart, unsigned int mask); /** * @brief Disables specific interrupts * - * @note These functions should not be used while using non-blocking Transaction Level + * @note These functions should not be used while using non-blocking Transaction Level * functions (Async or DMA) * * @param uart Pointer to UART registers (selects the UART block used.) @@ -561,7 +544,7 @@ int MXC_UART_DisableInt(mxc_uart_regs_t *uart, unsigned int mask); * @brief Gets the status flags that are currently set * * @param uart Pointer to UART registers (selects the UART block used.) - * + * * @return The status flags */ unsigned int MXC_UART_GetStatus(mxc_uart_regs_t *uart); @@ -571,13 +554,13 @@ unsigned int MXC_UART_GetStatus(mxc_uart_regs_t *uart); /* ************************************************************************* */ /** - * @brief Performs a blocking UART transaction. - * + * @brief Performs a blocking UART transaction. + * * @note Performs a blocking UART transaction as follows. * If tx_len is non-zero, transmit TX data * Once tx_len has been sent, if rx_len is non-zero, receive data * - * @param req Pointer to details of the transaction + * @param req Pointer to details of the transaction * * @return See \ref MXC_Error_Codes for the list of error return codes. */ @@ -585,11 +568,11 @@ int MXC_UART_Transaction(mxc_uart_req_t *req); /** * @brief Setup an interrupt-driven UART transaction - * + * * @note The TX FIFO will be filled with txData if necessary * Relevant interrupts will be enabled * - * @param req Pointer to details of the transaction + * @param req Pointer to details of the transaction * * @return See \ref MXC_Error_Codes for the list of error return codes. */ @@ -597,15 +580,15 @@ int MXC_UART_TransactionAsync(mxc_uart_req_t *req); /** * @brief Setup a DMA driven UART transaction - * + * * @note The TX FIFO will be filled with txData if necessary - * Relevant interrupts will be enabled. - * The DMA channel indicated by the request will be set up to load/unload the FIFOs - * with as few interrupt-based events as possible. The channel will be reset and + * Relevant interrupts will be enabled + * The DMA channel indicated by the request will be set up to load/unload the FIFOs + * with as few interrupt-based events as possible. The channel will be reset and * returned to the system at the end of the transaction. * - * @param req Pointer to details of the transaction - * @param dma Pointer to DMA registers used for UART DMA + * @param req Pointer to details of the transaction + * @param dma Pointer to DMA registers to use for UART DMA * * @return See \ref MXC_Error_Codes for the list of error return codes. */ @@ -623,27 +606,23 @@ int MXC_UART_TransactionDMA(mxc_uart_req_t *req, mxc_dma_regs_t *dma); void MXC_UART_DMACallback(int ch, int error); /** - * @brief Async callback + * @brief Async callback * - * @param uart The uart - * @param[in] retVal The ret value + * @param uart The uart + * @param retVal The ret value * * @return See \ref MXC_Error_Codes for the list of error return codes. */ int MXC_UART_AsyncCallback(mxc_uart_regs_t *uart, int retVal); -int MXC_UART_TxAsyncCallback(mxc_uart_regs_t *uart, int retVal); -int MXC_UART_RxAsyncCallback(mxc_uart_regs_t *uart, int retVal); /** * @brief stop any async callbacks * - * @param uart The uart + * @param uart The uart * * @return See \ref MXC_Error_Codes for the list of error return codes. */ int MXC_UART_AsyncStop(mxc_uart_regs_t *uart); -int MXC_UART_TxAsyncStop(mxc_uart_regs_t *uart); -int MXC_UART_RxAsyncStop(mxc_uart_regs_t *uart); /** * @brief Abort any asynchronous requests in progress. @@ -657,8 +636,6 @@ int MXC_UART_RxAsyncStop(mxc_uart_regs_t *uart); * @return See \ref MXC_Error_Codes for the list of error return codes. */ int MXC_UART_AbortAsync(mxc_uart_regs_t *uart); -int MXC_UART_TxAbortAsync(mxc_uart_regs_t *uart); -int MXC_UART_RxAbortAsync(mxc_uart_regs_t *uart); /** * @brief The processing function for asynchronous transactions. @@ -671,8 +648,8 @@ int MXC_UART_RxAbortAsync(mxc_uart_regs_t *uart); * * @return See \ref MXC_Error_Codes for the list of error return codes. */ - int MXC_UART_AsyncHandler(mxc_uart_regs_t *uart); + /** * @brief Provide TXCount for asynchronous transactions.. * @@ -680,7 +657,6 @@ int MXC_UART_AsyncHandler(mxc_uart_regs_t *uart); * * @return Returns transmit bytes (in FIFO). */ - uint32_t MXC_UART_GetAsyncTXCount(mxc_uart_req_t *req); /** @@ -761,4 +737,4 @@ int MXC_UART_GetRXDMAChannel(mxc_uart_regs_t *uart); } #endif -#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32570_UART_H_ +#endif // LIBRARIES_PERIPHDRIVERS_INCLUDE_MAX32657_UART_H_ diff --git a/Libraries/PeriphDrivers/Source/SYS/SVD/mcr_me30.svd b/Libraries/PeriphDrivers/Source/SYS/SVD/mcr_me30.svd index 24efc05e758..7930cd67e3e 100644 --- a/Libraries/PeriphDrivers/Source/SYS/SVD/mcr_me30.svd +++ b/Libraries/PeriphDrivers/Source/SYS/SVD/mcr_me30.svd @@ -49,13 +49,13 @@ ERTCO_EN - ERTCO Enable. + Enable ERTCO 4KHz. 3 1 - ERTCO_IN_EN - Enable 32K Oscillator input. + ERTCO_32KHZ_EN + Enable ERTCO 32KHz while ERTCO_EN. 5 1 diff --git a/Libraries/PeriphDrivers/Source/UART/uart_me30.c b/Libraries/PeriphDrivers/Source/UART/uart_me30.c index 4225b8b4506..7e9655ef80e 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_me30.c +++ b/Libraries/PeriphDrivers/Source/UART/uart_me30.c @@ -22,47 +22,29 @@ #include "mxc_device.h" #include "mxc_pins.h" #include "mxc_assert.h" -#include "uart_reva.h" +#include "uart_revb.h" #include "uart_common.h" #include "dma.h" +#include "dma_regs.h" void MXC_UART_DMACallback(int ch, int error) { - MXC_UART_RevA_DMACallback(ch, error); + MXC_UART_RevB_DMACallback(ch, error); } int MXC_UART_AsyncCallback(mxc_uart_regs_t *uart, int retVal) { - return MXC_UART_RevA_AsyncCallback((mxc_uart_reva_regs_t *)uart, retVal); -} - -int MXC_UART_TxAsyncCallback(mxc_uart_regs_t *uart, int retVal) -{ - return MXC_UART_RevA_TxAsyncCallback((mxc_uart_reva_regs_t *)uart, retVal); -} - -int MXC_UART_RxAsyncCallback(mxc_uart_regs_t *uart, int retVal) -{ - return MXC_UART_RevA_RxAsyncCallback((mxc_uart_reva_regs_t *)uart, retVal); + return MXC_UART_RevB_AsyncCallback((mxc_uart_revb_regs_t *)uart, retVal); } int MXC_UART_AsyncStop(mxc_uart_regs_t *uart) { - return MXC_UART_RevA_AsyncStop((mxc_uart_reva_regs_t *)uart); -} - -int MXC_UART_TxAsyncStop(mxc_uart_regs_t *uart) -{ - return MXC_UART_RevA_TxAsyncStop((mxc_uart_reva_regs_t *)uart); + return MXC_UART_RevB_AsyncStop((mxc_uart_revb_regs_t *)uart); } -int MXC_UART_RxAsyncStop(mxc_uart_regs_t *uart) -{ - return MXC_UART_RevA_RxAsyncStop((mxc_uart_reva_regs_t *)uart); -} - -int MXC_UART_Init(mxc_uart_regs_t *uart, unsigned int baud) +int MXC_UART_Init(mxc_uart_regs_t *uart, unsigned int baud, mxc_uart_clock_t clock) { +#ifndef MSDK_NO_GPIO_CLK_INIT int retval; retval = MXC_UART_Shutdown(uart); @@ -71,48 +53,98 @@ int MXC_UART_Init(mxc_uart_regs_t *uart, unsigned int baud) return retval; } - MXC_GPIO_Config(&gpio_cfg_uart); - MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_UART); + switch (clock) { + case MXC_UART_ERTCO_CLK: + MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_ERTCO); + break; + + case MXC_UART_IBRO_CLK: + MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_IBRO); + break; + + default: + break; + } + + switch (MXC_UART_GET_IDX(uart)) { + case 0: + MXC_GPIO_Config(&gpio_cfg_uart); + MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_UART); + break; + + default: + return E_BAD_PARAM; + } +#endif // MSDK_NO_GPIO_CLK_INIT - return MXC_UART_RevA_Init((mxc_uart_reva_regs_t *)uart, baud); + return MXC_UART_RevB_Init((mxc_uart_revb_regs_t *)uart, baud, clock); } int MXC_UART_Shutdown(mxc_uart_regs_t *uart) { - MXC_SYS_Reset_Periph(MXC_SYS_RESET0_UART); - MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_UART); + switch (MXC_UART_GET_IDX(uart)) { + case 0: + MXC_SYS_Reset_Periph(MXC_SYS_RESET0_UART); + MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_UART); + break; + + default: + return E_BAD_PARAM; + } return E_NO_ERROR; } int MXC_UART_ReadyForSleep(mxc_uart_regs_t *uart) { - return MXC_UART_RevA_ReadyForSleep((mxc_uart_reva_regs_t *)uart); + return MXC_UART_RevB_ReadyForSleep((mxc_uart_revb_regs_t *)uart); } -int MXC_UART_SetFrequency(mxc_uart_regs_t *uart, unsigned int baud) +int MXC_UART_SetFrequency(mxc_uart_regs_t *uart, unsigned int baud, mxc_uart_clock_t clock) { - return MXC_UART_RevA_SetFrequency((mxc_uart_reva_regs_t *)uart, baud); + int freq; + + if (MXC_UART_GET_IDX(uart) < 0) { + return E_BAD_PARAM; + } + + if (clock == MXC_UART_ERTCO_CLK) { + return E_BAD_PARAM; + } + + freq = MXC_UART_RevB_SetFrequency((mxc_uart_revb_regs_t *)uart, baud, clock); + + if (freq > 0) { + // Enable baud clock and wait for it to become ready. + uart->ctrl |= MXC_F_UART_CTRL_CLK_EN; + while (((uart->ctrl & MXC_F_UART_CTRL_CLK_RDY) >> MXC_F_UART_CTRL_CLK_RDY_POS) == 0) {} + } + + return freq; } int MXC_UART_GetFrequency(mxc_uart_regs_t *uart) { - return MXC_UART_RevA_GetFrequency((mxc_uart_reva_regs_t *)uart); + if (MXC_UART_GET_IDX(uart) < 0) { + return E_BAD_PARAM; + } + + return MXC_UART_RevB_GetFrequency((mxc_uart_revb_regs_t *)uart); } int MXC_UART_SetDataSize(mxc_uart_regs_t *uart, int dataSize) { - return MXC_UART_RevA_SetDataSize((mxc_uart_reva_regs_t *)uart, dataSize); + return MXC_UART_RevB_SetDataSize((mxc_uart_revb_regs_t *)uart, dataSize); } int MXC_UART_SetStopBits(mxc_uart_regs_t *uart, mxc_uart_stop_t stopBits) { - return MXC_UART_RevA_SetStopBits((mxc_uart_reva_regs_t *)uart, stopBits); + return MXC_UART_RevB_SetStopBits((mxc_uart_revb_regs_t *)uart, stopBits); } int MXC_UART_SetParity(mxc_uart_regs_t *uart, mxc_uart_parity_t parity) { - return MXC_UART_RevA_SetParity((mxc_uart_reva_regs_t *)uart, parity); + return MXC_UART_RevB_SetParity((mxc_uart_revb_regs_t *)uart, parity); } int MXC_UART_SetFlowCtrl(mxc_uart_regs_t *uart, mxc_uart_flow_t flowCtrl, int rtsThreshold) @@ -120,39 +152,29 @@ int MXC_UART_SetFlowCtrl(mxc_uart_regs_t *uart, mxc_uart_flow_t flowCtrl, int rt return E_NOT_SUPPORTED; } -int MXC_UART_SetClockSource(mxc_uart_regs_t *uart, int usePCLK) -{ - return MXC_UART_RevA_SetClockSource((mxc_uart_reva_regs_t *)uart, usePCLK); -} - -int MXC_UART_SetNullModem(mxc_uart_regs_t *uart, int nullModem) -{ - return MXC_UART_RevA_SetNullModem((mxc_uart_reva_regs_t *)uart, nullModem); -} - -int MXC_UART_SendBreak(mxc_uart_regs_t *uart) +int MXC_UART_SetClockSource(mxc_uart_regs_t *uart, mxc_uart_clock_t clock) { - return MXC_UART_RevA_SendBreak((mxc_uart_reva_regs_t *)uart); + return MXC_UART_RevB_SetClockSource((mxc_uart_revb_regs_t *)uart, clock); } int MXC_UART_GetActive(mxc_uart_regs_t *uart) { - return MXC_UART_RevA_GetActive((mxc_uart_reva_regs_t *)uart); + return MXC_UART_RevB_GetActive((mxc_uart_revb_regs_t *)uart); } int MXC_UART_AbortTransmission(mxc_uart_regs_t *uart) { - return MXC_UART_RevA_AbortTransmission((mxc_uart_reva_regs_t *)uart); + return MXC_UART_RevB_AbortTransmission((mxc_uart_revb_regs_t *)uart); } int MXC_UART_ReadCharacterRaw(mxc_uart_regs_t *uart) { - return MXC_UART_RevA_ReadCharacterRaw((mxc_uart_reva_regs_t *)uart); + return MXC_UART_RevB_ReadCharacterRaw((mxc_uart_revb_regs_t *)uart); } int MXC_UART_WriteCharacterRaw(mxc_uart_regs_t *uart, uint8_t character) { - return MXC_UART_RevA_WriteCharacterRaw((mxc_uart_reva_regs_t *)uart, character); + return MXC_UART_RevB_WriteCharacterRaw((mxc_uart_revb_regs_t *)uart, character); } int MXC_UART_ReadCharacter(mxc_uart_regs_t *uart) @@ -167,142 +189,152 @@ int MXC_UART_WriteCharacter(mxc_uart_regs_t *uart, uint8_t character) int MXC_UART_Read(mxc_uart_regs_t *uart, uint8_t *buffer, int *len) { - return MXC_UART_RevA_Read((mxc_uart_reva_regs_t *)uart, buffer, len); + return MXC_UART_RevB_Read((mxc_uart_revb_regs_t *)uart, buffer, len); } -int MXC_UART_Write(mxc_uart_regs_t *uart, uint8_t *byte, int *len) +int MXC_UART_Write(mxc_uart_regs_t *uart, const uint8_t *byte, int *len) { - return MXC_UART_RevA_Write((mxc_uart_reva_regs_t *)uart, byte, len); + return MXC_UART_RevB_Write((mxc_uart_revb_regs_t *)uart, byte, len); } unsigned int MXC_UART_ReadRXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len) { - return MXC_UART_RevA_ReadRXFIFO((mxc_uart_reva_regs_t *)uart, bytes, len); + return MXC_UART_RevB_ReadRXFIFO((mxc_uart_revb_regs_t *)uart, bytes, len); } int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, mxc_dma_regs_t *dma, unsigned char *bytes, unsigned int len, mxc_uart_dma_complete_cb_t callback) { mxc_dma_config_t config; - config.reqsel = MXC_DMA_REQUEST_UART0RX; // TODO(ME30): Updated DMA reqsel - return MXC_UART_RevA_ReadRXFIFODMA((mxc_uart_reva_regs_t *)uart, dma, bytes, len, callback, - config); + int uart_num = MXC_UART_GET_IDX(uart); + + switch (uart_num) { + case 0: + config.reqsel = MXC_DMA_REQUEST_UARTRX; + break; + + default: + return E_BAD_PARAM; + break; + } + + return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, dma, bytes, len, callback, config); } unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart) { - return MXC_UART_RevA_GetRXFIFOAvailable((mxc_uart_reva_regs_t *)uart); + return MXC_UART_RevB_GetRXFIFOAvailable((mxc_uart_revb_regs_t *)uart); } -unsigned int MXC_UART_WriteTXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned int len) +unsigned int MXC_UART_WriteTXFIFO(mxc_uart_regs_t *uart, const unsigned char *bytes, + unsigned int len) { - return MXC_UART_RevA_WriteTXFIFO((mxc_uart_reva_regs_t *)uart, bytes, len); + return MXC_UART_RevB_WriteTXFIFO((mxc_uart_revb_regs_t *)uart, bytes, len); } -int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, mxc_dma_regs_t *dma, unsigned char *bytes, unsigned int len, +int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, mxc_dma_regs_t *dma, const unsigned char *bytes, unsigned int len, mxc_uart_dma_complete_cb_t callback) { mxc_dma_config_t config; - config.reqsel = MXC_DMA_REQUEST_UART0TX; // TODO(ME30): Updated DMA reqsel - return MXC_UART_RevA_WriteTXFIFODMA((mxc_uart_reva_regs_t *)uart, dma, bytes, len, callback, - config); + int uart_num = MXC_UART_GET_IDX(uart); + switch (uart_num) { + case 0: + config.reqsel = MXC_DMA_REQUEST_UARTTX; + break; + + default: + return E_BAD_PARAM; + break; + } + + return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, dma, bytes, len, callback, config); } unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart) { - return MXC_UART_RevA_GetTXFIFOAvailable((mxc_uart_reva_regs_t *)uart); + return MXC_UART_RevB_GetTXFIFOAvailable((mxc_uart_revb_regs_t *)uart); } int MXC_UART_ClearRXFIFO(mxc_uart_regs_t *uart) { - return MXC_UART_RevA_ClearRXFIFO((mxc_uart_reva_regs_t *)uart); + return MXC_UART_RevB_ClearRXFIFO((mxc_uart_revb_regs_t *)uart); } int MXC_UART_ClearTXFIFO(mxc_uart_regs_t *uart) { - return MXC_UART_RevA_ClearTXFIFO((mxc_uart_reva_regs_t *)uart); + return MXC_UART_RevB_ClearTXFIFO((mxc_uart_revb_regs_t *)uart); } int MXC_UART_SetRXThreshold(mxc_uart_regs_t *uart, unsigned int numBytes) { - return MXC_UART_RevA_SetRXThreshold((mxc_uart_reva_regs_t *)uart, numBytes); + return MXC_UART_RevB_SetRXThreshold((mxc_uart_revb_regs_t *)uart, numBytes); } unsigned int MXC_UART_GetRXThreshold(mxc_uart_regs_t *uart) { - return MXC_UART_RevA_GetRXThreshold((mxc_uart_reva_regs_t *)uart); + return MXC_UART_RevB_GetRXThreshold((mxc_uart_revb_regs_t *)uart); } int MXC_UART_SetTXThreshold(mxc_uart_regs_t *uart, unsigned int numBytes) { - return MXC_UART_RevA_SetTXThreshold((mxc_uart_reva_regs_t *)uart, numBytes); + return E_NOT_SUPPORTED; } unsigned int MXC_UART_GetTXThreshold(mxc_uart_regs_t *uart) { - return MXC_UART_RevA_GetTXThreshold((mxc_uart_reva_regs_t *)uart); + return E_NOT_SUPPORTED; } unsigned int MXC_UART_GetFlags(mxc_uart_regs_t *uart) { - return MXC_UART_RevA_GetFlags((mxc_uart_reva_regs_t *)uart); + return MXC_UART_RevB_GetFlags((mxc_uart_revb_regs_t *)uart); } int MXC_UART_ClearFlags(mxc_uart_regs_t *uart, unsigned int flags) { - return MXC_UART_RevA_ClearFlags((mxc_uart_reva_regs_t *)uart, flags); + return MXC_UART_RevB_ClearFlags((mxc_uart_revb_regs_t *)uart, flags); } -int MXC_UART_EnableInt(mxc_uart_regs_t *uart, unsigned int mask) +int MXC_UART_EnableInt(mxc_uart_regs_t *uart, unsigned int intEn) { - return MXC_UART_RevA_EnableInt((mxc_uart_reva_regs_t *)uart, mask); + return MXC_UART_RevB_EnableInt((mxc_uart_revb_regs_t *)uart, intEn); } -int MXC_UART_DisableInt(mxc_uart_regs_t *uart, unsigned int mask) +int MXC_UART_DisableInt(mxc_uart_regs_t *uart, unsigned int intDis) { - return MXC_UART_RevA_DisableInt((mxc_uart_reva_regs_t *)uart, mask); + return MXC_UART_RevB_DisableInt((mxc_uart_revb_regs_t *)uart, intDis); } unsigned int MXC_UART_GetStatus(mxc_uart_regs_t *uart) { - return MXC_UART_RevA_GetStatus((mxc_uart_reva_regs_t *)uart); + return MXC_UART_RevB_GetStatus((mxc_uart_revb_regs_t *)uart); } int MXC_UART_Transaction(mxc_uart_req_t *req) { - return MXC_UART_RevA_Transaction((mxc_uart_reva_req_t *)req); + return MXC_UART_RevB_Transaction((mxc_uart_revb_req_t *)req); } int MXC_UART_TransactionAsync(mxc_uart_req_t *req) { - return MXC_UART_RevA_TransactionAsync((mxc_uart_reva_req_t *)req); + return MXC_UART_RevB_TransactionAsync((mxc_uart_revb_req_t *)req); } int MXC_UART_TransactionDMA(mxc_uart_req_t *req, mxc_dma_regs_t *dma) { - return MXC_UART_RevA_TransactionDMA((mxc_uart_reva_req_t *)req, dma); + return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req, dma); } int MXC_UART_AbortAsync(mxc_uart_regs_t *uart) { - return MXC_UART_RevA_AbortAsync((mxc_uart_reva_regs_t *)uart); -} - -int MXC_UART_TxAbortAsync(mxc_uart_regs_t *uart) -{ - return MXC_UART_RevA_TxAbortAsync((mxc_uart_reva_regs_t *)uart); -} - -int MXC_UART_RxAbortAsync(mxc_uart_regs_t *uart) -{ - return MXC_UART_RevA_RxAbortAsync((mxc_uart_reva_regs_t *)uart); + return MXC_UART_RevB_AbortAsync((mxc_uart_revb_regs_t *)uart); } int MXC_UART_AsyncHandler(mxc_uart_regs_t *uart) { - return MXC_UART_RevA_AsyncHandler((mxc_uart_reva_regs_t *)uart); + return MXC_UART_RevB_AsyncHandler((mxc_uart_revb_regs_t *)uart); } uint32_t MXC_UART_GetAsyncTXCount(mxc_uart_req_t *req) @@ -317,21 +349,25 @@ uint32_t MXC_UART_GetAsyncRXCount(mxc_uart_req_t *req) int MXC_UART_SetAutoDMAHandlers(mxc_uart_regs_t *uart, bool enable) { - return MXC_UART_RevA_SetAutoDMAHandlers((mxc_uart_reva_regs_t *)uart, enable); + return MXC_UART_RevB_SetAutoDMAHandlers((mxc_uart_revb_regs_t *)uart, enable); } + int MXC_UART_SetTXDMAChannel(mxc_uart_regs_t *uart, unsigned int channel) { - return MXC_UART_RevA_SetTXDMAChannel((mxc_uart_reva_regs_t *)uart, channel); + return MXC_UART_RevB_SetTXDMAChannel((mxc_uart_revb_regs_t *)uart, channel); } + int MXC_UART_GetTXDMAChannel(mxc_uart_regs_t *uart) { - return MXC_UART_RevA_GetTXDMAChannel((mxc_uart_reva_regs_t *)uart); + return MXC_UART_RevB_GetTXDMAChannel((mxc_uart_revb_regs_t *)uart); } + int MXC_UART_SetRXDMAChannel(mxc_uart_regs_t *uart, unsigned int channel) { - return MXC_UART_RevA_SetRXDMAChannel((mxc_uart_reva_regs_t *)uart, channel); + return MXC_UART_RevB_SetRXDMAChannel((mxc_uart_revb_regs_t *)uart, channel); } + int MXC_UART_GetRXDMAChannel(mxc_uart_regs_t *uart) { - return MXC_UART_RevA_GetRXDMAChannel((mxc_uart_reva_regs_t *)uart); + return MXC_UART_RevB_GetTXDMAChannel((mxc_uart_revb_regs_t *)uart); } diff --git a/Libraries/PeriphDrivers/Source/UART/uart_reva.c b/Libraries/PeriphDrivers/Source/UART/uart_reva.c index 5ba07b5c3e4..66517e7b427 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_reva.c +++ b/Libraries/PeriphDrivers/Source/UART/uart_reva.c @@ -28,6 +28,8 @@ #include "nvic_table.h" #endif +// TODO(DMA): Fix multiple DMA instance handling. + /* **** Definitions **** */ #define MXC_UART_REVA_ERRINT_EN \ (MXC_F_UART_REVA_INT_EN_RX_FRAME_ERROR | MXC_F_UART_REVA_INT_EN_RX_PARITY_ERROR | \ diff --git a/Libraries/PeriphDrivers/Source/UART/uart_revb.c b/Libraries/PeriphDrivers/Source/UART/uart_revb.c index da82f678825..87b81fd714e 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_revb.c +++ b/Libraries/PeriphDrivers/Source/UART/uart_revb.c @@ -29,6 +29,8 @@ #include "nvic_table.h" #endif +// TOD(DMA): Fix multiple instance handling. + /* **** Definitions **** */ #define MXC_UART_REVB_ERRINT_EN \ (MXC_F_UART_REVB_INT_EN_RX_FERR | MXC_F_UART_REVB_INT_EN_RX_PAR | MXC_F_UART_REVB_INT_EN_RX_OV) @@ -46,6 +48,7 @@ typedef struct { int channelTx; int channelRx; bool auto_dma_handlers; + mxc_dma_regs_t *dma; } uart_revb_req_state_t; uart_revb_req_state_t states[MXC_UART_INSTANCES]; @@ -93,6 +96,7 @@ int MXC_UART_RevB_Init(mxc_uart_revb_regs_t *uart, unsigned int baud, mxc_uart_r states[i].tx_req = NULL; states[i].rx_req = NULL; states[i].auto_dma_handlers = false; + states[i].dma = NULL; return E_NO_ERROR; } @@ -824,17 +828,58 @@ int MXC_UART_RevB_SetAutoDMAHandlers(mxc_uart_revb_regs_t *uart, bool enable) return E_NO_ERROR; } -void MXC_UART_RevB_DMA_SetupAutoHandlers(unsigned int channel) + +// TODO(DMA): Replaced the DMA instance number check to the only +// parts affected by this. Our DMA drivers probably +// needs a rework to handle multiple instances because +// the ME14's DMA drivers are very limited with +// the DMA instance selection. +#if (TARGET_NUM == 32657) + +void MXC_UART_RevA_DMA0_Handler(void) +{ + MXC_DMA_Handler(MXC_DMA0); +} + +void MXC_UART_RevA_DMA1_Handler(void) +{ + MXC_DMA_Handler(MXC_DMA1); +} + +#endif + +/* "Auto" handlers just need to call MXC_DMA_Handler with the correct +DMA instance. +*/ +void MXC_UART_RevB_DMA_SetupAutoHandlers(mxc_dma_regs_t *dma_instance, unsigned int channel) { #ifdef __arm__ - NVIC_EnableIRQ(MXC_DMA_CH_GET_IRQ(channel)); +#if (TARGET_NUM == 32657) + NVIC_EnableIRQ(MXC_DMA_CH_GET_IRQ(dma_instance, channel)); + + /* (JC): This is not the cleanest or most scalable way to do this, + but I tried defining default handler's in the system file. + Some complications make this the most attractive short-term + option. We could handle multiple DMA instances better in the DMA API (See the mismatch between the size of "dma_resource" array and the number of channels per instance, to start)*/ + if (dma_instance == MXC_DMA0) { + MXC_NVIC_SetVector(MXC_DMA_CH_GET_IRQ(dma_instance, channel), MXC_UART_RevA_DMA0_Handler); + } else if (dma_instance == MXC_DMA1) { + MXC_NVIC_SetVector(MXC_DMA_CH_GET_IRQ(dma_instance, channel), MXC_UART_RevA_DMA1_Handler); + } +#else + NVIC_EnableIRQ(MXC_DMA_CH_GET_IRQ(channel)); + + // Only one DMA instance, we can point direct to MXC_DMA_Handler MXC_NVIC_SetVector(MXC_DMA_CH_GET_IRQ(channel), MXC_DMA_Handler); +#endif // MXC_DMA_INSTANCES > 1 + #else // TODO(JC): RISC-V #endif // __arm__ } + int MXC_UART_RevB_SetTXDMAChannel(mxc_uart_revb_regs_t *uart, unsigned int channel) { int n = MXC_UART_GET_IDX((mxc_uart_regs_t *)uart); @@ -867,7 +912,7 @@ int MXC_UART_RevB_GetRXDMAChannel(mxc_uart_revb_regs_t *uart) return states[n].channelRx; } -int MXC_UART_RevB_ReadRXFIFODMA(mxc_uart_revb_regs_t *uart, unsigned char *bytes, unsigned int len, +int MXC_UART_RevB_ReadRXFIFODMA(mxc_uart_revb_regs_t *uart, mxc_dma_regs_t *dma, unsigned char *bytes, unsigned int len, mxc_uart_dma_complete_cb_t callback, mxc_dma_config_t config) { uint8_t channel; @@ -881,9 +926,13 @@ int MXC_UART_RevB_ReadRXFIFODMA(mxc_uart_revb_regs_t *uart, unsigned char *bytes if (states[uart_num].auto_dma_handlers && states[uart_num].channelRx < 0) { /* Acquire channel if we don't have one already */ +#if (TARGET_NUM == 32657) + channel = MXC_DMA_AcquireChannel(dma); +#else channel = MXC_DMA_AcquireChannel(); +#endif MXC_UART_RevB_SetRXDMAChannel(uart, channel); - MXC_UART_RevB_DMA_SetupAutoHandlers(channel); + MXC_UART_RevB_DMA_SetupAutoHandlers(dma, channel); } else { if (states[uart_num].channelRx < 0) return E_BAD_STATE; @@ -905,7 +954,13 @@ int MXC_UART_RevB_ReadRXFIFODMA(mxc_uart_revb_regs_t *uart, unsigned char *bytes states[uart_num].channelRx = channel; MXC_DMA_ConfigChannel(config, srcdst); MXC_DMA_SetCallback(channel, MXC_UART_DMACallback); + +#if (TARGET_NUM == 32657) + MXC_DMA_EnableInt(dma, channel); +#else MXC_DMA_EnableInt(channel); +#endif + MXC_DMA_Start(channel); //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; MXC_DMA_SetChannelInterruptEn(channel, 0, 1); @@ -914,7 +969,7 @@ int MXC_UART_RevB_ReadRXFIFODMA(mxc_uart_revb_regs_t *uart, unsigned char *bytes return E_NO_ERROR; } -int MXC_UART_RevB_WriteTXFIFODMA(mxc_uart_revb_regs_t *uart, const unsigned char *bytes, +int MXC_UART_RevB_WriteTXFIFODMA(mxc_uart_revb_regs_t *uart, mxc_dma_regs_t *dma, const unsigned char *bytes, unsigned int len, mxc_uart_dma_complete_cb_t callback, mxc_dma_config_t config) { @@ -929,9 +984,13 @@ int MXC_UART_RevB_WriteTXFIFODMA(mxc_uart_revb_regs_t *uart, const unsigned char if (states[uart_num].auto_dma_handlers && states[uart_num].channelTx < 0) { /* Acquire channel if we don't have one already */ +#if (TARGET_NUM == 32657) + channel = MXC_DMA_AcquireChannel(dma); +#else channel = MXC_DMA_AcquireChannel(); +#endif MXC_UART_RevB_SetTXDMAChannel(uart, channel); - MXC_UART_RevB_DMA_SetupAutoHandlers(channel); + MXC_UART_RevB_DMA_SetupAutoHandlers(dma, channel); } else { if (states[uart_num].channelTx < 0) return E_BAD_STATE; @@ -953,7 +1012,13 @@ int MXC_UART_RevB_WriteTXFIFODMA(mxc_uart_revb_regs_t *uart, const unsigned char states[uart_num].channelTx = channel; MXC_DMA_ConfigChannel(config, srcdst); MXC_DMA_SetCallback(channel, MXC_UART_DMACallback); + +#if (TARGET_NUM == 32657) + MXC_DMA_EnableInt(dma, channel); +#else MXC_DMA_EnableInt(channel); +#endif + MXC_DMA_Start(channel); //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; MXC_DMA_SetChannelInterruptEn(channel, 0, 1); @@ -962,10 +1027,13 @@ int MXC_UART_RevB_WriteTXFIFODMA(mxc_uart_revb_regs_t *uart, const unsigned char return E_NO_ERROR; } -int MXC_UART_RevB_TransactionDMA(mxc_uart_revb_req_t *req) +int MXC_UART_RevB_TransactionDMA(mxc_uart_revb_req_t *req, mxc_dma_regs_t *dma) { int uart_num = MXC_UART_GET_IDX((mxc_uart_regs_t *)(req->uart)); + // Save DMA instance for DMA Callback. + states[uart_num].dma = dma; + if (req->txLen) { if (req->txData == NULL) { return E_BAD_PARAM; @@ -990,7 +1058,11 @@ int MXC_UART_RevB_TransactionDMA(mxc_uart_revb_req_t *req) (req->uart)->dma |= (1 << MXC_F_UART_REVB_DMA_RX_THD_VAL_POS); (req->uart)->dma |= (2 << MXC_F_UART_REVB_DMA_TX_THD_VAL_POS); +#if (TARGET_NUM == 32657) + MXC_DMA_Init(dma); +#else MXC_DMA_Init(); +#endif // Reset rx/tx counters, req->rxCnt = 0; @@ -1000,7 +1072,7 @@ int MXC_UART_RevB_TransactionDMA(mxc_uart_revb_req_t *req) if ((req->txData != NULL) && (req->txLen)) { /* Save TX req, the DMA handler will use this later. */ states[uart_num].tx_req = req; - if (MXC_UART_WriteTXFIFODMA((mxc_uart_regs_t *)(req->uart), req->txData, req->txLen, + if (MXC_UART_WriteTXFIFODMA((mxc_uart_regs_t *)(req->uart), dma, req->txData, req->txLen, NULL) != E_NO_ERROR) { return E_BAD_PARAM; } @@ -1009,7 +1081,7 @@ int MXC_UART_RevB_TransactionDMA(mxc_uart_revb_req_t *req) //rx if ((req->rxData != NULL) && (req->rxLen)) { states[uart_num].rx_req = req; - if (MXC_UART_ReadRXFIFODMA((mxc_uart_regs_t *)(req->uart), req->rxData, req->rxLen, NULL) != + if (MXC_UART_ReadRXFIFODMA((mxc_uart_regs_t *)(req->uart), dma, req->rxData, req->rxLen, NULL) != E_NO_ERROR) { return E_BAD_PARAM; } @@ -1026,7 +1098,7 @@ void MXC_UART_RevB_DMACallback(int ch, int error) if (states[i].channelTx == ch) { /* Populate txLen. The number of "remainder" bytes is what's left on the DMA channel's count register. */ - states[i].tx_req->txCnt = states[i].tx_req->txLen - MXC_DMA->ch[ch].cnt; + states[i].tx_req->txCnt = states[i].tx_req->txLen - states[i].dma->ch[ch].cnt; temp_req = states[i].tx_req; @@ -1048,7 +1120,7 @@ void MXC_UART_RevB_DMACallback(int ch, int error) break; } else if (states[i].channelRx == ch) { /* Same as above, but for RX */ - states[i].rx_req->rxCnt = states[i].rx_req->rxLen - MXC_DMA->ch[ch].cnt; + states[i].rx_req->rxCnt = states[i].rx_req->rxLen - states[i].dma->ch[ch].cnt; temp_req = states[i].rx_req; if (states[i].auto_dma_handlers) { MXC_DMA_ReleaseChannel(ch); diff --git a/Libraries/PeriphDrivers/Source/UART/uart_revb.h b/Libraries/PeriphDrivers/Source/UART/uart_revb.h index 5bf47655a28..cd9f74e2082 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_revb.h +++ b/Libraries/PeriphDrivers/Source/UART/uart_revb.h @@ -74,12 +74,12 @@ int MXC_UART_RevB_Read(mxc_uart_revb_regs_t *uart, uint8_t *buffer, int *len); int MXC_UART_RevB_Write(mxc_uart_revb_regs_t *uart, const uint8_t *byte, int *len); unsigned int MXC_UART_RevB_ReadRXFIFO(mxc_uart_revb_regs_t *uart, unsigned char *bytes, unsigned int len); -int MXC_UART_RevB_ReadRXFIFODMA(mxc_uart_revb_regs_t *uart, unsigned char *bytes, unsigned int len, +int MXC_UART_RevB_ReadRXFIFODMA(mxc_uart_revb_regs_t *uart, mxc_dma_regs_t *dma, unsigned char *bytes, unsigned int len, mxc_uart_dma_complete_cb_t callback, mxc_dma_config_t config); unsigned int MXC_UART_RevB_GetRXFIFOAvailable(mxc_uart_revb_regs_t *uart); unsigned int MXC_UART_RevB_WriteTXFIFO(mxc_uart_revb_regs_t *uart, const unsigned char *bytes, unsigned int len); -int MXC_UART_RevB_WriteTXFIFODMA(mxc_uart_revb_regs_t *uart, const unsigned char *bytes, +int MXC_UART_RevB_WriteTXFIFODMA(mxc_uart_revb_regs_t *uart, mxc_dma_regs_t *dma, const unsigned char *bytes, unsigned int len, mxc_uart_dma_complete_cb_t callback, mxc_dma_config_t config); unsigned int MXC_UART_RevB_GetTXFIFOAvailable(mxc_uart_revb_regs_t *uart); @@ -97,7 +97,7 @@ unsigned int MXC_UART_RevB_GetStatus(mxc_uart_revb_regs_t *uart); int MXC_UART_RevB_Busy(mxc_uart_revb_regs_t *uart); int MXC_UART_RevB_Transaction(mxc_uart_revb_req_t *req); int MXC_UART_RevB_TransactionAsync(mxc_uart_revb_req_t *req); -int MXC_UART_RevB_TransactionDMA(mxc_uart_revb_req_t *req); +int MXC_UART_RevB_TransactionDMA(mxc_uart_revb_req_t *req, mxc_dma_regs_t *dma); int MXC_UART_RevB_AbortAsync(mxc_uart_revb_regs_t *uart); int MXC_UART_RevB_AsyncHandler(mxc_uart_revb_regs_t *uart); int MXC_UART_RevB_AsyncStop(mxc_uart_revb_regs_t *uart); diff --git a/Libraries/PeriphDrivers/max32657_files.mk b/Libraries/PeriphDrivers/max32657_files.mk index c8ed1baecaf..966c08ebd26 100644 --- a/Libraries/PeriphDrivers/max32657_files.mk +++ b/Libraries/PeriphDrivers/max32657_files.mk @@ -103,12 +103,12 @@ PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/TRNG/trng_revb.c PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/UART PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/UART/uart_common.c PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/UART/uart_me30.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/UART/uart_reva.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/UART/uart_revb.c PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/WDT PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_common.c PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_me30.c -PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_reva.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WDT/wdt_revb.c PERIPH_DRIVER_INCLUDE_DIR += $(SOURCE_DIR)/WUT PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/WUT/wut_me30.c From cb2a43cccc2bbfd8fb03fd466209dfa869d43f1f Mon Sep 17 00:00:00 2001 From: Woo Date: Wed, 8 May 2024 16:02:17 -0500 Subject: [PATCH 74/93] Update SYS registers to latest doc --- .../Device/Maxim/MAX32657/Include/gcr_regs.h | 17 ++----- .../Maxim/MAX32657/Include/max32657.svd | 46 +++++-------------- .../Maxim/MAX32657/Include/pwrseq_regs.h | 7 ++- .../PeriphDrivers/Source/LP/pwrseq_me30.svd | 8 +++- .../PeriphDrivers/Source/SYS/SVD/gcr_me30.svd | 38 ++------------- 5 files changed, 32 insertions(+), 84 deletions(-) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h index 9eece4d2c39..03ee86280f3 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h @@ -260,7 +260,7 @@ typedef struct { #define MXC_F_GCR_CLKCTRL_ERTCO_EN_POS 17 /**< CLKCTRL_ERTCO_EN Position */ #define MXC_F_GCR_CLKCTRL_ERTCO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_ERTCO_EN_POS)) /**< CLKCTRL_ERTCO_EN Mask */ -#define MXC_F_GCR_CLKCTRL_IPO_EN_POS 19 /**< CLKCTRL_IPO_EN Position */ +#define MXC_F_GCR_CLKCTRL_IPO_EN_POS 18 /**< CLKCTRL_IPO_EN Position */ #define MXC_F_GCR_CLKCTRL_IPO_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCTRL_IPO_EN_POS)) /**< CLKCTRL_IPO_EN Mask */ #define MXC_F_GCR_CLKCTRL_IBRO_EN_POS 20 /**< CLKCTRL_IBRO_EN Position */ @@ -321,19 +321,8 @@ typedef struct { * @brief Peripheral Clock Divider. * @{ */ -#define MXC_F_GCR_PCLKDIV_ADCFRQ_POS 10 /**< PCLKDIV_ADCFRQ Position */ -#define MXC_F_GCR_PCLKDIV_ADCFRQ ((uint32_t)(0xFUL << MXC_F_GCR_PCLKDIV_ADCFRQ_POS)) /**< PCLKDIV_ADCFRQ Mask */ - -#define MXC_F_GCR_PCLKDIV_AONCLKDIV_POS 14 /**< PCLKDIV_AONCLKDIV Position */ -#define MXC_F_GCR_PCLKDIV_AONCLKDIV ((uint32_t)(0x3UL << MXC_F_GCR_PCLKDIV_AONCLKDIV_POS)) /**< PCLKDIV_AONCLKDIV Mask */ -#define MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV4 ((uint32_t)0x0UL) /**< PCLKDIV_AONCLKDIV_DIV4 Value */ -#define MXC_S_GCR_PCLKDIV_AONCLKDIV_DIV4 (MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV4 << MXC_F_GCR_PCLKDIV_AONCLKDIV_POS) /**< PCLKDIV_AONCLKDIV_DIV4 Setting */ -#define MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV8 ((uint32_t)0x1UL) /**< PCLKDIV_AONCLKDIV_DIV8 Value */ -#define MXC_S_GCR_PCLKDIV_AONCLKDIV_DIV8 (MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV8 << MXC_F_GCR_PCLKDIV_AONCLKDIV_POS) /**< PCLKDIV_AONCLKDIV_DIV8 Setting */ -#define MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV16 ((uint32_t)0x2UL) /**< PCLKDIV_AONCLKDIV_DIV16 Value */ -#define MXC_S_GCR_PCLKDIV_AONCLKDIV_DIV16 (MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV16 << MXC_F_GCR_PCLKDIV_AONCLKDIV_POS) /**< PCLKDIV_AONCLKDIV_DIV16 Setting */ -#define MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV32 ((uint32_t)0x3UL) /**< PCLKDIV_AONCLKDIV_DIV32 Value */ -#define MXC_S_GCR_PCLKDIV_AONCLKDIV_DIV32 (MXC_V_GCR_PCLKDIV_AONCLKDIV_DIV32 << MXC_F_GCR_PCLKDIV_AONCLKDIV_POS) /**< PCLKDIV_AONCLKDIV_DIV32 Setting */ +#define MXC_F_GCR_PCLKDIV_CLKDIV_POS 0 /**< PCLKDIV_CLKDIV Position */ +#define MXC_F_GCR_PCLKDIV_CLKDIV ((uint32_t)(0xFFFFFFFFUL << MXC_F_GCR_PCLKDIV_CLKDIV_POS)) /**< PCLKDIV_CLKDIV Mask */ /**@} end of group GCR_PCLKDIV_Register */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd index 9b47aea4649..8dab57da06e 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd @@ -2039,7 +2039,7 @@ IPO_EN 50MHz High Frequency Internal Reference Clock Enable. - 19 + 18 1 @@ -2171,38 +2171,10 @@ 0x18 - ADCFRQ - ADC clock Frequency. These bits define the ADC clock frequency. FADC = FPCLK / (ADCFRQ). - 10 - 4 - - - AONCLKDIV - Always-ON (AON) domain Clock Divider. These bits define the AON domain clock divider. - 14 - 2 - - - DIV4 - PCLK divide by 4. - 0 - - - DIV8 - PCLK divide by 8. - 1 - - - DIV16 - PCLK divide by 16. - 2 - - - DIV32 - PCLK divide by 32. - 3 - - + CLKDIV + Clock Divide Value. + 0 + 32 @@ -3795,7 +3767,7 @@ 0x00 - RAMRET_EN + SRAMRET_EN System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 0 5 @@ -3901,6 +3873,12 @@ Low Power Peripheral Wakeup Status Register. 0x30 + + BACKUP + BACKUP Wakeful Flag. + 16 + 1 + RESET Reset Detected Wakeup Flag. diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/pwrseq_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/pwrseq_regs.h index d09bcc8d6f9..2998417c6f6 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/pwrseq_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/pwrseq_regs.h @@ -107,8 +107,8 @@ typedef struct { * @brief Low Power Control Register. * @{ */ -#define MXC_F_PWRSEQ_LPCTRL_RAMRET_EN_POS 0 /**< LPCTRL_RAMRET_EN Position */ -#define MXC_F_PWRSEQ_LPCTRL_RAMRET_EN ((uint32_t)(0x1FUL << MXC_F_PWRSEQ_LPCTRL_RAMRET_EN_POS)) /**< LPCTRL_RAMRET_EN Mask */ +#define MXC_F_PWRSEQ_LPCTRL_SRAMRET_EN_POS 0 /**< LPCTRL_SRAMRET_EN Position */ +#define MXC_F_PWRSEQ_LPCTRL_SRAMRET_EN ((uint32_t)(0x1FUL << MXC_F_PWRSEQ_LPCTRL_SRAMRET_EN_POS)) /**< LPCTRL_SRAMRET_EN Mask */ #define MXC_F_PWRSEQ_LPCTRL_FAST_POS 8 /**< LPCTRL_FAST Position */ #define MXC_F_PWRSEQ_LPCTRL_FAST ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPCTRL_FAST_POS)) /**< LPCTRL_FAST Mask */ @@ -175,6 +175,9 @@ typedef struct { * @brief Low Power Peripheral Wakeup Status Register. * @{ */ +#define MXC_F_PWRSEQ_LPPWST_BACKUP_POS 16 /**< LPPWST_BACKUP Position */ +#define MXC_F_PWRSEQ_LPPWST_BACKUP ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_BACKUP_POS)) /**< LPPWST_BACKUP Mask */ + #define MXC_F_PWRSEQ_LPPWST_RESET_POS 17 /**< LPPWST_RESET Position */ #define MXC_F_PWRSEQ_LPPWST_RESET ((uint32_t)(0x1UL << MXC_F_PWRSEQ_LPPWST_RESET_POS)) /**< LPPWST_RESET Mask */ diff --git a/Libraries/PeriphDrivers/Source/LP/pwrseq_me30.svd b/Libraries/PeriphDrivers/Source/LP/pwrseq_me30.svd index 3ace90f01b1..79fc6aad0fe 100644 --- a/Libraries/PeriphDrivers/Source/LP/pwrseq_me30.svd +++ b/Libraries/PeriphDrivers/Source/LP/pwrseq_me30.svd @@ -16,7 +16,7 @@ 0x00 - RAMRET_EN + SRAMRET_EN System RAM retention in BACKUP mode. These two bits are used in conjuction with RREGEN bit. 0 5 @@ -122,6 +122,12 @@ Low Power Peripheral Wakeup Status Register. 0x30 + + BACKUP + BACKUP Wakeful Flag. + 16 + 1 + RESET Reset Detected Wakeup Flag. diff --git a/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me30.svd b/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me30.svd index 09cbee89064..93e95ad3089 100644 --- a/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me30.svd +++ b/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me30.svd @@ -337,7 +337,7 @@ IPO_EN 50MHz High Frequency Internal Reference Clock Enable. - 19 + 18 1 @@ -469,38 +469,10 @@ 0x18 - ADCFRQ - ADC clock Frequency. These bits define the ADC clock frequency. FADC = FPCLK / (ADCFRQ). - 10 - 4 - - - AONCLKDIV - Always-ON (AON) domain Clock Divider. These bits define the AON domain clock divider. - 14 - 2 - - - DIV4 - PCLK divide by 4. - 0 - - - DIV8 - PCLK divide by 8. - 1 - - - DIV16 - PCLK divide by 16. - 2 - - - DIV32 - PCLK divide by 32. - 3 - - + CLKDIV + Clock Divide Value. + 0 + 32 From 71c10a5c0be006224d8c9880d3bd230192cd9384 Mon Sep 17 00:00:00 2001 From: Woo Date: Thu, 9 May 2024 11:23:32 -0500 Subject: [PATCH 75/93] Add nvic_table.c to build --- Libraries/PeriphDrivers/max32657_files.mk | 1 + 1 file changed, 1 insertion(+) diff --git a/Libraries/PeriphDrivers/max32657_files.mk b/Libraries/PeriphDrivers/max32657_files.mk index 966c08ebd26..9fb3de25b0d 100644 --- a/Libraries/PeriphDrivers/max32657_files.mk +++ b/Libraries/PeriphDrivers/max32657_files.mk @@ -50,6 +50,7 @@ PERIPH_DRIVER_INCLUDE_DIR += $(INCLUDE_DIR)/$(TARGET_UC)/ PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_assert.c PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_delay.c PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/mxc_lock.c +PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/nvic_table.c PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/sys_me30.c PERIPH_DRIVER_C_FILES += $(SOURCE_DIR)/SYS/pins_me30.c From 2221b7adf7d6c502b6df1ec2bb5b74f511c3c763 Mon Sep 17 00:00:00 2001 From: Sadik Ozer Date: Fri, 10 May 2024 17:16:04 +0300 Subject: [PATCH 76/93] Fix build issue on zephyr side - Exclude lp driver on zephyr side, also remove some unneeded functions - MAX32657 uart register match with MAX32662 uart registers Signed-off-by: Sadik Ozer --- Libraries/PeriphDrivers/Include/MAX32657/lp.h | 10 ------- Libraries/PeriphDrivers/Source/LP/lp_me30.c | 30 ------------------- .../zephyr/MAX/Include/wrap_max32_uart.h | 2 +- .../zephyr/MAX/Source/MAX32657/CMakeLists.txt | 2 +- 4 files changed, 2 insertions(+), 42 deletions(-) diff --git a/Libraries/PeriphDrivers/Include/MAX32657/lp.h b/Libraries/PeriphDrivers/Include/MAX32657/lp.h index bd9c7b0b9e8..e4c53fce38b 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/lp.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/lp.h @@ -181,16 +181,6 @@ void MXC_LP_EnableWUTAlarmWakeup(void); */ void MXC_LP_DisableWUTAlarmWakeup(void); -/** - * @brief Enables the LPCMP to wake up the device from any low power mode. - */ -void MXC_LP_EnableLPCMPWakeup(mxc_lpcmp_cmpsel_t cmp); - -/** - * @brief Disables the LPCMP from waking up the device. - */ -void MXC_LP_DisableLPCMPWakeup(mxc_lpcmp_cmpsel_t cmp); - /** * @brief Enables the HA0 to wake up the device from any low power mode. */ diff --git a/Libraries/PeriphDrivers/Source/LP/lp_me30.c b/Libraries/PeriphDrivers/Source/LP/lp_me30.c index a041107d1ca..b24173982eb 100644 --- a/Libraries/PeriphDrivers/Source/LP/lp_me30.c +++ b/Libraries/PeriphDrivers/Source/LP/lp_me30.c @@ -21,18 +21,10 @@ #include "gcr_regs.h" #include "mcr_regs.h" #include "lp.h" -#include "lpcmp.h" -#ifndef __riscv /* ARM */ #define SET_SLEEPDEEP(X) (SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk) #define CLR_SLEEPDEEP(X) (SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk) -#else -/* RISCV */ -/* These bits do not exist for RISCV core */ -#define SET_SLEEPDEEP(X) -#define CLR_SLEEPDEEP(X) -#endif void MXC_LP_EnterSleepMode(void) { @@ -221,28 +213,6 @@ void MXC_LP_DisableWUTAlarmWakeup(void) MXC_GCR->pm &= ~MXC_F_GCR_PM_WUT_WE; } -void MXC_LP_EnableLPCMPWakeup(mxc_lpcmp_cmpsel_t cmp) -{ - MXC_ASSERT((cmp >= MXC_LPCMP_CMP0) && (cmp <= MXC_LPCMP_CMP3)); - - if (cmp == MXC_LPCMP_CMP0) { - MXC_PWRSEQ->lppwen |= MXC_F_PWRSEQ_LPPWEN_AINCOMP0; - } else { - MXC_PWRSEQ->lppwen |= MXC_F_PWRSEQ_LPPWEN_LPCMP; - } -} - -void MXC_LP_DisableLPCMPWakeup(mxc_lpcmp_cmpsel_t cmp) -{ - MXC_ASSERT((cmp >= MXC_LPCMP_CMP0) && (cmp <= MXC_LPCMP_CMP3)); - - if (cmp == MXC_LPCMP_CMP0) { - MXC_PWRSEQ->lppwen &= ~MXC_F_PWRSEQ_LPPWEN_AINCOMP0; - } else { - MXC_PWRSEQ->lppwen &= ~MXC_F_PWRSEQ_LPPWEN_LPCMP; - } -} - int MXC_LP_ConfigDeepSleepClocks(uint32_t mask) { if (!(mask & (MXC_F_GCR_PM_IBRO_PD | MXC_F_GCR_PM_IPO_PD))) { diff --git a/Libraries/zephyr/MAX/Include/wrap_max32_uart.h b/Libraries/zephyr/MAX/Include/wrap_max32_uart.h index a7d1d9f0b95..9479e29dc57 100644 --- a/Libraries/zephyr/MAX/Include/wrap_max32_uart.h +++ b/Libraries/zephyr/MAX/Include/wrap_max32_uart.h @@ -124,7 +124,7 @@ static inline void Wrap_MXC_UART_DisableRxDMA(mxc_uart_regs_t *uart) #define ADI_MAX32_UART_RX_EMPTY MXC_F_UART_STATUS_RX_EM #define ADI_MAX32_UART_TX_EMPTY MXC_F_UART_STATUS_TX_EM -#if defined(CONFIG_SOC_MAX32662) +#if defined(CONFIG_SOC_MAX32662) || (CONFIG_SOC_MAX32657) // error flags #define ADI_MAX32_UART_ERROR_OVERRUN MXC_F_UART_INTFL_RX_OV #define ADI_MAX32_UART_ERROR_PARITY MXC_F_UART_INTFL_RX_PAR diff --git a/Libraries/zephyr/MAX/Source/MAX32657/CMakeLists.txt b/Libraries/zephyr/MAX/Source/MAX32657/CMakeLists.txt index b60488ac19a..26a4f27478a 100644 --- a/Libraries/zephyr/MAX/Source/MAX32657/CMakeLists.txt +++ b/Libraries/zephyr/MAX/Source/MAX32657/CMakeLists.txt @@ -55,7 +55,7 @@ zephyr_library_sources( ${MSDK_PERIPH_SRC_DIR}/ICC/icc_me30.c ${MSDK_PERIPH_SRC_DIR}/ICC/icc_reva.c - ${MSDK_PERIPH_SRC_DIR}/LP/lp_me30.c + #${MSDK_PERIPH_SRC_DIR}/LP/lp_me30.c ${MSDK_PERIPH_SRC_DIR}/WUT/wut_me30.c ${MSDK_PERIPH_SRC_DIR}/WUT/wut_reva.c From ef9bfcd4d5e2a8e5168e47fc9fe9854fd9990b1b Mon Sep 17 00:00:00 2001 From: Woo Date: Fri, 10 May 2024 16:14:11 -0500 Subject: [PATCH 77/93] Fix DMA multiple instance handling build errors --- .../Boards/MAX32657/EvKit_V1/Source/board.c | 2 +- .../Device/Maxim/MAX32657/Include/dma_regs.h | 54 +++------- .../Maxim/MAX32657/Include/max32657.svd | 99 +++---------------- .../PeriphDrivers/Include/MAX32657/dma.h | 34 ++----- Libraries/PeriphDrivers/Source/AES/aes_ai87.c | 2 +- Libraries/PeriphDrivers/Source/AES/aes_me12.c | 2 +- Libraries/PeriphDrivers/Source/AES/aes_me15.c | 2 +- Libraries/PeriphDrivers/Source/AES/aes_me17.c | 2 +- Libraries/PeriphDrivers/Source/AES/aes_me21.c | 2 +- .../Source/DMA/dma_reva_me30.svd | 99 +++---------------- Libraries/PeriphDrivers/Source/SPI/spi_me30.c | 24 +---- .../PeriphDrivers/Source/UART/uart_ai85.c | 6 +- .../PeriphDrivers/Source/UART/uart_ai87.c | 6 +- .../PeriphDrivers/Source/UART/uart_me12.c | 6 +- .../PeriphDrivers/Source/UART/uart_me15.c | 6 +- .../PeriphDrivers/Source/UART/uart_me16.c | 6 +- .../PeriphDrivers/Source/UART/uart_me17.c | 6 +- .../PeriphDrivers/Source/UART/uart_me18.c | 6 +- .../PeriphDrivers/Source/UART/uart_me21.c | 6 +- .../PeriphDrivers/Source/UART/uart_me55.c | 6 +- .../PeriphDrivers/Source/UART/uart_reva.c | 34 ++----- .../PeriphDrivers/Source/UART/uart_revb.c | 29 +++--- 22 files changed, 106 insertions(+), 333 deletions(-) diff --git a/Libraries/Boards/MAX32657/EvKit_V1/Source/board.c b/Libraries/Boards/MAX32657/EvKit_V1/Source/board.c index f0bdcddf5e0..4d02252ff00 100644 --- a/Libraries/Boards/MAX32657/EvKit_V1/Source/board.c +++ b/Libraries/Boards/MAX32657/EvKit_V1/Source/board.c @@ -92,7 +92,7 @@ int Console_Init(void) { int err; - if ((err = MXC_UART_Init(ConsoleUart, CONSOLE_BAUD)) != E_NO_ERROR) { + if ((err = MXC_UART_Init(ConsoleUart, CONSOLE_BAUD, MXC_UART_APB_CLK)) != E_NO_ERROR) { return err; } diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/dma_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/dma_regs.h index 822e7ff9cf8..0d77fc7711d 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/dma_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/dma_regs.h @@ -176,54 +176,24 @@ typedef struct { #define MXC_F_DMA_CTRL_REQUEST ((uint32_t)(0x3FUL << MXC_F_DMA_CTRL_REQUEST_POS)) /**< CTRL_REQUEST Mask */ #define MXC_V_DMA_CTRL_REQUEST_MEMTOMEM ((uint32_t)0x0UL) /**< CTRL_REQUEST_MEMTOMEM Value */ #define MXC_S_DMA_CTRL_REQUEST_MEMTOMEM (MXC_V_DMA_CTRL_REQUEST_MEMTOMEM << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_MEMTOMEM Setting */ -#define MXC_V_DMA_CTRL_REQUEST_SPI1RX ((uint32_t)0x1UL) /**< CTRL_REQUEST_SPI1RX Value */ -#define MXC_S_DMA_CTRL_REQUEST_SPI1RX (MXC_V_DMA_CTRL_REQUEST_SPI1RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI1RX Setting */ -#define MXC_V_DMA_CTRL_REQUEST_UART0RX ((uint32_t)0x4UL) /**< CTRL_REQUEST_UART0RX Value */ -#define MXC_S_DMA_CTRL_REQUEST_UART0RX (MXC_V_DMA_CTRL_REQUEST_UART0RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART0RX Setting */ -#define MXC_V_DMA_CTRL_REQUEST_UART1RX ((uint32_t)0x5UL) /**< CTRL_REQUEST_UART1RX Value */ -#define MXC_S_DMA_CTRL_REQUEST_UART1RX (MXC_V_DMA_CTRL_REQUEST_UART1RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART1RX Setting */ -#define MXC_V_DMA_CTRL_REQUEST_I2C0RX ((uint32_t)0x7UL) /**< CTRL_REQUEST_I2C0RX Value */ -#define MXC_S_DMA_CTRL_REQUEST_I2C0RX (MXC_V_DMA_CTRL_REQUEST_I2C0RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C0RX Setting */ -#define MXC_V_DMA_CTRL_REQUEST_I2C1RX ((uint32_t)0x8UL) /**< CTRL_REQUEST_I2C1RX Value */ -#define MXC_S_DMA_CTRL_REQUEST_I2C1RX (MXC_V_DMA_CTRL_REQUEST_I2C1RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C1RX Setting */ -#define MXC_V_DMA_CTRL_REQUEST_ADC ((uint32_t)0x9UL) /**< CTRL_REQUEST_ADC Value */ -#define MXC_S_DMA_CTRL_REQUEST_ADC (MXC_V_DMA_CTRL_REQUEST_ADC << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_ADC Setting */ -#define MXC_V_DMA_CTRL_REQUEST_I2C2RX ((uint32_t)0xAUL) /**< CTRL_REQUEST_I2C2RX Value */ -#define MXC_S_DMA_CTRL_REQUEST_I2C2RX (MXC_V_DMA_CTRL_REQUEST_I2C2RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C2RX Setting */ -#define MXC_V_DMA_CTRL_REQUEST_UART2RX ((uint32_t)0xEUL) /**< CTRL_REQUEST_UART2RX Value */ -#define MXC_S_DMA_CTRL_REQUEST_UART2RX (MXC_V_DMA_CTRL_REQUEST_UART2RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART2RX Setting */ -#define MXC_V_DMA_CTRL_REQUEST_SPI0RX ((uint32_t)0xFUL) /**< CTRL_REQUEST_SPI0RX Value */ -#define MXC_S_DMA_CTRL_REQUEST_SPI0RX (MXC_V_DMA_CTRL_REQUEST_SPI0RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI0RX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_UARTRX ((uint32_t)0x4UL) /**< CTRL_REQUEST_UARTRX Value */ +#define MXC_S_DMA_CTRL_REQUEST_UARTRX (MXC_V_DMA_CTRL_REQUEST_UARTRX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UARTRX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_I3CRX ((uint32_t)0x7UL) /**< CTRL_REQUEST_I3CRX Value */ +#define MXC_S_DMA_CTRL_REQUEST_I3CRX (MXC_V_DMA_CTRL_REQUEST_I3CRX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I3CRX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_SPIRX ((uint32_t)0xFUL) /**< CTRL_REQUEST_SPIRX Value */ +#define MXC_S_DMA_CTRL_REQUEST_SPIRX (MXC_V_DMA_CTRL_REQUEST_SPIRX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPIRX Setting */ #define MXC_V_DMA_CTRL_REQUEST_AESRX ((uint32_t)0x10UL) /**< CTRL_REQUEST_AESRX Value */ #define MXC_S_DMA_CTRL_REQUEST_AESRX (MXC_V_DMA_CTRL_REQUEST_AESRX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_AESRX Setting */ -#define MXC_V_DMA_CTRL_REQUEST_UART3RX ((uint32_t)0x1CUL) /**< CTRL_REQUEST_UART3RX Value */ -#define MXC_S_DMA_CTRL_REQUEST_UART3RX (MXC_V_DMA_CTRL_REQUEST_UART3RX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART3RX Setting */ -#define MXC_V_DMA_CTRL_REQUEST_I2SRX ((uint32_t)0x1EUL) /**< CTRL_REQUEST_I2SRX Value */ -#define MXC_S_DMA_CTRL_REQUEST_I2SRX (MXC_V_DMA_CTRL_REQUEST_I2SRX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2SRX Setting */ -#define MXC_V_DMA_CTRL_REQUEST_SPI1TX ((uint32_t)0x21UL) /**< CTRL_REQUEST_SPI1TX Value */ -#define MXC_S_DMA_CTRL_REQUEST_SPI1TX (MXC_V_DMA_CTRL_REQUEST_SPI1TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI1TX Setting */ -#define MXC_V_DMA_CTRL_REQUEST_UART0TX ((uint32_t)0x24UL) /**< CTRL_REQUEST_UART0TX Value */ -#define MXC_S_DMA_CTRL_REQUEST_UART0TX (MXC_V_DMA_CTRL_REQUEST_UART0TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART0TX Setting */ -#define MXC_V_DMA_CTRL_REQUEST_UART1TX ((uint32_t)0x25UL) /**< CTRL_REQUEST_UART1TX Value */ -#define MXC_S_DMA_CTRL_REQUEST_UART1TX (MXC_V_DMA_CTRL_REQUEST_UART1TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART1TX Setting */ -#define MXC_V_DMA_CTRL_REQUEST_I2C0TX ((uint32_t)0x27UL) /**< CTRL_REQUEST_I2C0TX Value */ -#define MXC_S_DMA_CTRL_REQUEST_I2C0TX (MXC_V_DMA_CTRL_REQUEST_I2C0TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C0TX Setting */ -#define MXC_V_DMA_CTRL_REQUEST_I2C1TX ((uint32_t)0x28UL) /**< CTRL_REQUEST_I2C1TX Value */ -#define MXC_S_DMA_CTRL_REQUEST_I2C1TX (MXC_V_DMA_CTRL_REQUEST_I2C1TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C1TX Setting */ -#define MXC_V_DMA_CTRL_REQUEST_I2C2TX ((uint32_t)0x2AUL) /**< CTRL_REQUEST_I2C2TX Value */ -#define MXC_S_DMA_CTRL_REQUEST_I2C2TX (MXC_V_DMA_CTRL_REQUEST_I2C2TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2C2TX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_UARTTX ((uint32_t)0x24UL) /**< CTRL_REQUEST_UARTTX Value */ +#define MXC_S_DMA_CTRL_REQUEST_UARTTX (MXC_V_DMA_CTRL_REQUEST_UARTTX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UARTTX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_I3CTX ((uint32_t)0x27UL) /**< CTRL_REQUEST_I3CTX Value */ +#define MXC_S_DMA_CTRL_REQUEST_I3CTX (MXC_V_DMA_CTRL_REQUEST_I3CTX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I3CTX Setting */ #define MXC_V_DMA_CTRL_REQUEST_CRCTX ((uint32_t)0x2CUL) /**< CTRL_REQUEST_CRCTX Value */ #define MXC_S_DMA_CTRL_REQUEST_CRCTX (MXC_V_DMA_CTRL_REQUEST_CRCTX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_CRCTX Setting */ -#define MXC_V_DMA_CTRL_REQUEST_UART2TX ((uint32_t)0x2EUL) /**< CTRL_REQUEST_UART2TX Value */ -#define MXC_S_DMA_CTRL_REQUEST_UART2TX (MXC_V_DMA_CTRL_REQUEST_UART2TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART2TX Setting */ -#define MXC_V_DMA_CTRL_REQUEST_SPI0TX ((uint32_t)0x2FUL) /**< CTRL_REQUEST_SPI0TX Value */ -#define MXC_S_DMA_CTRL_REQUEST_SPI0TX (MXC_V_DMA_CTRL_REQUEST_SPI0TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPI0TX Setting */ +#define MXC_V_DMA_CTRL_REQUEST_SPITX ((uint32_t)0x2FUL) /**< CTRL_REQUEST_SPITX Value */ +#define MXC_S_DMA_CTRL_REQUEST_SPITX (MXC_V_DMA_CTRL_REQUEST_SPITX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_SPITX Setting */ #define MXC_V_DMA_CTRL_REQUEST_AESTX ((uint32_t)0x30UL) /**< CTRL_REQUEST_AESTX Value */ #define MXC_S_DMA_CTRL_REQUEST_AESTX (MXC_V_DMA_CTRL_REQUEST_AESTX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_AESTX Setting */ -#define MXC_V_DMA_CTRL_REQUEST_UART3TX ((uint32_t)0x3CUL) /**< CTRL_REQUEST_UART3TX Value */ -#define MXC_S_DMA_CTRL_REQUEST_UART3TX (MXC_V_DMA_CTRL_REQUEST_UART3TX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_UART3TX Setting */ -#define MXC_V_DMA_CTRL_REQUEST_I2STX ((uint32_t)0x3EUL) /**< CTRL_REQUEST_I2STX Value */ -#define MXC_S_DMA_CTRL_REQUEST_I2STX (MXC_V_DMA_CTRL_REQUEST_I2STX << MXC_F_DMA_CTRL_REQUEST_POS) /**< CTRL_REQUEST_I2STX Setting */ #define MXC_F_DMA_CTRL_TO_WAIT_POS 10 /**< CTRL_TO_WAIT Position */ #define MXC_F_DMA_CTRL_TO_WAIT ((uint32_t)(0x1UL << MXC_F_DMA_CTRL_TO_WAIT_POS)) /**< CTRL_TO_WAIT Mask */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd index 8dab57da06e..b90fbc48bf2 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd @@ -621,48 +621,18 @@ 0x00 - SPI1RX - SPI1 RX - 0x01 - - - UART0RX - UART0 RX + UARTRX + UART RX 0x04 - UART1RX - UART1 RX - 0x05 - - - I2C0RX - I2C0 RX + I3CRX + I3C RX 0x07 - I2C1RX - I2C1 RX - 0x08 - - - ADC - ADC - 0x09 - - - I2C2RX - I2C2 RX - 0x0A - - - UART2RX - UART2 RX - 0x0E - - - SPI0RX - SPI0 RX + SPIRX + SPI RX 0x0F @@ -671,58 +641,23 @@ 0x10 - UART3RX - UART3 RX - 0x1C - - - I2SRX - I2S RX - 0x1E - - - SPI1TX - SPI1 TX - 0x21 - - - UART0TX - UART0 TX + UARTTX + UART TX 0x24 - UART1TX - UART1 TX - 0x25 - - - I2C0TX - I2C0 TX + I3CTX + I3C TX 0x27 - - I2C1TX - I2C1 TX - 0x28 - - - I2C2TX - I2C2 TX - 0x2A - CRCTX CRC TX 0x2C - UART2TX - UART2 TX - 0x2E - - - SPI0TX - SPI0 TX + SPITX + SPI TX 0x2F @@ -730,16 +665,6 @@ AES TX 0x30 - - UART3TX - UART3 TX - 0x3C - - - I2STX - I2S TX - 0x3E - diff --git a/Libraries/PeriphDrivers/Include/MAX32657/dma.h b/Libraries/PeriphDrivers/Include/MAX32657/dma.h index be679420abf..c806d7aae94 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/dma.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/dma.h @@ -57,39 +57,17 @@ typedef enum { typedef enum { MXC_DMA_REQUEST_MEMTOMEM = MXC_S_DMA_CTRL_REQUEST_MEMTOMEM, ///< Memory to Memory DMA Request Selection - MXC_DMA_REQUEST_SPI1RX = MXC_S_DMA_CTRL_REQUEST_SPI1RX, ///< SPI1 Receive DMA Request Selection - MXC_DMA_REQUEST_SPI0RX = MXC_S_DMA_CTRL_REQUEST_SPI0RX, ///< SPI0 Receive DMA Request Selection + MXC_DMA_REQUEST_SPIRX = MXC_S_DMA_CTRL_REQUEST_SPIRX, ///< SPI Receive DMA Request Selection MXC_DMA_REQUEST_UARTRX = - MXC_S_DMA_CTRL_REQUEST_UART0RX, ///< UART0 Receive DMA Request Selection - MXC_DMA_REQUEST_UART1RX = - MXC_S_DMA_CTRL_REQUEST_UART1RX, ///< UART1 Receive DMA Request Selection - MXC_DMA_REQUEST_I2C0RX = MXC_S_DMA_CTRL_REQUEST_I2C0RX, ///< I2C0 Receive DMA Request Selection - MXC_DMA_REQUEST_I2C1RX = MXC_S_DMA_CTRL_REQUEST_I2C1RX, ///< I2C1 Receive DMA Request Selection - MXC_DMA_REQUEST_ADC = MXC_S_DMA_CTRL_REQUEST_ADC, ///< ADC Receive DMA Request Selection - MXC_DMA_REQUEST_I2C2RX = MXC_S_DMA_CTRL_REQUEST_I2C2RX, ///< I2C2 Receive DMA Request Selection + MXC_S_DMA_CTRL_REQUEST_UARTRX, ///< UART Receive DMA Request Selection + MXC_DMA_REQUEST_I3CRX = MXC_S_DMA_CTRL_REQUEST_I3CRX, ///< I3C Receive DMA Request Selection MXC_DMA_REQUEST_AESRX = MXC_S_DMA_CTRL_REQUEST_AESRX, ///< AES Receive DMA Request Selection - MXC_DMA_REQUEST_UART2RX = - MXC_S_DMA_CTRL_REQUEST_UART2RX, ///< UART2 Receive DMA Request Selection - MXC_DMA_REQUEST_UART3RX = - MXC_S_DMA_CTRL_REQUEST_UART3RX, ///< UART3 Receive DMA Request Selection - MXC_DMA_REQUEST_I2SRX = MXC_S_DMA_CTRL_REQUEST_I2SRX, ///< I2S Receive DMA Request Selection - MXC_DMA_REQUEST_SPI1TX = MXC_S_DMA_CTRL_REQUEST_SPI1TX, ///< SPI1 Transmit DMA Request Selection - MXC_DMA_REQUEST_SPI0TX = MXC_S_DMA_CTRL_REQUEST_SPI0TX, ///< SPI0 Transmit DMA Request Selection + MXC_DMA_REQUEST_SPITX = MXC_S_DMA_CTRL_REQUEST_SPITX, ///< SPI Transmit DMA Request Selection MXC_DMA_REQUEST_UARTTX = - MXC_S_DMA_CTRL_REQUEST_UART0TX, ///< UART0 Transmit DMA Request Selection - MXC_DMA_REQUEST_UART1TX = - MXC_S_DMA_CTRL_REQUEST_UART1TX, ///< UART1 Transmit DMA Request Selection - MXC_DMA_REQUEST_I2C0TX = MXC_S_DMA_CTRL_REQUEST_I2C0TX, ///< I2C0 Transmit DMA Request Selection - MXC_DMA_REQUEST_I2C1TX = MXC_S_DMA_CTRL_REQUEST_I2C1TX, ///< I2C1 Transmit DMA Request Selection - MXC_DMA_REQUEST_I2C2TX = - MXC_S_DMA_CTRL_REQUEST_I2C2TX, ///< I2C2 Transmit DMA Request Selection */ + MXC_S_DMA_CTRL_REQUEST_UARTTX, ///< UART Transmit DMA Request Selection + MXC_DMA_REQUEST_I3CTX = MXC_S_DMA_CTRL_REQUEST_I3CTX, ///< I3C Transmit DMA Request Selection MXC_DMA_REQUEST_CRCTX = MXC_S_DMA_CTRL_REQUEST_CRCTX, ///< CRC Transmit DMA Request Selection */ MXC_DMA_REQUEST_AESTX = MXC_S_DMA_CTRL_REQUEST_AESTX, ///< AES Transmit DMA Request Selection - MXC_DMA_REQUEST_UART2TX = - MXC_S_DMA_CTRL_REQUEST_UART2TX, ///< UART2 Transmit DMA Request Selection - MXC_DMA_REQUEST_UART3TX = - MXC_S_DMA_CTRL_REQUEST_UART3TX, ///< UART3 Transmit DMA Request Selection - MXC_DMA_REQUEST_I2STX = MXC_S_DMA_CTRL_REQUEST_I2STX, ///< I2S Transmit DMA Request Selection } mxc_dma_reqsel_t; /** @brief Enumeration for the DMA prescaler */ diff --git a/Libraries/PeriphDrivers/Source/AES/aes_ai87.c b/Libraries/PeriphDrivers/Source/AES/aes_ai87.c index ba60f951604..d5a3eea3a8a 100644 --- a/Libraries/PeriphDrivers/Source/AES/aes_ai87.c +++ b/Libraries/PeriphDrivers/Source/AES/aes_ai87.c @@ -46,7 +46,7 @@ int MXC_AES_Init(void) // Start with a randomly generated key. MXC_AES_GenerateKey(); - MXC_AES_RevB_Init((mxc_aes_revb_regs_t *)MXC_AES); + MXC_AES_RevB_Init((mxc_aes_revb_regs_t *)MXC_AES, MXC_DMA); return E_NO_ERROR; } diff --git a/Libraries/PeriphDrivers/Source/AES/aes_me12.c b/Libraries/PeriphDrivers/Source/AES/aes_me12.c index 60c6eaeeb21..c66daaea508 100644 --- a/Libraries/PeriphDrivers/Source/AES/aes_me12.c +++ b/Libraries/PeriphDrivers/Source/AES/aes_me12.c @@ -41,7 +41,7 @@ int MXC_AES_Init(void) MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TRNG); #endif - return MXC_AES_RevB_Init((mxc_aes_revb_regs_t *)MXC_AES); + return MXC_AES_RevB_Init((mxc_aes_revb_regs_t *)MXC_AES, MXC_DMA); } void MXC_AES_EnableInt(uint32_t interrupt) diff --git a/Libraries/PeriphDrivers/Source/AES/aes_me15.c b/Libraries/PeriphDrivers/Source/AES/aes_me15.c index 60ecf1ead79..0a238ee8b6c 100644 --- a/Libraries/PeriphDrivers/Source/AES/aes_me15.c +++ b/Libraries/PeriphDrivers/Source/AES/aes_me15.c @@ -63,7 +63,7 @@ int MXC_AES_Init(void) // Start with a randomly generated key. MXC_AES_GenerateKey(); - MXC_AES_RevB_Init((mxc_aes_revb_regs_t *)MXC_AES); + MXC_AES_RevB_Init((mxc_aes_revb_regs_t *)MXC_AES, MXC_DMA); return E_NO_ERROR; } diff --git a/Libraries/PeriphDrivers/Source/AES/aes_me17.c b/Libraries/PeriphDrivers/Source/AES/aes_me17.c index 1cbca9635a9..50c7524712d 100644 --- a/Libraries/PeriphDrivers/Source/AES/aes_me17.c +++ b/Libraries/PeriphDrivers/Source/AES/aes_me17.c @@ -42,7 +42,7 @@ int MXC_AES_Init(void) MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TRNG); #endif - return MXC_AES_RevB_Init((mxc_aes_revb_regs_t *)MXC_AES); + return MXC_AES_RevB_Init((mxc_aes_revb_regs_t *)MXC_AES, MXC_DMA); } void MXC_AES_EnableInt(uint32_t interrupt) diff --git a/Libraries/PeriphDrivers/Source/AES/aes_me21.c b/Libraries/PeriphDrivers/Source/AES/aes_me21.c index cfb340482a9..83d50ad0623 100644 --- a/Libraries/PeriphDrivers/Source/AES/aes_me21.c +++ b/Libraries/PeriphDrivers/Source/AES/aes_me21.c @@ -40,7 +40,7 @@ int MXC_AES_Init(void) MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_TRNG); #endif - MXC_AES_RevB_Init((mxc_aes_revb_regs_t *)MXC_AES); + MXC_AES_RevB_Init((mxc_aes_revb_regs_t *)MXC_AES, MXC_DMA); return E_NO_ERROR; } diff --git a/Libraries/PeriphDrivers/Source/DMA/dma_reva_me30.svd b/Libraries/PeriphDrivers/Source/DMA/dma_reva_me30.svd index 2e190249a34..16ae2b95025 100644 --- a/Libraries/PeriphDrivers/Source/DMA/dma_reva_me30.svd +++ b/Libraries/PeriphDrivers/Source/DMA/dma_reva_me30.svd @@ -200,48 +200,18 @@ 0x00 - SPI1RX - SPI1 RX - 0x01 - - - UART0RX - UART0 RX + UARTRX + UART RX 0x04 - UART1RX - UART1 RX - 0x05 - - - I2C0RX - I2C0 RX + I3CRX + I3C RX 0x07 - I2C1RX - I2C1 RX - 0x08 - - - ADC - ADC - 0x09 - - - I2C2RX - I2C2 RX - 0x0A - - - UART2RX - UART2 RX - 0x0E - - - SPI0RX - SPI0 RX + SPIRX + SPI RX 0x0F @@ -250,58 +220,23 @@ 0x10 - UART3RX - UART3 RX - 0x1C - - - I2SRX - I2S RX - 0x1E - - - SPI1TX - SPI1 TX - 0x21 - - - UART0TX - UART0 TX + UARTTX + UART TX 0x24 - UART1TX - UART1 TX - 0x25 - - - I2C0TX - I2C0 TX + I3CTX + I3C TX 0x27 - - I2C1TX - I2C1 TX - 0x28 - - - I2C2TX - I2C2 TX - 0x2A - CRCTX CRC TX 0x2C - UART2TX - UART2 TX - 0x2E - - - SPI0TX - SPI0 TX + SPITX + SPI TX 0x2F @@ -309,16 +244,6 @@ AES TX 0x30 - - UART3TX - UART3 TX - 0x3C - - - I2STX - I2S TX - 0x3E - diff --git a/Libraries/PeriphDrivers/Source/SPI/spi_me30.c b/Libraries/PeriphDrivers/Source/SPI/spi_me30.c index 3d75b2bcd37..416b3ba8685 100644 --- a/Libraries/PeriphDrivers/Source/SPI/spi_me30.c +++ b/Libraries/PeriphDrivers/Source/SPI/spi_me30.c @@ -350,11 +350,7 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req, mxc_dma_regs_t *dma) if (req->txData != NULL) { switch (spi_num) { case 0: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; - - case 1: - reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselTx = MXC_DMA_REQUEST_SPITX; break; default: @@ -365,11 +361,7 @@ int MXC_SPI_MasterTransactionDMA(mxc_spi_req_t *req, mxc_dma_regs_t *dma) if (req->rxData != NULL) { switch (spi_num) { case 0: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; - - case 1: - reqselRx = MXC_DMA_REQUEST_SPI0RX; + reqselRx = MXC_DMA_REQUEST_SPIRX; break; default: @@ -403,11 +395,7 @@ int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req, mxc_dma_regs_t *dma) if (req->txData != NULL) { switch (spi_num) { case 0: - reqselTx = MXC_DMA_REQUEST_SPI1TX; - break; - - case 1: - reqselTx = MXC_DMA_REQUEST_SPI0TX; + reqselTx = MXC_DMA_REQUEST_SPITX; break; default: @@ -419,11 +407,7 @@ int MXC_SPI_SlaveTransactionDMA(mxc_spi_req_t *req, mxc_dma_regs_t *dma) if (req->rxData != NULL) { switch (spi_num) { case 0: - reqselRx = MXC_DMA_REQUEST_SPI1RX; - break; - - case 1: - reqselRx = MXC_DMA_REQUEST_SPI0RX; + reqselRx = MXC_DMA_REQUEST_SPIRX; break; default: diff --git a/Libraries/PeriphDrivers/Source/UART/uart_ai85.c b/Libraries/PeriphDrivers/Source/UART/uart_ai85.c index 361a7e13c63..722bf8881b2 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_ai85.c +++ b/Libraries/PeriphDrivers/Source/UART/uart_ai85.c @@ -328,7 +328,7 @@ int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned break; } - return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); + return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, config); } unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart) @@ -371,7 +371,7 @@ int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, const unsigned char *bytes, u break; } - return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); + return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, config); } unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart) @@ -446,7 +446,7 @@ int MXC_UART_TransactionAsync(mxc_uart_req_t *req) int MXC_UART_TransactionDMA(mxc_uart_req_t *req) { - return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req); + return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req, MXC_DMA); } int MXC_UART_AbortAsync(mxc_uart_regs_t *uart) diff --git a/Libraries/PeriphDrivers/Source/UART/uart_ai87.c b/Libraries/PeriphDrivers/Source/UART/uart_ai87.c index 51f31363a04..3ec7f5b6241 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_ai87.c +++ b/Libraries/PeriphDrivers/Source/UART/uart_ai87.c @@ -343,7 +343,7 @@ int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned break; } - return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); + return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, config); } unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart) @@ -382,7 +382,7 @@ int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, const unsigned char *bytes, u break; } - return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); + return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, config); } unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart) @@ -457,7 +457,7 @@ int MXC_UART_TransactionAsync(mxc_uart_req_t *req) int MXC_UART_TransactionDMA(mxc_uart_req_t *req) { - return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req); + return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req, MXC_DMA); } int MXC_UART_AbortAsync(mxc_uart_regs_t *uart) diff --git a/Libraries/PeriphDrivers/Source/UART/uart_me12.c b/Libraries/PeriphDrivers/Source/UART/uart_me12.c index 4f3b33da878..801ac966c81 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_me12.c +++ b/Libraries/PeriphDrivers/Source/UART/uart_me12.c @@ -259,7 +259,7 @@ int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned break; } - return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); + return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, config); } unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart) @@ -291,7 +291,7 @@ int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, const unsigned char *bytes, u break; } - return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); + return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, config); } unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart) @@ -366,7 +366,7 @@ int MXC_UART_TransactionAsync(mxc_uart_req_t *req) int MXC_UART_TransactionDMA(mxc_uart_req_t *req) { - return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req); + return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req, MXC_DMA); } int MXC_UART_AbortAsync(mxc_uart_regs_t *uart) diff --git a/Libraries/PeriphDrivers/Source/UART/uart_me15.c b/Libraries/PeriphDrivers/Source/UART/uart_me15.c index 3a89341ff61..142963f7b73 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_me15.c +++ b/Libraries/PeriphDrivers/Source/UART/uart_me15.c @@ -398,7 +398,7 @@ int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned break; } - return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); + return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, config); } unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart) @@ -437,7 +437,7 @@ int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, const unsigned char *bytes, u break; } - return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); + return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, config); } unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart) @@ -514,7 +514,7 @@ int MXC_UART_TransactionAsync(mxc_uart_req_t *req) int MXC_UART_TransactionDMA(mxc_uart_req_t *req) { - return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req); + return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req, MXC_DMA); } int MXC_UART_AbortAsync(mxc_uart_regs_t *uart) diff --git a/Libraries/PeriphDrivers/Source/UART/uart_me16.c b/Libraries/PeriphDrivers/Source/UART/uart_me16.c index d7c4640d5b2..86e6466afa5 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_me16.c +++ b/Libraries/PeriphDrivers/Source/UART/uart_me16.c @@ -339,7 +339,7 @@ int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned break; } - return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); + return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, config); } unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart) @@ -374,7 +374,7 @@ int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, const unsigned char *bytes, u break; } - return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); + return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, config); } unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart) @@ -451,7 +451,7 @@ int MXC_UART_TransactionAsync(mxc_uart_req_t *req) int MXC_UART_TransactionDMA(mxc_uart_req_t *req) { - return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req); + return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req, MXC_DMA); } int MXC_UART_AbortAsync(mxc_uart_regs_t *uart) diff --git a/Libraries/PeriphDrivers/Source/UART/uart_me17.c b/Libraries/PeriphDrivers/Source/UART/uart_me17.c index 7d9a4343e5a..4fea36b300d 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_me17.c +++ b/Libraries/PeriphDrivers/Source/UART/uart_me17.c @@ -364,7 +364,7 @@ int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned break; } - return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); + return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, config); } unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart) @@ -406,7 +406,7 @@ int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, const unsigned char *bytes, u break; } - return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); + return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, config); } unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart) @@ -481,7 +481,7 @@ int MXC_UART_TransactionAsync(mxc_uart_req_t *req) int MXC_UART_TransactionDMA(mxc_uart_req_t *req) { - return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req); + return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req, MXC_DMA); } int MXC_UART_AbortAsync(mxc_uart_regs_t *uart) diff --git a/Libraries/PeriphDrivers/Source/UART/uart_me18.c b/Libraries/PeriphDrivers/Source/UART/uart_me18.c index 7539ab305eb..88a19b95ab9 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_me18.c +++ b/Libraries/PeriphDrivers/Source/UART/uart_me18.c @@ -404,7 +404,7 @@ int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned break; } - return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); + return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, config); } unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart) @@ -446,7 +446,7 @@ int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, const unsigned char *bytes, u break; } - return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); + return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, config); } unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart) @@ -521,7 +521,7 @@ int MXC_UART_TransactionAsync(mxc_uart_req_t *req) int MXC_UART_TransactionDMA(mxc_uart_req_t *req) { - return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req); + return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req, MXC_DMA); } int MXC_UART_AbortAsync(mxc_uart_regs_t *uart) diff --git a/Libraries/PeriphDrivers/Source/UART/uart_me21.c b/Libraries/PeriphDrivers/Source/UART/uart_me21.c index c6ec59c119a..d3ef357bb3f 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_me21.c +++ b/Libraries/PeriphDrivers/Source/UART/uart_me21.c @@ -437,7 +437,7 @@ int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned break; } - return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); + return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, config); } unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart) @@ -475,7 +475,7 @@ int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigne break; } - return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); + return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, config); } unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart) @@ -552,7 +552,7 @@ int MXC_UART_TransactionAsync(mxc_uart_req_t *req) int MXC_UART_TransactionDMA(mxc_uart_req_t *req) { - return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req); + return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req, MXC_DMA); } int MXC_UART_AbortAsync(mxc_uart_regs_t *uart) diff --git a/Libraries/PeriphDrivers/Source/UART/uart_me55.c b/Libraries/PeriphDrivers/Source/UART/uart_me55.c index 463e315facd..b7859c068f1 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_me55.c +++ b/Libraries/PeriphDrivers/Source/UART/uart_me55.c @@ -298,7 +298,7 @@ int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned break; } - return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); + return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, config); } unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart) @@ -340,7 +340,7 @@ int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, const unsigned char *bytes, u break; } - return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, bytes, len, callback, config); + return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, config); } unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart) @@ -415,7 +415,7 @@ int MXC_UART_TransactionAsync(mxc_uart_req_t *req) int MXC_UART_TransactionDMA(mxc_uart_req_t *req) { - return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req); + return MXC_UART_RevB_TransactionDMA((mxc_uart_revb_req_t *)req, MXC_DMA); } int MXC_UART_AbortAsync(mxc_uart_regs_t *uart) diff --git a/Libraries/PeriphDrivers/Source/UART/uart_reva.c b/Libraries/PeriphDrivers/Source/UART/uart_reva.c index 66517e7b427..3c3ccf8a073 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_reva.c +++ b/Libraries/PeriphDrivers/Source/UART/uart_reva.c @@ -506,13 +506,7 @@ unsigned int MXC_UART_RevA_ReadRXFIFO(mxc_uart_reva_regs_t *uart, unsigned char return read; } - -// TODO(DMA): Replaced the DMA instance number check to the only -// parts affected by this. Our DMA drivers probably -// needs a rework to handle multiple instances because -// the ME14's DMA drivers are very limited with -// the DMA instance selection. -#if (TARGET_NUM == 32665 || TARGET_NUM == 32657) +#if (MXC_DMA_INSTANCES > 1) void MXC_UART_RevA_DMA0_Handler(void) { @@ -532,17 +526,17 @@ DMA instance. void MXC_UART_RevA_DMA_SetupAutoHandlers(mxc_dma_regs_t *dma_instance, unsigned int channel) { #ifdef __arm__ -#if (TARGET_NUM == 32665 || TARGET_NUM == 32657) - NVIC_EnableIRQ(MXC_DMA_CH_GET_IRQ(dma_instance, channel)); +#if (MXC_DMA_INSTANCES > 1) + NVIC_EnableIRQ(MXC_DMA_CH_GET_IRQ(channel)); /* (JC): This is not the cleanest or most scalable way to do this, but I tried defining default handler's in the system file. Some complications make this the most attractive short-term option. We could handle multiple DMA instances better in the DMA API (See the mismatch between the size of "dma_resource" array and the number of channels per instance, to start)*/ if (dma_instance == MXC_DMA0) { - MXC_NVIC_SetVector(MXC_DMA_CH_GET_IRQ(dma_instance, channel), MXC_UART_RevA_DMA0_Handler); + MXC_NVIC_SetVector(MXC_DMA_CH_GET_IRQ(channel), MXC_UART_RevA_DMA0_Handler); } else if (dma_instance == MXC_DMA1) { - MXC_NVIC_SetVector(MXC_DMA_CH_GET_IRQ(dma_instance, channel), MXC_UART_RevA_DMA1_Handler); + MXC_NVIC_SetVector(MXC_DMA_CH_GET_IRQ(channel), MXC_UART_RevA_DMA1_Handler); } #else NVIC_EnableIRQ(MXC_DMA_CH_GET_IRQ(channel)); @@ -572,7 +566,7 @@ int MXC_UART_RevA_ReadRXFIFODMA(mxc_uart_reva_regs_t *uart, mxc_dma_regs_t *dma, if (states[uart_num].auto_dma_handlers && states[uart_num].channelRx < 0) { /* Acquire channel if we don't have one already */ -#if MXC_DMA_INSTANCES > 1 || TARGET_NUM == 32657 +#if MXC_DMA_INSTANCES > 1 channel = MXC_DMA_AcquireChannel(dma); #else channel = MXC_DMA_AcquireChannel(); @@ -604,11 +598,7 @@ int MXC_UART_RevA_ReadRXFIFODMA(mxc_uart_reva_regs_t *uart, mxc_dma_regs_t *dma, MXC_DMA_ConfigChannel(config, srcdst); MXC_DMA_SetCallback(channel, MXC_UART_DMACallback); -#if (TARGET_NUM == 32657) - MXC_DMA_EnableInt(dma, channel); -#else MXC_DMA_EnableInt(channel); -#endif MXC_DMA_Start(channel); //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; @@ -697,7 +687,7 @@ unsigned int MXC_UART_RevA_WriteTXFIFODMA(mxc_uart_reva_regs_t *uart, mxc_dma_re if (states[uart_num].auto_dma_handlers && states[uart_num].channelTx < 0) { /* Acquire channel if we don't have one already */ -#if (TARGET_NUM == 32665 || TARGET_NUM == 32657) +#if (TARGET_NUM == 32665) channel = MXC_DMA_AcquireChannel(dma); #else channel = MXC_DMA_AcquireChannel(); @@ -727,11 +717,7 @@ unsigned int MXC_UART_RevA_WriteTXFIFODMA(mxc_uart_reva_regs_t *uart, mxc_dma_re MXC_DMA_ConfigChannel(config, srcdst); MXC_DMA_SetCallback(channel, MXC_UART_DMACallback); -#if (TARGET_NUM == 32657) - MXC_DMA_EnableInt(dma, channel); -#else MXC_DMA_EnableInt(channel); -#endif MXC_DMA_Start(channel); //MXC_DMA->ch[channel].ctrl |= MXC_F_DMA_CTRL_CTZ_IE; @@ -1003,7 +989,7 @@ int MXC_UART_RevA_TransactionDMA(mxc_uart_reva_req_t *req, mxc_dma_regs_t *dma) (req->uart)->dma |= (2 << MXC_F_UART_REVA_DMA_TXDMA_LEVEL_POS); // Set TX DMA threshold to 2 bytes -#if (TARGET_NUM == 32665 || TARGET_NUM == 32657) +#if (TARGET_NUM == 32665) MXC_DMA_Init(dma); #else MXC_DMA_Init(); @@ -1017,7 +1003,7 @@ int MXC_UART_RevA_TransactionDMA(mxc_uart_reva_req_t *req, mxc_dma_regs_t *dma) if ((req->txData != NULL) && (req->txLen)) { /* Save TX req, the DMA handler will use this later. */ states[uart_num].tx_req = req; -#if (TARGET_NUM == 32665 || TARGET_NUM == 32657) +#if (TARGET_NUM == 32665) if (MXC_UART_WriteTXFIFODMA((mxc_uart_regs_t *)(req->uart), dma, req->txData, req->txLen, NULL) != E_NO_ERROR) { return E_BAD_PARAM; @@ -1032,7 +1018,7 @@ int MXC_UART_RevA_TransactionDMA(mxc_uart_reva_req_t *req, mxc_dma_regs_t *dma) if ((req->rxData != NULL) && (req->rxLen)) { states[uart_num].rx_req = req; -#if (TARGET_NUM == 32665 || TARGET_NUM == 32657) +#if (TARGET_NUM == 32665) if (MXC_UART_ReadRXFIFODMA((mxc_uart_regs_t *)(req->uart), dma, req->rxData, req->rxLen, NULL) != E_NO_ERROR) { return E_BAD_PARAM; diff --git a/Libraries/PeriphDrivers/Source/UART/uart_revb.c b/Libraries/PeriphDrivers/Source/UART/uart_revb.c index 87b81fd714e..22f2dc503ba 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_revb.c +++ b/Libraries/PeriphDrivers/Source/UART/uart_revb.c @@ -829,12 +829,7 @@ int MXC_UART_RevB_SetAutoDMAHandlers(mxc_uart_revb_regs_t *uart, bool enable) } -// TODO(DMA): Replaced the DMA instance number check to the only -// parts affected by this. Our DMA drivers probably -// needs a rework to handle multiple instances because -// the ME14's DMA drivers are very limited with -// the DMA instance selection. -#if (TARGET_NUM == 32657) +#if (MXC_DMA_INSTANCES > 1) void MXC_UART_RevA_DMA0_Handler(void) { @@ -854,7 +849,7 @@ DMA instance. void MXC_UART_RevB_DMA_SetupAutoHandlers(mxc_dma_regs_t *dma_instance, unsigned int channel) { #ifdef __arm__ -#if (TARGET_NUM == 32657) +#if (MXC_DMA_INSTANCES > 1) NVIC_EnableIRQ(MXC_DMA_CH_GET_IRQ(dma_instance, channel)); /* (JC): This is not the cleanest or most scalable way to do this, @@ -926,7 +921,7 @@ int MXC_UART_RevB_ReadRXFIFODMA(mxc_uart_revb_regs_t *uart, mxc_dma_regs_t *dma, if (states[uart_num].auto_dma_handlers && states[uart_num].channelRx < 0) { /* Acquire channel if we don't have one already */ -#if (TARGET_NUM == 32657) +#if (MXC_DMA_INSTANCES > 1) channel = MXC_DMA_AcquireChannel(dma); #else channel = MXC_DMA_AcquireChannel(); @@ -955,7 +950,7 @@ int MXC_UART_RevB_ReadRXFIFODMA(mxc_uart_revb_regs_t *uart, mxc_dma_regs_t *dma, MXC_DMA_ConfigChannel(config, srcdst); MXC_DMA_SetCallback(channel, MXC_UART_DMACallback); -#if (TARGET_NUM == 32657) +#if (MXC_DMA_INSTANCES > 1) MXC_DMA_EnableInt(dma, channel); #else MXC_DMA_EnableInt(channel); @@ -984,7 +979,7 @@ int MXC_UART_RevB_WriteTXFIFODMA(mxc_uart_revb_regs_t *uart, mxc_dma_regs_t *dma if (states[uart_num].auto_dma_handlers && states[uart_num].channelTx < 0) { /* Acquire channel if we don't have one already */ -#if (TARGET_NUM == 32657) +#if (MXC_DMA_INSTANCES > 1) channel = MXC_DMA_AcquireChannel(dma); #else channel = MXC_DMA_AcquireChannel(); @@ -1013,7 +1008,7 @@ int MXC_UART_RevB_WriteTXFIFODMA(mxc_uart_revb_regs_t *uart, mxc_dma_regs_t *dma MXC_DMA_ConfigChannel(config, srcdst); MXC_DMA_SetCallback(channel, MXC_UART_DMACallback); -#if (TARGET_NUM == 32657) +#if (MXC_DMA_INSTANCES > 1) MXC_DMA_EnableInt(dma, channel); #else MXC_DMA_EnableInt(channel); @@ -1058,7 +1053,7 @@ int MXC_UART_RevB_TransactionDMA(mxc_uart_revb_req_t *req, mxc_dma_regs_t *dma) (req->uart)->dma |= (1 << MXC_F_UART_REVB_DMA_RX_THD_VAL_POS); (req->uart)->dma |= (2 << MXC_F_UART_REVB_DMA_TX_THD_VAL_POS); -#if (TARGET_NUM == 32657) +#if (MXC_DMA_INSTANCES > 1) MXC_DMA_Init(dma); #else MXC_DMA_Init(); @@ -1072,8 +1067,13 @@ int MXC_UART_RevB_TransactionDMA(mxc_uart_revb_req_t *req, mxc_dma_regs_t *dma) if ((req->txData != NULL) && (req->txLen)) { /* Save TX req, the DMA handler will use this later. */ states[uart_num].tx_req = req; +#if (MXC_DMA_INSTANCES > 1) if (MXC_UART_WriteTXFIFODMA((mxc_uart_regs_t *)(req->uart), dma, req->txData, req->txLen, NULL) != E_NO_ERROR) { +#else + if (MXC_UART_WriteTXFIFODMA((mxc_uart_regs_t *)(req->uart), req->txData, req->txLen, + NULL) != E_NO_ERROR) { +#endif return E_BAD_PARAM; } } @@ -1081,8 +1081,13 @@ int MXC_UART_RevB_TransactionDMA(mxc_uart_revb_req_t *req, mxc_dma_regs_t *dma) //rx if ((req->rxData != NULL) && (req->rxLen)) { states[uart_num].rx_req = req; +#if (MXC_DMA_INSTANCES > 1) if (MXC_UART_ReadRXFIFODMA((mxc_uart_regs_t *)(req->uart), dma, req->rxData, req->rxLen, NULL) != E_NO_ERROR) { +#else + if (MXC_UART_ReadRXFIFODMA((mxc_uart_regs_t *)(req->uart), req->rxData, req->rxLen, NULL) != + E_NO_ERROR) { +#endif return E_BAD_PARAM; } } From 089f77cd76561ea59b6ac162aef413b064ca5f53 Mon Sep 17 00:00:00 2001 From: Woo Date: Fri, 10 May 2024 16:27:27 -0500 Subject: [PATCH 78/93] Update copyrights --- Examples/MAX32657/Hello_World/main.c | 4 +- .../Boards/MAX32657/EvKit_V1/Include/board.h | 4 +- .../Boards/MAX32657/EvKit_V1/Source/board.c | 4 +- Libraries/Boards/MAX32657/EvKit_V1/board.mk | 4 +- .../Maxim/MAX32657/Source/GCC/max32657.mk | 4 +- .../MAX32657/Source/GCC/startup_max32657.S | 4 +- .../PeriphDrivers/Include/MAX32572/spi.h | 47 +++++++------------ .../PeriphDrivers/Include/MAX32690/spi.h | 2 + .../PeriphDrivers/Include/MAX78002/spi.h | 2 + Libraries/PeriphDrivers/max32657_files.mk | 4 +- 10 files changed, 29 insertions(+), 50 deletions(-) diff --git a/Examples/MAX32657/Hello_World/main.c b/Examples/MAX32657/Hello_World/main.c index 5a4ce99ba9d..843e085dce8 100644 --- a/Examples/MAX32657/Hello_World/main.c +++ b/Examples/MAX32657/Hello_World/main.c @@ -1,8 +1,6 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/Libraries/Boards/MAX32657/EvKit_V1/Include/board.h b/Libraries/Boards/MAX32657/EvKit_V1/Include/board.h index c656e706544..1cb5f8006d7 100644 --- a/Libraries/Boards/MAX32657/EvKit_V1/Include/board.h +++ b/Libraries/Boards/MAX32657/EvKit_V1/Include/board.h @@ -1,8 +1,6 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/Libraries/Boards/MAX32657/EvKit_V1/Source/board.c b/Libraries/Boards/MAX32657/EvKit_V1/Source/board.c index 4d02252ff00..d646e717d7b 100644 --- a/Libraries/Boards/MAX32657/EvKit_V1/Source/board.c +++ b/Libraries/Boards/MAX32657/EvKit_V1/Source/board.c @@ -1,8 +1,6 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/Libraries/Boards/MAX32657/EvKit_V1/board.mk b/Libraries/Boards/MAX32657/EvKit_V1/board.mk index 246fa72e684..15d62442879 100644 --- a/Libraries/Boards/MAX32657/EvKit_V1/board.mk +++ b/Libraries/Boards/MAX32657/EvKit_V1/board.mk @@ -1,8 +1,6 @@ ############################################################################### # - # Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - # Analog Devices, Inc.), - # Copyright (C) 2023-2024 Analog Devices, Inc. + # Copyright (C) 2024 Analog Devices, Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.mk b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.mk index 2fc1415874f..69ff32192f5 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.mk +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/max32657.mk @@ -1,8 +1,6 @@ ############################################################################### # - # Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - # Analog Devices, Inc.), - # Copyright (C) 2023-2024 Analog Devices, Inc. + # Copyright (C) 2024 Analog Devices, Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/startup_max32657.S b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/startup_max32657.S index 2fe3954e105..7c869bf8928 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/startup_max32657.S +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Source/GCC/startup_max32657.S @@ -1,8 +1,6 @@ /****************************************************************************** * - * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - * Analog Devices, Inc.), - * Copyright (C) 2023-2024 Analog Devices, Inc. + * Copyright (C) 2024 Analog Devices, Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. diff --git a/Libraries/PeriphDrivers/Include/MAX32572/spi.h b/Libraries/PeriphDrivers/Include/MAX32572/spi.h index bf119b2e843..a916096cbc9 100644 --- a/Libraries/PeriphDrivers/Include/MAX32572/spi.h +++ b/Libraries/PeriphDrivers/Include/MAX32572/spi.h @@ -4,35 +4,22 @@ */ /****************************************************************************** - * Copyright (C) 2023 Maxim Integrated Products, Inc., All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included - * in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS - * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF - * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. - * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES - * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Except as contained in this notice, the name of Maxim Integrated - * Products, Inc. shall not be used except as stated in the Maxim Integrated - * Products, Inc. Branding Policy. - * - * The mere transfer of this software does not imply any licenses - * of trade secrets, proprietary technology, copyrights, patents, - * trademarks, maskwork rights, or any other form of intellectual - * property whatsoever. Maxim Integrated Products, Inc. retains all - * ownership rights. + * + * Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by + * Analog Devices, Inc.), + * Copyright (C) 2023-2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. * ******************************************************************************/ @@ -606,6 +593,8 @@ unsigned int MXC_SPI_GetTXThreshold(mxc_spi_regs_t *spi); */ unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t *spi); +//////>>> Previous Implementation + /** * @brief Sets the number of bits per character * diff --git a/Libraries/PeriphDrivers/Include/MAX32690/spi.h b/Libraries/PeriphDrivers/Include/MAX32690/spi.h index b27fa01970e..65f2ce1d115 100644 --- a/Libraries/PeriphDrivers/Include/MAX32690/spi.h +++ b/Libraries/PeriphDrivers/Include/MAX32690/spi.h @@ -591,6 +591,8 @@ unsigned int MXC_SPI_GetTXThreshold(mxc_spi_regs_t *spi); */ unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t *spi); +//////>>> Previous Implementation + /** * @brief Sets the number of bits per character * diff --git a/Libraries/PeriphDrivers/Include/MAX78002/spi.h b/Libraries/PeriphDrivers/Include/MAX78002/spi.h index 8091c786738..52b8773c973 100644 --- a/Libraries/PeriphDrivers/Include/MAX78002/spi.h +++ b/Libraries/PeriphDrivers/Include/MAX78002/spi.h @@ -592,6 +592,8 @@ unsigned int MXC_SPI_GetTXThreshold(mxc_spi_regs_t *spi); */ unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t *spi); +//////>>> Previous Implementation + /** * @brief Sets the number of bits per character * diff --git a/Libraries/PeriphDrivers/max32657_files.mk b/Libraries/PeriphDrivers/max32657_files.mk index 9fb3de25b0d..e27970193f1 100644 --- a/Libraries/PeriphDrivers/max32657_files.mk +++ b/Libraries/PeriphDrivers/max32657_files.mk @@ -1,8 +1,6 @@ ############################################################################### # - # Copyright (C) 2022-2023 Maxim Integrated Products, Inc. (now owned by - # Analog Devices, Inc.), - # Copyright (C) 2023-2024 Analog Devices, Inc. + # Copyright (C) 2024 Analog Devices, Inc. # # Licensed under the Apache License, Version 2.0 (the "License"); # you may not use this file except in compliance with the License. From c25f62c0ff0e22f20cde9ae6269f7d8fa20b5019 Mon Sep 17 00:00:00 2001 From: Woo Date: Fri, 10 May 2024 16:28:27 -0500 Subject: [PATCH 79/93] Revert to original --- Libraries/PeriphDrivers/Include/MAX32572/spi.h | 1 - Libraries/PeriphDrivers/Include/MAX32690/spi.h | 1 - Libraries/PeriphDrivers/Include/MAX78002/spi.h | 1 - 3 files changed, 3 deletions(-) diff --git a/Libraries/PeriphDrivers/Include/MAX32572/spi.h b/Libraries/PeriphDrivers/Include/MAX32572/spi.h index a916096cbc9..4471b05eb9f 100644 --- a/Libraries/PeriphDrivers/Include/MAX32572/spi.h +++ b/Libraries/PeriphDrivers/Include/MAX32572/spi.h @@ -594,7 +594,6 @@ unsigned int MXC_SPI_GetTXThreshold(mxc_spi_regs_t *spi); unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t *spi); //////>>> Previous Implementation - /** * @brief Sets the number of bits per character * diff --git a/Libraries/PeriphDrivers/Include/MAX32690/spi.h b/Libraries/PeriphDrivers/Include/MAX32690/spi.h index 65f2ce1d115..d34563aafe2 100644 --- a/Libraries/PeriphDrivers/Include/MAX32690/spi.h +++ b/Libraries/PeriphDrivers/Include/MAX32690/spi.h @@ -592,7 +592,6 @@ unsigned int MXC_SPI_GetTXThreshold(mxc_spi_regs_t *spi); unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t *spi); //////>>> Previous Implementation - /** * @brief Sets the number of bits per character * diff --git a/Libraries/PeriphDrivers/Include/MAX78002/spi.h b/Libraries/PeriphDrivers/Include/MAX78002/spi.h index 52b8773c973..4d99415b096 100644 --- a/Libraries/PeriphDrivers/Include/MAX78002/spi.h +++ b/Libraries/PeriphDrivers/Include/MAX78002/spi.h @@ -593,7 +593,6 @@ unsigned int MXC_SPI_GetTXThreshold(mxc_spi_regs_t *spi); unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t *spi); //////>>> Previous Implementation - /** * @brief Sets the number of bits per character * From b2fc705c10a66825eb89d6af643cea344dc19ef2 Mon Sep 17 00:00:00 2001 From: Woo Date: Fri, 10 May 2024 16:29:12 -0500 Subject: [PATCH 80/93] Revert to original --- Libraries/PeriphDrivers/Include/MAX32690/spi.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Libraries/PeriphDrivers/Include/MAX32690/spi.h b/Libraries/PeriphDrivers/Include/MAX32690/spi.h index d34563aafe2..1063362a87b 100644 --- a/Libraries/PeriphDrivers/Include/MAX32690/spi.h +++ b/Libraries/PeriphDrivers/Include/MAX32690/spi.h @@ -591,7 +591,7 @@ unsigned int MXC_SPI_GetTXThreshold(mxc_spi_regs_t *spi); */ unsigned int MXC_SPI_GetRXThreshold(mxc_spi_regs_t *spi); -//////>>> Previous Implementation +//////>>> Previous Implementation (SPI v1) /** * @brief Sets the number of bits per character * From 908fdfd583255e0d59d628d4b09649bf172d672c Mon Sep 17 00:00:00 2001 From: Woo Date: Sat, 11 May 2024 17:13:38 -0500 Subject: [PATCH 81/93] clang-format --- .../Device/Maxim/MAX32657/Include/max32657.h | 32 +++++----- .../MAX32657/Include/partition_max32657.h | 1 + .../PeriphDrivers/Include/MAX32657/dma.h | 6 +- .../PeriphDrivers/Include/MAX32657/mxc_sys.h | 45 +++++--------- .../PeriphDrivers/Include/MAX32657/uart.h | 8 +-- Libraries/PeriphDrivers/Source/AES/aes_revb.c | 3 +- Libraries/PeriphDrivers/Source/DMA/dma_me30.c | 3 +- Libraries/PeriphDrivers/Source/SPI/spi_me30.c | 38 ++++++------ Libraries/PeriphDrivers/Source/SYS/sys_me30.c | 62 +++++++++---------- .../PeriphDrivers/Source/UART/uart_ai85.c | 6 +- .../PeriphDrivers/Source/UART/uart_ai87.c | 6 +- .../PeriphDrivers/Source/UART/uart_me12.c | 6 +- .../PeriphDrivers/Source/UART/uart_me15.c | 6 +- .../PeriphDrivers/Source/UART/uart_me16.c | 6 +- .../PeriphDrivers/Source/UART/uart_me17.c | 6 +- .../PeriphDrivers/Source/UART/uart_me18.c | 6 +- .../PeriphDrivers/Source/UART/uart_me21.c | 6 +- .../PeriphDrivers/Source/UART/uart_me30.c | 14 +++-- .../PeriphDrivers/Source/UART/uart_me55.c | 6 +- .../PeriphDrivers/Source/UART/uart_reva.c | 2 +- .../PeriphDrivers/Source/UART/uart_revb.c | 17 +++-- .../PeriphDrivers/Source/UART/uart_revb.h | 9 +-- Libraries/PeriphDrivers/Source/WDT/wdt_me30.c | 3 +- 23 files changed, 151 insertions(+), 146 deletions(-) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h index 9af4c582050..7ef1eeace46 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h @@ -141,15 +141,15 @@ typedef enum { /* ================== Processor Section ================== */ /* ================================================================================ */ -#define __CM33_REV 0x0000U /**< Cortex-M33 Core revision */ -#define __DSP_PRESENT 1U /**< Presence of DSP */ -#define __FPU_PRESENT 1U /**< Presence of FPU */ -#define __MPU_PRESENT 1U /**< Presence of MPU */ -#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ -#define __TZ_PRESENT 1U /**< Presence of TrustZone */ -#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ -#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ -#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ +#define __CM33_REV 0x0000U /**< Cortex-M33 Core revision */ +#define __DSP_PRESENT 1U /**< Presence of DSP */ +#define __FPU_PRESENT 1U /**< Presence of FPU */ +#define __MPU_PRESENT 1U /**< Presence of MPU */ +#define __SAUREGION_PRESENT 1U /**< Presence of FPU */ +#define __TZ_PRESENT 1U /**< Presence of TrustZone */ +#define __VTOR_PRESENT 1U /**< Presence of VTOR register in SCB */ +#define __NVIC_PRIO_BITS 4U /**< NVIC interrupt priority bits */ +#define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ #include #include @@ -168,7 +168,7 @@ typedef enum { /* Secure Regions */ /* ROM is always in secure region. */ -#define MXC_ROM_MEM_BASE 0x00000000UL +#define MXC_ROM_MEM_BASE 0x00000000UL #define MXC_ROM_MEM_SIZE 0x00010000UL #define MXC_FLASH_S_MEM_BASE 0x11000000UL #define MXC_FLASH_S_PAGE_SIZE 0x00002000UL @@ -468,7 +468,7 @@ typedef enum { #define MXC_BASE_GPIO0_NS ((uint32_t)0x40008000UL) #define MXC_GPIO0_NS ((mxc_gpio_regs_t *)MXC_BASE_GPIO0_NS) -#define MXC_GPIO_NS_GET_IDX(p) ((p) == MXC_GPIO0_NS ? 0 : -1) +#define MXC_GPIO_NS_GET_IDX(p) ((p) == MXC_GPIO0_NS ? 0 : -1) #define MXC_GPIO_NS_GET_GPIO(i) ((i) == 0 ? MXC_GPIO0_NS : 0) /* Secure Mapping */ @@ -599,7 +599,7 @@ We may want to handle GET_IRQ better... (p) == MXC_TMR3 ? 3 : \ (p) == MXC_TMR4 ? 4 : \ (p) == MXC_TMR5 ? 5 : \ - -1) + -1) /******************************************************************************/ /* I3C */ @@ -653,7 +653,7 @@ We may want to handle GET_IRQ better... #define MXC_BASE_DMA1 MXC_BASE_DMA1_S #define MXC_DMA1 MXC_DMA1_S -#define MXC_DMA_CH_GET_IRQ(p, i) \ +#define MXC_DMA_CH_GET_IRQ(p, i) \ ((IRQn_Type)(((p) == MXC_DMA0 && (i) == 0) ? DMA0_CH0_IRQn : \ ((p) == MXC_DMA0 && (i) == 1) ? DMA0_CH1_IRQn : \ ((p) == MXC_DMA0 && (i) == 2) ? DMA0_CH2_IRQn : \ @@ -662,7 +662,7 @@ We may want to handle GET_IRQ better... ((p) == MXC_DMA1 && (i) == 1) ? DMA1_CH1_IRQn : \ ((p) == MXC_DMA1 && (i) == 2) ? DMA1_CH2_IRQn : \ ((p) == MXC_DMA1 && (i) == 3) ? DMA1_CH3_IRQn : \ - 0)) + 0)) #else #define MXC_BASE_DMA0 MXC_BASE_DMA0_NS @@ -675,12 +675,12 @@ We may want to handle GET_IRQ better... #define MXC_DMA1 0 /* DMA1 IRQs not usable in Non-Secure state. */ -#define MXC_DMA_CH_GET_IRQ(p, i) \ +#define MXC_DMA_CH_GET_IRQ(p, i) \ ((IRQn_Type)(((p) == MXC_DMA0 && (i) == 0) ? DMA0_CH0_IRQn : \ ((p) == MXC_DMA0 && (i) == 1) ? DMA0_CH1_IRQn : \ ((p) == MXC_DMA0 && (i) == 2) ? DMA0_CH2_IRQn : \ ((p) == MXC_DMA0 && (i) == 3) ? DMA0_CH3_IRQn : \ - 0)) + 0)) #endif // IS_SECURE_ENVIRONMENT #define MXC_DMA_GET_BASE(i) ((i) == MXC_BASE_DMA0 ? 0 : (p) == MXC_BASE_DMA1 ? 1 : -1) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/partition_max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/partition_max32657.h index 5b9fed2bedf..ebefe92c99d 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/partition_max32657.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/partition_max32657.h @@ -30,6 +30,7 @@ #include "max32657.h" +// clang-format off #if IS_SECURE_ENVIRONMENT /* diff --git a/Libraries/PeriphDrivers/Include/MAX32657/dma.h b/Libraries/PeriphDrivers/Include/MAX32657/dma.h index c806d7aae94..b42a98f7519 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/dma.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/dma.h @@ -58,13 +58,11 @@ typedef enum { MXC_DMA_REQUEST_MEMTOMEM = MXC_S_DMA_CTRL_REQUEST_MEMTOMEM, ///< Memory to Memory DMA Request Selection MXC_DMA_REQUEST_SPIRX = MXC_S_DMA_CTRL_REQUEST_SPIRX, ///< SPI Receive DMA Request Selection - MXC_DMA_REQUEST_UARTRX = - MXC_S_DMA_CTRL_REQUEST_UARTRX, ///< UART Receive DMA Request Selection + MXC_DMA_REQUEST_UARTRX = MXC_S_DMA_CTRL_REQUEST_UARTRX, ///< UART Receive DMA Request Selection MXC_DMA_REQUEST_I3CRX = MXC_S_DMA_CTRL_REQUEST_I3CRX, ///< I3C Receive DMA Request Selection MXC_DMA_REQUEST_AESRX = MXC_S_DMA_CTRL_REQUEST_AESRX, ///< AES Receive DMA Request Selection MXC_DMA_REQUEST_SPITX = MXC_S_DMA_CTRL_REQUEST_SPITX, ///< SPI Transmit DMA Request Selection - MXC_DMA_REQUEST_UARTTX = - MXC_S_DMA_CTRL_REQUEST_UARTTX, ///< UART Transmit DMA Request Selection + MXC_DMA_REQUEST_UARTTX = MXC_S_DMA_CTRL_REQUEST_UARTTX, ///< UART Transmit DMA Request Selection MXC_DMA_REQUEST_I3CTX = MXC_S_DMA_CTRL_REQUEST_I3CTX, ///< I3C Transmit DMA Request Selection MXC_DMA_REQUEST_CRCTX = MXC_S_DMA_CTRL_REQUEST_CRCTX, ///< CRC Transmit DMA Request Selection */ MXC_DMA_REQUEST_AESTX = MXC_S_DMA_CTRL_REQUEST_AESTX, ///< AES Transmit DMA Request Selection diff --git a/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h b/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h index 4d0d93621d3..840d2bf2b45 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h @@ -66,42 +66,27 @@ typedef enum { /** @brief System clock disable enumeration. Used in MXC_SYS_ClockDisable and MXC_SYS_ClockEnable functions */ typedef enum { - MXC_SYS_PERIPH_CLOCK_GPIO0 = - MXC_F_GCR_PCLKDIS0_GPIO0_POS, /**< Disable GPIO0 clock */ - MXC_SYS_PERIPH_CLOCK_DMA0 = - MXC_F_GCR_PCLKDIS0_DMA0_POS, /**< Disable DMA0 clock */ - MXC_SYS_PERIPH_CLOCK_SPI = - MXC_F_GCR_PCLKDIS0_SPI_POS, /**< Disable SPI clock */ - MXC_SYS_PERIPH_CLOCK_UART = - MXC_F_GCR_PCLKDIS0_UART_POS, /**< Disable UART0 clock */ - MXC_SYS_PERIPH_CLOCK_I3C = - MXC_F_GCR_PCLKDIS0_I3C_POS, /**< Disable I2C/I3C clock */ - MXC_SYS_PERIPH_CLOCK_TMR0 = - MXC_F_GCR_PCLKDIS0_TMR0_POS, /**< Disable TMR0 clock */ - MXC_SYS_PERIPH_CLOCK_TMR1 = - MXC_F_GCR_PCLKDIS0_TMR1_POS, /**< Disable TMR1 clock */ - MXC_SYS_PERIPH_CLOCK_TMR2 = - MXC_F_GCR_PCLKDIS0_TMR2_POS, /**< Disable TMR2 clock */ - MXC_SYS_PERIPH_CLOCK_TMR3 = - MXC_F_GCR_PCLKDIS0_TMR3_POS, /**< Disable TMR3 clock */ - MXC_SYS_PERIPH_CLOCK_TMR4 = - MXC_F_GCR_PCLKDIS0_TMR4_POS, /**< Disable TMR4 clock */ - MXC_SYS_PERIPH_CLOCK_TMR5 = - MXC_F_GCR_PCLKDIS0_TMR5_POS, /**< Disable TMR4 clock */ + MXC_SYS_PERIPH_CLOCK_GPIO0 = MXC_F_GCR_PCLKDIS0_GPIO0_POS, /**< Disable GPIO0 clock */ + MXC_SYS_PERIPH_CLOCK_DMA0 = MXC_F_GCR_PCLKDIS0_DMA0_POS, /**< Disable DMA0 clock */ + MXC_SYS_PERIPH_CLOCK_SPI = MXC_F_GCR_PCLKDIS0_SPI_POS, /**< Disable SPI clock */ + MXC_SYS_PERIPH_CLOCK_UART = MXC_F_GCR_PCLKDIS0_UART_POS, /**< Disable UART0 clock */ + MXC_SYS_PERIPH_CLOCK_I3C = MXC_F_GCR_PCLKDIS0_I3C_POS, /**< Disable I2C/I3C clock */ + MXC_SYS_PERIPH_CLOCK_TMR0 = MXC_F_GCR_PCLKDIS0_TMR0_POS, /**< Disable TMR0 clock */ + MXC_SYS_PERIPH_CLOCK_TMR1 = MXC_F_GCR_PCLKDIS0_TMR1_POS, /**< Disable TMR1 clock */ + MXC_SYS_PERIPH_CLOCK_TMR2 = MXC_F_GCR_PCLKDIS0_TMR2_POS, /**< Disable TMR2 clock */ + MXC_SYS_PERIPH_CLOCK_TMR3 = MXC_F_GCR_PCLKDIS0_TMR3_POS, /**< Disable TMR3 clock */ + MXC_SYS_PERIPH_CLOCK_TMR4 = MXC_F_GCR_PCLKDIS0_TMR4_POS, /**< Disable TMR4 clock */ + MXC_SYS_PERIPH_CLOCK_TMR5 = MXC_F_GCR_PCLKDIS0_TMR5_POS, /**< Disable TMR4 clock */ /* PCLKDIS1 Below this line we add 32 to separate PCLKDIS0 and PCLKDIS1 */ - MXC_SYS_PERIPH_CLOCK_TRNG = - (MXC_F_GCR_PCLKDIS1_TRNG_POS + 32), /**< Disable TRNG clock */ + MXC_SYS_PERIPH_CLOCK_TRNG = (MXC_F_GCR_PCLKDIS1_TRNG_POS + 32), /**< Disable TRNG clock */ // MXC_SYS_PERIPH_CLOCK_SMPHR = // (MXC_F_GCR_PCLKDIS1_SMPHR_POS + 32), /**< Disable SMPHR clock */ - MXC_SYS_PERIPH_CLOCK_CRC = - (MXC_F_GCR_PCLKDIS1_CRC_POS + 32), /**< Disable CRC clock */ - MXC_SYS_PERIPH_CLOCK_AES = - (MXC_F_GCR_PCLKDIS1_AES_POS + 32), /**< Disable AES clock */ + MXC_SYS_PERIPH_CLOCK_CRC = (MXC_F_GCR_PCLKDIS1_CRC_POS + 32), /**< Disable CRC clock */ + MXC_SYS_PERIPH_CLOCK_AES = (MXC_F_GCR_PCLKDIS1_AES_POS + 32), /**< Disable AES clock */ // MXC_SYS_PERIPH_CLOCK_SPI = // (MXC_F_GCR_PCLKDIS1_SPI_POS + 32), /**< Disable SPI clock */ // TODO(JC): The SPI clock disable is defined in both PCLKDIS0 and PCLKDIS1 - MXC_SYS_PERIPH_CLOCK_WDT = - (MXC_F_GCR_PCLKDIS1_WDT_POS), /**< Disable WDT clock */ + MXC_SYS_PERIPH_CLOCK_WDT = (MXC_F_GCR_PCLKDIS1_WDT_POS), /**< Disable WDT clock */ } mxc_sys_periph_clock_t; /** @brief Enumeration to select System Clock source */ diff --git a/Libraries/PeriphDrivers/Include/MAX32657/uart.h b/Libraries/PeriphDrivers/Include/MAX32657/uart.h index e070b9f2f63..17c77244fba 100644 --- a/Libraries/PeriphDrivers/Include/MAX32657/uart.h +++ b/Libraries/PeriphDrivers/Include/MAX32657/uart.h @@ -368,8 +368,8 @@ unsigned int MXC_UART_ReadRXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, un * * @return See \ref MXC_ERROR_CODES for a list of return values */ -int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, mxc_dma_regs_t *dma, unsigned char *bytes, unsigned int len, - mxc_uart_dma_complete_cb_t callback); +int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, mxc_dma_regs_t *dma, unsigned char *bytes, + unsigned int len, mxc_uart_dma_complete_cb_t callback); /** * @brief Get the number of bytes currently available in the receive FIFO. @@ -403,8 +403,8 @@ unsigned int MXC_UART_WriteTXFIFO(mxc_uart_regs_t *uart, const unsigned char *by * * @return See \ref MXC_ERROR_CODES for a list of return values */ -int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, mxc_dma_regs_t *dma, const unsigned char *bytes, unsigned int len, - mxc_uart_dma_complete_cb_t callback); +int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, mxc_dma_regs_t *dma, const unsigned char *bytes, + unsigned int len, mxc_uart_dma_complete_cb_t callback); /** * @brief Get the amount of free space available in the transmit FIFO. diff --git a/Libraries/PeriphDrivers/Source/AES/aes_revb.c b/Libraries/PeriphDrivers/Source/AES/aes_revb.c index 77ce01370f1..f729102e840 100644 --- a/Libraries/PeriphDrivers/Source/AES/aes_revb.c +++ b/Libraries/PeriphDrivers/Source/AES/aes_revb.c @@ -386,7 +386,8 @@ int MXC_AES_RevB_GenericAsync(mxc_aes_revb_regs_t *aes, mxc_aes_revb_req_t *req, aes->ctrl |= MXC_F_AES_REVB_CTRL_DMA_RX_EN; //Enable AES DMA aes->ctrl |= MXC_F_AES_REVB_CTRL_DMA_TX_EN; //Enable AES DMA - if (MXC_AES_RevB_TXDMAConfig(dma_state.inputText, dma_state.remain, dma_state.dma) != E_NO_ERROR) { + if (MXC_AES_RevB_TXDMAConfig(dma_state.inputText, dma_state.remain, dma_state.dma) != + E_NO_ERROR) { return E_BAD_PARAM; } diff --git a/Libraries/PeriphDrivers/Source/DMA/dma_me30.c b/Libraries/PeriphDrivers/Source/DMA/dma_me30.c index d0359eaa1da..7ae6aaddf1b 100644 --- a/Libraries/PeriphDrivers/Source/DMA/dma_me30.c +++ b/Libraries/PeriphDrivers/Source/DMA/dma_me30.c @@ -157,7 +157,8 @@ void MXC_DMA_Handler(mxc_dma_regs_t *dma) MXC_DMA_RevA_Handler((mxc_dma_reva_regs_t *)dma); } -int MXC_DMA_MemCpy(mxc_dma_regs_t *dma, void *dest, void *src, int len, mxc_dma_complete_cb_t callback) +int MXC_DMA_MemCpy(mxc_dma_regs_t *dma, void *dest, void *src, int len, + mxc_dma_complete_cb_t callback) { return MXC_DMA_RevA_MemCpy((mxc_dma_reva_regs_t *)dma, dest, src, len, callback); } diff --git a/Libraries/PeriphDrivers/Source/SPI/spi_me30.c b/Libraries/PeriphDrivers/Source/SPI/spi_me30.c index 416b3ba8685..ac48b4f2b2d 100644 --- a/Libraries/PeriphDrivers/Source/SPI/spi_me30.c +++ b/Libraries/PeriphDrivers/Source/SPI/spi_me30.c @@ -71,18 +71,18 @@ int MXC_SPI_Init(mxc_spi_regs_t *spi, int masterMode, int quadModeUsed, int numS #if (TARGET != MAX78000 || TARGET_NUM == 32655) - //Define pins - if (pins.ss1) { - gpio_cfg_spi.mask = MXC_GPIO_PIN_26; - gpio_cfg_spi.func = MXC_GPIO_FUNC_ALT2; - MXC_GPIO_Config(&gpio_cfg_spi); - } + //Define pins + if (pins.ss1) { + gpio_cfg_spi.mask = MXC_GPIO_PIN_26; + gpio_cfg_spi.func = MXC_GPIO_FUNC_ALT2; + MXC_GPIO_Config(&gpio_cfg_spi); + } - if (pins.ss2) { - gpio_cfg_spi.func = MXC_GPIO_FUNC_ALT2; - gpio_cfg_spi.mask = MXC_GPIO_PIN_27; - MXC_GPIO_Config(&gpio_cfg_spi); - } + if (pins.ss2) { + gpio_cfg_spi.func = MXC_GPIO_FUNC_ALT2; + gpio_cfg_spi.mask = MXC_GPIO_PIN_27; + MXC_GPIO_Config(&gpio_cfg_spi); + } #endif //clear mask @@ -150,7 +150,7 @@ int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t *spi) // TODO(ME30): Validate this logic int sys_clk = (MXC_GCR->clkctrl & MXC_F_GCR_CLKCTRL_SYSCLK_SEL) >> - MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS; + MXC_F_GCR_CLKCTRL_SYSCLK_SEL_POS; switch (sys_clk) { case MXC_SYS_CLOCK_IPO: retval = IPO_FREQ; @@ -164,14 +164,14 @@ int MXC_SPI_GetPeripheralClock(mxc_spi_regs_t *spi) case MXC_SYS_CLOCK_ERTCO: retval = ERTCO_FREQ; break; - // TODO(ME30): EXTCLK definition is missing from registers - // case MXC_SYS_CLOCK_EXTCLK: - // retval = EXTCLK_FREQ; - // break; + // TODO(ME30): EXTCLK definition is missing from registers + // case MXC_SYS_CLOCK_EXTCLK: + // retval = EXTCLK_FREQ; + // break; #if TARGET_NUM == 32655 || TARGET_NUM == 32680 - case MXC_SYS_CLOCK_ERFO: - retval = ERFO_FREQ; - break; + case MXC_SYS_CLOCK_ERFO: + retval = ERFO_FREQ; + break; #endif default: return E_BAD_STATE; diff --git a/Libraries/PeriphDrivers/Source/SYS/sys_me30.c b/Libraries/PeriphDrivers/Source/SYS/sys_me30.c index 78e09ee40bc..c66b9bceed8 100644 --- a/Libraries/PeriphDrivers/Source/SYS/sys_me30.c +++ b/Libraries/PeriphDrivers/Source/SYS/sys_me30.c @@ -225,11 +225,11 @@ int MXC_SYS_ClockSourceEnable(mxc_sys_system_clock_t clock) return MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_IBRO_RDY); break; - // TODO(ME30): EXTCLK is missing from register definitions - // case MXC_SYS_CLOCK_EXTCLK: - // // No "RDY" bit to monitor, so just configure the GPIO - // return MXC_GPIO_Config(&gpio_cfg_extclk); - // break; + // TODO(ME30): EXTCLK is missing from register definitions + // case MXC_SYS_CLOCK_EXTCLK: + // // No "RDY" bit to monitor, so just configure the GPIO + // return MXC_GPIO_Config(&gpio_cfg_extclk); + // break; case MXC_SYS_CLOCK_INRO: // The 80k clock is always enabled @@ -242,7 +242,7 @@ int MXC_SYS_ClockSourceEnable(mxc_sys_system_clock_t clock) /* Initialize kickstart circuit Select Kick start circuit clock source- IPO/ISO */ - // TODO(ME30): MXC_FCR missing ERFOKS definition + // TODO(ME30): MXC_FCR missing ERFOKS definition // MXC_FCR->erfoks = ((MXC_S_FCR_ERFOKS_KSCLKSEL_ISO) // /* Set Drive strengh - 0x1,0x2,0x3 */ // | ((0x1) << MXC_F_FCR_ERFOKS_KSERFODRIVER_POS) @@ -290,16 +290,16 @@ int MXC_SYS_ClockSourceDisable(mxc_sys_system_clock_t clock) MXC_GCR->clkctrl &= ~MXC_F_GCR_CLKCTRL_IBRO_EN; break; - // TODO(ME30): Missing EXTCLK register definition - // case MXC_SYS_CLOCK_EXTCLK: - // /* - // There's not a great way to disable the external clock. - // Deinitializing the GPIO here may have unintended consequences - // for application code. - // Selecting a different system clock source is sufficient - // to "disable" the EXT_CLK source. - // */ - // break; + // TODO(ME30): Missing EXTCLK register definition + // case MXC_SYS_CLOCK_EXTCLK: + // /* + // There's not a great way to disable the external clock. + // Deinitializing the GPIO here may have unintended consequences + // for application code. + // Selecting a different system clock source is sufficient + // to "disable" the EXT_CLK source. + // */ + // break; case MXC_SYS_CLOCK_INRO: // The 80k clock is always enabled @@ -393,21 +393,21 @@ int MXC_SYS_Clock_Select(mxc_sys_system_clock_t clock) break; - // TODO(ME30): Missing EXTCLK register definition - // case MXC_SYS_CLOCK_EXTCLK: - // /* - // There's not "EXT_CLK RDY" bit for the ME17, so we'll - // blindly enable (configure GPIO) the external clock every time. - // */ - // err = MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_EXTCLK); - // if (err) - // return err; - - // // Set EXT clock as System Clock - // MXC_SETFIELD(MXC_GCR->clkctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL, - // MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK); - - // break; + // TODO(ME30): Missing EXTCLK register definition + // case MXC_SYS_CLOCK_EXTCLK: + // /* + // There's not "EXT_CLK RDY" bit for the ME17, so we'll + // blindly enable (configure GPIO) the external clock every time. + // */ + // err = MXC_SYS_ClockSourceEnable(MXC_SYS_CLOCK_EXTCLK); + // if (err) + // return err; + + // // Set EXT clock as System Clock + // MXC_SETFIELD(MXC_GCR->clkctrl, MXC_F_GCR_CLKCTRL_SYSCLK_SEL, + // MXC_S_GCR_CLKCTRL_SYSCLK_SEL_EXTCLK); + + // break; case MXC_SYS_CLOCK_ERFO: diff --git a/Libraries/PeriphDrivers/Source/UART/uart_ai85.c b/Libraries/PeriphDrivers/Source/UART/uart_ai85.c index 722bf8881b2..8a10a82604e 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_ai85.c +++ b/Libraries/PeriphDrivers/Source/UART/uart_ai85.c @@ -328,7 +328,8 @@ int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned break; } - return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, config); + return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, + config); } unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart) @@ -371,7 +372,8 @@ int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, const unsigned char *bytes, u break; } - return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, config); + return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, + config); } unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart) diff --git a/Libraries/PeriphDrivers/Source/UART/uart_ai87.c b/Libraries/PeriphDrivers/Source/UART/uart_ai87.c index 3ec7f5b6241..b75fbdf1411 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_ai87.c +++ b/Libraries/PeriphDrivers/Source/UART/uart_ai87.c @@ -343,7 +343,8 @@ int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned break; } - return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, config); + return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, + config); } unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart) @@ -382,7 +383,8 @@ int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, const unsigned char *bytes, u break; } - return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, config); + return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, + config); } unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart) diff --git a/Libraries/PeriphDrivers/Source/UART/uart_me12.c b/Libraries/PeriphDrivers/Source/UART/uart_me12.c index 801ac966c81..d010911bd5b 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_me12.c +++ b/Libraries/PeriphDrivers/Source/UART/uart_me12.c @@ -259,7 +259,8 @@ int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned break; } - return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, config); + return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, + config); } unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart) @@ -291,7 +292,8 @@ int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, const unsigned char *bytes, u break; } - return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, config); + return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, + config); } unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart) diff --git a/Libraries/PeriphDrivers/Source/UART/uart_me15.c b/Libraries/PeriphDrivers/Source/UART/uart_me15.c index 142963f7b73..ec12f57999d 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_me15.c +++ b/Libraries/PeriphDrivers/Source/UART/uart_me15.c @@ -398,7 +398,8 @@ int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned break; } - return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, config); + return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, + config); } unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart) @@ -437,7 +438,8 @@ int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, const unsigned char *bytes, u break; } - return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, config); + return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, + config); } unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart) diff --git a/Libraries/PeriphDrivers/Source/UART/uart_me16.c b/Libraries/PeriphDrivers/Source/UART/uart_me16.c index 86e6466afa5..0390362810b 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_me16.c +++ b/Libraries/PeriphDrivers/Source/UART/uart_me16.c @@ -339,7 +339,8 @@ int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned break; } - return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, config); + return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, + config); } unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart) @@ -374,7 +375,8 @@ int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, const unsigned char *bytes, u break; } - return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, config); + return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, + config); } unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart) diff --git a/Libraries/PeriphDrivers/Source/UART/uart_me17.c b/Libraries/PeriphDrivers/Source/UART/uart_me17.c index 4fea36b300d..3344a6e217a 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_me17.c +++ b/Libraries/PeriphDrivers/Source/UART/uart_me17.c @@ -364,7 +364,8 @@ int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned break; } - return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, config); + return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, + config); } unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart) @@ -406,7 +407,8 @@ int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, const unsigned char *bytes, u break; } - return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, config); + return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, + config); } unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart) diff --git a/Libraries/PeriphDrivers/Source/UART/uart_me18.c b/Libraries/PeriphDrivers/Source/UART/uart_me18.c index 88a19b95ab9..cae32b5e77b 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_me18.c +++ b/Libraries/PeriphDrivers/Source/UART/uart_me18.c @@ -404,7 +404,8 @@ int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned break; } - return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, config); + return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, + config); } unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart) @@ -446,7 +447,8 @@ int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, const unsigned char *bytes, u break; } - return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, config); + return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, + config); } unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart) diff --git a/Libraries/PeriphDrivers/Source/UART/uart_me21.c b/Libraries/PeriphDrivers/Source/UART/uart_me21.c index d3ef357bb3f..d4bbfc54589 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_me21.c +++ b/Libraries/PeriphDrivers/Source/UART/uart_me21.c @@ -437,7 +437,8 @@ int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned break; } - return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, config); + return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, + config); } unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart) @@ -475,7 +476,8 @@ int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigne break; } - return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, config); + return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, + config); } unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart) diff --git a/Libraries/PeriphDrivers/Source/UART/uart_me30.c b/Libraries/PeriphDrivers/Source/UART/uart_me30.c index 7e9655ef80e..93725f415bc 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_me30.c +++ b/Libraries/PeriphDrivers/Source/UART/uart_me30.c @@ -202,8 +202,8 @@ unsigned int MXC_UART_ReadRXFIFO(mxc_uart_regs_t *uart, unsigned char *bytes, un return MXC_UART_RevB_ReadRXFIFO((mxc_uart_revb_regs_t *)uart, bytes, len); } -int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, mxc_dma_regs_t *dma, unsigned char *bytes, unsigned int len, - mxc_uart_dma_complete_cb_t callback) +int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, mxc_dma_regs_t *dma, unsigned char *bytes, + unsigned int len, mxc_uart_dma_complete_cb_t callback) { mxc_dma_config_t config; @@ -219,7 +219,8 @@ int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, mxc_dma_regs_t *dma, unsigned break; } - return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, dma, bytes, len, callback, config); + return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, dma, bytes, len, callback, + config); } unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart) @@ -233,8 +234,8 @@ unsigned int MXC_UART_WriteTXFIFO(mxc_uart_regs_t *uart, const unsigned char *by return MXC_UART_RevB_WriteTXFIFO((mxc_uart_revb_regs_t *)uart, bytes, len); } -int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, mxc_dma_regs_t *dma, const unsigned char *bytes, unsigned int len, - mxc_uart_dma_complete_cb_t callback) +int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, mxc_dma_regs_t *dma, const unsigned char *bytes, + unsigned int len, mxc_uart_dma_complete_cb_t callback) { mxc_dma_config_t config; @@ -249,7 +250,8 @@ int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, mxc_dma_regs_t *dma, const un break; } - return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, dma, bytes, len, callback, config); + return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, dma, bytes, len, callback, + config); } unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart) diff --git a/Libraries/PeriphDrivers/Source/UART/uart_me55.c b/Libraries/PeriphDrivers/Source/UART/uart_me55.c index b7859c068f1..de15b76f0ef 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_me55.c +++ b/Libraries/PeriphDrivers/Source/UART/uart_me55.c @@ -298,7 +298,8 @@ int MXC_UART_ReadRXFIFODMA(mxc_uart_regs_t *uart, unsigned char *bytes, unsigned break; } - return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, config); + return MXC_UART_RevB_ReadRXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, + config); } unsigned int MXC_UART_GetRXFIFOAvailable(mxc_uart_regs_t *uart) @@ -340,7 +341,8 @@ int MXC_UART_WriteTXFIFODMA(mxc_uart_regs_t *uart, const unsigned char *bytes, u break; } - return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, config); + return MXC_UART_RevB_WriteTXFIFODMA((mxc_uart_revb_regs_t *)uart, MXC_DMA, bytes, len, callback, + config); } unsigned int MXC_UART_GetTXFIFOAvailable(mxc_uart_regs_t *uart) diff --git a/Libraries/PeriphDrivers/Source/UART/uart_reva.c b/Libraries/PeriphDrivers/Source/UART/uart_reva.c index 3c3ccf8a073..f7ce7d44693 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_reva.c +++ b/Libraries/PeriphDrivers/Source/UART/uart_reva.c @@ -539,7 +539,7 @@ void MXC_UART_RevA_DMA_SetupAutoHandlers(mxc_dma_regs_t *dma_instance, unsigned MXC_NVIC_SetVector(MXC_DMA_CH_GET_IRQ(channel), MXC_UART_RevA_DMA1_Handler); } #else - NVIC_EnableIRQ(MXC_DMA_CH_GET_IRQ(channel)); + NVIC_EnableIRQ(MXC_DMA_CH_GET_IRQ(channel)); // Only one DMA instance, we can point direct to MXC_DMA_Handler MXC_NVIC_SetVector(MXC_DMA_CH_GET_IRQ(channel), MXC_DMA_Handler); diff --git a/Libraries/PeriphDrivers/Source/UART/uart_revb.c b/Libraries/PeriphDrivers/Source/UART/uart_revb.c index 22f2dc503ba..1888f35a9d0 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_revb.c +++ b/Libraries/PeriphDrivers/Source/UART/uart_revb.c @@ -828,7 +828,6 @@ int MXC_UART_RevB_SetAutoDMAHandlers(mxc_uart_revb_regs_t *uart, bool enable) return E_NO_ERROR; } - #if (MXC_DMA_INSTANCES > 1) void MXC_UART_RevA_DMA0_Handler(void) @@ -862,7 +861,7 @@ void MXC_UART_RevB_DMA_SetupAutoHandlers(mxc_dma_regs_t *dma_instance, unsigned MXC_NVIC_SetVector(MXC_DMA_CH_GET_IRQ(dma_instance, channel), MXC_UART_RevA_DMA1_Handler); } #else - NVIC_EnableIRQ(MXC_DMA_CH_GET_IRQ(channel)); + NVIC_EnableIRQ(MXC_DMA_CH_GET_IRQ(channel)); // Only one DMA instance, we can point direct to MXC_DMA_Handler MXC_NVIC_SetVector(MXC_DMA_CH_GET_IRQ(channel), MXC_DMA_Handler); @@ -874,7 +873,6 @@ void MXC_UART_RevB_DMA_SetupAutoHandlers(mxc_dma_regs_t *dma_instance, unsigned #endif // __arm__ } - int MXC_UART_RevB_SetTXDMAChannel(mxc_uart_revb_regs_t *uart, unsigned int channel) { int n = MXC_UART_GET_IDX((mxc_uart_regs_t *)uart); @@ -907,7 +905,8 @@ int MXC_UART_RevB_GetRXDMAChannel(mxc_uart_revb_regs_t *uart) return states[n].channelRx; } -int MXC_UART_RevB_ReadRXFIFODMA(mxc_uart_revb_regs_t *uart, mxc_dma_regs_t *dma, unsigned char *bytes, unsigned int len, +int MXC_UART_RevB_ReadRXFIFODMA(mxc_uart_revb_regs_t *uart, mxc_dma_regs_t *dma, + unsigned char *bytes, unsigned int len, mxc_uart_dma_complete_cb_t callback, mxc_dma_config_t config) { uint8_t channel; @@ -964,9 +963,9 @@ int MXC_UART_RevB_ReadRXFIFODMA(mxc_uart_revb_regs_t *uart, mxc_dma_regs_t *dma, return E_NO_ERROR; } -int MXC_UART_RevB_WriteTXFIFODMA(mxc_uart_revb_regs_t *uart, mxc_dma_regs_t *dma, const unsigned char *bytes, - unsigned int len, mxc_uart_dma_complete_cb_t callback, - mxc_dma_config_t config) +int MXC_UART_RevB_WriteTXFIFODMA(mxc_uart_revb_regs_t *uart, mxc_dma_regs_t *dma, + const unsigned char *bytes, unsigned int len, + mxc_uart_dma_complete_cb_t callback, mxc_dma_config_t config) { uint8_t channel; mxc_dma_srcdst_t srcdst; @@ -1082,8 +1081,8 @@ int MXC_UART_RevB_TransactionDMA(mxc_uart_revb_req_t *req, mxc_dma_regs_t *dma) if ((req->rxData != NULL) && (req->rxLen)) { states[uart_num].rx_req = req; #if (MXC_DMA_INSTANCES > 1) - if (MXC_UART_ReadRXFIFODMA((mxc_uart_regs_t *)(req->uart), dma, req->rxData, req->rxLen, NULL) != - E_NO_ERROR) { + if (MXC_UART_ReadRXFIFODMA((mxc_uart_regs_t *)(req->uart), dma, req->rxData, req->rxLen, + NULL) != E_NO_ERROR) { #else if (MXC_UART_ReadRXFIFODMA((mxc_uart_regs_t *)(req->uart), req->rxData, req->rxLen, NULL) != E_NO_ERROR) { diff --git a/Libraries/PeriphDrivers/Source/UART/uart_revb.h b/Libraries/PeriphDrivers/Source/UART/uart_revb.h index cd9f74e2082..07178392176 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_revb.h +++ b/Libraries/PeriphDrivers/Source/UART/uart_revb.h @@ -74,14 +74,15 @@ int MXC_UART_RevB_Read(mxc_uart_revb_regs_t *uart, uint8_t *buffer, int *len); int MXC_UART_RevB_Write(mxc_uart_revb_regs_t *uart, const uint8_t *byte, int *len); unsigned int MXC_UART_RevB_ReadRXFIFO(mxc_uart_revb_regs_t *uart, unsigned char *bytes, unsigned int len); -int MXC_UART_RevB_ReadRXFIFODMA(mxc_uart_revb_regs_t *uart, mxc_dma_regs_t *dma, unsigned char *bytes, unsigned int len, +int MXC_UART_RevB_ReadRXFIFODMA(mxc_uart_revb_regs_t *uart, mxc_dma_regs_t *dma, + unsigned char *bytes, unsigned int len, mxc_uart_dma_complete_cb_t callback, mxc_dma_config_t config); unsigned int MXC_UART_RevB_GetRXFIFOAvailable(mxc_uart_revb_regs_t *uart); unsigned int MXC_UART_RevB_WriteTXFIFO(mxc_uart_revb_regs_t *uart, const unsigned char *bytes, unsigned int len); -int MXC_UART_RevB_WriteTXFIFODMA(mxc_uart_revb_regs_t *uart, mxc_dma_regs_t *dma, const unsigned char *bytes, - unsigned int len, mxc_uart_dma_complete_cb_t callback, - mxc_dma_config_t config); +int MXC_UART_RevB_WriteTXFIFODMA(mxc_uart_revb_regs_t *uart, mxc_dma_regs_t *dma, + const unsigned char *bytes, unsigned int len, + mxc_uart_dma_complete_cb_t callback, mxc_dma_config_t config); unsigned int MXC_UART_RevB_GetTXFIFOAvailable(mxc_uart_revb_regs_t *uart); int MXC_UART_RevB_ClearRXFIFO(mxc_uart_revb_regs_t *uart); int MXC_UART_RevB_ClearTXFIFO(mxc_uart_revb_regs_t *uart); diff --git a/Libraries/PeriphDrivers/Source/WDT/wdt_me30.c b/Libraries/PeriphDrivers/Source/WDT/wdt_me30.c index 8c1af1514bf..00ba3952860 100644 --- a/Libraries/PeriphDrivers/Source/WDT/wdt_me30.c +++ b/Libraries/PeriphDrivers/Source/WDT/wdt_me30.c @@ -43,8 +43,7 @@ int MXC_WDT_Shutdown(mxc_wdt_regs_t *wdt) { if (wdt == MXC_WDT) { MXC_SYS_ClockDisable(MXC_SYS_PERIPH_CLOCK_WDT); - } - else { + } else { return E_BAD_PARAM; } From 471b78474a7af5c598d0d230ba6518f39258abd9 Mon Sep 17 00:00:00 2001 From: Woo Date: Sat, 11 May 2024 17:16:14 -0500 Subject: [PATCH 82/93] Fix clang format comment --- .../CMSIS/Device/Maxim/MAX32657/Include/partition_max32657.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/partition_max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/partition_max32657.h index ebefe92c99d..04d1fb0590e 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/partition_max32657.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/partition_max32657.h @@ -1,4 +1,4 @@ -/*************************************************************************//** +/***************************************************************************** * @file partition_max32657.h * @brief CMSIS-Core(M) Device Initial Setup for Secure/Non-Secure Zones for * MAX32657 From ef44e4de19bed4e9349b2f9f7196ffde5656f832 Mon Sep 17 00:00:00 2001 From: Woo Date: Sat, 11 May 2024 17:20:53 -0500 Subject: [PATCH 83/93] Fix linter errors --- .../Device/Maxim/MAX32657/Include/partition_max32657.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/partition_max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/partition_max32657.h index 04d1fb0590e..a948716c809 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/partition_max32657.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/partition_max32657.h @@ -25,8 +25,8 @@ * limitations under the License. */ -#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_SOURCE_GCC_PARTITION_MAX32657_H_ -#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_SOURCE_GCC_PARTITION_MAX32657_H_ +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_PARTITION_MAX32657_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_PARTITION_MAX32657_H_ #include "max32657.h" @@ -1283,4 +1283,4 @@ __STATIC_INLINE void TZ_SAU_Setup (void) #endif // IS_SECURE_EVIRONMENT -#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_SOURCE_PARTITION_MAX32657_H_ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_PARTITION_MAX32657_H_ From 7ec3cd2ecaeb5890eed8c0e490d5a01386505111 Mon Sep 17 00:00:00 2001 From: Woo Date: Sat, 11 May 2024 17:28:33 -0500 Subject: [PATCH 84/93] Fix linter errors and exclude partition CMSIS files --- .github/workflows/linter.yml | 4 ++-- Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/.github/workflows/linter.yml b/.github/workflows/linter.yml index 3a8545c52b9..e07b7db3d28 100644 --- a/.github/workflows/linter.yml +++ b/.github/workflows/linter.yml @@ -62,7 +62,7 @@ jobs: # Checkout the code base # ########################## - name: Checkout Code - uses: actions/checkout@v3 + uses: actions/checkout@v4 with: # Full git history is needed to get a proper list of changed files within `super-linter` fetch-depth: 0 @@ -78,7 +78,7 @@ jobs: GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} # Skip autogenerated register files and internal use board files - FILTER_REGEX_EXCLUDE: (.*\/Libraries\/((CMSIS\/Device\/Maxim\/[^\/]*\/Include)|(PeriphDrivers\/Source\/[^\/]*))\/[^\/]*_regs\.h)|(.*\/Libraries\/Boards\/[^\/]*\/(BCB|Emulator|Simulation|ROM)[^\/]*\/.*)|(.*\/Examples\/[^\/]*\/Display\/lvgl-8\.0\.2\/.*)|(.*\/Examples\/[^\/]*\/Demo\/lv_conf.h)|(.*\/Libraries\/CMSIS\/5.9.0\/.*)|(.*\/Libraries\/CMSIS\/Include\/.*)|(.*\/Libraries\/Cordio\/.*)|(.*\/Libraries\/SDHC\/.*)|(.*\/Libraries\/lwIP\/.*)|(.*\/Examples\/[^\/]*\/CNN\/.*) + FILTER_REGEX_EXCLUDE: (.*\/Libraries\/(CMSIS\/Device\/Maxim\/[^\/]*\/Include)\/[^\/]partitions_*\.h)|(.*\/Libraries\/((CMSIS\/Device\/Maxim\/[^\/]*\/Include)|(PeriphDrivers\/Source\/[^\/]*))\/[^\/]*_regs\.h)|(.*\/Libraries\/Boards\/[^\/]*\/(BCB|Emulator|Simulation|ROM)[^\/]*\/.*)|(.*\/Examples\/[^\/]*\/Display\/lvgl-8\.0\.2\/.*)|(.*\/Examples\/[^\/]*\/Demo\/lv_conf.h)|(.*\/Libraries\/CMSIS\/5.9.0\/.*)|(.*\/Libraries\/CMSIS\/Include\/.*)|(.*\/Libraries\/Cordio\/.*)|(.*\/Libraries\/SDHC\/.*)|(.*\/Libraries\/lwIP\/.*)|(.*\/Examples\/[^\/]*\/CNN\/.*) # Explicity turn off all linters except CPP # SuperLinter Documentation says all we need to do is turn on the ones we want diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h index 7ef1eeace46..1472891893f 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h @@ -904,4 +904,4 @@ We may want to handle GET_IRQ better... #define SCB_CPACR_CP11_Pos 22 /*!< SCB CPACR: Coprocessor 11 Position */ #define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /*!< SCB CPACR: Coprocessor 11 Mask */ -#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX326657_INCLUDE_MAX32657_H_ +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_MAX32657_H_ From 68995039c9905bc7c137ffb46dcc7e12b09f8a51 Mon Sep 17 00:00:00 2001 From: Woo Date: Sat, 11 May 2024 17:37:52 -0500 Subject: [PATCH 85/93] Fix regex in linter and linter fix for pins_me30.c --- .github/workflows/linter.yml | 2 +- Libraries/PeriphDrivers/Source/SYS/pins_me30.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/linter.yml b/.github/workflows/linter.yml index e07b7db3d28..04ed2b54263 100644 --- a/.github/workflows/linter.yml +++ b/.github/workflows/linter.yml @@ -78,7 +78,7 @@ jobs: GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} # Skip autogenerated register files and internal use board files - FILTER_REGEX_EXCLUDE: (.*\/Libraries\/(CMSIS\/Device\/Maxim\/[^\/]*\/Include)\/[^\/]partitions_*\.h)|(.*\/Libraries\/((CMSIS\/Device\/Maxim\/[^\/]*\/Include)|(PeriphDrivers\/Source\/[^\/]*))\/[^\/]*_regs\.h)|(.*\/Libraries\/Boards\/[^\/]*\/(BCB|Emulator|Simulation|ROM)[^\/]*\/.*)|(.*\/Examples\/[^\/]*\/Display\/lvgl-8\.0\.2\/.*)|(.*\/Examples\/[^\/]*\/Demo\/lv_conf.h)|(.*\/Libraries\/CMSIS\/5.9.0\/.*)|(.*\/Libraries\/CMSIS\/Include\/.*)|(.*\/Libraries\/Cordio\/.*)|(.*\/Libraries\/SDHC\/.*)|(.*\/Libraries\/lwIP\/.*)|(.*\/Examples\/[^\/]*\/CNN\/.*) + FILTER_REGEX_EXCLUDE: (.*\/Libraries\/CMSIS\/Device\/Maxim\/[^\/]*\/Include\/[^\/]*\/partitions_*\.h)|(.*\/Libraries\/((CMSIS\/Device\/Maxim\/[^\/]*\/Include)|(PeriphDrivers\/Source\/[^\/]*))\/[^\/]*_regs\.h)|(.*\/Libraries\/Boards\/[^\/]*\/(BCB|Emulator|Simulation|ROM)[^\/]*\/.*)|(.*\/Examples\/[^\/]*\/Display\/lvgl-8\.0\.2\/.*)|(.*\/Examples\/[^\/]*\/Demo\/lv_conf.h)|(.*\/Libraries\/CMSIS\/5.9.0\/.*)|(.*\/Libraries\/CMSIS\/Include\/.*)|(.*\/Libraries\/Cordio\/.*)|(.*\/Libraries\/SDHC\/.*)|(.*\/Libraries\/lwIP\/.*)|(.*\/Examples\/[^\/]*\/CNN\/.*) # Explicity turn off all linters except CPP # SuperLinter Documentation says all we need to do is turn on the ones we want diff --git a/Libraries/PeriphDrivers/Source/SYS/pins_me30.c b/Libraries/PeriphDrivers/Source/SYS/pins_me30.c index 8bd7a5be81f..b7fd798dab0 100644 --- a/Libraries/PeriphDrivers/Source/SYS/pins_me30.c +++ b/Libraries/PeriphDrivers/Source/SYS/pins_me30.c @@ -78,4 +78,4 @@ const mxc_gpio_cfg_t gpio_cfg_spi_ts0 = { MXC_GPIO0, MXC_GPIO_PIN_3, MXC_GPIO_FU const mxc_gpio_cfg_t gpio_cfg_spi_ts1 = { MXC_GPIO0, MXC_GPIO_PIN_7, MXC_GPIO_FUNC_ALT1, MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; const mxc_gpio_cfg_t gpio_cfg_spi_ts2 = { MXC_GPIO0, MXC_GPIO_PIN_8, MXC_GPIO_FUNC_ALT1, - MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; \ No newline at end of file + MXC_GPIO_PAD_NONE, MXC_GPIO_VSSEL_VDDIO, MXC_GPIO_DRVSTR_0 }; From fd63b4a94a0e87c1218a51e0ae9c8be0475e4a0b Mon Sep 17 00:00:00 2001 From: Woo Date: Sat, 11 May 2024 17:41:29 -0500 Subject: [PATCH 86/93] Fix regex --- .github/workflows/linter.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/linter.yml b/.github/workflows/linter.yml index 04ed2b54263..5f411fe8db2 100644 --- a/.github/workflows/linter.yml +++ b/.github/workflows/linter.yml @@ -78,7 +78,7 @@ jobs: GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} # Skip autogenerated register files and internal use board files - FILTER_REGEX_EXCLUDE: (.*\/Libraries\/CMSIS\/Device\/Maxim\/[^\/]*\/Include\/[^\/]*\/partitions_*\.h)|(.*\/Libraries\/((CMSIS\/Device\/Maxim\/[^\/]*\/Include)|(PeriphDrivers\/Source\/[^\/]*))\/[^\/]*_regs\.h)|(.*\/Libraries\/Boards\/[^\/]*\/(BCB|Emulator|Simulation|ROM)[^\/]*\/.*)|(.*\/Examples\/[^\/]*\/Display\/lvgl-8\.0\.2\/.*)|(.*\/Examples\/[^\/]*\/Demo\/lv_conf.h)|(.*\/Libraries\/CMSIS\/5.9.0\/.*)|(.*\/Libraries\/CMSIS\/Include\/.*)|(.*\/Libraries\/Cordio\/.*)|(.*\/Libraries\/SDHC\/.*)|(.*\/Libraries\/lwIP\/.*)|(.*\/Examples\/[^\/]*\/CNN\/.*) + FILTER_REGEX_EXCLUDE: (.*\/Libraries\/CMSIS\/Device\/Maxim\/[^\/]*\/Include\/[^\/]*\/partitions_[^\/]*\.h)|(.*\/Libraries\/((CMSIS\/Device\/Maxim\/[^\/]*\/Include)|(PeriphDrivers\/Source\/[^\/]*))\/[^\/]*_regs\.h)|(.*\/Libraries\/Boards\/[^\/]*\/(BCB|Emulator|Simulation|ROM)[^\/]*\/.*)|(.*\/Examples\/[^\/]*\/Display\/lvgl-8\.0\.2\/.*)|(.*\/Examples\/[^\/]*\/Demo\/lv_conf.h)|(.*\/Libraries\/CMSIS\/5.9.0\/.*)|(.*\/Libraries\/CMSIS\/Include\/.*)|(.*\/Libraries\/Cordio\/.*)|(.*\/Libraries\/SDHC\/.*)|(.*\/Libraries\/lwIP\/.*)|(.*\/Examples\/[^\/]*\/CNN\/.*) # Explicity turn off all linters except CPP # SuperLinter Documentation says all we need to do is turn on the ones we want From 4e5e0716362671d9db64f6db8c509525da72a433 Mon Sep 17 00:00:00 2001 From: Woo Date: Sat, 11 May 2024 17:48:55 -0500 Subject: [PATCH 87/93] Revise regex --- .github/workflows/linter.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/linter.yml b/.github/workflows/linter.yml index 5f411fe8db2..82683c9d2f7 100644 --- a/.github/workflows/linter.yml +++ b/.github/workflows/linter.yml @@ -78,7 +78,7 @@ jobs: GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} # Skip autogenerated register files and internal use board files - FILTER_REGEX_EXCLUDE: (.*\/Libraries\/CMSIS\/Device\/Maxim\/[^\/]*\/Include\/[^\/]*\/partitions_[^\/]*\.h)|(.*\/Libraries\/((CMSIS\/Device\/Maxim\/[^\/]*\/Include)|(PeriphDrivers\/Source\/[^\/]*))\/[^\/]*_regs\.h)|(.*\/Libraries\/Boards\/[^\/]*\/(BCB|Emulator|Simulation|ROM)[^\/]*\/.*)|(.*\/Examples\/[^\/]*\/Display\/lvgl-8\.0\.2\/.*)|(.*\/Examples\/[^\/]*\/Demo\/lv_conf.h)|(.*\/Libraries\/CMSIS\/5.9.0\/.*)|(.*\/Libraries\/CMSIS\/Include\/.*)|(.*\/Libraries\/Cordio\/.*)|(.*\/Libraries\/SDHC\/.*)|(.*\/Libraries\/lwIP\/.*)|(.*\/Examples\/[^\/]*\/CNN\/.*) + FILTER_REGEX_EXCLUDE: (.*\/Libraries\/CMSIS\/Device\/Maxim\/.*\/Include\/partitions_.*\.h)|(.*\/Libraries\/((CMSIS\/Device\/Maxim\/[^\/]*\/Include)|(PeriphDrivers\/Source\/[^\/]*))\/[^\/]*_regs\.h)|(.*\/Libraries\/Boards\/[^\/]*\/(BCB|Emulator|Simulation|ROM)[^\/]*\/.*)|(.*\/Examples\/[^\/]*\/Display\/lvgl-8\.0\.2\/.*)|(.*\/Examples\/[^\/]*\/Demo\/lv_conf.h)|(.*\/Libraries\/CMSIS\/5.9.0\/.*)|(.*\/Libraries\/CMSIS\/Include\/.*)|(.*\/Libraries\/Cordio\/.*)|(.*\/Libraries\/SDHC\/.*)|(.*\/Libraries\/lwIP\/.*)|(.*\/Examples\/[^\/]*\/CNN\/.*) # Explicity turn off all linters except CPP # SuperLinter Documentation says all we need to do is turn on the ones we want From 42af8da6f59e1fffe11bfb92df1dd11ad34882ce Mon Sep 17 00:00:00 2001 From: Woo Date: Sat, 11 May 2024 17:57:56 -0500 Subject: [PATCH 88/93] Fix regex file path typo --- .github/workflows/linter.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/linter.yml b/.github/workflows/linter.yml index 82683c9d2f7..3f260dfce5a 100644 --- a/.github/workflows/linter.yml +++ b/.github/workflows/linter.yml @@ -78,7 +78,7 @@ jobs: GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }} # Skip autogenerated register files and internal use board files - FILTER_REGEX_EXCLUDE: (.*\/Libraries\/CMSIS\/Device\/Maxim\/.*\/Include\/partitions_.*\.h)|(.*\/Libraries\/((CMSIS\/Device\/Maxim\/[^\/]*\/Include)|(PeriphDrivers\/Source\/[^\/]*))\/[^\/]*_regs\.h)|(.*\/Libraries\/Boards\/[^\/]*\/(BCB|Emulator|Simulation|ROM)[^\/]*\/.*)|(.*\/Examples\/[^\/]*\/Display\/lvgl-8\.0\.2\/.*)|(.*\/Examples\/[^\/]*\/Demo\/lv_conf.h)|(.*\/Libraries\/CMSIS\/5.9.0\/.*)|(.*\/Libraries\/CMSIS\/Include\/.*)|(.*\/Libraries\/Cordio\/.*)|(.*\/Libraries\/SDHC\/.*)|(.*\/Libraries\/lwIP\/.*)|(.*\/Examples\/[^\/]*\/CNN\/.*) + FILTER_REGEX_EXCLUDE: (.*\/Libraries\/CMSIS\/Device\/Maxim\/.*\/Include\/partition_.*\.h)|(.*\/Libraries\/((CMSIS\/Device\/Maxim\/[^\/]*\/Include)|(PeriphDrivers\/Source\/[^\/]*))\/[^\/]*_regs\.h)|(.*\/Libraries\/Boards\/[^\/]*\/(BCB|Emulator|Simulation|ROM)[^\/]*\/.*)|(.*\/Examples\/[^\/]*\/Display\/lvgl-8\.0\.2\/.*)|(.*\/Examples\/[^\/]*\/Demo\/lv_conf.h)|(.*\/Libraries\/CMSIS\/5.9.0\/.*)|(.*\/Libraries\/CMSIS\/Include\/.*)|(.*\/Libraries\/Cordio\/.*)|(.*\/Libraries\/SDHC\/.*)|(.*\/Libraries\/lwIP\/.*)|(.*\/Examples\/[^\/]*\/CNN\/.*) # Explicity turn off all linters except CPP # SuperLinter Documentation says all we need to do is turn on the ones we want From 208ec4c40d7e0b54e1066c94e71cd7e21ad08320 Mon Sep 17 00:00:00 2001 From: Woo Date: Mon, 13 May 2024 13:49:16 -0500 Subject: [PATCH 89/93] Replace UART Half Empty flag to Threshold --- .../CMSIS/Device/Maxim/MAX32657/Include/max32657.svd | 8 ++++---- Libraries/CMSIS/Device/Maxim/MAX32657/Include/uart_regs.h | 8 ++++---- Libraries/PeriphDrivers/Source/UART/uart_revb_me30.svd | 8 ++++---- 3 files changed, 12 insertions(+), 12 deletions(-) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd index b90fbc48bf2..c379437193c 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd @@ -7911,8 +7911,8 @@ 1 - TX_HE - Enable Interrupt For TX FIFO has half empty + TX_THD + Enable Interrupt for when TX FIFO meets or passes the threshold level. 6 1 @@ -7966,8 +7966,8 @@ 1 - TX_HE - Flag for interrupt when TX FIFO is half empty + TX_THD + Flag for interrupt when TX FIFO meets or passes the threshold level. 6 1 diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/uart_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/uart_regs.h index e2506102de8..7b4b85265a4 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/uart_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/uart_regs.h @@ -233,8 +233,8 @@ typedef struct { #define MXC_F_UART_INTEN_TX_OB_POS 5 /**< INTEN_TX_OB Position */ #define MXC_F_UART_INTEN_TX_OB ((uint32_t)(0x1UL << MXC_F_UART_INTEN_TX_OB_POS)) /**< INTEN_TX_OB Mask */ -#define MXC_F_UART_INTEN_TX_HE_POS 6 /**< INTEN_TX_HE Position */ -#define MXC_F_UART_INTEN_TX_HE ((uint32_t)(0x1UL << MXC_F_UART_INTEN_TX_HE_POS)) /**< INTEN_TX_HE Mask */ +#define MXC_F_UART_INTEN_TX_THD_POS 6 /**< INTEN_TX_THD Position */ +#define MXC_F_UART_INTEN_TX_THD ((uint32_t)(0x1UL << MXC_F_UART_INTEN_TX_THD_POS)) /**< INTEN_TX_THD Mask */ #define MXC_F_UART_INTEN_RX_FULL_POS 7 /**< INTEN_RX_FULL Position */ #define MXC_F_UART_INTEN_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_INTEN_RX_FULL_POS)) /**< INTEN_RX_FULL Mask */ @@ -265,8 +265,8 @@ typedef struct { #define MXC_F_UART_INTFL_TX_OB_POS 5 /**< INTFL_TX_OB Position */ #define MXC_F_UART_INTFL_TX_OB ((uint32_t)(0x1UL << MXC_F_UART_INTFL_TX_OB_POS)) /**< INTFL_TX_OB Mask */ -#define MXC_F_UART_INTFL_TX_HE_POS 6 /**< INTFL_TX_HE Position */ -#define MXC_F_UART_INTFL_TX_HE ((uint32_t)(0x1UL << MXC_F_UART_INTFL_TX_HE_POS)) /**< INTFL_TX_HE Mask */ +#define MXC_F_UART_INTFL_TX_THD_POS 6 /**< INTFL_TX_THD Position */ +#define MXC_F_UART_INTFL_TX_THD ((uint32_t)(0x1UL << MXC_F_UART_INTFL_TX_THD_POS)) /**< INTFL_TX_THD Mask */ #define MXC_F_UART_INTFL_RX_FULL_POS 7 /**< INTFL_RX_FULL Position */ #define MXC_F_UART_INTFL_RX_FULL ((uint32_t)(0x1UL << MXC_F_UART_INTFL_RX_FULL_POS)) /**< INTFL_RX_FULL Mask */ diff --git a/Libraries/PeriphDrivers/Source/UART/uart_revb_me30.svd b/Libraries/PeriphDrivers/Source/UART/uart_revb_me30.svd index 12971e73f4a..d69d9ca2026 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_revb_me30.svd +++ b/Libraries/PeriphDrivers/Source/UART/uart_revb_me30.svd @@ -249,8 +249,8 @@ 1 - TX_HE - Enable Interrupt For TX FIFO has half empty + TX_THD + Enable Interrupt for when TX FIFO meets or passes the threshold level. 6 1 @@ -304,8 +304,8 @@ 1 - TX_HE - Flag for interrupt when TX FIFO is half empty + TX_THD + Flag for interrupt when TX FIFO meets or passes the threshold level. 6 1 From f040b6dea9e524ea9de0506d31fc2328bbf758a2 Mon Sep 17 00:00:00 2001 From: Jake Carter Date: Mon, 13 May 2024 14:23:40 -0600 Subject: [PATCH 90/93] Fix -Wexpansion-to-defined error for MAX32657 --- Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h index 1472891893f..44e81073244 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h @@ -153,7 +153,11 @@ typedef enum { #include #include -#define IS_SECURE_ENVIRONMENT (defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)) +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define IS_SECURE_ENVIRONMENT 1 +#else +#define IS_SECURE_ENVIRONMENT 0 +#endif /* ================================================================================ */ /* ================== Device Specific Memory Section ================== */ From 3c58bb4a5a6a8cd0d51d5790f93c3994f83979cc Mon Sep 17 00:00:00 2001 From: Woo Date: Mon, 13 May 2024 17:41:08 -0500 Subject: [PATCH 91/93] Add DMA1 to GCR_PCLKDIS1 register --- Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h | 3 +++ Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd | 6 ++++++ Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me30.svd | 6 ++++++ 3 files changed, 15 insertions(+) diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h index 03ee86280f3..817963f7fc1 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h @@ -447,6 +447,9 @@ typedef struct { #define MXC_F_GCR_PCLKDIS1_SPI_POS 16 /**< PCLKDIS1_SPI Position */ #define MXC_F_GCR_PCLKDIS1_SPI ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_SPI_POS)) /**< PCLKDIS1_SPI Mask */ +#define MXC_F_GCR_PCLKDIS1_DMA1_POS 21 /**< PCLKDIS1_DMA1 Position */ +#define MXC_F_GCR_PCLKDIS1_DMA1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_DMA1_POS)) /**< PCLKDIS1_DMA1 Mask */ + #define MXC_F_GCR_PCLKDIS1_WDT_POS 27 /**< PCLKDIS1_WDT Position */ #define MXC_F_GCR_PCLKDIS1_WDT ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_WDT_POS)) /**< PCLKDIS1_WDT Mask */ diff --git a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd index c379437193c..a3b75cce051 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd +++ b/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd @@ -2341,6 +2341,12 @@ 16 1 + + DMA1 + DMA1 Clock Disable + 21 + 1 + WDT WDT Clock Disable diff --git a/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me30.svd b/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me30.svd index 93e95ad3089..9485ad8c7c3 100644 --- a/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me30.svd +++ b/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me30.svd @@ -714,6 +714,12 @@ 16 1 + + DMA1 + DMA1 Clock Disable + 21 + 1 + WDT WDT Clock Disable From c8d3552e70cac387a984641586cc9fd034741c09 Mon Sep 17 00:00:00 2001 From: Woo Date: Mon, 13 May 2024 17:54:09 -0500 Subject: [PATCH 92/93] Revert MXC_DMA_INSTANCES to TARGET_NUM checks --- .../PeriphDrivers/Source/UART/uart_revb.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/Libraries/PeriphDrivers/Source/UART/uart_revb.c b/Libraries/PeriphDrivers/Source/UART/uart_revb.c index 1888f35a9d0..5e2067ebf1f 100644 --- a/Libraries/PeriphDrivers/Source/UART/uart_revb.c +++ b/Libraries/PeriphDrivers/Source/UART/uart_revb.c @@ -828,7 +828,7 @@ int MXC_UART_RevB_SetAutoDMAHandlers(mxc_uart_revb_regs_t *uart, bool enable) return E_NO_ERROR; } -#if (MXC_DMA_INSTANCES > 1) +#if (TARGET_NUM == 32657) void MXC_UART_RevA_DMA0_Handler(void) { @@ -848,7 +848,7 @@ DMA instance. void MXC_UART_RevB_DMA_SetupAutoHandlers(mxc_dma_regs_t *dma_instance, unsigned int channel) { #ifdef __arm__ -#if (MXC_DMA_INSTANCES > 1) +#if (TARGET_NUM == 32657) NVIC_EnableIRQ(MXC_DMA_CH_GET_IRQ(dma_instance, channel)); /* (JC): This is not the cleanest or most scalable way to do this, @@ -920,7 +920,7 @@ int MXC_UART_RevB_ReadRXFIFODMA(mxc_uart_revb_regs_t *uart, mxc_dma_regs_t *dma, if (states[uart_num].auto_dma_handlers && states[uart_num].channelRx < 0) { /* Acquire channel if we don't have one already */ -#if (MXC_DMA_INSTANCES > 1) +#if (TARGET_NUM == 32657) channel = MXC_DMA_AcquireChannel(dma); #else channel = MXC_DMA_AcquireChannel(); @@ -949,7 +949,7 @@ int MXC_UART_RevB_ReadRXFIFODMA(mxc_uart_revb_regs_t *uart, mxc_dma_regs_t *dma, MXC_DMA_ConfigChannel(config, srcdst); MXC_DMA_SetCallback(channel, MXC_UART_DMACallback); -#if (MXC_DMA_INSTANCES > 1) +#if (TARGET_NUM == 32657) MXC_DMA_EnableInt(dma, channel); #else MXC_DMA_EnableInt(channel); @@ -978,7 +978,7 @@ int MXC_UART_RevB_WriteTXFIFODMA(mxc_uart_revb_regs_t *uart, mxc_dma_regs_t *dma if (states[uart_num].auto_dma_handlers && states[uart_num].channelTx < 0) { /* Acquire channel if we don't have one already */ -#if (MXC_DMA_INSTANCES > 1) +#if (TARGET_NUM == 32657) channel = MXC_DMA_AcquireChannel(dma); #else channel = MXC_DMA_AcquireChannel(); @@ -1007,7 +1007,7 @@ int MXC_UART_RevB_WriteTXFIFODMA(mxc_uart_revb_regs_t *uart, mxc_dma_regs_t *dma MXC_DMA_ConfigChannel(config, srcdst); MXC_DMA_SetCallback(channel, MXC_UART_DMACallback); -#if (MXC_DMA_INSTANCES > 1) +#if (TARGET_NUM == 32657) MXC_DMA_EnableInt(dma, channel); #else MXC_DMA_EnableInt(channel); @@ -1052,7 +1052,7 @@ int MXC_UART_RevB_TransactionDMA(mxc_uart_revb_req_t *req, mxc_dma_regs_t *dma) (req->uart)->dma |= (1 << MXC_F_UART_REVB_DMA_RX_THD_VAL_POS); (req->uart)->dma |= (2 << MXC_F_UART_REVB_DMA_TX_THD_VAL_POS); -#if (MXC_DMA_INSTANCES > 1) +#if (TARGET_NUM == 32657) MXC_DMA_Init(dma); #else MXC_DMA_Init(); @@ -1066,7 +1066,7 @@ int MXC_UART_RevB_TransactionDMA(mxc_uart_revb_req_t *req, mxc_dma_regs_t *dma) if ((req->txData != NULL) && (req->txLen)) { /* Save TX req, the DMA handler will use this later. */ states[uart_num].tx_req = req; -#if (MXC_DMA_INSTANCES > 1) +#if (TARGET_NUM == 32657) if (MXC_UART_WriteTXFIFODMA((mxc_uart_regs_t *)(req->uart), dma, req->txData, req->txLen, NULL) != E_NO_ERROR) { #else @@ -1080,7 +1080,7 @@ int MXC_UART_RevB_TransactionDMA(mxc_uart_revb_req_t *req, mxc_dma_regs_t *dma) //rx if ((req->rxData != NULL) && (req->rxLen)) { states[uart_num].rx_req = req; -#if (MXC_DMA_INSTANCES > 1) +#if (TARGET_NUM == 32657) if (MXC_UART_ReadRXFIFODMA((mxc_uart_regs_t *)(req->uart), dma, req->rxData, req->rxLen, NULL) != E_NO_ERROR) { #else From cc07af19c29dd05274240b7bebbdd2e789adc161 Mon Sep 17 00:00:00 2001 From: Woo Date: Tue, 14 May 2024 10:17:30 -0500 Subject: [PATCH 93/93] Fixed IS_SECURE_ENVIRONMENT typo --- Libraries/CMSIS/Device/Maxim/GCC/gcc.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Libraries/CMSIS/Device/Maxim/GCC/gcc.mk b/Libraries/CMSIS/Device/Maxim/GCC/gcc.mk index 873d657f568..297837952f1 100644 --- a/Libraries/CMSIS/Device/Maxim/GCC/gcc.mk +++ b/Libraries/CMSIS/Device/Maxim/GCC/gcc.mk @@ -278,7 +278,7 @@ ifeq "$(MSECURITY_MODE)" "SECURE" # https://developer.arm.com/documentation/ecm0359818/latest PROJ_CFLAGS += -mcmse -PROJ_AFLAGS += -DIS_SECURE_ENVRIONMENT +PROJ_AFLAGS += -DIS_SECURE_ENVIRONMENT # Tell the linker we are building a secure project. This defines the "SECURE_LINK" symbol which the # linker uses to set the secure FLASH/SRAM memory address ranges.