diff --git a/Libraries/CMSIS/Device/Maxim/GCC/mxc_version.mk b/Libraries/CMSIS/Device/Maxim/GCC/mxc_version.mk
index cde4ab47d1..bd0ef8389c 100644
--- a/Libraries/CMSIS/Device/Maxim/GCC/mxc_version.mk
+++ b/Libraries/CMSIS/Device/Maxim/GCC/mxc_version.mk
@@ -16,7 +16,7 @@
  #
  ##############################################################################
 # Autogenerated version info for build system.
-MSDK_VERSION_STRING := v2023_10-307-gf557dbf1716
+MSDK_VERSION_STRING := v2023_10-333-ga03f3f8b2f8
 MSDK_VERSION_YEAR := 2023
 MSDK_VERSION_MONTH := 10
 
diff --git a/Libraries/Cordio/platform/targets/maxim/max32690/sources/pal_sys.c b/Libraries/Cordio/platform/targets/maxim/max32690/sources/pal_sys.c
index 870544c17a..54be4451b8 100644
--- a/Libraries/Cordio/platform/targets/maxim/max32690/sources/pal_sys.c
+++ b/Libraries/Cordio/platform/targets/maxim/max32690/sources/pal_sys.c
@@ -52,6 +52,7 @@
 #include "wut.h"
 #include "uart.h"
 #include "sema.h"
+#include "dma.h"
 
 /**************************************************************************************************
   Macros
@@ -102,6 +103,76 @@ void PalExitCs(void)
   __enable_irq();
 }
 
+/*************************************************************************************************/
+/*!
+ *  \brief  DMA interrupt handlers.
+ */
+/*************************************************************************************************/
+void DMA0_IRQHandler(void)
+{
+  MXC_DMA_Handler(); /* DMA channel 0 is associated with DMA instance 0 */
+}
+void DMA1_IRQHandler(void)
+{
+  MXC_DMA_Handler(); /* DMA channel 1 is associated with DMA instance 0 */
+}
+void DMA2_IRQHandler(void)
+{
+  MXC_DMA_Handler(); /* DMA channel 2 is associated with DMA instance 0 */
+}
+void DMA3_IRQHandler(void)
+{
+  MXC_DMA_Handler(); /* DMA channel 3 is associated with DMA instance 0 */
+}
+void DMA4_IRQHandler(void)
+{
+  MXC_DMA_Handler(); /* DMA channel 4 is associated with DMA instance 0 */
+}
+void DMA5_IRQHandler(void)
+{
+  MXC_DMA_Handler(); /* DMA channel 5 is associated with DMA instance 0 */
+}
+void DMA6_IRQHandler(void)
+{
+  MXC_DMA_Handler(); /* DMA channel 6 is associated with DMA instance 0 */
+}
+void DMA7_IRQHandler(void)
+{
+  MXC_DMA_Handler(); /* DMA channel 7 is associated with DMA instance 0 */
+}
+void DMA8_IRQHandler(void)
+{
+  MXC_DMA_Handler(); /* DMA channel 8 is associated with DMA instance 0 */
+}
+void DMA9_IRQHandler(void)
+{
+  MXC_DMA_Handler(); /* DMA channel 9 is associated with DMA instance 0 */
+}
+void DMA10_IRQHandler(void)
+{
+  MXC_DMA_Handler(); /* DMA channel 10 is associated with DMA instance 0 */
+}
+void DMA11_IRQHandler(void)
+{
+  MXC_DMA_Handler(); /* DMA channel 11 is associated with DMA instance 0 */
+}
+void DMA12_IRQHandler(void)
+{
+  MXC_DMA_Handler(); /* DMA channel 12 is associated with DMA instance 0 */
+}
+void DMA13_IRQHandler(void)
+{
+  MXC_DMA_Handler(); /* DMA channel 13 is associated with DMA instance 0 */
+}
+void DMA14_IRQHandler(void)
+{
+  MXC_DMA_Handler(); /* DMA channel 14 is associated with DMA instance 0 */
+}
+void DMA15_IRQHandler(void)
+{
+  MXC_DMA_Handler(); /* DMA channel 15 is associated with DMA instance 0 */
+}
+
 /*************************************************************************************************/
 /*!
  *  \brief      Common platform initialization.
diff --git a/Libraries/Cordio/platform/targets/maxim/max32690/sources/pal_uart.c b/Libraries/Cordio/platform/targets/maxim/max32690/sources/pal_uart.c
index 51f5af827a..aab5bec3b2 100644
--- a/Libraries/Cordio/platform/targets/maxim/max32690/sources/pal_uart.c
+++ b/Libraries/Cordio/platform/targets/maxim/max32690/sources/pal_uart.c
@@ -38,8 +38,13 @@
 #include "board.h"
 
 #include "uart.h"
+#include "dma.h"
 #include "sema.h"
 
+#include "uart_revb.h"
+
+#include "wsf_cs.h"
+
 #include <string.h>
 
 /**************************************************************************************************
@@ -65,71 +70,12 @@
 /*! \brief      Control block. */
 static struct {
   PalUartState_t state;
-  mxc_uart_req_t readReq;
-  mxc_uart_req_t writeReq;
   PalUartCompCback_t rdCback;
   PalUartCompCback_t wrCback;
+  int writeCh;
+  int readCh;
 } palUartCb[PAL_UARTS];
 
-/**************************************************************************************************
-  Local Functions
-**************************************************************************************************/
-
-/*************************************************************************************************/
-/*!
- *  \brief      UART Interrupt handlers.
- *
- *  \return     None.
- */
-/*************************************************************************************************/
-void UART_CommonHandler(mxc_uart_regs_t *uart)
-{
-  const int32_t err = MXC_UART_AsyncHandler(uart);
-
-  if(err == E_INVALID)
-  {
-    const uint8_t uartIdx = MXC_UART_GET_IDX(uart);
-
-    if( uartIdx == CONSOLE_UART || uartIdx == HCI_UART)
-    {
-      MXC_UART_ClearRXFIFO(uart);
-    }
-    else
-    {
-      PAL_SYS_ASSERT(err == E_NO_ERROR);
-    }
-  }
-  
-}
-void UART0_IRQHandler(void)
-{
-  
-  PalLedOn(PAL_LED_ID_CPU_ACTIVE);
-  UART_CommonHandler(MXC_UART0);
-
-}
-void UART1_IRQHandler(void)
-{
-  
-  PalLedOn(PAL_LED_ID_CPU_ACTIVE);
-  UART_CommonHandler(MXC_UART1);
-
-}
-void UART2_IRQHandler(void)
-{
-  
-  PalLedOn(PAL_LED_ID_CPU_ACTIVE);
-  UART_CommonHandler(MXC_UART2);
-
-}
-void UART3_IRQHandler(void)
-{
-  
-  PalLedOn(PAL_LED_ID_CPU_ACTIVE);
-  UART_CommonHandler(MXC_UART3);
-
-}
-
 /*************************************************************************************************/
 /*!
  *  \brief      Inter-processor communication interrupt handlers.
@@ -172,23 +118,30 @@ void RISCV_IRQHandler(void)
  *  \return     None.
  */
 /*************************************************************************************************/
-void palUartCallback(mxc_uart_req_t* req, int error)
+void palUartCallback(int ch, int error)
 {
   int i;
   for(i = 0; i < PAL_UARTS; i++) {
     /* Find the corresponding rqeuest and call the callback */
-    if(req == &palUartCb[i].readReq) {
+    
+     if((ch == palUartCb[i].readCh) && (palUartCb[i].state != PAL_UART_STATE_UNINIT)) {
+      palUartCb[i].readCh = -1;
       if(palUartCb[i].rdCback != NULL) {
         palUartCb[i].rdCback();
       }
+
+      MXC_DMA_ReleaseChannel(ch);
       return;
     }
 
-    if(req == &palUartCb[i].writeReq) {
+    if((ch == palUartCb[i].writeCh) && (palUartCb[i].state != PAL_UART_STATE_UNINIT)) {
+      palUartCb[i].writeCh = -1;
       palUartCb[i].state = PAL_UART_STATE_READY;
       if(palUartCb[i].wrCback != NULL) {
         palUartCb[i].wrCback();
       }
+
+      MXC_DMA_ReleaseChannel(ch);
       return;
     }
   }
@@ -283,8 +236,8 @@ static void PalMailInit(const PalUartConfig_t *pCfg)
 /*************************************************************************************************/
 void PalUartInit(PalUartId_t id, const PalUartConfig_t *pCfg)
 {
-  uint8_t uartNum;
-  int result;
+  uint8_t uartNum = palUartGetNum(id);
+  mxc_uart_regs_t *uart = MXC_UART_GET_UART(uartNum);
 
 #if defined(HCI_TR_MAIL) && (HCI_TR_MAIL != 0)
   if(id == PAL_UART_ID_CHCI) {
@@ -293,30 +246,50 @@ void PalUartInit(PalUartId_t id, const PalUartConfig_t *pCfg)
   }
 #endif
 
-  uartNum = palUartGetNum(id);
-
   PAL_SYS_ASSERT(palUartCb[uartNum].state == PAL_UART_STATE_UNINIT);
 
   /* Save the callback */
   palUartCb[uartNum].rdCback = pCfg->rdCback;
   palUartCb[uartNum].wrCback = pCfg->wrCback;
+  palUartCb[uartNum].readCh = -1;
+  palUartCb[uartNum].writeCh = -1;
+  
 
-  result = MXC_UART_Init(MXC_UART_GET_UART(uartNum), pCfg->baud, MXC_UART_IBRO_CLK);
-
+  int result = MXC_UART_Init(uart, pCfg->baud, MXC_UART_IBRO_CLK);
   (void)result;
   PAL_SYS_ASSERT(result == 0);
 
-  MXC_UART_SetDataSize(MXC_UART_GET_UART(uartNum), 8);
-  MXC_UART_SetStopBits(MXC_UART_GET_UART(uartNum), MXC_UART_STOP_1);
-  MXC_UART_SetParity(MXC_UART_GET_UART(uartNum), MXC_UART_PARITY_DISABLE);
+  /* Disable UART interrupts */
+  MXC_UART_DisableInt(uart, 0xFFFFFFFF);
+  MXC_UART_ClearFlags(uart, 0xFFFFFFFF);
+
+  MXC_UART_SetDataSize(uart, 8);
+  MXC_UART_SetStopBits(uart, MXC_UART_STOP_1);
+  MXC_UART_SetParity(uart, MXC_UART_PARITY_DISABLE);
   if(pCfg->hwFlow) {
-    MXC_UART_SetFlowCtrl(MXC_UART_GET_UART(uartNum), MXC_UART_FLOW_EN, 1);
+    MXC_UART_SetFlowCtrl(uart, MXC_UART_FLOW_EN, 1);
   }
   
-  const IRQn_Type uartIrqn = MXC_UART_GET_IRQ(uartNum);
-  NVIC_ClearPendingIRQ(uartIrqn);
-  NVIC_EnableIRQ(uartIrqn); 
-  
+  MXC_DMA_Init();
+
+  /* Enable the DMA channel interrupts */
+  NVIC_EnableIRQ(DMA0_IRQn);
+  NVIC_EnableIRQ(DMA1_IRQn);
+  NVIC_EnableIRQ(DMA2_IRQn);
+  NVIC_EnableIRQ(DMA3_IRQn);
+  NVIC_EnableIRQ(DMA4_IRQn);
+  NVIC_EnableIRQ(DMA5_IRQn);
+  NVIC_EnableIRQ(DMA6_IRQn);
+  NVIC_EnableIRQ(DMA7_IRQn);
+  NVIC_EnableIRQ(DMA8_IRQn);
+  NVIC_EnableIRQ(DMA9_IRQn);
+  NVIC_EnableIRQ(DMA10_IRQn);
+  NVIC_EnableIRQ(DMA11_IRQn);
+  NVIC_EnableIRQ(DMA12_IRQn);
+  NVIC_EnableIRQ(DMA13_IRQn);
+  NVIC_EnableIRQ(DMA14_IRQn);
+  NVIC_EnableIRQ(DMA15_IRQn);
+ 
   palUartCb[uartNum].state = PAL_UART_STATE_READY;
 }
 
@@ -334,13 +307,13 @@ void PalUartInit(PalUartId_t id, const PalUartConfig_t *pCfg)
 void PalUartDeInit(PalUartId_t id)
 {
   uint8_t uartNum = palUartGetNum(id);
-  int result;
 
-  result = MXC_UART_Shutdown(MXC_UART_GET_UART(uartNum));
+  int result = MXC_UART_Shutdown(MXC_UART_GET_UART(uartNum));
   (void)result;
   PAL_SYS_ASSERT(result);
 
   NVIC_DisableIRQ(MXC_UART_GET_IRQ(uartNum));
+  MXC_DMA_DeInit();
 
   palUartCb[uartNum].state = PAL_UART_STATE_UNINIT;
 }
@@ -378,9 +351,8 @@ PalUartState_t PalUartGetState(PalUartId_t id)
 /*************************************************************************************************/
 void PalUartReadData(PalUartId_t id, uint8_t *pData, uint16_t len)
 {
-  uint8_t uartNum;
-  uint32_t irqn;
-  int result;
+  uint8_t uartNum = palUartGetNum(id);
+  mxc_uart_regs_t* uart = MXC_UART_GET_UART(uartNum);
 
 #if defined(HCI_TR_MAIL) && (HCI_TR_MAIL != 0)
   if(id == PAL_UART_ID_CHCI) {
@@ -389,26 +361,69 @@ void PalUartReadData(PalUartId_t id, uint8_t *pData, uint16_t len)
   }
 #endif
 
-  uartNum = palUartGetNum(id);
-  irqn = MXC_UART_GET_IRQ(uartNum);
-
-  palUartCb[uartNum].readReq.uart       = MXC_UART_GET_UART(uartNum);
-  palUartCb[uartNum].readReq.rxData     = pData;
-  palUartCb[uartNum].readReq.rxLen      = len;
-  palUartCb[uartNum].readReq.txLen      = 0;
-  palUartCb[uartNum].readReq.callback   = palUartCallback;
+  WsfCsEnter();
+  int dmaCh = MXC_DMA_AcquireChannel();
+  WsfCsExit();
+
+  /* Save the channel number */
+  palUartCb[uartNum].readCh = dmaCh;
+
+  /* Setup the DMA transfer */
+  mxc_dma_config_t config = {
+    .ch = dmaCh,
+    .srcwd = MXC_DMA_WIDTH_BYTE,
+    .dstwd = MXC_DMA_WIDTH_BYTE,
+    .srcinc_en = 0,
+    .dstinc_en = 1
+  };
+
+  mxc_dma_srcdst_t srcdst = {
+    .ch = dmaCh,
+    .dest = (void*)pData,
+    .len = len
+  };
+
+  switch (uartNum) {
+  case 0:
+    config.reqsel = MXC_DMA_REQUEST_UART0RX;
+    break;
+
+  case 1:
+    config.reqsel = MXC_DMA_REQUEST_UART1RX;
+    break;
+
+  case 2:
+    config.reqsel = MXC_DMA_REQUEST_UART2RX;
+    break;
+
+  case 3:
+    config.reqsel = MXC_DMA_REQUEST_UART3RX;
+    break;
+
+  default:
+    PAL_SYS_ASSERT(0);
+    return;
+  }
 
-  NVIC_DisableIRQ(irqn);
+  MXC_DMA_ConfigChannel(config, srcdst);
+  MXC_DMA_SetCallback(dmaCh, palUartCallback);
+  
+  /* Enable Count-to-Zero (CTZ) interrupt */
+  MXC_DMA_EnableInt(dmaCh);
+  MXC_DMA_SetChannelInterruptEn(dmaCh, 0, 1);
 
-  /* Start the read */
-  result = MXC_UART_TransactionAsync(&palUartCb[uartNum].readReq);
-  (void)result;
-  PAL_SYS_ASSERT(result == E_SUCCESS);
+  /* Set Rx FIFO threshold */
+  uart->dma |= 1 << MXC_F_UART_REVB_DMA_RX_THD_VAL_POS;
+  /* Enable channel receiving */ 
+  uart->dma |= MXC_F_UART_REVB_DMA_RX_EN;
 
-  /* Enable the interrupt */
-  NVIC_EnableIRQ(irqn);
+  /* Start the transfer */
+  MXC_DMA_Start(dmaCh);
 }
 
+
+
+
 /*************************************************************************************************/
 /*!
  *  \brief      Write data to Tx FIFO.
@@ -424,10 +439,8 @@ void PalUartReadData(PalUartId_t id, uint8_t *pData, uint16_t len)
 /*************************************************************************************************/
 void PalUartWriteData(PalUartId_t id, const uint8_t *pData, uint16_t len)
 {
-  uint8_t uartNum;
-  uint32_t irqn;
-  int result;
-
+  uint8_t uartNum = palUartGetNum(id);
+  mxc_uart_regs_t* uart = MXC_UART_GET_UART(uartNum);
 
 #if defined(HCI_TR_MAIL) && (HCI_TR_MAIL != 0)
   if(id == PAL_UART_ID_CHCI) {
@@ -435,25 +448,63 @@ void PalUartWriteData(PalUartId_t id, const uint8_t *pData, uint16_t len)
     return;
   }
 #endif
+  
+  WsfCsEnter();
+  int dmaCh = MXC_DMA_AcquireChannel();
+  WsfCsExit();
 
-  uartNum = palUartGetNum(id);
-  irqn = MXC_UART_GET_IRQ(uartNum);
+  palUartCb[uartNum].writeCh = dmaCh;
+  palUartCb[uartNum].state = PAL_UART_STATE_BUSY;
 
-  NVIC_DisableIRQ(irqn);
+  /* Setup the DMA transfer */
+  mxc_dma_config_t config = {
+    .ch = dmaCh,
+    .srcwd = MXC_DMA_WIDTH_BYTE,
+    .dstwd = MXC_DMA_WIDTH_BYTE,
+    .srcinc_en = 1,
+    .dstinc_en = 0
+  };
+
+  mxc_dma_srcdst_t srcdst = {
+    .ch = dmaCh,
+    .source = (void*)pData,
+    .len = len
+  };
+
+  switch (uartNum) {
+  case 0:
+    config.reqsel = MXC_DMA_REQUEST_UART0TX;
+    break;
+
+  case 1:
+    config.reqsel = MXC_DMA_REQUEST_UART1TX;
+    break;
+
+  case 2:
+    config.reqsel = MXC_DMA_REQUEST_UART2TX;
+    break;
+
+  case 3:
+    config.reqsel = MXC_DMA_REQUEST_UART3TX;
+    break;
+
+  default:
+    PAL_SYS_ASSERT(0);
+    return;
+  }
 
-  palUartCb[uartNum].state = PAL_UART_STATE_BUSY;
+  MXC_DMA_ConfigChannel(config, srcdst);
+  MXC_DMA_SetCallback(dmaCh, palUartCallback);
 
-  palUartCb[uartNum].writeReq.uart       = MXC_UART_GET_UART(uartNum);
-  palUartCb[uartNum].writeReq.txData     = pData;
-  palUartCb[uartNum].writeReq.txLen      = len;
-  palUartCb[uartNum].writeReq.rxLen      = 0;
-  palUartCb[uartNum].writeReq.callback   = palUartCallback;
+  /* Enable Count-to-Zero (CTZ) interrupt */
+  MXC_DMA_EnableInt(dmaCh);
+  MXC_DMA_SetChannelInterruptEn(dmaCh, 0, 1);
 
-  /* Start the write */
-  result = MXC_UART_TransactionAsync(&palUartCb[uartNum].writeReq);
-  (void)result;
-  PAL_SYS_ASSERT(result == E_SUCCESS);
+  /* Set Tx FIFO threshold */
+  uart->dma |= 2 << MXC_F_UART_REVB_DMA_TX_THD_VAL_POS;
+  /* Enable channel transmission */
+  uart->dma |= MXC_F_UART_REVB_DMA_TX_EN;
 
-  /* Enable the interrupt */
-  NVIC_EnableIRQ(irqn);
+  /* Start the transfer */
+  MXC_DMA_Start(dmaCh);
 }