diff --git a/Libraries/CMSIS/5.9.0/Core/Include/core_rv32.h b/Libraries/CMSIS/5.9.0/Core/Include/core_rv32.h index 0f047a9230a..1c5cf5a1658 100644 --- a/Libraries/CMSIS/5.9.0/Core/Include/core_rv32.h +++ b/Libraries/CMSIS/5.9.0/Core/Include/core_rv32.h @@ -484,7 +484,13 @@ __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) */ __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) { - //NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ + if (IRQn < 32) { + MXC_INTR->irq0_set_pending |= (1 << IRQn); + MXC_EVENT->event0_set_pending |= (1 << IRQn); + } else { + MXC_INTR->irq1_set_pending |= (1 << (IRQn - 32)); + MXC_EVENT->event1_set_pending |= (1 << (IRQn - 32)); + } } /** \brief Clear Pending Interrupt diff --git a/Libraries/CMSIS/Device/Maxim/MAX32655/Source/GCC/startup_riscv_max32655.S b/Libraries/CMSIS/Device/Maxim/MAX32655/Source/GCC/startup_riscv_max32655.S index b09523f27a5..ab29f457ebd 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX32655/Source/GCC/startup_riscv_max32655.S +++ b/Libraries/CMSIS/Device/Maxim/MAX32655/Source/GCC/startup_riscv_max32655.S @@ -165,8 +165,9 @@ __isr_vector: Reset_Handler: /* set 0 in mtvec (base for IVT) */ - csrrw x0, mtvec, x0 - + la t0, (__isr_vector + 1) + csrrw x0, mtvec, t0 + /* Initialize Stack Pointer */ la sp, __StackTop diff --git a/Libraries/CMSIS/Device/Maxim/MAX78000/Source/GCC/startup_riscv_max78000.S b/Libraries/CMSIS/Device/Maxim/MAX78000/Source/GCC/startup_riscv_max78000.S index befa57e96cc..49d2dfd680b 100644 --- a/Libraries/CMSIS/Device/Maxim/MAX78000/Source/GCC/startup_riscv_max78000.S +++ b/Libraries/CMSIS/Device/Maxim/MAX78000/Source/GCC/startup_riscv_max78000.S @@ -126,9 +126,9 @@ __isr_vector: .globl Reset_Handler .type Reset_Handler, %function Reset_Handler: - - /* set 0 in mtvec (base for IVT) */ - csrrw x0, mtvec, x0 + /* Load interrupt vector table */ + la t0, (__isr_vector + 1) + csrrw x0, mtvec, t0 /* Initialize Stack Pointer */ la sp, __StackTop