From 1438fa75931d312769f70cdc27ae4e55bdbe2b5a Mon Sep 17 00:00:00 2001
From: Jake Carter <jake.carter@analog.com>
Date: Tue, 14 Mar 2023 17:47:04 -0500
Subject: [PATCH] Fix RISC-V Debug Functional Test Errors (#489)

* Use MXC_NVIC_SetVector for AI87 imagenet-riscv

* Signal M4 before entering while(1) for Hello_World-riscv
---
 Examples/MAX32655/Hello_World-riscv/main_riscv.c | 6 +++---
 Examples/MAX32680/Hello_World-riscv/main_riscv.c | 6 +++---
 Examples/MAX78002/CNN/imagenet-riscv/main.c      | 2 +-
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/Examples/MAX32655/Hello_World-riscv/main_riscv.c b/Examples/MAX32655/Hello_World-riscv/main_riscv.c
index 23b4f74b94..d44565df65 100644
--- a/Examples/MAX32655/Hello_World-riscv/main_riscv.c
+++ b/Examples/MAX32655/Hello_World-riscv/main_riscv.c
@@ -47,6 +47,9 @@ int main(void)
     Debug_Init(); // Set up RISCV JTAG
     MXC_ICC_Enable(MXC_ICC1); // Enable cache
 
+    // Signal the Cortex-M4
+    MXC_SEMA->irq0 = MXC_F_SEMA_IRQ0_EN | MXC_F_SEMA_IRQ0_CM4_IRQ;
+
     printf("Hello World!\n");
     while (1) {
         LED_On(0);
@@ -56,8 +59,5 @@ int main(void)
         printf("count = %d\n", cnt++);
     }
 
-    // Signal the Cortex-M4
-    MXC_SEMA->irq0 = MXC_F_SEMA_IRQ0_EN | MXC_F_SEMA_IRQ0_CM4_IRQ;
-
     return 0;
 }
diff --git a/Examples/MAX32680/Hello_World-riscv/main_riscv.c b/Examples/MAX32680/Hello_World-riscv/main_riscv.c
index 23b4f74b94..d44565df65 100644
--- a/Examples/MAX32680/Hello_World-riscv/main_riscv.c
+++ b/Examples/MAX32680/Hello_World-riscv/main_riscv.c
@@ -47,6 +47,9 @@ int main(void)
     Debug_Init(); // Set up RISCV JTAG
     MXC_ICC_Enable(MXC_ICC1); // Enable cache
 
+    // Signal the Cortex-M4
+    MXC_SEMA->irq0 = MXC_F_SEMA_IRQ0_EN | MXC_F_SEMA_IRQ0_CM4_IRQ;
+
     printf("Hello World!\n");
     while (1) {
         LED_On(0);
@@ -56,8 +59,5 @@ int main(void)
         printf("count = %d\n", cnt++);
     }
 
-    // Signal the Cortex-M4
-    MXC_SEMA->irq0 = MXC_F_SEMA_IRQ0_EN | MXC_F_SEMA_IRQ0_CM4_IRQ;
-
     return 0;
 }
diff --git a/Examples/MAX78002/CNN/imagenet-riscv/main.c b/Examples/MAX78002/CNN/imagenet-riscv/main.c
index a10f764a15..3ea6fbc513 100644
--- a/Examples/MAX78002/CNN/imagenet-riscv/main.c
+++ b/Examples/MAX78002/CNN/imagenet-riscv/main.c
@@ -62,7 +62,7 @@ int main(void)
 
     MXC_FCR->urvbootaddr = (uint32_t)&__FlashStart_; // Set RISC-V boot address
     MXC_SYS_ClockEnable(MXC_SYS_PERIPH_CLOCK_SMPHR); // Enable Sempahore clock
-    NVIC_SetVector(RISCV_IRQn, WakeISR); // Set wakeup ISR
+    MXC_NVIC_SetVector(RISCV_IRQn, WakeISR); // Set wakeup ISR
 
     // DO NOT DELETE THIS LINE:
     MXC_Delay(SEC(2)); // Let debugger interrupt if needed