Firmware Extentions

[damercer]

The M1k hardware can operate in ways not presently provided/supported in the firmware.

First off as a friendly reminder. In the new Rev F board, the 3 PWM outputs have been moved to the digital connector. It would be nice to be able to program the PWM signals?

I acknowledge and stipulate that there are not many if any CPU cycles left to do anything else while streaming data.

I think there are still some possibilities for more features that do not add or change the number of CPU cycles used while streaming.

Right now the two AD7682 ADCs in the hardware are configured to simultaneously measure both voltage and current on both channel A and B at 100KSPS. Each of the two ADCs run at 200 KSPS to get 4 measurement values at 100 KSPS for a total of 4X100K or 400K.

Another very useful way to possibly configure the hardware would be for each ADC to just measure the voltage signal channel at 200 KSPS, for the same total number of samples 2X200K or 400K.

Acknowledging that the two AWG DACs sample rate will still be 100KSPS you might ask what good is having the voltage measurements at 200KSPS? Well, there are the Hi-Z modes where the inputs are uses like a scope channel (or spectrum analyzer) and could be measuring a signal generated by some independent source not related to the AWG outputs. In addition the circuit under test might (likely will) include some kind of filtering function that shifts or smooths out the AWG DAC steps. When viewing a signal in the time domain more samples per second is always a good thing. There are many less obvious side advantages of a higher sample rate and oversampling that I have identified over the last many years of working on this sort of thing.

So how could this be accomplished?

The two AD7682 ADCs have 4 way input multiplexers that in the present configuration cycle through the four analog measurement signals:
From the schematic for U11
VSENSE-A -> IN0
VSENSE-B -> IN1
ISENSE-A -> IN2
ISENSE-B -> IN3
And U12
VSENSE-B -> IN0
VSENSE-A -> IN1
ISENSE-B -> IN2
ISENSE-A -> IN3

According to datasheet Table 11. Configuration Register Description, it is possible to select how the chip sequences though the MUX inputs. Bit 1 and 2 of the register configure the Channel sequencer which Allows for scanning channels in an IN0 to IN3 fashion when set to 11. Which I believe is the way it is being done now. In addition the sequencer can be disabled (bits 2:1 set 00), so the Mux is set to whichever channel is selected by setting register bits 7 and 8.

It looks to me that providing 2X sampling modes for any one combination of voltage or current measurement per channel is easily done by setting these register bits differently. The possible settings in 2X sampling mode would be:

With Mux sequencer disabled, 2:1 set to 00
Channel A voltage (U11) 8:7 set to 00
Channel A current (U11) 8:7 set to 10
Channel B voltage (U12) 8:7 set to 00
Channel B current (U12) 8:7 set to 10

The 1X simultaneous modes would still be:
Channel A voltage and current
Channel B voltage and current

Providing these new configurations in the firmware would of course require additions / changes to libsmu and pysmu to select thew modes and properly format the raw ADC output to calibrated values in the returned array.

I would like to also suggest some stretch goals:

Simple 4 bit Logic analyzer functions?

Again there are probably not enough CPU cycles to have the hardware walk AND chew gum at the same time but maybe there is a way to have it either walk (present analog sampling modes) OR chew gum (logic analyzer mode)?

Most all the low cost micro-controller based USB instruments have rudimentary logic analyzer functionality like:

The $29 EspoTek Labrador Board, https://espotek.com/labrador/product/espotek-labrador-board/

The $20 Xprotolab Plain, http://www.gabotronics.com/oscilloscopes/xprotolab-plain.htm

Maybe M1k could have a mode where the four logic inputs are read and streamed over the USB? Maybe not at a super high sample rate but it is only 4 bits at a time after all. If we are sending 4X16 bits at 100K analog right now might it be possible to at least send 16X4 bits at 100K or effectively 1.6 MBits/sec for each digital input? How fast could the digital inputs be sampled?

Pattern generator mode?

Support for common serial protocols (SPI, I2C)? Stream serial data to/from new DAC and ADC provided in ADALP2000 kit?

Most of the actual logic analyzer software like the GUI and any serial protocol analyzers would be written in a high level language on the host computer.

This might take more work in the firmware but we might trade off the simultaneous current measurements for mixed signal voltage and digital data channels?

Doug

[damercer]

Here is another capability that we should think about adding in the firmware.

After creating over 100 labs for M1k it has become apparent that, with one or two notable exceptions, one channel is always used as a source for the input of the circuit and the second channel is used in Hi-Z mode to measure the output or some internal node of the circuit. This was mostly out of necessity because in the SMU idea (rev D) both source and measure functions share a single pin and a channel could only be an output or an input. You basically have a one channel function generator and a two channel scope where one scope channel is always connected to the function generator. Obvious examples of this are when using the Spectrum Analyzer, Bode plotter, Network Analyzer, Impedance Analyzer or vector voltmeter. One AWG is driving the input while the second channel in Hi-Z measures the output. As a result one side of the dual AD5663 DAC is not being used.

Again based on how I read the AD5663 datasheet, depending on how you set bits in the control register, it would be possible to write to just one DAC at 200KSPS rather than both DACs at 100KSPS each. It might require that the LDAC signal be toggled at 200 KHz to update the DAC output rather tham 100 KHz when using both DACs. The other DAC could be set to a constant value and that channel used as a variable power supply, in the Rev F version anyway.

With both the input ADCs and the one AWG DAC running at 200KSPS, the measurement bandwidth, or test frequency when using the Spectrum Analyzer, Bode plotter, Network Analyzer, Impedance Analyzer or vector voltmeter will be doubled.

As with viewing a signal in the time domain, generating more samples per second (over-sampling) is always a good thing.

This new mode of sampling at 2X on one DAC should be independent of the new ADC sampling modes, i.e. you should be allowed to mix and match between ADC and DAC modes. I see no reason they would be mutually exclusive.