From 429bbd30ade78edfa6bea237d31c1f26374bfe5e Mon Sep 17 00:00:00 2001 From: Iulia Moldovan Date: Wed, 13 Nov 2024 17:00:02 +0200 Subject: [PATCH 01/10] docs/library: Uniformize the obsolete IP warning * axi_ad9144 * axi_ad9371 * axi_ad9643 * axi_ad9671 Signed-off-by: Iulia Moldovan --- docs/library/axi_ad9144/index.rst | 15 ++++++++------- docs/library/axi_ad9371/index.rst | 11 +++++++---- docs/library/axi_ad9643/index.rst | 4 ++-- docs/library/axi_ad9671/index.rst | 10 ++++++++-- 4 files changed, 25 insertions(+), 15 deletions(-) diff --git a/docs/library/axi_ad9144/index.rst b/docs/library/axi_ad9144/index.rst index 2f16142669..f09338d166 100644 --- a/docs/library/axi_ad9144/index.rst +++ b/docs/library/axi_ad9144/index.rst @@ -4,15 +4,17 @@ AXI AD9144 (OBSOLETE) ================================================================================ .. warning:: - This IP is was discontinued, limited support available. Last release for this - IP is ``hdl_2019_r2`` and can be found on our HDL repository, on the branch - with the same name. + + The support for :git-hdl:`AXI AD9144 ` + has been discontinued, the latest tested release being ``hdl_2019_r2``. + This page is for legacy purposes only. The :git-hdl:`AXI AD9144 ` IP core can be used to interface the :adi:`AD9144` DAC. An AXI Memory Map interface is used for -configuration. Data is sent in a format that can be transmitted by Xilinx's -JESD IP. More about the generic framework interfacing DACs, can be read -in :ref:`axi_adc`. +configuration. Data is sent in a format that can be transmitted by AMD Xilinx's +JESD IP. + +More about the generic framework interfacing DACs, can be read in :ref:`axi_adc`. Features -------------------------------------------------------------------------------- @@ -40,7 +42,6 @@ Files * - :git-hdl:`hdl_2019_r2:library/axi_ad9144/axi_ad9144_constr.xdc` - Constraint file of the IP. - Block Diagram -------------------------------------------------------------------------------- diff --git a/docs/library/axi_ad9371/index.rst b/docs/library/axi_ad9371/index.rst index 097f215d9c..449511b61e 100644 --- a/docs/library/axi_ad9371/index.rst +++ b/docs/library/axi_ad9371/index.rst @@ -4,9 +4,10 @@ AXI AD9371 (OBSOLETE) ================================================================================ .. warning:: - This IP is was discontinued, limited support available. Last release for this - IP is ``hdl_2019_r2`` and can be found on our HDL repository, on the branch - with the same name. + + The support for :git-hdl:`AXI AD9371 ` + has been discontinued, the latest tested release being ``hdl_2019_r2``. + This page is for legacy purposes only. .. note:: This page has a great historical background. The same functionalities are @@ -15,7 +16,9 @@ AXI AD9371 (OBSOLETE) The :git-hdl:`AXI AD9371 ` IP core can be used to interface the :adi:`AD9371` device. An AXI Memory Map interface is used for configuration. Data is sent in a format that can be transmitted by Xilinx's -JESD IP. More about the generic framework interfacing ADCs, that contains the +JESD IP. + +More about the generic framework interfacing ADCs and DACs, that contains the ``up_dac_channel``, ``up_adc_channel`` and ``up_dac_common modules``, ``up_adc_common modules`` can be read in :ref:`axi_dac` and :ref:`axi_adc`. diff --git a/docs/library/axi_ad9643/index.rst b/docs/library/axi_ad9643/index.rst index 5d85a7a059..1806e02da1 100644 --- a/docs/library/axi_ad9643/index.rst +++ b/docs/library/axi_ad9643/index.rst @@ -6,7 +6,7 @@ AXI AD9643 (OBSOLETE) .. warning:: The support for :git-hdl:`AXI AD9643 ` IP - has been discontinued, the latest tested release being hdl_2016_r1. + has been discontinued, the latest tested release being ``hdl_2016_r1``. This page is for legacy purposes only. The :git-hdl:`AXI AD9643 ` IP core was used @@ -158,7 +158,7 @@ delayed independently through the delay controller register map. For more information regarding the 7 Series primitives you can take a look at AMD Xilinx's user guides UG472, UG471 and UG953. -The output of the interface module is fed to the channel modules. +The output of the interface module is fed to the channel modules. The channel module implements: * a PRBS monitor diff --git a/docs/library/axi_ad9671/index.rst b/docs/library/axi_ad9671/index.rst index 62f78cb294..266c1d6140 100644 --- a/docs/library/axi_ad9671/index.rst +++ b/docs/library/axi_ad9671/index.rst @@ -5,11 +5,17 @@ AXI AD9671 (OBSOLETE) .. hdl-component-diagram:: -The :git-hdl:`AXI AD9671 ` IP core +.. warning:: + + The support for :git-hdl:`AXI AD9671 ` + has been discontinued. + This page is kept for legacy purposes only. + +The :git-hdl:`AXI AD9671 ` IP core can be used to interface the :adi:`AD9671` Octal Ultrasound AFE with digital demodulator. An AXI Memory Map interface is used for configuration. -Data is received from Xilinx JESD IP. +Data is received from AMD Xilinx JESD IP. More about the generic framework interfacing ADCs can be read in :ref:`axi_adc`. From 5a91f1ce1ed4b53d2a642c0c70ed934fcae02e17 Mon Sep 17 00:00:00 2001 From: Iulia Moldovan Date: Mon, 18 Nov 2024 15:06:23 +0200 Subject: [PATCH 02/10] docs/library: Fixes and cleanup * Remove trailing whitespaces * Fix lists indentation * Replace links with roles where possible Signed-off-by: Iulia Moldovan --- docs/library/axi_ad9144/index.rst | 4 ++-- docs/library/axi_ad9371/index.rst | 2 +- docs/library/axi_ad9963/index.rst | 2 +- docs/library/axi_laser_driver/index.rst | 6 +++--- docs/library/axi_pwm_gen/index.rst | 2 +- docs/library/axi_sysid/index.rst | 2 +- docs/library/common/ad_dds/index.rst | 4 ++-- docs/library/corundum/index.rst | 4 ++-- docs/library/data_offload/index.rst | 2 +- docs/library/index.rst | 2 +- docs/library/spi_engine/index.rst | 2 +- docs/library/spi_engine/instruction-format.rst | 6 +++--- docs/library/spi_engine/tutorial.rst | 6 +++--- docs/library/util_axis_fifo_asym/index.rst | 2 +- docs/library/util_extract/index.rst | 2 +- docs/library/util_pack/util_cpack2.rst | 2 +- docs/library/util_pack/util_upack2.rst | 2 +- docs/library/util_rfifo/index.rst | 2 +- docs/library/util_var_fifo/index.rst | 2 +- docs/library/util_wfifo/index.rst | 2 +- docs/library/xilinx/index.rst | 2 +- 21 files changed, 30 insertions(+), 30 deletions(-) diff --git a/docs/library/axi_ad9144/index.rst b/docs/library/axi_ad9144/index.rst index f09338d166..0f6b146dfb 100644 --- a/docs/library/axi_ad9144/index.rst +++ b/docs/library/axi_ad9144/index.rst @@ -161,9 +161,9 @@ Software Support * :git-linux:`2019_R2:arch/arm64/boot/dts/xilinx/adi-ad9144-fmc-ebz.dtsi` * :git-linux:`2019_R2:arch/arm64/boot/dts/xilinx/zynqmp-zcu102-rev10-ad9144-fmc-ebz.dts` - + * No-OS device driver at: - + * :git-no-os:`2019_r2:drivers/dac/ad9144/ad9144.c` * :git-no-os:`2019_r2:drivers/dac/ad9144/iio_ad9144.c` diff --git a/docs/library/axi_ad9371/index.rst b/docs/library/axi_ad9371/index.rst index 449511b61e..5531f27c7b 100644 --- a/docs/library/axi_ad9371/index.rst +++ b/docs/library/axi_ad9371/index.rst @@ -177,7 +177,7 @@ The axi_ad9371 cores architecture contains: * ADC channel processing modules, one for each channel (receive path supports 4 channels) - + * data processing modules ( DC filter, IQ Correction and Data format control) * ADC Channel register map diff --git a/docs/library/axi_ad9963/index.rst b/docs/library/axi_ad9963/index.rst index 7be93ccc36..a69cbdf5ba 100644 --- a/docs/library/axi_ad9963/index.rst +++ b/docs/library/axi_ad9963/index.rst @@ -248,7 +248,7 @@ Software Support -------------------------------------------------------------------------------- The software for this part can be found as part of the :adi:`ADALM2000` -(or shortly, M2K) reference design. +(or shortly, M2K) reference design. * Linux device driver at :git-linux:`drivers/iio/adc/ad9963.c` diff --git a/docs/library/axi_laser_driver/index.rst b/docs/library/axi_laser_driver/index.rst index 0046ab1c8c..103a43d3bf 100644 --- a/docs/library/axi_laser_driver/index.rst +++ b/docs/library/axi_laser_driver/index.rst @@ -71,17 +71,17 @@ Interface signal can be used for preconditioning various IPs of the data path. * - tia_chsel - Control lines for the TIA channel multiplexer. - * - irq + * - irq - Interrupt signal. Register Map -------------------------------------------------------------------------------- .. hdl-regmap:: - :name: AXI_LASER_DRIVER + :name: AXI_LASER_DRIVER References ------------------------------------------------------------------------------- * HDL IP core at :git-hdl:`library/axi_laser_driver` -* :dokuwiki:`AXI Laser Driver on wiki ` \ No newline at end of file +* :dokuwiki:`AXI Laser Driver on wiki ` diff --git a/docs/library/axi_pwm_gen/index.rst b/docs/library/axi_pwm_gen/index.rst index 85d84715eb..02617041c6 100644 --- a/docs/library/axi_pwm_gen/index.rst +++ b/docs/library/axi_pwm_gen/index.rst @@ -285,4 +285,4 @@ References -------------------------------------------------------------------------------- * HDL IP core at :git-hdl:`library/axi_pwm_gen` -* :dokuwiki:`AXI PWM GEN on wiki ` \ No newline at end of file +* :dokuwiki:`AXI PWM GEN on wiki ` diff --git a/docs/library/axi_sysid/index.rst b/docs/library/axi_sysid/index.rst index 7aa9f32416..7f685dc6d0 100644 --- a/docs/library/axi_sysid/index.rst +++ b/docs/library/axi_sysid/index.rst @@ -251,4 +251,4 @@ References -------------------------------------------------------------------------------- * HDL IP core at :git-hdl:`library/axi_sysid` and :git-hdl:`library/sysid_rom` -* :dokuwiki:`System ID on wiki ` \ No newline at end of file +* :dokuwiki:`System ID on wiki ` diff --git a/docs/library/common/ad_dds/index.rst b/docs/library/common/ad_dds/index.rst index 4ca4ee5e6c..b46d058935 100644 --- a/docs/library/common/ad_dds/index.rst +++ b/docs/library/common/ad_dds/index.rst @@ -329,5 +329,5 @@ References -------------------------------------------------------------------------------- * HDL IP core at :git-hdl:`library/common/ad_dds.v` and :git-hdl:`library/common/ad_dds_1.v` - and :git-hdl:`library/common/ad_dds_2.v` -* :dokuwiki:`Direct digital synthesis on wiki ` \ No newline at end of file + and :git-hdl:`library/common/ad_dds_2.v` +* :dokuwiki:`Direct digital synthesis on wiki ` diff --git a/docs/library/corundum/index.rst b/docs/library/corundum/index.rst index 7b5d29fd5f..66d7fda131 100644 --- a/docs/library/corundum/index.rst +++ b/docs/library/corundum/index.rst @@ -58,7 +58,7 @@ and it needs to be cloned alongside this repository. - J- A. Forencich, System-Level Considerations for Optical Switching in Data Center Networks. (`Thesis`_) .. _FCCM Paper: https://www.cse.ucsd.edu/~snoeren/papers/corundum-fccm20.pdf -.. _FCCM Presentation: https://www.fccm.org/past/2020/forums/topic/corundum-an-open-source-100-gbps-nic/ +.. _FCCM Presentation: https://www.fccm.org/past/2020/forums/topic/corundum-an-open-source-100-gbps-nic/ .. _Thesis: https://escholarship.org/uc/item/3mc9070t References @@ -67,4 +67,4 @@ References * HDL IP core at :git-hdl:`library/corundum` * HDL project at :git-hdl:`projects/ad_gmsl2eth_sl` * :ref:`ad_gmsl2eth_sl` -* :adi:`AD-GMSL2ETH-SL` \ No newline at end of file +* :adi:`AD-GMSL2ETH-SL` diff --git a/docs/library/data_offload/index.rst b/docs/library/data_offload/index.rst index 79417da7ad..b73ad910cb 100644 --- a/docs/library/data_offload/index.rst +++ b/docs/library/data_offload/index.rst @@ -494,4 +494,4 @@ References -------------------------------------------------------------------------------- * HDL IP core at :git-hdl:`library/data_offload` -* :dokuwiki:`Data Offload Engine on wiki ` \ No newline at end of file +* :dokuwiki:`Data Offload Engine on wiki ` diff --git a/docs/library/index.rst b/docs/library/index.rst index c5bc6c3262..126b883779 100644 --- a/docs/library/index.rst +++ b/docs/library/index.rst @@ -107,4 +107,4 @@ available sources can be found in the same archive. axi_ad9144/index axi_ad9371/index axi_ad9643/index - axi_ad9671/index \ No newline at end of file + axi_ad9671/index diff --git a/docs/library/spi_engine/index.rst b/docs/library/spi_engine/index.rst index f9c2b53c72..1fbdc832e9 100644 --- a/docs/library/spi_engine/index.rst +++ b/docs/library/spi_engine/index.rst @@ -109,4 +109,4 @@ References -------------------------------------------------------------------------------- * HDL IP core at :git-hdl:`library/spi_engine` -* :dokuwiki:`SPI Engine on wiki ` \ No newline at end of file +* :dokuwiki:`SPI Engine on wiki ` diff --git a/docs/library/spi_engine/instruction-format.rst b/docs/library/spi_engine/instruction-format.rst index d959142883..11aec5b211 100644 --- a/docs/library/spi_engine/instruction-format.rst +++ b/docs/library/spi_engine/instruction-format.rst @@ -201,7 +201,7 @@ The CS Invert Mask Instructions allows the user to select on a per-pin basis whether the Chip Select will be active-low (default) or active-high (inverted). Note that the Chip-Select instructions should remain the same because the value of CS is inverted at the output register, and additional logic (e.g. reset -counters) occurs when the CS active state is asserted. +counters) occurs when the CS active state is asserted. Since the physical values on the pins are inverted at the output, the current Invert Mask does not affect the use of the :ref:`spi_engine cs-instruction`. As @@ -226,9 +226,9 @@ version 1.02.00 of the core. - reserved - Reserved for future use. Must always be set to 0. * - m - - Mask + - Mask - Mask for selecting inverted CS channels. For the bits set to 1, the - corresponding channel will be inverted at the output. + corresponding channel will be inverted at the output. .. _spi_engine configuration-registers: diff --git a/docs/library/spi_engine/tutorial.rst b/docs/library/spi_engine/tutorial.rst index b086972896..3f892fd382 100644 --- a/docs/library/spi_engine/tutorial.rst +++ b/docs/library/spi_engine/tutorial.rst @@ -6,7 +6,7 @@ SPI Engine Tutorial - PulSAR-ADC The goal of this tutorial is to present the process of adding :ref:`spi_engine` support for an ADI precision converter or family of converters using a few simple steps. -The target carrier is the Digilent Cora-z7s board using a PMOD connector. +The target carrier is the Digilent Cora Z7S board using a PMOD connector. Evaluating the target device -------------------------------------------------------------------------------- @@ -18,7 +18,7 @@ They all share the same interface and the same PCB, the differences being found in their performance. The table below offers a comparison between the timing parameters of the SPI interface for these devices. Using this table we can see how much they have in common and where the key differences are. All the values -are for 3.3V VIO since the Cora-z7s is only 3.3V capable. +are for 3.3V VIO since the Cora Z7S is only 3.3V capable. +----------+----------+------+----------+----------+----------+----------+ | Device | Re | KSPS | T\_ | T_CONV | T_CYC | T_ACQ | @@ -165,7 +165,7 @@ Key timing characteristics: 750 ns T_CYC 500 ns T_CONV 250 ns T_ACQ - 12 ns T_SCLK @ >3V VIO (cora pmod is 3V3) + 12 ns T_SCLK @ >3V VIO (Cora PMOD is 3V3) Sample rate control ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/library/util_axis_fifo_asym/index.rst b/docs/library/util_axis_fifo_asym/index.rst index baa1d8c43e..34c3e9558a 100644 --- a/docs/library/util_axis_fifo_asym/index.rst +++ b/docs/library/util_axis_fifo_asym/index.rst @@ -178,4 +178,4 @@ References -------------------------------------------------------------------------------- * HDL IP core at :git-hdl:`library/util_axis_fifo_asym` -* :dokuwiki:`Asymmetric AXI Stream FIFO Core on wiki ` \ No newline at end of file +* :dokuwiki:`Asymmetric AXI Stream FIFO Core on wiki ` diff --git a/docs/library/util_extract/index.rst b/docs/library/util_extract/index.rst index 40f83ae7a6..5ed0290ed3 100644 --- a/docs/library/util_extract/index.rst +++ b/docs/library/util_extract/index.rst @@ -59,4 +59,4 @@ References -------------------------------------------------------------------------------- * HDL IP core at :git-hdl:`library/util_extract/util_extract.v` -* :dokuwiki:`UTIL EXTRACT on wiki ` \ No newline at end of file +* :dokuwiki:`UTIL EXTRACT on wiki ` diff --git a/docs/library/util_pack/util_cpack2.rst b/docs/library/util_pack/util_cpack2.rst index 7c3386ad5e..3045f7facb 100644 --- a/docs/library/util_pack/util_cpack2.rst +++ b/docs/library/util_pack/util_cpack2.rst @@ -86,4 +86,4 @@ or 16 bits. References -------------------------------------------------------------------------------- -* HDL IP core at :git-hdl:`library/util_pack/util_cpack2` \ No newline at end of file +* HDL IP core at :git-hdl:`library/util_pack/util_cpack2` diff --git a/docs/library/util_pack/util_upack2.rst b/docs/library/util_pack/util_upack2.rst index 147460d7e4..02abca80e9 100644 --- a/docs/library/util_pack/util_upack2.rst +++ b/docs/library/util_pack/util_upack2.rst @@ -89,4 +89,4 @@ initiates a read from the DMA three out of four clock cycles. References -------------------------------------------------------------------------------- -* HDL IP core at :git-hdl:`library/util_pack/util_upack2` \ No newline at end of file +* HDL IP core at :git-hdl:`library/util_pack/util_upack2` diff --git a/docs/library/util_rfifo/index.rst b/docs/library/util_rfifo/index.rst index 12d99a43e0..ce2cc360b2 100644 --- a/docs/library/util_rfifo/index.rst +++ b/docs/library/util_rfifo/index.rst @@ -102,4 +102,4 @@ References -------------------------------------------------------------------------------- * HDL IP core at :git-hdl:`library/util_rfifo` -* :dokuwiki:`UTIL RFIFO on wiki ` \ No newline at end of file +* :dokuwiki:`UTIL RFIFO on wiki ` diff --git a/docs/library/util_var_fifo/index.rst b/docs/library/util_var_fifo/index.rst index d61eef296f..935d5ec05a 100644 --- a/docs/library/util_var_fifo/index.rst +++ b/docs/library/util_var_fifo/index.rst @@ -89,4 +89,4 @@ References -------------------------------------------------------------------------------- * HDL IP core at :git-hdl:`library/util_var_fifo` -* :dokuwiki:`UTIL VAR FIFO on wiki ` \ No newline at end of file +* :dokuwiki:`UTIL VAR FIFO on wiki ` diff --git a/docs/library/util_wfifo/index.rst b/docs/library/util_wfifo/index.rst index e75e47c12f..5935db2a55 100644 --- a/docs/library/util_wfifo/index.rst +++ b/docs/library/util_wfifo/index.rst @@ -85,4 +85,4 @@ Interface References -------------------------------------------------------------------------------- -* HDL IP core at :git-hdl:`library/util_wfifo` \ No newline at end of file +* HDL IP core at :git-hdl:`library/util_wfifo` diff --git a/docs/library/xilinx/index.rst b/docs/library/xilinx/index.rst index 8a1b418257..e3c8da200f 100644 --- a/docs/library/xilinx/index.rst +++ b/docs/library/xilinx/index.rst @@ -8,5 +8,5 @@ Contents .. toctree:: :maxdepth: 2 - + UTIL_ADXCVR From 00a1cb0a620508c134eb30c67bfa37b751efce0e Mon Sep 17 00:00:00 2001 From: Iulia Moldovan Date: Tue, 19 Nov 2024 09:35:29 +0200 Subject: [PATCH 03/10] docs/user_guide: Fixes and cleanup * Remove trailing whitespaces * Fix lists indentation * Replace links with roles where possible * Replace code-block with shell directive where needed * build_intel_boot_image: * Add links to the device trees of the respective projects * Fix lists indentation Signed-off-by: Iulia Moldovan --- docs/user_guide/architecture.rst | 30 ++-- docs/user_guide/build_boot_bin.rst | 4 +- docs/user_guide/build_hdl.rst | 156 ++++++++++-------- docs/user_guide/build_intel_boot_image.rst | 165 ++++++++++--------- docs/user_guide/docs_guidelines.rst | 52 +++--- docs/user_guide/ip_cores/creating_new_ip.rst | 2 +- docs/user_guide/ip_cores/use_adi_ips.rst | 9 +- docs/user_guide/porting_project.rst | 8 +- 8 files changed, 229 insertions(+), 197 deletions(-) diff --git a/docs/user_guide/architecture.rst b/docs/user_guide/architecture.rst index e89d1a1621..2d68d6cfce 100644 --- a/docs/user_guide/architecture.rst +++ b/docs/user_guide/architecture.rst @@ -40,7 +40,7 @@ Take :adi:`AD-FMCOMMS2 ` with :xilinx:`ZedBoard `; the ``system_bd.tcl`` will look like the following: -.. code-block:: bash +.. shell:: source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl source ../common/fmcomms2_bd.tcl @@ -315,25 +315,25 @@ AMD platforms - FMC connector 2 - VADJ FMC connector - Family - * - `AC701 `__ ** + * - :xilinx:`AC701` ** - JTAG - HPC (2 GTP @ 6.6 Gbps) - --- - 3.3V/**\*2.5V**/1.8V - Artix-7 - * - `Cora Z7-07S `__ + * - :xilinx:`Cora Z7S ` - SD card - --- - --- - --- - Zynq-7000 - * - `KC705 `__ + * - :xilinx:`KC705` - JTAG - HPC (4 GTX @ 10.3125 Gbps) - LPC (1 GTX @ 10.3125 Gbps) - 3.3V/**\*2.5V**/1.8V - Kintex-7 - * - `KCU105 `__ + * - :xilinx:`KCU105` - JTAG - HPC (8 GTH @ 16.3 Gbps) - LPC (1 GTH @ 16.3 Gbps) @@ -345,61 +345,61 @@ AMD platforms - --- - --- - Zynq-7000 - * - `VC707 `__ + * - :xilinx:`VC707` - JTAG - HPC (8 GTX @ 12.5 Gbps) - HPC (8 GTX @ 12.5 Gbps) - **\*1.8V**/1.5V/1.2V - Virtex-7 - * - `VC709 `__ ** + * - :xilinx:`VC709` ** - JTAG - HPC (10 GTH @ 13.1 Gbps) - --- - **\*1.8V** - Virtex-7 - * - `VCK190 `__ + * - :xilinx:`VCK190` - SD card - FMC+ (12 GTY @ 28.21 Gbps) - FMC+ (12 GTY @ 28.21 Gbps) - **\*1.5V**/1.2V - Versal AI Core - * - `VCU118 `__ + * - :xilinx:`VCU118` - JTAG - FMC+ (24 GTY @ 28.21 Gbps) - LPC - **\*1.8V**/1.5V/1.2V - Virtex UltraScale+ - * - `VCU128 `__ + * - :xilinx:`VCU128` - JTAG - FMC+ (24 GTY @ 28.21 Gbps) - --- - **\*1.8V**/1.5V/1.2V - Virtex UltraScale+ HBM - * - `VMK180 `__ + * - :xilinx:`VMK180` - SD card - FMC+ (12 GTY @ 28.21 Gbps) - FMC+ (12 GTY @ 28.21 Gbps) - **\*1.5V**/1.2V - Versal Prime Series - * - `VPK180 `__ + * - :xilinx:`VPK180` - SD card - FMC+ (8 GTYP @ 32.75 Gbps) - --- - **\*1.5V**/1.2V - Versal Premium - * - `ZC702 `__ + * - :xilinx:`ZC702` - SD card - LPC - LPC - 3.3V/**\*2.5V**/1.8V - Zynq-7000 - * - `ZC706 `__ + * - :xilinx:`ZC706` - SD card - HPC (8 GTX @ 10.3125 Gbps) - LPC (1 GTX @ 10.3125 Gbps) - 3.3V/**\*2.5V**/1.8V - Zynq-7000 - * - `ZCU102 `__ + * - :xilinx:`ZCU102` - SD card - HPC (8 GTH @ 16.3 Gbps) - HPC (8 GTH @ 16.3 Gbps) diff --git a/docs/user_guide/build_boot_bin.rst b/docs/user_guide/build_boot_bin.rst index 270d30fccd..c522987694 100644 --- a/docs/user_guide/build_boot_bin.rst +++ b/docs/user_guide/build_boot_bin.rst @@ -45,7 +45,7 @@ The script can take 3 parameters: - the ``name`` of the tar.gz output archive (``name``.tar.gz) (**optional**); see the note below. -.. shell:: +.. shell:: bash $build_boot_bin.sh system_top.xsa u-boot.elf [output-archive] @@ -97,7 +97,7 @@ The script can take 4 parameters: - the ``name`` of the tar.gz output archive (``name``.tar.gz) (**optional**); see the note below. -.. shell:: +.. shell:: bash $build_zynqmp_boot_bin.sh system_top.xsa u-boot.elf (download | bl31.elf | ) [output-archive] diff --git a/docs/user_guide/build_hdl.rst b/docs/user_guide/build_hdl.rst index 7fa0597133..4a0ceda4b8 100644 --- a/docs/user_guide/build_hdl.rst +++ b/docs/user_guide/build_hdl.rst @@ -95,7 +95,7 @@ the repository. This is the best method to get the sources. Here, we are cloning the repository inside a directory called **adi**. Please refer to the :ref:`git_repository` section for more details. -.. shell:: +.. shell:: bash $git clone git@github.com:analogdevicesinc/hdl.git @@ -118,16 +118,16 @@ HDL repo. The **main** branch always points to the latest stable release branch, but it also has features **that are not fully tested**. If you want to switch to any other branch you need to checkout that branch: -.. shell:: +.. shell:: bash - $cd hdl + ~/hdl $git checkout hdl_2022_r2 If this is your first time cloning, you have the latest source files. If not, you can simply pull the latest sources using ``git pull`` or ``git rebase`` if you have local changes. -.. shell:: +.. shell:: bash ~/hdl $git fetch origin # shows what changes will be pulled on your local copy @@ -152,7 +152,7 @@ method in your **~/.bashrc** file as follows: .. code-block:: bash - XVERSION=2023.1 + XVERSION=2023.2 load_amd () { source /opt/Xilinx/Vivado/$XVERSION/settings64.sh @@ -164,14 +164,13 @@ method in your **~/.bashrc** file as follows: .bashrc files outside of wrapper methods, as multiple vendor environments may conflict with each other. - Then, `re-source your bashrc `__ for the current session (or open a new one) and call the defined method: -.. code-block:: bash +.. shell:: bash - source ~/.bashrc - load_amd + $source ~/.bashrc + $load_amd Check out the following sections for the paths you need to export. @@ -186,21 +185,30 @@ package name. Change the path and the tool version accordingly to your installation! -.. code-block:: bash - :linenos: +For AMD Xilinx Vivado: - # for AMD Xilinx - source /opt/Xilinx/Vivado/202x.x/settings64.sh +.. shell:: bash - export PATH=$PATH:/opt/Xilinx/Vivado/202x.x/bin:/opt/Xilinx/Vitis/202x.x/bin - export PATH=$PATH:/opt/Xilinx/Vitis/202x.x/gnu/microblaze/nt/bin + ~/hdl + $source /opt/Xilinx/Vivado/202x.x/settings64.sh + + $export PATH=$PATH:/opt/Xilinx/Vivado/202x.x/bin:/opt/Xilinx/Vitis/202x.x/bin + $export PATH=$PATH:/opt/Xilinx/Vitis/202x.x/gnu/microblaze/nt/bin - # for Intel - export PATH=$PATH:/opt/intelFPGA_pro/2x.x/quartus/bin +For Intel Quartus: - # for Lattice - export PATH=$PATH:/opt/lscc/propel/202x.x/builder/rtf/bin/lin64 - export PATH=$PATH:/opt/lscc/radiant/202x.x/bin/lin64 +.. shell:: bash + + ~/hdl + $export PATH=$PATH:/opt/intelFPGA_pro/2x.x/quartus/bin + +For Lattice: + +.. shell:: bash + + ~/hdl + $export PATH=$PATH:/opt/lscc/propel/202x.x/builder/rtf/bin/lin64 + $export PATH=$PATH:/opt/lscc/radiant/202x.x/bin/lin64 3b. Windows environment setup ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -213,29 +221,36 @@ and command-line interface for Microsoft Windows. Change the path and the tool version accordingly to your installation! -For example: +For AMD Xilinx Vivado: -.. code-block:: bash - :linenos: +.. shell:: bash - # for AMD Xilinx - source /cygdrive/path_to/Xilinx/Vivado/202x.x/settings64.sh + ~/hdl + $source /cygdrive/path_to/Xilinx/Vivado/202x.x/settings64.sh + + $export PATH=$PATH:/cygdrive/c/Xilinx/Vivado/202x.x/bin + $export PATH=$PATH:/cygdrive/c/Xilinx/Vivado_HLS/202x.x/bin + $export PATH=$PATH:/cygdrive/c/Xilinx/Vitis/202x.x/bin + $export PATH=$PATH:/cygdrive/c/Xilinx/Vitis/202x.x/gnu/microblaze/nt/bin + $export PATH=$PATH:/cygdrive/c/Xilinx/Vitis/202x.x/gnu/arm/nt/bin + $export PATH=$PATH:/cygdrive/c/Xilinx/Vitis/202x.x/gnu/microblaze/linux_toolchain/nt64_be/bin + $export PATH=$PATH:/cygdrive/c/Xilinx/Vitis/202x.x/gnu/microblaze/linux_toolchain/nt64_le/bin + $export PATH=$PATH:/cygdrive/c/Xilinx/Vitis/202x.x/gnu/aarch32/nt/gcc-arm-none-eabi/bin - export PATH=$PATH:/cygdrive/c/Xilinx/Vivado/202x.x/bin - export PATH=$PATH:/cygdrive/c/Xilinx/Vivado_HLS/202x.x/bin - export PATH=$PATH:/cygdrive/c/Xilinx/Vitis/202x.x/bin - export PATH=$PATH:/cygdrive/c/Xilinx/Vitis/202x.x/gnu/microblaze/nt/bin - export PATH=$PATH:/cygdrive/c/Xilinx/Vitis/202x.x/gnu/arm/nt/bin - export PATH=$PATH:/cygdrive/c/Xilinx/Vitis/202x.x/gnu/microblaze/linux_toolchain/nt64_be/bin - export PATH=$PATH:/cygdrive/c/Xilinx/Vitis/202x.x/gnu/microblaze/linux_toolchain/nt64_le/bin - export PATH=$PATH:/cygdrive/c/Xilinx/Vitis/202x.x/gnu/aarch32/nt/gcc-arm-none-eabi/bin +For Intel Quartus: - # for Intel - export PATH=$PATH:/cygdrive/c/intelFPGA_pro/2x.x/quartus/bin64 +.. shell:: bash + + ~/hdl + $export PATH=$PATH:/cygdrive/c/intelFPGA_pro/2x.x/quartus/bin64 - # for Lattice - export PATH=$PATH:/cygdrive/c/lscc/propel/202x.x/builder/rtf/bin/nt64 - export PATH=$PATH:/cygdrive/c/lscc/radiant/202x.x/bin/nt64 +For Lattice: + +.. shell:: bash + + ~/hdl + $export PATH=$PATH:/cygdrive/c/lscc/propel/202x.x/builder/rtf/bin/nt64 + $export PATH=$PATH:/cygdrive/c/lscc/radiant/202x.x/bin/nt64 .. collapsible:: Alternatives to Cygwin/Linux terminal @@ -258,7 +273,7 @@ For example: Use the ``which`` command to locate the command which would be executed in the current environment, for example: -.. shell:: +.. shell:: bash $which git /usr/bin/git @@ -317,7 +332,7 @@ A generic path where you want to build the project would look like: **EXAMPLE**: Here we are building the **DAQ2** project on the **ZC706** carrier. -.. shell:: +.. shell:: bash ~/hdl $cd projects/daq2/zc706 @@ -367,7 +382,7 @@ the ``ADI_USE_OOC_SYNTHESIS`` system variable. By setting the maximum parallel out-of-context synthesis jobs. If not set, the default parallel job number is set to 4. -.. shell:: +.. shell:: bash ~/hdl $export ADI_USE_OOC_SYNTHESIS=y @@ -392,7 +407,7 @@ project in OOC mode since the cache is not cleared as with normal compile flow. Set: - .. shell:: + .. shell:: bash ~/hdl $export ADI_USE_OOC_SYNTHESIS=n @@ -408,19 +423,19 @@ commands are in the source Tcl file and output is redirected to a log file. In the below example that is **axi_ad7768_ip.log** inside the **library/axi_ad7768** directory. -.. shell:: +.. shell:: bash ~/hdl $make -C library/axi_ad7768 - make[1]: Entering directory '/path/to/hdl/library/axi_ad7768' - rm -rf *.cache *.data *.xpr *.log component.xml *.jou xgui *.ip_user_files *.srcs *.hw *.sim .Xil - vivado -mode batch -source axi_ad7768_ip.tcl >> axi_ad7768_ip.log 2>&1 + make[1]: Entering directory '/path/to/hdl/library/axi_ad7768' + rm -rf *.cache *.data *.xpr *.log component.xml *.jou xgui *.ip_user_files *.srcs *.hw *.sim .Xil + vivado -mode batch -source axi_ad7768_ip.tcl >> axi_ad7768_ip.log 2>&1 If the ``make`` command returns an error (and stops), **you must first check the contents of the log file**. You may also check the generated files for more information. -.. shell:: +.. shell:: bash ~/hdl $ls -ltr library/axi_ad7768 @@ -434,18 +449,20 @@ It is exactly the same **rule** as the library component. The log file, in this example, is called **daq2_zc706_vivado.log** and is inside the **projects/daq2/zc706** directory. -.. shell:: +.. shell:: bash + ~/hdl/projects/daq2/zc706 $make - [ -- snip --] - rm -rf *.cache *.data *.xpr *.log *.jou xgui *.runs *.srcs *.sdk *.hw *.sim .Xil *.ip_user_files - vivado -mode batch -source system_project.tcl >> daq2_zc706_vivado.log 2>&1 - make: Leaving directory '/path/to/hdl/projects/daq2/zc706' + [ -- snip --] + rm -rf *.cache *.data *.xpr *.log *.jou xgui *.runs *.srcs *.sdk *.hw *.sim .Xil *.ip_user_files + vivado -mode batch -source system_project.tcl >> daq2_zc706_vivado.log 2>&1 + make: Leaving directory '/path/to/hdl/projects/daq2/zc706' Do a quick (or detailed) check on files. -.. shell:: +.. shell:: bash + ~/hdl $ls -ltr projects/daq2/zc706 $tail projects/daq2/zc706/daq2_zc706_vivado.log @@ -456,8 +473,9 @@ Do a quick (or detailed) check on files. And finally, if the project build is successful, the **system_top.xsa** file should be in the **.sdk** folder. -.. shell:: +.. shell:: bash + ~/hdl $ls -ltr projects/daq2/zc706/daq2_zc706.sdk You may now use this **system_top.xsa** file as the input to your no-OS and/or Linux @@ -490,7 +508,7 @@ Starting with Vivado 2019.3, the output file extension was changed from To create a swap file you can use the following commands: - .. shell:: + .. shell:: bash $sudo fallocate -l "memory size (e.g 1G, 2G, 8G, etc.)" /swapfile $sudo chmod 600 /swapfile @@ -499,13 +517,13 @@ Starting with Vivado 2019.3, the output file extension was changed from If you want to make the change permanent, add this line to */etc/fstab*: - .. code-block:: bash + .. shell:: bash - /swapfile swap swap defaults 0 0 + $/swapfile swap swap defaults 0 0 If you want to deactivate the swap memory: - .. shell:: + .. shell:: bash $sudo swapoff -v /swapfile @@ -562,8 +580,9 @@ A generic path where you want to build the project would look like: **EXAMPLE**: Here we are building the **ADRV9371X** project on the **Arria 10 SoC** carrier. -.. shell:: +.. shell:: bash + ~/hdl $cd projects/adrv9371x/a10soc $make @@ -597,16 +616,18 @@ this contains the most relevant information that you need to provide. Do NOT copy-paste ``make`` command line text -.. shell:: +.. shell:: bash + ~/hdl $ls -ltr projects/adrv9371x/a10soc $tail projects/adrv9371x/a10soc/adrv9371x_a10soc_quartus.log And finally, if the project was built is successfully, the **.sopcinfo** and **.sof** files should be in the same folder. -.. shell:: +.. shell:: bash + ~/hdl $ls -ltr projects/adrv9371x/a10soc/*.sopcinfo $ls -ltr projects/adrv9371x/a10soc/*.sof @@ -642,7 +663,7 @@ The **sof** file is used to program the device. allocate 15 GB of virtual memory, to be able to make a build for the project. To create a swap file you can use the following commands: - .. shell:: + .. shell:: bash $sudo fallocate -l "memory size (e.g 1G, 2G, 8G, etc.)" /swapfile $sudo chmod 600 /swapfile @@ -651,13 +672,13 @@ The **sof** file is used to program the device. If you want to make the change permanent, add this line to */etc/fstab*: - .. code-block:: bash + .. shell:: bash - /swapfile swap swap defaults 0 0 + $/swapfile swap swap defaults 0 0 If you want to deactivate the swap memory: - .. shell:: + .. shell:: bash $sudo swapoff -v /swapfile @@ -733,7 +754,7 @@ axi2apb_bridge AXI4 to APB Bridge 1.1.1 gp_timer Timer-Counter 1.3.0 ==================== ============================= ======= -.. shell:: +.. shell:: bash ~/hdl $cd projects/common/lfcpnx @@ -763,8 +784,9 @@ This contains the most relevant information that you need to provide. Do NOT copy-paste ``make`` command line text! -.. shell:: +.. shell:: bash + ~/hdl $ls -ltr $ls -ltr / $ls -ltr // diff --git a/docs/user_guide/build_intel_boot_image.rst b/docs/user_guide/build_intel_boot_image.rst index 299d272f92..6c983a3124 100644 --- a/docs/user_guide/build_intel_boot_image.rst +++ b/docs/user_guide/build_intel_boot_image.rst @@ -5,7 +5,7 @@ Generating HDL boot image for Intel projects This page is dedicated to the building process of boot image for supported Intel/Altera projects. One key file specific to these projects is -the ``bootloader``. It's role is to initialize the system after the +the ``bootloader``. Its role is to initialize the system after the BootROM runs. It bridges the gap between the limited functionality of the BootROM and the end user application, configuring the system as needed before the larger application can run. @@ -13,9 +13,9 @@ the larger application can run. In the following links you can find more details on the process and the necessary components: -- `Booting and Configuration `__ -- `SocBootFromFPGA `__ -- `Intel Bootloader `__ +- `Booting and Configuration `__ +- `SocBootFromFPGA `__ +- `Intel Bootloader `__ Necessary files for booting up an HDL project ------------------------------------------------------------------------------- @@ -32,24 +32,26 @@ files: - For Arria 10 SoC projects (:ref:`build example `): - - ``/u-boot.img`` - - ``/fit_spl_fpga.itb`` - - ``/extlinux/extlinux.conf`` (keep the directory) - - ``/socfpga_arria10_socdk_sdmmc.dtb`` - - ``/socfpga_arria10-common/zImage`` - - ``/u-boot-splx4.sfp`` (preloader image) + - ``/u-boot.img`` + - ``/fit_spl_fpga.itb`` + - ``/extlinux/extlinux.conf`` (keep the directory) + - ``/socfpga_arria10_socdk_sdmmc.dtb`` + - ``/socfpga_arria10-common/zImage`` + - ``/u-boot-splx4.sfp`` (preloader image) -- For Cyclone5 SoC project (build examples: :ref:`Terasic C5 `, :ref:`DE10Nano `): +- For Cyclone5 SoC project (build examples: + :ref:`Terasic C5 `, + :ref:`DE10Nano `): - - ``/u-boot.scr`` - - ``/soc_system.rbf`` - - ``/extlinux/extlinux.conf`` (keep the directory) - - ``/socfpga_arria10-common/socfpga.dtb`` - - ``/zImage`` - - ``/u-boot-with-spl.sfp`` (preloader image) + - ``/u-boot.scr`` + - ``/soc_system.rbf`` + - ``/extlinux/extlinux.conf`` (keep the directory) + - ``/socfpga_arria10-common/socfpga.dtb`` + - ``/zImage`` + - ``/u-boot-with-spl.sfp`` (preloader image) .. note:: - + Some files, like **fit_spl_fpga.itb** or **extlinux**, were introduced later in the Intel boot flow with the U-Boot image update. @@ -61,7 +63,7 @@ can be obtained from :dokuwiki:`here `. .. note:: - + Make sure to always use the latest version of Kuiper Linux. If the desired project is not supported anymore, use the last version of Kuiper where it's present. @@ -78,7 +80,7 @@ Supposing your host is a Linux system, your carrier is an Arria10, the eval board/project is AD9081 and you are using the built files from the Kuiper image mounted at ``/mnt/BOOT``, then you would: -.. shell:: +.. shell:: bash $cd /mnt/BOOT $cp socfpga_arria10_socdk_ad9081/u-boot.img . @@ -92,14 +94,14 @@ Writing the boot preloader partition requires special attention, first look for the device with BOOT mountpoint and annotate the third partition from the same device: -.. code-block:: bash +.. shell:: bash - lsblk + $lsblk Then, clear the partition with zeros and write the preloader image (in this example, Arria10 SoC's *./u-boot-splx4.sfp*): -.. shell:: +.. shell:: bash :no-path: $DEV=mmcblk0p3 @@ -119,7 +121,7 @@ Then, clear the partition with zeros and write the preloader image The snippet below can infer the device based on the *BOOT* partition mountpoint - .. shell:: + .. shell:: bash $DEV=$(lsblk | sed -n 's/.*\(\b[s][d-z][a-z][0-9]\)\s*.*\/BOOT/\1/p' | sed 's/^\(...\).*/\1/') $if [ -z "$DEV" ] ; then \ @@ -142,9 +144,9 @@ the other). built. Follow these instructions to write the file to your SD card, depending on the operating system that you use (Windows or Linux): - - :dokuwiki:`[Wiki] Building the Intel SoC-FPGA kernel and devicetrees from source ` - - :dokuwiki:`[Wiki] Linux Download and setting up the image ` - - :dokuwiki:`[Wiki] Formatting and Flashing SD Cards using Windows ` + - :dokuwiki:`[Wiki] Building the Intel SoC-FPGA kernel and devicetrees from source ` + - :dokuwiki:`[Wiki] Linux Download and setting up the image ` + - :dokuwiki:`[Wiki] Formatting and Flashing SD Cards using Windows ` Proceed by cloning the repository, setting the environment to an ARM architecture cross compiler, build the configuration file, build the Kernel image, and @@ -152,20 +154,19 @@ lastly build the device tree (specific to each combination of carrier and eval board). You may notice that in the ``export CROSS_COMPILE`` examples there is a -"trailing" dash ``-``, and the reason for this is because an export: +"trailing" dash ``-``. That is because within the Makeiles, this path becomes +/path/to/arm-linux-gnueabihf-gcc (with ``gcc`` appended). -.. shell:: +.. shell:: bash $export CROSS_COMPILE=/path/to/arm-linux-gnueabihf- -Within the Makefiles, this path becomes /path/to/arm-linux-gnueabihf-gcc -(with ``gcc`` added at the end). If your environment already has the compiler in the path (test if :code:`which arm-linux-gnueabihf-gcc` returns the expected path), you can set ``CROSS_COMPILE`` to: -.. shell:: +.. shell:: bash $export CROSS_COMPILE=arm-linux-gnueabihf- @@ -185,15 +186,15 @@ support and may not be available in your default package manager. ADRV9371/Arria 10 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- HDL Project: :git-hdl:`projects/adrv9371x/a10soc` -- ADI's Linux kernel: :git-linux:`here <>` +- HDL Project: :git-hdl:`projects/adrv9371x/a10soc` +- ADI's Linux kernel: :git-linux:`arch/arm/boot/dts/socfpga_arria10_socdk_adrv9371.dts` Building the Linux Kernel image and the Devicetree ``````````````````````````````````````````````````````````````````````````````` **Linux/Cygwin/WSL** -.. shell:: +.. shell:: bash $git clone https://github.com/analogdevicesinc/linux.git $cd linux/ @@ -212,7 +213,7 @@ Building the Hardware Design Clone the HDL repository, then build the project: -.. shell:: +.. shell:: bash $git clone https://github.com/analogdevicesinc/hdl.git $cd hdl/projects/adrv9371x/a10soc @@ -229,7 +230,7 @@ compiler environment variables. Pay attention to directoy changes to where the commands are run from, and always confirm with ``pwd`` to show the current path at you terminal. -.. shell:: +.. shell:: bash :no-path: $cd ~/hdl/projects/adrv9371x/a10soc ; pwd @@ -240,7 +241,7 @@ compiler environment variables. Building the Preloader and Bootloader Image ``````````````````````````````````````````````````````````````````````````````` -This flow applies starting with release :git-hdl:`2021_R1` / +This flow applies starting with release :git-hdl:`2021_R1 ` / Quartus Pro version 20.1. For older versions of the flow see previous versions of this page on wiki :dokuwiki:`Altera SOC Quick Start Guide `. @@ -248,7 +249,7 @@ of this page on wiki In the HDL project directory, create the ``software/bootloader`` folder and clone the ``u-boot-socfpga`` image: -.. shell:: +.. shell:: bash :no-path: $cd ~/hdl/projects/adrv9371x/a10soc ; pwd @@ -259,7 +260,7 @@ clone the ``u-boot-socfpga`` image: Then run the qts filter and build the preloader and bootloader images: -.. shell:: +.. shell:: bash :no-path: $cd ~/hdl/projects/adrv9371x/a10soc/software/bootloader ; pwd @@ -274,7 +275,7 @@ Then run the qts filter and build the preloader and bootloader images: Create the SPL image: -.. shell:: +.. shell:: bash :no-path: $cd ~/hdl/projects/adrv9371x/a10soc/software/bootloader/u-boot-socfpga ; pwd @@ -288,7 +289,7 @@ Last but not least, create the **extlinux.conf** Linux configuration file, which will be copied to /BOOT partition of the SD Card, in a folder named ``extlinux``: -.. shell:: +.. shell:: bash :no-path: $cd ~/hdl/projects/adrv9371x/a10soc/software/bootloader/u-boot-socfpga ; pwd @@ -312,7 +313,7 @@ device mountpoints accordingly Flash the SD Card with the Kuiper Linux image: -.. shell:: +.. shell:: bash $time sudo dd if=./2023-12-13-ADI-Kuiper-full.img of=/dev/sdz status=progress bs=4194304 2952+0 records in @@ -326,7 +327,7 @@ Flash the SD Card with the Kuiper Linux image: Mount the /BOOT partition: -.. shell:: +.. shell:: bash :no-path: $lsblk @@ -347,7 +348,7 @@ Mount the /BOOT partition: Copy the built files to the /BOOT partition: -.. shell:: +.. shell:: bash :no-path: $cd ~/hdl/projects/adrv9371x/a10soc ; pwd @@ -362,7 +363,7 @@ Copy the built files to the /BOOT partition: Unmount the /BOOT partition: -.. shell:: +.. shell:: bash :no-path: $sudo umount /dev/sdz1 @@ -375,7 +376,7 @@ Unmount the /BOOT partition: Flash the preloader boot partition: -.. shell:: +.. shell:: bash :no-path: $cd ~/hdl/projects/adrv9371x/a10soc/software/bootloader/u-boot-socfpga ; pwd @@ -395,15 +396,15 @@ Flash the preloader boot partition: ARRADIO/Terasic C5 SoC ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- HDL Project: :git-hdl:`` -- ADI's Linux kernel: :git-linux:`here <>` +- HDL Project: :git-hdl:`projects/arradio/c5soc` +- ADI's Linux kernel: :git-linux:`arch/arm/boot/dts/socfpga_cyclone5_sockit_arradio.dts` Building the Linux Kernel image and the Devicetree ``````````````````````````````````````````````````````````````````````````````` **Linux/Cygwin/WSL** -.. shell:: +.. shell:: bash $git clone https://github.com/analogdevicesinc/linux.git $cd linux/ @@ -422,7 +423,7 @@ Building the Hardware Design Clone the HDL repository, then build the project: -.. shell:: +.. shell:: bash $git clone https://github.com/analogdevicesinc/hdl.git $cd hdl/projects/arradio/c5soc @@ -439,7 +440,7 @@ compiler environment variables. Pay attention to directory changes to where the commands are run from, and always confirm with ``pwd`` to show the current path at you terminal. -.. shell:: +.. shell:: bash :no-path: $cd ~/hdl/projects/arradio/c5soc ; pwd @@ -450,15 +451,15 @@ compiler environment variables. Building the Preloader and Bootloader Image ``````````````````````````````````````````````````````````````````````````````` -This flow applies starting with release :git-hdl:`2021_R1` / +This flow applies starting with release :git-hdl:`2021_R1 ` / Quartus Pro version 20.1. For older versions of the flow see previous versions of this page on wiki :dokuwiki:`Altera SOC Quick Start Guide `. -In HDL project directory, create the software/bootloader folder and clone the -``u-boot-socfpga`` image. Before that create a new BSP settings file: +In the HDL project directory, create the ``software/bootloader`` folder and +clone the ``u-boot-socfpga`` image. Before that, create a new BSP settings file: -.. shell:: +.. shell:: bash :no-path: $cd ~/hdl/projects/arradio/c5soc ; pwd @@ -475,7 +476,7 @@ In HDL project directory, create the software/bootloader folder and clone the Then run the qts filter and build the preloader and bootloader images: -.. shell:: +.. shell:: bash :no-path: $cd ~/hdl/projects/arradio/c5soc/software/bootloader ; pwd @@ -488,7 +489,7 @@ Then run the qts filter and build the preloader and bootloader images: Make u-boot.scr file - this file shall be copied to /BOOT partition of the SD Card: -.. shell:: +.. shell:: bash :no-path: $cd ~/hdl/projects/arradio/c5soc/software/bootloader/u-boot-socfpga ; pwd @@ -501,7 +502,7 @@ Last but not least, create the **extlinux.conf** Linux configuration file, which will be copied to /BOOT partition of the SD Card, in a folder named ``extlinux``: -.. shell:: +.. shell:: bash :no-path: $cd ~/hdl/projects/arradio/c5soc/software/bootloader/u-boot-socfpga ; pwd @@ -562,7 +563,7 @@ device mountpoints accordingly Flash the SD Card with the Kuiper Linux image: -.. shell:: +.. shell:: bash $time sudo dd if=./2023-12-13-ADI-Kuiper-full.img of=/dev/sdz status=progress bs=4194304 2952+0 records in @@ -576,7 +577,7 @@ Flash the SD Card with the Kuiper Linux image: Mount the /BOOT partition: -.. shell:: +.. shell:: bash :no-path: $lsblk @@ -597,7 +598,7 @@ Mount the /BOOT partition: Copy the built files to the /BOOT partition: -.. shell:: +.. shell:: bash :no-path: $cd ~/hdl/projects/arradio/c5soc ; pwd @@ -612,7 +613,7 @@ Copy the built files to the /BOOT partition: Unmount the /BOOT partition: -.. shell:: +.. shell:: bash :no-path: $sudo umount /dev/sdz1 @@ -625,7 +626,7 @@ Unmount the /BOOT partition: Flash the preloader boot partition: -.. shell:: +.. shell:: bash :no-path: $cd ~/hdl/projects/arradio/c5soc/software/bootloader/u-boot-socfpga ; pwd @@ -645,15 +646,15 @@ Flash the preloader boot partition: CN0540/DE10Nano ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- HDL Project: :git-hdl:`` -- ADI's Linux kernel: :git-linux:`here <>` +- HDL Project: :git-hdl:`projects/cn0540/de10nano` +- ADI's Linux kernel: :git-linux:`arch/arm/boot/dts/socfpga_cyclone5_de10_nano_cn0540.dts` Building the Linux Kernel image and the Devicetree ``````````````````````````````````````````````````````````````````````````````` **Linux/Cygwin/WSL** -.. shell:: +.. shell:: bash $git clone https://github.com/analogdevicesinc/linux.git $cd linux/ @@ -672,7 +673,7 @@ Building the Hardware Design Clone the HDL repository, then build the project: -.. shell:: +.. shell:: bash $git clone https://github.com/analogdevicesinc/hdl.git $cd hdl/projects/cn0540/de10nano @@ -689,7 +690,7 @@ compiler environment variables. Pay attention to directory changes to where the commands are run from, and always confirm with ``pwd`` to show the current path at you terminal. -.. shell:: +.. shell:: bash :no-path: $cd ~/hdl/projects/cn0540/de10nano ; pwd @@ -700,15 +701,15 @@ compiler environment variables. Building the Preloader and Bootloader Image ``````````````````````````````````````````````````````````````````````````````` -This flow applies starting with release :git-hdl:`2021_R1` / +This flow applies starting with release :git-hdl:`2021_R1 ` / Quartus Pro version 20.1. For older versions of the flow see previous versions of this page on wiki :dokuwiki:`Altera SOC Quick Start Guide `. -In HDL project directory, create the software/bootloader folder and clone the -``u-boot-socfpga`` image. Before that create a new BSP settings file: +In the HDL project directory, create the ``software/bootloader`` folder and +clone the ``u-boot-socfpga`` image. Before that, create a new BSP settings file: -.. shell:: +.. shell:: bash :no-path: $cd ~/hdl/projects/cn0540/de10nano ; pwd @@ -725,7 +726,7 @@ In HDL project directory, create the software/bootloader folder and clone the Then run the qts filter and build the preloader and bootloader images: -.. shell:: +.. shell:: bash :no-path: $cd ~/hdl/projects/cn0540/de10nano/software/bootloader ; pwd @@ -738,7 +739,7 @@ Then run the qts filter and build the preloader and bootloader images: Make u-boot.scr file - this file shall be copied to /BOOT partition of the SD Card: -.. shell:: +.. shell:: bash :no-path: $cd ~/hdl/projects/arradio/c5soc/software/bootloader/u-boot-socfpga ; pwd @@ -751,7 +752,7 @@ Last but not least, create the **extlinux.conf** Linux configuration file, which will be copied to /BOOT partition of the SD Card, in a folder named ``extlinux``: -.. shell:: +.. shell:: bash :no-path: $cd ~/hdl/projects/cn0540/de10nano/software/bootloader/u-boot-socfpga ; pwd @@ -775,7 +776,7 @@ device mountpoints accordingly Flash the SD Card with the Kuiper Linux image: -.. shell:: +.. shell:: bash $time sudo dd if=./2023-12-13-ADI-Kuiper-full.img of=/dev/sdz status=progress bs=4194304 2952+0 records in @@ -789,7 +790,7 @@ Flash the SD Card with the Kuiper Linux image: Mount the /BOOT partition: -.. shell:: +.. shell:: bash :no-path: $lsblk @@ -810,7 +811,7 @@ Mount the /BOOT partition: Copy the built files to the /BOOT partition: -.. shell:: +.. shell:: bash :no-path: $cd ~/hdl/projects/cn0540/de10nano ; pwd @@ -825,7 +826,7 @@ Copy the built files to the /BOOT partition: Unmount the /BOOT partition: -.. shell:: +.. shell:: bash :no-path: $sudo umount /dev/sdz1 @@ -838,7 +839,7 @@ Unmount the /BOOT partition: Flash the preloader boot partition: -.. shell:: +.. shell:: bash :no-path: $cd ~/hdl/projects/cn0540/de10nano/software/bootloader/u-boot-socfpga ; pwd @@ -852,4 +853,4 @@ Flash the preloader boot partition: 1697+1 records in 1697+1 records out 868996 bytes (869 kB, 849 KiB) copied, 0.21262 s, 4.1 MB/s - $sync \ No newline at end of file + $sync diff --git a/docs/user_guide/docs_guidelines.rst b/docs/user_guide/docs_guidelines.rst index cc2b5b8784..154bc8f706 100644 --- a/docs/user_guide/docs_guidelines.rst +++ b/docs/user_guide/docs_guidelines.rst @@ -16,22 +16,24 @@ Before creating a new page This section has the sole role to present the steps that are required to be able to create and build a new documentation related page. Some steps are -recommended to be revised regularly to keep the necessary tools updated. +recommended to be revised regularly to keep the necessary tools updated. First, make sure you have the latest version of ``pip`` installed. It must be newer than 23 version. If not, update it by running the following command: -.. code-block:: +.. shell:: bash + :no-path: - pip install pip --upgrade + $pip install pip --upgrade Then install the necessary documentation tools by running (:git-hdl:`HDL <>` repository is the working directory): -.. code-block:: - - cd docs/ - pip install -r requirements.txt --upgrade +.. shell:: bash + + ~/hdl + $cd docs/ + $pip install -r requirements.txt --upgrade Use the same command to regularly update the documentation tools. Specially if something looks broken. @@ -41,18 +43,20 @@ Before building a page, it's recommended to build all the projects from directly taken from the libraries' project folder (e.g.: ``/library/axi_dmac/component.xml``) after being built. Build the libraries by running: -.. code-block:: - - cd library/ - make +.. shell:: bash + + ~/hdl + $cd library/ + $make Now, after the page has been written, inside ``/docs`` folder run the following command: -.. code-block:: - - cd docs/ - make html +.. shell:: bash + + ~/hdl + $cd docs/ + $make html The generated documentation will be available at ``/docs/_build/html``. @@ -62,16 +66,18 @@ This is because Sphinx rebuilds only "touched" pages and, for example, adding a page changes the sidebar navigation for all pages. This is done by running the below commands (inside ``/docs`` folder): -.. code-block:: - - make clean - make html +.. shell:: bash + + ~/hdl/docs + $make clean + $make html Or more straight forward (clean & rebuild): -.. code-block:: - - make clean html +.. shell:: bash + + ~/hdl/docs + $make clean html Make sure to read the next chapters as they provide more info on how to write a HDL specific Sphinx documentation page. @@ -107,7 +113,7 @@ they're not included in any toctree. They are inserted like this: -.. code-block:: +.. code-block:: rst .. include:: ../common/more_information.rst diff --git a/docs/user_guide/ip_cores/creating_new_ip.rst b/docs/user_guide/ip_cores/creating_new_ip.rst index 7c07516e79..53648bccfc 100644 --- a/docs/user_guide/ip_cores/creating_new_ip.rst +++ b/docs/user_guide/ip_cores/creating_new_ip.rst @@ -125,7 +125,7 @@ simulation environment as well. RO Value of the Version is hardcoded in the IP. ENDFIELD - + FIELD [31:0] ID PERIPHERAL_ID diff --git a/docs/user_guide/ip_cores/use_adi_ips.rst b/docs/user_guide/ip_cores/use_adi_ips.rst index 0db2d29f2c..a8865fe485 100644 --- a/docs/user_guide/ip_cores/use_adi_ips.rst +++ b/docs/user_guide/ip_cores/use_adi_ips.rst @@ -5,18 +5,19 @@ Use ADI IPs into your own project Clone the GitHub repository: -.. code:: bash +.. shell:: - git clone https://github.com/analogdevicesinc/hdl.git + $git clone https://github.com/analogdevicesinc/hdl.git Vivado ------------------------------------------------------------------------------- Navigate to hdl/library and build all the libraries -.. code:: bash +.. shell:: - make -C library all + ~/hdl + $make -C library all Launch a Vivado GUI and open the Settings window. Go to IP section and expand it. There you will find a section called Repository. diff --git a/docs/user_guide/porting_project.rst b/docs/user_guide/porting_project.rst index 68cfd393f0..80bb62eef9 100644 --- a/docs/user_guide/porting_project.rst +++ b/docs/user_guide/porting_project.rst @@ -10,7 +10,9 @@ that it would create a tremendous maintenance workload, that would require a lot of human resources, and would increase the required time for testing. The general rule of thumb is to support a given project with a fairly popular -carrier (e.g. ZC706 or A10SoC), which is powerful enough to showcase the board +carrier (e.g. :xilinx:`ZC706` or +:intel:`A10SoC `), +which is powerful enough to showcase the board features and maximum performance. All the HDL projects were designed to maximize source code reuse, minimize @@ -137,7 +139,8 @@ Example with an Intel board ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ In this section, we are presenting all the necessary steps to create a base -design for the Intel Arria 10 SoC development board (abbreviated, `A10SoC`_). +design for the Intel Arria 10 SoC development board (abbreviated, +:intel:`A10SoC `). First, you need to create a new directory in ``hdl/projects/common`` with the name of the carrier. @@ -372,5 +375,4 @@ To create a carrier common FMC connections file: * Two parameters indicating both FMC ports in the desired order for projects that use both FMC connectors. -.. _A10SoC: https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/arria/10-sx.html .. _lfcpnx: https://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/CertusPro-NXEvaluationBoard From cbd356ae1fa1ca48faf2398c2278ef5732da69d1 Mon Sep 17 00:00:00 2001 From: Iulia Moldovan Date: Tue, 12 Nov 2024 08:38:09 +0200 Subject: [PATCH 04/10] docs/user_guide/architecture: Add Intel section Signed-off-by: Iulia Moldovan --- docs/user_guide/architecture.rst | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/docs/user_guide/architecture.rst b/docs/user_guide/architecture.rst index 2d68d6cfce..d115c4d450 100644 --- a/docs/user_guide/architecture.rst +++ b/docs/user_guide/architecture.rst @@ -182,6 +182,14 @@ If the address is between 0x7000_0000 - 0x7FFF_FFFF then the AXI peripherics will be placed in 0xB000_0000 - 0xBFFF_FFFF range by adding 0x4000_0000 to the address. +**Intel** + +Applying to DE10-Nano, C5SoC. + +The address usually (but not always) starts from 0x0002_0000, or the first +available block of a bigger size. In Quartus block design you should be +able to determine it. + SPI ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ From afce7ef3590ac138fad02949ab7e99ebd839bb27 Mon Sep 17 00:00:00 2001 From: Iulia Moldovan Date: Mon, 18 Nov 2024 14:54:30 +0200 Subject: [PATCH 05/10] docs/projects/template: Fixes and cleanup * Fix lists indentation and references * Replace code-block with shell directive * Add comments to better emphasize the text which should be kept Signed-off-by: Iulia Moldovan --- docs/projects/template/index.rst | 299 +++++++++++++++++-------------- 1 file changed, 169 insertions(+), 130 deletions(-) diff --git a/docs/projects/template/index.rst b/docs/projects/template/index.rst index 051318ee02..d1f8e2b7d0 100644 --- a/docs/projects/template/index.rst +++ b/docs/projects/template/index.rst @@ -2,38 +2,41 @@ .. _template_project: -Project template +AD---- HDL Project (template) =============================================================================== Overview ------------------------------------------------------------------------------- -**\*Some specifications about the board, the chip, etc. Typically the -information found on the** https://www.analog.com/en/products/ -**website**\ \* +.. + Some specifications about the board, the chip, etc. Typically the + information found on the https://www.analog.com/en/products/ + website Supported boards ------------------------------------------------------------------------------- -**\*IF IT APPLIES**\ \* - -- :adi:`AD9081-FMCA-EBZ ` -- :adi:`AD9082-FMCA-EBZ ` +- :adi:`EVAL-AD9467` Supported devices ------------------------------------------------------------------------------- -**\*EXAMPLES**\ \* +.. + EXAMPLES -- :adi:`AD9081` -- :adi:`AD9177` -- :adi:`AD9209` +- :adi:`AD9467` +- :adi:`AD9081` +- :adi:`AD9177` +- :adi:`AD9209` Supported carriers ------------------------------------------------------------------------------- -**\*At least one. Should be updated each time the project is ported to -another carrier. Take these tables as an example:**\ \* +.. + At least one. Should be updated each time the project is ported to + another carrier. + + Take these tables as an example: .. list-table:: :widths: 35 35 30 @@ -42,7 +45,7 @@ another carrier. Take these tables as an example:**\ \* * - Evaluation board - Carrier - FMC slot - * - :adi:`AD9081-FMCA-EBZ ` + * - :adi:`EVAL-AD9081` - :intel:`A10SoC ` - FMCA * - @@ -68,7 +71,7 @@ another carrier. Take these tables as an example:**\ \* * - Evaluation board - Carrier - FMC slot - * - :adi:`AD9082-FMCA-EBZ ` + * - :adi:`EVAL-AD9082` - :xilinx:`VCK190` - FMC0 * - @@ -90,7 +93,9 @@ Block diagram If the project has multiple ways of configuration, then make subsections to this section and show the default configuration and some other popular modes. -\**\* KEEP THIS PARAGRAPH \**\* +.. + KEEP THIS PARAGRAPH + The data path and clock domains are depicted in the below diagram: .. image:: ../ad9783_ebz/ad9783_zcu102_block_diagram.svg @@ -98,60 +103,64 @@ The data path and clock domains are depicted in the below diagram: :align: center :alt: AD9783-EBZ/ZCU102 block diagram -\*\* MUST: Use SVG format for the diagram \*\* +.. + MUST: Use SVG format for the diagram -\*\* TIP: Block diagrams should contain subtitles only if there are at least two -different diagrams \*\* +.. + TIP: Block diagrams should contain subtitles only if there are at least two + different diagrams Configuration modes ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -\**\* MENTION IF ANY MODES ARE AVAILABLE FOR CONFIGURATION \**\* +.. + MENTION IF ANY MODES ARE AVAILABLE FOR CONFIGURATION -**EXAMPLES BUT NOT LIMITED TO** +.. + EXAMPLES BUT NOT LIMITED TO The following are the parameters of this project that can be configured: -- JESD_MODE: used link layer encoder mode - - - 64B66B - 64b66b link layer defined in JESD204C, uses AMD IP as Physical - Layer - - 8B10B - 8b10b link layer defined in JESD204B, uses ADI IP as Physical - Layer - -- RX_LANE_RATE: lane rate of the Rx link (MxFE to FPGA) -- TX_LANE_RATE: lane rate of the Tx link (FPGA to MxFE) -- REF_CLK_RATE: the rate of the reference clock -- [RX/TX]_JESD_M: number of converters per link -- [RX/TX]_JESD_L: number of lanes per link -- [RX/TX]_JESD_S: number of samples per frame -- [RX/TX]_JESD_NP: number of bits per sample -- [RX/TX]_NUM_LINKS: number of links -- [RX/TX]_TPL_WIDTH -- TDD_SUPPORT: set to 1, adds the TDD; enables external synchronization through TDD. Must be set to 1 when SHARED_DEVCLK=1 -- SHARED_DEVCLK -- TDD_CHANNEL_CNT -- TDD_SYNC_WIDTH -- TDD_SYNC_INT -- TDD_SYNC_EXT -- TDD_SYNC_EXT_CDC: if enabled, the CDC circuitry for the external sync signal is added -- [RX/TX]_KS_PER_CHANNEL: Number of samples stored in internal buffers in - kilosamples per converter (M) -- [ADC/DAC]_DO_MEM_TYPE -- Check out this guide on more details regarding these parameters: - :ref:`axi_tdd` +- JESD_MODE: used link layer encoder mode + + - 64B66B - 64b66b link layer defined in JESD204C, uses AMD IP as Physical Layer + - 8B10B - 8b10b link layer defined in JESD204B, uses ADI IP as Physical Layer + +- RX_LANE_RATE: lane rate of the Rx link (MxFE to FPGA) +- TX_LANE_RATE: lane rate of the Tx link (FPGA to MxFE) +- REF_CLK_RATE: the rate of the reference clock +- [RX/TX]_JESD_M: number of converters per link +- [RX/TX]_JESD_L: number of lanes per link +- [RX/TX]_JESD_S: number of samples per frame +- [RX/TX]_JESD_NP: number of bits per sample +- [RX/TX]_NUM_LINKS: number of links +- [RX/TX]_TPL_WIDTH +- TDD_SUPPORT: set to 1, adds the TDD; enables external synchronization through TDD. Must be set to 1 when SHARED_DEVCLK=1 +- SHARED_DEVCLK +- TDD_CHANNEL_CNT +- TDD_SYNC_WIDTH +- TDD_SYNC_INT +- TDD_SYNC_EXT +- TDD_SYNC_EXT_CDC: if enabled, the CDC circuitry for the external sync signal is added +- [RX/TX]_KS_PER_CHANNEL: Number of samples stored in internal buffers in + kilosamples per converter (M) +- [ADC/DAC]_DO_MEM_TYPE +- Check out this guide on more details regarding these parameters: + :ref:`axi_tdd` Clock scheme ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- External clock source - :dokuwiki:`AD-SYNCHRONA14-EBZ ` -- SYSREF clocks are LVDS -- ADCCLK and REFCLK are LVPECL +- External clock source + :dokuwiki:`AD-SYNCHRONA14-EBZ ` +- SYSREF clocks are LVDS +- ADCCLK and REFCLK are LVPECL -\*\* ADD IMAGE IF APPLIES! MUST: Use SVG format \*\* +.. + ADD IMAGE IF APPLIES! MUST: Use SVG format -**\*DESCRIBE OTHER COMPONENTS FROM THE PROJECT, EX: SYNCHRONA**\ \* +.. + DESCRIBE OTHER COMPONENTS FROM THE PROJECT, EX: SYNCHRONA Only the channels presented in the clocking selection are relevant. For the rest, you can either disable them or just put a divided frequency of @@ -160,8 +169,9 @@ the source clock. Limitations ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ -**\*EXAMPLE OF CONFIGURATION/LIMITATION. PLEASE WRITE THIS KIND OF -INFORMATION IF IT APPLIES TO THE PROJECT**\ \* +.. + EXAMPLE OF CONFIGURATION/LIMITATION. PLEASE WRITE THIS KIND OF INFORMATION IF + IT APPLIES TO THE PROJECT The design has one JESD receive chain with 4 lanes at rate of 13Gbps. The JESD receive chain consists of a physical layer represented by an @@ -187,20 +197,25 @@ chains are merged together and transferred to the DDR with a single DMA. CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -\**\* KEEP THIS PARAGRAPH \**\* +.. + KEEP THIS PARAGRAPH + The addresses are dependent on the architecture of the FPGA, having an offset added to the base address from HDL (see more at :ref:`architecture`). -**If there are any PL SPI connections, they must be added in this table too** +.. + If there are any PL SPI connections, they must be added in this table too -\**\* THIS IS JUST AN EXAMPLE \**\* +.. + THIS IS JUST AN EXAMPLE Depending on the values of parameters $INTF_CFG, $ADI_PHY_SEL and $TDD_SUPPORT, -some IPs are instatiated and some are not. +some IPs are instantiated and some are not. Check-out the table below to find out the conditions. -\*\* MUST: Hexadecimal addresses are written in caps and separated by an underscore. \*\* +.. + MUST: Hexadecimal addresses are written in caps and separated by an underscore. ==================== ================================= =============== =========== ============ Instance Depends on parameter Zynq/Microblaze ZynqMP Versal @@ -239,7 +254,8 @@ I2C connections SPI connections ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -THESE ARE JUST EXAMPLES!!! +.. + THESE ARE JUST EXAMPLES! .. list-table:: :widths: 25 25 25 25 @@ -265,7 +281,8 @@ THESE ARE JUST EXAMPLES!!! GPIOs ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -**Add explanation depending on your case** +.. + Add explanation depending on your case .. list-table:: :widths: 25 20 20 20 15 @@ -297,8 +314,9 @@ GPIOs - 117:86 - 141:110 -\*\* MUST: GPIOs should be listed in descending order and should have the number -of bits specified next to their name \*\* +.. + MUST: GPIOs should be listed in descending order and should have the number + of bits specified next to their name Interrupts ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -437,18 +455,21 @@ Instance name HDL Linux Zynq Actual Zynq Linux ZynqMP Actual ZynqMP S10SoC Li --- 0 29 61 89 121 17 40 72 ================ === ========== =========== ============ ============= ====== =============== ================ -!!!! These are the project-specific interrupts (usually found in -/project_name/common/Project_name_bd,tcl). -Add the name of the component that uses that interrupt. -Delete the dropdown section when you insert the table in your page +.. + These are the project-specific interrupts (usually found in + /project_name/common/Project_name_bd,tcl). + Add the name of the component that uses that interrupt. + Delete the dropdown section when you insert the table in your page -NOTE THAT FOR ULTRASCALE\+ DEVICES, THE PS I2C IS NOT SUPPORTED IN LINUX!! -ALWAYS USE PL I2C FOR THESE DESIGNS!! +.. + NOTE THAT FOR ULTRASCALE\+ DEVICES, THE PS I2C IS NOT SUPPORTED IN LINUX!! + ALWAYS USE PL I2C FOR THESE DESIGNS!! Building the HDL project ------------------------------------------------------------------------------- -**\*YOU CAN KEEP THE FIRST PARAGRAPH SINCE IT IS GENERIC**\ \* +.. + YOU CAN KEEP THE FIRST PARAGRAPH SINCE IT IS GENERIC The design is built upon ADI's generic HDL reference design framework. ADI distributes the bit/elf files of these projects as part of the @@ -458,33 +479,36 @@ If you want to build the sources, ADI makes them available on the `clone `__ the HDL repository. -Then go to the **\*PROJECT LOCATION WITHIN HDL (EX: -projects/ad9695/zcu102)**\ \* location and run the make command by -typing in your command prompt: +Then go to the hdl/projects/$eval_board/$carrier location and run the make +command. **Linux/Cygwin/WSL** -**\*Say which is the default configuration that's built when running -``make``, give examples of running with all parameters and also with -just one. Say that it will create a folder with the name ... when -running with the following parameters.**\ \* +.. + Say which is the default configuration that's built when running + ``make``, give examples of running with all parameters and also with + just one. Say that it will create a folder with the name ... when + running with the following parameters. + +Example of running the ``make`` command without parameters (using the default +configuration): -.. code-block:: - :linenos: - :emphasize-lines: 2, 6 +.. shell:: - user@analog:~$ cd hdl/projects/ad9081_fmca_ebz/zcu102 - // these are just examples of how to write the *make* command with parameters - user@analog:~/hdl/projects/ad9081_fmca_ebz/zcu102$ make parameter1=value parameter2=value + $cd hdl/projects/ad9081_fmca_ebz/zcu102 + $make - user@analog:~$ cd hdl/projects/ad9081_fmca_ebz/a10soc - // these are just examples of how to write the *make* command with parameters - user@analog:~/hdl/projects/ad9081_fmca_ebz/a10soc$ make RX_LANE_RATE=2.5 TX_LANE_RATE=2.5 RX_JESD_L=8 RX_JESD_M=4 RX_JESD_S=1 RX_JESD_NP=16 TX_JESD_L=8 TX_JESD_M=4 TX_JESD_S=1 TX_JESD_NP=16 +Example of running the ``make`` command with parameters: + +.. shell:: + + $cd hdl/projects/ad9081_fmca_ebz/a10soc + $make RX_LANE_RATE=2.5 TX_LANE_RATE=2.5 RX_JESD_L=8 RX_JESD_M=4 RX_JESD_S=1 RX_JESD_NP=16 TX_JESD_L=8 TX_JESD_M=4 TX_JESD_S=1 TX_JESD_NP=16 The following dropdowns contain tables with the parameters that can be used to configure this project, depending on the carrier used. Where a cell contains a --- (dash) it means that the parameter doesn't exist -for that project (ad9081_fmca_ebz/carrier or ad9082_fmca_ebz/carrier). +for that project (ad9081_fmca_ebz/$carrier or ad9082_fmca_ebz/$carrier). .. collapsible:: Default values of the make parameters for AD9082-FMCA-EBZ @@ -531,7 +555,8 @@ for that project (ad9081_fmca_ebz/carrier or ad9082_fmca_ebz/carrier). | TX_KS_PER_CHANNEL | 64 | 64 | --- | --- | +-------------------+--------+--------+--------------+--------------+ - .. warning:: + .. admonition:: Legend + :class: note ``*`` --- for this carrier only the 8B10B mode is supported @@ -549,17 +574,23 @@ because of truncation of some keywords so the name will not exceed the limits of the Operating System (``JESD``, ``LANE``, etc. are removed) of 260 characters. -**\*KEEP THIS LINE TOO**\ \* +.. + KEEP THIS LINE TOO + A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. Software considerations ------------------------------------------------------------------------------- -\**\* MENTION THESE \**\* +.. + MENTION THESE -ADC - crossbar config \**\* THIS IS JUST AN EXAMPLE \**\* +ADC - crossbar config \**\* EXAMPLE \**\* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +.. + THIS SECTION IS JUST AN EXAMPLE + Due to physical constraints, Rx lanes are reordered as described in the following table. @@ -580,9 +611,12 @@ ADC phy Lane FPGA Rx lane / Logical Lane 7 1 ============ =========================== -DAC - crossbar config \**\* THIS IS JUST AN EXAMPLE \**\* +DAC - crossbar config \**\* EXAMPLE \**\* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +.. + THIS SECTION IS JUST AN EXAMPLE + Due to physical constraints, Tx lanes are reordered as described in the following table: @@ -609,13 +643,14 @@ Resources Systems related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Links to the Quick start guides, to the pages where the hardware changes are - specified in detail, etc. in the form of a table as the one below +- Links to the Quick start guides, to the pages where the hardware changes are + specified in detail, etc. in the form of a table as the one below -**THIS IS JUST AN EXAMPLE** +.. + THIS IS JUST AN EXAMPLE -- :dokuwiki:`[Wiki] AD9081 & AD9082 & AD9988 & AD9986 Prototyping Platform User Guide ` -- Here you can find all the quick start guides on wiki documentation :dokuwiki:`[Wiki] AD9081/AD9082/AD9986/AD9988 Quick Start Guides ` +- :dokuwiki:`[Wiki] AD9081 & AD9082 & AD9988 & AD9986 Prototyping Platform User Guide ` +- Here you can find all the quick start guides on wiki documentation :dokuwiki:`[Wiki] AD9081/AD9082/AD9986/AD9988 Quick Start Guides ` Here you can find the quick start guides available for these evaluation boards: @@ -636,35 +671,36 @@ Here you can find the quick start guides available for these evaluation boards: - :dokuwiki:`VCK190/VMK180 ` - :dokuwiki:`A10SoC ` -- Other relevant information +- Other relevant information Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheets: +- Product datasheets: - - :adi:`AD9081` - - :adi:`AD9082` - - :adi:`AD9988` - - :adi:`AD9986` -- `UG-1578, Device User Guide `__ -- `UG-1829, Evaluation Board User Guide `__ + - :adi:`AD9081` + - :adi:`AD9082` + - :adi:`AD9988` + - :adi:`AD9986` +- `UG-1578, Device User Guide `__ +- `UG-1829, Evaluation Board User Guide `__ HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Link to the project source code -- Table like the one below. Must have as first IP (if it exists) the IP that - was created with this project (i.e., axi_ad9783). If there isn't, then to - be taken in the order they are written in the Makefile of the project, - stating the source code link in a column and the documentation link in - another column -- Other relevant information +- Link to the project source code +- Table like the one below. Must have as first IP (if it exists) the IP that + was created with this project (i.e., axi_ad9783). If there isn't, then to + be taken in the order they are written in the Makefile of the project, + stating the source code link in a column and the documentation link in + another column +- Other relevant information -**THIS IS JUST AN EXAMPLE** +.. + THIS IS JUST AN EXAMPLE -- :git-hdl:`AD9081_FMCA_EBZ HDL project source code ` -- :git-hdl:`AD9082_FMCA_EBZ HDL project source code ` +- :git-hdl:`AD9081_FMCA_EBZ HDL project source code ` +- :git-hdl:`AD9082_FMCA_EBZ HDL project source code ` .. list-table:: :widths: 30 35 35 @@ -710,30 +746,33 @@ HDL related - :git-hdl:`library/jesd204/ad_ip_jesd204_tpl_dac` - :ref:`ad_ip_jesd204_tpl_dac` -\**\* MENTION THESE for JESD reference designs \**\* +.. + MENTION THESE for JESD reference designs -- :dokuwiki:`[Wiki] Generic JESD204B block designs ` -- :ref:`jesd204` +- :dokuwiki:`[Wiki] Generic JESD204B block designs ` +- :ref:`jesd204` -\**\* MENTION THIS for SPI Engine reference designs \**\* +.. + MENTION THIS for SPI Engine reference designs -- :ref:`SPI Engine Framework documentation ` +- :ref:`SPI Engine Framework documentation ` Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -**THIS IS JUST AN EXAMPLE** +.. + THIS IS JUST AN EXAMPLE -- :dokuwiki:`[Wiki] AD9081-FMCA-EBZ Linux driver wiki page ` +- :dokuwiki:`[Wiki] AD9081-FMCA-EBZ Linux driver wiki page ` If there is no Linux driver page, then insert a link to the code of the driver and of the device tree. -- Python support (THIS IS JUST AN EXAMPLE): +- Python support (THIS IS JUST AN EXAMPLE): - - `AD9081 class documentation `__ - - `PyADI-IIO documentation `__ - - `Example link`_ + - `AD9081 class documentation `__ + - `PyADI-IIO documentation `__ + - `Example link`_ .. include:: ../common/more_information.rst From 03f9e41948413193a576c2a01e19cc9812e1b902 Mon Sep 17 00:00:00 2001 From: Iulia Moldovan Date: Tue, 19 Nov 2024 11:17:17 +0200 Subject: [PATCH 06/10] docs/projects: Add ref. to CPU Intercon. Addr. & update section * user_guide/architecture: Create label for CPU intercon. section Signed-off-by: Iulia Moldovan --- docs/projects/ad3552r_evb/index.rst | 6 ++-- docs/projects/ad408x_fmc_evb/index.rst | 3 +- docs/projects/ad411x_ad717x/index.rst | 4 +-- docs/projects/ad4134_fmc/index.rst | 4 +-- docs/projects/ad4170_asdz/index.rst | 10 +++--- docs/projects/ad4630_fmc/index.rst | 4 +-- docs/projects/ad469x_evb/index.rst | 2 +- docs/projects/ad485x_fmcz/index.rst | 20 +++++------ docs/projects/ad5766_sdz/index.rst | 4 +-- docs/projects/ad57xx_ardz/index.rst | 10 +++--- docs/projects/ad7134_fmc/index.rst | 4 +-- docs/projects/ad738x_fmc/index.rst | 4 +-- docs/projects/ad7405_fmc/index.rst | 2 +- docs/projects/ad7606x_fmc/index.rst | 4 +-- docs/projects/ad7616_sdz/index.rst | 4 +-- docs/projects/ad77681evb/index.rst | 2 +- docs/projects/ad7768evb/index.rst | 4 +-- docs/projects/ad777x_ardz/index.rst | 10 ++++++ docs/projects/ad9081_fmca_ebz/index.rst | 21 ++++++++++- .../projects/ad9081_fmca_ebz_x_band/index.rst | 2 +- docs/projects/ad9213_evb/index.rst | 10 +++--- docs/projects/ad9265_fmc/index.rst | 8 ++--- docs/projects/ad9434_fmc/index.rst | 2 +- docs/projects/ad9467_fmc/index.rst | 2 +- docs/projects/ad9656_fmc/index.rst | 22 ++++++------ docs/projects/ad9695_fmc/index.rst | 10 +++--- docs/projects/ad9739a_fmc/index.rst | 7 ++-- docs/projects/ad9783_ebz/index.rst | 16 ++++----- docs/projects/ad_gmsl2eth_sl/index.rst | 2 +- docs/projects/adaq7980_sdz/index.rst | 4 +-- docs/projects/adaq8092_fmc/index.rst | 2 +- docs/projects/adrv9026/index.rst | 28 +++++++-------- docs/projects/adrv904x/index.rst | 20 +++++------ docs/projects/adv7511/index.rst | 12 +++---- docs/projects/cn0363/index.rst | 4 +-- docs/projects/cn0506/index.rst | 8 ++--- docs/projects/cn0540/index.rst | 10 +++--- docs/projects/cn0561/index.rst | 18 +++++++--- docs/projects/cn0577/index.rst | 2 +- docs/projects/cn0579/index.rst | 2 +- docs/projects/cn0585/index.rst | 36 +++++++++---------- docs/projects/max96724/index.rst | 2 +- docs/projects/pulsar_adc/index.rst | 2 +- docs/projects/pulsar_lvds/index.rst | 4 +-- docs/projects/template/index.rst | 2 +- docs/user_guide/architecture.rst | 2 ++ 46 files changed, 199 insertions(+), 162 deletions(-) diff --git a/docs/projects/ad3552r_evb/index.rst b/docs/projects/ad3552r_evb/index.rst index 167c69beac..818e678a1b 100644 --- a/docs/projects/ad3552r_evb/index.rst +++ b/docs/projects/ad3552r_evb/index.rst @@ -61,14 +61,14 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL (see more at :ref:`architecture`). +added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). ==================== =============== Instance Zynq/Microblaze ==================== =============== axi_ad3552r_dac 0x44A7_0000 -axi_dac_dma 0x44A3_0000 -axi_clkgen 0x44B0_0000 +axi_dac_dma 0x44A3_0000 +axi_clkgen 0x44B0_0000 ==================== =============== GPIOs diff --git a/docs/projects/ad408x_fmc_evb/index.rst b/docs/projects/ad408x_fmc_evb/index.rst index 1456d90681..4711a6cd9c 100644 --- a/docs/projects/ad408x_fmc_evb/index.rst +++ b/docs/projects/ad408x_fmc_evb/index.rst @@ -80,8 +80,7 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL (see more at :ref:`architecture`). - +added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). ==================== =============== Instance Zynq/Microblaze diff --git a/docs/projects/ad411x_ad717x/index.rst b/docs/projects/ad411x_ad717x/index.rst index bb50faf12e..d51c27f97d 100644 --- a/docs/projects/ad411x_ad717x/index.rst +++ b/docs/projects/ad411x_ad717x/index.rst @@ -92,10 +92,10 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL (see more at :ref:`architecture`). +added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). ======================== =========== -Instance Address +Instance DE10-Nano ======================== =========== axi_dmac_0 0x0002_0000 axi_spi_engine_0 0x0003_0000 diff --git a/docs/projects/ad4134_fmc/index.rst b/docs/projects/ad4134_fmc/index.rst index 5e8a2b3df1..f897fa2fc4 100644 --- a/docs/projects/ad4134_fmc/index.rst +++ b/docs/projects/ad4134_fmc/index.rst @@ -77,10 +77,10 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL(see more at :ref:`architecture`). +added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). ======================== =========== -Instance Address +Instance Zynq ======================== =========== spi_ad4134_axi_regmap 0x44A0_0000 axi_ad4134_dma 0x44A3_0000 diff --git a/docs/projects/ad4170_asdz/index.rst b/docs/projects/ad4170_asdz/index.rst index 4dd2cacc74..047caa1d7b 100644 --- a/docs/projects/ad4170_asdz/index.rst +++ b/docs/projects/ad4170_asdz/index.rst @@ -59,18 +59,18 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL (see more at :ref:`architecture`). +added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). -======================== =========== -Instance Address -======================== =========== +======================== ================= +Instance Zynq*/DE10-Nano** +======================== ================= spi_ad4170_axi_regmap* 0x44A0_0000 axi_ad4170_dma* 0x44A3_0000 axi_ad4170_iic* 0x44A4_0000 spi_clkgen* 0x44A7_0000 axi_dmac_0** 0x0002_0000 axi_spi_engine_0** 0x0003_0000 -======================== =========== +======================== ================= .. admonition:: Legend :class: note diff --git a/docs/projects/ad4630_fmc/index.rst b/docs/projects/ad4630_fmc/index.rst index e57af0bfc8..734d396070 100644 --- a/docs/projects/ad4630_fmc/index.rst +++ b/docs/projects/ad4630_fmc/index.rst @@ -188,10 +188,10 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL(see more at :ref:`architecture`). +added to the base address from HDL(see more at :ref:`architecture cpu-intercon-addr`). ======================== =========== -Instance Address +Instance Zynq ======================== =========== spi_ad463x_axi_regmap 0x44A0_0000 axi_ad463x_dma 0x44A3_0000 diff --git a/docs/projects/ad469x_evb/index.rst b/docs/projects/ad469x_evb/index.rst index 2e54e0e740..7a77fb4bd0 100644 --- a/docs/projects/ad469x_evb/index.rst +++ b/docs/projects/ad469x_evb/index.rst @@ -121,7 +121,7 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL(see more at :ref:`architecture`). +added to the base address from HDL(see more at :ref:`architecture cpu-intercon-addr`). ====================== ================= Instance Zynq*/DE10-Nano** diff --git a/docs/projects/ad485x_fmcz/index.rst b/docs/projects/ad485x_fmcz/index.rst index 2adaf97412..0b4e007d09 100644 --- a/docs/projects/ad485x_fmcz/index.rst +++ b/docs/projects/ad485x_fmcz/index.rst @@ -133,16 +133,16 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL(see more at :ref:`architecture`). - -==================== =============== -Instance Zynq -==================== =============== -axi_ad485x 0x43c00000 -axi_pwm_gen 0x43d00000 -ad485x_dma 0x43e00000 -adc_clkgen 0x44000000 -==================== =============== +added to the base address from HDL(see more at :ref:`architecture cpu-intercon-addr`). + +============== =========== +Instance Zynq +============== =========== +axi_ad485x 0x43C0_0000 +axi_pwm_gen 0x43D0_0000 +ad485x_dma 0x43E0_0000 +adc_clkgen 0x4400_0000 +============== =========== SPI connections ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/projects/ad5766_sdz/index.rst b/docs/projects/ad5766_sdz/index.rst index 45efd82193..75056514ee 100644 --- a/docs/projects/ad5766_sdz/index.rst +++ b/docs/projects/ad5766_sdz/index.rst @@ -94,10 +94,10 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL (see more at :ref:`architecture`). +added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). ======================== =========== -Instance Address +Instance Zynq ======================== =========== spi/axi 0x44A0_0000 spi/axi_ad5766 0x44A1_0000 diff --git a/docs/projects/ad57xx_ardz/index.rst b/docs/projects/ad57xx_ardz/index.rst index bf8b43839f..ad585ad82e 100644 --- a/docs/projects/ad57xx_ardz/index.rst +++ b/docs/projects/ad57xx_ardz/index.rst @@ -76,11 +76,11 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL (see more at :ref:`architecture`). +added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). -======================== =========== -Instance Address -======================== =========== +======================== ================= +Instance Zynq*/DE10-Nano** +======================== ================= spi_ad57xx_axi_regmap* 0x44A0_0000 ad57xx_tx_dma* 0x44A4_0000 trig_gen* 0x44B0_0000 @@ -89,7 +89,7 @@ axi_dmac_0** 0x0003_0000 axi_spi_engine_0** 0x0004_0000 trig_gen** 0x0005_0000 spi_clk_pll_reconfig** 0x0006_0000 -======================== =========== +======================== ================= .. admonition:: Legend :class: note diff --git a/docs/projects/ad7134_fmc/index.rst b/docs/projects/ad7134_fmc/index.rst index 16495003da..3d1aa17359 100644 --- a/docs/projects/ad7134_fmc/index.rst +++ b/docs/projects/ad7134_fmc/index.rst @@ -115,10 +115,10 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL(see more at :ref:`architecture`). +added to the base address from HDL(see more at :ref:`architecture cpu-intercon-addr`). ======================== =========== -Instance Address +Instance Zynq ======================== =========== dual_ad7134_axi_regmap 0x44A0_0000 axi_ad7134_dma 0x44A3_0000 diff --git a/docs/projects/ad738x_fmc/index.rst b/docs/projects/ad738x_fmc/index.rst index ff9580967a..277287e816 100644 --- a/docs/projects/ad738x_fmc/index.rst +++ b/docs/projects/ad738x_fmc/index.rst @@ -151,10 +151,10 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL (see more at :ref:`architecture`). +added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). ========================= =========== -Instance Address +Instance Zynq ========================= =========== spi_ad738x_adc_axi_regmap 0x44A0_0000 axi_ad738x_dma 0x44A3_0000 diff --git a/docs/projects/ad7405_fmc/index.rst b/docs/projects/ad7405_fmc/index.rst index 9ad3f244b3..464b1b9859 100644 --- a/docs/projects/ad7405_fmc/index.rst +++ b/docs/projects/ad7405_fmc/index.rst @@ -86,7 +86,7 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL (see more at :ref:`architecture`). +added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). ==================== =============== Instance Zynq/Microblaze diff --git a/docs/projects/ad7606x_fmc/index.rst b/docs/projects/ad7606x_fmc/index.rst index b805ea89a0..3691a81460 100644 --- a/docs/projects/ad7606x_fmc/index.rst +++ b/docs/projects/ad7606x_fmc/index.rst @@ -166,10 +166,10 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL (see more at :ref:`architecture`). +added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). ======================== =========== -Instance Address +Instance Zynq ======================== =========== axi_ad7606x_dma 0x44A3_0000 spi_clkgen 0x44A7_0000 diff --git a/docs/projects/ad7616_sdz/index.rst b/docs/projects/ad7616_sdz/index.rst index 7ad1b2277c..c37f0956ec 100644 --- a/docs/projects/ad7616_sdz/index.rst +++ b/docs/projects/ad7616_sdz/index.rst @@ -123,10 +123,10 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL(see more at :ref:`architecture`). +added to the base address from HDL(see more at :ref:`architecture cpu-intercon-addr`). ======================== =========== -Instance Address +Instance Zynq ======================== =========== axi_ad7616_dma 0x44A3_0000 spi_clkgen 0x44A7_0000 diff --git a/docs/projects/ad77681evb/index.rst b/docs/projects/ad77681evb/index.rst index 50f7a94657..92dc36b649 100644 --- a/docs/projects/ad77681evb/index.rst +++ b/docs/projects/ad77681evb/index.rst @@ -63,7 +63,7 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL(see more at :ref:`architecture`). +added to the base address from HDL(see more at :ref:`architecture cpu-intercon-addr`). ========================= =========== Instance Zynq diff --git a/docs/projects/ad7768evb/index.rst b/docs/projects/ad7768evb/index.rst index f9cca2651e..fb79f25e11 100644 --- a/docs/projects/ad7768evb/index.rst +++ b/docs/projects/ad7768evb/index.rst @@ -102,10 +102,10 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL(see more at :ref:`architecture`). +added to the base address from HDL(see more at :ref:`architecture cpu-intercon-addr`). ========================= =========== -Instance Address +Instance Zynq ========================= =========== axi_ad7768_adc 0x43C0_0000 ad7768_dma 0x7C40_0000 diff --git a/docs/projects/ad777x_ardz/index.rst b/docs/projects/ad777x_ardz/index.rst index 5fd21c565c..f28c1c27d8 100644 --- a/docs/projects/ad777x_ardz/index.rst +++ b/docs/projects/ad777x_ardz/index.rst @@ -81,6 +81,16 @@ Clock scheme :align: center :alt: AD777x clocking scheme +CPU/Memory interconnects addresses +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +============== =========== +Instance Zynq +============== =========== +axi_ad777x_adc 0x43C0_0000 +ad777x_dma 0x7C48_0000 +============== =========== + SPI connections ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/projects/ad9081_fmca_ebz/index.rst b/docs/projects/ad9081_fmca_ebz/index.rst index 72cb26f04f..b27982e53e 100644 --- a/docs/projects/ad9081_fmca_ebz/index.rst +++ b/docs/projects/ad9081_fmca_ebz/index.rst @@ -379,7 +379,7 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL (see more at :ref:`architecture`). +added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). Depending on the values of parameters $INTF_CFG, $ADI_PHY_SEL and $TDD_SUPPORT, some IPs are instatiated and some are not. @@ -402,6 +402,25 @@ mxfe_tx_data_offload $INTF_CFG!="RX" 0x7C44_0000 0x9C44_00 axi_tdd_0 $TDD_SUPPORT==1 0x7C46_0000 0x9C46_0000 0xBC46_00000 ==================== ================================= =============== =========== ============ +For the Intel carriers, only a part of the CPU interrupts are specified, +as the rest depend on the values of $TX_NUM_OF_LANES and $TRANSCEIVER_TYPE +(see :git-hdl:`projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_qsys.tcl` +for more details). + +=============================== =========== +Instance Intel +=============================== =========== +mxfe_rx_jesd204.link_reconfig 0x000C_0000 +mxfe_rx_jesd204.link_management 0x000C_4000 +mxfe_tx_jesd204.link_reconfig 0x000C_8000 +mxfe_tx_jesd204.link_management 0x000C_C000 +mxfe_rx_tpl.s_axi 0x000D_2000 +mxfe_tx_tpl.s_axi 0x000D_4000 +mxfe_rx_dma.s_axi 0x000D_8000 +mxfe_tx_dma.s_axi 0x000D_C000 +mxfe_gpio.s1 0x000E_0000 +=============================== =========== + SPI connections ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/projects/ad9081_fmca_ebz_x_band/index.rst b/docs/projects/ad9081_fmca_ebz_x_band/index.rst index 3b5a965d3d..2bd3e99ba8 100644 --- a/docs/projects/ad9081_fmca_ebz_x_band/index.rst +++ b/docs/projects/ad9081_fmca_ebz_x_band/index.rst @@ -143,7 +143,7 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL (see more at :ref:`architecture`). +added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). ==================== =========== Instance ZynqMP diff --git a/docs/projects/ad9213_evb/index.rst b/docs/projects/ad9213_evb/index.rst index 3c53ada549..9ed7325d1c 100644 --- a/docs/projects/ad9213_evb/index.rst +++ b/docs/projects/ad9213_evb/index.rst @@ -83,17 +83,17 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL (see more at :ref:`architecture`). +added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). Check-out the table below to find out the conditions. ==================== =============== Instance Zynq/Microblaze ==================== =============== -axi_ad9213_xcvr 0x44A6_0000 -rx_ad9213_tpl_core 0x44A1_0000 -axi_ad9213_jesd 0x44A9_0000 -axi_ad9213_dma 0x7C42_0000 +axi_ad9213_xcvr 0x44A6_0000 +rx_ad9213_tpl_core 0x44A1_0000 +axi_ad9213_jesd 0x44A9_0000 +axi_ad9213_dma 0x7C42_0000 ==================== =============== SPI connections diff --git a/docs/projects/ad9265_fmc/index.rst b/docs/projects/ad9265_fmc/index.rst index 8a10d076fb..77802272ab 100644 --- a/docs/projects/ad9265_fmc/index.rst +++ b/docs/projects/ad9265_fmc/index.rst @@ -70,15 +70,13 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL (see more at :ref:`architecture`). - -Check-out the table below to find out the conditions. +added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). ==================== =============== Instance Zynq/Microblaze ==================== =============== -axi_ad9265 0x44A00000 -axi_ad9265_dma 0x44A30000 +axi_ad9265 0x44A0_0000 +axi_ad9265_dma 0x44A3_0000 ==================== =============== SPI connections diff --git a/docs/projects/ad9434_fmc/index.rst b/docs/projects/ad9434_fmc/index.rst index cbe0c901e2..7ca72b9bc4 100644 --- a/docs/projects/ad9434_fmc/index.rst +++ b/docs/projects/ad9434_fmc/index.rst @@ -88,7 +88,7 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL(see more at :ref:`architecture`). +added to the base address from HDL(see more at :ref:`architecture cpu-intercon-addr`). ==================== =============== Instance Zynq/Microblaze diff --git a/docs/projects/ad9467_fmc/index.rst b/docs/projects/ad9467_fmc/index.rst index d3572b5f69..45eee8fee9 100644 --- a/docs/projects/ad9467_fmc/index.rst +++ b/docs/projects/ad9467_fmc/index.rst @@ -132,7 +132,7 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL (see more at :ref:`architecture`). +added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). ==================== =============== Instance Zynq/Microblaze diff --git a/docs/projects/ad9656_fmc/index.rst b/docs/projects/ad9656_fmc/index.rst index 1409d63c6c..c308a0d6e2 100644 --- a/docs/projects/ad9656_fmc/index.rst +++ b/docs/projects/ad9656_fmc/index.rst @@ -107,18 +107,16 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL (see more at :ref:`architecture`). - -Check-out the table below to find out the conditions. - -================== =============== -Instance Zynq/Microblaze -================== =============== -rx_ad9656_tpl_core 0x44A00000 -axi_ad9656_rx_xcvr 0x44A60000 -axi_ad9656_rx_jesd 0x44AA0000 -axi_ad9656_rx_dma 0x7C400000 -================== =============== +added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). + +================== =========== +Instance ZynqMP +================== =========== +rx_ad9656_tpl_core 0x84A0_0000 +axi_ad9656_rx_xcvr 0x84A6_0000 +axi_ad9656_rx_jesd 0x84AA_0000 +axi_ad9656_rx_dma 0x9C40_0000 +================== =========== SPI connections ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/projects/ad9695_fmc/index.rst b/docs/projects/ad9695_fmc/index.rst index a86eaabec4..50ab2b6b74 100644 --- a/docs/projects/ad9695_fmc/index.rst +++ b/docs/projects/ad9695_fmc/index.rst @@ -118,15 +118,15 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL (see more at :ref:`architecture`). +added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). ================== =========== Instance ZynqMP ================== =========== -rx_ad9695_tpl_core 0x44A0_0000 -axi_ad9695_rx_xcvr 0x44A6_0000 -axi_ad9695_rx_jesd 0x44AA_0000 -axi_ad9695_rx_dma 0x7C40_0000 +rx_ad9695_tpl_core 0x84A0_0000 +axi_ad9695_rx_xcvr 0x84A6_0000 +axi_ad9695_rx_jesd 0x84AA_0000 +axi_ad9695_rx_dma 0x9C40_0000 ================== =========== SPI connections diff --git a/docs/projects/ad9739a_fmc/index.rst b/docs/projects/ad9739a_fmc/index.rst index 6ae24cb842..82a7b61dac 100644 --- a/docs/projects/ad9739a_fmc/index.rst +++ b/docs/projects/ad9739a_fmc/index.rst @@ -98,11 +98,14 @@ Two clock paths are available to drive the clock input on the CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +The addresses are dependent on the architecture of the FPGA, having an offset +added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). + ==================== =============== Instance Zynq/Microblaze ==================== =============== -axi_ad9739a 0x7420_0000 -axi_ad9739a_dma 0x7c42_0000 +axi_ad9739a 0x7420_0000 +axi_ad9739a_dma 0x7C42_0000 ==================== =============== SPI connections diff --git a/docs/projects/ad9783_ebz/index.rst b/docs/projects/ad9783_ebz/index.rst index b091d2e20d..199ddc028a 100644 --- a/docs/projects/ad9783_ebz/index.rst +++ b/docs/projects/ad9783_ebz/index.rst @@ -62,14 +62,14 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL (see more at :ref:`architecture`). - -============== =============== =========== -Instance Zynq/Microblaze ZynqMP -============== =============== =========== -axi_ad9783 0x7420_0000 0x9420_0000 -axi_ad9783_dma 0x7C42_0000 0x9C42_0000 -============== =============== =========== +added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). + +============== =========== +Instance ZynqMP +============== =========== +axi_ad9783 0x9420_0000 +axi_ad9783_dma 0x9C42_0000 +============== =========== SPI connections ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/projects/ad_gmsl2eth_sl/index.rst b/docs/projects/ad_gmsl2eth_sl/index.rst index f1e7ebb6e0..9a58173040 100644 --- a/docs/projects/ad_gmsl2eth_sl/index.rst +++ b/docs/projects/ad_gmsl2eth_sl/index.rst @@ -64,7 +64,7 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL (see more at :ref:`architecture`). +added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). ======================== =========== Instance Address diff --git a/docs/projects/adaq7980_sdz/index.rst b/docs/projects/adaq7980_sdz/index.rst index 96fb6586c4..6a40d9115f 100644 --- a/docs/projects/adaq7980_sdz/index.rst +++ b/docs/projects/adaq7980_sdz/index.rst @@ -72,10 +72,10 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL (see more at :ref:`architecture`). +added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). =========================== =========== -Instance Address +Instance Zynq =========================== =========== axi_adaq7980_dma 0x44A3_0000 spi_clkgen 0x44A7_0000 diff --git a/docs/projects/adaq8092_fmc/index.rst b/docs/projects/adaq8092_fmc/index.rst index 59f2bf365c..8272c4bd2f 100644 --- a/docs/projects/adaq8092_fmc/index.rst +++ b/docs/projects/adaq8092_fmc/index.rst @@ -75,7 +75,7 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL (see more at :ref:`architecture`). +added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). ==================== =============== Instance Zynq/Microblaze diff --git a/docs/projects/adrv9026/index.rst b/docs/projects/adrv9026/index.rst index 05ad4f0333..c018661b9e 100644 --- a/docs/projects/adrv9026/index.rst +++ b/docs/projects/adrv9026/index.rst @@ -120,20 +120,20 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL (see more at :ref:`architecture`). - -==================== =========== =========== =========== -Instance ZynqMP Versal Microblaze -==================== =========== =========== =========== -axi_adrv9026_tx_jesd 0x84A90000 0xA4A90000 0x44A90000 -axi_adrv9026_rx_jesd 0x84AA0000 0xA4AA0000 0x44AA0000 -axi_adrv9026_tx_dma 0x9c420000 0xBC420000 0x7c420000 -axi_adrv9026_rx_dma 0x9c400000 0xBC400000 0x7c400000 -tx_adrv9026_tpl_core 0x84A04000 0xA4A04000 0x44A04000 -rx_adrv9026_tpl_core 0x84A00000 0xA4A00000 0x44A00000 -axi_adrv9026_tx_xcvr 0x84A80000 0xA4A80000 0x44A80000 -axi_adrv9026_rx_xcvr 0x84A60000 0xA4A60000 0x44A60000 -==================== =========== =========== =========== +added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). + +==================== ==================== =============== =========== =========== +Instance Depends on parameter Zynq/Microblaze ZynqMP Versal +==================== ==================== =============== =========== =========== +rx_adrv9026_tpl_core 0x44A0_0000 0x84A0_0000 0xA4A0_0000 +tx_adrv9026_tpl_core 0x44A0_4000 0x84A0_4000 0xA4A0_4000 +axi_adrv9026_rx_xcvr $ADI_PHY_SEL==1 0x44A6_0000 0x84A6_0000 0xA4A6_0000 +axi_adrv9026_tx_xcvr $ADI_PHY_SEL==1 0x44A8_0000 0x84A8_0000 0xA4A8_0000 +axi_adrv9026_tx_jesd 0x44A9_0000 0x84A9_0000 0xA4A9_0000 +axi_adrv9026_rx_jesd 0x44AA_0000 0x84AA_0000 0xA4AA_0000 +axi_adrv9026_rx_dma 0x7C40_0000 0x9C40_0000 0xBC40_0000 +axi_adrv9026_tx_dma 0x7C42_0000 0x9C42_0000 0xBC42_0000 +==================== ==================== =============== =========== =========== SPI connections ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/projects/adrv904x/index.rst b/docs/projects/adrv904x/index.rst index 0aa4f1092c..c49e9791c6 100644 --- a/docs/projects/adrv904x/index.rst +++ b/docs/projects/adrv904x/index.rst @@ -120,19 +120,19 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL (see more at :ref:`architecture`). +added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). ==================== =========== =========== -Instance ZynqMP Versal +Instance ZynqMP Versal ==================== =========== =========== -axi_adrv904x_tx_jesd 0x84A90000 0xA4A90000 -axi_adrv904x_rx_jesd 0x84AA0000 0xA4AA0000 -axi_adrv904x_tx_dma 0x9C420000 0xBC420000 -axi_adrv904x_rx_dma 0x9C400000 0xBC400000 -tx_adrv904x_tpl_core 0x84A04000 0xA4A04000 -rx_adrv904x_tpl_core 0x84A00000 0xA4A00000 -axi_adrv904x_tx_xcvr 0x84A80000 0xA4A80000 -axi_adrv904x_rx_xcvr 0x84A60000 0xA4A60000 +axi_adrv904x_tx_jesd 0x84A9_0000 0xA4A9_0000 +axi_adrv904x_rx_jesd 0x84AA_0000 0xA4AA_0000 +axi_adrv904x_tx_dma 0x9C42_0000 0xBC42_0000 +axi_adrv904x_rx_dma 0x9C40_0000 0xBC40_0000 +tx_adrv904x_tpl_core 0x84A0_4000 0xA4A0_4000 +rx_adrv904x_tpl_core 0x84A0_0000 0xA4A0_0000 +axi_adrv904x_tx_xcvr 0x84A8_0000 0xA4A8_0000 +axi_adrv904x_rx_xcvr 0x84A6_0000 0xA4A6_0000 ==================== =========== =========== SPI connections diff --git a/docs/projects/adv7511/index.rst b/docs/projects/adv7511/index.rst index d3b14f6142..b29b8699a7 100644 --- a/docs/projects/adv7511/index.rst +++ b/docs/projects/adv7511/index.rst @@ -67,19 +67,19 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL(see more at :ref:`architecture`). +added to the base address from HDL(see more at :ref:`architecture cpu-intercon-addr`). ======================== =========== -Instance Address +Instance Zynq ======================== =========== axi_iic_main 0x4160_0000 axi_sysid_0 0x4500_0000 axi_hdmi_clkgen 0x7900_0000 axi_hdmi_dma 0x4300_0000 -axi_hdmi_core 0x70e0_0000 -axi_spdif_tx_core 0x75c0_0000 -axi_i2s_adi * 0x7760_0000 -axi_iic_fmc * 0x4162_0000 +axi_hdmi_core 0x70E0_0000 +axi_spdif_tx_core 0x75C0_0000 +axi_i2s_adi* 0x7760_0000 +axi_iic_fmc* 0x4162_0000 ======================== =========== .. admonition:: Legend diff --git a/docs/projects/cn0363/index.rst b/docs/projects/cn0363/index.rst index 3db57c0aaa..b5b650fe77 100644 --- a/docs/projects/cn0363/index.rst +++ b/docs/projects/cn0363/index.rst @@ -66,10 +66,10 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL (see more at :ref:`architecture`). +added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). ======================== =========== -Instance Address +Instance Zynq ======================== =========== axi_adc 0x43C0_0000 spi_cn0363_axi_regmap 0x44A0_0000 diff --git a/docs/projects/cn0506/index.rst b/docs/projects/cn0506/index.rst index fa8924fbac..cacc9d6745 100644 --- a/docs/projects/cn0506/index.rst +++ b/docs/projects/cn0506/index.rst @@ -137,17 +137,17 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL(see more at :ref:`architecture`). +added to the base address from HDL(see more at :ref:`architecture cpu-intercon-addr`). ======================== =========== -Instance Address +Instance Zynq ======================== =========== axi_iic_main * 0x4160_0000 axi_sysid_0 0x4500_0000 axi_hdmi_clkgen * 0x7900_0000 axi_hdmi_dma * 0x4300_0000 -axi_hdmi_core * 0x70e0_0000 -axi_spdif_tx_core * 0x75c0_0000 +axi_hdmi_core * 0x70E0_0000 +axi_spdif_tx_core * 0x75C0_0000 axi_i2s_adi ** 0x7760_0000 axi_iic_fmc ** 0x4162_0000 ======================== =========== diff --git a/docs/projects/cn0540/index.rst b/docs/projects/cn0540/index.rst index af4bb6dad8..5b2e90c2af 100644 --- a/docs/projects/cn0540/index.rst +++ b/docs/projects/cn0540/index.rst @@ -74,11 +74,11 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL (see more at :ref:`architecture`). +added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). -======================== =========== -Instance Address -======================== =========== +======================== ================= +Instance Zynq*/DE10-Nano** +======================== ================= spi_cn0540_axi_regmap* 0x44A0_0000 axi_cn0540_dma* 0x44A3_0000 axi_iic_cn0540* 0x44A4_0000 @@ -86,7 +86,7 @@ xadc_in* 0x44A5_0000 spi_clkgen* 0x44A7_0000 axi_dmac_0** 0x0002_0000 axi_spi_engine_0** 0x0003_0000 -======================== =========== +======================== ================= .. admonition:: Legend :class: note diff --git a/docs/projects/cn0561/index.rst b/docs/projects/cn0561/index.rst index b87de3d893..99225a2c09 100644 --- a/docs/projects/cn0561/index.rst +++ b/docs/projects/cn0561/index.rst @@ -98,16 +98,24 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL(see more at :ref:`architecture`). +added to the base address from HDL(see more at :ref:`architecture cpu-intercon-addr`). -======================== =========== -Instance Address -======================== =========== +======================== =============== +Instance Zynq/DE10-Nano* +======================== =============== spi_cn0561_axi_regmap 0x44A0_0000 axi_cn0561_dma 0x44A3_0000 odr_generator 0x44B0_0000 axi_cn0561_clkgen 0x44B1_0000 -======================== =========== +axi_dmac_0* 0x0002_0000 +axi_spi_engine_0* 0x0003_0000 +odr_generator* 0x0004_0000 +======================== =============== + +.. admonition:: Legend + :class: note + + ``*`` instantiated only for DE10-Nano SPI connections ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/projects/cn0577/index.rst b/docs/projects/cn0577/index.rst index 6f637f839d..c65a23c979 100644 --- a/docs/projects/cn0577/index.rst +++ b/docs/projects/cn0577/index.rst @@ -98,7 +98,7 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL (see more at :ref:`architecture`). +added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). ==================== =============== Instance Zynq/Microblaze diff --git a/docs/projects/cn0579/index.rst b/docs/projects/cn0579/index.rst index 80f354732d..5092dc7593 100644 --- a/docs/projects/cn0579/index.rst +++ b/docs/projects/cn0579/index.rst @@ -71,7 +71,7 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL (see more at :ref:`architecture`). +added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). =============== =========== =========== Instance Zynq Cyclone V diff --git a/docs/projects/cn0585/index.rst b/docs/projects/cn0585/index.rst index 682dc4dfe2..d575ef559a 100644 --- a/docs/projects/cn0585/index.rst +++ b/docs/projects/cn0585/index.rst @@ -66,24 +66,24 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL (see more at :ref:`architecture`). - -==================== ======================= -Instance Address Zynq/Microblaze -==================== ======================= - axi_ltc2387_0 0X44A0_0000 - axi_ltc2387_1 0X44A1_0000 - axi_ltc2387_2 0X44A2_0000 - axi_ltc2387_3 0X44A3_0000 - axi_ltc2387_dma 0X44A4_0000 - axi_clkgen 0X44B0_0000 - axi_pwm_gen 0X44B1_0000 - max_spi 0X44B2_0000 - axi_ad3552r_0 0X44D0_0000 - axi_dac_0_dma 0X44D3_0000 - axi_ad3552r_1 0X44E0_0000 - axi_dac_1_dma 0X44E3_0000 -==================== ======================= +added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). + +================ =============== +Instance Zynq/Microblaze +================ =============== +axi_ltc2387_0 0X44A0_0000 +axi_ltc2387_1 0X44A1_0000 +axi_ltc2387_2 0X44A2_0000 +axi_ltc2387_3 0X44A3_0000 +axi_ltc2387_dma 0X44A4_0000 +axi_clkgen 0X44B0_0000 +axi_pwm_gen 0X44B1_0000 +max_spi 0X44B2_0000 +axi_ad3552r_0 0X44D0_0000 +axi_dac_0_dma 0X44D3_0000 +axi_ad3552r_1 0X44E0_0000 +axi_dac_1_dma 0X44E3_0000 +================ =============== I2C connections ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/projects/max96724/index.rst b/docs/projects/max96724/index.rst index a40d1e05a3..de83350aab 100644 --- a/docs/projects/max96724/index.rst +++ b/docs/projects/max96724/index.rst @@ -62,7 +62,7 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL (see more at :ref:`architecture`). +added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). ======================== =========== Instance Address diff --git a/docs/projects/pulsar_adc/index.rst b/docs/projects/pulsar_adc/index.rst index e7df78a4e8..b17c1214d7 100644 --- a/docs/projects/pulsar_adc/index.rst +++ b/docs/projects/pulsar_adc/index.rst @@ -189,7 +189,7 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL(see more at :ref:`architecture`). +added to the base address from HDL(see more at :ref:`architecture cpu-intercon-addr`). ========================= =========== Instance Address diff --git a/docs/projects/pulsar_lvds/index.rst b/docs/projects/pulsar_lvds/index.rst index c4bf1a3fd8..a176c75e66 100644 --- a/docs/projects/pulsar_lvds/index.rst +++ b/docs/projects/pulsar_lvds/index.rst @@ -165,10 +165,10 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL (see more at :ref:`architecture`). +added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). ======================== =========== -Instance Address +Instance Zynq ======================== =========== axi_pulsar_lvds 0x44A0_0000 axi_pulsar_lvds_dma 0x44A3_0000 diff --git a/docs/projects/template/index.rst b/docs/projects/template/index.rst index d1f8e2b7d0..dc0c6dec1b 100644 --- a/docs/projects/template/index.rst +++ b/docs/projects/template/index.rst @@ -201,7 +201,7 @@ CPU/Memory interconnects addresses KEEP THIS PARAGRAPH The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL (see more at :ref:`architecture`). +added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). .. If there are any PL SPI connections, they must be added in this table too diff --git a/docs/user_guide/architecture.rst b/docs/user_guide/architecture.rst index d115c4d450..ddc479bed8 100644 --- a/docs/user_guide/architecture.rst +++ b/docs/user_guide/architecture.rst @@ -146,6 +146,8 @@ In HDL, these ports are named slightly different than how they're in the documentations. Thus, to make it easier for beginners, here you have the naming of the ports depending on the microprocessor used. +.. _architecture cpu-intercon-addr: + CPU/Memory interconnects addresses ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ From b6f0bb837280154d185da075715fb71d263061af Mon Sep 17 00:00:00 2001 From: Iulia Moldovan Date: Tue, 19 Nov 2024 09:34:49 +0200 Subject: [PATCH 07/10] docs/projects: Fixes and cleanup On all project docs: * Fix the way links are written * Fix lists indentation * Remove trailing whitespaces Additionally: * ad3552r_evb: Change the title according to the project name * ad408x_fmc_evb: Add newline at end of file * ad4110: Fix page title * ad411x_ad717x: - Remove link to AD4170-4 as this is not part of this project - Fix links to boards, as they weren't ok for EVAL-AD7173/5 * ad4170_asdz: - Remove wrong link to EVAL-AD4170-ASDZ, as it doesn't exist yet - Add links to all supported devices * ad4630_fmc: Add missing links to ADAQ4224 * ad5766_sdz: Add link to no-OS driver * ad57xx_ardz: Add section for the block diagram * ad5758_sdz: Add section for the block diagram * ad7124_asdz: Fix links to evaluation boards, as they were pointing to the chips * ad9213_evb: Add section for the block diagram * ad9656_fmc: Fix wrong name in diagram * adv7513: Add section for the block diagram * cn0561: Fix evaluation board link * cn0579: Add section for the block diagram Signed-off-by: Iulia Moldovan --- docs/projects/ad3552r_evb/index.rst | 35 +-- docs/projects/ad408x_fmc_evb/index.rst | 57 ++-- docs/projects/ad4110/index.rst | 27 +- docs/projects/ad411x_ad717x/index.rst | 57 ++-- docs/projects/ad4134_fmc/index.rst | 28 +- docs/projects/ad4170_asdz/index.rst | 51 ++-- docs/projects/ad4630_fmc/index.rst | 95 ++++--- docs/projects/ad469x_evb/index.rst | 2 +- docs/projects/ad485x_fmcz/index.rst | 56 ++-- docs/projects/ad5758_sdz/index.rst | 5 +- docs/projects/ad5766_sdz/index.rst | 34 +-- docs/projects/ad57xx_ardz/index.rst | 3 + docs/projects/ad7124_asdz/index.rst | 17 +- docs/projects/ad7134_fmc/index.rst | 32 ++- docs/projects/ad738x_fmc/index.rst | 116 ++++---- docs/projects/ad7606x_fmc/index.rst | 137 +++++----- docs/projects/ad7616_sdz/index.rst | 55 ++-- docs/projects/ad77681evb/index.rst | 2 +- docs/projects/ad7768evb/index.rst | 37 ++- docs/projects/ad777x_ardz/index.rst | 38 ++- docs/projects/ad9081_fmca_ebz/index.rst | 248 +++++++++--------- docs/projects/ad9213_evb/index.rst | 39 ++- .../ad9656_fmc_xilinx_block_diagram.svg | 20 +- docs/projects/ad9656_fmc/index.rst | 6 +- docs/projects/ad9739a_fmc/index.rst | 8 +- docs/projects/adaq7980_sdz/index.rst | 23 +- docs/projects/adrv9026/index.rst | 99 +++---- docs/projects/adrv904x/index.rst | 2 +- docs/projects/adv7511/index.rst | 8 +- docs/projects/adv7513/index.rst | 46 ++-- docs/projects/cn0363/index.rst | 4 +- docs/projects/cn0506/index.rst | 10 +- docs/projects/cn0561/index.rst | 79 +++--- docs/projects/cn0577/index.rst | 2 +- docs/projects/cn0579/index.rst | 3 + docs/projects/max96724/index.rst | 12 +- docs/projects/pulsar_lvds/index.rst | 12 +- 37 files changed, 736 insertions(+), 769 deletions(-) diff --git a/docs/projects/ad3552r_evb/index.rst b/docs/projects/ad3552r_evb/index.rst index 818e678a1b..c5be441ba7 100644 --- a/docs/projects/ad3552r_evb/index.rst +++ b/docs/projects/ad3552r_evb/index.rst @@ -1,16 +1,16 @@ .. _ad3552r_evb: -EVAL-AD3552R HDL project +AD3552R-EVB HDL project ================================================================================ Overview ------------------------------------------------------------------------------- -The :adi:`EVAL-AD3552R ` is an evaluation board for the -:adi:`AD3552R `, a dual-channel, 16-bit fast precision -digital-to-analog converter (DAC). Each channel of the :adi:`AD3552R ` -is equipped with a different transimpedance amplifier: Channel 0 has a fast -amplifier that achieves the optimal dynamic performance and Channel 1 has a +The :adi:`EVAL-AD3552R` is an evaluation board for the +:adi:`AD3552R`, a dual-channel, 16-bit fast precision +digital-to-analog converter (DAC). Each channel of the :adi:`AD3552R` +is equipped with a different transimpedance amplifier: Channel 0 has a fast +amplifier that achieves the optimal dynamic performance and Channel 1 has a precision amplifier that guarantees the optimal DC precision over temperature. The board allows testing all the output ranges of the DAC, waveform generation, @@ -19,12 +19,12 @@ power supply and reference options. Supported boards ------------------------------------------------------------------------------- -- :adi:`EVAL-AD3552R ` +- :adi:`EVAL-AD3552R` Supported devices ------------------------------------------------------------------------------- -- :adi:`AD3552R` +- :adi:`AD3552R` Supported carriers ------------------------------------------------------------------------------- @@ -45,7 +45,7 @@ Block design .. warning:: - The VADJ for the Zedboard must be set to 1.8V. + The VADJ for Zedboard must be set to 1.8V. Block diagram ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -131,8 +131,8 @@ Below are the Programmable Logic interrupts used in this project. ================ === ========== =========== Instance name HDL Linux Zynq Actual Zynq -================ === ========== =========== -axi_dac_dma 13 57 89 +================ === ========== =========== +axi_dac_dma 13 57 89 ================ === ========== =========== Building the HDL project @@ -162,21 +162,22 @@ Resources Systems related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :dokuwiki:`[Wiki] EVAL-AD3552R Evaluation Board on ZedBoard User Guide ` +- :dokuwiki:`[Wiki] EVAL-AD3552R Evaluation Board on ZedBoard User Guide ` Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheets: +- Product datasheets: - - :adi:`AD3552R` + - :adi:`AD3552R` + - :adi:`EVAL-AD3552R` -- :adi:`UG-2217, User Guide | EVAL-AD3552R ` +- :adi:`UG-2217, User Guide | EVAL-AD3552R ` HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`EVAL-AD3552R HDL project source code ` +- :git-hdl:`EVAL-AD3552R HDL project source code ` .. list-table:: :widths: 30 35 35 @@ -217,7 +218,7 @@ HDL related Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :dokuwiki:`[Wiki] AD3552R Dual Channel, 16-Bit, 33 MUPS, Multispan, Multi-IO SPI DAC Linux device driver ` +- :dokuwiki:`[Wiki] AD3552R Dual Channel, 16-Bit, 33 MUPS, Multispan, Multi-IO SPI DAC Linux device driver ` .. include:: ../common/more_information.rst diff --git a/docs/projects/ad408x_fmc_evb/index.rst b/docs/projects/ad408x_fmc_evb/index.rst index 4711a6cd9c..a03103bffd 100644 --- a/docs/projects/ad408x_fmc_evb/index.rst +++ b/docs/projects/ad408x_fmc_evb/index.rst @@ -6,12 +6,11 @@ AD408X-FMC-EVB HDL project Overview ------------------------------------------------------------------------------- -The :adi:`EVAL-AD4080-FMC ` is designed to demonstrate the -:adi:`AD4080 ` -performance. +The :adi:`EVAL-AD4080-FMC` is designed to demonstrate the +:adi:`AD4080` performance. -The :adi:`EVAL-AD4080-FMC ` HDL design supports the following -:adi:`AD4080 ` features: +The :adi:`EVAL-AD4080-FMC` HDL design supports the following +:adi:`AD4080` features: * Single/Dual lane DDR data capture * Self synchronization using the fixed pattern and bit-slip feature @@ -20,23 +19,24 @@ The :adi:`EVAL-AD4080-FMC ` HDL design supports the following interface (SPI) * Sampling rate capability between 1.25 MSPS and 40 MSPS -The :adi:`EVAL-AD4080-FMC ` evaluation board was designed for +The :adi:`EVAL-AD4080-FMC` evaluation board was designed for use with the Digilent ZedBoard via the field programmable gate array(FPGA) mezzanine card (FMC) connector. Supported boards ------------------------------------------------------------------------------- -- :adi:`EVAL-AD4080-FMC ` +- :adi:`EVAL-AD4080-FMC` Supported devices ------------------------------------------------------------------------------- -- :adi:`AD4080` -- :adi:`AD9508` -- :adi:`ADF4350` -- :adi:`LT6236` -- :adi:`ADP7182` -- :adi:`ADA4945-1` + +- :adi:`AD4080` +- :adi:`AD9508` +- :adi:`ADA4945-1` +- :adi:`ADF4350` +- :adi:`ADP7182` +- :adi:`LT6236` Supported carriers ------------------------------------------------------------------------------- @@ -199,19 +199,19 @@ Systems related Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheets: +- Product datasheets: - - :adi:`AD4080` - - :adi:`AD9508` - - :adi:`ADF4350` - - :adi:`LT6236` - - :adi:`ADP7182` - - :adi:`ADA4945-1` + - :adi:`AD4080` + - :adi:`AD9508` + - :adi:`ADA4945-1` + - :adi:`ADF4350` + - :adi:`ADP7182` + - :adi:`LT6236` HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`AD408x-FMC-EVB HDL project source code ` +- :git-hdl:`AD408x-FMC-EVB HDL project source code ` .. list-table:: :widths: 30 35 35 @@ -248,15 +248,14 @@ HDL related Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Python support: +- Python support: - - `PyADI-IIO documentation `__ - - `PyADI-IIO example `__ - - `PyADI-IIO class `__ - - AD4080-FMC-EVB Linux device tree :git-linux:`zynq-zed-adv7511-ad4080.dts - ` - - AD4080 Linux driver :git-linux:`ad4080.c ` + - `PyADI-IIO documentation `__ + - `PyADI-IIO example `__ + - `PyADI-IIO class `__ + - AD4080-FMC-EVB Linux device tree :git-linux:`arch/arm/boot/dts/zynq-zed-adv7511-ad4080.dts` + - AD4080 Linux driver :git-linux:`ad4080.c ` .. include:: ../common/more_information.rst -.. include:: ../common/support.rst \ No newline at end of file +.. include:: ../common/support.rst diff --git a/docs/projects/ad4110/index.rst b/docs/projects/ad4110/index.rst index 7a018a7222..153cc97367 100644 --- a/docs/projects/ad4110/index.rst +++ b/docs/projects/ad4110/index.rst @@ -1,6 +1,6 @@ .. _ad4110: -AD4110-SDZ HDL project +AD4110 HDL project ================================================================================ Overview @@ -42,17 +42,17 @@ Applications: Supported boards ------------------------------------------------------------------------------- -- :adi:`EVAL-AD4110-1SDZ ` +- :adi:`EVAL-AD4110-1` Supported devices ------------------------------------------------------------------------------- -- :adi:`AD4110-1` +- :adi:`AD4110-1` Supported carriers ------------------------------------------------------------------------------- -- :xilinx:`ZedBoard ` on PMODs +- :xilinx:`ZedBoard ` on PMODs Block design ------------------------------------------------------------------------------- @@ -65,8 +65,7 @@ The data path and clock domains are depicted in the below diagram: .. image:: ad4110_block_diagram.svg :width: 800 :align: center - :alt: AD4110_SDZ block diagram - + :alt: AD4110 block diagram Jumper setup ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -111,7 +110,7 @@ GPIOs The Software GPIO number is calculated as follows: -- Zynq-7000: if PS7 is used, then the offset is 54 +- Zynq-7000: if PS7 is used, then the offset is 54 .. list-table:: :widths: 25 25 25 25 @@ -158,13 +157,13 @@ Resources Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheet: :adi:`AD4110-1` -- `UG-1203: EVAL-AD4110-1SDZ Board User Guide `__ +- Product datasheet: :adi:`AD4110-1` +- `UG-1203: EVAL-AD4110-1SDZ Board User Guide `__ HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`AD4110-SDZ HDL project source code ` +- :git-hdl:`AD4110 HDL project source code ` .. list-table:: :widths: 30 35 35 @@ -201,10 +200,10 @@ HDL related Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-no-os:`AD4110-SDZ No-OS project source code ` -- :git-no-os:`AD4110 No-OS Driver source code ` -- :dokuwiki:`AD4110 No-OS Driver documentation ` -- :dokuwiki:`AD4110 IIO Application ` +- :git-no-os:`AD4110 No-OS project source code ` +- :git-no-os:`AD4110 No-OS Driver source code ` +- :dokuwiki:`AD4110 No-OS Driver documentation ` +- :dokuwiki:`AD4110 IIO Application ` .. include:: ../common/more_information.rst diff --git a/docs/projects/ad411x_ad717x/index.rst b/docs/projects/ad411x_ad717x/index.rst index d51c27f97d..adc70963a8 100644 --- a/docs/projects/ad411x_ad717x/index.rst +++ b/docs/projects/ad411x_ad717x/index.rst @@ -28,7 +28,7 @@ digital signal conditioning blocks to allow users to configure an individual setup for each analog input channel in use. The :adi:`AD7172-2` /:adi:`AD7172-4` /:adi:`AD7173-8` features a maximum output -data rate of 31.25 kSPS, :adi:`AD7175-2`/ :adi:`AD7175-8` /:adi:`AD7176-2` +data rate of 31.25 kSPS, :adi:`AD7175-2`/ :adi:`AD7175-8` /:adi:`AD7176-2` features a maximum output data rate of 250 kSPS and :adi:`AD7177-2` features a maximum output data rate of 10 kSPS. @@ -44,35 +44,35 @@ capturing continuous samples at the maximum sample rate. Supported boards --------------------------------------------------------------------------------- -- :adi:`EVAL-AD4111-ARDZ ` -- :adi:`EVAL-AD4112-ARDZ ` -- :adi:`EVAL-AD4114-SDZ ` -- :adi:`EVAL-AD4115-SDZ ` -- :adi:`EVAL-AD4116-ASDZ ` -- :adi:`EVAL-AD7173-8ARDZ ` -- :adi:`EVAL-AD7175-8ARDZ ` +- :adi:`EVAL-AD4111` +- :adi:`EVAL-AD4112` +- :adi:`EVAL-AD4114` +- :adi:`EVAL-AD4115` +- :adi:`EVAL-AD4116` +- :adi:`EVAL-AD7173-8SDZ` +- :adi:`EVAL-AD7175-8` Supported devices --------------------------------------------------------------------------------- -- :adi:`AD4111` -- :adi:`AD4112` -- :adi:`AD4113` -- :adi:`AD4114` -- :adi:`AD4115` -- :adi:`AD4116` -- :adi:`AD7172-2` -- :adi:`AD7172-4` -- :adi:`AD7173-8` -- :adi:`AD7175-2` -- :adi:`AD7175-8` -- :adi:`AD7176-2` -- :adi:`AD7177-2` +- :adi:`AD4111` +- :adi:`AD4112` +- :adi:`AD4113` +- :adi:`AD4114` +- :adi:`AD4115` +- :adi:`AD4116` +- :adi:`AD7172-2` +- :adi:`AD7172-4` +- :adi:`AD7173-8` +- :adi:`AD7175-2` +- :adi:`AD7175-8` +- :adi:`AD7176-2` +- :adi:`AD7177-2` Supported carriers ------------------------------------------------------------------------------- -- :intel:`DE10-Nano ` Arduino shield connector +- :intel:`DE10-Nano ` Arduino shield connector Block design ------------------------------------------------------------------------------- @@ -80,7 +80,6 @@ Block design Block diagram ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - The data path and clock domains are depicted in the below diagram: .. image:: ad411x_ad717x_hdl.svg @@ -141,7 +140,7 @@ GPIOs The Software GPIO number is calculated as follows: -- DE10-Nano: the offset is 32 +- DE10-Nano: the offset is 32 .. list-table:: :widths: 25 25 25 25 @@ -176,8 +175,8 @@ Below are the Programmable Logic interrupts used in this project. ================ === =============== ================ Instance name HDL Linux DE10-Nano Actual DE10-Nano ================ === =============== ================ -axi_spi_engine_0 5 45 77 -axi_dmac_0 4 44 76 +axi_spi_engine_0 5 45 77 +axi_dmac_0 4 44 76 ================ === =============== ================ Building the HDL project @@ -209,13 +208,13 @@ Hardware related - Product datasheets: - - :adi:`AD4170-4` - :adi:`AD4111` - :adi:`AD4112` - :adi:`AD4113` - :adi:`AD4114` - :adi:`AD4115` - :adi:`AD4116` + - :adi:`AD4170-4` - :adi:`AD7172-2` - :adi:`AD7172-4` - :adi:`AD7173-8` @@ -227,7 +226,7 @@ Hardware related HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`AD411x_AD717x HDL project source code ` +- :git-hdl:`AD411x_AD717x HDL project source code ` .. list-table:: :widths: 30 35 35 @@ -244,7 +243,7 @@ HDL related - :ref:`here ` * - AXI_PWM_GEN - :git-hdl:`library/axi_pwm_gen` - - :dokuwiki:`[Wiki] ` + - :dokuwiki:`[Wiki] ` * - AXI_SYSID - :git-hdl:`library/axi_sysid ` - :ref:`here ` diff --git a/docs/projects/ad4134_fmc/index.rst b/docs/projects/ad4134_fmc/index.rst index f897fa2fc4..73503a724c 100644 --- a/docs/projects/ad4134_fmc/index.rst +++ b/docs/projects/ad4134_fmc/index.rst @@ -35,17 +35,17 @@ free ADC device. Supported boards ------------------------------------------------------------------------------- -- :adi:`EVAL-AD4134 ` +- :adi:`EVAL-AD4134` Supported devices ------------------------------------------------------------------------------- -- :adi:`AD4134` +- :adi:`AD4134` Supported carriers ------------------------------------------------------------------------------- -- :xilinx:`ZedBoard ` on FMC slot +- :xilinx:`ZedBoard ` on FMC slot Block design ------------------------------------------------------------------------------- @@ -109,7 +109,7 @@ GPIOs The Software GPIO number is calculated as follows: -- Zynq-7000: if PS7 is used, then offset is 54 +- Zynq-7000: if PS7 is used, then offset is 54 .. list-table:: :widths: 25 25 25 25 @@ -192,14 +192,13 @@ Resources Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheet: :adi:`AD4134` - -- `UG-2016, EVAL-AD4134FMCZ Board User Guide `__ +- Product datasheet: :adi:`AD4134` +- `UG-2016, EVAL-AD4134FMCZ Board User Guide `__ HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`AD4134-FMC HDL project source code ` +- :git-hdl:`AD4134-FMC HDL project source code ` .. list-table:: :widths: 30 35 35 @@ -248,22 +247,21 @@ HDL related - :git-hdl:`library/util_i2c_mixer` - --- -- :ref:`SPI Engine Framework documentation ` +- :ref:`SPI Engine Framework documentation ` Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Linux support: -- :git-linux:`Linux device tree zynq-zed-adv7511-ad4134.dts ` -- :git-linux:`Linux driver ad4134.c ` +- :git-linux:`Linux device tree zynq-zed-adv7511-ad4134.dts ` +- :git-linux:`Linux driver ad4134.c ` No-OS support: -- :git-no-os:`AD4134_FMC No-OS project source code ` -- :git-no-os:`AD4134/AD7134 No-OS Driver source code ` -- :dokuwiki:`AD4134/AD7134 No-OS Software documentation[Wiki] ` -- :dokuwiki:`How to build No-OS ` +- :git-no-os:`AD4134_FMC No-OS project source code ` +- :git-no-os:`AD4134/AD7134 No-OS Driver source code ` +- :dokuwiki:`AD4134/AD7134 No-OS Software documentation[Wiki] ` .. include:: ../common/more_information.rst diff --git a/docs/projects/ad4170_asdz/index.rst b/docs/projects/ad4170_asdz/index.rst index 047caa1d7b..315db411b2 100644 --- a/docs/projects/ad4170_asdz/index.rst +++ b/docs/projects/ad4170_asdz/index.rst @@ -6,41 +6,42 @@ AD4170_ASDZ HDL project Overview -------------------------------------------------------------------------------- -The HDL reference design for the :adi:`AD4170-4` and :adi:`AD4170-8` provides a -high resolution, 24-Bit, DC to 50 kHz Input Bandwidth, Multichannel, Low Noise +The HDL reference design for the :adi:`AD4170-4` and :adi:`AD4170-8` provides a +high resolution, 24-Bit, DC to 50 kHz Input Bandwidth, Multichannel, Low Noise Precision Sigma-Delta ADC with PGA. The data acquisition board incorporates the AD4170-4 or AD4170-8, a DC to 50 kHz -input bandwidth, low noise, high speed, completely integrated analog front end -for high precision measurement applications. +input bandwidth, low noise, high speed, completely integrated analog front end +for high precision measurement applications. -The AD4170-4/8 offers output data rates from 7.6 SPS up to 500 kSPS. +The AD4170-4/8 offers output data rates from 7.6 SPS up to 500 kSPS. The device contains a low noise, 24-bit Σ-Δ analog-to-digital converter (ADC), -and can be configured to have 4 differential inputs or 8 single-ended or +and can be configured to have 4 differential inputs or 8 single-ended or pseudodifferential inputs. The on-chip low noise gain stage ensures that signals of small amplitude can be interfaced directly to the AD4170-4/8. This project has a :ref:`spi_engine` instance to control and acquire data from -the AD4170-4/8 24-bit precision ADC. This instance provides support for +the AD4170-4/8 24-bit precision ADC. This instance provides support for capturing continuous samples at the maximum sample rate. Supported boards ------------------------------------------------------------------------------- -- :adi:`EVAL-AD7140-ASDZ ` +- EVAL-AD4170-ASDZ Supported devices ------------------------------------------------------------------------------- -- :adi:`AD4170` -- :adi:`AD4171` -- :adi:`AD4172` +- :adi:`AD4170` +- :adi:`AD4170-4` +- :adi:`AD4171` +- :adi:`AD4172` Supported carriers ------------------------------------------------------------------------------- -- :xilinx:`Cora Z7-07S ` Arduino shield connector -- :intel:`DE10-Nano ` Arduino shield connector +- :xilinx:`Cora Z7-07S ` Arduino shield connector +- :intel:`DE10-Nano ` Arduino shield connector Block design ------------------------------------------------------------------------------- @@ -75,8 +76,8 @@ axi_spi_engine_0** 0x0003_0000 .. admonition:: Legend :class: note - - ``*`` instantiated only for Cora Z7S - - ``**`` instantiated only for DE10-Nano + - ``*`` instantiated only for Cora Z7S + - ``**`` instantiated only for DE10-Nano I2C connections ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -104,8 +105,8 @@ I2C connections .. admonition:: Legend :class: note - - ``*`` instantiated only for Cora Z7S - - ``**`` instantiated only for DE10-Nano + - ``*`` instantiated only for Cora Z7S + - ``**`` instantiated only for DE10-Nano SPI connections ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -128,7 +129,7 @@ GPIOs The Software GPIO number is calculated as follows: -- Cora Z7S: the offset is 54 +- Cora Z7S: the offset is 54 .. list-table:: :widths: 25 25 25 25 @@ -151,7 +152,7 @@ The Software GPIO number is calculated as follows: - 32 - 86 -- DE10-Nano: the offset is 32 +- DE10-Nano: the offset is 32 .. list-table:: :widths: 25 25 25 25 @@ -227,14 +228,12 @@ Resources Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheets: - - - :adi:`AD4170-4` +- Product datasheet: :adi:`AD4170-4` HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`AD4170_ASDZ HDL project source code ` +- :git-hdl:`AD4170_ASDZ HDL project source code ` .. list-table:: :widths: 30 35 35 @@ -274,10 +273,10 @@ HDL related .. admonition:: Legend :class: note - - ``*`` instantiated only for Cora Z7S - - ``**`` instantiated only for DE10-Nano + - ``*`` instantiated only for Cora Z7S + - ``**`` instantiated only for DE10-Nano -- :ref:`SPI Engine Framework documentation ` +- :ref:`SPI Engine Framework documentation ` Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/projects/ad4630_fmc/index.rst b/docs/projects/ad4630_fmc/index.rst index 734d396070..a9bff6a06a 100644 --- a/docs/projects/ad4630_fmc/index.rst +++ b/docs/projects/ad4630_fmc/index.rst @@ -9,7 +9,7 @@ Overview The :adi:`AD4630-24` is a two-channel, simultaneous sampling, Easy Drive, 2 MSPS successive approximation register (SAR) analog-to-digital converter (ADC). The :adi:`AD4030-24` is the single channel version. With a guaranteed maximum ±0.9 -ppm INL and no missing codes at 24-bits, the :adi:`AD4630-24` and +ppm INL and no missing codes at 24-bits, the :adi:`AD4630-24` and :adi:`AD4030-24` achieve unparalleled precision from −40°C to +125°C. The :adi:`AD4030-16` is a 16-bit dual channel version. @@ -37,10 +37,10 @@ integrates all critical power supply and reference bypass capacitors, reducing the footprint and system component count, and lessening sensitivity to board layout. -The ADAQ4224 is a μModule® precision data acquisition (DAQ) signal chain -solution that reduces the development cycle of a precision measurement system -by transferring the signal chain design challenge of component selection, -optimization, and layout from the designer to the device. With a guaranteed +The ADAQ4224 is a μModule® precision data acquisition (DAQ) signal chain +solution that reduces the development cycle of a precision measurement system +by transferring the signal chain design challenge of component selection, +optimization, and layout from the designer to the device. With a guaranteed maximum ±TBD ppm INL and no missing codes at 24 bits, the ADAQ4224 achieves unparalleled precision from −40°C to +85°C. @@ -62,28 +62,28 @@ Applications: * Seismology * Semiconductor manufacturing * Scientific instrumentation - + Supported boards ------------------------------------------------------------------------------- -- :adi:`EVAL-AD4030-24FMCZ ` -- :adi:`EVAL-AD4630-16FMCZ ` -- :adi:`EVAL-AD4630-24FMCZ ` -- EVAL-ADAQ4224-FMCZ -- EVAL-ISO-4224-FMCZ +- :adi:`EVAL-AD4030-24FMCZ` +- :adi:`EVAL-AD4630-16FMCZ` +- :adi:`EVAL-AD4630-24FMCZ` +- :adi:`EVAL-ADAQ4224-FMCZ` +- :adi:`EV-ISO-4224-FMCZ` Supported devices ------------------------------------------------------------------------------- -- :adi:`AD4030-24` -- :adi:`AD4630-16` -- :adi:`AD4630-24` -- ADAQ4224 +- :adi:`AD4030-24` +- :adi:`AD4630-16` +- :adi:`AD4630-24` +- :adi:`ADAQ4224` Supported carriers ------------------------------------------------------------------------------- -- :xilinx:`ZedBoard ` on FMC slot +- :xilinx:`ZedBoard ` on FMC slot Block design --------------------------------------------------------------------------------- @@ -169,20 +169,31 @@ Configuration modes ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The CLK_MODE configuration parameter defines clocking mode of the device's -digital interface: Options: 0 - SPI mode, 1 - Echo-clock or Master clock mode +digital interface: + +* 0 - SPI mode +* 1 - Echo-clock or Master clock mode The NUM_OF_SDI configuration parameter defines the number of MOSI lines of the -SPI interface: Options: 1 - Interleaved mode, 2 - 1 lane per channel, -4 - 2 lanes per channel, 8 - 4 lanes per channel +SPI interface: + +* 1 - Interleaved mode +* 2 - 1 lane per channel, +* 4 - 2 lanes per channel +* 8 - 4 lanes per channel The CAPTURE_ZONE configuration parameter defines the capture zone of the next -sample. There are two capture zones: 1 - from negative edge of the BUSY line -until the next CNV positive edge -20ns, 2 - from the next consecutive CNV -positive edge +20ns until the second next consecutive CNV positive edge -20ns +sample. There are two capture zones: + +* 1 - from negative edge of the BUSY line until the next CNV positive edge -20ns +* 2 - from the next consecutive CNV positive edge +20ns until the second next + consecutive CNV positive edge -20ns The DDR_EN configuration parameter defines the type of data transfer. In echo and master clock mode the SDI lines can have Single or Double Data Rates. -Options: 0 - MISO runs on SDR, 1 - MISO runs on DDR. + +* 0 - MISO runs on SDR +* 1 - MISO runs on DDR. CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -203,7 +214,7 @@ sync_generator* 0x44C0_0000 .. admonition:: Legend :class: note - - ``*`` instantiated, but only used for ADAQ4224 with isolated power supply + ``*`` instantiated, but only used for ADAQ4224 with isolated power supply I2C connections ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -222,21 +233,21 @@ I2C connections - axi_iic_fmc - 0x4162_0000 - --- - * - - - - - + * - + - + - - 0x50 - eeprom - * - - - - - + * - + - + - - 0x5F - temperature sensor * .. admonition:: Legend :class: note - - ``*`` Temperature Sensor HW Monitor is present only in ADAQ4224 + - ``*`` Temperature Sensor HW Monitor is present only in ADAQ4224 SPI connections ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -259,7 +270,7 @@ GPIOs The Software GPIO number is calculated as follows: -- Zynq-7000: if PS7 is used, then offset is 54 +- Zynq-7000: if PS7 is used, then offset is 54 .. list-table:: :widths: 25 25 25 25 @@ -293,8 +304,8 @@ The Software GPIO number is calculated as follows: .. admonition:: Legend :class: note - - ``*`` instantiated, but used for ADAQ4224 only - - ``**`` instantiated, but used for ADAQ4224 with isolated power supply + - ``*`` instantiated, but used for ADAQ4224 only + - ``**`` instantiated, but used for ADAQ4224 with isolated power supply Interrupts ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -351,18 +362,18 @@ Systems related Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheets: +- Product datasheets: -- :adi:`AD4030-24` -- :adi:`AD4630-16` -- :adi:`AD4630-24` -- :dokuwiki:`[Wiki] AD4630/AD4030 Evaluation Board User Guide ` + - :adi:`AD4030-24` + - :adi:`AD4630-16` + - :adi:`AD4630-24` +- :dokuwiki:`[Wiki] AD4630/AD4030 Evaluation Board User Guide ` HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`AD4630_FMC HDL project source code ` -- :dokuwiki:`[Wiki] AD4630_FMC HDL project documentation ` +- :git-hdl:`AD4630_FMC HDL project source code ` +- :dokuwiki:`[Wiki] AD4630_FMC HDL project documentation ` .. list-table:: :widths: 30 35 35 @@ -414,7 +425,7 @@ HDL related - :git-hdl:`library/util_i2c_mixer ` - --- -- :ref:`SPI Engine Framework documentation ` +- :ref:`SPI Engine Framework documentation ` Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/projects/ad469x_evb/index.rst b/docs/projects/ad469x_evb/index.rst index 7a77fb4bd0..407ef5e847 100644 --- a/docs/projects/ad469x_evb/index.rst +++ b/docs/projects/ad469x_evb/index.rst @@ -306,7 +306,7 @@ Resources Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheet: +- Product datasheets: - :adi:`AD4695`/:adi:`AD4696` - :adi:`AD4697`/:adi:`AD4698` diff --git a/docs/projects/ad485x_fmcz/index.rst b/docs/projects/ad485x_fmcz/index.rst index 0b4e007d09..d8b8d8b0a7 100644 --- a/docs/projects/ad485x_fmcz/index.rst +++ b/docs/projects/ad485x_fmcz/index.rst @@ -6,8 +6,8 @@ AD485x_FMCZ HDL project Overview ------------------------------------------------------------------------------- -This design is meant to support the AD485x family. -For example, :adi:`EVAL-AD4858` board contains :adi:`AD4858` chip, which is a 20-bit, low +This design is meant to support the AD485x family. For example, +:adi:`EVAL-AD4858` board contains :adi:`AD4858` chip, which is a 20-bit, low noise 8-channel simultaneous sampling successive approximation register (SAR) ADC, with buffered differential, wide common range picoamp inputs. @@ -38,37 +38,25 @@ Supported devices Supported carriers ------------------------------------------------------------------------------- -.. list-table:: - :widths: 35 35 30 - :header-rows: 1 - - * - Evaluation board - - Carrier - - FMC slot - * - :adi:`EVAL-AD4858 ` - - :xilinx:`ZedBoard ` - - FMC LPC - * - :adi:`EVAL-AD4857 ` - - :xilinx:`ZedBoard ` - - FMC LPC - * - :adi:`EVAL-AD4856 ` - - :xilinx:`ZedBoard ` - - FMC LPC - * - :adi:`EVAL-AD4855 ` - - :xilinx:`ZedBoard ` - - FMC LPC - * - :adi:`EVAL-AD4854 ` - - :xilinx:`ZedBoard ` - - FMC LPC - * - :adi:`EVAL-AD4853 ` - - :xilinx:`ZedBoard ` - - FMC LPC - * - :adi:`EVAL-AD4852 ` - - :xilinx:`ZedBoard ` - - FMC LPC - * - :adi:`EVAL-AD4851 ` - - :xilinx:`ZedBoard ` - - FMC LPC ++--------------------+----------+----------+ +| Evaluation board | Carrier | FMC slot | ++====================+==========+==========+ +| :adi:`EVAL-AD4858` | ZedBoard | FMC LPC | ++--------------------+ | | +| :adi:`EVAL-AD4857` | | | ++--------------------+ | | +| :adi:`EVAL-AD4856` | | | ++--------------------+ | | +| :adi:`EVAL-AD4855` | | | ++--------------------+ | | +| :adi:`EVAL-AD4854` | | | ++--------------------+ | | +| :adi:`EVAL-AD4853` | | | ++--------------------+ | | +| :adi:`EVAL-AD4852` | | | ++--------------------+ | | +| :adi:`EVAL-AD4851` | | | ++--------------------+----------+----------+ Block design ------------------------------------------------------------------------------- @@ -219,7 +207,7 @@ Here you can find the quick start guides available for these evaluation boards: HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`AD485x_FMCZ HDL project source code ` +- :git-hdl:`AD485x_FMCZ HDL project source code ` .. list-table:: :widths: 30 35 35 diff --git a/docs/projects/ad5758_sdz/index.rst b/docs/projects/ad5758_sdz/index.rst index 2b0117e5e6..812313b317 100644 --- a/docs/projects/ad5758_sdz/index.rst +++ b/docs/projects/ad5758_sdz/index.rst @@ -54,6 +54,9 @@ Other required hardware Block design ------------------------------------------------------------------------------- +Block diagram +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + The data path and clock domains are depicted in the below diagram: .. image:: ad5758_block_diagram.svg @@ -62,7 +65,7 @@ The data path and clock domains are depicted in the below diagram: :alt: AD5758_SDZ block diagram Jumper setup -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ================== ================ ============================================ Jumper/Solder link Default Position Description diff --git a/docs/projects/ad5766_sdz/index.rst b/docs/projects/ad5766_sdz/index.rst index 75056514ee..2b10e71583 100644 --- a/docs/projects/ad5766_sdz/index.rst +++ b/docs/projects/ad5766_sdz/index.rst @@ -28,7 +28,7 @@ negative high voltage power supplies for the output amplifiers. A VLOGIC supply pin is provided to set the logic levels for the digital interface pins. The :adi:`AD5766`/ :adi:`AD5767` utilize a versatile 4-wire serial interface that operates at clock rates of up to 50 MHz for write mode and up to 10MHz for -readback and daisy-chain mode, and is compatible with SPIR, QSPI., MICROWIRE. +readback and daisy-chain mode, and is compatible with SPIR, QSPI., MICROWIRE. and DSP interface standards. The :adi:`AD5766`/ :adi:`AD5767` are available in a 4mm x 4mm WLCSP package @@ -43,19 +43,19 @@ Applications: Supported boards ------------------------------------------------------------------------------- -- :adi:`EVAL-AD5766 ` +- :adi:`EVAL-AD5766` Supported devices ------------------------------------------------------------------------------- -- :adi:`AD5766` -- :adi:`AD5767` +- :adi:`AD5766` +- :adi:`AD5767` Supported carriers ------------------------------------------------------------------------------- -- :xilinx:`ZedBoard ` on FMC slot -- :adi:`SDP-I-FMC ` +- :xilinx:`ZedBoard ` on FMC slot +- :adi:`SDP-I-FMC ` Block design ------------------------------------------------------------------------------- @@ -148,7 +148,7 @@ GPIOs The Software GPIO number is calculated as follows: -- Zynq-7000: if PS7 is used, then offset is 54 +- Zynq-7000: if PS7 is used, then offset is 54 .. list-table:: :widths: 25 25 25 25 @@ -206,16 +206,16 @@ Resources Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheets: +- Product datasheets: - - :adi:`AD5766` - - :adi:`AD5767` -- `UG-1070, Evaluation Board User Guide `__ + - :adi:`AD5766` + - :adi:`AD5767` +- `UG-1070, Evaluation Board User Guide `__ HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`ad5766_sdz HDL project source code ` +- :git-hdl:`ad5766_sdz HDL project source code ` .. list-table:: :widths: 30 35 35 @@ -235,7 +235,7 @@ HDL related - :ref:`here ` * - AXI_HDMI_TX - :git-hdl:`library/axi_hdmi_tx ` - - :ref:`here ` + - :ref:`here ` * - AXI_I2S_ADI - :git-hdl:`library/axi_i2s_adi ` - --- @@ -259,16 +259,16 @@ HDL related - :ref:`here ` * - UTIL_I2C-MIXER - :git-hdl:`library/util_i2c_mixer ` - - --- + - --- - :ref:`SPI Engine Framework documentation ` Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-no-os:`AD5766 - No-OS driver source code ` -- :dokuwiki:`AD5766 - No-OS Driver [Wiki] ` -- :dokuwiki:`How to build No-OS ` +- :git-no-os:`AD5766 no-OS project ` +- :git-no-os:`AD5766 no-OS driver source code ad5766.c ` +- :dokuwiki:`[Wiki] AD5766 no-OS driver doc. ` .. include:: ../common/more_information.rst diff --git a/docs/projects/ad57xx_ardz/index.rst b/docs/projects/ad57xx_ardz/index.rst index ad585ad82e..81a112b636 100644 --- a/docs/projects/ad57xx_ardz/index.rst +++ b/docs/projects/ad57xx_ardz/index.rst @@ -57,6 +57,9 @@ Supported carriers Block design ------------------------------------------------------------------------------- +Block diagram +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + The data path and clock domains are depicted in the below diagrams: diff --git a/docs/projects/ad7124_asdz/index.rst b/docs/projects/ad7124_asdz/index.rst index ee2311d432..8746da65d2 100644 --- a/docs/projects/ad7124_asdz/index.rst +++ b/docs/projects/ad7124_asdz/index.rst @@ -6,24 +6,24 @@ AD7124-ASDZ HDL project Overview -------------------------------------------------------------------------------- -The HDL reference design for the :adi:`AD7124-4` and :adi:`AD7124-8` provides a -4/8-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and +The HDL reference design for the :adi:`AD7124-4` and :adi:`AD7124-8` provides a +4/8-Channel, Low Noise, Low Power, 24-Bit, Sigma-Delta ADC with PGA and Reference. -The AD7124-4/8 offers output data rates from 1.17 SPS up to 19,200 SPS. -The AD7124-4/8 can achieve simultaneous 50 Hz and 60 Hz rejection when operating -at an output data rate of 25 SPS (single cycle settling), with rejection in +The AD7124-4/8 offers output data rates from 1.17 SPS up to 19,200 SPS. +The AD7124-4/8 can achieve simultaneous 50 Hz and 60 Hz rejection when operating +at an output data rate of 25 SPS (single cycle settling), with rejection in excess of 80 dB achieved at lower output data rates. This project has a SPI instance to control and acquire data from the AD7124-4/8 -24-bit precision ADC. This instance provides support for capturing continuous +24-bit precision ADC. This instance provides support for capturing continuous samples at the maximum sample rate. Supported boards ------------------------------------------------------------------------------- -- :adi:`EVAL-AD7124-4 ` -- :adi:`EVAL-AD7124-8 ` +- :adi:`EVAL-AD7124-4` +- :adi:`EVAL-AD7124-8` Supported devices ------------------------------------------------------------------------------- @@ -121,7 +121,6 @@ the HDL repository, and then build the project as follows: **Linux/Cygwin/WSL** .. code-block:: - :linenos: user@analog:~$ cd hdl/projects/ad7124_asdz/de10nano user@analog:~/hdl/projects/ad7124_asdz/de10nano make diff --git a/docs/projects/ad7134_fmc/index.rst b/docs/projects/ad7134_fmc/index.rst index 3d1aa17359..6d1d9752a6 100644 --- a/docs/projects/ad7134_fmc/index.rst +++ b/docs/projects/ad7134_fmc/index.rst @@ -44,17 +44,17 @@ Xilinx FPGA development board. Supported boards ------------------------------------------------------------------------------- -- :adi:`EVAL-AD7134FMCZ ` +- :adi:`EVAL-AD7134FMCZ` Supported devices ------------------------------------------------------------------------------- -- :adi:`AD7134` +- :adi:`AD7134` Supported carriers ------------------------------------------------------------------------------- -- :xilinx:`ZedBoard ` on FMC slot * +- :xilinx:`ZedBoard ` on FMC slot * .. admonition:: Legend :class: note @@ -64,8 +64,8 @@ Supported carriers Block design ------------------------------------------------------------------------------- -The reference design uses the SPI Engine Framework to interface with the two -AD7134 ADCs. It only supports the slave mode for both devices with both DCLK +The reference design uses the SPI Engine Framework to interface with the two +AD7134 ADCs. It only supports the slave mode for both devices with both DCLK and ODR generated by the FPGA. Each device sends data on 4 of the 8 DIN bits. Block diagram @@ -151,7 +151,7 @@ GPIOs The Software GPIO number is calculated as follows: -- Zynq-7000: if PS7 is used, then offset is 54 +- Zynq-7000: if PS7 is used, then offset is 54 .. list-table:: :widths: 25 25 25 25 @@ -192,8 +192,8 @@ The Software GPIO number is calculated as follows: * - ad713x_resetn[1:0] - INOUT - 33:32 - - 87:86 - + - 87:86 + Interrupts ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -234,14 +234,14 @@ Resources Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheet: :adi:`AD7134` +- Product datasheet: :adi:`AD7134` -- `UG-1599: EVAL-AD7134FMCZ Board User Guide `__ +- `UG-1599: EVAL-AD7134FMCZ Board User Guide `__ HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`AD7134-FMC HDL project source code ` +- :git-hdl:`AD7134-FMC HDL project source code ` .. list-table:: :widths: 30 35 35 @@ -290,18 +290,16 @@ HDL related - :git-hdl:`library/util_i2c_mixer` - --- -- :ref:`SPI Engine Framework documentation ` +- :ref:`SPI Engine Framework documentation ` Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-no-os:`AD7134-FMC No-OS project source code ` - -- :git-no-os:`AD4134/AD7134 No-OS Driver source code ` +- :git-no-os:`AD7134-FMC No-OS project source code ` -- :dokuwiki:`AD4134/AD7134 No-OS Driver documentation ` +- :git-no-os:`AD4134/AD7134 No-OS Driver source code ` -- :dokuwiki:`How to build No-OS ` +- :dokuwiki:`AD4134/AD7134 No-OS Driver documentation ` .. include:: ../common/more_information.rst diff --git a/docs/projects/ad738x_fmc/index.rst b/docs/projects/ad738x_fmc/index.rst index 277287e816..002e510b12 100644 --- a/docs/projects/ad738x_fmc/index.rst +++ b/docs/projects/ad738x_fmc/index.rst @@ -46,39 +46,39 @@ Applications: Supported boards ------------------------------------------------------------------------------- -- :adi:`EVAL-AD7380FMCZ ` -- :adi:`EVAL-AD7381FMCZ ` -- :adi:`EVAL-AD7386FMCZ ` -- :adi:`EVAL-AD7383FMCZ ` -- :adi:`EVAL-AD7380-4FMCZ ` +- :adi:`EVAL-AD7380FMCZ` +- :adi:`EVAL-AD7381FMCZ` +- :adi:`EVAL-AD7386FMCZ` +- :adi:`EVAL-AD7383FMCZ` +- :adi:`EVAL-AD7380-4FMCZ` Supported devices ------------------------------------------------------------------------------- -- :adi:`AD7380` -- :adi:`AD7380-4` -- :adi:`AD7381` -- :adi:`AD7381-4` -- :adi:`AD7383` -- :adi:`AD7383-4` -- :adi:`AD7384` -- :adi:`AD7384-4` -- :adi:`AD7386` -- :adi:`AD7387` -- :adi:`AD7388` -- :adi:`AD7388-4` -- :adi:`AD7389-4` -- :adi:`AD4680` -- :adi:`AD4681` -- :adi:`AD4682` -- :adi:`AD4683` -- :adi:`AD4684` -- :adi:`AD4685` +- :adi:`AD7380` +- :adi:`AD7380-4` +- :adi:`AD7381` +- :adi:`AD7381-4` +- :adi:`AD7383` +- :adi:`AD7383-4` +- :adi:`AD7384` +- :adi:`AD7384-4` +- :adi:`AD7386` +- :adi:`AD7387` +- :adi:`AD7388` +- :adi:`AD7388-4` +- :adi:`AD7389-4` +- :adi:`AD4680` +- :adi:`AD4681` +- :adi:`AD4682` +- :adi:`AD4683` +- :adi:`AD4684` +- :adi:`AD4685` Supported carriers ------------------------------------------------------------------------------- -- :xilinx:`ZedBoard ` on FMC slot +- :xilinx:`ZedBoard ` on FMC slot Block design ------------------------------------------------------------------------------- @@ -113,13 +113,13 @@ In case of the **Alert Indication Output Pin** functionality: make ALERT_SPI_N=1 -The NUM_OF_SDI configuration parameter defines the number of SDI lines used: -- Options: 1, 2, 4. -By default is set to 1. +The **NUM_OF_SDI** configuration parameter defines the number of SDI lines used: +**{1, 2, 4}**. By default is set to 1. -For the ALERT functionality, the following parameters will be used in make +For the **ALERT** functionality, the following parameters will be used in make command: ALERT_SPI_N. -For the serial data output functionality, the following parameters will be + +For the **serial data output** functionality, the following parameters will be used in make command: ALERT_SPI_N, NUM_OF_SDI. Jumper setup @@ -206,7 +206,7 @@ GPIOs The Software GPIO number is calculated as follows: -- Zynq-7000: if PS7 is used, then the offset is 54 +- Zynq-7000: if PS7 is used, then the offset is 54 .. list-table:: :widths: 25 25 25 25 25 25 @@ -287,33 +287,33 @@ Resources Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheets: - - - :adi:`AD7380` - - :adi:`AD7380-4` - - :adi:`AD7381` - - :adi:`AD7381-4` - - :adi:`AD7383` - - :adi:`AD7383-4` - - :adi:`AD7384` - - :adi:`AD7384-4` - - :adi:`AD7386` - - :adi:`AD7387` - - :adi:`AD7388` - - :adi:`AD7388-4` - - :adi:`AD7389-4` - - :adi:`AD4680` - - :adi:`AD4681` - - :adi:`AD4682` - - :adi:`AD4683` - - :adi:`AD4684` - - :adi:`AD4685` -- `UG-1304, Evaluation Board User Guide `__ +- Product datasheets: + + - :adi:`AD7380` + - :adi:`AD7380-4` + - :adi:`AD7381` + - :adi:`AD7381-4` + - :adi:`AD7383` + - :adi:`AD7383-4` + - :adi:`AD7384` + - :adi:`AD7384-4` + - :adi:`AD7386` + - :adi:`AD7387` + - :adi:`AD7388` + - :adi:`AD7388-4` + - :adi:`AD7389-4` + - :adi:`AD4680` + - :adi:`AD4681` + - :adi:`AD4682` + - :adi:`AD4683` + - :adi:`AD4684` + - :adi:`AD4685` +- `UG-1304, Evaluation Board User Guide `__ HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`AD738x_FMC HDL project source code ` +- :git-hdl:`AD738x_FMC HDL project source code ` .. list-table:: :widths: 30 35 35 @@ -362,15 +362,13 @@ HDL related - :git-hdl:`library/util_i2c_mixer ` - --- -- :ref:`SPI Engine Framework documentation ` +- :ref:`SPI Engine Framework documentation ` Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-no-os:`AD738X_FMC No-OS project ` -- :dokuwiki:`AD738X_FMC - No-OS Driver [Wiki] ` - -- :dokuwiki:`How to build No-OS ` +- :git-no-os:`AD738X_FMC No-OS project ` +- :dokuwiki:`AD738X_FMC - No-OS Driver [Wiki] ` .. include:: ../common/more_information.rst diff --git a/docs/projects/ad7606x_fmc/index.rst b/docs/projects/ad7606x_fmc/index.rst index 3691a81460..35f2421c2c 100644 --- a/docs/projects/ad7606x_fmc/index.rst +++ b/docs/projects/ad7606x_fmc/index.rst @@ -27,56 +27,55 @@ lower Vdrive operation, diagnostics, additional oversampling ratios and per channel analog input range selection with bipolar differential, bipolar single-ended and unipolar single-ended options. -The :adi:`EVAL-AD7606B-FMCZ ` and -:adi:`EVAL-AD7606C-18 ` evaluation boards are designed to -help users to easily evaluate the features of :adi:`AD7606B`, +The :adi:`EVAL-AD7606B-FMCZ` and :adi:`EVAL-AD7606C-18` evaluation boards +are designed to help users to easily evaluate the features of :adi:`AD7606B`, :adi:`AD7606C-16` and :adi:`AD7606C-18` analog-to-digital converters (ADCs). Supported boards ------------------------------------------------------------------------------- -- :adi:`EVAL-AD7606B ` -- :adi:`EVAL-AD7606C-16 ` -- :adi:`EVAL-AD7606C-18 ` -- :adi:`EVAL-AD7605-4 ` -- :adi:`EVAL-AD7606-8 ` -- :adi:`EVAL-AD7606-6 ` -- :adi:`EVAL-AD7606-4 ` -- :adi:`EVAL-AD7607 ` -- :adi:`EVAL-AD7608 ` -- :adi:`EVAL-AD7609 ` +- :adi:`EVAL-AD7606B` +- :adi:`EVAL-AD7606C-16` +- :adi:`EVAL-AD7606C-18` +- :adi:`EVAL-AD7605-4` +- :adi:`EVAL-AD7606-8` +- :adi:`EVAL-AD7606-6` +- :adi:`EVAL-AD7606-4` +- :adi:`EVAL-AD7607` +- :adi:`EVAL-AD7608` +- :adi:`EVAL-AD7609` Supported devices ------------------------------------------------------------------------------- -- :adi:`AD7606B` -- :adi:`AD7606C-16` -- :adi:`AD7606C-18` -- :adi:`AD7606` -- :adi:`AD7606-6` -- :adi:`AD7606-4` -- :adi:`AD7607` -- :adi:`AD7608` -- :adi:`AD7609` -- :adi:`ADP7118` -- :adi:`ADR4525` +- :adi:`AD7606B` +- :adi:`AD7606C-16` +- :adi:`AD7606C-18` +- :adi:`AD7606` +- :adi:`AD7606-6` +- :adi:`AD7606-4` +- :adi:`AD7607` +- :adi:`AD7608` +- :adi:`AD7609` +- :adi:`ADP7118` +- :adi:`ADR4525` Supported carriers ------------------------------------------------------------------------------- -- :xilinx:`ZedBoard ` on FMC slot +- :xilinx:`ZedBoard ` on FMC slot Block design ------------------------------------------------------------------------------- The data path of the HDL design is simple as follows: -- the parallel interface is controlled by the - :dokuwiki:`axi_ad7606x ` IP core -- the serial interface is controlled by the :ref:`SPI_Engine ` - Framework -- data is written into memory by a DMA (:ref:`axi_dmac core `) -- all the control pins of the device are driven by GPIOs +- the parallel interface is controlled by the + :ref:`axi_ad7606x IP core ` +- the serial interface is controlled by the :ref:`SPI_Engine ` + Framework +- data is written into memory by a DMA (:ref:`axi_dmac core `) +- all the control pins of the device are driven by GPIOs Block diagram ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -123,16 +122,14 @@ In case of the **SERIAL** interface: This switch is a **hardware** switch. Please rebuild the design if the variable has been changed. - - JP5 - Position A - Serial interface - - JP5 - Position B - Parallel interface + - JP5 - Position A - Serial interface + - JP5 - Position B - Parallel interface The NUM_OF_SDI configuration parameter defines the number of SDI lines used: -- Options: 1, 2, 4, 8. -By default is set to 8. +**{1, 2, 4, 8}**. By default is set to 8. The ADC_N_BITS configuration parameter specifies the ADC resolution: -- Options: 16, 18. -By default it is set to 16. +**{16, 18}**. By default it is set to 16. Jumper setup ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -181,8 +178,8 @@ axi_ad7606x * 0x44A0_0000 .. admonition:: Legend :class: note - - ``*`` instantiated only for INTF=0 (parallel interface) - - ``**`` instantiated only for INTF=1 (serial interface) + - ``*`` instantiated only for INTF=0 (parallel interface) + - ``**`` instantiated only for INTF=1 (serial interface) I2C connections ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -228,7 +225,7 @@ GPIOs The Software GPIO number is calculated as follows: -- Zynq-7000: if PS7 is used, then offset is 54 +- Zynq-7000: if PS7 is used, then offset is 54 .. list-table:: :widths: 25 25 25 25 @@ -274,8 +271,8 @@ The Software GPIO number is calculated as follows: .. admonition:: Legend :class: note - - ``*`` instantiated only for INTF=0 (parallel interface) - - ``**`` instantiated only for INTF=1 (serial interface) + - ``*`` instantiated only for INTF=0 (parallel interface) + - ``**`` instantiated only for INTF=1 (serial interface) Interrupts ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -292,8 +289,8 @@ spi_ad7606 ** 12 56 88 .. admonition:: Legend :class: note - - ``*`` instantiated only for INTF=0 (parallel interface) - - ``**`` instantiated only for INTF=1 (serial interface) + - ``*`` instantiated only for INTF=0 (parallel interface) + - ``**`` instantiated only for INTF=1 (serial interface) Building the HDL project ------------------------------------------------------------------------------- @@ -309,7 +306,6 @@ the HDL repository, and then build the project as follows:. **Linux/Cygwin/WSL** .. code-block:: - :linenos: user@analog:~$ cd hdl/projects/ad7606x_fmc/zed user@analog:~/hdl/projects/ad7606x_fmc/zed$ make DEV_CONFIG=2 INTF=0 @@ -337,9 +333,9 @@ Connections and hardware changes Depending on the required interface mode, some hardware modifications need to be done. - - **JP5** - A - Serial interface - - **JP5** - B - Parallel interface - - **JP7, JP12, JP13, JP14** - B - Differential operation + - **JP5** - A - Serial interface + - **JP5** - B - Parallel interface + - **JP7, JP12, JP13, JP14** - B - Differential operation Resources ------------------------------------------------------------------------------- @@ -347,27 +343,27 @@ Resources Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheets: - - - :adi:`AD7606` - - :adi:`AD7606B` - - :adi:`AD7606C-16` - - :adi:`AD7606C-18` - - :adi:`AD7605-4` - - :adi:`AD7606` - - :adi:`AD7606-6` - - :adi:`AD7606-4` - - :adi:`AD7607` - - :adi:`AD7608` - - :adi:`AD7609` - - :adi:`ADP7118` - - :adi:`ADR4525` - - :adi:`UG-1870, Evaluation Board User Guide ` +- Product datasheets: + + - :adi:`AD7606` + - :adi:`AD7606B` + - :adi:`AD7606C-16` + - :adi:`AD7606C-18` + - :adi:`AD7605-4` + - :adi:`AD7606` + - :adi:`AD7606-6` + - :adi:`AD7606-4` + - :adi:`AD7607` + - :adi:`AD7608` + - :adi:`AD7609` + - :adi:`ADP7118` + - :adi:`ADR4525` + - :adi:`UG-1870, Evaluation Board User Guide ` HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`AD7606X_FMC HDL project source code ` +- :git-hdl:`AD7606X_FMC HDL project source code ` .. list-table:: :widths: 30 35 35 @@ -431,17 +427,16 @@ HDL related .. admonition:: Legend :class: note - - ``*`` instantiated only for INTF=0 (parallel interface) - - ``**`` instantiated only for INTF=1 (serial interface) + - ``*`` instantiated only for INTF=0 (parallel interface) + - ``**`` instantiated only for INTF=1 (serial interface) -- :ref:`SPI Engine Framework documentation ` +- :ref:`SPI Engine Framework documentation ` Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-no-os:`AD7606_FMC No-OS driver source code ` -- :dokuwiki:`AD7606 - No-OS Driver [Wiki] ` -- :dokuwiki:`How to build No-OS ` +- :git-no-os:`AD7606_FMC No-OS driver source code ` +- :dokuwiki:`AD7606 - No-OS Driver [Wiki] ` .. include:: ../common/more_information.rst diff --git a/docs/projects/ad7616_sdz/index.rst b/docs/projects/ad7616_sdz/index.rst index c37f0956ec..407376493d 100644 --- a/docs/projects/ad7616_sdz/index.rst +++ b/docs/projects/ad7616_sdz/index.rst @@ -26,33 +26,33 @@ high-speed serial and parallel interfaces. Supported boards ------------------------------------------------------------------------------- -- :adi:`EVAL-AD7616 ` +- :adi:`EVAL-AD7616` Supported devices ------------------------------------------------------------------------------- -- :adi:`AD7616` +- :adi:`AD7616` Supported carriers ------------------------------------------------------------------------------- -- :xilinx:`ZedBoard ` on FMC slot -- :xilinx:`ZC706` on FMC LPC slot +- :xilinx:`ZedBoard ` on FMC slot +- :xilinx:`ZC706` on FMC LPC slot Other required hardware ------------------------------------------------------------------------------- -- :adi:`SDP-I-FMC ` +- :adi:`SDP-I-FMC ` Block design ------------------------------------------------------------------------------- The data path of the HDL design is simple as follows: -- the parallel interface is controlled by the axi_ad7616 IP core -- the serial interface is controlled by the SPI Engine Framework -- data is written into memory by a DMA (axi_dmac core) -- all the control pins of the device are driven by GPIOs +- the parallel interface is controlled by the axi_ad7616 IP core +- the serial interface is controlled by the SPI Engine Framework +- data is written into memory by a DMA (axi_dmac core) +- all the control pins of the device are driven by GPIOs Block diagram ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -99,8 +99,8 @@ In case of the **SERIAL** interface: This switch is a *hardware* switch. Please rebuild the design if the variable has been changed. - - SL5 - unmounted - Parallel interface - - SL5 - mounted - Serial interface + - SL5 - unmounted - Parallel interface + - SL5 - mounted - Serial interface Jumper setup ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -138,8 +138,8 @@ axi_ad7616 * 0x44A8_0000 .. admonition:: Legend :class: note - - ``*`` instantiated only for SER_PAR_N=0 (parallel interface) - - ``**`` instantiated only for SER_PAR_N=1 (serial interface) + - ``*`` instantiated only for SER_PAR_N=0 (parallel interface) + - ``**`` instantiated only for SER_PAR_N=1 (serial interface) I2C connections ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -185,7 +185,7 @@ GPIOs The Software GPIO number is calculated as follows: -- Zynq-7000: if PS7 is used, then offset is 54 +- Zynq-7000: if PS7 is used, then offset is 54 .. list-table:: :widths: 25 25 25 25 @@ -231,7 +231,7 @@ The Software GPIO number is calculated as follows: .. admonition:: Legend :class: note - - ``**`` instantiated only for SER_PAR_N=1 (serial interface) + - ``**`` instantiated only for SER_PAR_N=1 (serial interface) Interrupts ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -249,8 +249,8 @@ axi_ad7616 * 10 54 87 .. admonition:: Legend :class: note - - ``*`` instantiated only for SER_PAR_N=0 (parallel interface) - - ``**`` instantiated only for SER_PAR_N=1 (serial interface) + - ``*`` instantiated only for SER_PAR_N=0 (parallel interface) + - ``**`` instantiated only for SER_PAR_N=1 (serial interface) Building the HDL project ------------------------------------------------------------------------------- @@ -297,8 +297,8 @@ Connections and hardware changes Depending on the required interface mode, some hardware modifications need to be done. - - **SL5** - unmounted - Parallel interface - - **SL5** - mounted - Serial interface + - **SL5** - unmounted - Parallel interface + - **SL5** - mounted - Serial interface Resources ------------------------------------------------------------------------------- @@ -306,14 +306,13 @@ Resources Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheet: :adi:`AD7616` - -- `UG-1012, Evaluation Board User Guide `__ +- Product datasheet: :adi:`AD7616` +- `UG-1012, Evaluation Board User Guide `__ HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`AD7616_SDZ HDL project source code ` +- :git-hdl:`AD7616_SDZ HDL project source code ` .. list-table:: :widths: 30 35 35 @@ -371,17 +370,15 @@ HDL related .. admonition:: Legend :class: note - - ``*`` instantiated only for SER_PAR_N=0 (parallel interface) - - ``**`` instantiated only for SER_PAR_N=1 (serial interface) + - ``*`` instantiated only for SER_PAR_N=0 (parallel interface) + - ``**`` instantiated only for SER_PAR_N=1 (serial interface) -- :ref:`SPI Engine Framework documentation ` +- :ref:`SPI Engine Framework documentation ` Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-no-os:`AD7616_SDZ No-OS project source code ` - -- :dokuwiki:`How to build No-OS ` +- :git-no-os:`AD7616_SDZ No-OS project source code ` .. include:: ../common/more_information.rst diff --git a/docs/projects/ad77681evb/index.rst b/docs/projects/ad77681evb/index.rst index 92dc36b649..547ef40e7b 100644 --- a/docs/projects/ad77681evb/index.rst +++ b/docs/projects/ad77681evb/index.rst @@ -21,7 +21,7 @@ finite impulse response (FIR) digital filter at 256 kSPS, giving 110.8 kHz input bandwidth (BW), combined with ±1.1 ppm integral nonlinearity (INL), ±30 µV offset error, and ±30 ppm gain error. Wider bandwidth, up to 500 kHz Nyquist, 204 kHz, −3 dB, is available using the sinc5 filter, enabling a view of signals -over an extended range. +over an extended range. A 1.024 MHz sinc5 filter path exists for users seeking an even higher output data rate. This path is quantization noise limited; therefore, it is best suited diff --git a/docs/projects/ad7768evb/index.rst b/docs/projects/ad7768evb/index.rst index fb79f25e11..130e006aa1 100644 --- a/docs/projects/ad7768evb/index.rst +++ b/docs/projects/ad7768evb/index.rst @@ -55,19 +55,19 @@ to +105°C. The device is housed in a 10 mm × 10 mm 64-lead LQFP package with a Supported boards ------------------------------------------------------------------------------- -- :adi:`EVAL-AD7768 ` -- :adi:`EVAL-AD7768-4 ` +- :adi:`EVAL-AD7768` +- :adi:`EVAL-AD7768-4` Supported devices ------------------------------------------------------------------------------- -- :adi:`AD7768` -- :adi:`AD7768-4` +- :adi:`AD7768` +- :adi:`AD7768-4` Supported carriers --------------------------------------------------------------------------------- -- :xilinx:`ZedBoard ` on FMC slot +- :xilinx:`ZedBoard ` on FMC slot Block design ------------------------------------------------------------------------------- @@ -77,9 +77,6 @@ Block diagram The data path and clock domains are depicted in the below diagram: -AD7768-EVB -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - .. image:: ad7768evb_fmc_hdl.svg :width: 800 :align: center @@ -140,7 +137,7 @@ GPIOs The Software GPIO number is calculated as follows: -- Zynq-7000: if PS7 is used, then offset is 54 +- Zynq-7000: if PS7 is used, then offset is 54 .. list-table:: :widths: 25 25 25 25 @@ -214,19 +211,17 @@ Resources Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheets: - -- :adi:`AD7768` -- :adi:`AD7768-4` -- :adi:`UG-917, Evaluation Board User Guide ` -- :adi:`UG-921, Evaluation Board User Guide ` +- Product datasheets: + - :adi:`AD7768` + - :adi:`AD7768-4` +- :adi:`UG-917, Evaluation Board User Guide ` +- :adi:`UG-921, Evaluation Board User Guide ` HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`AD7768-EVB HDL project source code ` -- :dokuwiki:`[Wiki] AD7768-EVB Bare Metal Quick Start Guide ` -- :dokuwiki:`[Wiki] AXI_AD7768 ` +- :git-hdl:`AD7768-EVB HDL project source code ` +- :dokuwiki:`[Wiki] AD7768-EVB Bare Metal Quick Start Guide ` .. list-table:: :widths: 30 35 35 @@ -269,9 +264,9 @@ HDL related Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-linux:`AD7768 Linux driver source code ` -- :git-no-os:`AD7768 No-OS project source code ` -- :dokuwiki:`[Wiki] AD7768 IIO Precision ADC Linux Driver ` +- :git-linux:`AD7768 Linux driver source code ` +- :git-no-os:`AD7768 No-OS project source code ` +- :dokuwiki:`[Wiki] AD7768 IIO Precision ADC Linux Driver ` .. include:: ../common/more_information.rst diff --git a/docs/projects/ad777x_ardz/index.rst b/docs/projects/ad777x_ardz/index.rst index f28c1c27d8..17098095a2 100644 --- a/docs/projects/ad777x_ardz/index.rst +++ b/docs/projects/ad777x_ardz/index.rst @@ -6,23 +6,21 @@ AD777X-ARDZ HDL project Overview ------------------------------------------------------------------------------- -The EVAL-AD7770-ARDZ / EVAL-AD7771-ARDZ / EVAL-AD7779-ARDZ evaluation kit -features the :adi:`AD7770`, :adi:`AD7771`, and :adi:`AD7779` 24-bit, +The EVAL-AD7770-ARDZ / EVAL-AD7771-ARDZ / EVAL-AD7779-ARDZ evaluation kit +features the :adi:`AD7770`, :adi:`AD7771`, and :adi:`AD7779` 24-bit, analog-to-digital converters (ADCs). -The AD777x is an 8-channel, simultaneous sampling analog-to-digital converter -(ADC). Eight full Σ-Δ ADCs are on-chip. The AD777x provides an ultralow input -current to allow direct sensor connection. Each input channel has a +The AD777x is an 8-channel, simultaneous sampling analog-to-digital converter +(ADC). Eight full Σ-Δ ADCs are on-chip. The AD777x provides an ultralow input +current to allow direct sensor connection. Each input channel has a programmable gain stage allowing gains of 1, 2, 4, and 8 to map lower amplitude -sensor outputs into the full-scale ADC input range, maximizing the dynamic +sensor outputs into the full-scale ADC input range, maximizing the dynamic range of the signal chain. Supported boards ------------------------------------------------------------------------------- -- EVAL-AD7770-ARDZ -- EVAL-AD7771-ARDZ -- EVAL-AD7779-ARDZ +- :adi:`EVAL-AD7770/1/9-ARDZ ` Supported devices ------------------------------------------------------------------------------- @@ -51,13 +49,13 @@ Supported carriers - :xilinx:`ZedBoard ` - PMOD-JA, PMOD-JB, PMOD-JC * - EVAL-AD7770-ARDZ - - :intel:`De10-Nano ` + - :intel:`DE10-Nano ` - Arduino shield connector * - EVAL-AD7771-ARDZ - - :intel:`De10-Nano ` + - :intel:`DE10-Nano ` - Arduino shield connector * - EVAL-AD7779-ARDZ - - :intel:`De10-Nano ` + - :intel:`DE10-Nano ` - Arduino shield connector Block design @@ -107,7 +105,7 @@ SPI connections - AD777x - 0 * - PL** - - sys_spi + - sys_spi - AD777x - 0 @@ -115,7 +113,7 @@ SPI connections :class: note - ``*`` only for ZedBoard - - ``**`` only for De10-Nano + - ``**`` only for DE10-Nano GPIOs ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -138,7 +136,7 @@ GPIOs - OUT - 39 - 93 - - 7 + - 7 * - GPIO2 - INOUT - 38 @@ -154,22 +152,22 @@ GPIOs - 36 - 90 - 4 - * - SDP_MCLK + * - SDP_MCLK - OUT - 35 - 89 - 3 - * - SDP_CONVST + * - SDP_CONVST - OUT - 34 - 88 - 2 - * - START_N + * - START_N - OUT - 33 - 87 - 1 - * - ALERT + * - ALERT - IN - 32 - 86 @@ -189,7 +187,7 @@ ad777x_dma** 5 - - 45 77 :class: note - ``*`` only for ZedBoard - - ``**`` only for De10-Nano + - ``**`` only for DE10-Nano Building the HDL project ------------------------------------------------------------------------------- diff --git a/docs/projects/ad9081_fmca_ebz/index.rst b/docs/projects/ad9081_fmca_ebz/index.rst index b27982e53e..160c14b2dd 100644 --- a/docs/projects/ad9081_fmca_ebz/index.rst +++ b/docs/projects/ad9081_fmca_ebz/index.rst @@ -9,8 +9,8 @@ Overview The :adi:`AD9081-FMCA-EBZ ` / :adi:`AD9082-FMCA-EBZ ` reference design (also known as Single MxFE) is a processor based (e.g. Microblaze) embedded system. -This reference design works with :adi:`EVAL-AD9986 ` and -:adi:`EVAL-AD9988 ` as well. +This reference design works with :adi:`EVAL-AD9986` and +:adi:`EVAL-AD9988` as well. The design consists from a receive and a transmit chain. The receive chain transports the captured samples from ADC to the system @@ -42,29 +42,29 @@ but must share the same reference clock. Supported boards ------------------------------------------------------------------------------- -- :adi:`AD9081-FMCA-EBZ ` -- :adi:`AD9082-FMCA-EBZ ` -- :adi:`EVAL-AD9988 ` -- :adi:`EVAL-AD9986 ` +- :adi:`AD9081-FMCA-EBZ ` +- :adi:`AD9082-FMCA-EBZ ` +- :adi:`EVAL-AD9988` +- :adi:`EVAL-AD9986` Supported devices ------------------------------------------------------------------------------- -- :adi:`AD9081` -- :adi:`AD9082` -- :adi:`AD9177` -- :adi:`AD9207` -- :adi:`AD9209` -- :adi:`AD9986` -- :adi:`AD9988` +- :adi:`AD9081` +- :adi:`AD9082` +- :adi:`AD9177` +- :adi:`AD9207` +- :adi:`AD9209` +- :adi:`AD9986` +- :adi:`AD9988` Supported carriers ------------------------------------------------------------------------------- .. note:: - :adi:`EVAL-AD9988 ` can be an alternative to - :adi:`AD9081-FMCA-EBZ ` and :adi:`EVAL-AD9986 ` + :adi:`EVAL-AD9988` can be an alternative to + :adi:`AD9081-FMCA-EBZ ` and :adi:`EVAL-AD9986` can be an alternative to :adi:`AD9082-FMCA-EBZ `. Both :adi:`AD9081` and :adi:`AD9988` have MxFE Quad, 16-bit, 12 GSPS RF DAC @@ -135,13 +135,13 @@ Supported carriers in your setup, the following reworks are required **on the evaluation board**: - - To avoid using an external clock source and fully rely on the HMC7044 - clock chip, rotate the C6D/C4D caps in C5D/C3D position - (Please note: In the latest version of the board, this is now the - default configuration, so this configuration step **might not - be needed anymore**). - - If LEDS V1P0_LED and VINT_LED are not on, please **depopulate R22M - and populate R2M** + - To avoid using an external clock source and fully rely on the HMC7044 + clock chip, rotate the C6D/C4D caps in C5D/C3D position + (Please note: In the latest version of the board, this is now the + default configuration, so this configuration step **might not + be needed anymore**). + - If LEDS V1P0_LED and VINT_LED are not on, please **depopulate R22M + and populate R2M** For the carrier, :intel:`A10SoC `, @@ -185,25 +185,23 @@ Example block design for Single link; M=8; L=4 The Rx links (ADC Path) operate with the following parameters: -- Rx Deframer parameters: L=4, M=8, F=4, S=1, NP=16, N=16 (Quick - Config 0x0A) -- Sample Rate: 250 MSPS -- Dual link: No -- RX_DEVICE_CLK: 250 MHz (Lane Rate/40) -- REF_CLK: 500MHz (Lane Rate/20) -- JESD204B Lane Rate: 10Gbps -- QPLL0 or CPLL +- Rx Deframer parameters: L=4, M=8, F=4, S=1, NP=16, N=16 (Quick Config 0x0A) +- Sample Rate: 250 MSPS +- Dual link: No +- RX_DEVICE_CLK: 250 MHz (Lane Rate/40) +- REF_CLK: 500MHz (Lane Rate/20) +- JESD204B Lane Rate: 10Gbps +- QPLL0 or CPLL The Tx links (DAC Path) operate with the following parameters: -- Tx Framer parameters: L=4, M=8, F=4, S=1, NP=16, N=16 (Quick Config - 0x09) -- Sample Rate: 250 MSPS -- Dual link: No -- TX_DEVICE_CLK: 250 MHz (Lane Rate/40) -- REF_CLK: 500MHz (Lane Rate/20) -- JESD204B Lane Rate: 10Gbps -- QPLL0 or CPLL +- Tx Framer parameters: L=4, M=8, F=4, S=1, NP=16, N=16 (Quick Config 0x09) +- Sample Rate: 250 MSPS +- Dual link: No +- TX_DEVICE_CLK: 250 MHz (Lane Rate/40) +- REF_CLK: 500MHz (Lane Rate/20) +- JESD204B Lane Rate: 10Gbps +- QPLL0 or CPLL Example block design for Single link; M=4; L=8 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -216,29 +214,28 @@ Example block design for Single link; M=4; L=8 The Rx links are set for full bandwidth mode and operate with the following parameters: -- Rx Deframer parameters: L=8, M=4, F=1, S=1, NP=16, N=16 (Quick - Config 0x12) -- Sample Rate: 1550 MSPS -- Dual link: No -- RX_DEVICE_CLK: 387.5 MHz (Lane Rate/40) -- REF_CLK: 775MHz (Lane Rate/20) -- JESD204B Lane Rate: 15.5Gbps -- QPLL0 +- Rx Deframer parameters: L=8, M=4, F=1, S=1, NP=16, N=16 (Quick Config 0x12) +- Sample Rate: 1550 MSPS +- Dual link: No +- RX_DEVICE_CLK: 387.5 MHz (Lane Rate/40) +- REF_CLK: 775MHz (Lane Rate/20) +- JESD204B Lane Rate: 15.5Gbps +- QPLL0 The Tx links are set for full bandwidth mode and operate with the following parameters: -- Tx Framer parameters: L=8, M=4, F=1, S=1, NP=16, N=16 (Quick Config - 0x11) -- Sample Rate: 1550 MSPS -- Dual link: No -- TX_DEVICE_CLK: 387.5 MHz (Lane Rate/40) -- REF_CLK: 775MHz (Lane Rate/20) -- JESD204B Lane Rate: 15.5Gbps -- QPLL0 +- Tx Framer parameters: L=8, M=4, F=1, S=1, NP=16, N=16 (Quick Config 0x11) +- Sample Rate: 1550 MSPS +- Dual link: No +- TX_DEVICE_CLK: 387.5 MHz (Lane Rate/40) +- REF_CLK: 775MHz (Lane Rate/20) +- JESD204B Lane Rate: 15.5Gbps +- QPLL0 Example block design for Single link; M=2; L=8; JESD204C ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + .. note:: In 2019_R2 release, the AMD JESD Physical layer IP Core is used, @@ -271,25 +268,23 @@ Example block design for Single link; M=2; L=8; JESD204C The Rx link is operating with the following parameters: -- Rx Deframer parameters: L=8, M=2, F=1, S=2, NP=16, N=16 (Quick Config - 0x13) -- Sample Rate: 4000 MSPS -- Dual link: No -- RX_DEVICE_CLK: 250 MHz (Lane Rate/66) -- REF_CLK: 500 MHz (Lane Rate/33) -- JESD204C Lane Rate: 16.5Gbps -- QPLL1 +- Rx Deframer parameters: L=8, M=2, F=1, S=2, NP=16, N=16 (Quick Config 0x13) +- Sample Rate: 4000 MSPS +- Dual link: No +- RX_DEVICE_CLK: 250 MHz (Lane Rate/66) +- REF_CLK: 500 MHz (Lane Rate/33) +- JESD204C Lane Rate: 16.5Gbps +- QPLL1 The Tx link is operating with the following parameters: -- Tx Framer parameters: L=8, M=2, F=1, S=4, NP=8, N=8 (Quick Config - 0x13) -- Sample Rate: 8000 MSPS -- Dual link: No -- TX_DEVICE_CLK: 250 MHz (Lane Rate/66) -- REF_CLK: 500 MHz (Lane Rate/33) -- JESD204C Lane Rate: 16.5Gbps -- QPLL1 +- Tx Framer parameters: L=8, M=2, F=1, S=4, NP=8, N=8 (Quick Config 0x13) +- Sample Rate: 8000 MSPS +- Dual link: No +- TX_DEVICE_CLK: 250 MHz (Lane Rate/66) +- REF_CLK: 500 MHz (Lane Rate/33) +- JESD204C Lane Rate: 16.5Gbps +- QPLL1 Configuration modes ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -312,35 +307,35 @@ for each project. The following are the parameters of this project that can be configured: -- JESD_MODE: used link layer encoder mode - - - 64B66B - 64b66b link layer defined in JESD204C, uses AMD IP as Physical - Layer - - 8B10B - 8b10b link layer defined in JESD204B, uses ADI IP as Physical - Layer - -- RX_LANE_RATE: lane rate of the Rx link (MxFE to FPGA) -- TX_LANE_RATE: lane rate of the Tx link (FPGA to MxFE) -- REF_CLK_RATE: the rate of the reference clock -- DEVICE_CLK_RATE: the rate of the device clock (Intel only) -- [RX/TX]_JESD_M: number of converters per link -- [RX/TX]_JESD_L: number of lanes per link -- [RX/TX]_JESD_S: number of samples per frame -- [RX/TX]_JESD_NP: number of bits per sample -- [RX/TX]_NUM_LINKS: number of links -- [RX/TX]_TPL_WIDTH -- TDD_SUPPORT: set to 1, adds the TDD; enables external synchronization through TDD. Must be set to 1 when SHARED_DEVCLK=1 -- SHARED_DEVCLK -- TDD_CHANNEL_CNT -- TDD_SYNC_WIDTH -- TDD_SYNC_INT -- TDD_SYNC_EXT -- TDD_SYNC_EXT_CDC: if enabled, the CDC circuitry for the external sync signal is added -- [RX/TX]_KS_PER_CHANNEL: Number of samples stored in internal buffers in - kilosamples per converter (M) -- [ADC/DAC]_DO_MEM_TYPE -- Check out this guide on more details regarding these parameters: - :dokuwiki:`resources/fpga/docs/axi_tdd` +- JESD_MODE: used link layer encoder mode + + - 64B66B - 64b66b link layer defined in JESD204C, uses AMD IP as Physical + Layer + - 8B10B - 8b10b link layer defined in JESD204B, uses ADI IP as Physical + Layer +- RX_LANE_RATE: lane rate of the Rx link (MxFE to FPGA) +- TX_LANE_RATE: lane rate of the Tx link (FPGA to MxFE) +- REF_CLK_RATE: the rate of the reference clock +- DEVICE_CLK_RATE: the rate of the device clock (Intel only) +- [RX/TX]_JESD_M: number of converters per link +- [RX/TX]_JESD_L: number of lanes per link +- [RX/TX]_JESD_S: number of samples per frame +- [RX/TX]_JESD_NP: number of bits per sample +- [RX/TX]_NUM_LINKS: number of links +- [RX/TX]_TPL_WIDTH +- TDD_SUPPORT: set to 1, adds the TDD; enables external synchronization + through TDD. Must be set to 1 when SHARED_DEVCLK=1 +- SHARED_DEVCLK +- TDD_CHANNEL_CNT +- TDD_SYNC_WIDTH +- TDD_SYNC_INT +- TDD_SYNC_EXT +- TDD_SYNC_EXT_CDC: if enabled, the CDC circuitry for the external sync signal + is added +- [RX/TX]_KS_PER_CHANNEL: Number of samples stored in internal buffers in + kilosamples per converter (M) +- [ADC/DAC]_DO_MEM_TYPE +- Check out this guide on more details regarding these parameters: :ref:`axi_tdd` Clock scheme ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -370,10 +365,10 @@ Limitations For the parameter selection, the following restrictions apply: - - NP = 8, 12, 16 - - F = 1, 2, 3, 4, 6, 8 - - :ref:`JESD204B/C Link Rx peripheral > restrictions ` - - :ref:`JESD204B/C Link Tx peripheral > restrictions ` + - NP = 8, 12, 16 + - F = 1, 2, 3, 4, 6, 8 + - :ref:`JESD204B/C Link Rx peripheral > restrictions ` + - :ref:`JESD204B/C Link Tx peripheral > restrictions ` CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -565,10 +560,10 @@ for that project (ad9081_fmca_ebz/carrier or ad9082_fmca_ebz/carrier). For the parameter selection, the following restrictions apply: - - NP = 8, 12, 16 - - F = 1, 2, 3, 4, 6, 8 - - :ref:`JESD204B/C Link Rx peripheral > restrictions ` - - :ref:`JESD204B/C Link Tx peripheral > restrictions ` + - NP = 8, 12, 16 + - F = 1, 2, 3, 4, 6, 8 + - :ref:`JESD204B/C Link Rx peripheral > restrictions ` + - :ref:`JESD204B/C Link Tx peripheral > restrictions ` ``NP`` notation is equivalent with ``N'`` @@ -681,7 +676,8 @@ for that project (ad9081_fmca_ebz/carrier or ad9082_fmca_ebz/carrier). | TX_KS_PER_CHANNEL | 64 | 64 | 64 | --- | --- | +-------------------+--------+--------+--------+--------------+--------------+ - .. warning:: + .. admonition:: Legend + :class: note ``*`` --- for this carrier only the 8B10B mode is supported @@ -756,9 +752,9 @@ Resources Systems related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :dokuwiki:`[Wiki] AD9081 & AD9082 & AD9988 & AD9986 Prototyping Platform User Guide ` -- Here you can find all the quick start guides on wiki documentation - :dokuwiki:`[Wiki] AD9081/AD9082/AD9986/AD9988 Quick Start Guides ` +- :dokuwiki:`[Wiki] AD9081 & AD9082 & AD9988 & AD9986 Prototyping Platform User Guide ` +- Here you can find all the quick start guides on wiki documentation + :dokuwiki:`[Wiki] AD9081/AD9082/AD9986/AD9988 Quick Start Guides ` Here you can find the quick start guides available for these evaluation boards: @@ -784,20 +780,20 @@ Here you can find the quick start guides available for these evaluation boards: Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheets: +- Product datasheets: - - :adi:`AD9081` - - :adi:`AD9082` - - :adi:`AD9988` - - :adi:`AD9986` -- `UG-1578, Device User Guide `__ -- `UG-1829, Evaluation Board User Guide `__ + - :adi:`AD9081` + - :adi:`AD9082` + - :adi:`AD9988` + - :adi:`AD9986` +- `UG-1578, Device User Guide `__ +- `UG-1829, Evaluation Board User Guide `__ HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`AD9081_FMCA_EBZ HDL project source code ` -- :git-hdl:`AD9082_FMCA_EBZ HDL project source code ` +- :git-hdl:`AD9081_FMCA_EBZ HDL project source code ` +- :git-hdl:`AD9082_FMCA_EBZ HDL project source code ` .. list-table:: :widths: 30 35 35 @@ -843,17 +839,17 @@ HDL related - :git-hdl:`library/jesd204/ad_ip_jesd204_tpl_dac` - :ref:`here ` -- :dokuwiki:`[Wiki] Generic JESD204B block designs ` -- :ref:`jesd204` +- :dokuwiki:`[Wiki] Generic JESD204B block designs ` +- :ref:`jesd204` Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :dokuwiki:`[Wiki] AD9081-FMCA-EBZ Linux driver wiki page ` -- Python support: +- :dokuwiki:`[Wiki] AD9081-FMCA-EBZ Linux driver wiki page ` +- Python support: - - `AD9081 class documentation `__ - - `PyADI-IIO documentation `__ + - `AD9081 class documentation `__ + - `PyADI-IIO documentation `__ .. include:: ../common/more_information.rst diff --git a/docs/projects/ad9213_evb/index.rst b/docs/projects/ad9213_evb/index.rst index 9ed7325d1c..85c69a6300 100644 --- a/docs/projects/ad9213_evb/index.rst +++ b/docs/projects/ad9213_evb/index.rst @@ -6,7 +6,7 @@ AD9213-EVB HDL project Overview ------------------------------------------------------------------------------- -The :adi:`AD9213-EVB ` reference design is a processor based +The :adi:`AD9213-EVB ` reference design is a processor based (e.g. Microblaze) embedded system. The design implements a high-speed receive chain using JESD204B. @@ -46,6 +46,9 @@ Supported carriers Block design ------------------------------------------------------------------------------- +Block diagram +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + The data path and clock domains are depicted in the below diagrams: .. image:: ad9213_jesd_diagram.svg @@ -53,15 +56,17 @@ The data path and clock domains are depicted in the below diagrams: :align: center :alt: AD9213-EVB JESD204B M=1 L=16 block diagram -The Rx links (ADC Path) operate with the following parameters: +.. important:: -- Rx parameters: L=16, M=1, F=2, S=16, NP=16, N=16 -- Sample Rate: 10 GSPS -- Dual link: No -- RX_DEVICE_CLK: 312.25 MHz (Lane Rate/40) -- REF_CLK: 625 MHz (Lane Rate/20) -- JESD204B Lane Rate: 12.5 Gbps -- QPLL0 + The Rx links (ADC Path) operate with the following parameters: + + - Rx parameters: L=16, M=1, F=2, S=16, NP=16, N=16 + - Sample Rate: 10 GSPS + - Dual link: No + - RX_DEVICE_CLK: 312.25 MHz (Lane Rate/40) + - REF_CLK: 625 MHz (Lane Rate/20) + - JESD204B Lane Rate: 12.5 Gbps + - QPLL0 .. math:: Lane Rate = Sample Rate*\frac{M}{L}*N'* \frac{10}{8} @@ -69,15 +74,10 @@ The Rx links (ADC Path) operate with the following parameters: Clock scheme ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -The clock sources depend on the carrier that is used: - -:xilinx:`VCU118` -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - .. image:: ad9213_clocks.svg :width: 500 :align: center - :alt: AD9213-EVB VCU118 clock scheme + :alt: AD9213-EVB/VCU118 clock scheme CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -152,8 +152,8 @@ Below are the Programmable Logic interrupts used in this project. Instance name IRQ number ================ =========== hmc7044_spi 5 -axi_ad9213_dma 12 -axi_ad9213_jesd 13 +axi_ad9213_dma 12 +axi_ad9213_jesd 13 ================ =========== Building the HDL project @@ -178,10 +178,7 @@ Resources Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheets: - - - :adi:`AD9213` - +- Product datasheet: :adi:`AD9213` - :adi:`Device data sheet ` - :adi:`Evaluation Board ` diff --git a/docs/projects/ad9656_fmc/ad9656_fmc_xilinx_block_diagram.svg b/docs/projects/ad9656_fmc/ad9656_fmc_xilinx_block_diagram.svg index 59e5951131..51602bbd0f 100644 --- a/docs/projects/ad9656_fmc/ad9656_fmc_xilinx_block_diagram.svg +++ b/docs/projects/ad9656_fmc/ad9656_fmc_xilinx_block_diagram.svg @@ -9,7 +9,7 @@ id="svg1" xml:space="preserve" sodipodi:docname="ad9656_fmc_xilinx_block_diagram.svg" - inkscape:version="1.3 (0e150ed6c4, 2023-07-21)" + inkscape:version="1.1.1 (3bf5ae0d25, 2021-09-20)" xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape" xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd" xmlns:xlink="http://www.w3.org/1999/xlink" @@ -25,14 +25,16 @@ inkscape:deskcolor="#d1d1d1" inkscape:document-units="mm" inkscape:zoom="1.1389101" - inkscape:cx="538.23386" - inkscape:cy="412.67522" + inkscape:cx="537.79486" + inkscape:cy="412.23622" inkscape:window-width="1920" - inkscape:window-height="1122" - inkscape:window-x="18" - inkscape:window-y="1357" + inkscape:window-height="1017" + inkscape:window-x="917" + inkscape:window-y="1076" inkscape:window-maximized="1" - inkscape:current-layer="layer1-7" />AD9434 COREAD9656 CORE` +- :adi:`EVAL-AD9656` Supported devices ------------------------------------------------------------------------------- @@ -53,7 +53,7 @@ Supported carriers Block design ------------------------------------------------------------------------------- -ZCU102 block diagram +Block diagram ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ .. image:: ad9656_fmc_xilinx_block_diagram.svg @@ -252,4 +252,4 @@ Software related .. include:: ../common/more_information.rst -.. include:: ../common/support.rst \ No newline at end of file +.. include:: ../common/support.rst diff --git a/docs/projects/ad9739a_fmc/index.rst b/docs/projects/ad9739a_fmc/index.rst index 82a7b61dac..00eb240bc0 100644 --- a/docs/projects/ad9739a_fmc/index.rst +++ b/docs/projects/ad9739a_fmc/index.rst @@ -62,7 +62,7 @@ AD9739A FMC Card block diagram :alt: AD9739A-FMC/ZC706 fmc card block diagram The DDS consists of a Xilinx DDS IP core and a DDR based data generator. The -core generates 6 samples at every fDAC/3 clock cycles for each port of +core generates 6 samples at every fDAC/3 clock cycles for each port of :adi:`AD9739A `. The SPI interface allows programming the :adi:`ADF4350 ` and/or @@ -78,7 +78,7 @@ Two clock paths are available to drive the clock input on the - The factory default option connects the :adi:`ADF4350 ` to the :adi:`AD9739A `. The :adi:`ADF4350 ` is able to - synthesize a clock over the entire specified range of + synthesize a clock over the entire specified range of the :adi:`AD9739A ` (1.6GHz to 2.5GHz) - Jumper CLOCK SOURCE (S1) must be moved to the :adi:`ADF4350 ` @@ -90,7 +90,7 @@ Two clock paths are available to drive the clock input on the position. C102 and C99 on the back of the board also need to be removed from their default position, and then soldered into the vertical position from the large square pad they were previously soldered to and the narrow - pads closer to the :adi:`ADCLK914 ` (U3). Observe the + pads closer to the :adi:`ADCLK914 ` (U3). Observe the orientation of the caps before removing them; they must be soldered with their narrow edge against the PCB, and not the wide side as is common with most components. @@ -207,4 +207,4 @@ Software related .. include:: ../common/more_information.rst -.. include:: ../common/support.rst \ No newline at end of file +.. include:: ../common/support.rst diff --git a/docs/projects/adaq7980_sdz/index.rst b/docs/projects/adaq7980_sdz/index.rst index 6a40d9115f..af302e110a 100644 --- a/docs/projects/adaq7980_sdz/index.rst +++ b/docs/projects/adaq7980_sdz/index.rst @@ -42,18 +42,18 @@ Applications: Supported boards ------------------------------------------------------------------------------- -- :adi:`EVAL-ADAQ7980 ` +- :adi:`EVAL-ADAQ7980` Supported devices ------------------------------------------------------------------------------- -- :adi:`ADAQ7980` -- :adi:`ADAQ7988` +- :adi:`ADAQ7980` +- :adi:`ADAQ7988` Supported carriers ------------------------------------------------------------------------------- -- :xilinx:`ZedBoard ` on FMC slot +- :xilinx:`ZedBoard ` on FMC slot Block design ------------------------------------------------------------------------------- @@ -127,7 +127,7 @@ GPIOs The Software GPIO number is calculated as follows: -- Zynq-7000: if PS7 is used, then offset is 54 +- Zynq-7000: if PS7 is used, then offset is 54 .. list-table:: :widths: 25 25 25 25 @@ -192,14 +192,13 @@ Resources Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheet: :adi:`ADAQ7980`/:adi:`ADAQ7988` - -- `UG-1060, Evaluation Board User Guide `__ +- Product datasheet: :adi:`ADAQ7980`/:adi:`ADAQ7988` +- `UG-1060, Evaluation Board User Guide `__ HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`ADAQ7980_SDZ HDL project source code ` +- :git-hdl:`ADAQ7980_SDZ HDL project source code ` .. list-table:: :widths: 30 35 35 @@ -248,14 +247,12 @@ HDL related - :git-hdl:`library/util_i2c_mixer ` - :ref:`here ` -- :ref:`SPI Engine Framework documentation ` +- :ref:`SPI Engine Framework documentation ` Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-no-os:`ADAQ7980_SDZ No-OS project ` - -- :dokuwiki:`How to build No-OS ` +- :git-no-os:`ADAQ7980_SDZ No-OS project ` .. include:: ../common/more_information.rst diff --git a/docs/projects/adrv9026/index.rst b/docs/projects/adrv9026/index.rst index c018661b9e..064b530e6d 100644 --- a/docs/projects/adrv9026/index.rst +++ b/docs/projects/adrv9026/index.rst @@ -3,19 +3,19 @@ ADRV9026 HDL reference design =============================================================================== -The ADRV9026 is a highly integrated, radio frequency (RF) agile transceiver -offering four independently controlled transmitters, dedicated observation -receiver inputs for monitoring each transmitter channel, four independently -controlled receivers, integrated synthesizers, and digital signal processing -functions providing a complete transceiver solution. The device provides the -performance demanded by cellular infrastructure applications, such as small -cell base station radios, macro 3G/4G/5G systems, and massive multiple +The ADRV9026 is a highly integrated, radio frequency (RF) agile transceiver +offering four independently controlled transmitters, dedicated observation +receiver inputs for monitoring each transmitter channel, four independently +controlled receivers, integrated synthesizers, and digital signal processing +functions providing a complete transceiver solution. The device provides the +performance demanded by cellular infrastructure applications, such as small +cell base station radios, macro 3G/4G/5G systems, and massive multiple in/multiple out (MIMO) base stations. Supported boards ------------------------------------------------------------------------------- -- :adi:`ADRV9026/ADRV9029 ` +- :adi:`ADRV9026/ADRV9029 ` Supported carriers ------------------------------------------------------------------------------- @@ -28,7 +28,7 @@ Supported carriers - Carrier - FMC slot * - :adi:`ADRV9026/ADRV9029 ` - - `A10SoC`_ + - A10SoC`_ - FMCA * - - :xilinx:`ZCU102` @@ -58,23 +58,23 @@ Example block design for Single link; M=8; L=4 The Rx links (ADC Path) operate with the following parameters: -- Rx Deframer parameters: L=4, M=8, F=4, S=1, NP=16, N=16 -- Sample Rate: 250 MSPS -- Dual link: No -- RX_DEVICE_CLK: 250 MHz (Lane Rate/40) -- REF_CLK: 500MHz (Lane Rate/20) -- JESD204B Lane Rate: 10Gbps -- QPLL0 or CPLL +- Rx Deframer parameters: L=4, M=8, F=4, S=1, NP=16, N=16 +- Sample Rate: 250 MSPS +- Dual link: No +- RX_DEVICE_CLK: 250 MHz (Lane Rate/40) +- REF_CLK: 500MHz (Lane Rate/20) +- JESD204B Lane Rate: 10Gbps +- QPLL0 or CPLL The Tx links (DAC Path) operate with the following parameters: -- Tx Framer parameters: L=4, M=8, F=4, S=1, NP=16, N=16 -- Sample Rate: 250 MSPS -- Dual link: No -- TX_DEVICE_CLK: 250 MHz (Lane Rate/40) -- REF_CLK: 500MHz (Lane Rate/20) -- JESD204B Lane Rate: 10Gbps -- QPLL0 or CPLL +- Tx Framer parameters: L=4, M=8, F=4, S=1, NP=16, N=16 +- Sample Rate: 250 MSPS +- Dual link: No +- TX_DEVICE_CLK: 250 MHz (Lane Rate/40) +- REF_CLK: 500MHz (Lane Rate/20) +- JESD204B Lane Rate: 10Gbps +- QPLL0 or CPLL Configuration modes ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -96,17 +96,17 @@ for each project. The following are the parameters of this project that can be configured: -- JESD_MODE: used link layer encoder mode +- JESD_MODE: used link layer encoder mode - - 64B66B - 64b66b link layer defined in JESD204C - - 8B10B - 8b10b link layer defined in JESD204B + - 64B66B - 64b66b link layer defined in JESD204C + - 8B10B - 8b10b link layer defined in JESD204B -- RX_LANE_RATE: lane rate of the Rx link -- TX_LANE_RATE: lane rate of the Tx link -- [RX/TX]_JESD_M: number of converters per link -- [RX/TX]_JESD_L: number of lanes per link -- [RX/TX]_JESD_S: number of samples per frame -- [RX/TX]_NUM_LINKS: number of links +- RX_LANE_RATE: lane rate of the Rx link +- TX_LANE_RATE: lane rate of the Tx link +- [RX/TX]_JESD_M: number of converters per link +- [RX/TX]_JESD_L: number of lanes per link +- [RX/TX]_JESD_S: number of samples per frame +- [RX/TX]_NUM_LINKS: number of links Clock scheme ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -150,8 +150,8 @@ SPI connections - spi0 - ADRV9026 - 0 - * - - - + * - + - - AD9528 - 1 @@ -159,7 +159,8 @@ GPIOs ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ZCU102 -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + .. list-table:: :widths: 25 20 20 15 :header-rows: 2 @@ -250,7 +251,8 @@ ZCU102 - 128:110 VCU118 -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + .. list-table:: :widths: 25 20 20 15 :header-rows: 2 @@ -356,13 +358,14 @@ axi_adrv9026_rx_dma 14 109 141 Microblaze ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + ==================== === ============ Instance name HDL Microblaze ==================== === ============ -axi_adrv9026_tx_jesd 15 15 -axi_adrv9026_rx_jesd 14 14 -axi_adrv9026_tx_dma 13 13 -axi_adrv9026_rx_dma 12 12 +axi_adrv9026_tx_jesd 15 15 +axi_adrv9026_rx_jesd 14 14 +axi_adrv9026_tx_dma 13 13 +axi_adrv9026_rx_dma 12 12 ==================== === ============ Building the HDL project @@ -460,7 +463,7 @@ Resources Systems related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :dokuwiki:`[Wiki] ADRV9026 & ADRV9029 Prototyping Platform User Guide ` +- :dokuwiki:`[Wiki] ADRV9026 & ADRV9029 Prototyping Platform User Guide ` Here you can find the quick start guides available for these evaluation boards: @@ -476,15 +479,13 @@ Here you can find the quick start guides available for these evaluation boards: Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheets: - - - :adi:`ADRV9026` -- `UG-1578, Device User Guide `__ +- Product datasheet: :adi:`ADRV9026` +- `UG-1578, Device User Guide `__ HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`ADRV9026 HDL project source code ` +- :git-hdl:`ADRV9026 HDL project source code ` .. list-table:: :widths: 30 40 35 @@ -530,13 +531,13 @@ HDL related - :git-hdl:`library/jesd204/ad_ip_jesd204_tpl_dac` - :ref:`here ` -- :dokuwiki:`[Wiki] Generic JESD204B block designs ` -- :ref:`jesd204` +- :dokuwiki:`[Wiki] Generic JESD204B block designs ` +- :ref:`jesd204` Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :dokuwiki:`[Wiki] ADRV9026 Linux driver wiki page ` +- :dokuwiki:`[Wiki] ADRV9026 Linux driver wiki page ` .. include:: ../common/more_information.rst diff --git a/docs/projects/adrv904x/index.rst b/docs/projects/adrv904x/index.rst index c49e9791c6..159005d1c7 100644 --- a/docs/projects/adrv904x/index.rst +++ b/docs/projects/adrv904x/index.rst @@ -35,7 +35,7 @@ Supported carriers * - EVAL-ADRV904x - :xilinx:`ZCU102` - FMC HPC0 - * - + * - - :xilinx:`VCK190` - FMCP1 diff --git a/docs/projects/adv7511/index.rst b/docs/projects/adv7511/index.rst index b29b8699a7..8d2c815048 100644 --- a/docs/projects/adv7511/index.rst +++ b/docs/projects/adv7511/index.rst @@ -134,7 +134,7 @@ Below are the Programmable Logic interrupts used in this project. =========================== === ============ ============= Instance name HDL Linux Zynq Actual Zynq =========================== === ============ ============= -axi_hdmi_dma/irq 15 59 91 +axi_hdmi_dma/irq 15 59 91 axi_iic_main/iic2intc_irpt 14 58 90 axi_iic_fmc/iic2intc_irpt* 11 55 87 =========================== === ============ ============= @@ -218,15 +218,15 @@ Software related - :git-linux:`ADV7511 driver source code ` - :git-linux:`ADV7511 - ZED dtsi source code (arm32) ` - + - :git-linux:`ADV7511 - ZED dts source code (arm32) ` - :git-linux:`ADV7511 - ZC706 dtsi source code (arm32) ` - + - :git-linux:`ADV7511 - ZC706 dts source code (arm32) ` - :git-linux:`ADV7511 - ZC702 dtsi source code (arm32) ` - + - :git-linux:`ADV7511 - ZC702 dts source code (arm32) ` - :dokuwiki:`ADV7511 driver docs ` diff --git a/docs/projects/adv7513/index.rst b/docs/projects/adv7513/index.rst index 02a52f0118..a708beecdd 100644 --- a/docs/projects/adv7513/index.rst +++ b/docs/projects/adv7513/index.rst @@ -27,12 +27,12 @@ with exposed pad and is specified over the −25°C to +85°C temperature range. Supported devices ------------------------------------------------------------------------------- -- :adi:`ADV7513` +- :adi:`ADV7513` Supported carriers ------------------------------------------------------------------------------- -- Internal component of :intel:`De10-Nano ` +- Internal component of :intel:`De10-Nano ` Block design ------------------------------------------------------------------------------- @@ -40,7 +40,7 @@ Block design The reference design uses HDL-related HDMI cores in order to interface the :adi:`ADV7513` IC into the De10-Nano evaluation kit. -ADV7513 Block Diagram +Block diagram ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ .. image:: adv7513_bd.svg @@ -52,7 +52,7 @@ CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The addresses are dependent on the architecture of the FPGA, having an offset -added to the base address from HDL(see more at :ref:`architecture`). +added to the base address from HDL (see more at :ref:`architecture cpu-intercon-addr`). ======================== =========== Instance DE10-Nano @@ -97,14 +97,14 @@ Interrupts Below are the Programmable Logic interrupts used in this project. -=========================== === ===== -Instance name HDL Linux =========================== === ===== -sys_gpio_bd/irq 0 40 -sys_spi/irq 1 41 -sys_gpio_in/irq 2 42 -ltc2308_spi/irq 3 43 -video_dmac/interrupt_sender 7 47 +Instance name HDL Linux +=========================== === ===== +sys_gpio_bd/irq 0 40 +sys_spi/irq 1 41 +sys_gpio_in/irq 2 42 +ltc2308_spi/irq 3 43 +video_dmac/interrupt_sender 7 47 =========================== === ===== Building the HDL project @@ -116,18 +116,16 @@ ADI distributes the bit/elf files of these projects as part of the If you want to build the sources, ADI makes them available on the :git-hdl:`HDL repository `. To get the source you must `clone `__ -the HDL repository, and then build the project as follows:. +the HDL repository, and then build the project as follows: **Linux/Cygwin/WSL** -.. code-block:: - :linenos: +.. shell:: - user@analog:~$ cd hdl/projects/adv7513/de10nano - user@analog:~/hdl/projects/adv7513/de10nano$ make + $ cd hdl/projects/adv7513/de10nano + $ make -A more comprehensive build guide can be found in the :ref:`build_hdl` -user guide. +A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. Resources ------------------------------------------------------------------------------- @@ -135,12 +133,12 @@ Resources Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheet: :adi:`ADV7513` +- Product datasheet: :adi:`ADV7513` HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`ADV7513 HDL project source code ` +- :git-hdl:`ADV7513 HDL project source code ` .. list-table:: :widths: 30 35 35 @@ -165,11 +163,9 @@ HDL related Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-linux:`ADV7513 driver source code ` - -- :git-linux:`ADV7513 - DE10-Nano Base dtsi source code (arm32) ` - -- :dokuwiki:`ADV7511 driver docs ` +- :git-linux:`ADV7513 driver source code ` +- :git-linux:`ADV7513 - DE10-Nano Base dtsi source code (arm32) ` +- :dokuwiki:`ADV7511 driver docs ` .. include:: ../common/more_information.rst diff --git a/docs/projects/cn0363/index.rst b/docs/projects/cn0363/index.rst index b5b650fe77..050f184e8e 100644 --- a/docs/projects/cn0363/index.rst +++ b/docs/projects/cn0363/index.rst @@ -226,7 +226,7 @@ HDL related - :ref:`here ` * - AXI_GENERIC_ADC - :git-hdl:`library/axi_generic_adc ` - - --- + - --- * - AXI_HDMI_TX - :git-hdl:`library/axi_hdmi_tx ` - :ref:`here ` @@ -265,7 +265,7 @@ HDL related - :ref:`here ` * - UTIL_AXIS_RESIZE - :git-hdl:`library/util_axis_resize` - - --- + - --- * - UTIL_I2C-MIXER - :git-hdl:`library/util_i2c_mixer ` - --- diff --git a/docs/projects/cn0506/index.rst b/docs/projects/cn0506/index.rst index cacc9d6745..8e9f59b9bb 100644 --- a/docs/projects/cn0506/index.rst +++ b/docs/projects/cn0506/index.rst @@ -185,7 +185,7 @@ The Software GPIO number is calculated as follows: * - link_st_b - IN - 34 - - 88 + - 88 * - int_n_a - IN - 33 @@ -228,7 +228,7 @@ The Software GPIO number is calculated as follows: - 35 * - link_st_b - IN - - 34 + - 34 * - mii_crs_a - IN - 33 @@ -257,7 +257,7 @@ Below are the Programmable Logic interrupts used in this project. =========================== === ============ ============= Instance name HDL Linux Zynq Actual Zynq =========================== === ============ ============= -axi_hdmi_dma/irq* 15 59 91 +axi_hdmi_dma/irq* 15 59 91 axi_iic_main/iic2intc_irpt* 14 58 90 axi_iic_fmc/iic2intc_irpt* 11 55 87 =========================== === ============ ============= @@ -298,7 +298,7 @@ then the folder name will be: ``INTF_CFGMII`` -A more comprehensive build guide can be found in the :ref:`build_hdl` +A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. Resources @@ -308,7 +308,7 @@ Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - Product datasheet: :adi:`CN0506` -- ADIN1300 datasheet: :adi:`ADIN1300` +- ADIN1300 datasheet: :adi:`ADIN1300` HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/projects/cn0561/index.rst b/docs/projects/cn0561/index.rst index 99225a2c09..0f27c9b995 100644 --- a/docs/projects/cn0561/index.rst +++ b/docs/projects/cn0561/index.rst @@ -6,56 +6,56 @@ CN0561 HDL project Overview ------------------------------------------------------------------------------- -The :adi:`AD4134` is a quad channel, low noise, simultaneous sampling, -precision analog-to-digital converter (ADC), based on the continuous time -sigma-delta (CTSD) modulation scheme. This architecture inherently rejects -signals around the ADC aliasing frequency band, giving the device its inherent -antialiasing capability, and removesthe need for a complex external +The :adi:`AD4134` is a quad channel, low noise, simultaneous sampling, +precision analog-to-digital converter (ADC), based on the continuous time +sigma-delta (CTSD) modulation scheme. This architecture inherently rejects +signals around the ADC aliasing frequency band, giving the device its inherent +antialiasing capability, and removesthe need for a complex external antialiasing filter. -This device has four independent converter channels in parallel, each with a -CTSD modulator and a digital decimation and filtering path. It enables -simultaneous sampling of four signal sources, with a maximum input bandwidth +This device has four independent converter channels in parallel, each with a +CTSD modulator and a digital decimation and filtering path. It enables +simultaneous sampling of four signal sources, with a maximum input bandwidth of 391.5 kHz. It supports a wide range of ODR frequencies, from 0.01 kSPS to -1496 kSPS wih less than 0.01 SPS adjustment resolution, allowing the user to +1496 kSPS wih less than 0.01 SPS adjustment resolution, allowing the user to granularly vary sampling speed to achieve coherent sampling. -The :adi:`AD4134` supports two device configuration schemes: serial peripheral -interface (SPI) and hardware pin configuration (pin control mode). -The SPI control mode offers access to all the features and configuration -options available on the chip. Pin control mode offers the benefit of -simplifying the device configuration, enabling the device to operate +The :adi:`AD4134` supports two device configuration schemes: serial peripheral +interface (SPI) and hardware pin configuration (pin control mode). +The SPI control mode offers access to all the features and configuration +options available on the chip. Pin control mode offers the benefit of +simplifying the device configuration, enabling the device to operate autonomously after power-up operating in a standalone mode. -The HDL reference design for the EVAL-CN0561 provides all the interfaces that -are necessary to interact with the device using a Xilinx FPGA development -board; to acquire data from the ADC device, supporting continuous data -capture at maximum 1.5 MSPS data rate. However, due to a hardware limitation, +The HDL reference design for the EVAL-CN0561 provides all the interfaces that +are necessary to interact with the device using a Xilinx FPGA development +board; to acquire data from the ADC device, supporting continuous data +capture at maximum 1.5 MSPS data rate. However, due to a hardware limitation, the Cora-Z7s variant will only support a maximum data clock of 24MHz, in contrast with 50MHz supported on the Zedboard. Supported boards ------------------------------------------------------------------------------- -- :adi:`EVAL-CN0561 ` +- :adi:`EVAL-CN0561 ` Supported devices ------------------------------------------------------------------------------- -- :adi:`AD4134` +- :adi:`AD4134` Supported carriers ------------------------------------------------------------------------------- -- :xilinx:`ZedBoard ` on FMC slot -- `Cora Z7-07S `_ on Arduino type headers -- `DE10-Nano `__ on Arduino type headers +- :xilinx:`ZedBoard ` on FMC slot +- `Cora Z7-07S `_ on Arduino type headers +- `DE10-Nano `__ on Arduino type headers Block design ------------------------------------------------------------------------------- -The reference design uses the SPI Engine Framework to interface with -the AD4134 ADC and only supports the slave mode with both DCLK and ODR +The reference design uses the SPI Engine Framework to interface with +the AD4134 ADC and only supports the slave mode with both DCLK and ODR generated by the FPGA. The device sends data on the 4 DIN bits. Block diagram @@ -71,7 +71,7 @@ The data path and clock domains are depicted in the below diagrams: .. admonition:: Legend :class: note - ``*`` The block design for Cora Z7-07S remains the same, the only + ``*`` The block design for Cora Z7-07S remains the same, the only difference is the data clock frequency of 24MHz. Jumper setup @@ -138,7 +138,7 @@ GPIOs The Software GPIO number is calculated as follows: -- Zynq-7000: if PS7 is used, then offset is 54 +- Zynq-7000: if PS7 is used, then offset is 54 .. list-table:: :widths: 25 25 25 25 @@ -176,7 +176,7 @@ The Software GPIO number is calculated as follows: - INOUT - 32 - 86 - + Interrupts ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -203,12 +203,11 @@ the HDL repository, and then build the project as follows:. **Linux/Cygwin/WSL** .. code-block:: - :linenos: user@analog:~$ cd hdl/projects/cn0561/zed user@analog:~/hdl/projects/cn0561/zed$ make -A more comprehensive build guide can be found in the :ref:`build_hdl` +A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. Resources @@ -217,12 +216,12 @@ Resources Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheet: :adi:`AD4134` +- Product datasheet: :adi:`AD4134` HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`CN0561 HDL project source code ` +- :git-hdl:`CN0561 HDL project source code ` .. list-table:: :widths: 30 35 35 @@ -274,21 +273,17 @@ HDL related .. admonition:: Legend :class: note - - ``*`` instantiated only for Zed carrier - - ``**`` instantiated only for Zed and De10Nano carriers + - ``*`` instantiated only for Zed carrier + - ``**`` instantiated only for Zed and DE10-Nano carriers -- :ref:`SPI Engine Framework documentation ` +- :ref:`SPI Engine Framework documentation ` Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-no-os:`CN0561 No-OS project source code ` - -- :git-no-os:`AD4134/AD7134 No-OS Driver source code ` - -- :dokuwiki:`AD4134/AD7134 No-OS Driver documentation ` - -- :dokuwiki:`How to build No-OS ` +- :git-no-os:`CN0561 No-OS project source code ` +- :git-no-os:`AD4134/AD7134 No-OS Driver source code ` +- :dokuwiki:`AD4134/AD7134 No-OS Driver documentation ` .. include:: ../common/more_information.rst diff --git a/docs/projects/cn0577/index.rst b/docs/projects/cn0577/index.rst index c65a23c979..705f12e3b9 100644 --- a/docs/projects/cn0577/index.rst +++ b/docs/projects/cn0577/index.rst @@ -72,7 +72,7 @@ one-bit-adc-dac, in software. - Shorting pins 1 and 2 → PD_N = 1, device is not powered down - Shorting pins 2 and 3 → PD_N = 0, device is powered down - + - P2 - configures TESTPAT - Shorting pins 1 and 2 → TESTPAT = 1, pattern testing is active diff --git a/docs/projects/cn0579/index.rst b/docs/projects/cn0579/index.rst index 5092dc7593..f761b4b6e2 100644 --- a/docs/projects/cn0579/index.rst +++ b/docs/projects/cn0579/index.rst @@ -52,6 +52,9 @@ Supported carriers Block design ------------------------------------------------------------------------------- +Block diagram +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + The data path and clock domains are depicted in the below diagram: .. image:: cn0579_block_diagram.svg diff --git a/docs/projects/max96724/index.rst b/docs/projects/max96724/index.rst index de83350aab..8358800c5d 100644 --- a/docs/projects/max96724/index.rst +++ b/docs/projects/max96724/index.rst @@ -150,12 +150,12 @@ Below are the Programmable Logic interrupts used in this project. ====================== === ============ ============= Instance name HDL Linux ZynqMP Actual ZynqMP ====================== === ============ ============= -csirxss_irq 13 109 141 -iic2intc_irpt 12 108 140 -v_frmbuf_wr0/interrupt 11 107 139 -v_frmbuf_wr1/interrupt 10 106 138 -v_frmbuf_wr2/interrupt 9 105 137 -v_frmbuf_wr3/interrupt 8 104 136 +csirxss_irq 13 109 141 +iic2intc_irpt 12 108 140 +v_frmbuf_wr0/interrupt 11 107 139 +v_frmbuf_wr1/interrupt 10 106 138 +v_frmbuf_wr2/interrupt 9 105 137 +v_frmbuf_wr3/interrupt 8 104 136 ====================== === ============ ============= Building the HDL project diff --git a/docs/projects/pulsar_lvds/index.rst b/docs/projects/pulsar_lvds/index.rst index a176c75e66..b672f1a796 100644 --- a/docs/projects/pulsar_lvds/index.rst +++ b/docs/projects/pulsar_lvds/index.rst @@ -9,9 +9,9 @@ Overview The :adi:`AD7625`, :adi:`AD7626`, :adi:`AD7960`, :adi:`AD7961` devices are parts from ADC LVDS PulSAR family. The :adi:`AD7625` / :adi:`AD7626` is a 16-bit, 6 MSPS / 10 MSPS, charge -redistribution successive approximation register (SAR) architecture, +redistribution successive approximation register (SAR) architecture, analog to-digital converter (ADC). SAR architecture allows unmatched performance -both in noise (92dB SNR) and in linearity (±1 LSB INL / ±0.45 LSB INL). The +both in noise (92dB SNR) and in linearity (±1 LSB INL / ±0.45 LSB INL). The AD7626 contains a high speed 16-bit sampling ADC, an internal conversion clock, and an internal buffered reference. On the CNV edge, it samples the voltage difference between IN+ and IN- pins. The voltages on these pins swing in opposite @@ -19,7 +19,7 @@ phase between 0 V and REF. The 4.096V reference voltage, REF, can be generated internally or applied externally. All converted results are available on a single LVDS self-clocked or -echoed-clock serial interface reducing external hardware connections. The +echoed-clock serial interface reducing external hardware connections. The :adi:`AD7625` / :adi:`AD7626` is available in a 32-lead LFCSP (5mm by 5mm) with operation specified from -40°C to +85°C. @@ -115,7 +115,7 @@ Jumper/Solder link Default Position Description ================== ================= =========================================== LK2 Inserted Connects REFIN to the 1.2V external reference. -LK3 Inserted Connects the 4.096 V output from the +LK3 Inserted Connects the 4.096 V output from the :adi:`ADR4540` after buffer :adi:`AD8031` solution. LK6 B Connects the output of the VCM buffer to @@ -142,11 +142,11 @@ Jumper/Solder link Default Position Description LK2,LK3 Inserted Option to use external amplifier supplies + VS and – VS. LK4 Inserted Connects to +7 V coming from :adi:`ADP7102`. -LK5 B Connects to −2.5 V coming from +LK5 B Connects to −2.5 V coming from :adi:`ADP2300`. LK6 B Connects the output of VCM buffer to VCM of amplifier. -LK7 B Connects the +5 V output from +LK7 B Connects the +5 V output from :adi:`ADR4550` to REF buffer AD8031. JP1,JP2 B Connects analog inputs VIN+ and VIN− to the inputs of the ADC driver. From 7ed156ee32fd522dd17bfdc9a5bd6e9923eae76d Mon Sep 17 00:00:00 2001 From: Iulia Moldovan Date: Fri, 1 Nov 2024 09:50:13 +0200 Subject: [PATCH 08/10] docs/projects: Update references to IP doc. * ad4170_asdz: Fix typo in IP link * ad469x_fmc: Fix typo in IP link * ad5766_sdz: Fix typo in IP link * ad738x_fmc: Fix typo in IP link Signed-off-by: Iulia Moldovan --- docs/projects/ad3552r_evb/index.rst | 12 ++--- docs/projects/ad408x_fmc_evb/index.rst | 19 ++++--- docs/projects/ad4110/index.rst | 10 ++-- docs/projects/ad411x_ad717x/index.rst | 36 ++++++------- docs/projects/ad4134_fmc/index.rst | 20 +++---- docs/projects/ad4170_asdz/index.rst | 34 ++++++------ docs/projects/ad4630_fmc/index.rst | 20 +++---- docs/projects/ad469x_evb/index.rst | 2 +- docs/projects/ad485x_fmcz/index.rst | 28 +++++----- docs/projects/ad5758_sdz/index.rst | 10 ++-- docs/projects/ad5766_sdz/index.rst | 40 +++++++------- docs/projects/ad57xx_ardz/index.rst | 38 ++++++------- docs/projects/ad7134_fmc/index.rst | 20 +++---- docs/projects/ad738x_fmc/index.rst | 46 ++++++++-------- docs/projects/ad7606x_fmc/index.rst | 54 +++++++++---------- docs/projects/ad7616_sdz/index.rst | 22 ++++---- docs/projects/ad77681evb/index.rst | 40 +++++++------- docs/projects/ad7768evb/index.rst | 32 +++++------ docs/projects/ad777x_ardz/index.rst | 14 ++--- docs/projects/ad9081_fmca_ebz/index.rst | 24 ++++----- .../projects/ad9081_fmca_ebz_x_band/index.rst | 51 +++++++++--------- docs/projects/ad9213_evb/index.rst | 14 ++--- docs/projects/ad9265_fmc/index.rst | 32 +++++------ docs/projects/ad9434_fmc/index.rst | 24 ++++----- docs/projects/ad9467_fmc/index.rst | 12 ++--- docs/projects/ad9656_fmc/index.rst | 18 +++---- docs/projects/ad9695_fmc/index.rst | 2 +- docs/projects/ad9739a_fmc/index.rst | 10 ++-- docs/projects/ad9783_ebz/index.rst | 10 ++-- docs/projects/ad_gmsl2eth_sl/index.rst | 20 +++---- docs/projects/adaq7980_sdz/index.rst | 48 ++++++++--------- docs/projects/adaq8092_fmc/index.rst | 14 ++--- docs/projects/adrv9026/index.rst | 24 ++++----- docs/projects/adrv904x/index.rst | 26 ++++----- docs/projects/adv7511/index.rst | 12 ++--- docs/projects/adv7513/index.rst | 14 ++--- docs/projects/cn0363/index.rst | 50 ++++++++--------- docs/projects/cn0506/index.rst | 14 ++--- docs/projects/cn0540/index.rst | 34 ++++++------ docs/projects/cn0561/index.rst | 20 +++---- docs/projects/cn0577/index.rst | 14 ++--- docs/projects/cn0579/index.rst | 10 ++-- docs/projects/cn0585/index.rst | 18 +++---- docs/projects/max96724/index.rst | 4 +- docs/projects/pulsar_adc/index.rst | 42 +++++++-------- docs/projects/pulsar_lvds/index.rst | 30 +++++------ docs/projects/template/index.rst | 16 +++--- 47 files changed, 552 insertions(+), 552 deletions(-) diff --git a/docs/projects/ad3552r_evb/index.rst b/docs/projects/ad3552r_evb/index.rst index c5be441ba7..8bfb40edf7 100644 --- a/docs/projects/ad3552r_evb/index.rst +++ b/docs/projects/ad3552r_evb/index.rst @@ -189,16 +189,16 @@ HDL related * - AXI_AD3552R - :git-hdl:`library/axi_ad3552r` - - :ref:`here ` + - :ref:`axi_ad3552r` * - AXI_CLKGEN - :git-hdl:`library/axi_clkgen` - - :ref:`here ` + - :ref:`axi_clkgen` * - AXI_DMAC - :git-hdl:`library/axi_dmac` - - :ref:`here ` + - :ref:`axi_dmac` * - AXI_HDMI_TX - :git-hdl:`library/axi_hdmi_tx` - - :ref:`here ` + - :ref:`axi_hdmi_tx` * - AXI_I2S_ADI - :git-hdl:`library/axi_i2s_adi` - — @@ -207,10 +207,10 @@ HDL related - — * - AXI_SYSID - :git-hdl:`library/axi_sysid` - - :ref:`here ` + - :ref:`axi_sysid` * - SYSID_ROM - :git-hdl:`library/sysid_rom` - - :ref:`here ` + - :ref:`axi_sysid` * - UTIL_I2C_MIXER - :git-hdl:`library/util_i2c_mixer` - — diff --git a/docs/projects/ad408x_fmc_evb/index.rst b/docs/projects/ad408x_fmc_evb/index.rst index a03103bffd..36dfcfa5bd 100644 --- a/docs/projects/ad408x_fmc_evb/index.rst +++ b/docs/projects/ad408x_fmc_evb/index.rst @@ -222,28 +222,31 @@ HDL related - Documentation link * - AXI_AD408X - :git-hdl:`library/axi_ad408x` - - :ref:`here ` + - :ref:`axi_ad408x` + * - AXI_CLOCK_MONITOR + - :git-hdl:`library/axi_clock_monitor` + - :ref:`axi_clock_monitor` * - AXI_CLKGEN - :git-hdl:`library/axi_clkgen` - - :ref:`here ` + - :ref:`axi_clkgen` * - AXI_DMAC - :git-hdl:`library/axi_dmac` - - :ref:`here ` + - :ref:`axi_dmac` * - AXI_HDMI_TX - :git-hdl:`library/axi_hdmi_tx` - - :ref:`here ` + - :ref:`axi_hdmi_tx` * - AXI_I2S_ADI - :git-hdl:`library/axi_i2s_adi` - - — + - --- * - AXI_SPDIF_TX - :git-hdl:`library/axi_spdif_tx` - - — + - --- * - SYSID_ROM - :git-hdl:`library/sysid_rom` - - :ref:`here ` + - :ref:`axi_sysid` * - UTIL_I2C_MIXER - :git-hdl:`library/util_i2c_mixer` - - — + - --- Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/projects/ad4110/index.rst b/docs/projects/ad4110/index.rst index 153cc97367..63e5c2b1a3 100644 --- a/docs/projects/ad4110/index.rst +++ b/docs/projects/ad4110/index.rst @@ -174,13 +174,13 @@ HDL related - Documentation link * - AXI_CLKGEN - :git-hdl:`library/axi_clkgen` - - :ref:`here ` + - :ref:`axi_clkgen` * - AXI_DMAC - :git-hdl:`library/axi_dmac` - - :ref:`here ` + - :ref:`axi_dmac` * - AXI_HDMI_TX - :git-hdl:`library/axi_hdmi_tx` - - :ref:`here ` + - :ref:`axi_hdmi_tx` * - AXI_I2S_ADI - :git-hdl:`library/axi_i2s_adi` - --- @@ -189,10 +189,10 @@ HDL related - --- * - AXI_SYSID - :git-hdl:`library/axi_sysid` - - :ref:`here ` + - :ref:`axi_sysid` * - AXI_SYSID_ROM - :git-hdl:`library/sysid_rom` - - :ref:`here ` + - :ref:`axi_sysid` * - UTIL_I2C_MIXER - :git-hdl:`library/util_i2c_mixer` - --- diff --git a/docs/projects/ad411x_ad717x/index.rst b/docs/projects/ad411x_ad717x/index.rst index adc70963a8..39adfe1af5 100644 --- a/docs/projects/ad411x_ad717x/index.rst +++ b/docs/projects/ad411x_ad717x/index.rst @@ -236,35 +236,35 @@ HDL related - Source code link - Documentation link * - AXI_DMAC - - :git-hdl:`library/axi_dmac ` - - :ref:`here ` + - :git-hdl:`library/axi_dmac` + - :ref:`axi_dmac` * - AXI_HDMI_TX - - :git-hdl:`library/axi_hdmi_tx ` - - :ref:`here ` + - :git-hdl:`library/axi_hdmi_tx` + - :ref:`axi_hdmi_tx` * - AXI_PWM_GEN - :git-hdl:`library/axi_pwm_gen` - - :dokuwiki:`[Wiki] ` + - :ref:`axi_pwm_gen` * - AXI_SYSID - - :git-hdl:`library/axi_sysid ` - - :ref:`here ` + - :git-hdl:`library/axi_sysid` + - :ref:`axi_sysid` * - AXI_SPI_ENGINE - - :git-hdl:`library/spi_engine/axi_spi_engine ` - - :ref:`here ` + - :git-hdl:`library/spi_engine/axi_spi_engine` + - :ref:`spi_engine axi` * - SPI_ENGINE_EXECUTION - - :git-hdl:`library/spi_engine/spi_engine_execution ` - - :ref:`here ` + - :git-hdl:`library/spi_engine/spi_engine_execution` + - :ref:`spi_engine execution` * - SPI_ENGINE_INTERCONNECT - - :git-hdl:`library/spi_engine/spi_engine_interconnect ` - - :ref:`here ` + - :git-hdl:`library/spi_engine/spi_engine_interconnect` + - :ref:`spi_engine interconnect` * - SPI_ENGINE_OFFLOAD - :git-hdl:`library/spi_engine/spi_engine_offload` - - :ref:`here ` + - :ref:`spi_engine offload` * - SYSID_ROM - - :git-hdl:`library/sysid_rom ` - - :ref:`here ` + - :git-hdl:`library/sysid_rom` + - :ref:`axi_sysid` * - UTIL_SIGMA_DELTA_SPI - - :git-hdl:`library/util_sigma_delta_spi ` - - :dokuwiki:`[Wiki] ` + - :git-hdl:`library/util_sigma_delta_spi` + - :ref:`util_sigma_delta_spi` - :ref:`SPI Engine Framework documentation ` diff --git a/docs/projects/ad4134_fmc/index.rst b/docs/projects/ad4134_fmc/index.rst index 73503a724c..57a41c9bbb 100644 --- a/docs/projects/ad4134_fmc/index.rst +++ b/docs/projects/ad4134_fmc/index.rst @@ -209,40 +209,40 @@ HDL related - Documentation link * - AXI_CLKGEN - :git-hdl:`library/axi_clkgen` - - :ref:`here ` + - :ref:`axi_clkgen` * - AXI_DMAC - :git-hdl:`library/axi_dmac` - - :ref:`here ` + - :ref:`axi_dmac` * - AXI_HDMI_TX - :git-hdl:`library/axi_hdmi_tx` - - :ref:`here ` + - :ref:`axi_hdmi_tx` * - AXI_I2S_ADI - :git-hdl:`library/axi_i2s_adi` - --- * - AXI_PWM_GEN - :git-hdl:`library/axi_pwm_gen` - - :ref:`here ` + - :ref:`axi_pwm_gen` * - AXI_SPDIF_TX - :git-hdl:`library/axi_spdif_tx` - --- * - AXI_SYSID - :git-hdl:`library/axi_sysid` - - :ref:`here ` + - :ref:`axi_sysid` * - AXI_SPI_ENGINE - :git-hdl:`library/spi_engine/axi_spi_engine` - - :ref:`here ` + - :ref:`spi_engine axi` * - SPI_ENGINE_EXECUTION - :git-hdl:`library/spi_engine/spi_engine_execution` - - :ref:`here ` + - :ref:`spi_engine execution` * - SPI_ENGINE_INTERCONNECT - :git-hdl:`library/spi_engine/spi_engine_interconnect` - - :ref:`here ` + - :ref:`spi_engine interconnect` * - SPI_ENGINE_OFFLOAD - :git-hdl:`library/spi_engine/spi_engine_offload` - - :ref:`here ` + - :ref:`spi_engine offload` * - AXI_SYSID_ROM - :git-hdl:`library/sysid_rom` - - :ref:`here ` + - :ref:`axi_sysid` * - UTIL_I2C_MIXER - :git-hdl:`library/util_i2c_mixer` - --- diff --git a/docs/projects/ad4170_asdz/index.rst b/docs/projects/ad4170_asdz/index.rst index 315db411b2..1f3bdb5a1b 100644 --- a/docs/projects/ad4170_asdz/index.rst +++ b/docs/projects/ad4170_asdz/index.rst @@ -243,32 +243,32 @@ HDL related - Source code link - Documentation link * - AXI_CLKGEN - - :git-hdl:`library/axi_dmac ` * - - :ref:`here ` + - :git-hdl:`library/axi_clkgen` * + - :ref:`axi_clkgen` * - AXI_DMAC - - :git-hdl:`library/axi_dmac ` - - :ref:`here ` + - :git-hdl:`library/axi_dmac` + - :ref:`axi_dmac` * - AXI_HDMI_TX - - :git-hdl:`library/axi_hdmi_tx ` ** - - :ref:`here ` + - :git-hdl:`library/axi_hdmi_tx` ** + - :ref:`axi_hdmi_tx` * - AXI_SYSID - - :git-hdl:`library/axi_sysid ` - - :ref:`here ` + - :git-hdl:`library/axi_sysid` + - :ref:`axi_sysid` * - AXI_SPI_ENGINE - - :git-hdl:`library/spi_engine/axi_spi_engine ` - - :ref:`here ` + - :git-hdl:`library/spi_engine/axi_spi_engine` + - :ref:`spi_engine axi` * - SPI_ENGINE_EXECUTION - - :git-hdl:`library/spi_engine/spi_engine_execution ` - - :ref:`here ` + - :git-hdl:`library/spi_engine/spi_engine_execution` + - :ref:`spi_engine execution` * - SPI_ENGINE_INTERCONNECT - - :git-hdl:`library/spi_engine/spi_engine_interconnect ` - - :ref:`here ` + - :git-hdl:`library/spi_engine/spi_engine_interconnect` + - :ref:`spi_engine interconnect` * - SPI_ENGINE_OFFLOAD - :git-hdl:`library/spi_engine/spi_engine_offload` - - :ref:`here ` + - :ref:`spi_engine offload` * - SYSID_ROM - - :git-hdl:`library/sysid_rom ` - - :ref:`here ` + - :git-hdl:`library/sysid_rom` + - :ref:`axi_sysid` .. admonition:: Legend :class: note diff --git a/docs/projects/ad4630_fmc/index.rst b/docs/projects/ad4630_fmc/index.rst index a9bff6a06a..4b7a28aad7 100644 --- a/docs/projects/ad4630_fmc/index.rst +++ b/docs/projects/ad4630_fmc/index.rst @@ -387,42 +387,42 @@ HDL related - --- * - AXI_CLKGEN - :git-hdl:`library/axi_clkgen` - - :ref:`here ` + - :ref:`axi_clkgen` * - AXI_DMAC - :git-hdl:`library/axi_dmac` - - :ref:`here ` + - :ref:`axi_dmac` * - AXI_HDMI_TX - :git-hdl:`library/axi_hdmi_tx` - - :ref:`here ` + - :ref:`axi_hdmi_tx` * - AXI_I2S_ADI - :git-hdl:`library/axi_i2s_adi` - --- * - AXI_PWM_GEN - :git-hdl:`library/axi_pwm_gen` - - :ref:`here ` + - :ref:`axi_pwm_gen` * - AXI_SPDIF_TX - :git-hdl:`library/axi_spdif_tx` - --- * - AXI_SPI_ENGINE - :git-hdl:`library/spi_engine/axi_spi_engine` - - :ref:`here ` + - :ref:`spi_engine axi` * - SPI_AXIS_REORDER - :git-hdl:`library/spi_engine/spi_axis_reorder` - --- * - SPI_ENGINE_EXECUTION - :git-hdl:`library/spi_engine/spi_engine_execution` - - :ref:`here ` + - :ref:`spi_engine execution` * - SPI_ENGINE_INTERCONNECT - :git-hdl:`library/spi_engine/spi_engine_interconnect` - - :ref:`here ` + - :ref:`spi_engine interconnect` * - SPI_ENGINE_OFFLOAD - :git-hdl:`library/spi_engine/spi_engine_offload` - - :ref:`here ` + - :ref:`spi_engine offload` * - SYSID_ROM - :git-hdl:`library/sysid_rom` - - :ref:`here ` + - :ref:`axi_sysid` * - UTIL_I2C_MIXER - - :git-hdl:`library/util_i2c_mixer ` + - :git-hdl:`library/util_i2c_mixer` - --- - :ref:`SPI Engine Framework documentation ` diff --git a/docs/projects/ad469x_evb/index.rst b/docs/projects/ad469x_evb/index.rst index 407ef5e847..913178355d 100644 --- a/docs/projects/ad469x_evb/index.rst +++ b/docs/projects/ad469x_evb/index.rst @@ -326,7 +326,7 @@ HDL related - Source code link - Documentation link * - AXI_CLKGEN - - :git-hdl:`library/axi_dmac` + - :git-hdl:`library/axi_clkgen` - :ref:`axi_clkgen` * - AXI_DMAC - :git-hdl:`library/axi_dmac` diff --git a/docs/projects/ad485x_fmcz/index.rst b/docs/projects/ad485x_fmcz/index.rst index d8b8d8b0a7..cfda3568f3 100644 --- a/docs/projects/ad485x_fmcz/index.rst +++ b/docs/projects/ad485x_fmcz/index.rst @@ -217,29 +217,29 @@ HDL related - Source code link - Documentation link * - AXI_AD485x - - :git-hdl:`library/axi_ad485x ` + - :git-hdl:`library/axi_ad485x` - --- * - AXI_DMAC - - :git-hdl:`library/axi_dmac ` - - :ref:`here ` + - :git-hdl:`library/axi_dmac` + - :ref:`axi_dmac` * - AXI_CLKGEN - - :git-hdl:`library/axi_clkgen ` - - :ref:`here ` + - :git-hdl:`library/axi_clkgen` + - :ref:`axi_clkgen` * - AXI_PWM_GEN - - :git-hdl:`library/axi_pwm_gen ` - - :ref:`here ` + - :git-hdl:`library/axi_pwm_gen` + - :ref:`axi_pwm_gen` * - AXI_HDMI_TX - - :git-hdl:`library/axi_hdmi_tx ` - - :ref:`here ` + - :git-hdl:`library/axi_hdmi_tx` + - :ref:`axi_hdmi_tx` * - AXI_SPDIF_TX - - :git-hdl:`library/axi_spdif_tx ` + - :git-hdl:`library/axi_spdif_tx` - --- * - AXI_SYSID - - :git-hdl:`library/axi_sysid ` - - :ref:`here ` + - :git-hdl:`library/axi_sysid` + - :ref:`axi_sysid` * - SYSID_ROM - - :git-hdl:`library/sysid_rom ` - - :ref:`here ` + - :git-hdl:`library/sysid_rom` + - :ref:`axi_sysid` Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/projects/ad5758_sdz/index.rst b/docs/projects/ad5758_sdz/index.rst index 812313b317..c2f885c53b 100644 --- a/docs/projects/ad5758_sdz/index.rst +++ b/docs/projects/ad5758_sdz/index.rst @@ -178,13 +178,13 @@ HDL related - Documentation link * - AXI_CLKGEN - :git-hdl:`library/axi_clkgen` - - :ref:`here ` + - :ref:`axi_clkgen` * - AXI_DMAC - :git-hdl:`library/axi_dmac` - - :ref:`here ` + - :ref:`axi_dmac` * - AXI_HDMI_TX - :git-hdl:`library/axi_hdmi_tx` - - :ref:`here ` + - :ref:`axi_hdmi_tx` * - AXI_I2S_ADI - :git-hdl:`library/axi_i2s_adi` - --- @@ -193,10 +193,10 @@ HDL related - --- * - AXI_SYSID - :git-hdl:`library/axi_sysid` - - :ref:`here ` + - :ref:`axi_sysid` * - AXI_SYSID_ROM - :git-hdl:`library/sysid_rom` - - :ref:`here ` + - :ref:`axi_sysid` * - UTIL_I2C_MIXER - :git-hdl:`library/util_i2c_mixer` - --- diff --git a/docs/projects/ad5766_sdz/index.rst b/docs/projects/ad5766_sdz/index.rst index 2b10e71583..3f4eeb6909 100644 --- a/docs/projects/ad5766_sdz/index.rst +++ b/docs/projects/ad5766_sdz/index.rst @@ -225,40 +225,40 @@ HDL related - Source code link - Documentation link * - AXI_AD5766 - - :git-hdl:`library/axi_ad5766 ` + - :git-hdl:`library/axi_ad5766` - --- * - AXI_CLKGEN - - :git-hdl:`library/axi_dmac ` - - :ref:`here ` + - :git-hdl:`library/axi_clkgen` + - :ref:`axi_clkgen` * - AXI_DMAC - - :git-hdl:`library/axi_dmac ` - - :ref:`here ` + - :git-hdl:`library/axi_dmac` + - :ref:`axi_dmac` * - AXI_HDMI_TX - - :git-hdl:`library/axi_hdmi_tx ` - - :ref:`here ` + - :git-hdl:`library/axi_hdmi_tx` + - :ref:`axi_hdmi_tx` * - AXI_I2S_ADI - - :git-hdl:`library/axi_i2s_adi ` + - :git-hdl:`library/axi_i2s_adi` - --- * - AXI_SPDIF_TX - - :git-hdl:`library/axi_spdif_tx ` + - :git-hdl:`library/axi_spdif_tx` - --- * - AXI_SYSID - - :git-hdl:`library/axi_sysid ` - - :ref:`here ` + - :git-hdl:`library/axi_sysid` + - :ref:`axi_sysid` * - AXI_SPI_ENGINE - - :git-hdl:`library/spi_engine/axi_spi_engine ` - - :ref:`here ` + - :git-hdl:`library/spi_engine/axi_spi_engine` + - :ref:`spi_engine axi` * - SPI_ENGINE_EXECUTION - - :git-hdl:`library/spi_engine/spi_engine_execution ` - - :ref:`here ` + - :git-hdl:`library/spi_engine/spi_engine_execution` + - :ref:`spi_engine execution` * - SPI_ENGINE_INTERCONNECT - - :git-hdl:`library/spi_engine/spi_engine_interconnect ` - - :ref:`here ` + - :git-hdl:`library/spi_engine/spi_engine_interconnect` + - :ref:`spi_engine interconnect` * - SYSID_ROM - - :git-hdl:`library/sysid_rom ` - - :ref:`here ` + - :git-hdl:`library/sysid_rom` + - :ref:`axi_sysid` * - UTIL_I2C-MIXER - - :git-hdl:`library/util_i2c_mixer ` + - :git-hdl:`library/util_i2c_mixer` - --- - :ref:`SPI Engine Framework documentation ` diff --git a/docs/projects/ad57xx_ardz/index.rst b/docs/projects/ad57xx_ardz/index.rst index 81a112b636..64a8805cc8 100644 --- a/docs/projects/ad57xx_ardz/index.rst +++ b/docs/projects/ad57xx_ardz/index.rst @@ -277,35 +277,35 @@ HDL related - Source code link - Documentation link * - AXI_CLKGEN - - :git-hdl:`library/axi_dmac ` * - - :ref:`here ` + - :git-hdl:`library/axi_clkgen` * + - :ref:`axi_clkgen` * - AXI_DMAC - - :git-hdl:`library/axi_dmac ` - - :ref:`here ` + - :git-hdl:`library/axi_dmac` + - :ref:`axi_dmac` * - AXI_HDMI_TX - - :git-hdl:`library/axi_hdmi_tx ` ** - - :ref:`here ` + - :git-hdl:`library/axi_hdmi_tx` ** + - :ref:`axi_hdmi_tx` * - AXI_PWM_GEN - - :git-hdl:`library/axi_pwm_gen ` - - :ref:`here ` + - :git-hdl:`library/axi_pwm_gen` + - :ref:`axi_pwm_gen` * - AXI_SYSID - - :git-hdl:`library/axi_sysid ` - - :ref:`here ` + - :git-hdl:`library/axi_sysid` + - :ref:`axi_sysid` * - AXI_SPI_ENGINE - - :git-hdl:`library/spi_engine/axi_spi_engine ` - - :ref:`here ` + - :git-hdl:`library/spi_engine/axi_spi_engine` + - :ref:`spi_engine axi` * - SPI_ENGINE_EXECUTION - - :git-hdl:`library/spi_engine/spi_engine_execution ` - - :ref:`here ` + - :git-hdl:`library/spi_engine/spi_engine_execution` + - :ref:`spi_engine execution` * - SPI_ENGINE_INTERCONNECT - - :git-hdl:`library/spi_engine/spi_engine_interconnect ` - - :ref:`here ` + - :git-hdl:`library/spi_engine/spi_engine_interconnect` + - :ref:`spi_engine interconnect` * - SPI_ENGINE_OFFLOAD - :git-hdl:`library/spi_engine/spi_engine_offload` - - :ref:`here ` + - :ref:`spi_engine offload` * - SYSID_ROM - - :git-hdl:`library/sysid_rom ` - - :ref:`here ` + - :git-hdl:`library/sysid_rom` + - :ref:`axi_sysid` .. admonition:: Legend :class: note diff --git a/docs/projects/ad7134_fmc/index.rst b/docs/projects/ad7134_fmc/index.rst index 6d1d9752a6..bc9f9d9d48 100644 --- a/docs/projects/ad7134_fmc/index.rst +++ b/docs/projects/ad7134_fmc/index.rst @@ -252,40 +252,40 @@ HDL related - Documentation link * - AXI_CLKGEN - :git-hdl:`library/axi_clkgen` - - :ref:`here ` + - :ref:`axi_clkgen` * - AXI_DMAC - :git-hdl:`library/axi_dmac` - - :ref:`here ` + - :ref:`axi_dmac` * - AXI_HDMI_TX - :git-hdl:`library/axi_hdmi_tx` - - :ref:`here ` + - :ref:`axi_hdmi_tx` * - AXI_I2S_ADI - :git-hdl:`library/axi_i2s_adi` - --- * - AXI_PWM_GEN - :git-hdl:`library/axi_pwm_gen` - - :ref:`here ` + - :ref:`axi_pwm_gen` * - AXI_SDDIF_TX - :git-hdl:`library/axi_spdif_tx` - --- * - AXI_SYSID - :git-hdl:`library/axi_sysid` - - :ref:`here ` + - :ref:`axi_sysid` * - AXI_SPI_ENGINE - :git-hdl:`library/spi_engine/axi_spi_engine` - - :ref:`here ` + - :ref:`spi_engine axi` * - SPI_ENGINE_EXECUTION - :git-hdl:`library/spi_engine/spi_engine_execution` - - :ref:`here ` + - :ref:`spi_engine execution` * - SPI_ENGINE_INTERCONNECT - :git-hdl:`library/spi_engine/spi_engine_interconnect` - - :ref:`here ` + - :ref:`spi_engine interconnect` * - SPI_ENGINE_OFFLOAD - :git-hdl:`library/spi_engine/spi_engine_offload` - - :ref:`here ` + - :ref:`spi_engine offload` * - AXI_SYSID_ROM - :git-hdl:`library/sysid_rom` - - :ref:`here ` + - :ref:`axi_sysid` * - UTIL_I2C_MIXER - :git-hdl:`library/util_i2c_mixer` - --- diff --git a/docs/projects/ad738x_fmc/index.rst b/docs/projects/ad738x_fmc/index.rst index 002e510b12..b1b0139bd2 100644 --- a/docs/projects/ad738x_fmc/index.rst +++ b/docs/projects/ad738x_fmc/index.rst @@ -323,43 +323,43 @@ HDL related - Source code link - Documentation link * - AXI_CLKGEN - - :git-hdl:`library/axi_dmac ` - - :ref:`here ` + - :git-hdl:`library/axi_clkgen` + - :ref:`axi_clkgen` * - AXI_DMAC - - :git-hdl:`library/axi_dmac ` - - :ref:`here ` + - :git-hdl:`library/axi_dmac` + - :ref:`axi_dmac` * - AXI_HDMI_TX - - :git-hdl:`library/axi_hdmi_tx ` - - :ref:`here ` + - :git-hdl:`library/axi_hdmi_tx` + - :ref:`axi_hdmi_tx` * - AXI_I2S_ADI - - :git-hdl:`library/axi_i2s_adi ` + - :git-hdl:`library/axi_i2s_adi` - --- * - AXI_PWM_GEN - - :git-hdl:`library/axi_pwm_gen ` - - :ref:`here ` + - :git-hdl:`library/axi_pwm_gen` + - :ref:`axi_pwm_gen` * - AXI_SPDIF_TX - - :git-hdl:`library/axi_spdif_tx ` + - :git-hdl:`library/axi_spdif_tx` - --- * - AXI_SYSID - - :git-hdl:`library/axi_sysid ` - - :ref:`here ` + - :git-hdl:`library/axi_sysid` + - :ref:`axi_sysid` * - AXI_SPI_ENGINE - - :git-hdl:`library/spi_engine/axi_spi_engine ` - - :ref:`here ` + - :git-hdl:`library/spi_engine/axi_spi_engine` + - :ref:`spi_engine axi` * - SPI_ENGINE_EXECUTION - - :git-hdl:`library/spi_engine/spi_engine_execution ` - - :ref:`here ` + - :git-hdl:`library/spi_engine/spi_engine_execution` + - :ref:`spi_engine execution` * - SPI_ENGINE_INTERCONNECT - - :git-hdl:`library/spi_engine/spi_engine_interconnect ` - - :ref:`here ` + - :git-hdl:`library/spi_engine/spi_engine_interconnect` + - :ref:`spi_engine interconnect` * - SPI_ENGINE_OFFLOAD - - :git-hdl:`library/spi_engine/spi_engine_offload ` - - :ref:`here ` + - :git-hdl:`library/spi_engine/spi_engine_offload` + - :ref:`spi_engine offload` * - SYSID_ROM - - :git-hdl:`library/sysid_rom ` - - :ref:`here ` + - :git-hdl:`library/sysid_rom` + - :ref:`axi_sysid` * - UTIL_I2C-MIXER - - :git-hdl:`library/util_i2c_mixer ` + - :git-hdl:`library/util_i2c_mixer` - --- - :ref:`SPI Engine Framework documentation ` diff --git a/docs/projects/ad7606x_fmc/index.rst b/docs/projects/ad7606x_fmc/index.rst index 35f2421c2c..606b0b05ec 100644 --- a/docs/projects/ad7606x_fmc/index.rst +++ b/docs/projects/ad7606x_fmc/index.rst @@ -376,53 +376,53 @@ HDL related - :git-hdl:`library/util_cdc/sync_bits.v ` ** - --- * - AD_EDGE_DETECT - - :git-hdl:`library/common/ad_edge_detect.v ` + - :git-hdl:`library/common/ad_edge_detect.v` - --- * - AXI_AD7606x - - :git-hdl:`library/axi_ad7606x ` * - - :dokuwiki:`[Wiki] ` + - :git-hdl:`library/axi_ad7606x` * + - :ref:`axi_ad7606x` * - AXI_CLKGEN - - :git-hdl:`library/axi_clkgen ` - - :ref:`here ` + - :git-hdl:`library/axi_clkgen` + - :ref:`axi_clkgen` * - AXI_DMAC - - :git-hdl:`library/axi_dmac ` - - :ref:`here ` + - :git-hdl:`library/axi_dmac` + - :ref:`axi_dmac` * - AXI_HDMI_TX - - :git-hdl:`library/axi_hdmi_tx ` - - :ref:`here ` + - :git-hdl:`library/axi_hdmi_tx` + - :ref:`axi_hdmi_tx` * - AXI_I2S_ADI - - :git-hdl:`library/axi_i2s_adi ` + - :git-hdl:`library/axi_i2s_adi` - --- * - AXI_PWM_GEN - - :git-hdl:`library/axi_pwm_gen ` - - :ref:`here ` + - :git-hdl:`library/axi_pwm_gen` + - :ref:`axi_pwm_gen` * - AXI_SPDIF_TX - - :git-hdl:`library/axi_spdif_tx ` + - :git-hdl:`library/axi_spdif_tx` - --- * - AXI_SYSID - - :git-hdl:`library/axi_sysid ` - - :ref:`here ` + - :git-hdl:`library/axi_sysid` + - :ref:`axi_sysid` * - AXI_SPI_ENGINE - - :git-hdl:`library/spi_engine/axi_spi_engine ` ** - - :ref:`here ` + - :git-hdl:`library/spi_engine/axi_spi_engine` ** + - :ref:`spi_engine axi` * - SPI_ENGINE_EXECUTION - - :git-hdl:`library/spi_engine/spi_engine_execution ` ** - - :ref:`here ` + - :git-hdl:`library/spi_engine/spi_engine_execution` ** + - :ref:`spi_engine execution` * - SPI_ENGINE_INTERCONNECT - - :git-hdl:`library/spi_engine/spi_engine_interconnect ` ** - - :ref:`here ` + - :git-hdl:`library/spi_engine/spi_engine_interconnect` ** + - :ref:`spi_engine interconnect` * - SPI_ENGINE_OFFLOAD - - :git-hdl:`library/spi_engine/spi_engine_offload ` ** - - :ref:`here ` + - :git-hdl:`library/spi_engine/spi_engine_offload` ** + - :ref:`spi_engine offload` * - SYSID_ROM - - :git-hdl:`library/sysid_rom ` - - :ref:`here ` + - :git-hdl:`library/sysid_rom` + - :ref:`axi_sysid` * - UTIL_I2C_MIXER - - :git-hdl:`library/util_i2c_mixer ` + - :git-hdl:`library/util_i2c_mixer` - --- * - UTIL_CPACK2 - :git-hdl:`library/util_pack/util_cpack2 ` * - - :ref:`here ` + - :ref:`util_cpack2` .. admonition:: Legend :class: note diff --git a/docs/projects/ad7616_sdz/index.rst b/docs/projects/ad7616_sdz/index.rst index 407376493d..a61a39a62a 100644 --- a/docs/projects/ad7616_sdz/index.rst +++ b/docs/projects/ad7616_sdz/index.rst @@ -326,46 +326,46 @@ HDL related - --- * - AXI_AD7616 - :git-hdl:`library/axi_ad7616` * - - :ref:`here ` + - :ref:`axi_ad7616` * - AXI_CLKGEN - :git-hdl:`library/axi_clkgen` - - :ref:`here ` + - :ref:`axi_clkgen` * - AXI_DMAC - :git-hdl:`library/axi_dmac` - - :ref:`here ` + - :ref:`axi_dmac` * - AXI_HDMI_TX - :git-hdl:`library/axi_hdmi_tx` - - :ref:`here ` + - :ref:`axi_hdmi_tx` * - AXI_I2S_ADI - :git-hdl:`library/axi_i2s_adi` - --- * - AXI_PWM_GEN - :git-hdl:`library/axi_pwm_gen` - - :ref:`here ` + - :ref:`axi_pwm_gen` * - AXI_SPDIF_TX - :git-hdl:`library/axi_spdif_tx` - --- * - AXI_SPI_ENGINE - :git-hdl:`library/spi_engine/axi_spi_engine` ** - - :ref:`here ` + - :ref:`spi_engine axi` * - AXI_SYSID - :git-hdl:`library/axi_sysid` - - :ref:`here ` + - :ref:`axi_sysid` * - SPI_ENGINE_EXECUTION - :git-hdl:`library/spi_engine/spi_engine_execution` ** - - :ref:`here ` + - :ref:`spi_engine execution` * - SPI_ENGINE_INTERCONNECT - :git-hdl:`library/spi_engine/spi_engine_interconnect` ** - - :ref:`here ` + - :ref:`spi_engine interconnect` * - SPI_ENGINE_OFFLOAD - :git-hdl:`library/spi_engine/spi_engine_offload` ** - - :ref:`here ` + - :ref:`spi_engine offload` * - SYNC_BITS - :git-hdl:`library/util_cdc/sync_bits.v` - --- * - SYSID_ROM - :git-hdl:`library/sysid_rom` - - :ref:`here ` + - :ref:`axi_sysid` .. admonition:: Legend :class: note diff --git a/docs/projects/ad77681evb/index.rst b/docs/projects/ad77681evb/index.rst index 547ef40e7b..3785b6ae46 100644 --- a/docs/projects/ad77681evb/index.rst +++ b/docs/projects/ad77681evb/index.rst @@ -211,40 +211,40 @@ HDL related - Source code link - Documentation link * - AXI_CLKGEN - - :git-hdl:`library/axi_clkgen ` - - :ref:`here ` + - :git-hdl:`library/axi_clkgen` + - :ref:`axi_clkgen` * - AXI_DMAC - - :git-hdl:`library/axi_dmac ` - - :ref:`here ` + - :git-hdl:`library/axi_dmac` + - :ref:`axi_dmac` * - AXI_HDMI_TX - - :git-hdl:`library/axi_hdmi_tx ` - - :ref:`here ` + - :git-hdl:`library/axi_hdmi_tx` + - :ref:`axi_hdmi_tx` * - AXI_I2S_ADI - - :git-hdl:`library/axi_i2s_adi ` + - :git-hdl:`library/axi_i2s_adi` - --- * - AXI_SPDIF_TX - - :git-hdl:`library/axi_spdif_tx ` + - :git-hdl:`library/axi_spdif_tx` - --- * - AXI_SYSID - - :git-hdl:`library/axi_sysid ` - - :ref:`here ` + - :git-hdl:`library/axi_sysid` + - :ref:`axi_sysid` * - AXI_SPI_ENGINE - - :git-hdl:`library/spi_engine/axi_spi_engine ` - - :ref:`here ` + - :git-hdl:`library/spi_engine/axi_spi_engine` + - :ref:`spi_engine axi` * - SPI_ENGINE_EXECUTION - - :git-hdl:`library/spi_engine/spi_engine_execution ` - - :ref:`here ` + - :git-hdl:`library/spi_engine/spi_engine_execution` + - :ref:`spi_engine execution` * - SPI_ENGINE_INTERCONNECT - - :git-hdl:`library/spi_engine/spi_engine_interconnect ` - - :ref:`here ` + - :git-hdl:`library/spi_engine/spi_engine_interconnect` + - :ref:`spi_engine interconnect` * - SPI_ENGINE_OFFLOAD - :git-hdl:`library/spi_engine/spi_engine_offload` - - :ref:`here ` + - :ref:`spi_engine offload` * - SYSID_ROM - - :git-hdl:`library/sysid_rom ` - - :ref:`here ` + - :git-hdl:`library/sysid_rom` + - :ref:`axi_sysid` * - UTIL_I2C_MIXER - - :git-hdl:`library/util_i2c_mixer ` + - :git-hdl:`library/util_i2c_mixer` - --- - :ref:`SPI Engine Framework documentation ` diff --git a/docs/projects/ad7768evb/index.rst b/docs/projects/ad7768evb/index.rst index 130e006aa1..2c07091ce3 100644 --- a/docs/projects/ad7768evb/index.rst +++ b/docs/projects/ad7768evb/index.rst @@ -231,35 +231,35 @@ HDL related - Source code link - Documentation link * - AXI_AD7768 - - :git-hdl:`library/axi_ad7768 ` - - :ref:`here ` + - :git-hdl:`library/axi_ad7768` + - :ref:`axi_ad7768` * - AXI_CLKGEN - - :git-hdl:`library/axi_clkgen ` - - :ref:`here ` + - :git-hdl:`library/axi_clkgen` + - :ref:`axi_clkgen` * - AXI_DMAC - - :git-hdl:`library/axi_dmac ` - - :ref:`here ` + - :git-hdl:`library/axi_dmac` + - :ref:`axi_dmac` * - AXI_HDMI_TX - - :git-hdl:`library/axi_hdmi_tx ` - - :ref:`here ` + - :git-hdl:`library/axi_hdmi_tx` + - :ref:`axi_hdmi_tx` * - AXI_I2S_ADI - - :git-hdl:`library/axi_i2s_adi ` + - :git-hdl:`library/axi_i2s_adi` - --- * - AXI_SPDIF_TX - - :git-hdl:`library/axi_spdif_tx ` + - :git-hdl:`library/axi_spdif_tx` - --- * - AXI_SYSID - - :git-hdl:`library/axi_sysid ` - - :ref:`here ` + - :git-hdl:`library/axi_sysid` + - :ref:`axi_sysid` * - SYSID_ROM - - :git-hdl:`library/sysid_rom ` - - :ref:`here ` + - :git-hdl:`library/sysid_rom` + - :ref:`axi_sysid` * - UTIL_I2C_MIXER - - :git-hdl:`library/util_i2c_mixer ` + - :git-hdl:`library/util_i2c_mixer` - --- * - UTIL_CPACK2 - :git-hdl:`library/util_pack/util_cpack2 ` - - :ref:`here ` + - :ref:`util_cpack2` Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/projects/ad777x_ardz/index.rst b/docs/projects/ad777x_ardz/index.rst index 17098095a2..f6c4925077 100644 --- a/docs/projects/ad777x_ardz/index.rst +++ b/docs/projects/ad777x_ardz/index.rst @@ -246,16 +246,16 @@ HDL related - Documentation link * - AXI_AD777x - :git-hdl:`library/axi_ad777x` - - :ref:`here ` + - :ref:`axi_ad777x` * - AXI_CLKGEN* - :git-hdl:`library/axi_clkgen` - - :ref:`here ` + - :ref:`axi_clkgen` * - AXI_DMAC - :git-hdl:`library/axi_dmac` - - :ref:`here ` + - :ref:`axi_dmac` * - AXI_HDMI_TX - :git-hdl:`library/axi_hdmi_tx` - - :ref:`here ` + - :ref:`axi_hdmi_tx` * - AXI_I2S_ADI* - :git-hdl:`library/axi_i2s_adi` - — @@ -264,16 +264,16 @@ HDL related - — * - AXI_SYSID - :git-hdl:`library/axi_sysid` - - :ref:`here ` + - :ref:`axi_sysid` * - SYSID_ROM - :git-hdl:`library/sysid_rom` - - :ref:`here ` + - :ref:`axi_sysid` * - UTIL_I2C_MIXER* - :git-hdl:`library/util_i2c_mixer` - — * - UTIL_CPACK2 - :git-hdl:`library/util_pack/util_cpack2` - - :ref:`here ` + - :ref:`util_cpack2` .. admonition:: Legend :class: note diff --git a/docs/projects/ad9081_fmca_ebz/index.rst b/docs/projects/ad9081_fmca_ebz/index.rst index 160c14b2dd..677b6e790d 100644 --- a/docs/projects/ad9081_fmca_ebz/index.rst +++ b/docs/projects/ad9081_fmca_ebz/index.rst @@ -804,40 +804,40 @@ HDL related - Documentation link * - AXI_DMAC - :git-hdl:`library/axi_dmac` - - :ref:`here ` + - :ref:`axi_dmac` * - AXI_SYSID - :git-hdl:`library/axi_sysid` - - :ref:`here ` + - :ref:`axi_sysid` * - SYSID_ROM - :git-hdl:`library/sysid_rom` - - :ref:`here ` + - :ref:`axi_sysid` * - UTIL_CPACK2 - :git-hdl:`library/util_pack/util_cpack2` - - :ref:`here ` + - :ref:`util_cpack2` * - UTIL_UPACK2 - :git-hdl:`library/util_pack/util_upack2` - - :ref:`here ` + - :ref:`util_upack2` * - UTIL_ADXCVR for AMD - :git-hdl:`library/xilinx/util_adxcvr` - - :ref:`here ` + - :ref:`util_adxcvr` * - AXI_ADXCVR for Intel - :git-hdl:`library/intel/axi_adxcvr` - - :ref:`here ` + - :ref:`axi_adxcvr intel` * - AXI_ADXCVR for AMD - :git-hdl:`library/xilinx/axi_adxcvr` - - :ref:`here ` + - :ref:`axi_adxcvr amd` * - AXI_JESD204_RX - :git-hdl:`library/jesd204/axi_jesd204_rx` - - :ref:`here ` + - :ref:`axi_jesd204_rx` * - AXI_JESD204_TX - :git-hdl:`library/jesd204/axi_jesd204_tx` - - :ref:`here ` + - :ref:`axi_jesd204_tx` * - JESD204_TPL_ADC - :git-hdl:`library/jesd204/ad_ip_jesd204_tpl_adc` - - :ref:`here ` + - :ref:`ad_ip_jesd204_tpl_adc` * - JESD204_TPL_DAC - :git-hdl:`library/jesd204/ad_ip_jesd204_tpl_dac` - - :ref:`here ` + - :ref:`ad_ip_jesd204_tpl_dac` - :dokuwiki:`[Wiki] Generic JESD204B block designs ` - :ref:`jesd204` diff --git a/docs/projects/ad9081_fmca_ebz_x_band/index.rst b/docs/projects/ad9081_fmca_ebz_x_band/index.rst index 2bd3e99ba8..de2c4f94cf 100644 --- a/docs/projects/ad9081_fmca_ebz_x_band/index.rst +++ b/docs/projects/ad9081_fmca_ebz_x_band/index.rst @@ -365,70 +365,67 @@ HDL related - Documentation link * - AXI_DMAC - :git-hdl:`library/axi_dmac` - - :ref:`here ` + - :ref:`axi_dmac` * - AXI_SYSID - :git-hdl:`library/axi_sysid` - - :ref:`here ` + - :ref:`axi_sysid` * - AXI_TDD - :git-hdl:`library/axi_tdd` - - :ref:`here ` + - :ref:`axi_tdd` * - DATA_OFFLOAD - :git-hdl:`library/data_offload` - - :ref:`here ` + - :ref:`data_offload` * - JESD204_TPL_ADC - :git-hdl:`library/jesd204/ad_ip_jesd204_tpl_adc` - - :ref:`here ` - * - JESD204_TPL_DACm + - :ref:`ad_ip_jesd204_tpl_adc` + * - JESD204_TPL_DAC - :git-hdl:`library/jesd204/ad_ip_jesd204_tpl_dac` - - :ref:`here ` + - :ref:`ad_ip_jesd204_tpl_dac` * - AXI_JESD204_RX - :git-hdl:`library/jesd204/axi_jesd204_rx` - - :ref:`here ` + - :ref:`axi_jesd204_rx` * - AXI_JESD204_TX - :git-hdl:`library/jesd204/axi_jesd204_tx` - - :ref:`here ` - * - JESD204_RX - - :git-hdl:`library/jesd204/jesd204_rx` - - - * - JESD204_TX - - :git-hdl:`library/jesd204/jesd204_rx` - - + - :ref:`axi_jesd204_tx` + * - JESD204 + - :git-hdl:`library/jesd204` + - :ref:`jesd204` * - JESD204_VERSAL_GT_ADAPTER_RX - :git-hdl:`library/jesd204/jesd204_versal_gt_adapter_rx` - - + - --- * - JESD204_VERSAL_GT_ADAPTER_TX - :git-hdl:`library/jesd204/jesd204_versal_gt_adapter_tx` - - + - --- * - SYSID_ROM - :git-hdl:`library/sysid_rom` - - :ref:`here ` + - :ref:`axi_sysid` * - UTIL_ADCFIFO - :git-hdl:`library/util_adcfifo` - - + - --- * - UTIL_DACFIFO - :git-hdl:`library/util_dacfifo` - - + - --- * - UTIL_DO_RAM - :git-hdl:`library/util_do_ram` - - + - --- * - UTIL_HBM - :git-hdl:`library/util_hbm` - - + - --- * - UTIL_CPACK2 - :git-hdl:`library/util_pack/util_cpack2` - - :ref:`here ` + - :ref:`util_cpack2` * - UTIL_UPACK2 - :git-hdl:`library/util_pack/util_upack2` - - :ref:`here ` + - :ref:`util_upack2` * - AXI_ADXCVR for AMD - :git-hdl:`library/xilinx/axi_adxcvr` - - :ref:`here ` + - :ref:`axi_adxcvr amd` * - UTIL_ADXCVR for AMD - :git-hdl:`library/xilinx/util_adxcvr` - - :ref:`here ` + - :ref:`util_adxcvr` * - JESD204_TPL_DAC - :git-hdl:`library/jesd204/ad_ip_jesd204_tpl_dac` - - :ref:`here ` + - :ref:`ad_ip_jesd204_tpl_dac` - :dokuwiki:`[Wiki] Generic JESD204B block designs ` - :ref:`jesd204` diff --git a/docs/projects/ad9213_evb/index.rst b/docs/projects/ad9213_evb/index.rst index 85c69a6300..2b8c252d49 100644 --- a/docs/projects/ad9213_evb/index.rst +++ b/docs/projects/ad9213_evb/index.rst @@ -196,25 +196,25 @@ HDL related - Documentation link * - AXI_DMAC - :git-hdl:`library/axi_dmac` - - :ref:`here ` + - :ref:`axi_dmac` * - AXI_SYSID - :git-hdl:`library/axi_sysid` - - :ref:`here ` + - :ref:`axi_sysid` * - SYSID_ROM - :git-hdl:`library/sysid_rom` - - :ref:`here ` + - :ref:`axi_sysid` * - UTIL_ADXCVR - :git-hdl:`library/xilinx/util_adxcvr` - - :ref:`here ` + - :ref:`util_adxcvr` * - AXI_ADXCVR - :git-hdl:`library/xilinx/axi_adxcvr` - - :ref:`here ` + - :ref:`axi_adxcvr amd` * - AXI_JESD204_RX - :git-hdl:`library/jesd204/axi_jesd204_rx` - - :ref:`here ` + - :ref:`axi_jesd204_rx` * - JESD204_TPL_ADC - :git-hdl:`library/jesd204/ad_ip_jesd204_tpl_adc` - - :ref:`here ` + - :ref:`ad_ip_jesd204_tpl_adc` - :dokuwiki:`[Wiki] Generic JESD204B block designs ` - :ref:`jesd204` diff --git a/docs/projects/ad9265_fmc/index.rst b/docs/projects/ad9265_fmc/index.rst index 77802272ab..4819713cbf 100644 --- a/docs/projects/ad9265_fmc/index.rst +++ b/docs/projects/ad9265_fmc/index.rst @@ -172,32 +172,32 @@ HDL related - Source code link - Documentation link * - AXI_AD9265 - - :git-hdl:`library/axi_ad9265 ` - - :ref:`here ` + - :git-hdl:`library/axi_ad9265` + - :ref:`axi_ad9265` * - AXI_DMAC - - :git-hdl:`library/axi_dmac ` - - :ref:`here ` + - :git-hdl:`library/axi_dmac` + - :ref:`axi_dmac` * - AXI_CLKGEN - - :git-hdl:`library/axi_clkgen ` - - :ref:`here ` + - :git-hdl:`library/axi_clkgen` + - :ref:`axi_clkgen` * - AXI_HDMI_TX - - :git-hdl:`library/axi_hdmi_tx ` - - :ref:`here ` + - :git-hdl:`library/axi_hdmi_tx` + - :ref:`axi_hdmi_tx` * - AXI_SPDIF_TX - - :git-hdl:`library/axi_spdif_tx ` + - :git-hdl:`library/axi_spdif_tx` - --- * - AXI_I2S_ADI - - :git-hdl:`library/axi_sysid ` + - :git-hdl:`library/axi_i2s_adi` - --- * - AXI_SYSID - - :git-hdl:`library/axi_sysid ` - - :ref:`here ` + - :git-hdl:`library/axi_sysid` + - :ref:`axi_sysid` * - SYSID_ROM - - :git-hdl:`library/sysid_rom ` - - :ref:`here ` + - :git-hdl:`library/sysid_rom` + - :ref:`axi_sysid` * - UTIL_I2C_MIXER - - :git-hdl:`library/util_i2c_mixer ` - - :ref:`here ` + - :git-hdl:`library/util_i2c_mixer` + - :ref:`spi_engine offload` Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/projects/ad9434_fmc/index.rst b/docs/projects/ad9434_fmc/index.rst index 7ca72b9bc4..c80f6f698c 100644 --- a/docs/projects/ad9434_fmc/index.rst +++ b/docs/projects/ad9434_fmc/index.rst @@ -193,26 +193,26 @@ HDL related - Source code link - Documentation link * - AXI_AD9434 - - :git-hdl:`library/axi_ad9434 ` + - :git-hdl:`library/axi_ad9434` - --- * - AXI_DMAC - - :git-hdl:`library/axi_dmac ` - - :ref:`here ` + - :git-hdl:`library/axi_dmac` + - :ref:`axi_dmac` * - AXI_CLKGEN - - :git-hdl:`library/axi_clkgen ` - - :ref:`here ` + - :git-hdl:`library/axi_clkgen` + - :ref:`axi_clkgen` * - AXI_HDMI_TX - - :git-hdl:`library/axi_hdmi_tx ` - - :ref:`here ` + - :git-hdl:`library/axi_hdmi_tx` + - :ref:`axi_hdmi_tx` * - AXI_SPDIF_TX - - :git-hdl:`library/axi_spdif_tx ` + - :git-hdl:`library/axi_spdif_tx` - --- * - AXI_SYSID - - :git-hdl:`library/axi_sysid ` - - :ref:`here ` + - :git-hdl:`library/axi_sysid` + - :ref:`axi_sysid` * - SYSID_ROM - - :git-hdl:`library/sysid_rom ` - - :ref:`here ` + - :git-hdl:`library/sysid_rom` + - :ref:`axi_sysid` Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/projects/ad9467_fmc/index.rst b/docs/projects/ad9467_fmc/index.rst index 45eee8fee9..77ba41cea5 100644 --- a/docs/projects/ad9467_fmc/index.rst +++ b/docs/projects/ad9467_fmc/index.rst @@ -232,16 +232,16 @@ HDL related - Documentation link * - AXI_AD9467 - :git-hdl:`library/axi_ad9467` - - :ref:`here ` + - :ref:`axi_ad9467` * - AXI_CLKGEN - :git-hdl:`library/axi_clkgen` - - :ref:`here ` + - :ref:`axi_clkgen` * - AXI_DMAC - :git-hdl:`library/axi_dmac` - - :ref:`here ` + - :ref:`axi_dmac` * - AXI_HDMI_TX - :git-hdl:`library/axi_hdmi_tx` - - :ref:`here ` + - :ref:`axi_hdmi_tx` * - AXI_I2S_ADI - :git-hdl:`library/axi_i2s_adi` - --- @@ -250,10 +250,10 @@ HDL related - --- * - AXI_SYSID - :git-hdl:`library/axi_sysid` - - :ref:`here ` + - :ref:`axi_sysid` * - SYSID_ROM - :git-hdl:`library/sysid_rom` - - :ref:`here ` + - :ref:`axi_sysid` * - UTIL_I2C_MIXER - :git-hdl:`library/util_i2c_mixer` - --- diff --git a/docs/projects/ad9656_fmc/index.rst b/docs/projects/ad9656_fmc/index.rst index 6a4fed3add..ddddc0669e 100644 --- a/docs/projects/ad9656_fmc/index.rst +++ b/docs/projects/ad9656_fmc/index.rst @@ -218,31 +218,31 @@ HDL related - Documentation link * - AXI_DMAC - :git-hdl:`library/axi_dmac` - - :ref:`here ` + - :ref:`axi_dmac` * - AXI_SYSID - :git-hdl:`library/axi_sysid` - - :ref:`here ` + - :ref:`axi_sysid` * - AD_IP_JESD204_TPL_ADC - :git-hdl:`library/jesd204/ad_ip_jesd204_tpl_adc` - - :ref:`here ` + - :ref:`ad_ip_jesd204_tpl_adc` * - AXI_JESD204_RX - :git-hdl:`library/jesd204/axi_jesd204_rx` - - :ref:`here ` + - :ref:`axi_jesd204_rx` * - JESD204_RX - :git-hdl:`library/jesd204/axi_jesd204_rx` - - :ref:`here ` + - :ref:`axi_jesd204_rx` * - SYSID_ROM - :git-hdl:`library/sysid_rom` - - :ref:`here ` + - :ref:`axi_sysid` * - UTIL_CPACK2 - :git-hdl:`library/util_pack/util_cpack2` - - :ref:`here ` + - :ref:`util_cpack2` * - AXI_ADXCVR - :git-hdl:`library/xilinx/axi_adxcvr` - - :ref:`here ` + - :ref:`axi_adxcvr` * - UTIL_ADXCVR - :git-hdl:`library/xilinx/util_adxcvr` - - :ref:`here ` + - :ref:`util_adxcvr` Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/projects/ad9695_fmc/index.rst b/docs/projects/ad9695_fmc/index.rst index 50ab2b6b74..555ff1f998 100644 --- a/docs/projects/ad9695_fmc/index.rst +++ b/docs/projects/ad9695_fmc/index.rst @@ -306,7 +306,7 @@ HDL related - :ref:`util_adxcvr` * - AXI_ADXCVR for AMD - :git-hdl:`library/xilinx/axi_adxcvr` - - :ref:`axi_adxcvr` + - :ref:`axi_adxcvr amd` * - AXI_JESD204_RX - :git-hdl:`library/jesd204/axi_jesd204_rx` - :ref:`axi_jesd204_rx` diff --git a/docs/projects/ad9739a_fmc/index.rst b/docs/projects/ad9739a_fmc/index.rst index 00eb240bc0..fd2dfd2ab7 100644 --- a/docs/projects/ad9739a_fmc/index.rst +++ b/docs/projects/ad9739a_fmc/index.rst @@ -180,22 +180,22 @@ HDL related - — * - AXI_DMAC - :git-hdl:`library/axi_dmac` - - :ref:`here ` + - :ref:`axi_dmac` * - AXI_CLKGEN - :git-hdl:`library/axi_clkgen` - - :ref:`here ` + - :ref:`axi_clkgen` * - AXI_SYSID - :git-hdl:`library/axi_sysid` - - :ref:`here ` + - :ref:`axi_sysid` * - AXI_HDMI_TX - :git-hdl:`library/axi_hdmi_tx` - - :ref:`here ` + - :ref:`axi_hdmi_tx` * - AXI_SPDIF_TX - :git-hdl:`library/axi_spdif_tx` - — * - SYSID_ROM - :git-hdl:`library/sysid_rom` - - :ref:`here ` + - :ref:`axi_sysid` Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/projects/ad9783_ebz/index.rst b/docs/projects/ad9783_ebz/index.rst index 199ddc028a..a82dc972cc 100644 --- a/docs/projects/ad9783_ebz/index.rst +++ b/docs/projects/ad9783_ebz/index.rst @@ -175,19 +175,19 @@ HDL related - Documentation link * - AXI_AD9783 - :git-hdl:`library/axi_ad9783` - - :ref:`here ` + - :ref:`axi_ad9783` * - AXI_DMAC - :git-hdl:`library/axi_dmac` - - :ref:`here ` + - :ref:`axi_dmac` * - AXI_SYSID - :git-hdl:`library/axi_sysid` - - :ref:`here ` + - :ref:`axi_sysid` * - SYSID_ROM - :git-hdl:`library/sysid_rom` - - :ref:`here ` + - :ref:`axi_sysid` * - UTIL_UPACK2 - :git-hdl:`library/util_pack/util_upack2` - - :ref:`here ` + - :ref:`util_upack2` Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/projects/ad_gmsl2eth_sl/index.rst b/docs/projects/ad_gmsl2eth_sl/index.rst index 9a58173040..09c98381f2 100644 --- a/docs/projects/ad_gmsl2eth_sl/index.rst +++ b/docs/projects/ad_gmsl2eth_sl/index.rst @@ -277,20 +277,20 @@ HDL related - Source code link - Documentation link * - AXI_CLKGEN - - :git-hdl:`library/axi_clkgen ` - - :ref:`here ` + - :git-hdl:`library/axi_clkgen` + - :ref:`axi_clkgen` * - AXI_PWM_GEN - - :git-hdl:`library/axi_pwm_gen ` - - :ref:`here ` + - :git-hdl:`library/axi_pwm_gen` + - :ref:`axi_pwm_gen` * - AXI_SYSID - - :git-hdl:`library/axi_sysid ` - - :ref:`here ` + - :git-hdl:`library/axi_sysid` + - :ref:`axi_sysid` * - CORUNDUM - - :git-hdl:`library/corundum ` - - :ref:`here ` + - :git-hdl:`library/corundum` + - :ref:`corundum` * - SYSID_ROM - - :git-hdl:`library/sysid_rom ` - - :ref:`here ` + - :git-hdl:`library/sysid_rom` + - :ref:`axi_sysid` Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/projects/adaq7980_sdz/index.rst b/docs/projects/adaq7980_sdz/index.rst index af302e110a..f13adbc6ea 100644 --- a/docs/projects/adaq7980_sdz/index.rst +++ b/docs/projects/adaq7980_sdz/index.rst @@ -208,44 +208,44 @@ HDL related - Source code link - Documentation link * - AXI_CLKGEN - - :git-hdl:`library/axi_dmac ` - - :ref:`here ` + - :git-hdl:`library/axi_clkgen` + - :ref:`axi_clkgen` * - AXI_DMAC - - :git-hdl:`library/axi_dmac ` - - :ref:`here ` + - :git-hdl:`library/axi_dmac` + - :ref:`axi_dmac` * - AXI_HDMI_TX - - :git-hdl:`library/axi_hdmi_tx ` - - :ref:`here ` + - :git-hdl:`library/axi_hdmi_tx` + - :ref:`axi_hdmi_tx` * - AXI_I2S_ADI - - :git-hdl:`library/axi_i2s_adi ` + - :git-hdl:`library/axi_i2s_adi` - --- * - AXI_PWM_GEN - - :git-hdl:`library/axi_pwm_gen ` - - :ref:`here ` + - :git-hdl:`library/axi_pwm_gen` + - :ref:`axi_pwm_gen` * - AXI_SPDIF_TX - - :git-hdl:`library/axi_spdif_tx ` + - :git-hdl:`library/axi_spdif_tx` - --- * - AXI_SPI_ENGINE - - :git-hdl:`library/spi_engine/axi_spi_engine ` - - :ref:`here ` + - :git-hdl:`library/spi_engine/axi_spi_engine` + - :ref:`spi_engine axi` * - AXI_SYSID - - :git-hdl:`library/axi_sysid ` - - :ref:`here ` + - :git-hdl:`library/axi_sysid` + - :ref:`axi_sysid` * - SPI_ENGINE_EXECUTION - - :git-hdl:`library/spi_engine/spi_engine_execution ` - - :ref:`here ` + - :git-hdl:`library/spi_engine/spi_engine_execution` + - :ref:`spi_engine execution` * - SPI_ENGINE_INTERCONNECT - - :git-hdl:`library/spi_engine/spi_engine_interconnect ` - - :ref:`here ` + - :git-hdl:`library/spi_engine/spi_engine_interconnect` + - :ref:`spi_engine interconnect` * - SPI_ENGINE_OFFLOAD - - :git-hdl:`library/spi_engine/spi_engine_offload ` - - :ref:`here ` + - :git-hdl:`library/spi_engine/spi_engine_offload` + - :ref:`spi_engine offload` * - SYSID_ROM - - :git-hdl:`library/sysid_rom ` - - :ref:`here ` + - :git-hdl:`library/sysid_rom` + - :ref:`axi_sysid` * - UTIL_I2C_MIXER - - :git-hdl:`library/util_i2c_mixer ` - - :ref:`here ` + - :git-hdl:`library/util_i2c_mixer` + - :ref:`spi_engine offload` - :ref:`SPI Engine Framework documentation ` diff --git a/docs/projects/adaq8092_fmc/index.rst b/docs/projects/adaq8092_fmc/index.rst index 8272c4bd2f..f384b89b3b 100644 --- a/docs/projects/adaq8092_fmc/index.rst +++ b/docs/projects/adaq8092_fmc/index.rst @@ -199,16 +199,16 @@ HDL related - Documentation link * - AXI_ADAQ8092 - :git-hdl:`library/axi_adaq8092` - - :ref:`here ` + - :ref:`axi_adaq8092` * - AXI_CLKGEN - :git-hdl:`library/axi_clkgen` - - :ref:`here ` + - :ref:`axi_clkgen` * - AXI_DMAC - :git-hdl:`library/axi_dmac` - - :ref:`here ` + - :ref:`axi_dmac` * - AXI_HDMI_TX - :git-hdl:`library/axi_hdmi_tx` - - :ref:`here ` + - :ref:`axi_hdmi_tx` * - AXI_I2S_ADI - :git-hdl:`library/axi_i2s_adi` - — @@ -217,16 +217,16 @@ HDL related - — * - AXI_SYSID - :git-hdl:`library/axi_sysid` - - :ref:`here ` + - :ref:`axi_sysid` * - SYSID_ROM - :git-hdl:`library/sysid_rom` - - :ref:`here ` + - :ref:`axi_sysid` * - UTIL_I2C_MIXER - :git-hdl:`library/util_i2c_mixer` - — * - UTIL_CPACK2 - :git-hdl:`library/util_pack/util_cpack2` - - :ref:`here ` + - :ref:`util_cpack2` Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/projects/adrv9026/index.rst b/docs/projects/adrv9026/index.rst index 064b530e6d..a418243079 100644 --- a/docs/projects/adrv9026/index.rst +++ b/docs/projects/adrv9026/index.rst @@ -496,40 +496,40 @@ HDL related - Documentation link * - AXI_DMAC - :git-hdl:`library/axi_dmac` - - :ref:`here ` + - :ref:`axi_dmac` * - AXI_SYSID - :git-hdl:`library/axi_sysid` - - :ref:`here ` + - :ref:`axi_sysid` * - SYSID_ROM - :git-hdl:`library/sysid_rom` - - :ref:`here ` + - :ref:`axi_sysid` * - UTIL_UPACK2 - :git-hdl:`library/util_pack/util_upack2` - - :ref:`here ` + - :ref:`util_upack2` * - UTIL_CPACK2 - :git-hdl:`library/util_pack/util_cpack2` - - :ref:`here ` + - :ref:`util_upack2` * - UTIL_ADXCVR for AMD - :git-hdl:`library/xilinx/util_adxcvr` - - :ref:`here ` + - :ref:`util_adxcvr` * - AXI_ADXCVR for Intel - :git-hdl:`library/intel/axi_adxcvr` - - :ref:`here ` + - :ref:`axi_adxcvr intel` * - AXI_ADXCVR for AMD - :git-hdl:`library/xilinx/axi_adxcvr` - - :ref:`here ` + - :ref:`axi_adxcvr amd` * - AXI_JESD204_RX - :git-hdl:`library/jesd204/axi_jesd204_rx` - - :ref:`here ` + - :ref:`axi_jesd204_rx` * - AXI_JESD204_TX - :git-hdl:`library/jesd204/axi_jesd204_tx` - - :ref:`here ` + - :ref:`axi_jesd204_tx` * - JESD204_TPL_ADC - :git-hdl:`library/jesd204/ad_ip_jesd204_tpl_adc` - - :ref:`here ` + - :ref:`ad_ip_jesd204_tpl_adc` * - JESD204_TPL_DAC - :git-hdl:`library/jesd204/ad_ip_jesd204_tpl_dac` - - :ref:`here ` + - :ref:`ad_ip_jesd204_tpl_dac` - :dokuwiki:`[Wiki] Generic JESD204B block designs ` - :ref:`jesd204` diff --git a/docs/projects/adrv904x/index.rst b/docs/projects/adrv904x/index.rst index 159005d1c7..609d556db1 100644 --- a/docs/projects/adrv904x/index.rst +++ b/docs/projects/adrv904x/index.rst @@ -379,43 +379,43 @@ HDL related - Documentation link * - AXI_DMAC - :git-hdl:`library/axi_dmac` - - :ref:`here ` + - :ref:`axi_dmac` * - AXI_SYSID - :git-hdl:`library/axi_sysid` - - :ref:`here ` + - :ref:`axi_sysid` * - SYSID_ROM - :git-hdl:`library/sysid_rom` - - :ref:`here ` + - :ref:`axi_sysid` * - UTIL_CPACK2 - :git-hdl:`library/util_pack/util_cpack2` - - :ref:`here ` + - :ref:`util_cpack2` * - UTIL_UPACK2 - :git-hdl:`library/util_pack/util_upack2` - - :ref:`here ` + - :ref:`util_upack2` * - DATA_OFFLOAD - :git-hdl:`library/data_offload` - - :ref:`here ` + - :ref:`data_offload` * - UTIL_DO_RAM - :git-hdl:`library/util_do_ram` - - :ref:`here ` + - :ref:`data_offload` * - UTIL_ADXCVR for AMD - :git-hdl:`library/xilinx/util_adxcvr` - - :ref:`here ` + - :ref:`util_adxcvr` * - AXI_ADXCVR for AMD - :git-hdl:`library/xilinx/axi_adxcvr` - - :ref:`here ` + - :ref:`axi_adxcvr amd` * - AXI_JESD204_RX - :git-hdl:`library/jesd204/axi_jesd204_rx` - - :ref:`here ` + - :ref:`axi_jesd204_rx` * - AXI_JESD204_TX - :git-hdl:`library/jesd204/axi_jesd204_tx` - - :ref:`here ` + - :ref:`axi_jesd204_tx` * - JESD204_TPL_ADC - :git-hdl:`library/jesd204/ad_ip_jesd204_tpl_adc` - - :ref:`here ` + - :ref:`ad_ip_jesd204_tpl_dac` * - JESD204_TPL_DAC - :git-hdl:`library/jesd204/ad_ip_jesd204_tpl_dac` - - :ref:`here ` + - :ref:`ad_ip_jesd204_tpl_dac` - :ref:`jesd204` diff --git a/docs/projects/adv7511/index.rst b/docs/projects/adv7511/index.rst index 8d2c815048..bd116d3402 100644 --- a/docs/projects/adv7511/index.rst +++ b/docs/projects/adv7511/index.rst @@ -188,19 +188,19 @@ HDL related - Documentation link * - AXI_CLKGEN - :git-hdl:`library/axi_clkgen` - - :ref:`here ` + - :ref:`axi_clkgen` * - AXI_HDMI_TX - :git-hdl:`library/axi_hdmi_tx` - - :ref:`here ` + - :ref:`axi_hdmi_tx` * - AXI_I2S_ADI * - :git-hdl:`library/axi_i2s_adi` - --- * - AXI_SYSID - - :git-hdl:`library/axi_sysid ` - - :ref:`here ` + - :git-hdl:`library/axi_sysid` + - :ref:`axi_sysid` * - SYSID_ROM - - :git-hdl:`library/sysid_rom ` - - :ref:`here ` + - :git-hdl:`library/sysid_rom` + - :ref:`axi_sysid` * - AXI_SDDIF_TX - :git-hdl:`library/axi_spdif_tx` - --- diff --git a/docs/projects/adv7513/index.rst b/docs/projects/adv7513/index.rst index a708beecdd..f8b2160dfe 100644 --- a/docs/projects/adv7513/index.rst +++ b/docs/projects/adv7513/index.rst @@ -148,17 +148,17 @@ HDL related - Source code link - Documentation link * - AXI_DMAC - - :git-hdl:`library/axi_dmac ` - - :ref:`here ` + - :git-hdl:`library/axi_dmac` + - :ref:`axi_dmac` * - AXI_HDMI_TX - :git-hdl:`library/axi_hdmi_tx` - - :ref:`here ` + - :ref:`axi_hdmi_tx` * - AXI_SYSID - - :git-hdl:`library/axi_sysid ` - - :ref:`here ` + - :git-hdl:`library/axi_sysid` + - :ref:`axi_sysid` * - SYSID_ROM - - :git-hdl:`library/sysid_rom ` - - :ref:`here ` + - :git-hdl:`library/sysid_rom` + - :ref:`axi_sysid` Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/projects/cn0363/index.rst b/docs/projects/cn0363/index.rst index 050f184e8e..5dafd450f7 100644 --- a/docs/projects/cn0363/index.rst +++ b/docs/projects/cn0363/index.rst @@ -222,56 +222,56 @@ HDL related - Source code link - Documentation link * - AXI_DMAC - - :git-hdl:`library/axi_dmac ` - - :ref:`here ` + - :git-hdl:`library/axi_dmac` + - :ref:`axi_dmac` * - AXI_GENERIC_ADC - - :git-hdl:`library/axi_generic_adc ` + - :git-hdl:`library/axi_generic_adc` - --- * - AXI_HDMI_TX - - :git-hdl:`library/axi_hdmi_tx ` - - :ref:`here ` + - :git-hdl:`library/axi_hdmi_tx` + - :ref:`axi_hdmi_tx` * - AXI_I2S_ADI - - :git-hdl:`library/axi_i2s_adi ` + - :git-hdl:`library/axi_i2s_adi` - --- * - AXI_SPDIF_TX - - :git-hdl:`library/axi_spdif_tx ` + - :git-hdl:`library/axi_spdif_tx` - --- * - AXI_SYSID - - :git-hdl:`library/axi_sysid ` - - :ref:`here ` + - :git-hdl:`library/axi_sysid` + - :ref:`axi_sysid` * - CN0363_DMA_SEQUENCER - - :git-hdl:`library/cn0363/cn0363_dma_sequencer ` - - :dokuwiki:`[Wiki] ` + - :git-hdl:`library/cn0363/cn0363_dma_sequencer` + - :dokuwiki:`[Wiki] ` * - CN0363_PHASE_DATA_SYNC - - :git-hdl:`library/cn0363/cn0363_phase_data_sync ` + - :git-hdl:`library/cn0363/cn0363_phase_data_sync` - :dokuwiki:`[Wiki] ` * - CORDIC_DEMOD - - :git-hdl:`library/cordic_demod ` + - :git-hdl:`library/cordic_demod` - --- * - AXI_SPI_ENGINE - - :git-hdl:`library/spi_engine/axi_spi_engine ` - - :ref:`here ` + - :git-hdl:`library/spi_engine/axi_spi_engine` + - :ref:`spi_engine axi` * - SPI_ENGINE_EXECUTION - - :git-hdl:`library/spi_engine/spi_engine_execution ` - - :ref:`here ` + - :git-hdl:`library/spi_engine/spi_engine_execution` + - :ref:`spi_engine execution` * - SPI_ENGINE_INTERCONNECT - - :git-hdl:`library/spi_engine/spi_engine_interconnect ` - - :ref:`here ` + - :git-hdl:`library/spi_engine/spi_engine_interconnect` + - :ref:`spi_engine interconnect` * - SPI_ENGINE_OFFLOAD - :git-hdl:`library/spi_engine/spi_engine_offload` - - :ref:`here ` + - :ref:`spi_engine offload` * - SYSID_ROM - - :git-hdl:`library/sysid_rom ` - - :ref:`here ` + - :git-hdl:`library/sysid_rom` + - :ref:`axi_sysid` * - UTIL_AXIS_RESIZE - :git-hdl:`library/util_axis_resize` - --- * - UTIL_I2C-MIXER - - :git-hdl:`library/util_i2c_mixer ` + - :git-hdl:`library/util_i2c_mixer` - --- * - UTIL_SIGMA_DELTA_SPI - - :git-hdl:`library/util_sigma_delta_spi ` - - :dokuwiki:`[Wiki] ` + - :git-hdl:`library/util_sigma_delta_spi` + - :ref:`util_sigma_delta_spi` - :ref:`SPI Engine Framework documentation ` diff --git a/docs/projects/cn0506/index.rst b/docs/projects/cn0506/index.rst index 8e9f59b9bb..9cbc5a94b8 100644 --- a/docs/projects/cn0506/index.rst +++ b/docs/projects/cn0506/index.rst @@ -324,19 +324,19 @@ HDL related - Documentation link * - AXI_CLKGEN * - :git-hdl:`library/axi_clkgen` - - :ref:`here ` + - :ref:`axi_clkgen` * - AXI_HDMI_TX * - :git-hdl:`library/axi_hdmi_tx` - - :ref:`here ` + - :ref:`axi_hdmi_tx` * - AXI_I2S_ADI ** - :git-hdl:`library/axi_i2s_adi` - --- * - AXI_SYSID - - :git-hdl:`library/axi_sysid ` - - :ref:`here ` + - :git-hdl:`library/axi_sysid` + - :ref:`axi_sysid` * - SYSID_ROM - - :git-hdl:`library/sysid_rom ` - - :ref:`here ` + - :git-hdl:`library/sysid_rom` + - :ref:`axi_sysid` * - AXI_SDDIF_TX * - :git-hdl:`library/axi_spdif_tx` - --- @@ -345,7 +345,7 @@ HDL related - --- * - UTIL_MII_TO_RMII \*** - :git-hdl:`library/util_mii_to_rmii` - - :ref:`here ` + - :ref:`util_mii_to_rmii` .. admonition:: Legend :class: note diff --git a/docs/projects/cn0540/index.rst b/docs/projects/cn0540/index.rst index 5b2e90c2af..ac99b0a383 100644 --- a/docs/projects/cn0540/index.rst +++ b/docs/projects/cn0540/index.rst @@ -318,32 +318,32 @@ HDL related - Source code link - Documentation link * - AXI_CLKGEN - - :git-hdl:`library/axi_dmac ` * - - :ref:`here ` + - :git-hdl:`library/axi_clkgen` * + - :ref:`axi_clkgen` * - AXI_DMAC - - :git-hdl:`library/axi_dmac ` - - :ref:`here ` + - :git-hdl:`library/axi_dmac` + - :ref:`axi_dmac` * - AXI_HDMI_TX - - :git-hdl:`library/axi_hdmi_tx ` ** - - :ref:`here ` + - :git-hdl:`library/axi_hdmi_tx` ** + - :ref:`axi_hdmi_tx` * - AXI_SYSID - - :git-hdl:`library/axi_sysid ` - - :ref:`here ` + - :git-hdl:`library/axi_sysid` + - :ref:`axi_sysid` * - AXI_SPI_ENGINE - - :git-hdl:`library/spi_engine/axi_spi_engine ` - - :ref:`here ` + - :git-hdl:`library/spi_engine/axi_spi_engine` + - :ref:`spi_engine axi` * - SPI_ENGINE_EXECUTION - - :git-hdl:`library/spi_engine/spi_engine_execution ` - - :ref:`here ` + - :git-hdl:`library/spi_engine/spi_engine_execution` + - :ref:`spi_engine execution` * - SPI_ENGINE_INTERCONNECT - - :git-hdl:`library/spi_engine/spi_engine_interconnect ` - - :ref:`here ` + - :git-hdl:`library/spi_engine/spi_engine_interconnect` + - :ref:`spi_engine interconnect` * - SPI_ENGINE_OFFLOAD - :git-hdl:`library/spi_engine/spi_engine_offload` - - :ref:`here ` + - :ref:`spi_engine offload` * - SYSID_ROM - - :git-hdl:`library/sysid_rom ` - - :ref:`here ` + - :git-hdl:`library/sysid_rom` + - :ref:`axi_sysid` .. admonition:: Legend :class: note diff --git a/docs/projects/cn0561/index.rst b/docs/projects/cn0561/index.rst index 0f27c9b995..f7a68220c5 100644 --- a/docs/projects/cn0561/index.rst +++ b/docs/projects/cn0561/index.rst @@ -232,40 +232,40 @@ HDL related - Documentation link * - AXI_CLKGEN - :git-hdl:`library/axi_clkgen` - - :ref:`here ` + - :ref:`axi_clkgen` * - AXI_DMAC - :git-hdl:`library/axi_dmac` - - :ref:`here ` + - :ref:`axi_dmac` * - AXI_HDMI_TX ** - :git-hdl:`library/axi_hdmi_tx` - - :ref:`here ` + - :ref:`axi_hdmi_tx` * - AXI_I2S_ADI * - :git-hdl:`library/axi_i2s_adi` - --- * - AXI_PWM_GEN - :git-hdl:`library/axi_pwm_gen` - - :ref:`here ` + - :ref:`axi_pwm_gen` * - AXI_SDDIF_TX * - :git-hdl:`library/axi_spdif_tx` - --- * - AXI_SYSID - :git-hdl:`library/axi_sysid` - - :ref:`here ` + - :ref:`axi_sysid` * - AXI_SPI_ENGINE - :git-hdl:`library/spi_engine/axi_spi_engine` - - :ref:`here ` + - :ref:`spi_engine axi` * - SPI_ENGINE_EXECUTION - :git-hdl:`library/spi_engine/spi_engine_execution` - - :ref:`here ` + - :ref:`spi_engine execution` * - SPI_ENGINE_INTERCONNECT - :git-hdl:`library/spi_engine/spi_engine_interconnect` - - :ref:`here ` + - :ref:`spi_engine interconnect` * - SPI_ENGINE_OFFLOAD - :git-hdl:`library/spi_engine/spi_engine_offload` - - :ref:`here ` + - :ref:`spi_engine offload` * - AXI_SYSID_ROM - :git-hdl:`library/sysid_rom` - - :ref:`here ` + - :ref:`axi_sysid` * - UTIL_I2C_MIXER * - :git-hdl:`library/util_i2c_mixer` - --- diff --git a/docs/projects/cn0577/index.rst b/docs/projects/cn0577/index.rst index 705f12e3b9..3fe84dbbf5 100644 --- a/docs/projects/cn0577/index.rst +++ b/docs/projects/cn0577/index.rst @@ -209,22 +209,22 @@ HDL related - Documentation link * - AXI_LTC2387 - :git-hdl:`library/axi_ltc2387` - - :dokuwiki:`[Wiki] ` + - :ref:`axi_ltc2387` * - AXI_CLKGEN - :git-hdl:`library/axi_clkgen` - - :ref:`here ` + - :ref:`axi_clkgen` * - AXI_DMAC - :git-hdl:`library/axi_dmac` - - :ref:`here ` + - :ref:`axi_dmac` * - AXI_SYSID - :git-hdl:`library/axi_sysid` - - :ref:`here ` + - :ref:`axi_sysid` * - AXI_PWM_GEN - :git-hdl:`library/axi_pwm_gen` - - :ref:`here ` + - :ref:`axi_pwm_gen` * - AXI_HDMI_TX - :git-hdl:`library/axi_hdmi_tx` - - :ref:`here ` + - :ref:`axi_hdmi_tx` * - AXI_I2S_ADI - :git-hdl:`library/axi_i2s_adi` - — @@ -233,7 +233,7 @@ HDL related - — * - SYSID_ROM - :git-hdl:`library/sysid_rom` - - :ref:`here ` + - :ref:`axi_sysid` * - UTIL_I2C_MIXER - :git-hdl:`library/util_i2c_mixer` - — diff --git a/docs/projects/cn0579/index.rst b/docs/projects/cn0579/index.rst index f761b4b6e2..8633882ad0 100644 --- a/docs/projects/cn0579/index.rst +++ b/docs/projects/cn0579/index.rst @@ -250,19 +250,19 @@ HDL related - Documentation link * - AXI_AD7768 - :git-hdl:`library/axi_ad7768` - - :ref:`here ` + - :ref:`axi_ad7768` * - AXI_DMAC - :git-hdl:`library/axi_dmac` - - :ref:`here ` + - :ref:`axi_dmac` * - AXI_SYSID - :git-hdl:`library/axi_sysid` - - :ref:`here ` + - :ref:`axi_sysid` * - SYSID_ROM - :git-hdl:`library/sysid_rom` - - :ref:`here ` + - :ref:`axi_sysid` * - UTIL_CPACK2 - :git-hdl:`library/util_pack/util_cpack2` - - :ref:`here ` + - :ref:`util_cpack2` Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/projects/cn0585/index.rst b/docs/projects/cn0585/index.rst index d575ef559a..ab6a464ac1 100644 --- a/docs/projects/cn0585/index.rst +++ b/docs/projects/cn0585/index.rst @@ -236,28 +236,28 @@ HDL related - Documentation link * - AXI_AD3552R - :git-hdl:`library/axi_ad3552r` - - :ref:`here ` + - :ref:`axi_ad3552r` * - AXI_LTC2387 - :git-hdl:`library/axi_ltc2387` - - :dokuwiki:`[Wiki] ` + - :ref:`axi_ltc2387` * - AXI_DMAC - :git-hdl:`library/axi_dmac` - - :ref:`here ` + - :ref:`axi_dmac` * - AXI_SYSID - :git-hdl:`library/axi_sysid` - - :ref:`here ` + - :ref:`axi_sysid` * - SYSID_ROM - :git-hdl:`library/sysid_rom` - - :ref:`here ` + - :ref:`axi_sysid` * - AXI_CLKGEN - :git-hdl:`library/axi_clkgen` - - :ref:`here ` + - :ref:`axi_clkgen` * - AXI_PWM_GEN - :git-hdl:`library/axi_pwm_gen` - - :ref:`here ` + - :ref:`axi_pwm_gen` * - AXI_HDMI_TX - :git-hdl:`library/axi_hdmi_tx` - - :ref:`here ` + - :ref:`axi_hdmi_tx` * - AXI_I2S_ADI - :git-hdl:`library/axi_i2s_adi` - — @@ -269,7 +269,7 @@ HDL related - — * - UTIL_PACK/UTIL_CPACK2 - :git-hdl:`library/util_pack/util_cpack2` - - :ref:`here ` + - :ref:`util_cpack2` Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/projects/max96724/index.rst b/docs/projects/max96724/index.rst index 8358800c5d..af797ab4fa 100644 --- a/docs/projects/max96724/index.rst +++ b/docs/projects/max96724/index.rst @@ -203,8 +203,8 @@ HDL related - Source code link - Documentation link * - AXI_SYSID - - :git-hdl:`library/axi_sysid ` - - :ref:`here ` + - :git-hdl:`library/axi_sysid` + - :ref:`axi_sysid` Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/projects/pulsar_adc/index.rst b/docs/projects/pulsar_adc/index.rst index b17c1214d7..9bc032cf48 100644 --- a/docs/projects/pulsar_adc/index.rst +++ b/docs/projects/pulsar_adc/index.rst @@ -407,43 +407,43 @@ HDL related - Source code link - Documentation link * - AXI_CLKGEN - - :git-hdl:`library/axi_clkgen ` - - :ref:`here ` + - :git-hdl:`library/axi_clkgen` + - :ref:`axi_clkgen` * - AXI_DMAC - - :git-hdl:`library/axi_dmac ` - - :ref:`here ` + - :git-hdl:`library/axi_dmac` + - :ref:`axi_dmac` * - AXI_HDMI_TX - - :git-hdl:`library/axi_hdmi_tx ` * - - :ref:`here ` + - :git-hdl:`library/axi_hdmi_tx` * + - :ref:`axi_hdmi_tx` * - AXI_I2S_ADI - - :git-hdl:`library/axi_i2s_adi ` * + - :git-hdl:`library/axi_i2s_adi` * - --- * - AXI_PWM_GEN - :git-hdl:`library/axi_pwm_gen` - - :ref:`here ` + - :ref:`axi_pwm_gen` * - AXI_SPDIF_TX - - :git-hdl:`library/axi_spdif_tx ` * + - :git-hdl:`library/axi_spdif_tx` * - --- * - AXI_SYSID - - :git-hdl:`library/axi_sysid ` - - :ref:`here ` + - :git-hdl:`library/axi_sysid` + - :ref:`axi_sysid` * - AXI_SPI_ENGINE - - :git-hdl:`library/spi_engine/axi_spi_engine ` - - :ref:`here ` + - :git-hdl:`library/spi_engine/axi_spi_engine` + - :ref:`spi_engine axi` * - SPI_ENGINE_EXECUTION - - :git-hdl:`library/spi_engine/spi_engine_execution ` - - :ref:`here ` + - :git-hdl:`library/spi_engine/spi_engine_execution` + - :ref:`spi_engine execution` * - SPI_ENGINE_INTERCONNECT - - :git-hdl:`library/spi_engine/spi_engine_interconnect ` - - :ref:`here ` + - :git-hdl:`library/spi_engine/spi_engine_interconnect` + - :ref:`spi_engine interconnect` * - SPI_ENGINE_OFFLOAD - :git-hdl:`library/spi_engine/spi_engine_offload` - - :ref:`here ` + - :ref:`spi_engine offload` * - SYSID_ROM - - :git-hdl:`library/sysid_rom ` - - :ref:`here ` + - :git-hdl:`library/sysid_rom` + - :ref:`axi_sysid` * - UTIL_I2C_MIXER - - :git-hdl:`library/util_i2c_mixer ` * + - :git-hdl:`library/util_i2c_mixer` * - --- .. admonition:: Legend diff --git a/docs/projects/pulsar_lvds/index.rst b/docs/projects/pulsar_lvds/index.rst index b672f1a796..b3915eb9ec 100644 --- a/docs/projects/pulsar_lvds/index.rst +++ b/docs/projects/pulsar_lvds/index.rst @@ -312,34 +312,34 @@ HDL related - Source code link - Documentation link * - AXI_PULSAR_LVDS - - :git-hdl:`library/axi_pulsar_lvds ` + - :git-hdl:`library/axi_pulsar_lvds` - --- * - AXI_CLKGEN - - :git-hdl:`library/axi_clkgen ` - - :ref:`here ` + - :git-hdl:`library/axi_clkgen` + - :ref:`axi_clkgen` * - AXI_DMAC - - :git-hdl:`library/axi_dmac ` - - :ref:`here ` + - :git-hdl:`library/axi_dmac` + - :ref:`axi_dmac` * - AXI_HDMI_TX - - :git-hdl:`library/axi_hdmi_tx ` - - :ref:`here ` + - :git-hdl:`library/axi_hdmi_tx` + - :ref:`axi_hdmi_tx` * - AXI_I2S_ADI - - :git-hdl:`library/axi_i2s_adi ` + - :git-hdl:`library/axi_i2s_adi` - --- * - AXI_PWM_GEN - :git-hdl:`library/axi_pwm_gen` - - :ref:`here ` + - :ref:`axi_pwm_gen` * - AXI_SPDIF_TX - - :git-hdl:`library/axi_spdif_tx ` + - :git-hdl:`library/axi_spdif_tx` - --- * - AXI_SYSID - - :git-hdl:`library/axi_sysid ` - - :ref:`here ` + - :git-hdl:`library/axi_sysid` + - :ref:`axi_sysid` * - SYSID_ROM - - :git-hdl:`library/sysid_rom ` - - :ref:`here ` + - :git-hdl:`library/sysid_rom` + - :ref:`axi_sysid` * - UTIL_I2C_MIXER - - :git-hdl:`library/util_i2c_mixer ` + - :git-hdl:`library/util_i2c_mixer` - --- .. include:: ../common/more_information.rst diff --git a/docs/projects/template/index.rst b/docs/projects/template/index.rst index dc0c6dec1b..ea070712f9 100644 --- a/docs/projects/template/index.rst +++ b/docs/projects/template/index.rst @@ -711,28 +711,28 @@ HDL related - Documentation link * - AXI_DMAC - :git-hdl:`library/axi_dmac` - - :ref:`here ` + - :ref:`axi_dmac` * - AXI_SYSID - :git-hdl:`library/axi_sysid` - - :ref:`here ` + - :ref:`axi_sysid` * - SYSID_ROM - :git-hdl:`library/sysid_rom` - - :ref:`here ` + - :ref:`axi_sysid` * - UTIL_CPACK2 - :git-hdl:`library/util_pack/util_cpack2` - - :ref:`here ` + - :ref:`util_cpack2` * - UTIL_UPACK2 - :git-hdl:`library/util_pack/util_upack2` - - :ref:`here ` + - :ref:`util_upack2` * - UTIL_ADXCVR for AMD - :git-hdl:`library/xilinx/util_adxcvr` - - :ref:`here ` + - :ref:`util_adxcvr` * - AXI_ADXCVR for Intel - :git-hdl:`library/intel/axi_adxcvr` - - :ref:`here ` + - :ref:`axi_adxcvr intel` * - AXI_ADXCVR for AMD - :git-hdl:`library/xilinx/axi_adxcvr` - - :ref:`here ` + - :ref:`axi_adxcvr amd` * - AXI_JESD204_RX - :git-hdl:`library/jesd204/axi_jesd204_rx` - :ref:`axi_jesd204_rx` From 89fffd409073d7e6110645e42b768adaebfecb24 Mon Sep 17 00:00:00 2001 From: Iulia Moldovan Date: Tue, 19 Nov 2024 09:29:54 +0200 Subject: [PATCH 09/10] docs/projects: Replace links with roles Signed-off-by: Iulia Moldovan --- docs/projects/ad4170_asdz/index.rst | 2 +- docs/projects/ad57xx_ardz/index.rst | 4 ++-- docs/projects/adrv9026/index.rst | 4 +--- docs/projects/cn0540/index.rst | 14 +++++++------- docs/projects/cn0561/index.rst | 11 ++++++----- docs/projects/cn0579/index.rst | 10 +++++----- docs/projects/pulsar_adc/index.rst | 2 +- 7 files changed, 23 insertions(+), 24 deletions(-) diff --git a/docs/projects/ad4170_asdz/index.rst b/docs/projects/ad4170_asdz/index.rst index 1f3bdb5a1b..9297745e44 100644 --- a/docs/projects/ad4170_asdz/index.rst +++ b/docs/projects/ad4170_asdz/index.rst @@ -40,7 +40,7 @@ Supported devices Supported carriers ------------------------------------------------------------------------------- -- :xilinx:`Cora Z7-07S ` Arduino shield connector +- :xilinx:`Cora Z7S ` Arduino shield connector - :intel:`DE10-Nano ` Arduino shield connector Block design diff --git a/docs/projects/ad57xx_ardz/index.rst b/docs/projects/ad57xx_ardz/index.rst index 64a8805cc8..7b959d1850 100644 --- a/docs/projects/ad57xx_ardz/index.rst +++ b/docs/projects/ad57xx_ardz/index.rst @@ -49,7 +49,7 @@ Supported devices Supported carriers ------------------------------------------------------------------------------- -- :xilinx:`Cora Z7-07S ` +- :xilinx:`Cora Z7S ` Arduino shield connector - :intel:`DE10-Nano ` Arduino shield connector @@ -73,7 +73,7 @@ The data path and clock domains are depicted in the below diagrams: :width: 800 :align: center - AD5780-ARDZ HDL design block diagram for the Cora Z7-07S + AD5780-ARDZ HDL design block diagram for the Cora Z7S CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/projects/adrv9026/index.rst b/docs/projects/adrv9026/index.rst index a418243079..760d5322c1 100644 --- a/docs/projects/adrv9026/index.rst +++ b/docs/projects/adrv9026/index.rst @@ -28,7 +28,7 @@ Supported carriers - Carrier - FMC slot * - :adi:`ADRV9026/ADRV9029 ` - - A10SoC`_ + - :intel:`A10SoC ` - FMCA * - - :xilinx:`ZCU102` @@ -542,5 +542,3 @@ Software related .. include:: ../common/more_information.rst .. include:: ../common/support.rst - -.. _A10SoC: https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/arria/10-sx.html diff --git a/docs/projects/cn0540/index.rst b/docs/projects/cn0540/index.rst index ac99b0a383..cbc96bcd90 100644 --- a/docs/projects/cn0540/index.rst +++ b/docs/projects/cn0540/index.rst @@ -43,8 +43,8 @@ Supported devices Supported carriers ------------------------------------------------------------------------------- -- :xilinx:`Cora Z7-07S ` Arduino shield connector -- :intel:`De10-Nano ` Arduino shield connector +- :xilinx:`Cora Z7S ` Arduino shield connector +- :intel:`DE10-Nano ` Arduino shield connector Block design ------------------------------------------------------------------------------- @@ -92,7 +92,7 @@ axi_spi_engine_0** 0x0003_0000 :class: note - ``*`` instantiated only for Cora Z7S - - ``**`` instantiated only for De10-Nano + - ``**`` instantiated only for DE10-Nano I2C connections ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -189,7 +189,7 @@ The Software GPIO number is calculated as follows: - 32 - 86 -- De10-Nano: the offset is 32 +- DE10-Nano: the offset is 32 .. list-table:: :widths: 25 25 25 25 @@ -202,7 +202,7 @@ The Software GPIO number is calculated as follows: * - - (from FPGA view) - - - De10-Nano + - DE10-Nano * - ltc2308_cs - OUT - 41 @@ -254,7 +254,7 @@ spi_cn0540 11 55 87 =================== === ========== =========== ================ === =============== ================ -Instance name HDL Linux De10-Nano Actual De10-Nano +Instance name HDL Linux DE10-Nano Actual DE10-Nano ================ === =============== ================ axi_spi_engine_0 5 45 77 axi_dmac_0 4 44 76 @@ -349,7 +349,7 @@ HDL related :class: note - ``*`` instantiated only for Cora Z7S - - ``**`` instantiated only for De10-Nano + - ``**`` instantiated only for DE10-Nano - :ref:`SPI Engine Framework documentation ` diff --git a/docs/projects/cn0561/index.rst b/docs/projects/cn0561/index.rst index f7a68220c5..63380ada6e 100644 --- a/docs/projects/cn0561/index.rst +++ b/docs/projects/cn0561/index.rst @@ -31,7 +31,7 @@ The HDL reference design for the EVAL-CN0561 provides all the interfaces that are necessary to interact with the device using a Xilinx FPGA development board; to acquire data from the ADC device, supporting continuous data capture at maximum 1.5 MSPS data rate. However, due to a hardware limitation, -the Cora-Z7s variant will only support a maximum data clock of 24MHz, +the Cora Z7S variant will only support a maximum data clock of 24MHz, in contrast with 50MHz supported on the Zedboard. Supported boards @@ -48,8 +48,9 @@ Supported carriers ------------------------------------------------------------------------------- - :xilinx:`ZedBoard ` on FMC slot -- `Cora Z7-07S `_ on Arduino type headers -- `DE10-Nano `__ on Arduino type headers +- :xilinx:`Cora Z7S ` on Arduino type headers +- :intel:`DE10-Nano ` + on Arduino type headers Block design ------------------------------------------------------------------------------- @@ -66,12 +67,12 @@ The data path and clock domains are depicted in the below diagrams: .. image:: cn0561_hdl.svg :width: 800 :align: center - :alt: CN0561/ZED/Cora Z7-07S block diagram * + :alt: CN0561/ZED/Cora Z7S block diagram * .. admonition:: Legend :class: note - ``*`` The block design for Cora Z7-07S remains the same, the only + ``*`` The block design for Cora Z7S remains the same, the only difference is the data clock frequency of 24MHz. Jumper setup diff --git a/docs/projects/cn0579/index.rst b/docs/projects/cn0579/index.rst index 8633882ad0..2ecd91c158 100644 --- a/docs/projects/cn0579/index.rst +++ b/docs/projects/cn0579/index.rst @@ -43,7 +43,7 @@ Supported carriers - Carrier - FMC slot * - :adi:`CN0579` - - :xilinx:`Cora Z7-07S ` + - :xilinx:`Cora Z7S ` - Arduino headers * - - :intel:`DE10-Nano ` @@ -87,7 +87,7 @@ axi_iic_dac* 0x44A4_0000 --- .. admonition:: Legend :class: note - ``*`` instantiated only for Cora Z7-07S + ``*`` instantiated only for Cora Z7S I2C connections ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -115,7 +115,7 @@ I2C connections .. admonition:: Legend :class: note - - ``*`` only for Cora Z7-07S + - ``*`` only for Cora Z7S - ``**`` only for DE10-Nano SPI connections @@ -141,7 +141,7 @@ SPI connections .. admonition:: Legend :class: note - - ``*`` only for Cora Z7-07S + - ``*`` only for Cora Z7S - ``**`` only for DE10-Nano GPIOs @@ -183,7 +183,7 @@ cn0579_dma** 5 --- --- 45 77 .. admonition:: Legend :class: note - - ``*`` only for Cora Z7-07S + - ``*`` only for Cora Z7S - ``**`` only for DE10-Nano Building the HDL project diff --git a/docs/projects/pulsar_adc/index.rst b/docs/projects/pulsar_adc/index.rst index 9bc032cf48..d63ee05b43 100644 --- a/docs/projects/pulsar_adc/index.rst +++ b/docs/projects/pulsar_adc/index.rst @@ -124,7 +124,7 @@ PulSAR with FMC connector: Supported carriers ------------------------------------------------------------------------------- -- :xilinx:`Cora Z7-07S ` PMOD connector +- :xilinx:`Cora Z7S ` PMOD connector - :xilinx:`ZedBoard ` on FMC slot Other required hardware From 7adbfb45ec7edffb02f9f01fc4a8c0eca5af7045 Mon Sep 17 00:00:00 2001 From: Iulia Moldovan Date: Tue, 19 Nov 2024 12:45:29 +0200 Subject: [PATCH 10/10] docs: Replaced code-block with shell directive where needed Signed-off-by: Iulia Moldovan --- docs/projects/ad3552r_evb/index.rst | 7 +- docs/projects/ad408x_fmc_evb/index.rst | 7 +- docs/projects/ad4110/index.rst | 12 +- docs/projects/ad411x_ad717x/index.rst | 7 +- docs/projects/ad4134_fmc/index.rst | 7 +- docs/projects/ad4170_asdz/index.rst | 14 +- docs/projects/ad4630_fmc/index.rst | 7 +- docs/projects/ad469x_evb/index.rst | 14 +- docs/projects/ad485x_fmcz/index.rst | 6 +- docs/projects/ad5758_sdz/index.rst | 32 ++- docs/projects/ad5766_sdz/index.rst | 9 +- docs/projects/ad57xx_ardz/index.rst | 58 +++--- docs/projects/ad7124_asdz/index.rst | 18 +- docs/projects/ad7134_fmc/index.rst | 9 +- docs/projects/ad719x_asdz/index.rst | 14 +- docs/projects/ad738x_fmc/index.rst | 15 +- docs/projects/ad7405_fmc/index.rst | 50 +++-- docs/projects/ad7606x_fmc/index.rst | 14 +- docs/projects/ad7616_sdz/index.rst | 15 +- docs/projects/ad77681evb/index.rst | 35 ++-- docs/projects/ad7768evb/index.rst | 7 +- docs/projects/ad777x_ardz/index.rst | 64 +++--- docs/projects/ad9081_fmca_ebz/index.rst | 51 +++-- .../projects/ad9081_fmca_ebz_x_band/index.rst | 183 +++++++++--------- docs/projects/ad9213_evb/index.rst | 41 ++-- docs/projects/ad9265_fmc/index.rst | 16 +- docs/projects/ad9434_fmc/index.rst | 14 +- docs/projects/ad9467_fmc/index.rst | 50 +++-- docs/projects/ad9656_fmc/index.rst | 42 ++-- docs/projects/ad9695_fmc/index.rst | 31 +-- docs/projects/ad9739a_fmc/index.rst | 63 +++--- docs/projects/ad9783_ebz/index.rst | 38 ++-- docs/projects/ad_gmsl2eth_sl/index.rst | 73 ++++--- docs/projects/adaq7980_sdz/index.rst | 7 +- docs/projects/adaq8092_fmc/index.rst | 37 ++-- docs/projects/adrv9026/index.rst | 15 +- docs/projects/adrv904x/index.rst | 69 ++++--- docs/projects/adv7511/index.rst | 61 +++--- docs/projects/adv7513/index.rst | 4 +- docs/projects/cn0363/index.rst | 7 +- docs/projects/cn0506/index.rst | 107 +++++----- docs/projects/cn0540/index.rst | 39 ++-- docs/projects/cn0561/index.rst | 6 +- docs/projects/cn0577/index.rst | 79 ++++---- docs/projects/cn0579/index.rst | 62 +++--- docs/projects/cn0585/index.rst | 49 +++-- docs/projects/max96724/index.rst | 43 ++-- docs/projects/pulsar_adc/index.rst | 183 +++++++++--------- docs/projects/pulsar_lvds/index.rst | 77 ++++---- docs/user_guide/architecture.rst | 7 +- 50 files changed, 902 insertions(+), 973 deletions(-) diff --git a/docs/projects/ad3552r_evb/index.rst b/docs/projects/ad3552r_evb/index.rst index 8bfb40edf7..c46f14c825 100644 --- a/docs/projects/ad3552r_evb/index.rst +++ b/docs/projects/ad3552r_evb/index.rst @@ -148,11 +148,10 @@ the HDL repository, and then build the project as follows: **Linux/Cygwin/WSL** -.. code-block:: - :linenos: +.. shell:: - user@analog:~$ cd hdl/projects/ad3552r_evb/zed - user@analog:~/hdl/projects/ad3552r_evb/zed$ make + $cd hdl/projects/ad3552r_evb/zed + $make A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. diff --git a/docs/projects/ad408x_fmc_evb/index.rst b/docs/projects/ad408x_fmc_evb/index.rst index 36dfcfa5bd..a52cc50024 100644 --- a/docs/projects/ad408x_fmc_evb/index.rst +++ b/docs/projects/ad408x_fmc_evb/index.rst @@ -180,11 +180,10 @@ the HDL repository, and then build the project as follows: **Linux/Cygwin/WSL** -.. code-block:: - :linenos: +.. shell:: - user@analog:~$ cd hdl/projects/ad408x_fmc_evb/zed - user@analog:~/hdl/projects/ad408x_fmc_evb/zed$ make + $cd hdl/projects/ad408x_fmc_evb/zed + $make A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. diff --git a/docs/projects/ad4110/index.rst b/docs/projects/ad4110/index.rst index 63e5c2b1a3..cdac73eef3 100644 --- a/docs/projects/ad4110/index.rst +++ b/docs/projects/ad4110/index.rst @@ -138,18 +138,16 @@ ADI distributes the bit/elf files of these projects as part of the If you want to build the sources, ADI makes them available on the :git-hdl:`HDL repository `. To get the source you must `clone `__ -the HDL repository, and then build the project as follows:. +the HDL repository, and then build the project as follows: **Linux/Cygwin/WSL** -.. code-block:: - :linenos: +.. shell:: - user@analog:~$ cd hdl/projects/ad4110/zed - user@analog:~/hdl/projects/ad4110/zed$ make + $cd hdl/projects/ad4110/zed + $make -A more comprehensive build guide can be found in the :ref:`build_hdl` -user guide. +A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. Resources ------------------------------------------------------------------------------- diff --git a/docs/projects/ad411x_ad717x/index.rst b/docs/projects/ad411x_ad717x/index.rst index 39adfe1af5..300ab04b18 100644 --- a/docs/projects/ad411x_ad717x/index.rst +++ b/docs/projects/ad411x_ad717x/index.rst @@ -192,11 +192,10 @@ the HDL repository, and then build the project as follows: **Linux/Cygwin/WSL** -.. code-block:: - :linenos: +.. shell:: - user@analog:~$ cd hdl/projects/ad411x_ad717x/de10nano - user@analog:~/hdl/projects/ad411x_ad717x/de10nano$ make + $cd hdl/projects/ad411x_ad717x/de10nano + $make A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. diff --git a/docs/projects/ad4134_fmc/index.rst b/docs/projects/ad4134_fmc/index.rst index 57a41c9bbb..7b65f397e6 100644 --- a/docs/projects/ad4134_fmc/index.rst +++ b/docs/projects/ad4134_fmc/index.rst @@ -177,11 +177,10 @@ the HDL repository, and then build the project as follows:. **Linux/Cygwin/WSL** -.. code-block:: - :linenos: +.. shell:: - user@analog:~$ cd hdl/projects/ad4134_fmc/zed - user@analog:~/hdl/projects/ad4134_fmc/zed$ make + $cd hdl/projects/ad4134_fmc/zed + $make A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. diff --git a/docs/projects/ad4170_asdz/index.rst b/docs/projects/ad4170_asdz/index.rst index 9297745e44..5db8981d2e 100644 --- a/docs/projects/ad4170_asdz/index.rst +++ b/docs/projects/ad4170_asdz/index.rst @@ -208,17 +208,15 @@ the HDL repository, and then build the project as follows: **Linux/Cygwin/WSL** -.. code-block:: - :linenos: +.. shell:: - user@analog:~$ cd hdl/projects/ad4170_asdz/coraz7s - user@analog:~/hdl/projects/ad4170_asdz/coraz7s$ make + $cd hdl/projects/ad4170_asdz/coraz7s + $make -.. code-block:: - :linenos: +.. shell:: - user@analog:~$ cd hdl/projects/ad4170_asdz/de10nano - user@analog:~/hdl/projects/ad4170_asdz/de10nano$ make + $cd hdl/projects/ad4170_asdz/de10nano + $make A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. diff --git a/docs/projects/ad4630_fmc/index.rst b/docs/projects/ad4630_fmc/index.rst index 4b7a28aad7..6a98533812 100644 --- a/docs/projects/ad4630_fmc/index.rst +++ b/docs/projects/ad4630_fmc/index.rst @@ -332,11 +332,10 @@ the HDL repository, and then build the project as follows:. **Linux/Cygwin/WSL** -.. code-block:: - :linenos: +.. shell:: - user@analog:~$ cd hdl/projects/ad4630_fmc/zed - user@analog:~/hdl/projects/ad4630_fmc/zed$ make NUM_OF_SDI=4 CAPTURE_ZONE=2 + $cd hdl/projects/ad4630_fmc/zed + $make NUM_OF_SDI=4 CAPTURE_ZONE=2 The result of the build, if parameters were used, will be in a folder named by the configuration used: diff --git a/docs/projects/ad469x_evb/index.rst b/docs/projects/ad469x_evb/index.rst index 913178355d..6685044593 100644 --- a/docs/projects/ad469x_evb/index.rst +++ b/docs/projects/ad469x_evb/index.rst @@ -107,15 +107,15 @@ modifications need to be done on the board and/or ``make`` command: In case we link CNV signal to PWM: -.. code-block:: +.. shell:: bash - make SPI_4WIRE=0 + $make SPI_4WIRE=0 In case we link CNV signal to SPI_CS: -.. code-block:: +.. shell:: bash - make SPI_4WIRE=1 + $make SPI_4WIRE=1 CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -282,10 +282,10 @@ the HDL repository, and then build the project as follows: **Linux/Cygwin/WSL** -.. code-block:: +.. shell:: - user@analog:~$ cd hdl/projects/ad469x_evb/zed - user@analog:~/hdl/projects/ad469x_evb/zed$ make SPI_4WIRE=0 + $cd hdl/projects/ad469x_evb/zed + $make SPI_4WIRE=0 The result of the build, if parameters were used, will be in a folder named by the configuration used: diff --git a/docs/projects/ad485x_fmcz/index.rst b/docs/projects/ad485x_fmcz/index.rst index cfda3568f3..67c6b33922 100644 --- a/docs/projects/ad485x_fmcz/index.rst +++ b/docs/projects/ad485x_fmcz/index.rst @@ -179,10 +179,10 @@ make command by typing in your command prompt (this example is for **Linux/Cygwin/WSL** -.. code-block:: +.. shell:: - user@analog:~$ cd hdl/projects/ad485x_fmc/zed - user@analog:~$ make + $cd hdl/projects/ad485x_fmc/zed + $make A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. diff --git a/docs/projects/ad5758_sdz/index.rst b/docs/projects/ad5758_sdz/index.rst index c2f885c53b..7fc0e20dcc 100644 --- a/docs/projects/ad5758_sdz/index.rst +++ b/docs/projects/ad5758_sdz/index.rst @@ -34,22 +34,22 @@ Applications: Supported boards ------------------------------------------------------------------------------- -- :adi:`EVAL-AD5758 ` +- :adi:`EVAL-AD5758` Supported devices ------------------------------------------------------------------------------- -- :adi:`AD5758` +- :adi:`AD5758` Supported carriers ------------------------------------------------------------------------------- -- :xilinx:`ZedBoard ` on FMC slot +- :xilinx:`ZedBoard ` on FMC slot Other required hardware ------------------------------------------------------------------------------- -- :adi:`SDP-S` +- :adi:`SDP-S` Block design ------------------------------------------------------------------------------- @@ -106,7 +106,7 @@ GPIOs The Software GPIO number is calculated as follows: -- Zynq-7000: if PS7 is used, then the offset is 54 +- Zynq-7000: if PS7 is used, then the offset is 54 .. list-table:: :widths: 25 25 25 25 @@ -146,14 +146,12 @@ the HDL repository, and then build the project as follows:. **Linux/Cygwin/WSL** -.. code-block:: - :linenos: +.. shell:: - user@analog:~$ cd hdl/projects/ad5758_sdz/zed - user@analog:~/hdl/projects/ad5758_sdz/zed$ make + $cd hdl/projects/ad5758_sdz/zed + $make -A more comprehensive build guide can be found in the :ref:`build_hdl` -user guide. +A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. Resources ------------------------------------------------------------------------------- @@ -161,13 +159,13 @@ Resources Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheet: :adi:`AD5758` -- :adi:`UG-1268: EVAL-AD5758 Board User Guide ` +- Product datasheet: :adi:`AD5758` +- :adi:`UG-1268: EVAL-AD5758 Board User Guide ` HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`AD5758-SDZ HDL project source code ` +- :git-hdl:`AD5758-SDZ HDL project source code ` .. list-table:: :widths: 30 35 35 @@ -213,9 +211,9 @@ Linux support: No-OS support: -- :git-no-os:`AD5758-SDZ No-OS project source code ` -- :git-no-os:`AD5758 No-OS Driver source code ` -- :dokuwiki:`AD5758 No-OS Driver documentation ` +- :git-no-os:`AD5758-SDZ No-OS project source code ` +- :git-no-os:`AD5758 No-OS Driver source code ` +- :dokuwiki:`AD5758 No-OS Driver documentation ` .. include:: ../common/more_information.rst diff --git a/docs/projects/ad5766_sdz/index.rst b/docs/projects/ad5766_sdz/index.rst index 3f4eeb6909..a2f8bf7d7e 100644 --- a/docs/projects/ad5766_sdz/index.rst +++ b/docs/projects/ad5766_sdz/index.rst @@ -192,11 +192,10 @@ the HDL repository, and then build the project as follows: **Linux/Cygwin/WSL** -.. code-block:: - :linenos: +.. shell:: - user@analog:~$ cd hdl/projects/ad5766_sdz/zed - user@analog:~/hdl/projects/ad5766_sdz/zed$ make + $cd hdl/projects/ad5766_sdz/zed + $make A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. @@ -261,7 +260,7 @@ HDL related - :git-hdl:`library/util_i2c_mixer` - --- -- :ref:`SPI Engine Framework documentation ` +- :ref:`SPI Engine Framework documentation ` Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/projects/ad57xx_ardz/index.rst b/docs/projects/ad57xx_ardz/index.rst index 7b959d1850..d7ba505fcd 100644 --- a/docs/projects/ad57xx_ardz/index.rst +++ b/docs/projects/ad57xx_ardz/index.rst @@ -33,25 +33,25 @@ maximum sample rate. Supported boards ------------------------------------------------------------------------------- -- :adi:`EVAL-AD5780ARDZ` -- :adi:`EVAL-AD5781ARDZ` -- :adi:`EVAL-AD5791ARDZ` +- :adi:`EVAL-AD5780ARDZ` +- :adi:`EVAL-AD5781ARDZ` +- :adi:`EVAL-AD5791ARDZ` Supported devices ------------------------------------------------------------------------------- -- :adi:`AD5760` -- :adi:`AD5780` -- :adi:`AD5781` -- :adi:`AD5790` -- :adi:`AD5791` +- :adi:`AD5760` +- :adi:`AD5780` +- :adi:`AD5781` +- :adi:`AD5790` +- :adi:`AD5791` Supported carriers ------------------------------------------------------------------------------- -- :xilinx:`Cora Z7S ` +- :xilinx:`Cora Z7S ` Arduino shield connector -- :intel:`DE10-Nano ` +- :intel:`DE10-Nano ` Arduino shield connector Block design @@ -97,8 +97,8 @@ spi_clk_pll_reconfig** 0x0006_0000 .. admonition:: Legend :class: note - - ``*`` instantiated only for Cora Z7S - - ``**`` instantiated only for DE10-Nano + - ``*`` instantiated only for Cora Z7S + - ``**`` instantiated only for DE10-Nano I2C connections ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -126,8 +126,8 @@ I2C connections .. admonition:: Legend :class: note - - ``*`` instantiated only for Cora Z7S - - ``**`` instantiated only for DE10-Nano + - ``*`` instantiated only for Cora Z7S + - ``**`` instantiated only for DE10-Nano SPI connections ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -150,7 +150,7 @@ GPIOs The Software GPIO number is calculated as follows: -- Cora Z7S: the offset is 54 +- Cora Z7S: the offset is 54 .. list-table:: :widths: 25 25 25 25 @@ -177,7 +177,7 @@ The Software GPIO number is calculated as follows: - 32 - 86 -- DE10-Nano: the offset is 32 +- DE10-Nano: the offset is 32 .. list-table:: :widths: 25 25 25 25 @@ -236,17 +236,15 @@ the HDL repository, and then build the project as follows: **Linux/Cygwin/WSL** -.. code-block:: - :linenos: +.. shell:: - user@analog:~$ cd hdl/projects/ad57xx_ardz/coraz7s - user@analog:~/hdl/projects/ad57xx_ardz/coraz7s$ make + $cd hdl/projects/ad57xx_ardz/coraz7s + $make -.. code-block:: - :linenos: +.. shell:: - user@analog:~$ cd hdl/projects/ad57xx_ardz/de10nano - user@analog:~/hdl/projects/ad57xx_ardz/de10nano$ make + $cd hdl/projects/ad57xx_ardz/de10nano + $make A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. @@ -267,7 +265,7 @@ Hardware related HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`AD57XX_ARDZ HDL project source code ` +- :git-hdl:`AD57XX_ARDZ HDL project source code ` .. list-table:: :widths: 30 40 30 @@ -310,15 +308,15 @@ HDL related .. admonition:: Legend :class: note - - ``*`` instantiated only for Cora Z7S - - ``**`` instantiated only for DE10-Nano + - ``*`` instantiated only for Cora Z7S + - ``**`` instantiated only for DE10-Nano -- :ref:`SPI Engine Framework documentation ` +- :ref:`SPI Engine Framework documentation ` Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -.. - - :git-linux:`AD57XX Linux driver ad57xx.c ` + +- :git-linux:`AD57XX Linux driver ad57xx.c ` .. include:: ../common/more_information.rst diff --git a/docs/projects/ad7124_asdz/index.rst b/docs/projects/ad7124_asdz/index.rst index 8746da65d2..bc62448ca1 100644 --- a/docs/projects/ad7124_asdz/index.rst +++ b/docs/projects/ad7124_asdz/index.rst @@ -22,19 +22,19 @@ samples at the maximum sample rate. Supported boards ------------------------------------------------------------------------------- -- :adi:`EVAL-AD7124-4` -- :adi:`EVAL-AD7124-8` +- :adi:`EVAL-AD7124-4` +- :adi:`EVAL-AD7124-8` Supported devices ------------------------------------------------------------------------------- -- :adi:`AD7124-4` -- :adi:`AD7124-8` +- :adi:`AD7124-4` +- :adi:`AD7124-8` Supported carriers ------------------------------------------------------------------------------- -- :intel:`DE10-Nano ` Arduino shield connector +- :intel:`DE10-Nano ` Arduino shield connector Block design ------------------------------------------------------------------------------- @@ -88,7 +88,7 @@ GPIOs The Software GPIO number is calculated as follows: -- DE10-Nano: the offset is 32 +- DE10-Nano: the offset is 32 .. list-table:: :widths: 25 25 25 25 @@ -120,10 +120,10 @@ the HDL repository, and then build the project as follows: **Linux/Cygwin/WSL** -.. code-block:: +.. shell:: - user@analog:~$ cd hdl/projects/ad7124_asdz/de10nano - user@analog:~/hdl/projects/ad7124_asdz/de10nano make + $cd hdl/projects/ad7124_asdz/de10nano + $make A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. diff --git a/docs/projects/ad7134_fmc/index.rst b/docs/projects/ad7134_fmc/index.rst index bc9f9d9d48..501d4510d9 100644 --- a/docs/projects/ad7134_fmc/index.rst +++ b/docs/projects/ad7134_fmc/index.rst @@ -219,11 +219,10 @@ the HDL repository, and then build the project as follows:. **Linux/Cygwin/WSL** -.. code-block:: - :linenos: +.. shell:: - user@analog:~$ cd hdl/projects/ad7134_fmc/zed - user@analog:~/hdl/projects/ad7134_fmc/zed$ make + $cd hdl/projects/ad7134_fmc/zed + $make A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. @@ -296,9 +295,7 @@ Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - :git-no-os:`AD7134-FMC No-OS project source code ` - - :git-no-os:`AD4134/AD7134 No-OS Driver source code ` - - :dokuwiki:`AD4134/AD7134 No-OS Driver documentation ` .. include:: ../common/more_information.rst diff --git a/docs/projects/ad719x_asdz/index.rst b/docs/projects/ad719x_asdz/index.rst index ebb07f39f1..f36bbebfff 100644 --- a/docs/projects/ad719x_asdz/index.rst +++ b/docs/projects/ad719x_asdz/index.rst @@ -153,10 +153,8 @@ connected to Cora Z7S through PMOD JA: .. shell:: - $ cd hdl/projects/ad719x_asdz/coraz7s - $ make - # or explicitly setting the variable to 0, which is the same - $ make ARDZ_PMOD_N=0 + $cd hdl/projects/ad719x_asdz/coraz7s + $make The other possible way to connect the supported boards to CoraZ7S, is through the Arduino header, for which the project needs to be built with the parameter @@ -166,8 +164,8 @@ The built project will be located at hdl/projects/ad719x_asdz/coraz7s/**ARDZPMOD .. shell:: - $ cd hdl/projects/ad719x_asdz/coraz7s - $ make ARDZ_PMOD_N=1 + $cd hdl/projects/ad719x_asdz/coraz7s + $make ARDZ_PMOD_N=1 DE10-Nano ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -179,8 +177,8 @@ is not parameterizable: .. shell:: - $ cd hdl/projects/ad719x_asdz/de10nano - $ make + $cd hdl/projects/ad719x_asdz/de10nano + $make A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. diff --git a/docs/projects/ad738x_fmc/index.rst b/docs/projects/ad738x_fmc/index.rst index b1b0139bd2..c69206b076 100644 --- a/docs/projects/ad738x_fmc/index.rst +++ b/docs/projects/ad738x_fmc/index.rst @@ -103,15 +103,15 @@ be done on the board and/or ``make`` command: In case of the **Serial Data Output Pin** functionality: -.. code-block:: +.. shell:: bash - make ALERT_SPI_N=0 + $make ALERT_SPI_N=0 In case of the **Alert Indication Output Pin** functionality: -.. code-block:: +.. shell:: bash - make ALERT_SPI_N=1 + $make ALERT_SPI_N=1 The **NUM_OF_SDI** configuration parameter defines the number of SDI lines used: **{1, 2, 4}**. By default is set to 1. @@ -262,11 +262,10 @@ the HDL repository, and then build the project as follows: **Linux/Cygwin/WSL** -.. code-block:: - :linenos: +.. shell:: - user@analog:~$ cd hdl/projects/ad738x_fmc/zed - user@analog:~/hdl/projects/ad738x_fmc/zed$ make ALERT_SPI_N=0 NUM_OF_SDI=4 + $cd hdl/projects/ad738x_fmc/zed + $make ALERT_SPI_N=0 NUM_OF_SDI=4 The result of the build, if parameters were used, will be in a folder named by the configuration used: diff --git a/docs/projects/ad7405_fmc/index.rst b/docs/projects/ad7405_fmc/index.rst index 464b1b9859..9fc47e293d 100644 --- a/docs/projects/ad7405_fmc/index.rst +++ b/docs/projects/ad7405_fmc/index.rst @@ -19,16 +19,16 @@ single-ended, and for :adi:`AD7405` is differential. Supported boards ------------------------------------------------------------------------------- -- :adi:`EVAL-AD7405` -- :adi:`EVAL-AD7403` -- :adi:`EVAL-ADuM7701` +- :adi:`EVAL-AD7405` +- :adi:`EVAL-AD7403` +- :adi:`EVAL-ADuM7701` Supported devices ------------------------------------------------------------------------------- -- :adi:`AD7405` -- :adi:`AD7403` -- :adi:`ADuM7701` +- :adi:`AD7405` +- :adi:`AD7403` +- :adi:`ADuM7701` Supported carriers ------------------------------------------------------------------------------- @@ -77,10 +77,10 @@ Block design for the single-ended signals (:adi:`ADuM7701` and :adi:`AD7403`) Configuration modes ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- LVDS_CMOS_N: specific to the type of the data and clock signals +- LVDS_CMOS_N: specific to the type of the data and clock signals - - 0 - Single-ended data and clock signals (default) - - 1 - Differential data and clock signals + - 0 - Single-ended data and clock signals (default) + - 1 - Differential data and clock signals CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -147,19 +147,17 @@ the HDL repository. Default (Single-ended data and clock signals): -.. code-block:: - :linenos: +.. shell:: - user@analog:~$ cd hdl/projects/ad7405/zed - user@analog:~/hdl/projects/ad7405/zed$ make + $cd hdl/projects/ad7405/zed + $make If differential data and clock signals are desired: -.. code-block:: - :linenos: +.. shell:: - user@analog:~$ cd hdl/projects/ad7405/zed - user@analog:~/hdl/projects/ad7405/zed$ make LVDS_CMOS_N=1 + $cd hdl/projects/ad7405/zed + $make LVDS_CMOS_N=1 A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. @@ -169,25 +167,25 @@ Resources Systems related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :dokuwiki:`[Wiki] ADuM7701 - Reference Design ` +- :dokuwiki:`[Wiki] ADuM7701 - Reference Design ` Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheets: +- Product datasheets: - - :adi:`AD7405` - - :adi:`AD7403` - - :adi:`ADuM7701` + - :adi:`AD7405` + - :adi:`AD7403` + - :adi:`ADuM7701` -- `UG-690, EVAL-AD7405FMCZ User Guide `__ -- `UG-683, EVAL-AD7403FMCZ User Guide `__ -- `UG-1525, EV-ADuM7701-8FMCZ User Guide `__ +- `UG-690, EVAL-AD7405FMCZ User Guide `__ +- `UG-683, EVAL-AD7403FMCZ User Guide `__ +- `UG-1525, EV-ADuM7701-8FMCZ User Guide `__ HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`AD7405-FMC HDL project source code ` +- :git-hdl:`AD7405-FMC HDL project source code ` .. list-table:: :widths: 30 35 35 diff --git a/docs/projects/ad7606x_fmc/index.rst b/docs/projects/ad7606x_fmc/index.rst index 606b0b05ec..134a3406da 100644 --- a/docs/projects/ad7606x_fmc/index.rst +++ b/docs/projects/ad7606x_fmc/index.rst @@ -107,15 +107,15 @@ hardware modifications need to be done on the board and/or ``make`` command: In case of the **PARALLEL** interface: -.. code-block:: +.. shell:: bash - make INTF=0 + $make INTF=0 In case of the **SERIAL** interface: -.. code-block:: +.. shell:: bash - make INTF=1 + $make INTF=1 .. note:: @@ -305,10 +305,10 @@ the HDL repository, and then build the project as follows:. **Linux/Cygwin/WSL** -.. code-block:: +.. shell:: - user@analog:~$ cd hdl/projects/ad7606x_fmc/zed - user@analog:~/hdl/projects/ad7606x_fmc/zed$ make DEV_CONFIG=2 INTF=0 + $cd hdl/projects/ad7606x_fmc/zed + $make INTF=0 ADC_N_BITS=16 The result of the build, if parameters were used, will be in a folder named by the configuration used: diff --git a/docs/projects/ad7616_sdz/index.rst b/docs/projects/ad7616_sdz/index.rst index a61a39a62a..f8510b964b 100644 --- a/docs/projects/ad7616_sdz/index.rst +++ b/docs/projects/ad7616_sdz/index.rst @@ -84,15 +84,15 @@ some hardware modifications need to be done on the board and/or make command: In case of the **PARALLEL** interface: -.. code-block:: +.. shell:: bash - make SER_PAR_N=0 + $make SER_PAR_N=0 In case of the **SERIAL** interface: -.. code-block:: +.. shell:: bash - make SER_PAR_N=1 + $make SER_PAR_N=1 .. note:: @@ -265,11 +265,10 @@ the HDL repository, and then build the project as follows:. **Linux/Cygwin/WSL** -.. code-block:: - :linenos: +.. shell:: - user@analog:~$ cd hdl/projects/ad7616_sdz/zed - user@analog:~/hdl/projects/ad7616_sdz/zed$ make SER_PAR_N=0 + $cd hdl/projects/ad7616_sdz/zed + $make SER_PAR_N=0 The result of the build, if parameters were used, will be in a folder named by the configuration used: diff --git a/docs/projects/ad77681evb/index.rst b/docs/projects/ad77681evb/index.rst index 3785b6ae46..b39f0295c0 100644 --- a/docs/projects/ad77681evb/index.rst +++ b/docs/projects/ad77681evb/index.rst @@ -32,19 +32,19 @@ signal processor (DSP). Supported boards ------------------------------------------------------------------------------- -- :adi:`EVAL-AD7768-1` -- :adi:`EVAL-ADAQ7768-1` +- :adi:`EVAL-AD7768-1` +- :adi:`EVAL-ADAQ7768-1` Supported devices ------------------------------------------------------------------------------- -- :adi:`AD7768-1` -- :adi:`ADAQ7768-1` +- :adi:`AD7768-1` +- :adi:`ADAQ7768-1` Supported carriers ------------------------------------------------------------------------------- -- :xilinx:`ZedBoard ` on FMC slot +- :xilinx:`ZedBoard ` on FMC slot Block design ------------------------------------------------------------------------------- @@ -117,7 +117,7 @@ GPIOs The Software GPIO number is calculated as follows: -- Zynq-7000: if PS7 is used, then offset is 54 +- Zynq-7000: if PS7 is used, then offset is 54 .. list-table:: :widths: 25 25 25 25 @@ -173,11 +173,10 @@ the HDL repository, and then build the project as follows: **Linux/Cygwin/WSL** -.. code-block:: - :linenos: +.. shell:: - user@analog:~$ cd hdl/projects/ad77681evb/zed - user@analog:~/hdl/projects/ad77681evb/zed$ make + $cd hdl/projects/ad77681evb/zed + $make A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. @@ -192,16 +191,16 @@ Systems related Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheets: +- Product datasheets: - - :adi:`AD7768-1` - - :adi:`ADAQ7768-1` + - :adi:`AD7768-1` + - :adi:`ADAQ7768-1` HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`ad77681evb HDL project source code ` -- :dokuwiki:`[Wiki] AD7768-1 User Guide ` +- :git-hdl:`ad77681evb HDL project source code ` +- :dokuwiki:`[Wiki] AD7768-1 User Guide ` .. list-table:: :widths: 30 40 30 @@ -247,14 +246,14 @@ HDL related - :git-hdl:`library/util_i2c_mixer` - --- -- :ref:`SPI Engine Framework documentation ` +- :ref:`SPI Engine Framework documentation ` Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - :git-linux:`AD7768-1 Linux driver source code ` -- AD7768-1 Linux device tree :git-linux:`zynq-zed-adv7511-ad7768-1-evb.dts ` -- ADAQ7768-1 Linux device tree :git-linux:`zynq-zed-adv7511-adaq7768-1-evb.dts ` +- AD7768-1 Linux device tree :git-linux:`zynq-zed-adv7511-ad7768-1-evb.dts ` +- ADAQ7768-1 Linux device tree :git-linux:`zynq-zed-adv7511-adaq7768-1-evb.dts ` .. include:: ../common/more_information.rst diff --git a/docs/projects/ad7768evb/index.rst b/docs/projects/ad7768evb/index.rst index 2c07091ce3..15af2f30ef 100644 --- a/docs/projects/ad7768evb/index.rst +++ b/docs/projects/ad7768evb/index.rst @@ -197,11 +197,10 @@ the HDL repository, and then build the project as follows: **Linux/Cygwin/WSL** -.. code-block:: - :linenos: +.. shell:: - user@analog:~$ cd hdl/projects/ad7768evb/zed - user@analog:~/hdl/projects/ad7768evb/zed$ make + $cd hdl/projects/ad7768evb/zed + $make A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. diff --git a/docs/projects/ad777x_ardz/index.rst b/docs/projects/ad777x_ardz/index.rst index f6c4925077..0ec4a81d61 100644 --- a/docs/projects/ad777x_ardz/index.rst +++ b/docs/projects/ad777x_ardz/index.rst @@ -20,14 +20,14 @@ range of the signal chain. Supported boards ------------------------------------------------------------------------------- -- :adi:`EVAL-AD7770/1/9-ARDZ ` +- :adi:`EVAL-AD7770/1/9-ARDZ ` Supported devices ------------------------------------------------------------------------------- -- :adi:`AD7770` -- :adi:`AD7771` -- :adi:`AD7779` +- :adi:`AD7770` +- :adi:`AD7771` +- :adi:`AD7779` Supported carriers ------------------------------------------------------------------------------- @@ -82,12 +82,12 @@ Clock scheme CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -============== =========== -Instance Zynq -============== =========== -axi_ad777x_adc 0x43C0_0000 -ad777x_dma 0x7C48_0000 -============== =========== +============== =========== =========== +Instance Zynq DE10-Nano +============== =========== =========== +axi_ad777x_adc 0x43C0_0000 0x0002_0000 +ad777x_dma 0x7C48_0000 0x0003_0000 +============== =========== =========== SPI connections ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -112,8 +112,8 @@ SPI connections .. admonition:: Legend :class: note - - ``*`` only for ZedBoard - - ``**`` only for DE10-Nano + - ``*`` only for ZedBoard + - ``**`` only for DE10-Nano GPIOs ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -177,17 +177,17 @@ Interrupts ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ================ === ========== =========== =============== ================ -Instance name HDL Linux Zynq Actual Zynq Linux Cyclone V Actual Cyclone V +Instance name HDL Linux Zynq Actual Zynq Linux DE10-Nano Actual DE10-Nano ================ === ========== =========== =============== ================ -ad777x_dma* 10 54 86 - - -ad777x_dma** 5 - - 45 77 +ad777x_dma* 10 54 86 --- --- +ad777x_dma** 5 --- --- 45 77 ================ === ========== =========== =============== ================ .. admonition:: Legend :class: note - - ``*`` only for ZedBoard - - ``**`` only for DE10-Nano + - ``*`` only for ZedBoard + - ``**`` only for DE10-Nano Building the HDL project ------------------------------------------------------------------------------- @@ -202,21 +202,19 @@ the HDL repository. **Linux/Cygwin/WSL** -Make for ZedBoard project: +Building the ZedBoard project: -.. code-block:: - :linenos: +.. shell:: - user@analog:~$ cd hdl/projects/ad777x_ardz/zed - user@analog:~/hdl/projects/ad777x_ardz/zed$ make + $cd hdl/projects/ad777x_ardz/zed + $make -Make for De10Nano project: +Building the DE10-Nano project: -.. code-block:: - :linenos: +.. shell:: - user@analog:~$ cd hdl/projects/ad777x_ardz/de10nano - user@analog:~/hdl/projects/ad777x_ardz/de10nano$ make + $cd hdl/projects/ad777x_ardz/de10nano + $make A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. @@ -226,16 +224,16 @@ Resources Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheets: +- Product datasheets: - - :adi:`AD7770` - - :adi:`AD7771` - - :adi:`AD7779` + - :adi:`AD7770` + - :adi:`AD7771` + - :adi:`AD7779` HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`AD777X-ARDZ HDL project source code ` +- :git-hdl:`AD777X-ARDZ HDL project source code ` .. list-table:: :widths: 30 35 35 @@ -278,7 +276,7 @@ HDL related .. admonition:: Legend :class: note - - ``*`` only for ZedBoard + - ``*`` only for ZedBoard .. include:: ../common/more_information.rst diff --git a/docs/projects/ad9081_fmca_ebz/index.rst b/docs/projects/ad9081_fmca_ebz/index.rst index 677b6e790d..3dd32e5179 100644 --- a/docs/projects/ad9081_fmca_ebz/index.rst +++ b/docs/projects/ad9081_fmca_ebz/index.rst @@ -252,19 +252,19 @@ Example block design for Single link; M=2; L=8; JESD204C The project must be built with the following parameters: - .. code-block:: bash - - make JESD_MODE=64B66B \ - RX_RATE=16.5 \ - TX_RATE=16.5 \ - RX_JESD_M=2 \ - RX_JESD_L=8 \ - RX_JESD_S=2 \ - RX_JESD_NP=16 \ - TX_JESD_M=2 \ - TX_JESD_L=8 \ - TX_JESD_S=4 \ - TX_JESD_NP=8 + .. shell:: bash + + $make JESD_MODE=64B66B \ + $ RX_RATE=16.5 \ + $ TX_RATE=16.5 \ + $ RX_JESD_M=2 \ + $ RX_JESD_L=8 \ + $ RX_JESD_S=2 \ + $ RX_JESD_NP=16 \ + $ TX_JESD_M=2 \ + $ TX_JESD_L=8 \ + $ TX_JESD_S=4 \ + $ TX_JESD_NP=8 The Rx link is operating with the following parameters: @@ -534,27 +534,26 @@ If you want to build the sources, ADI makes them available on the `clone `__ the HDL repository. -Then go to the :git-hdl:`projects/ad9081_fmca_ebz ` -location and run the make command by typing in your command prompt: +Then go to the :git-hdl:`projects/ad9081_fmca_ebz` or +(:git-hdl:`projects/ad9082_fmca_ebz`) +location and run the make command by typing in you command prompt: -**Linux/Cygwin/WSL** +Example for building the project with parameters: -.. code-block:: - :linenos: - :emphasize-lines: 2, 6 +**Linux/Cygwin/WSL** - user@analog:~$ cd hdl/projects/ad9081_fmca_ebz/zcu102 - // these are just examples of how to write the *make* command with parameters - user@analog:~/hdl/projects/ad9081_fmca_ebz/zcu102$ make parameter1=value parameter2=value +.. shell:: - user@analog:~$ cd hdl/projects/ad9081_fmca_ebz/a10soc - // these are just examples of how to write the *make* command with parameters - user@analog:~/hdl/projects/ad9081_fmca_ebz/a10soc$ make RX_LANE_RATE=2.5 TX_LANE_RATE=2.5 RX_JESD_L=8 RX_JESD_M=4 RX_JESD_S=1 RX_JESD_NP=16 TX_JESD_L=8 TX_JESD_M=4 TX_JESD_S=1 TX_JESD_NP=16 + $cd hdl/projects/ad9081_fmca_ebz/zcu102 + $make RX_LANE_RATE=2.5 TX_LANE_RATE=2.5 \ + $ RX_JESD_L=8 RX_JESD_M=4 RX_JESD_S=1 \ + $ RX_JESD_NP=16 TX_JESD_L=8 TX_JESD_M=4 \ + $ TX_JESD_S=1 TX_JESD_NP=16 The following dropdowns contain tables with the parameters that can be used to configure this project, depending on the carrier used. Where a cell contains a --- (dash) it means that the parameter doesn't exist -for that project (ad9081_fmca_ebz/carrier or ad9082_fmca_ebz/carrier). +for that project (ad9081_fmca_ebz/$carrier or ad9082_fmca_ebz/$carrier). .. warning:: diff --git a/docs/projects/ad9081_fmca_ebz_x_band/index.rst b/docs/projects/ad9081_fmca_ebz_x_band/index.rst index de2c4f94cf..12e634c547 100644 --- a/docs/projects/ad9081_fmca_ebz_x_band/index.rst +++ b/docs/projects/ad9081_fmca_ebz_x_band/index.rst @@ -17,8 +17,8 @@ Overview The :adi:`X-Band Development Platform ` contains one MxFE® software defined, direct RF sampling transceivers, -:dokuwiki:`X-Band to C-Band Up/Down Converter ` -, and a :dokuwiki:`X/Ku Band analog phased array ` +:dokuwiki:`X-Band to C-Band Up/Down Converter `, +and a :dokuwiki:`X/Ku Band analog phased array ` proto-typing platform. The target application is phased array radars, electronic warfare, and ground-based SATCOM, specifically a X Band 32 transmit/32 receive channel hybrid @@ -35,26 +35,26 @@ reference software, HDL code, and MATLAB system-level interfacing software. Supported boards ------------------------------------------------------------------------------- -- :adi:`X-Band Phased Array Platform ` -- :adi:`AD9081-FMCA-EBZ ` -- :dokuwiki:`ADAR1000EVAL1Z (Stingray) ` -- :dokuwiki:`ADXUD1AEBZ ` +- :adi:`X-Band Phased Array Platform ` +- :adi:`AD9081-FMCA-EBZ ` +- :dokuwiki:`ADAR1000EVAL1Z (Stingray) ` +- :dokuwiki:`ADXUD1AEBZ ` Supported devices ------------------------------------------------------------------------------- -- :adi:`AD9081` -- :adi:`ADAR1000` -- :adi:`ADTR1107` -- :adi:`HMC652LP2E` -- :adi:`HMC773ALC3B` -- :adi:`ADL8111` -- :adi:`HMC8411` -- :adi:`HMC963` -- :adi:`HMC383LC4` -- :adi:`ADF4371` -- :adi:`ADRF5020` -- :adi:`HMC903LP3E` -- :adi:`LT8653S` +- :adi:`AD9081` +- :adi:`ADAR1000` +- :adi:`ADTR1107` +- :adi:`HMC652LP2E` +- :adi:`HMC773ALC3B` +- :adi:`ADL8111` +- :adi:`HMC8411` +- :adi:`HMC963` +- :adi:`HMC383LC4` +- :adi:`ADF4371` +- :adi:`ADRF5020` +- :adi:`HMC903LP3E` +- :adi:`LT8653S` Supported carriers ------------------------------------------------------------------------------- @@ -86,57 +86,57 @@ Example block design for Single link; M=8; L=4 The Rx links (ADC Path) operate with the following parameters: -- Rx Deframer parameters: L=4, M=8, F=4, S=1, NP=16, N=16 (Quick +- Rx Deframer parameters: L=4, M=8, F=4, S=1, NP=16, N=16 (Quick Config 0x0A) -- Sample Rate: 250 MSPS -- Dual link: No -- RX_DEVICE_CLK: 250 MHz (Lane Rate/40) -- REF_CLK: 500MHz (Lane Rate/20) -- JESD204B Lane Rate: 10Gbps -- QPLL0 or CPLL +- Sample Rate: 250 MSPS +- Dual link: No +- RX_DEVICE_CLK: 250 MHz (Lane Rate/40) +- REF_CLK: 500MHz (Lane Rate/20) +- JESD204B Lane Rate: 10Gbps +- QPLL0 or CPLL The Tx links (DAC Path) operate with the following parameters: -- Tx Framer parameters: L=4, M=8, F=4, S=1, NP=16, N=16 (Quick Config +- Tx Framer parameters: L=4, M=8, F=4, S=1, NP=16, N=16 (Quick Config 0x09) -- Sample Rate: 250 MSPS -- Dual link: No -- TX_DEVICE_CLK: 250 MHz (Lane Rate/40) -- REF_CLK: 500MHz (Lane Rate/20) -- JESD204B Lane Rate: 10Gbps -- QPLL0 or CPLL +- Sample Rate: 250 MSPS +- Dual link: No +- TX_DEVICE_CLK: 250 MHz (Lane Rate/40) +- REF_CLK: 500MHz (Lane Rate/20) +- JESD204B Lane Rate: 10Gbps +- QPLL0 or CPLL Configuration modes ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The following are the parameters of this project that can be configured: -- JESD_MODE: used link layer encoder mode +- JESD_MODE: used link layer encoder mode - - 64B66B - 64b66b link layer defined in JESD204C, uses AMD IP as Physical + - 64B66B - 64b66b link layer defined in JESD204C, uses AMD IP as Physical Layer - - 8B10B - 8b10b link layer defined in JESD204B, uses ADI IP as Physical + - 8B10B - 8b10b link layer defined in JESD204B, uses ADI IP as Physical Layer -- RX_LANE_RATE: lane rate of the Rx link (MxFE to FPGA) -- TX_LANE_RATE: lane rate of the Tx link (FPGA to MxFE) -- [RX/TX]_JESD_M: number of converters per link -- [RX/TX]_JESD_L: number of lanes per link -- [RX/TX]_JESD_S: number of samples per frame -- [RX/TX]_JESD_NP: number of bits per sample -- [RX/TX]_NUM_LINKS: number of links -- TDD_SUPPORT: set to 1, adds the TDD; enables external synchronization through +- RX_LANE_RATE: lane rate of the Rx link (MxFE to FPGA) +- TX_LANE_RATE: lane rate of the Tx link (FPGA to MxFE) +- [RX/TX]_JESD_M: number of converters per link +- [RX/TX]_JESD_L: number of lanes per link +- [RX/TX]_JESD_S: number of samples per frame +- [RX/TX]_JESD_NP: number of bits per sample +- [RX/TX]_NUM_LINKS: number of links +- TDD_SUPPORT: set to 1, adds the TDD; enables external synchronization through TDD. Must be set to 1 when SHARED_DEVCLK=1 -- SHARED_DEVCLK -- TDD_CHANNEL_CNT -- TDD_SYNC_WIDTH -- TDD_SYNC_INT -- TDD_SYNC_EXT -- TDD_SYNC_EXT_CDC: if enabled, the CDC circuitry for the external sync signal +- SHARED_DEVCLK +- TDD_CHANNEL_CNT +- TDD_SYNC_WIDTH +- TDD_SYNC_INT +- TDD_SYNC_EXT +- TDD_SYNC_EXT_CDC: if enabled, the CDC circuitry for the external sync signal is added -- [RX/TX]_KS_PER_CHANNEL: Number of samples stored in internal buffers in +- [RX/TX]_KS_PER_CHANNEL: Number of samples stored in internal buffers in kilosamples per converter (M) -- Check out this guide on more details regarding these parameters: +- Check out this guide on more details regarding these parameters: :ref:`axi_tdd` CPU/Memory interconnects addresses @@ -233,7 +233,7 @@ GPIOs ====================== ================ ============== ============== GPIO signal Direction HDL GPIO EMIO Software GPIO ---- (from FPGA view) --- Zynq MP + (from FPGA view) Zynq MP ====================== ================ ============== ============== gpio_o_86_ms OUT 86 163 gpio_o_85_ms OUT 85 162 @@ -299,15 +299,15 @@ the HDL repository. **Linux/Cygwin/WSL** -.. code-block:: - :linenos: +.. shell:: - user@analog:~$ cd hdl/projects/ad9081_fmca_ebz_x_band/zcu102 - user@analog:~/hdl/projects/ad9081_fmca_ebz_x_band/zcu102$ make + $cd hdl/projects/ad9081_fmca_ebz_x_band/zcu102 + $make A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. .. warning:: + All the details regarding the build parameters can be found on the :ref:`AD9081/AD9082/AD9986/AD9988 HDL project page ` @@ -324,37 +324,36 @@ Resources Systems related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :dokuwiki:`[Wiki] ADAR1000EVAL1Z (STINGRAY) ANALOG BEAMFORMING FRONT-END ` +- :dokuwiki:`[Wiki] ADAR1000EVAL1Z (STINGRAY) ANALOG BEAMFORMING FRONT-END ` Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheets: - - - :adi:`AD9081` - - :adi:`ADAR1000` - - :adi:`ADTR1107` - - :adi:`HMC652LP2E` - - :adi:`HMC773ALC3B` - - :adi:`ADL8111` - - :adi:`HMC8411` - - :adi:`HMC963` - - :adi:`HMC383LC4` - - :adi:`ADF4371` - - :adi:`ADRF5020` - - :adi:`HMC903LP3E` - - :adi:`LT8653S` - -- :dokuwiki:`[Wiki] X-Band Platform Hardware ` -- :adi:`AD9081-FMCA-EBZ ` - -- :dokuwiki:`ADAR1000EVAL1Z (Stingray) ` -- :dokuwiki:`ADXUD1AEBZ ` +- Product datasheets: + + - :adi:`AD9081` + - :adi:`ADAR1000` + - :adi:`ADTR1107` + - :adi:`HMC652LP2E` + - :adi:`HMC773ALC3B` + - :adi:`ADL8111` + - :adi:`HMC8411` + - :adi:`HMC963` + - :adi:`HMC383LC4` + - :adi:`ADF4371` + - :adi:`ADRF5020` + - :adi:`HMC903LP3E` + - :adi:`LT8653S` + +- :dokuwiki:`[Wiki] X-Band Platform Hardware ` +- :adi:`AD9081-FMCA-EBZ ` +- :dokuwiki:`ADAR1000EVAL1Z (Stingray) ` +- :dokuwiki:`ADXUD1AEBZ ` HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`AD9081_FMCA_EBZ_X_BAND HDL project source code ` +- :git-hdl:`AD9081_FMCA_EBZ_X_BAND HDL project source code ` .. list-table:: :widths: 30 35 35 @@ -427,26 +426,26 @@ HDL related - :git-hdl:`library/jesd204/ad_ip_jesd204_tpl_dac` - :ref:`ad_ip_jesd204_tpl_dac` -- :dokuwiki:`[Wiki] Generic JESD204B block designs ` -- :ref:`jesd204` +- :dokuwiki:`[Wiki] Generic JESD204B block designs ` +- :ref:`jesd204` Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :dokuwiki:`[Wiki] X-Band Platform Software ` -- :dokuwiki:`[Wiki] AD9081-FMCA-EBZ Linux driver wiki page ` +- :dokuwiki:`[Wiki] X-Band Platform Software ` +- :dokuwiki:`[Wiki] AD9081-FMCA-EBZ Linux driver wiki page ` -- Stingray devicetrees: +- Stingray devicetrees: - - :git-linux:`zynqmp-zcu102-rev10-stingray-vcxo100.dts` - - :git-linux:`zynqmp-zcu102-rev10-stingray.dts` - - :git-linux:`zynqmp-zcu102-rev10-stingray-direct-clk.dts` - - :git-linux:`zynqmp-zcu102-rev10-stingray-vcxo100-direct-clk.dts` + - :git-linux:`zynqmp-zcu102-rev10-stingray-vcxo100.dts` + - :git-linux:`zynqmp-zcu102-rev10-stingray.dts` + - :git-linux:`zynqmp-zcu102-rev10-stingray-direct-clk.dts` + - :git-linux:`zynqmp-zcu102-rev10-stingray-vcxo100-direct-clk.dts` -- Python support: +- Python support: - - `AD9081 class documentation `__ - - `PyADI-IIO documentation `__ + - `AD9081 class documentation `__ + - `PyADI-IIO documentation `__ .. include:: ../common/more_information.rst diff --git a/docs/projects/ad9213_evb/index.rst b/docs/projects/ad9213_evb/index.rst index 2b8c252d49..2644396f97 100644 --- a/docs/projects/ad9213_evb/index.rst +++ b/docs/projects/ad9213_evb/index.rst @@ -22,12 +22,12 @@ an AXI-Lite interface. Supported boards ------------------------------------------------------------------------------- -- :adi:`AD9213-EVB ` +- :adi:`AD9213-EVB ` Supported devices ------------------------------------------------------------------------------- -- :adi:`AD9213` +- :adi:`AD9213` Supported carriers ------------------------------------------------------------------------------- @@ -60,13 +60,13 @@ The data path and clock domains are depicted in the below diagrams: The Rx links (ADC Path) operate with the following parameters: - - Rx parameters: L=16, M=1, F=2, S=16, NP=16, N=16 - - Sample Rate: 10 GSPS - - Dual link: No - - RX_DEVICE_CLK: 312.25 MHz (Lane Rate/40) - - REF_CLK: 625 MHz (Lane Rate/20) - - JESD204B Lane Rate: 12.5 Gbps - - QPLL0 + - Rx parameters: L=16, M=1, F=2, S=16, NP=16, N=16 + - Sample Rate: 10 GSPS + - Dual link: No + - RX_DEVICE_CLK: 312.25 MHz (Lane Rate/40) + - REF_CLK: 625 MHz (Lane Rate/20) + - JESD204B Lane Rate: 12.5 Gbps + - QPLL0 .. math:: Lane Rate = Sample Rate*\frac{M}{L}*N'* \frac{10}{8} @@ -167,8 +167,15 @@ If you want to build the sources, ADI makes them available on the `clone `__ the HDL repository. -Then go to the :git-hdl:`projects/ad9213_evb ` -location and run the "make" command by typing in your command prompt. +Then go to the :git-hdl:`projects/ad9213_evb` location and run the make +command by typing in your command prompt: + +**Linux/Cygwin/WSL** + +.. shell:: + + $cd hdl/projects/ad9213_evb/vcu118 + $make A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. @@ -178,14 +185,14 @@ Resources Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheet: :adi:`AD9213` -- :adi:`Device data sheet ` -- :adi:`Evaluation Board ` +- Product datasheet: :adi:`AD9213` +- :adi:`Device data sheet ` +- :adi:`Evaluation Board ` HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`AD9213_EVB HDL project source code ` +- :git-hdl:`AD9213_EVB HDL project source code ` .. list-table:: :widths: 30 35 35 @@ -216,8 +223,8 @@ HDL related - :git-hdl:`library/jesd204/ad_ip_jesd204_tpl_adc` - :ref:`ad_ip_jesd204_tpl_adc` -- :dokuwiki:`[Wiki] Generic JESD204B block designs ` -- :ref:`jesd204` +- :dokuwiki:`[Wiki] Generic JESD204B block designs ` +- :ref:`jesd204` .. include:: ../common/more_information.rst diff --git a/docs/projects/ad9265_fmc/index.rst b/docs/projects/ad9265_fmc/index.rst index 4819713cbf..3b20ef3842 100644 --- a/docs/projects/ad9265_fmc/index.rst +++ b/docs/projects/ad9265_fmc/index.rst @@ -20,12 +20,12 @@ inputs of the ADC. Supported boards ------------------------------------------------------------------------------- -- :adi:`EVAL-AD9265 ` +- :adi:`EVAL-AD9265 ` Supported devices ------------------------------------------------------------------------------- -- :adi:`AD9265` +- :adi:`AD9265` Supported carriers ------------------------------------------------------------------------------- @@ -129,10 +129,10 @@ make command by typing in your command prompt(this example :xilinx:`ZC706`): **Linux/Cygwin/WSL** -.. code-block:: +.. shell:: - user@analog:~$ cd hdl/projects/ad9265_fmc/zc706 - user@analog:~/hdl/projects/ad9265_fmc/zc706$ make + $cd hdl/projects/ad9265_fmc/zc706 + $make A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. @@ -156,13 +156,13 @@ Here you can find the quick start guides available for these evaluation boards: Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheets: :adi:`AD9265` -- :dokuwiki:`[Wiki] Evaluating AD9265, user guide ` +- Product datasheets: :adi:`AD9265` +- :dokuwiki:`[Wiki] Evaluating AD9265, user guide ` HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`AD9265-FMC HDL project source code ` +- :git-hdl:`AD9265-FMC HDL project source code ` .. list-table:: :widths: 30 35 35 diff --git a/docs/projects/ad9434_fmc/index.rst b/docs/projects/ad9434_fmc/index.rst index c80f6f698c..74502038c7 100644 --- a/docs/projects/ad9434_fmc/index.rst +++ b/docs/projects/ad9434_fmc/index.rst @@ -148,10 +148,10 @@ make command by typing in your command prompt (this example is for **Linux/Cygwin/WSL** -.. code-block:: +.. shell:: - user@analog:~$ cd hdl/projects/ad9434_fmc/zc706 - user@analog:~/hdl/projects/ad9434_fmc/zc706$ make + $cd hdl/projects/ad9434_fmc/zc706 + $make A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. @@ -176,14 +176,14 @@ Here you can find the quick start guides available for these evaluation boards: Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheet: :adi:`AD9434` -- Schematic file: `ad9434_fmc_500ebz_sch.pdf `__ -- :dokuwiki:`EVAL-AD9434 user guide ` +- Product datasheet: :adi:`AD9434` +- Schematic file: `ad9434_fmc_500ebz_sch.pdf `__ +- :dokuwiki:`EVAL-AD9434 user guide ` HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`AD9434-FMC HDL project source code ` +- :git-hdl:`AD9434-FMC HDL project source code ` .. list-table:: :widths: 30 35 35 diff --git a/docs/projects/ad9467_fmc/index.rst b/docs/projects/ad9467_fmc/index.rst index 77ba41cea5..905124293e 100644 --- a/docs/projects/ad9467_fmc/index.rst +++ b/docs/projects/ad9467_fmc/index.rst @@ -18,18 +18,18 @@ and/or setting up the :adi:`ADL5565` differential amplifier, respectively. Supported boards ------------------------------------------------------------------------------- -- :adi:`AD9467-FMC-250EBZ ` also referred to as EVAL-AD9467 +- :adi:`AD9467-FMC-250EBZ ` also referred to as EVAL-AD9467 Supported devices ------------------------------------------------------------------------------- -- :adi:`AD9467` +- :adi:`AD9467` Supported carriers ------------------------------------------------------------------------------- -- :xilinx:`KC705` LPC slot -- :xilinx:`ZedBoard ` +- :xilinx:`KC705` LPC slot +- :xilinx:`ZedBoard ` Block design ------------------------------------------------------------------------------- @@ -102,8 +102,8 @@ The evaluation board can be set up to be clocked from the **crystal oscillator**, Y200. This oscillator is a low phase noise oscillator from Vectron (VCC6-QCD-250M000). -- Install C205 and C206 -- Remove C202 +- Install C205 and C206 +- Remove C202 Jumper P200 is used to disable the oscillator from running. @@ -113,9 +113,9 @@ Clock generator AD9517 A **differential LVPECL or LVDS clock driver** can also be used to clock the ADC input using the AD9517. -- Populate (C304, C305) for LVPECL clock driver **or** (C306, C307) for +- Populate (C304, C305) for LVPECL clock driver **or** (C306, C307) for LVDS clock driver, with 0.1 µF capacitors -- Remove C209 and C210 to disconnect the default clock path inputs +- Remove C209 and C210 to disconnect the default clock path inputs The :adi:`AD9517` has many SPI-selectable options that are set to a default mode of operation. Consult the :adi:`AD9517` data sheet for more information @@ -190,38 +190,34 @@ location and run the make command by typing in your command prompt: **Linux/Cygwin/WSL** -.. code-block:: - :linenos: +.. shell:: - user@analog:~$ cd hdl/projects/ad9467_fmc/zed - user@analog:~/hdl/projects/ad9467_fmc/zed$ make + $cd hdl/projects/ad9467_fmc/zed + $make A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. -Check this wiki page if you're not familiar about `how to build an ADI -HDL project `__. - Resources ------------------------------------------------------------------------------- Systems related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :dokuwiki:`AD9467-FMC Quick Start Guide ` +- :dokuwiki:`AD9467-FMC Quick Start Guide ` Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheet: :adi:`AD9467` -- The schematic of the board can be found - :dokuwiki:`here `, - or :dokuwiki:`here ` - for older versions. +- Product datasheet: :adi:`AD9467` +- The schematic of the board can be found + :dokuwiki:`here `, + or :dokuwiki:`here ` + for older versions. HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`AD9467_FMC HDL project source code ` +- :git-hdl:`AD9467_FMC HDL project source code ` .. list-table:: :widths: 30 35 35 @@ -261,11 +257,11 @@ HDL related Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- AD9467-FMC KC705 Linux device tree :git-linux:`arch/microblaze/boot/dts/kc705_ad9467_fmc.dts` -- :git-linux:`AD9467-FMC ZedBoard Linux device tree zynq-zed-adv7511-ad9467-fmc-250ebz.dts ` -- :git-linux:`Linux driver ad9467.c ` -- :dokuwiki:`[Wiki] AD9467-FMC on ZedBoard using ACE ` -- :git-no-os:`No-OS project ` and :git-no-os:`no-OS driver ` +- AD9467-FMC KC705 Linux device tree :git-linux:`arch/microblaze/boot/dts/kc705_ad9467_fmc.dts` +- :git-linux:`AD9467-FMC ZedBoard Linux device tree zynq-zed-adv7511-ad9467-fmc-250ebz.dts ` +- :git-linux:`Linux driver ad9467.c ` +- :dokuwiki:`[Wiki] AD9467-FMC on ZedBoard using ACE ` +- :git-no-os:`No-OS project ` and :git-no-os:`no-OS driver ` .. include:: ../common/more_information.rst diff --git a/docs/projects/ad9656_fmc/index.rst b/docs/projects/ad9656_fmc/index.rst index ddddc0669e..c7a4277785 100644 --- a/docs/projects/ad9656_fmc/index.rst +++ b/docs/projects/ad9656_fmc/index.rst @@ -29,12 +29,12 @@ specific system requirements Supported boards ------------------------------------------------------------------------------- -- :adi:`EVAL-AD9656` +- :adi:`EVAL-AD9656` Supported devices ------------------------------------------------------------------------------- -- :adi:`AD9656` +- :adi:`AD9656` Supported carriers ------------------------------------------------------------------------------- @@ -63,12 +63,12 @@ Block diagram The Rx links (ADC Path) operate with the following parameters: -- Rx Deframer parameters: L=4, M=4, S=1, NP=16, N=16 -- Dual link: No -- RX_DEVICE_CLK: 62.5 MHz -- REF_CLK: 125MHz -- JESD204B Lane Rate: 10Gbps -- QPLL0 or CPLL +- Rx Deframer parameters: L=4, M=4, S=1, NP=16, N=16 +- Dual link: No +- RX_DEVICE_CLK: 62.5 MHz +- REF_CLK: 125MHz +- JESD204B Lane Rate: 10Gbps +- QPLL0 or CPLL AD9656 FMC Card block diagram ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -177,19 +177,19 @@ the HDL repository. **Linux/Cygwin/WSL** -.. code-block:: +.. shell:: - user@analog:~$ cd hdl/projects/ad9656_fmc/zcu102 - user@analog:~/hdl/projects/ad9656_fmc/zcu102$ make + $cd hdl/projects/ad9656_fmc/zcu102 + $make Below are the parameters that are used to configure this project, on :xilinx:`ZCU102`. -- JESD_MODE :red:`8B10B` -- RX_NUM_OF_LANES 4 -- RX_NUM_OF_CONVERTERS 4 -- RX_SAMPLES_PER_FRAME 1 -- RX_SAMPLE_WIDTH 16 -- RX_SAMPLES_PER_CHANNEL 2 +- JESD_MODE :red:`8B10B` +- RX_NUM_OF_LANES 4 +- RX_NUM_OF_CONVERTERS 4 +- RX_SAMPLES_PER_FRAME 1 +- RX_SAMPLE_WIDTH 16 +- RX_SAMPLES_PER_CHANNEL 2 A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. @@ -200,14 +200,14 @@ Resources Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheets: :adi:`AD9656` -- :dokuwiki:`[Wiki] Evaluating the AD9656 ADC converter ` +- Product datasheets: :adi:`AD9656` +- :dokuwiki:`[Wiki] Evaluating the AD9656 ADC converter ` HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :dokuwiki:`[Wiki] AD9656 HDL Reference Design ` -- :git-hdl:`AD9656-FMC HDL project source code ` +- :dokuwiki:`[Wiki] AD9656 HDL Reference Design ` +- :git-hdl:`AD9656-FMC HDL project source code ` .. list-table:: :widths: 30 35 35 diff --git a/docs/projects/ad9695_fmc/index.rst b/docs/projects/ad9695_fmc/index.rst index 555ff1f998..a090146d63 100644 --- a/docs/projects/ad9695_fmc/index.rst +++ b/docs/projects/ad9695_fmc/index.rst @@ -76,9 +76,9 @@ Configuration modes The following are the parameters of this project that can be configured: -- RX_JESD_M: number of converters per link - by default set to 2 -- RX_JESD_L: number of lanes per link - by default set to 4 -- RX_JESD_S: number of samples per frame - by default set to 1 +- RX_JESD_M: number of converters per link - by default set to 2 +- RX_JESD_L: number of lanes per link - by default set to 4 +- RX_JESD_S: number of samples per frame - by default set to 1 For more ways to configure this project, check :adi:`Table 35 from the AD9695 data sheet `, @@ -219,16 +219,19 @@ Examples on how to build the project: **Linux/Cygwin/WSL** -.. code-block:: - :linenos: +Example for building with the default configuration: - // without parameters (default configuration) - user@analog:~$ cd hdl/projects/ad9695_fmc/zcu102 - user@analog:~/hdl/projects/ad9695_fmc/zcu102$ make +.. shell:: - // with parameters - user@analog:~$ cd hdl/projects/ad9695_fmc/zcu102 - user@analog:~/hdl/projects/ad9695_fmc/zcu102$ make RX_JESD_M=2 RX_JESD_L=4 + $cd hdl/projects/ad9695_fmc/zcu102 + $make + +Example for building with parameters: + +.. shell:: + + $cd hdl/projects/ad9695_fmc/zcu102 + $make RX_JESD_M=2 RX_JESD_L=4 Default values of the ``make`` parameters for AD9695-FMC: @@ -275,7 +278,7 @@ Systems related Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheet: :adi:`AD9695` +- Product datasheet: :adi:`AD9695` HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -317,8 +320,8 @@ HDL related - :git-hdl:`library/jesd204/ad_ip_jesd204_tpl_adc` - :ref:`ad_ip_jesd204_tpl_adc` -- :dokuwiki:`[Wiki] Generic JESD204B block designs ` -- :ref:`jesd204` +- :dokuwiki:`[Wiki] Generic JESD204B block designs ` +- :ref:`jesd204` Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/projects/ad9739a_fmc/index.rst b/docs/projects/ad9739a_fmc/index.rst index fd2dfd2ab7..5eb777225a 100644 --- a/docs/projects/ad9739a_fmc/index.rst +++ b/docs/projects/ad9739a_fmc/index.rst @@ -20,17 +20,17 @@ available for driving the clock externally. Supported boards ------------------------------------------------------------------------------- -- :adi:`EVAL-AD9739A ` +- :adi:`EVAL-AD9739A ` Supported devices ------------------------------------------------------------------------------- -- :adi:`AD9739A ` +- :adi:`AD9739A ` Supported carriers ------------------------------------------------------------------------------- -- :xilinx:`ZC706` on FMC LPC slot +- :xilinx:`ZC706` on FMC LPC slot Block design ------------------------------------------------------------------------------- @@ -76,24 +76,24 @@ Clock scheme Two clock paths are available to drive the clock input on the :adi:`AD9739A `: -- The factory default option connects the :adi:`ADF4350 ` to - the :adi:`AD9739A `. The :adi:`ADF4350 ` is able to - synthesize a clock over the entire specified range of - the :adi:`AD9739A ` (1.6GHz to 2.5GHz) +- The factory default option connects the :adi:`ADF4350 ` to + the :adi:`AD9739A `. The :adi:`ADF4350 ` is able to + synthesize a clock over the entire specified range of + the :adi:`AD9739A ` (1.6GHz to 2.5GHz) - - Jumper CLOCK SOURCE (S1) must be moved to the :adi:`ADF4350 ` - position + - Jumper CLOCK SOURCE (S1) must be moved to the :adi:`ADF4350 ` + position -- Alternatively, an external clock can be provided via the SMA CLKIN (J3) jack +- Alternatively, an external clock can be provided via the SMA CLKIN (J3) jack - - Jumper CLOCK SOURCE (S1) must be moved to the :adi:`ADCLK914 ` - position. C102 and C99 on the back of the board also need to be removed - from their default position, and then soldered into the vertical position - from the large square pad they were previously soldered to and the narrow - pads closer to the :adi:`ADCLK914 ` (U3). Observe the - orientation of the caps before removing them; they must be soldered with - their narrow edge against the PCB, and not the wide side as is common - with most components. + - Jumper CLOCK SOURCE (S1) must be moved to the :adi:`ADCLK914 ` + position. C102 and C99 on the back of the board also need to be removed + from their default position, and then soldered into the vertical position + from the large square pad they were previously soldered to and the narrow + pads closer to the :adi:`ADCLK914 ` (U3). Observe the + orientation of the caps before removing them; they must be soldered with + their narrow edge against the PCB, and not the wide side as is common + with most components. CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -139,11 +139,10 @@ To get the source you must `clone `__ the HDL repository. -.. code-block:: - :linenos: +.. shell:: - user@analog:~$ cd hdl/projects/ad9739a_fmc/zc706 - user@analog:~/hdl/projects/ad9739a_fmc/zc706$ make + $cd hdl/projects/ad9739a_fmc/zc706 + $make A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. @@ -154,19 +153,19 @@ Resources Systems related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :dokuwiki:`[Wiki] AD9737A-EBZ/AD9739A-EBZ Quick Start Guide ` - (with ACE) -- :dokuwiki:`[Wiki] AD9739A Native FMC Card/Xilinx Reference Designs ` +- :dokuwiki:`[Wiki] AD9737A-EBZ/AD9739A-EBZ Quick Start Guide ` + (with ACE) +- :dokuwiki:`[Wiki] AD9739A Native FMC Card/Xilinx Reference Designs ` Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheets: :adi:`AD9739A` +- Product datasheets: :adi:`AD9739A` HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`AD9739A-FMC HDL project source code ` +- :git-hdl:`AD9739A-FMC HDL project source code ` .. list-table:: :widths: 30 35 35 @@ -177,7 +176,7 @@ HDL related - Documentation link * - AXI_AD9739A - :git-hdl:`library/axi_ad9739a` - - — + - — * - AXI_DMAC - :git-hdl:`library/axi_dmac` - :ref:`axi_dmac` @@ -200,10 +199,10 @@ HDL related Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-linux:`AD9739A-FMC Linux driver ` -- :git-linux:`AD9739A-FMC Linux device tree ` -- :git-no-os:`AD9739A-FMC No-Os project ` -- :git-no-os:`AD9739A-FMC No-Os driver ` +- :git-linux:`AD9739A-FMC Linux driver ` +- :git-linux:`AD9739A-FMC Linux device tree ` +- :git-no-os:`AD9739A-FMC No-Os project ` +- :git-no-os:`AD9739A-FMC No-Os driver ` .. include:: ../common/more_information.rst diff --git a/docs/projects/ad9783_ebz/index.rst b/docs/projects/ad9783_ebz/index.rst index a82dc972cc..cc550c292a 100644 --- a/docs/projects/ad9783_ebz/index.rst +++ b/docs/projects/ad9783_ebz/index.rst @@ -20,19 +20,19 @@ The :adi:`EVAL-AD9783` board is connected to the FPGA carrier through Supported boards ------------------------------------------------------------------------------- -- :adi:`EVAL-AD9783` +- :adi:`EVAL-AD9783` Supported devices ------------------------------------------------------------------------------- -- :adi:`AD9780` -- :adi:`AD9781` -- :adi:`AD9783` +- :adi:`AD9780` +- :adi:`AD9781` +- :adi:`AD9783` Supported carriers ------------------------------------------------------------------------------- -- :xilinx:`ZCU102` on FMC HPC0 slot +- :xilinx:`ZCU102` on FMC HPC0 slot Block design ------------------------------------------------------------------------------- @@ -50,8 +50,8 @@ The data path and clock domains are depicted in the below diagram: Clock scheme ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- External clock source connected to J1 (CLOCK IN) -- For maximum performance, give a 500 MHz clock +- External clock source connected to J1 (CLOCK IN) +- For maximum performance, give a 500 MHz clock To make the connection between the :adi:`EVAL-AD9783` evaluation board and the carrier using SPI, some hardware changes must be done to the evaluation @@ -115,10 +115,10 @@ the HDL repository, and then build the project as follows: **Linux/Cygwin/WSL** -.. code-block:: +.. shell:: - user@analog:~$ cd hdl/projects/ad9783_ebz/zcu102 - user@analog:~/hdl/projects/ad9783_ebz/zcu102$ make + $cd hdl/projects/ad9783_ebz/zcu102 + $make A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. @@ -153,18 +153,18 @@ Here you can find the quick start guides available for these evaluation boards: Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheets: +- Product datasheets: - - :adi:`AD9780` - - :adi:`AD9781` - - :adi:`AD9783` - - :adi:`EVAL-AD9783` - - :adi:`AD-DAC-FMC`-ADP + - :adi:`AD9780` + - :adi:`AD9781` + - :adi:`AD9783` + - :adi:`EVAL-AD9783` + - :adi:`AD-DAC-FMC`-ADP HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`AD9783_EBZ HDL project source code ` +- :git-hdl:`AD9783_EBZ HDL project source code ` .. list-table:: :widths: 30 35 35 @@ -192,8 +192,8 @@ HDL related Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-linux:`Linux device tree zynqmp-zcu102-rev10-ad9783.dts ` -- :git-linux:`Linux driver ad9783.c ` +- :git-linux:`Linux device tree zynqmp-zcu102-rev10-ad9783.dts ` +- :git-linux:`Linux driver ad9783.c ` .. include:: ../common/more_information.rst diff --git a/docs/projects/ad_gmsl2eth_sl/index.rst b/docs/projects/ad_gmsl2eth_sl/index.rst index 09c98381f2..b5c970b247 100644 --- a/docs/projects/ad_gmsl2eth_sl/index.rst +++ b/docs/projects/ad_gmsl2eth_sl/index.rst @@ -27,31 +27,31 @@ and the PTP logic. Supported devices ------------------------------------------------------------------------------- -- :adi:`MAX96724` -- :adi:`MAX17573` -- :adi:`ADM7154` -- :adi:`MAX25206` -- :adi:`LTC3303` -- :adi:`LTC4355` -- :adi:`AD9545` +- :adi:`MAX96724` +- :adi:`MAX17573` +- :adi:`ADM7154` +- :adi:`MAX25206` +- :adi:`LTC3303` +- :adi:`LTC4355` +- :adi:`AD9545` Supported carriers ------------------------------------------------------------------------------- -- :xilinx:`K26 SOM ` +- :xilinx:`K26 SOM ` Block diagram ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The data path designed in this reference design is as follows: -- the virtual channel inputs of one CSI-2 output port of the deserializer are - captured using Xilinx's `MIPI CSI-2 Rx Subsystem IP `_ -- data is written into memory by using a Xilinx video-related DMA implementation - `Video Framebuffer Write `_ -- the control of the camera modules is realized through I2C using Xilinx's - `AXI IIC logic `_ -- data is transmitted to a 10G-capable node by using Corundum NIC implementation +- the virtual channel inputs of one CSI-2 output port of the deserializer are + captured using Xilinx's `MIPI CSI-2 Rx Subsystem IP `_ +- data is written into memory by using a Xilinx video-related DMA implementation + `Video Framebuffer Write `_ +- the control of the camera modules is realized through I2C using Xilinx's + `AXI IIC logic `_ +- data is transmitted to a 10G-capable node by using Corundum NIC implementation The data path and elements of the video network, 10G NIC, are depicted in the below diagram: @@ -124,7 +124,7 @@ GPIOs The Software GPIO number is calculated as follows: -- ZynqMP: if PS8 EMIOs are used, then offset is 78 +- ZynqMP: if PS8 EMIOs are used, then offset is 78 .. list-table:: :widths: 25 25 25 25 @@ -227,9 +227,9 @@ and it needs to be cloned alongside this repository. The following papers pertain to the Corundum source code: - - J- A. Forencich, A. C. Snoeren, G. Porter, G. Papen, Corundum: An Open-Source 100-Gbps NIC, in FCCM'20. - (`FCCM Paper`_, `FCCM Presentation`_) - - J- A. Forencich, System-Level Considerations for Optical Switching in Data Center Networks. (`Thesis`_) + - J- A. Forencich, A. C. Snoeren, G. Porter, G. Papen, Corundum: An Open-Source 100-Gbps NIC, in FCCM'20. + (`FCCM Paper`_, `FCCM Presentation`_) + - J- A. Forencich, System-Level Considerations for Optical Switching in Data Center Networks. (`Thesis`_) .. _FCCM Paper: https://www.cse.ucsd.edu/~snoeren/papers/corundum-fccm20.pdf .. _FCCM Presentation: https://www.fccm.org/past/2020/forums/topic/corundum-an-open-source-100-gbps-nic/ @@ -237,13 +237,12 @@ and it needs to be cloned alongside this repository. **Linux/Cygwin/WSL** -.. code-block:: - :linenos: +.. shell:: - user@analog:~$ git clone https://github.com/corundum/corundum.git - user@analog:~$ git checkout ed4a26e2cbc0a429c45d5cd5ddf1177f86838914 - user@analog:~$ cd hdl/projects/ad_gmsl2eth_sl/k26 - user@analog:~/hdl/projects/ad_gmsl2eth_sl/k26$ make + $git clone https://github.com/corundum/corundum.git + $git checkout ed4a26e2cbc0a429c45d5cd5ddf1177f86838914 + $cd hdl/projects/ad_gmsl2eth_sl/k26 + $make A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. @@ -253,21 +252,21 @@ Resources Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheets: +- Product datasheets: - - :adi:`AD-GMSL2ETH-SL` - - :adi:`MAX96724 ` - - :adi:`MAX17573 ` - - :adi:`ADM7154 ` - - :adi:`MAX25206 ` - - :adi:`LTC3303 ` - - :adi:`LTC4355 ` - - :adi:`AD9545 ` + - :adi:`AD-GMSL2ETH-SL` + - :adi:`MAX96724 ` + - :adi:`MAX17573 ` + - :adi:`ADM7154 ` + - :adi:`MAX25206 ` + - :adi:`LTC3303 ` + - :adi:`LTC4355 ` + - :adi:`AD9545 ` HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`AD-GMSL2ETH-SL HDL project source code ` +- :git-hdl:`AD-GMSL2ETH-SL HDL project source code ` .. list-table:: :widths: 30 35 35 @@ -295,8 +294,8 @@ HDL related Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- `GMSL-related repository `_ -- :git-linux:`GMSL drivers/dts ` +- `GMSL-related repository `_ +- :git-linux:`GMSL drivers/dts ` .. include:: ../common/more_information.rst diff --git a/docs/projects/adaq7980_sdz/index.rst b/docs/projects/adaq7980_sdz/index.rst index f13adbc6ea..ef96a00ec7 100644 --- a/docs/projects/adaq7980_sdz/index.rst +++ b/docs/projects/adaq7980_sdz/index.rst @@ -178,11 +178,10 @@ the HDL repository, and then build the project as follows:. **Linux/Cygwin/WSL** -.. code-block:: - :linenos: +.. shell:: - user@analog:~$ cd hdl/projects/adaq7980_sdz/zed - user@analog:~/hdl/projects/adaq7980_sdz/zed$ make + $cd hdl/projects/adaq7980_sdz/zed + $make A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. diff --git a/docs/projects/adaq8092_fmc/index.rst b/docs/projects/adaq8092_fmc/index.rst index f384b89b3b..ca7464d3c4 100644 --- a/docs/projects/adaq8092_fmc/index.rst +++ b/docs/projects/adaq8092_fmc/index.rst @@ -21,13 +21,13 @@ which must be consulted in conjunction with this user guide when using the Supported boards ------------------------------------------------------------------------------- -- :adi:`EVAL-ADAQ8092 ` -- :adi:`DC1075B` +- :adi:`EVAL-ADAQ8092` +- :adi:`DC1075B` Supported devices ------------------------------------------------------------------------------- -- :adi:`ADAQ8092` +- :adi:`ADAQ8092` Supported carriers ------------------------------------------------------------------------------- @@ -61,10 +61,10 @@ Block diagram Clock scheme ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- External clock source +- External clock source - - Rohde & Schwarz SMA100A (clock source) - Suggested - - :adi:`DC1075B (Clock Divider) - Suggested ` + - Rohde & Schwarz SMA100A (clock source) - Suggested + - :adi:`DC1075B (Clock Divider) - Suggested ` .. image:: ../adaq8092_fmc/adaq8092_clock_scheme.svg :width: 800 @@ -162,11 +162,10 @@ the HDL repository, and then build the project as follows: **Linux/Cygwin/WSL** -.. code-block:: - :linenos: +.. shell:: - user@analog:~$ cd hdl/projects/adaq8092_fmc/zed - user@analog:~/hdl/projects/adaq8092_fmc/zed$ make + $cd hdl/projects/adaq8092_fmc/zed + $make A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. @@ -176,19 +175,17 @@ Resources Systems related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :dokuwiki:`[Wiki] ADAQ8092 Evaluation Board User Guide ` +- :dokuwiki:`[Wiki] ADAQ8092 Evaluation Board User Guide ` Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheets: - - - :adi:`ADAQ8092` +- Product datasheets: :adi:`ADAQ8092` HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`EVAL-ADAQ8092 HDL project source code ` +- :git-hdl:`EVAL-ADAQ8092 HDL project source code ` .. list-table:: :widths: 30 35 35 @@ -231,13 +228,13 @@ HDL related Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :dokuwiki:`[Wiki] ADAQ8092 14-Bit, 105 MSPS, μModule Linux device driver ` +- :dokuwiki:`[Wiki] ADAQ8092 14-Bit, 105 MSPS, μModule Linux device driver ` -- Python support : +- Python support : - - `ADAQ8092 Python class documentation `__ - - :git-pyadi-iio:`ADAQ8092 PyADI-IIO example ` - - :git-pyadi-iio:`PyADI-IIO documentation ` + - `ADAQ8092 Python class documentation `__ + - :git-pyadi-iio:`ADAQ8092 PyADI-IIO example ` + - :git-pyadi-iio:`PyADI-IIO documentation ` .. include:: ../common/more_information.rst diff --git a/docs/projects/adrv9026/index.rst b/docs/projects/adrv9026/index.rst index 760d5322c1..c934541435 100644 --- a/docs/projects/adrv9026/index.rst +++ b/docs/projects/adrv9026/index.rst @@ -379,19 +379,18 @@ If you want to build the sources, ADI makes them available on the `clone `__ the HDL repository. -Then go to the :git-hdl:`projects/adrv9026 ` -location and run the make command by typing in your command prompt: +Then go to the project location, choose your carrier and run the make command +by typing in your command prompt: **Linux/Cygwin/WSL** -.. code-block:: - :linenos: +.. shell:: - user@analog:~$ cd hdl/projects/adrv9026/zcu102 - user@analog:~/hdl/projects/adrv9026/zcu102$ make + $cd hdl/projects/adrv9026/zcu102 + $make - user@analog:~$ cd hdl/projects/adrv9026/a10soc - user@analog:~/hdl/projects/adrv9026/a10soc$ make + $cd hdl/projects/adrv9026/a10soc + $make The following dropdowns contain tables with the parameters that can be used to configure this project, depending on the carrier used. diff --git a/docs/projects/adrv904x/index.rst b/docs/projects/adrv904x/index.rst index 609d556db1..fb2fe041e2 100644 --- a/docs/projects/adrv904x/index.rst +++ b/docs/projects/adrv904x/index.rst @@ -15,12 +15,12 @@ stations. Supported devices ------------------------------------------------------------------------------- -- :adi:`ADRV9040` +- :adi:`ADRV9040` Supported boards ------------------------------------------------------------------------------- -- :adi:`EVAL-ADRV904x` +- :adi:`EVAL-ADRV904x` Supported carriers ------------------------------------------------------------------------------- @@ -57,23 +57,23 @@ Example block design for Single link; M=16; L=8 The Rx links (ADC Path) operate with the following parameters: -- Rx Deframer parameters: L=8, M=16, F=4, S=1, NP=16, N=16 -- Sample Rate: 491.52 MSPS -- Dual link: No -- RX_DEVICE_CLK: 245.76 MHz (Lane Rate/66) -- REF_CLK: 491.52 MHz (Lane Rate/33) -- JESD204C Lane Rate: 16.22 Gbps -- QPLL0 +- Rx Deframer parameters: L=8, M=16, F=4, S=1, NP=16, N=16 +- Sample Rate: 491.52 MSPS +- Dual link: No +- RX_DEVICE_CLK: 245.76 MHz (Lane Rate/66) +- REF_CLK: 491.52 MHz (Lane Rate/33) +- JESD204C Lane Rate: 16.22 Gbps +- QPLL0 The Tx links (DAC Path) operate with the following parameters: -- Tx Deframer parameters: L=8, M=16, F=4, S=1, NP=16, N=16 -- Sample Rate: 491.52 MSPS -- Dual link: No -- TX_DEVICE_CLK: 245.76 MHz (Lane Rate/66) -- REF_CLK: 491.52 MHz (Lane Rate/33) -- JESD204C Lane Rate: 16.22 Gbps -- QPLL0 +- Tx Deframer parameters: L=8, M=16, F=4, S=1, NP=16, N=16 +- Sample Rate: 491.52 MSPS +- Dual link: No +- TX_DEVICE_CLK: 245.76 MHz (Lane Rate/66) +- REF_CLK: 491.52 MHz (Lane Rate/33) +- JESD204C Lane Rate: 16.22 Gbps +- QPLL0 Configuration modes ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -95,18 +95,18 @@ for each project. The following are the parameters of this project that can be configured: -- JESD_MODE: used link layer encoder mode +- JESD_MODE: used link layer encoder mode - - 64B66B - 64b66b link layer defined in JESD204C - - 8B10B - 8b10b link layer defined in JESD204B + - 64B66B - 64b66b link layer defined in JESD204C + - 8B10B - 8b10b link layer defined in JESD204B -- RX_LANE_RATE: lane rate of the Rx link -- TX_LANE_RATE: lane rate of the Tx link -- [RX/TX]_JESD_M: number of converters per link -- [RX/TX]_JESD_L: number of lanes per link -- [RX/TX]_JESD_S: number of samples per frame -- [RX/TX]_JESD_NP: number of bits per sample -- [RX/TX]_NUM_LINKS: number of links +- RX_LANE_RATE: lane rate of the Rx link +- TX_LANE_RATE: lane rate of the Tx link +- [RX/TX]_JESD_M: number of converters per link +- [RX/TX]_JESD_L: number of lanes per link +- [RX/TX]_JESD_S: number of samples per frame +- [RX/TX]_JESD_NP: number of bits per sample +- [RX/TX]_NUM_LINKS: number of links Clock scheme ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -261,11 +261,10 @@ location and run the make command by typing in your command prompt: **Linux/Cygwin/WSL** -.. code-block:: - :linenos: +.. shell:: - user@analog:~$ cd hdl/projects/adrv904x/zcu102 - user@analog:~/hdl/projects/adrv904x/zcu102$ make + $cd hdl/projects/adrv904x/zcu102 + $make The following dropdowns contain tables with the parameters that can be used to configure this project, depending on the carrier used. @@ -347,7 +346,7 @@ Resources Systems related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :dokuwiki:`[Wiki] ADRV904x Prototyping Platform User Guide ` +- :dokuwiki:`[Wiki] ADRV904x Prototyping Platform User Guide ` Here you can find the quick start guides available for these evaluation boards: @@ -363,12 +362,12 @@ Here you can find the quick start guides available for these evaluation boards: Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheets: :adi:`ADRV9040 ` +- Product datasheets: :adi:`ADRV9040` HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`ADRV904x HDL project source code ` +- :git-hdl:`ADRV904x HDL project source code ` .. list-table:: :widths: 30 40 35 @@ -417,12 +416,12 @@ HDL related - :git-hdl:`library/jesd204/ad_ip_jesd204_tpl_dac` - :ref:`ad_ip_jesd204_tpl_dac` -- :ref:`jesd204` +- :ref:`jesd204` Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :dokuwiki:`[Wiki] ADRV904x Linux driver wiki page ` +- :dokuwiki:`[Wiki] ADRV904x Linux driver wiki page ` .. include:: ../common/more_information.rst diff --git a/docs/projects/adv7511/index.rst b/docs/projects/adv7511/index.rst index bd116d3402..671644a5f1 100644 --- a/docs/projects/adv7511/index.rst +++ b/docs/projects/adv7511/index.rst @@ -26,14 +26,14 @@ is provided in a 100-lead LQFP surface-mount plastic package and is specified ov Supported devices ------------------------------------------------------------------------------- -- :adi:`ADV7511` +- :adi:`ADV7511` Supported carriers ------------------------------------------------------------------------------- -- :xilinx:`ZC702` -- :xilinx:`ZC706` -- :xilinx:`ZedBoard ` +- :xilinx:`ZC702` +- :xilinx:`ZC706` +- :xilinx:`ZedBoard ` Block design ------------------------------------------------------------------------------- @@ -85,14 +85,14 @@ axi_iic_fmc* 0x4162_0000 .. admonition:: Legend :class: note - - ``*`` instantiated only for Zed carrier + - ``*`` instantiated only for Zed carrier GPIO ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The Software GPIO number is calculated as follows: -- Zynq-7000: if PS7 EMIOs are used, then offset is 54 +- Zynq-7000: if PS7 EMIOs are used, then offset is 54 .. list-table:: :widths: 25 25 25 25 @@ -122,9 +122,9 @@ The Software GPIO number is calculated as follows: .. admonition:: Legend :class: note - - ``*`` instantiated only for Zed carrier - - ``**`` instantiated only for ZC706 carrier - - ``***`` instantiated only for ZC702 carrier + - ``*`` instantiated only for Zed carrier + - ``**`` instantiated only for ZC706 carrier + - ``***`` instantiated only for ZC702 carrier Interrupts ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -142,7 +142,7 @@ axi_iic_fmc/iic2intc_irpt* 11 55 87 .. admonition:: Legend :class: note - - ``*`` instantiated only for Zed carrier + - ``*`` instantiated only for Zed carrier Building the HDL project ------------------------------------------------------------------------------- @@ -157,13 +157,12 @@ the HDL repository, and then build the project as follows:. **Linux/Cygwin/WSL** -.. code-block:: - :linenos: +.. shell:: - user@analog:~$ cd hdl/projects/adv7511/zed - user@analog:~/hdl/projects/adv7511/zed$ make + $cd hdl/projects/adv7511/zed + $make -A more comprehensive build guide can be found in the :ref:`build_hdl` +A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. Resources @@ -172,12 +171,12 @@ Resources Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheet: :adi:`ADV7511` +- Product datasheet: :adi:`ADV7511` HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`ADV7511 HDL project source code ` +- :git-hdl:`ADV7511 HDL project source code ` .. list-table:: :widths: 30 35 35 @@ -210,28 +209,20 @@ HDL related .. admonition:: Legend :class: note - - ``*`` instantiated only for Zed carrier + - ``*`` instantiated only for Zed carrier Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-linux:`ADV7511 driver source code ` - -- :git-linux:`ADV7511 - ZED dtsi source code (arm32) ` - -- :git-linux:`ADV7511 - ZED dts source code (arm32) ` - -- :git-linux:`ADV7511 - ZC706 dtsi source code (arm32) ` - -- :git-linux:`ADV7511 - ZC706 dts source code (arm32) ` - -- :git-linux:`ADV7511 - ZC702 dtsi source code (arm32) ` - -- :git-linux:`ADV7511 - ZC702 dts source code (arm32) ` - -- :dokuwiki:`ADV7511 driver docs ` - -- :git-no-OS:`ADV7511 no-OS project source code ` +- :git-linux:`ADV7511 driver source code ` +- :git-linux:`ADV7511 - ZED dtsi source code (arm32) ` +- :git-linux:`ADV7511 - ZED dts source code (arm32) ` +- :git-linux:`ADV7511 - ZC706 dtsi source code (arm32) ` +- :git-linux:`ADV7511 - ZC706 dts source code (arm32) ` +- :git-linux:`ADV7511 - ZC702 dtsi source code (arm32) ` +- :git-linux:`ADV7511 - ZC702 dts source code (arm32) ` +- :dokuwiki:`ADV7511 driver docs ` +- :git-no-OS:`ADV7511 no-OS project source code ` .. include:: ../common/more_information.rst diff --git a/docs/projects/adv7513/index.rst b/docs/projects/adv7513/index.rst index f8b2160dfe..43326af3f6 100644 --- a/docs/projects/adv7513/index.rst +++ b/docs/projects/adv7513/index.rst @@ -122,8 +122,8 @@ the HDL repository, and then build the project as follows: .. shell:: - $ cd hdl/projects/adv7513/de10nano - $ make + $cd hdl/projects/adv7513/de10nano + $make A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. diff --git a/docs/projects/cn0363/index.rst b/docs/projects/cn0363/index.rst index 5dafd450f7..13018aedb9 100644 --- a/docs/projects/cn0363/index.rst +++ b/docs/projects/cn0363/index.rst @@ -172,11 +172,10 @@ the HDL repository, and then build the project as follows: **Linux/Cygwin/WSL** -.. code-block:: - :linenos: +.. shell:: - user@analog:~$ cd hdl/projects/cn0363/zed - user@analog:~/hdl/projects/cn0363/zed$ make + $cd hdl/projects/cn0363/zed + $make A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. diff --git a/docs/projects/cn0506/index.rst b/docs/projects/cn0506/index.rst index 9cbc5a94b8..4c6dc77899 100644 --- a/docs/projects/cn0506/index.rst +++ b/docs/projects/cn0506/index.rst @@ -23,27 +23,27 @@ at 100 Mbps or 10 Mbps. Supported boards ------------------------------------------------------------------------------- -- :adi:`EVAL-CN0506 ` +- :adi:`EVAL-CN0506 ` Supported devices ------------------------------------------------------------------------------- -- :adi:`ADIN1300` -- :adi:`LTC4316 ` -- :adi:`LTC3502 ` +- :adi:`ADIN1300` +- :adi:`LTC4316 ` +- :adi:`LTC3502 ` Supported carriers ------------------------------------------------------------------------------- -- :intel:`A10SOC ` on FMC_A HPC * -- :xilinx:`ZCU102` on FMC HPC1 -- :xilinx:`ZC706` on FMC LPC -- :xilinx:`ZedBoard ` on FMC slot +- :intel:`A10SOC ` on FMC_A HPC * +- :xilinx:`ZCU102` on FMC HPC1 +- :xilinx:`ZC706` on FMC LPC +- :xilinx:`ZedBoard ` on FMC slot .. admonition:: Legend :class: note - - ``*`` only the MII interface is supported to be connected to A10SoC + - ``*`` only the MII interface is supported to be connected to A10SoC Block design ------------------------------------------------------------------------------- @@ -155,16 +155,16 @@ axi_iic_fmc ** 0x4162_0000 .. admonition:: Legend :class: note - - ``*`` instantiated only for Zed and ZC706 carriers - - ``**`` instantiated only for Zed carrier + - ``*`` instantiated only for Zed and ZC706 carriers + - ``**`` instantiated only for Zed carrier GPIO ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The Software GPIO number is calculated as follows: -- Zynq-7000: if PS7 EMIOs are used, then offset is 54 -- ZynqMP: if PS8 EMIOs are used, then offset is 78 +- Zynq-7000: if PS7 EMIOs are used, then offset is 54 +- ZynqMP: if PS8 EMIOs are used, then offset is 78 .. list-table:: :widths: 25 25 25 25 @@ -211,7 +211,7 @@ The Software GPIO number is calculated as follows: - 7:0 - 85:78 -- Intel FPGAs - Altera Arria 10 SoC +- Intel FPGAs - Altera Arria 10 SoC .. list-table:: :widths: 25 25 25 @@ -245,9 +245,9 @@ The Software GPIO number is calculated as follows: .. admonition:: Legend :class: note - - ``*`` instantiated only for Zed carrier - - ``**`` instantiated only for ZC706 carrier - - ``***`` instantiated only for ZCU102 carrier + - ``*`` instantiated only for Zed carrier + - ``**`` instantiated only for ZC706 carrier + - ``***`` instantiated only for ZCU102 carrier Interrupts ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -265,8 +265,8 @@ axi_iic_fmc/iic2intc_irpt* 11 55 87 .. admonition:: Legend :class: note - - ``*`` instantiated only for Zed and ZC706 carriers - - ``**`` instantiated only for Zed carrier + - ``*`` instantiated only for Zed and ZC706 carriers + - ``**`` instantiated only for Zed carrier Building the HDL project ------------------------------------------------------------------------------- @@ -281,11 +281,10 @@ the HDL repository, and then build the project as follows:. **Linux/Cygwin/WSL** -.. code-block:: - :linenos: +.. shell:: - user@analog:~$ cd hdl/projects/cn0506/zed - user@analog:~/hdl/projects/cn0506/zed$ make INTF_CFG=MII + $cd hdl/projects/cn0506/zed + $make INTF_CFG=MII The result of the build, if parameters were used, will be in a folder named by the configuration used: @@ -307,13 +306,13 @@ Resources Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheet: :adi:`CN0506` -- ADIN1300 datasheet: :adi:`ADIN1300` +- Product datasheet: :adi:`CN0506` +- ADIN1300 datasheet: :adi:`ADIN1300` HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`CN0506 HDL project source code ` +- :git-hdl:`CN0506 HDL project source code ` .. list-table:: :widths: 30 35 35 @@ -350,46 +349,30 @@ HDL related .. admonition:: Legend :class: note - - ``*`` instantiated only for Zed and ZC706 carriers - - ``**`` instantiated only for Zed carrier - - ``***`` instantiated only for Zed, ZC706 and ZCU102 carriers + - ``*`` instantiated only for Zed and ZC706 carriers + - ``**`` instantiated only for Zed carrier + - ``***`` instantiated only for Zed, ZC706 and ZCU102 carriers Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-linux:`CN0506 MII dtsi source code (arm32) ` - -- :git-linux:`CN0506 RGMII dtsi source code (arm32) ` - -- :git-linux:`CN0506 RMII dtsi source code (arm32) ` - -- :git-linux:`CN0506 MII dtsi source code (arm64) ` - -- :git-linux:`CN0506 RGMII dtsi source code (arm64) ` - -- :git-linux:`CN0506 RMII dtsi source code (arm64) ` - -- :git-linux:`CN0506 MII - A10SOC dts source code (arm32) ` - -- :git-linux:`CN0506 MII - ZCU102 dts source code (arm64) ` - -- :git-linux:`CN0506 RGMII - ZCU102 dts source code (arm64) ` - -- :git-linux:`CN0506 RMII - ZCU102 dts source code (arm64) ` - -- :git-linux:`CN0506 MII - ZC706 dts source code (arm32) ` - -- :git-linux:`CN0506 RGMII - ZC706 dts source code (arm32) ` - -- :git-linux:`CN0506 RMII - ZC706 dts source code (arm32) ` - -- :git-linux:`CN0506 MII - ZED dts source code (arm32) ` - -- :git-linux:`CN0506 RGMII - ZED dts source code (arm32) ` - -- :git-linux:`CN0506 RMII - ZED dts source code (arm32) ` - -- :dokuwiki:`ADIN1300 driver docs ` +- :git-linux:`CN0506 MII dtsi source code (arm32) ` +- :git-linux:`CN0506 RGMII dtsi source code (arm32) ` +- :git-linux:`CN0506 RMII dtsi source code (arm32) ` +- :git-linux:`CN0506 MII dtsi source code (arm64) ` +- :git-linux:`CN0506 RGMII dtsi source code (arm64) ` +- :git-linux:`CN0506 RMII dtsi source code (arm64) ` +- :git-linux:`CN0506 MII - A10SOC dts source code (arm32) ` +- :git-linux:`CN0506 MII - ZCU102 dts source code (arm64) ` +- :git-linux:`CN0506 RGMII - ZCU102 dts source code (arm64) ` +- :git-linux:`CN0506 RMII - ZCU102 dts source code (arm64) ` +- :git-linux:`CN0506 MII - ZC706 dts source code (arm32) ` +- :git-linux:`CN0506 RGMII - ZC706 dts source code (arm32) ` +- :git-linux:`CN0506 RMII - ZC706 dts source code (arm32) ` +- :git-linux:`CN0506 MII - ZED dts source code (arm32) ` +- :git-linux:`CN0506 RGMII - ZED dts source code (arm32) ` +- :git-linux:`CN0506 RMII - ZED dts source code (arm32) ` +- :dokuwiki:`ADIN1300 driver docs ` .. include:: ../common/more_information.rst diff --git a/docs/projects/cn0540/index.rst b/docs/projects/cn0540/index.rst index cbc96bcd90..864b472c66 100644 --- a/docs/projects/cn0540/index.rst +++ b/docs/projects/cn0540/index.rst @@ -30,21 +30,21 @@ capturing continuous samples at the maximum sample rate. Supported boards ------------------------------------------------------------------------------- -- :adi:`EVAL-CN0540-ARDZ ` +- :adi:`EVAL-CN0540-ARDZ ` Supported devices ------------------------------------------------------------------------------- -- :adi:`AD7768-1` -- :adi:`ADA4945-1` -- :adi:`LT3092` -- :adi:`LTC2606` +- :adi:`AD7768-1` +- :adi:`ADA4945-1` +- :adi:`LT3092` +- :adi:`LTC2606` Supported carriers ------------------------------------------------------------------------------- -- :xilinx:`Cora Z7S ` Arduino shield connector -- :intel:`DE10-Nano ` Arduino shield connector +- :xilinx:`Cora Z7S ` Arduino shield connector +- :intel:`DE10-Nano ` Arduino shield connector Block design ------------------------------------------------------------------------------- @@ -91,8 +91,8 @@ axi_spi_engine_0** 0x0003_0000 .. admonition:: Legend :class: note - - ``*`` instantiated only for Cora Z7S - - ``**`` instantiated only for DE10-Nano + - ``*`` instantiated only for Cora Z7S + - ``**`` instantiated only for DE10-Nano I2C connections ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -138,7 +138,7 @@ GPIOs The Software GPIO number is calculated as follows: -- Cora Z7S: the offset is 54 +- Cora Z7S: the offset is 54 .. list-table:: :widths: 25 25 25 25 @@ -189,7 +189,7 @@ The Software GPIO number is calculated as follows: - 32 - 86 -- DE10-Nano: the offset is 32 +- DE10-Nano: the offset is 32 .. list-table:: :widths: 25 25 25 25 @@ -273,11 +273,10 @@ the HDL repository, and then build the project as follows: **Linux/Cygwin/WSL** -.. code-block:: - :linenos: +.. shell:: - user@analog:~$ cd hdl/projects/cn0540/coraz7s - user@analog:~/hdl/projects/cn0540/coraz7s$ make + $cd hdl/projects/cn0540/coraz7s + $make A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. @@ -307,8 +306,8 @@ Hardware related HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`CN0540_ARDZ HDL project source code ` -- :dokuwiki:`[Wiki] CN0540 HDL project documentation ` +- :git-hdl:`CN0540_ARDZ HDL project source code ` +- :dokuwiki:`[Wiki] CN0540 HDL project documentation ` .. list-table:: :widths: 30 35 35 @@ -348,10 +347,10 @@ HDL related .. admonition:: Legend :class: note - - ``*`` instantiated only for Cora Z7S - - ``**`` instantiated only for DE10-Nano + - ``*`` instantiated only for Cora Z7S + - ``**`` instantiated only for DE10-Nano -- :ref:`SPI Engine Framework documentation ` +- :ref:`SPI Engine Framework documentation ` Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/projects/cn0561/index.rst b/docs/projects/cn0561/index.rst index 63380ada6e..4f1147d141 100644 --- a/docs/projects/cn0561/index.rst +++ b/docs/projects/cn0561/index.rst @@ -203,10 +203,10 @@ the HDL repository, and then build the project as follows:. **Linux/Cygwin/WSL** -.. code-block:: +.. shell:: - user@analog:~$ cd hdl/projects/cn0561/zed - user@analog:~/hdl/projects/cn0561/zed$ make + $cd hdl/projects/cn0561/zed + $make A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. diff --git a/docs/projects/cn0577/index.rst b/docs/projects/cn0577/index.rst index 3fe84dbbf5..004dd7c139 100644 --- a/docs/projects/cn0577/index.rst +++ b/docs/projects/cn0577/index.rst @@ -23,18 +23,18 @@ application, through setting a parameter. Supported boards ------------------------------------------------------------------------------- -- :adi:`CN0577` +- :adi:`CN0577` Supported devices ------------------------------------------------------------------------------- -- :adi:`ADAQ23876` -- :adi:`LTC2387-18` +- :adi:`ADAQ23876` +- :adi:`LTC2387-18` Supported carriers ------------------------------------------------------------------------------- -- :xilinx:`ZedBoard ` on FMC slot +- :xilinx:`ZedBoard ` on FMC slot Block design ------------------------------------------------------------------------------- @@ -55,10 +55,10 @@ The data path and clock domains are depicted in the below diagram: Configuration modes ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - - TWOLANES: specifies the number of lanes used +- TWOLANES: specifies the number of lanes used - - 1 - two-lane output mode (default) - - 0 - one-lane output mode + - 1 - two-lane output mode (default) + - 0 - one-lane output mode Jumper setup ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -68,31 +68,31 @@ the device can act in different modes, as described below. Of course, the PD jumper overrides the PD signal from the FPGA. It is controlled by a one-bit-adc-dac, in software. - - P1 - configures PD_N +- P1 - configures PD_N - - Shorting pins 1 and 2 → PD_N = 1, device is not powered down - - Shorting pins 2 and 3 → PD_N = 0, device is powered down + - Shorting pins 1 and 2 → PD_N = 1, device is not powered down + - Shorting pins 2 and 3 → PD_N = 0, device is powered down - - P2 - configures TESTPAT +- P2 - configures TESTPAT - - Shorting pins 1 and 2 → TESTPAT = 1, pattern testing is active - - Shorting pins 2 and 3 → TESTPAT = 0, pattern testing is inactive + - Shorting pins 1 and 2 → TESTPAT = 1, pattern testing is active + - Shorting pins 2 and 3 → TESTPAT = 0, pattern testing is inactive - - P3 - configures TWOLANES parameter +- P3 - configures TWOLANES parameter - - Shorting pins 1 and 2 → TWOLANES = 1 (TWO LANES mode) - - Shorting pins 2 and 3 → TWOLANES = 0 (ONE LANE mode) + - Shorting pins 1 and 2 → TWOLANES = 1 (TWO LANES mode) + - Shorting pins 2 and 3 → TWOLANES = 0 (ONE LANE mode) Clock scheme ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- The clock architecture of the :adi:`CN0577` is designed - with careful consideration to ensure low jitter and low phase noise -- An on-board 120 MHz voltage controlled crystal oscillator (VCXO) is used to - provide the clock for the :adi:`CN0577` board and the FPGA. - It is further named as reference clock. This clock is gated and fed back to - the device as the sampling clock, on which the data was sampled -- The DMA runs on the ZynqPS clock FCLK_CLK0 which has a frequency of 100MHz +- The clock architecture of the :adi:`CN0577` is designed + with careful consideration to ensure low jitter and low phase noise +- An on-board 120 MHz voltage controlled crystal oscillator (VCXO) is used to + provide the clock for the :adi:`CN0577` board and the FPGA. + It is further named as reference clock. This clock is gated and fed back to + the device as the sampling clock, on which the data was sampled +- The DMA runs on the ZynqPS clock FCLK_CLK0 which has a frequency of 100MHz CPU/Memory interconnects addresses ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -160,19 +160,10 @@ the HDL repository. Default (two-lane mode): -.. code-block:: - :linenos: +.. shell:: - user@analog:~$ cd hdl/projects/cn0577/zed - user@analog:~/hdl/projects/cn0577/zed$ make - -If one-lane mode is desired: - -.. code-block:: - :linenos: - - user@analog:~$ cd hdl/projects/cn0577/zed - user@analog:~/hdl/projects/cn0577/zed$ make TWOLANES=0 + $cd hdl/projects/cn0577/zed + $make A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. @@ -183,22 +174,22 @@ Resources Systems related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :dokuwiki:`[Wiki] EVAL-CN0577-FMCZ User Guide ` -- :dokuwiki:`[Wiki] CN0577 HDL Reference Design ` +- :dokuwiki:`[Wiki] EVAL-CN0577-FMCZ User Guide ` +- :dokuwiki:`[Wiki] CN0577 HDL Reference Design ` Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheets: +- Product datasheets: - - :adi:`LTC2387-18` + - :adi:`LTC2387-18` -- `Circuit Note CN0577 `__ +- `Circuit Note CN0577 `__ HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`CN0577 HDL project source code ` +- :git-hdl:`CN0577 HDL project source code ` .. list-table:: :widths: 30 35 35 @@ -241,9 +232,9 @@ HDL related Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :dokuwiki:`[Wiki] LTC2387 SAR ADC IIO Linux driver page ` -- :git-linux:`CN0577 Linux device tree ` -- :git-linux:`LTC2387 Linux driver ` +- :dokuwiki:`[Wiki] LTC2387 SAR ADC IIO Linux driver page ` +- :git-linux:`CN0577 Linux device tree ` +- :git-linux:`LTC2387 Linux driver ` .. include:: ../common/more_information.rst diff --git a/docs/projects/cn0579/index.rst b/docs/projects/cn0579/index.rst index 2ecd91c158..2e3ce270da 100644 --- a/docs/projects/cn0579/index.rst +++ b/docs/projects/cn0579/index.rst @@ -22,15 +22,15 @@ techniques for system characterization and machine learning algorithms. Supported boards ------------------------------------------------------------------------------- -- :adi:`CN0579` +- :adi:`CN0579` Supported devices ------------------------------------------------------------------------------- -- :adi:`AD7768-4` -- :adi:`AD5696R` -- :adi:`ADA4945-1` -- :adi:`ADG5421F` +- :adi:`AD7768-4` +- :adi:`AD5696R` +- :adi:`ADA4945-1` +- :adi:`ADG5421F` Supported carriers ------------------------------------------------------------------------------- @@ -115,8 +115,8 @@ I2C connections .. admonition:: Legend :class: note - - ``*`` only for Cora Z7S - - ``**`` only for DE10-Nano + - ``*`` only for Cora Z7S + - ``**`` only for DE10-Nano SPI connections ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -141,8 +141,8 @@ SPI connections .. admonition:: Legend :class: note - - ``*`` only for Cora Z7S - - ``**`` only for DE10-Nano + - ``*`` only for Cora Z7S + - ``**`` only for DE10-Nano GPIOs ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -183,8 +183,8 @@ cn0579_dma** 5 --- --- 45 77 .. admonition:: Legend :class: note - - ``*`` only for Cora Z7S - - ``**`` only for DE10-Nano + - ``*`` only for Cora Z7S + - ``**`` only for DE10-Nano Building the HDL project ------------------------------------------------------------------------------- @@ -201,19 +201,17 @@ the HDL repository, and then build the project as follows: Building the CoraZ7S project: -.. code-block:: bash - :linenos: +.. shell:: - user@analog:~$ cd hdl/projects/cn0579/coraz7s - user@analog:~/hdl/projects/cn0579/coraz7s$ make + $cd hdl/projects/cn0579/coraz7s + $make Building the DE-10Nano project: -.. code-block:: bash - :linenos: +.. shell:: - user@analog:~$ cd hdl/projects/cn0579/de10nano - user@analog:~/hdl/projects/cn0579/de10nano$ make + $cd hdl/projects/cn0579/de10nano + $make A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. @@ -223,23 +221,23 @@ Resources Systems related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :dokuwiki:`[Wiki] EVAL-CN0579-ARDZ User Guide ` -- :adi:`Circuit Note CN0579 ` +- :dokuwiki:`[Wiki] EVAL-CN0579-ARDZ User Guide ` +- :adi:`Circuit Note CN0579 ` Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheets: +- Product datasheets: - - :adi:`AD7768-4` - - :adi:`AD5696R` - - :adi:`ADA4945-1` - - :adi:`ADG5421F` + - :adi:`AD7768-4` + - :adi:`AD5696R` + - :adi:`ADA4945-1` + - :adi:`ADG5421F` HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`CN0579 HDL project source code ` +- :git-hdl:`CN0579 HDL project source code ` .. list-table:: :widths: 30 35 35 @@ -267,19 +265,19 @@ HDL related Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :dokuwiki:`[Wiki] AD7768 IIO Precision ADC Linux Driver ` +- :dokuwiki:`[Wiki] AD7768 IIO Precision ADC Linux Driver ` -- Python support: +- Python support: - :git-pyadi-iio:`PyADI-IIO documentation ` - :git-pyadi-iio:`PyADI-IIO CN0579 class ` - :git-pyadi-iio:`PyADI-IIO CN0579 example ` -- CN0579 on Cora Z7s Linux device tree +- CN0579 on Cora Z7s Linux device tree :git-linux:`arch/arm/boot/dts/zynq-coraz7s-cn0579_i2c.dts` -- CN0579 on DE-10Nano Linux device tree +- CN0579 on DE-10Nano Linux device tree :git-linux:`arch/arm/boot/dts/socfpga_cyclone5_de10_nano_cn0579_i2c.dts` -- AD7768 Linux driver :git-linux:`ad7768.c ` +- AD7768 Linux driver :git-linux:`ad7768.c ` .. include:: ../common/more_information.rst diff --git a/docs/projects/cn0585/index.rst b/docs/projects/cn0585/index.rst index ab6a464ac1..ce08908915 100644 --- a/docs/projects/cn0585/index.rst +++ b/docs/projects/cn0585/index.rst @@ -18,17 +18,17 @@ together to build a development system setup. Supported boards ------------------------------------------------------------------------------- -- :adi:`CN0585 ` -- :adi:`CN0584 ` +- :adi:`CN0585 ` +- :adi:`CN0584 ` Supported devices ------------------------------------------------------------------------------- -- :adi:`AD3552R` -- :adi:`ADAQ23876` -- :adi:`AD7291` -- :adi:`ADG5421F` -- :adi:`MAX7301` +- :adi:`AD3552R` +- :adi:`ADAQ23876` +- :adi:`AD7291` +- :adi:`ADG5421F` +- :adi:`MAX7301` Supported carriers ------------------------------------------------------------------------------- @@ -192,11 +192,10 @@ If you want to build the sources, ADI makes them available on the `clone `__ the HDL repository. -.. code-block:: - :linenos: +.. shell:: - user@analog:~$ cd hdl/projects/cn0585/zed - user@analog:~/hdl/projects/cn0585/zed$ make + $cd hdl/projects/cn0585/zed + $make A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. @@ -207,25 +206,25 @@ Resources Systems related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :dokuwiki:`[Wiki] EVAL-CN0585-FMCZ User Guide ` -- :dokuwiki:`[Wiki] CN0584 User Guide ` +- :dokuwiki:`[Wiki] EVAL-CN0585-FMCZ User Guide ` +- :dokuwiki:`[Wiki] CN0584 User Guide ` Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheets: +- Product datasheets: - - :adi:`ADAQ23876` - - :adi:`AD3552R` - - :adi:`AD7291` - - :adi:`MAX7301` -- `Circuit Note CN-0585 `__ -- `Circuit Note CN-0584 `__ + - :adi:`ADAQ23876` + - :adi:`AD3552R` + - :adi:`AD7291` + - :adi:`MAX7301` +- `Circuit Note CN-0585 `__ +- `Circuit Note CN-0584 `__ HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`CN0585 HDL project source code ` +- :git-hdl:`CN0585 HDL project source code ` .. list-table:: :widths: 30 35 35 @@ -274,12 +273,12 @@ HDL related Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :dokuwiki:`[Wiki] AD3552R Dual Channel, 16-Bit, 33 MUPS, Multispan, Multi-IO SPI DAC Linux device driver page ` -- :dokuwiki:`[Wiki] LTC2387 SAR ADC IIO Linux driver page ` +- :dokuwiki:`[Wiki] AD3552R Dual Channel, 16-Bit, 33 MUPS, Multispan, Multi-IO SPI DAC Linux device driver page ` +- :dokuwiki:`[Wiki] LTC2387 SAR ADC IIO Linux driver page ` -- Python support: +- Python support: - - `PyADI-IIO documentation `__ + - `PyADI-IIO documentation `__ .. include:: ../common/more_information.rst diff --git a/docs/projects/max96724/index.rst b/docs/projects/max96724/index.rst index af797ab4fa..778e940234 100644 --- a/docs/projects/max96724/index.rst +++ b/docs/projects/max96724/index.rst @@ -23,29 +23,29 @@ standard FAKRA coaxial cables. Supported boards ------------------------------------------------------------------------------- -- :adi:`MAX96724 DPHY Evaluation Kit (EV Kit) ` +- :adi:`MAX96724 DPHY Evaluation Kit (EV Kit) ` Supported devices ------------------------------------------------------------------------------- -- :adi:`MAX9724` +- :adi:`MAX9724` Supported carriers ------------------------------------------------------------------------------- -- :xilinx:`KV260 Vision Evaluation Kit ` using Raspberry Pi camera interface +- :xilinx:`KV260 Vision Evaluation Kit ` using Raspberry Pi camera interface Block design ------------------------------------------------------------------------------- The data path designed in this reference design is as follows: -- the virtual channel inputs of one CSI-2 output port of the deserializer are - captured using Xilinx's `MIPI CSI-2 Rx Subsystem IP `_ -- data is written into memory by using a Xilinx video-related DMA implementation - `Video Framebuffer Write `_ -- the control of the camera modules is realized through I2C using Xilinx's - `AXI IIC logic `_ +- the virtual channel inputs of one CSI-2 output port of the deserializer are + captured using Xilinx's `MIPI CSI-2 Rx Subsystem IP `_ +- data is written into memory by using a Xilinx video-related DMA implementation + `Video Framebuffer Write `_ +- the control of the camera modules is realized through I2C using Xilinx's + `AXI IIC logic `_ Block diagram ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -99,7 +99,7 @@ GPIOs The Software GPIO number is calculated as follows: -- ZynqMP: if PS8 EMIOs are used, then offset is 78 +- ZynqMP: if PS8 EMIOs are used, then offset is 78 .. list-table:: :widths: 25 25 25 25 @@ -171,11 +171,10 @@ the HDL repository, and then build the project as follows: **Linux/Cygwin/WSL** -.. code-block:: - :linenos: +.. shell:: - user@analog:~$ cd hdl/projects/max96724/kv260 - user@analog:~/hdl/projects/max96724/kv260$ make + $cd hdl/projects/max96724/kv260 + $make A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. @@ -185,15 +184,15 @@ Resources Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheets: +- Product datasheets: - - :adi:`MAX96724 ` - - :adi:`MAX96724 DPHY Evaluation Kit (EV Kit) ` + - :adi:`MAX96724 ` + - :adi:`MAX96724 DPHY Evaluation Kit (EV Kit) ` HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`MAX96724 HDL project source code ` +- :git-hdl:`MAX96724 HDL project source code ` .. list-table:: :widths: 30 35 35 @@ -208,9 +207,11 @@ HDL related Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- `GMSL-related repository `_ -- The user guide that exemplify the system interfaced using :adi:`AD-GMSLCAMRPI-ADP adaptor ` is available in wiki `page `_ -- :git-linux:`GMSL drivers/dts ` +- `GMSL-related repository `_ +- The user guide that exemplify the system interfaced using + :adi:`AD-GMSLCAMRPI-ADP adaptor ` is available at + :dokuwiki:`wiki page ` +- :git-linux:`GMSL drivers/dts ` .. include:: ../common/more_information.rst diff --git a/docs/projects/pulsar_adc/index.rst b/docs/projects/pulsar_adc/index.rst index d63ee05b43..0b7747a366 100644 --- a/docs/projects/pulsar_adc/index.rst +++ b/docs/projects/pulsar_adc/index.rst @@ -71,66 +71,66 @@ Supported boards PulSAR with PMOD connector: -- :adi:`EVAL-AD7685-PMDZ` -- :adi:`EVAL-AD7686-PMDZ` -- :adi:`EVAL-AD7687-PMDZ` -- :adi:`EVAL-AD7688-PMDZ` -- :adi:`EVAL-AD7690-PMDZ` -- :adi:`EVAL-AD7691-PMDZ` -- :adi:`EVAL-AD7693-PMDZ` -- :adi:`EVAL-AD7942-PMDZ` -- :adi:`EVAL-AD7946-PMDZ` -- :adi:`EVAL-AD7980-PMDZ` -- :adi:`EVAL-AD7982-PMDZ` -- :adi:`EVAL-AD7983-PMDZ` -- :adi:`EVAL-AD7984-PMDZ` -- :adi:`EVAL-AD7988-1-PMDZ` -- :adi:`EVAL-AD7988-5-PMDZ` -- :adi:`EVAL-ADAQ40xx` +- :adi:`EVAL-AD7685-PMDZ` +- :adi:`EVAL-AD7686-PMDZ` +- :adi:`EVAL-AD7687-PMDZ` +- :adi:`EVAL-AD7688-PMDZ` +- :adi:`EVAL-AD7690-PMDZ` +- :adi:`EVAL-AD7691-PMDZ` +- :adi:`EVAL-AD7693-PMDZ` +- :adi:`EVAL-AD7942-PMDZ` +- :adi:`EVAL-AD7946-PMDZ` +- :adi:`EVAL-AD7980-PMDZ` +- :adi:`EVAL-AD7982-PMDZ` +- :adi:`EVAL-AD7983-PMDZ` +- :adi:`EVAL-AD7984-PMDZ` +- :adi:`EVAL-AD7988-1-PMDZ` +- :adi:`EVAL-AD7988-5-PMDZ` +- :adi:`EVAL-ADAQ40xx` PulSAR with FMC connector: -- :adi:`EVAL-AD400x-FMCZ` +- :adi:`EVAL-AD400x-FMCZ` Supported devices ------------------------------------------------------------------------------- PulSAR with PMOD connector: -- :adi:`AD7685` -- :adi:`AD7686` -- :adi:`AD7687` -- :adi:`AD7688` -- :adi:`AD7690` -- :adi:`AD7691` -- :adi:`AD7693` -- :adi:`AD7942` -- :adi:`AD7946` -- :adi:`AD7980` -- :adi:`AD7982` -- :adi:`AD7983` -- :adi:`AD7984` -- :adi:`AD7988-1` -- :adi:`AD7988-5` -- :adi:`ADAQ4003` +- :adi:`AD7685` +- :adi:`AD7686` +- :adi:`AD7687` +- :adi:`AD7688` +- :adi:`AD7690` +- :adi:`AD7691` +- :adi:`AD7693` +- :adi:`AD7942` +- :adi:`AD7946` +- :adi:`AD7980` +- :adi:`AD7982` +- :adi:`AD7983` +- :adi:`AD7984` +- :adi:`AD7988-1` +- :adi:`AD7988-5` +- :adi:`ADAQ4003` PulSAR with FMC connector: -- :adi:`AD4003` -- :adi:`AD4007` -- :adi:`AD4011` -- :adi:`AD4020` +- :adi:`AD4003` +- :adi:`AD4007` +- :adi:`AD4011` +- :adi:`AD4020` Supported carriers ------------------------------------------------------------------------------- -- :xilinx:`Cora Z7S ` PMOD connector -- :xilinx:`ZedBoard ` on FMC slot +- :xilinx:`Cora Z7S ` PMOD connector +- :xilinx:`ZedBoard ` on FMC slot Other required hardware ------------------------------------------------------------------------------- -- :adi:`EVAL-PMD-IB1Z` +- :adi:`EVAL-PMD-IB1Z` .. note:: @@ -168,18 +168,18 @@ connector or the Pmod JA connector. The ``FMC_N_PMOD`` parameter is used to select between the them: -* 0 - for PMOD -* 1 - for FMC (default) +- 0 - for PMOD +- 1 - for FMC (default) The PulSAR project supports different configurations required for certain ADCs, like the AD7944. These modes are selected using the ``SPI_OP_MODE`` parameter: -* 0 - for normal SPI Engine connections (default) -* 1 - for 3-wire "single" mode where CS drives the SDO line while the CS line - is driven by GPIO -* 2 - SDO is driven by GPIO and the CS line is driven by CS. +- 0 - for normal SPI Engine connections (default) +- 1 - for 3-wire "single" mode where CS drives the SDO line while the CS line + is driven by GPIO +- 2 - SDO is driven by GPIO and the CS line is driven by CS. .. caution:: @@ -248,7 +248,7 @@ GPIOs The Software GPIO number is calculated as follows: -- Zynq-7000: if PS7 is used, then offset is 54 +- Zynq-7000: if PS7 is used, then offset is 54 .. list-table:: :widths: 40 25 25 25 @@ -278,8 +278,8 @@ The Software GPIO number is calculated as follows: .. admonition:: Legend :class: note - - ``*`` instantiated only for PulSAR_ADC_PMDZ projects - - ``**`` instantiated only for FMC_N_PMOD=1 (AD40xx) + - ``*`` instantiated only for PulSAR_ADC_PMDZ projects + - ``**`` instantiated only for FMC_N_PMOD=1 (AD40xx) Interrupts ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -306,44 +306,43 @@ the HDL repository, and then build the project as follows:. **Linux/Cygwin/WSL** -.. code-block:: - :linenos: +.. shell:: bash - user@analog:~$ cd hdl/projects/pulsar_adc/zed - user@analog:~/hdl/projects/pulsar_adc/zed$ make FMC_N_PMOD=1 SPI_OP_MODE=0 + $cd hdl/projects/pulsar_adc/zed + $make FMC_N_PMOD=1 SPI_OP_MODE=0 Build examples: Zedboard Pmod support -.. code-block:: +.. shell:: bash - make FMC_N_PMOD=0 + $make FMC_N_PMOD=0 Zedboard standard configuration FMC support (default) -.. code-block:: +.. shell:: bash - make FMC_N_PMOD=1 SPI_OP_MODE=0 - builds standard FMC version + $make FMC_N_PMOD=1 SPI_OP_MODE=0 - builds standard FMC version Zedboard FMC support for AD7944 4-wire mode ("multi") -.. code-block:: +.. shell:: bash - make FMC_N_PMOD=1 SPI_OP_MODE=1 + $make FMC_N_PMOD=1 SPI_OP_MODE=1 Zedboard FMC support for AD7944 chain mode or 3-wire "single" -.. code-block:: +.. shell:: bash - make FMC_N_PMOD=1 SPI_OP_MODE=2 + $make FMC_N_PMOD=1 SPI_OP_MODE=2 The result of the build, if parameters were used, will be in a folder named by the used configuration. If the following command was run -.. code-block:: +.. shell:: bash - make FMC_N_PMOD=1 SPI_OP_MODE=0 + $make FMC_N_PMOD=1 SPI_OP_MODE=0 then the folder name will be: @@ -363,41 +362,41 @@ Hardware related Datasheets for PulSAR with PMOD connector: -- :adi:`AD7942` -- :adi:`AD7946` -- :adi:`AD7988-1` -- :adi:`AD7685` -- :adi:`AD7687` -- :adi:`AD7691` -- :adi:`AD7686` -- :adi:`AD7688` -- :adi:`AD7693` -- :adi:`AD7988-5` -- :adi:`AD7980` -- :adi:`AD7983` -- :adi:`AD7690` -- :adi:`AD7982` -- :adi:`AD7984` -- :adi:`UG-682, Evaluation Board User Guide ` -- :adi:`UG-340, Evaluation Board User Guide ` +- :adi:`AD7942` +- :adi:`AD7946` +- :adi:`AD7988-1` +- :adi:`AD7685` +- :adi:`AD7687` +- :adi:`AD7691` +- :adi:`AD7686` +- :adi:`AD7688` +- :adi:`AD7693` +- :adi:`AD7988-5` +- :adi:`AD7980` +- :adi:`AD7983` +- :adi:`AD7690` +- :adi:`AD7982` +- :adi:`AD7984` +- :adi:`UG-682, Evaluation Board User Guide ` +- :adi:`UG-340, Evaluation Board User Guide ` Datasheets PulSAR with FMC connector: -- :adi:`AD4003` -- :adi:`AD4007` -- :adi:`AD4011` -- :adi:`AD4020` -- :adi:`ADAQ4003` -- :adi:`UG-1042, Evaluation Board User Guide ` -- :adi:`UG-1042, Evaluation Board User Guide ` +- :adi:`AD4003` +- :adi:`AD4007` +- :adi:`AD4011` +- :adi:`AD4020` +- :adi:`ADAQ4003` +- :adi:`UG-1042, Evaluation Board User Guide ` +- :adi:`UG-1042, Evaluation Board User Guide ` HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`pulsar_adc HDL project source code ` -- :dokuwiki:`[Wiki] PulSAR ADC PMOD HDL start guide ` -- :dokuwiki:`[Wiki] PulSAR ADC PMOD quick start guide ` -- :dokuwiki:`[Wiki] AD40xx/ADAQ40xx quick start guide ` +- :git-hdl:`pulsar_adc HDL project source code ` +- :dokuwiki:`[Wiki] PulSAR ADC PMOD HDL start guide ` +- :dokuwiki:`[Wiki] PulSAR ADC PMOD quick start guide ` +- :dokuwiki:`[Wiki] AD40xx/ADAQ40xx quick start guide ` .. list-table:: :widths: 30 40 30 @@ -451,7 +450,7 @@ HDL related ``*`` instantiated only for AD40xx/ADAQ40xx -- :ref:`SPI Engine Framework documentation ` +- :ref:`SPI Engine Framework documentation ` Software related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/projects/pulsar_lvds/index.rst b/docs/projects/pulsar_lvds/index.rst index b3915eb9ec..98bc9daa9e 100644 --- a/docs/projects/pulsar_lvds/index.rst +++ b/docs/projects/pulsar_lvds/index.rst @@ -47,34 +47,34 @@ Applications: Supported boards ------------------------------------------------------------------------------- -- :adi:`EVAL-AD7625-FMCZ ` -- :adi:`EVAL-AD7626-FMCZ ` -- :adi:`EVAL-AD7960-FMCZ ` -- :adi:`EVAL-AD7961-FMCZ ` +- :adi:`EVAL-AD7625` +- :adi:`EVAL-AD7626` +- :adi:`EVAL-AD7960` +- :adi:`EVAL-AD7961` Supported devices ------------------------------------------------------------------------------- -- :adi:`AD7625` -- :adi:`AD7626` -- :adi:`AD7960` -- :adi:`AD7961` -- :adi:`ADR3412` -- :adi:`ADR4520` -- :adi:`AD74540` -- :adi:`AD4550` -- :adi:`AD8031` -- :adi:`ADA4899-1` -- :adi:`ADA4897-1` -- :adi:`ADP7102` -- :adi:`ADP7104` -- :adi:`ADP124` -- :adi:`ADP2300` +- :adi:`AD7625` +- :adi:`AD7626` +- :adi:`AD7960` +- :adi:`AD7961` +- :adi:`ADR3412` +- :adi:`ADR4520` +- :adi:`AD74540` +- :adi:`AD4550` +- :adi:`AD8031` +- :adi:`ADA4899-1` +- :adi:`ADA4897-1` +- :adi:`ADP7102` +- :adi:`ADP7104` +- :adi:`ADP124` +- :adi:`ADP2300` Supported carriers ------------------------------------------------------------------------------- -- :xilinx:`ZedBoard ` on FMC slot +- :xilinx:`ZedBoard ` on FMC slot Block design ------------------------------------------------------------------------------- @@ -97,15 +97,15 @@ hardware modifications need to be done on the board and/or make command: In case of the **AD7960** project: -.. code-block:: +.. shell:: bash - make RESOLUTION_16_18N=0 + $make RESOLUTION_16_18N=0 In case of the **AD7625/AD7626/AD7961** project: -.. code-block:: +.. shell:: bash - make RESOLUTION_16_18N=1 + $make RESOLUTION_16_18N=1 Jumper setup AD7625/AD7626 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -204,7 +204,7 @@ GPIOs The Software GPIO number is calculated as follows: -- Zynq-7000: if PS7 is used, then offset is 54 +- Zynq-7000: if PS7 is used, then offset is 54 .. list-table:: :widths: 25 25 25 25 @@ -238,7 +238,7 @@ The Software GPIO number is calculated as follows: .. admonition:: Legend :class: note - - ``**`` instantiated only for AD7960/AD7961 + - ``**`` instantiated only for AD7960/AD7961 Interrupts ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -264,11 +264,10 @@ the HDL repository, and then build the project as follows: **Linux/Cygwin/WSL** -.. code-block:: - :linenos: +.. shell:: bash - user@analog:~$ cd hdl/projects/pulsar_lvds_adc/zed - user@analog:~/hdl/projects/pulsar_lvds_adc/zed$ make RESOLUTION_16_18N=0 + $cd hdl/projects/pulsar_lvds_adc/zed + $make RESOLUTION_16_18N=0 The result of the build, if parameters were used, will be in a folder named by the configuration used: @@ -289,20 +288,20 @@ Resources Hardware related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- Product datasheets: +- Product datasheets: - - :adi:`AD7625` - - :adi:`AD7626` - - :adi:`AD7960` - - :adi:`AD7961` - - :adi:`UG-745, Evaluation Board User Guide ` - - :adi:`UG-490, Evaluation Board User Guide ` - - :adi:`UG-581, Evaluation Board User Guide ` + - :adi:`AD7625` + - :adi:`AD7626` + - :adi:`AD7960` + - :adi:`AD7961` + - :adi:`UG-745, Evaluation Board User Guide ` + - :adi:`UG-490, Evaluation Board User Guide ` + - :adi:`UG-581, Evaluation Board User Guide ` HDL related ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -- :git-hdl:`PULSAR_LVDS HDL project source code ` +- :git-hdl:`PULSAR_LVDS HDL project source code ` .. list-table:: :widths: 30 35 35 diff --git a/docs/user_guide/architecture.rst b/docs/user_guide/architecture.rst index ddc479bed8..5c68ecaff0 100644 --- a/docs/user_guide/architecture.rst +++ b/docs/user_guide/architecture.rst @@ -40,10 +40,11 @@ Take :adi:`AD-FMCOMMS2 ` with :xilinx:`ZedBoard `; the ``system_bd.tcl`` will look like the following: -.. shell:: +.. shell:: bash + :no-path: - source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl - source ../common/fmcomms2_bd.tcl + $source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl + $source ../common/fmcomms2_bd.tcl Typical project diagram -------------------------------------------------------------------------------