+ +
+

AD7405-FMC HDL project#

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+

Overview#

+

The EVAL-AD7405 is a full-featured evaluation board +designed to allow the user to easily evaluate all features of the AD7405 +isolated analog-to-digital converter (ADC).

+

The provided HDL reference design supports the AD7405 , AD7403 +and ADuM7701 devices. +One of the main differences between these devices is the type of the digital +data lines. In the case of ADuM7701 and AD7403, it is +single-ended, and for AD7405 is differential.

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Supported boards#

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Supported devices#

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Supported carriers#

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+ +++++ + + + + + + + + + + + + + + + + + + + + +

Evaluation board

Carrier

FMC slot

EVAL-AD7405

ZedBoard

FMC-LPC

EVAL-AD7403

ZedBoard

FMC-LPC

EVAL-ADuM7701

ZedBoard

FMC-LPC

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+
+
+

Block design#

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+

Block diagram#

+

The data path and clock domains are depicted in the below diagrams:

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+

Block design for the differential signals (AD7405)#

+AD7405_FMC/ZedBoard block diagram +
+
+

Block design for the single-ended signals (ADuM7701 and AD7403)#

+AD7405_FMC/ZedBoard block diagram +
+
+
+

Configuration modes#

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    +

  • LVDS_CMOS_N: specific to the type of the data and clock signals

    +
      +

    • 0 - Single-ended data and clock signals (default)

      • +

    • 1 - Differential data and clock signals

      • +
    +
    • +
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+

CPU/Memory interconnects addresses#

+

The addresses are dependent on the architecture of the FPGA, having an offset +added to the base address from HDL (see more at HDL Architecture).

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+ + + + + + + + + + + + + + +

Instance

Zynq/Microblaze

axi_ad7405_dma

0x44A3_0000

axi_adc_clkgen

0x44A4_0000

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+
+
+

GPIOs#

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+ +++++++ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

GPIO signal

Direction

HDL GPIO EMIO

Software GPIO

Software GPIO

(from FPGA view)

Zynq-7000

Zynq MP

filter_reset

INOUT

48

102

124

decimation_ratio[15:0]

INOUT

47:32

101:86

125:110

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+
+
+

Interrupts#

+

Below are the Programmable Logic interrupts used in this project.

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+ + + + + + + + + + + + + + + +

Instance name

HDL

Linux Zynq

Actual Zynq

axi_ad7405_dma

13

57

89

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+
+
+
+

Building the HDL project#

+

The design is built upon ADI’s generic HDL reference design framework. +ADI distributes the bit/elf files of these projects as part of the +ADI Kuiper Linux. +If you want to build the sources, ADI makes them available on the +HDL repository. To get the source you must +clone +the HDL repository.

+

Default (Single-ended data and clock signals):

+
1user@analog:~$ cd hdl/projects/ad7405/zed
+2user@analog:~/hdl/projects/ad7405/zed$ make
+
+
+

If differential data and clock signals are desired:

+
1user@analog:~$ cd hdl/projects/ad7405/zed
+2user@analog:~/hdl/projects/ad7405/zed$ make LVDS_CMOS_N=1
+
+
+

A more comprehensive build guide can be found in the Build an HDL project user guide.

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Resources#

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More information#

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Support#

+

Analog Devices, Inc. will provide limited online support for anyone +using the reference design with ADI components via the +EngineerZone FPGA reference designs forum.

+

For questions regarding the ADI Linux device drivers, device trees, etc. +from our Linux GitHub repository, the team will offer support +on the EngineerZone Linux software drivers forum.

+

For questions concerning the ADI No-OS drivers, from our +No-OS GitHub repository, the team will offer support on the +EngineerZone microcontroller No-OS drivers forum.

+

It should be noted, that the older the tools’ versions and release branches +are, the lower the chances to receive support from ADI engineers.

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