From f384d6167024942792eafce9e20ef640a5e5228d Mon Sep 17 00:00:00 2001 From: Jorge Marques Date: Sun, 1 Oct 2023 20:16:05 -0300 Subject: [PATCH] i3c_controller: arbitration da, bcr lookup Better arbitration handling, check if the received DA is known, and if the IBI requester will send the MDB after the request (BCR[2] == 1). Signed-off-by: Jorge Marques --- docs/regmap/adi_regmap_i3c_controller.txt | 44 ++++-- .../i3c_controller_bit_mod.v | 14 +- .../i3c_controller_core/i3c_controller_core.v | 10 ++ .../i3c_controller_framing.v | 130 ++++++++++++++---- .../i3c_controller_core/i3c_controller_word.v | 41 ++++-- .../i3c_controller_word_cmd.v | 15 +- .../i3c_controller_cmd_parser.v | 6 +- .../i3c_controller_regmap.v | 4 +- .../ad405x_i3c_ardz/coraz7s/system_constr.xdc | 4 - 9 files changed, 197 insertions(+), 71 deletions(-) diff --git a/docs/regmap/adi_regmap_i3c_controller.txt b/docs/regmap/adi_regmap_i3c_controller.txt index d782192ff95..593e5343b40 100644 --- a/docs/regmap/adi_regmap_i3c_controller.txt +++ b/docs/regmap/adi_regmap_i3c_controller.txt @@ -117,18 +117,21 @@ FIELD IBI_ALMOST_FULL RW If set to 0 the IBI_ALMOST_FULL interrupt is masked. +ENDFIELD FIELD [5] 0x00 CMDR_PENDING RW If set to 0 the CMDR_PENDING interrupt is masked. +ENDFIELD FIELD [6] 0x00 IBI_PENDING RW If set to 0 the IBI_PENDING interrupt is masked. +ENDFIELD ############################################################################################ ############################################################################################ @@ -276,6 +279,27 @@ RO ENDFIELD +FIELD +[27:24] 0x?? +CMDR_FIFO_ERROR +RO +If an error occurred during the transfer. +ENDFIELD + +FIELD +[19:8] 0x?? +CMDR_FIFO_BUFFER_LENGTH +RO +Unsigned 12-bits transferred payload length. +ENDFIELD + +FIELD +[7:0] 0x?? +CMDR_FIFO_SYNC +RO +Command synchronization. +ENDFIELD + ############################################################################################ ############################################################################################ @@ -337,27 +361,24 @@ IBI_FIFO ENDREG FIELD -[31:24] 0x?? -IBI_FIFO_BYTE_3 -RO -ENDFIELD - -FIELD -[23:16] 0x?? -IBI_FIFO_BYTE_2 +[23:17] 0x?? +IBI_FIFO_DA RO +IBI Dynamic address. ENDFIELD FIELD [15:8] 0x?? -IBI_FIFO_BYTE_1 +IBI_FIFO_MDB RO +IBI MDB, if the peripheral's BCR[2] is Low, the field is ignored. ENDFIELD FIELD [7:0] 0x?? -IBI_FIFO_BYTE_0 +IBI_FIFO_SYNC RO +Synchronization number. ENDFIELD ############################################################################################ @@ -571,6 +592,9 @@ The Controller, index 0, is set to HIGH when a DA is written to DEV_CHAR_0_0, while the others peripherals are set HIGH when the peripherals actually receives the DA during the DAA. The state can also be overwritten to explicit attach device (e.g. has static addr). +A slot cannot be recycled, when the device is detached, it still keeps its slot in +case it is attached again, effectively, only its IBIs are rejectedin the detached +state. ENDFIELD FIELD diff --git a/library/i3c_controller/i3c_controller_core/i3c_controller_bit_mod.v b/library/i3c_controller/i3c_controller_core/i3c_controller_bit_mod.v index 5e7c4f40377..7aeb20e506c 100644 --- a/library/i3c_controller/i3c_controller_core/i3c_controller_bit_mod.v +++ b/library/i3c_controller/i3c_controller_core/i3c_controller_bit_mod.v @@ -55,9 +55,9 @@ module i3c_controller_bit_mod ( // 3: 1.56MHz input [1:0] scl_pp_sg, // SCL Push-pull speed grade - output reg rx, + output rx, output reg rx_raw, - output reg rx_valid, + output rx_valid, // Bus drive signals @@ -131,14 +131,12 @@ module i3c_controller_bit_mod ( always @(posedge clk) begin scl_high_reg <= scl_high; - rx_valid <= 1'b0; sdo <= sdo_w; - rx_raw <= sdi; - if (~scl_high_reg & scl_high) begin - rx <= sdi; // Multi-cycle-path worst-case: 4 clks (12.5MHz, half-bit ack) - rx_valid <= 1'b1; - end + rx_raw <= sdi === 1'b0 ? 1'b0 : 1'b1; end + // Multi-cycle-path worst-case: 4 clks (12.5MHz, half-bit ack) + assign rx = rx_raw; + assign rx_valid = ~scl_high_reg & scl_high; assign sdo_w = sm == `MOD_BIT_CMD_START_ ? (scl_high ? ~count[pp_sg+1] : 1'b1) : sm == `MOD_BIT_CMD_STOP_ ? (scl_high ? count[pp_sg+1] : 1'b0) : diff --git a/library/i3c_controller/i3c_controller_core/i3c_controller_core.v b/library/i3c_controller/i3c_controller_core/i3c_controller_core.v index 7edb302de62..f6a90606747 100644 --- a/library/i3c_controller/i3c_controller_core/i3c_controller_core.v +++ b/library/i3c_controller/i3c_controller_core/i3c_controller_core.v @@ -119,11 +119,14 @@ module i3c_controller_core #( wire cmdw_rx_valid; wire [7:0] cmdw_rx; + wire arbitration_valid; + wire ibi_bcr_2; wire ibi_requested; wire ibi_requested_auto; wire ibi_tick; wire [6:0] ibi_da; wire [7:0] ibi_mdb; + wire ibi_da_attached; wire [31:0] pid_bcr_dcr; wire pid_bcr_dcr_tick; @@ -164,8 +167,12 @@ module i3c_controller_core #( .cmdw_rx(cmdw_rx), .rx_raw(rx_raw), .cmd_nop(cmd_nop), + .arbitration_valid(arbitration_valid), + .ibi_bcr_2(ibi_bcr_2), .ibi_requested(ibi_requested), .ibi_requested_auto(ibi_requested_auto), + .ibi_da(ibi_da), + .ibi_da_attached(ibi_da_attached), .pid_bcr_dcr_tick(pid_bcr_dcr_tick), .pid_bcr_dcr(pid_bcr_dcr), .rmap_ibi_config(rmap_ibi_config), @@ -193,10 +200,13 @@ module i3c_controller_core #( .cmd_ready(cmd_ready), .rx(rx), .rx_valid(rx_valid), + .arbitration_valid(arbitration_valid), + .ibi_bcr_2(ibi_bcr_2), .ibi_requested(ibi_requested), .ibi_requested_auto(ibi_requested_auto), .ibi_tick(ibi_tick), .ibi_da(ibi_da), + .ibi_da_attached(ibi_da_attached), .ibi_mdb(ibi_mdb), .pid_bcr_dcr_tick(pid_bcr_dcr_tick), .pid_bcr_dcr(pid_bcr_dcr), diff --git a/library/i3c_controller/i3c_controller_core/i3c_controller_framing.v b/library/i3c_controller/i3c_controller_core/i3c_controller_framing.v index a5278c87dad..ba484de7c14 100644 --- a/library/i3c_controller/i3c_controller_core/i3c_controller_framing.v +++ b/library/i3c_controller/i3c_controller_core/i3c_controller_framing.v @@ -112,8 +112,12 @@ module i3c_controller_framing #( // IBI interface - input ibi_requested, - output reg ibi_requested_auto, + input arbitration_valid, + output ibi_bcr_2, + input ibi_requested, + output reg ibi_requested_auto, + input [6:0] ibi_da, + output ibi_da_attached, // DAA interface @@ -124,7 +128,7 @@ module i3c_controller_framing #( input [1:0] rmap_ibi_config, input [29:0] rmap_devs_ctrl_mr, - output reg [14:0] rmap_devs_ctrl, + output [14:0] rmap_devs_ctrl, output rmap_dev_char_e, output rmap_dev_char_we, output [5:0] rmap_dev_char_addr, @@ -144,13 +148,13 @@ module i3c_controller_framing #( reg [6:0] cmdp_da_reg; reg cmdp_rnw_reg; - reg ibi_requested_lock; - reg [`CMDW_HEADER_WIDTH:0] sm; reg [7:0] cmdw_body; reg sr; reg ctrl_daa; reg [3:0] j; + reg [15:0] devs_ctrl; // first bit is unused + reg [14:0] devs_ctrl_mask; reg [2:0] smt; localparam [2:0] @@ -159,7 +163,8 @@ module i3c_controller_framing #( setup_sdo = 2, cleanup = 3, seek = 4, - commit = 5; + commit = 5, + arbitration= 6; reg [0:0] smr; localparam [0:0] request = 0, @@ -175,7 +180,8 @@ module i3c_controller_framing #( smt <= setup; smr <= request; ctrl_daa <= 1'b0; - rmap_devs_ctrl <= 'd0; + devs_ctrl <= 'd1; + devs_ctrl_mask <= 15'hffff; j <= 0; ibi_requested_auto <= 1'b0; end else if (cmdw_nack) begin @@ -184,7 +190,7 @@ module i3c_controller_framing #( smr <= request; ctrl_daa <= 1'b0; end else begin - rmap_devs_ctrl <= (rmap_devs_ctrl | rmap_devs_ctrl_mr[14:0]) + devs_ctrl_mask <= (devs_ctrl_mask | rmap_devs_ctrl_mr[14:0]) & ~rmap_devs_ctrl_mr[29:15]; // SDI Ready is are not checked, data will be lost // if it do not accept/provide data when needed. @@ -211,20 +217,15 @@ module i3c_controller_framing #( cmdp_buffer_len_reg <= cmdp_buffer_len; cmdp_da_reg <= cmdp_da; cmdp_rnw_reg <= cmdp_rnw; - ibi_requested_lock <= 1'b0; end transfer: begin sr <= cmdp_sr_reg; - if (ibi_requested & ~ibi_requested_lock) begin - sm <= ibi_enable ? `CMDW_IBI_MDB : `CMDW_SR; - ibi_requested_lock <= 1'b1; - end if (cmdw_ready) begin ibi_requested_auto <= 1'b0; case(sm) `CMDW_NOP: begin smt <= setup; - j <= 0; + j <= 'd0; end `CMDW_SR, `CMDW_START: begin @@ -234,9 +235,7 @@ module i3c_controller_framing #( ctrl_daa <= 1'b0; end `CMDW_BCAST_7E_W0: begin - sm <= cmdp_ccc_reg ? - (cmdp_ccc_id_reg == CCC_ENTDAA ? `CMDW_CCC_OD : `CMDW_CCC_PP) : - `CMDW_MSG_SR; + smt <= arbitration; cmdw_body <= {cmdp_ccc_bcast_reg, cmdp_ccc_id_reg}; // Attention to BCAST here end `CMDW_CCC_OD: begin @@ -248,11 +247,10 @@ module i3c_controller_framing #( if (cmdp_ccc_bcast_reg) begin sm <= `CMDW_MSG_SR; end else if (cmdp_buffer_len_reg == 0) begin - sm <= `CMDW_STOP; + sm <= `CMDW_STOP_PP; smt <= sr ? setup : transfer; end else begin smt <= setup_sdo; - sm <= `CMDW_STOP; sm <= `CMDW_NOP; end end @@ -266,10 +264,10 @@ module i3c_controller_framing #( end `CMDW_DAA_DEV_CHAR_2: begin sm <= `CMDW_DYN_ADDR; - cmdw_body <= rmap_dev_char_rdata; + cmdw_body <= rmap_dev_char_rdata[7:0]; end `CMDW_DYN_ADDR: begin - sm <= j == MAX_DEVS ? `CMDW_STOP : `CMDW_START; + sm <= j == MAX_DEVS ? `CMDW_STOP_OD : `CMDW_START; smt <= commit; end `CMDW_MSG_SR: begin @@ -288,7 +286,7 @@ module i3c_controller_framing #( `CMDW_MSG_RX: begin cmdp_buffer_len_reg <= cmdp_buffer_len_reg - 1; if (~|cmdp_buffer_len_reg[11:1]) begin - sm <= `CMDW_STOP; + sm <= `CMDW_STOP_PP; smt <= sr ? setup : transfer; end end @@ -296,18 +294,19 @@ module i3c_controller_framing #( cmdp_buffer_len_reg <= cmdp_buffer_len_reg - 1; if (~|cmdp_buffer_len_reg[11:1]) begin smt <= sr ? setup : transfer; - sm <= `CMDW_STOP; + sm <= `CMDW_STOP_PP; end else begin smt <= setup_sdo; sm <= `CMDW_NOP; end end - `CMDW_STOP: begin + `CMDW_STOP_OD, + `CMDW_STOP_PP: begin sm <= `CMDW_NOP; cmdp_sr_reg <= 1'b0; end `CMDW_IBI_MDB: begin - sm <= cmdp_valid_reg ? `CMDW_SR : `CMDW_STOP; + sm <= cmdp_valid_reg ? `CMDW_SR : `CMDW_STOP_PP; end default: begin sm <= `CMDW_NOP; @@ -337,24 +336,49 @@ module i3c_controller_framing #( request: begin end read: begin - if (rmap_devs_ctrl[j] == 1'b0 & rmap_dev_char_rdata[8] == 1'b1) begin + if (devs_ctrl[j] == 1'b0 & rmap_dev_char_rdata[8] == 1'b1) begin smt <= transfer; end if (rmap_dev_char_rdata[8] == 1'b0) begin // If I2C, just set it as attached - rmap_devs_ctrl[j] <= 1'b1; + devs_ctrl[j] <= 1'b1; + end + if (devs_ctrl[j] == 1'b1) begin + j <= j + 1; end - j <= j + 1; end endcase smr <= ~smr; end commit: begin + devs_ctrl[j] <= 1'b1; if (cmdw_ready) begin - rmap_devs_ctrl[j-1] <= 1'b1; smt <= transfer; end end + arbitration: begin + if (arbitration_valid) begin + smt <= transfer; + // IBI requested during CMDW_BCAST_7E_W0. + // At the word module, was ACKed if IBI is enabled and DA is known, if not, NACKed. + if (ibi_requested) begin + // Receive MSB if IBI is enabled, DA is known and device . + if (ibi_enable & ibi_da_attached & ibi_bcr_2) begin + sm <= `CMDW_IBI_MDB; + // NACKed if BCR[2] is High or + // ACKed/NACKed if BCR[2] is Low. + end else begin + sm <= cmdp_valid_reg ? `CMDW_START : `CMDW_STOP_OD; + end + // No IBI requested during CMDW_BCAST_7E_W0. + end else if (cmdp_valid_reg) begin + sm <= cmdp_ccc_reg ? + (cmdp_ccc_id_reg == CCC_ENTDAA ? `CMDW_CCC_OD : `CMDW_CCC_PP) : `CMDW_MSG_SR; + end else begin + sm <= `CMDW_STOP_OD; + end + end + end default: begin smt <= setup; end @@ -362,6 +386,53 @@ module i3c_controller_framing #( end end + // 7-bit addr RAM for 1 cc data request. + + genvar i; + + // Obtain addr index in dev_ctrl, 0 means unknown device, + // since index 0 is reserved for this controller. + + wire [3:0] pos; + wire wen; + wire [6:0] rwaddr; + wire [6:0] raddr; + wire [3:0] rout; + assign ibi_da_attached = rmap_devs_ctrl[rout] & rout != 'd0; + assign pos = j; + assign wen = smt == commit; + assign rwaddr = cmdw_body[7:1]; + assign raddr = ibi_da; + + generate + for (i=0; i < 4; i=i+1) begin + // TODO Replace with inferred + RAM128X1D #( + .INIT(128'd0) + ) i_mem_pos ( + .A(rwaddr), // Read/write port 7-bit address input + .DPRA(raddr), // Read 7-bit address input + .SPO(), // Read/write port 1-bit output + .DPO(rout[i]), // Read port 1-bit output + .D(pos[i]), // Write data input + .WE(wen), // Write enable input + .WCLK(clk)); // Write clock input + end + endgenerate + + // Obtain BCR[2] from device, unknown devs return 0. + + RAM128X1D #( + .INIT(128'd0) + ) i_mem_bcr_2 ( + .A(rwaddr), + .DPRA(raddr), + .SPO(), + .DPO(ibi_bcr_2), + .D(pid_bcr_dcr[10]), + .WE(wen), + .WCLK(clk)); + reg [1:0] k; wire [1:0] l; always @(posedge clk) begin @@ -373,6 +444,7 @@ module i3c_controller_framing #( assign rmap_dev_char_wdata = pid_bcr_dcr; assign rmap_dev_char_we = pid_bcr_dcr_tick; assign rmap_dev_char_e = smt == seek | pid_bcr_dcr_tick; + assign rmap_devs_ctrl = devs_ctrl[15:1] & devs_ctrl_mask; assign cmdp_ready = smt == setup & cmdw_ready & !cmdw_nack & reset_n; assign sdo_ready = (smt == setup_sdo | smt == cleanup) & reset_n; diff --git a/library/i3c_controller/i3c_controller_core/i3c_controller_word.v b/library/i3c_controller/i3c_controller_core/i3c_controller_word.v index 4a7878c83b5..72a0fbbd8ec 100644 --- a/library/i3c_controller/i3c_controller_core/i3c_controller_word.v +++ b/library/i3c_controller/i3c_controller_core/i3c_controller_word.v @@ -71,10 +71,13 @@ module i3c_controller_word ( // IBI interface + output reg arbitration_valid, + input wire ibi_bcr_2, output reg ibi_requested, input wire ibi_requested_auto, output reg ibi_tick, output wire [6:0] ibi_da, + input wire ibi_da_attached, output wire [7:0] ibi_mdb, // DAA interface @@ -126,7 +129,8 @@ module i3c_controller_word ( `CMDW_MSG_SR : i_ = 0; `CMDW_MSG_RX : i_ = 8; // SDI+T `CMDW_MSG_TX : i_ = 8; // SDO+T - `CMDW_STOP : i_ = 0; + `CMDW_STOP_OD : i_ = 0; + `CMDW_STOP_PP : i_ = 0; `CMDW_BCAST_7E_W1 : i_ = 8; // 7'h7e+RnW=1+ACK `CMDW_DAA_DEV_CHAR_1 : i_ = 31; // 32-bitMSB_PID `CMDW_DAA_DEV_CHAR_2 : i_ = 31; // 16-bitLSB_PID+BCR+DCR @@ -147,7 +151,8 @@ module i3c_controller_word ( `CMDW_MSG_SR : sg = 1; `CMDW_MSG_RX : sg = 1; `CMDW_MSG_TX : sg = 1; - `CMDW_STOP : sg = 1; + `CMDW_STOP_OD : sg = 0; + `CMDW_STOP_PP : sg = 1; `CMDW_BCAST_7E_W1 : sg = 0; `CMDW_DAA_DEV_CHAR_1 : sg = 0; `CMDW_DAA_DEV_CHAR_2 : sg = 0; @@ -168,6 +173,7 @@ module i3c_controller_word ( always @(posedge clk) begin cmdw_nack <= 1'b0; cmdw_rx_valid <= 1'b0; + arbitration_valid <= 1'b0; ibi_tick <= 1'b0; pid_bcr_dcr_tick <= 1'b0; if (!reset_n) begin @@ -191,7 +197,6 @@ module i3c_controller_word ( end setup: begin smt <= transfer; - ibi_requested <= 1'b0; do_ack <= 1'b0; do_rx_t <= 1'b0; @@ -205,17 +210,20 @@ module i3c_controller_word ( `CMDW_BCAST_7E_W0: begin // During the header broadcast, the peripheral shall issue an IBI, due // to this the SDO is monitored and if the controller loses arbitration, - // shall ACK if IBI is enabled and receive the MDB+bytes (if the DCR says so), + // shall ACK if IBI is enabled and the DA is attached. + // If the peripheral's DCR[2] == 1'b1, also receive the MDB. // or NACK and Sr. // In both cases, the cmd's transfer will continue after the IBI is // resolved; - if (i[2:1] == 2'b11) begin + // TODO multiple ibi bytes. + if (i[2:1] == 2'b11 & ~ibi_requested) begin // 1'b0+RnW=0 cmd_r <= `MOD_BIT_CMD_WRITE_; cmd_wr <= 1'b0; end else if (i == 8) begin if (ibi_requested) begin // also ibi_len ... - cmd_r <= ibi_enable ? `MOD_BIT_CMD_ACK_IBI_ : `MOD_BIT_CMD_READ_; // & ibi_ack + // ACK if IBI is enabled and DA is known, if not, NACK. + cmd_r <= ibi_enable & ibi_da_attached ? `MOD_BIT_CMD_ACK_IBI_ : `MOD_BIT_CMD_READ_; end else begin // ACK cmd_r <= `MOD_BIT_CMD_ACK_SDR_; @@ -285,7 +293,8 @@ module i3c_controller_word ( cmd_wr <= cmdw_body[7 - i[2:0]]; end end - `CMDW_STOP: begin + `CMDW_STOP_OD, + `CMDW_STOP_PP: begin cmd_r <= `MOD_BIT_CMD_STOP_; end `CMDW_DAA_DEV_CHAR_1, @@ -323,7 +332,7 @@ module i3c_controller_word ( `CMDW_BCAST_7E_W1, `CMDW_BCAST_7E_W0: begin if (do_ack & rx !== 1'b0) begin - sm <= `CMDW_STOP; + sm <= `CMDW_STOP_OD; smt <= setup; cmdw_nack <= 1'b1; // Tick // Due to NACK'ED STOP inheriting NACK'ED word i value, @@ -333,7 +342,7 @@ module i3c_controller_word ( end `CMDW_MSG_RX: begin if (do_rx_t & rx === 1'b0) begin - sm <= `CMDW_STOP; + sm <= `CMDW_STOP_OD; smt <= setup; cmdw_nack <= 1'b1; cmdw_nacked <= 1'b1; @@ -345,12 +354,24 @@ module i3c_controller_word ( case (sm) `CMDW_NOP, - `CMDW_STOP: begin + `CMDW_STOP_OD, + `CMDW_STOP_PP: begin ibi_requested <= ibi_requested; end `CMDW_BCAST_7E_W0: begin ibi_da_reg[8-i] <= rx; + // Arbitration for IBI request. ibi_requested <= i < 6 & rx === 1'b0 ? 1'b1 : ibi_requested; + if (i == 7) begin + arbitration_valid <= 1'b1; + end + if (i == 8 & ibi_requested) begin + ibi_requested <= 1'b0; + // IBI from known peripheral without MDB (BCR[2] is Low). + if (ibi_da_attached & ~ibi_bcr_2) begin + ibi_tick <= 1'b1; + end + end end `CMDW_MSG_RX: begin if (i == 8) begin diff --git a/library/i3c_controller/i3c_controller_core/i3c_controller_word_cmd.v b/library/i3c_controller/i3c_controller_core/i3c_controller_word_cmd.v index 5e1684502fc..70eadfaa47d 100644 --- a/library/i3c_controller/i3c_controller_core/i3c_controller_word_cmd.v +++ b/library/i3c_controller/i3c_controller_core/i3c_controller_word_cmd.v @@ -48,11 +48,12 @@ `define CMDW_MSG_RX 5'd07 `define CMDW_CCC_OD 5'd08 `define CMDW_CCC_PP 5'd09 -`define CMDW_STOP 5'd10 -`define CMDW_BCAST_7E_W1 5'd11 -`define CMDW_DAA_DEV_CHAR_1 5'd12 -`define CMDW_DAA_DEV_CHAR_2 5'd13 -`define CMDW_DYN_ADDR 5'd14 -`define CMDW_IBI_MDB 5'd15 -`define CMDW_SR 5'd16 +`define CMDW_STOP_OD 5'd10 +`define CMDW_STOP_PP 5'd11 +`define CMDW_BCAST_7E_W1 5'd12 +`define CMDW_DAA_DEV_CHAR_1 5'd13 +`define CMDW_DAA_DEV_CHAR_2 5'd14 +`define CMDW_DYN_ADDR 5'd15 +`define CMDW_IBI_MDB 5'd16 +`define CMDW_SR 5'd17 `endif diff --git a/library/i3c_controller/i3c_controller_host_interface/i3c_controller_cmd_parser.v b/library/i3c_controller/i3c_controller_host_interface/i3c_controller_cmd_parser.v index 54ab3f6e75c..bb216aa0269 100644 --- a/library/i3c_controller/i3c_controller_host_interface/i3c_controller_cmd_parser.v +++ b/library/i3c_controller/i3c_controller_host_interface/i3c_controller_cmd_parser.v @@ -96,6 +96,9 @@ module i3c_controller_cmd_parser ( CE2_ERROR = 4'd3, NACK_RESP = 4'd9; + localparam [6:0] + CCC_ENTDAA = 'h07; + reg [2:0] sm; localparam [2:0] receive = 0, @@ -115,6 +118,7 @@ module i3c_controller_cmd_parser ( receive: begin cmdr_error <= NO_ERROR; cmdr1 <= cmd; + cmdr2 <= 8'd0; if (cmd_valid) begin sm <= buffer_setup; end else begin @@ -134,7 +138,7 @@ module i3c_controller_cmd_parser ( end xfer_await_ready: begin if (cmdp_ready) begin - sm <= receipt; + sm <= cmdp_ccc_id == CCC_ENTDAA ? receive : receipt; // DAA does not throw cmdr // TODO: implement NACK_RESP error, for that, need to differentiate bcast // address from da address ack (or drop it and handle any NACK as // CE2). diff --git a/library/i3c_controller/i3c_controller_host_interface/i3c_controller_regmap.v b/library/i3c_controller/i3c_controller_host_interface/i3c_controller_regmap.v index 25b1320ff58..ebc9f62142a 100644 --- a/library/i3c_controller/i3c_controller_host_interface/i3c_controller_regmap.v +++ b/library/i3c_controller/i3c_controller_host_interface/i3c_controller_regmap.v @@ -383,7 +383,7 @@ module i3c_controller_regmap #( ad_mem_dual #( .DATA_WIDTH(32), .ADDRESS_WIDTH(6) - ) i_dev_char_1_2 ( + ) i_mem_dev_char ( .clka(s_axi_aclk), .wea(dev_char_wea), .ea(dev_char_ea), @@ -427,7 +427,7 @@ module i3c_controller_regmap #( ad_mem_dual #( .DATA_WIDTH(32), .ADDRESS_WIDTH(5) - ) i_dev_char_1_2 ( + ) i_mem_offload ( .clka(s_axi_aclk), .wea(offload_wea), .ea(offload_ea), diff --git a/projects/ad405x_i3c_ardz/coraz7s/system_constr.xdc b/projects/ad405x_i3c_ardz/coraz7s/system_constr.xdc index 97700fe85c0..f52a708a4a7 100644 --- a/projects/ad405x_i3c_ardz/coraz7s/system_constr.xdc +++ b/projects/ad405x_i3c_ardz/coraz7s/system_constr.xdc @@ -23,10 +23,6 @@ set_multicycle_path -from [get_clocks clk_fpga_0] -to [get_ports i3c_controller_ set_multicycle_path -from [get_clocks clk_1] -to [get_clocks $i3c_clk] -setup 4 set_multicycle_path -from [get_clocks clk_1] -to [get_clocks $i3c_clk] -hold 3 -# The rx_raw_reg is used to observe the SDA lane for IBI requests during bus idle condition, -# and the delay does not matter. -set_false_path -from [get_ports i3c_controller_0_sda] -to [get_cells -hierarchical -filter {NAME =~ *i3c_controller_bit_mod/rx_raw_reg}] - # Notes # tcr/tcf rising/fall time for SCL is 150e06 * 1 / fSCL, at fSCL = 12.5 MHz => 12ns, at fSCL = 6.25 MHz, 24ns. # and t_SCO has a minimum/default value of 8ns and max of 12 ns