diff --git a/library/common/ad_dds.v b/library/common/ad_dds.v index f378b39ad5..ff8719f7d2 100644 --- a/library/common/ad_dds.v +++ b/library/common/ad_dds.v @@ -41,7 +41,7 @@ module ad_dds #( parameter DISABLE = 0, // range 8-24 parameter DDS_DW = 16, - // range 8-16 (FIX ME) + // range 8-32 parameter PHASE_DW = 16, // set 1 for CORDIC or 2 for Polynomial parameter DDS_TYPE = 1, diff --git a/library/common/up_dac_channel.v b/library/common/up_dac_channel.v index 89f41f9795..89c857eed6 100644 --- a/library/common/up_dac_channel.v +++ b/library/common/up_dac_channel.v @@ -43,6 +43,8 @@ module up_dac_channel #( parameter CHANNEL_ID = 4'h0, parameter CHANNEL_NUMBER = 8'b0, parameter DDS_DISABLE = 0, + parameter DDS_PHASE_DW = 16, + parameter DDS_EXT_DW = 0, parameter USERPORTS_DISABLE = 0, parameter IQCORRECTION_DISABLE = 0, parameter XBAR_ENABLE = 0 @@ -53,11 +55,11 @@ module up_dac_channel #( input dac_clk, input dac_rst, output [15:0] dac_dds_scale_1, - output [15:0] dac_dds_init_1, - output [15:0] dac_dds_incr_1, output [15:0] dac_dds_scale_2, - output [15:0] dac_dds_init_2, - output [15:0] dac_dds_incr_2, + output [DDS_EXT_DW+15:0] dac_dds_init_1, + output [DDS_EXT_DW+15:0] dac_dds_incr_1, + output [DDS_EXT_DW+15:0] dac_dds_init_2, + output [DDS_EXT_DW+15:0] dac_dds_incr_2, output [15:0] dac_pat_data_1, output [15:0] dac_pat_data_2, output [ 3:0] dac_data_sel, @@ -107,6 +109,10 @@ module up_dac_channel #( reg [15:0] up_dac_dds_scale_2 = 'd0; reg [15:0] up_dac_dds_init_2 = 'd0; reg [15:0] up_dac_dds_incr_2 = 'd0; + reg [15:0] up_dac_dds_init_1_extend = 'd0; + reg [15:0] up_dac_dds_incr_1_extend = 'd0; + reg [15:0] up_dac_dds_init_2_extend = 'd0; + reg [15:0] up_dac_dds_incr_2_extend = 'd0; reg [15:0] up_dac_pat_data_2 = 'd0; reg [15:0] up_dac_pat_data_1 = 'd0; reg up_dac_iqcor_enb = 'd0; @@ -135,8 +141,18 @@ module up_dac_channel #( // internal signals - wire up_wreq_s; - wire up_rreq_s; + wire up_wreq_s; + wire up_rreq_s; + wire [ 5:0] dds_phase_w = DDS_PHASE_DW[5:0]; + + wire [15:0] dac_dds_init_1_s; + wire [15:0] dac_dds_incr_1_s; + wire [15:0] dac_dds_init_2_s; + wire [15:0] dac_dds_incr_2_s; + wire [DDS_EXT_DW:0] dac_dds_init_1_extend; + wire [DDS_EXT_DW:0] dac_dds_incr_1_extend; + wire [DDS_EXT_DW:0] dac_dds_init_2_extend; + wire [DDS_EXT_DW:0] dac_dds_incr_2_extend; // 2's complement function @@ -179,6 +195,10 @@ module up_dac_channel #( up_dac_dds_scale_2 <= 'd0; up_dac_dds_init_2 <= 'd0; up_dac_dds_incr_2 <= 'd0; + up_dac_dds_init_1_extend <= 'd0; + up_dac_dds_incr_1_extend <= 'd0; + up_dac_dds_init_2_extend <= 'd0; + up_dac_dds_incr_2_extend <= 'd0; end end else begin always @(negedge up_rstn or posedge up_clk) begin @@ -189,6 +209,10 @@ module up_dac_channel #( up_dac_dds_scale_2 <= 'd0; up_dac_dds_init_2 <= 'd0; up_dac_dds_incr_2 <= 'd0; + up_dac_dds_init_1_extend <= 'd0; + up_dac_dds_incr_1_extend <= 'd0; + up_dac_dds_init_2_extend <= 'd0; + up_dac_dds_incr_2_extend <= 'd0; end else begin if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'h0)) begin up_dac_dds_scale_1 <= up_wdata[15:0]; @@ -204,6 +228,14 @@ module up_dac_channel #( up_dac_dds_init_2 <= up_wdata[31:16]; up_dac_dds_incr_2 <= up_wdata[15:0]; end + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'hb)) begin + up_dac_dds_init_1_extend <= up_wdata[31:16]; + up_dac_dds_incr_1_extend <= up_wdata[15:0]; + end + if ((up_wreq_s == 1'b1) && (up_waddr[3:0] == 4'hc)) begin + up_dac_dds_init_2_extend <= up_wdata[31:16]; + up_dac_dds_incr_2_extend <= up_wdata[15:0]; + end end end end @@ -351,7 +383,7 @@ module up_dac_channel #( case (up_raddr[3:0]) 4'h0: up_rdata_int <= { 16'd0, up_dac_dds_scale_1}; 4'h1: up_rdata_int <= { up_dac_dds_init_1, up_dac_dds_incr_1}; - 4'h2: up_rdata_int <= { 16'd0, up_dac_dds_scale_2}; + 4'h2: up_rdata_int <= { 10'd0, dds_phase_w, up_dac_dds_scale_2}; 4'h3: up_rdata_int <= { up_dac_dds_init_2, up_dac_dds_incr_2}; 4'h4: up_rdata_int <= { up_dac_pat_data_2, up_dac_pat_data_1}; 4'h5: up_rdata_int <= { 29'd0, up_dac_iqcor_enb, up_dac_lb_enb, up_dac_pn_enb}; @@ -362,6 +394,8 @@ module up_dac_channel #( dac_usr_datatype_bits}; 4'h9: up_rdata_int <= { dac_usr_interpolation_m, dac_usr_interpolation_n}; 4'ha: up_rdata_int <= { 30'd0, up_dac_iq_mode}; + 4'hb: up_rdata_int <= { up_dac_dds_init_1_extend, up_dac_dds_incr_1_extend}; + 4'hc: up_rdata_int <= { up_dac_dds_init_2_extend, up_dac_dds_incr_2_extend}; default: up_rdata_int <= 0; endcase end else begin @@ -402,7 +436,7 @@ module up_dac_channel #( // dac control & status - up_xfer_cntrl #(.DATA_WIDTH(177)) i_xfer_cntrl ( + up_xfer_cntrl #(.DATA_WIDTH(241)) i_xfer_cntrl ( .up_rstn (up_rstn), .up_clk (up_clk), .up_data_cntrl ({ up_dac_iq_mode, @@ -415,6 +449,10 @@ module up_dac_channel #( up_dac_dds_scale_tc_2, up_dac_dds_init_2, up_dac_dds_incr_2, + up_dac_dds_init_1_extend, + up_dac_dds_incr_1_extend, + up_dac_dds_init_2_extend, + up_dac_dds_incr_2_extend, up_dac_pat_data_1, up_dac_pat_data_2, up_dac_data_sel_m, @@ -428,17 +466,26 @@ module up_dac_channel #( dac_iqcor_coeff_1, dac_iqcor_coeff_2, dac_dds_scale_1, - dac_dds_init_1, - dac_dds_incr_1, + dac_dds_init_1_s, + dac_dds_incr_1_s, dac_dds_scale_2, - dac_dds_init_2, - dac_dds_incr_2, + dac_dds_init_2_s, + dac_dds_incr_2_s, + dac_dds_init_1_extend, + dac_dds_incr_1_extend, + dac_dds_init_2_extend, + dac_dds_incr_2_extend, dac_pat_data_1, dac_pat_data_2, dac_data_sel, dac_mask_enable, dac_src_chan_sel})); + assign dac_dds_init_1 = {dac_dds_init_1_extend[DDS_EXT_DW:0], dac_dds_init_1_s}; + assign dac_dds_incr_1 = {dac_dds_incr_1_extend[DDS_EXT_DW:0], dac_dds_incr_1_s}; + assign dac_dds_init_2 = {dac_dds_init_2_extend[DDS_EXT_DW:0], dac_dds_init_2_s}; + assign dac_dds_incr_2 = {dac_dds_incr_2_extend[DDS_EXT_DW:0], dac_dds_incr_2_s}; + endmodule // ***************************************************************************