From cde99569484925abae5e4304b8c830fbb5cef187 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Mon, 13 Feb 2023 19:52:29 +0200 Subject: [PATCH] ad4858_fmcz: Initial design Reference design for AD4858 20-bit, low noise 8-channel, SAR ADC with buffered differential, wide common range picoamp inputs. The design supports: - CMOS and LVDS interfaces(at build time) - Runtime sampling changes - Store captured samples in RAM, through DMA (available via software support) Documentation at: https://wiki.analog.com/resources/eval/user-guides/ad4858_fmcz/ad4858_fmcz_hdl --- projects/ad4858_fmcz/Makefile | 7 + projects/ad4858_fmcz/Readme.md | 7 + .../ad4858_fmcz/common/ad4858_fmcz_bd.tcl | 163 ++++++++++++ projects/ad4858_fmcz/zed/Makefile | 27 ++ projects/ad4858_fmcz/zed/README.rst | 9 + projects/ad4858_fmcz/zed/system_bd.tcl | 16 ++ projects/ad4858_fmcz/zed/system_constr.tcl | 53 ++++ projects/ad4858_fmcz/zed/system_project.tcl | 38 +++ projects/ad4858_fmcz/zed/system_top_cmos.v | 238 ++++++++++++++++++ projects/ad4858_fmcz/zed/system_top_lvds.v | 237 +++++++++++++++++ 10 files changed, 795 insertions(+) create mode 100644 projects/ad4858_fmcz/Makefile create mode 100755 projects/ad4858_fmcz/Readme.md create mode 100644 projects/ad4858_fmcz/common/ad4858_fmcz_bd.tcl create mode 100644 projects/ad4858_fmcz/zed/Makefile create mode 100644 projects/ad4858_fmcz/zed/README.rst create mode 100644 projects/ad4858_fmcz/zed/system_bd.tcl create mode 100644 projects/ad4858_fmcz/zed/system_constr.tcl create mode 100644 projects/ad4858_fmcz/zed/system_project.tcl create mode 100644 projects/ad4858_fmcz/zed/system_top_cmos.v create mode 100644 projects/ad4858_fmcz/zed/system_top_lvds.v diff --git a/projects/ad4858_fmcz/Makefile b/projects/ad4858_fmcz/Makefile new file mode 100644 index 0000000000..1402069e10 --- /dev/null +++ b/projects/ad4858_fmcz/Makefile @@ -0,0 +1,7 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +include ../scripts/project-toplevel.mk diff --git a/projects/ad4858_fmcz/Readme.md b/projects/ad4858_fmcz/Readme.md new file mode 100755 index 0000000000..97f4dc1c38 --- /dev/null +++ b/projects/ad4858_fmcz/Readme.md @@ -0,0 +1,7 @@ +# AD4858 HDL Project + +Here are some pointers to help you: + * Parts : [AD4858](https://www.analog.com/ad4858) + * Project Doc: https://wiki.analog.com/resources/eval/user-guides/ad4858_fmcz + * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/ad4858_fmcz/ad4858_fmcz_hdl + * Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers/iio-adc/axi-adc-hdl diff --git a/projects/ad4858_fmcz/common/ad4858_fmcz_bd.tcl b/projects/ad4858_fmcz/common/ad4858_fmcz_bd.tcl new file mode 100644 index 0000000000..a1c8293bc8 --- /dev/null +++ b/projects/ad4858_fmcz/common/ad4858_fmcz_bd.tcl @@ -0,0 +1,163 @@ +############################################################################### +## Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set LVDS_CMOS_N $ad_project_params(LVDS_CMOS_N) + +# ad4858 interface + +if {$LVDS_CMOS_N == "0"} { + create_bd_port -dir O scki + create_bd_port -dir I scko + create_bd_port -dir I adc_lane_0 + create_bd_port -dir I adc_lane_1 + create_bd_port -dir I adc_lane_2 + create_bd_port -dir I adc_lane_3 + create_bd_port -dir I adc_lane_4 + create_bd_port -dir I adc_lane_5 + create_bd_port -dir I adc_lane_6 + create_bd_port -dir I adc_lane_7 +} else { + create_bd_port -dir O scki_p + create_bd_port -dir O scki_n + create_bd_port -dir I scko_p + create_bd_port -dir I scko_n + create_bd_port -dir I sdo_p + create_bd_port -dir I sdo_n +} + +create_bd_port -dir I busy +create_bd_port -dir O cnv +create_bd_port -dir O lvds_cmos_n + +create_bd_port -dir O system_cpu_clk + +# adc clock generator + +ad_ip_instance axi_clkgen adc_clkgen +ad_ip_parameter adc_clkgen CONFIG.CLKIN_PERIOD 5 +ad_ip_parameter adc_clkgen CONFIG.VCO_DIV 1 +ad_connect sys_200m_clk adc_clkgen/clk +if {$LVDS_CMOS_N == "0"} { + # CMOS setup + # clk0 = 100M + ad_ip_parameter adc_clkgen CONFIG.VCO_MUL 5 + ad_ip_parameter adc_clkgen CONFIG.CLK0_DIV 10 + ad_connect adc_clk adc_clkgen/clk_0 +} else { + # LVDS setup + # clk0 = 200M + # clk1 = 400M + ad_ip_parameter adc_clkgen CONFIG.VCO_MUL 6 + ad_ip_parameter adc_clkgen CONFIG.CLK0_DIV 6 + ad_ip_parameter adc_clkgen CONFIG.ENABLE_CLKOUT1 "true" + ad_ip_parameter adc_clkgen CONFIG.CLK1_DIV 3 + ad_connect adc_clk adc_clkgen/clk_0 + ad_connect adc_fast_clk adc_clkgen/clk_1 +} + +# adc clock domain reset + +ad_ip_instance proc_sys_reset adc_rstgen +ad_ip_parameter adc_rstgen CONFIG.C_EXT_RST_WIDTH 1 +ad_connect adc_rstgen/ext_reset_in sys_cpu_resetn +ad_connect adc_rstgen/slowest_sync_clk adc_clk +ad_connect adc_resetn adc_rstgen/peripheral_aresetn +ad_connect adc_reset adc_rstgen/peripheral_reset + +# adc(ad4858-dma) + +ad_ip_instance axi_dmac ad4858_dma +ad_ip_parameter ad4858_dma CONFIG.DMA_TYPE_SRC 2 +ad_ip_parameter ad4858_dma CONFIG.DMA_TYPE_DEST 0 +ad_ip_parameter ad4858_dma CONFIG.CYCLIC 0 +ad_ip_parameter ad4858_dma CONFIG.SYNC_TRANSFER_START 1 +ad_ip_parameter ad4858_dma CONFIG.AXI_SLICE_SRC 0 +ad_ip_parameter ad4858_dma CONFIG.AXI_SLICE_DEST 0 +ad_ip_parameter ad4858_dma CONFIG.DMA_2D_TRANSFER 0 +ad_ip_parameter ad4858_dma CONFIG.DMA_DATA_WIDTH_SRC 256 +ad_ip_parameter ad4858_dma CONFIG.DMA_DATA_WIDTH_DEST 64 + +ad_connect adc_clk ad4858_dma/fifo_wr_clk + +# axi pwm gen + +ad_ip_instance axi_pwm_gen axi_pwm_gen +ad_ip_parameter axi_pwm_gen CONFIG.N_PWMS 1 +ad_ip_parameter axi_pwm_gen CONFIG.PULSE_0_WIDTH 1 +ad_ip_parameter axi_pwm_gen CONFIG.PULSE_0_PERIOD 8 + +ad_connect cnv axi_pwm_gen/pwm_0 +ad_connect adc_clk axi_pwm_gen/ext_clk +ad_connect sys_cpu_resetn axi_pwm_gen/s_axi_aresetn +ad_connect sys_cpu_clk axi_pwm_gen/s_axi_aclk + +# axi_ad4858 + +ad_ip_instance axi_ad4858 axi_ad4858 +ad_ip_parameter axi_ad4858 CONFIG.LVDS_CMOS_N $LVDS_CMOS_N +ad_ip_parameter axi_ad4858 CONFIG.EXTERNAL_CLK 1 +ad_connect axi_ad4858/external_clk adc_clk +if {$LVDS_CMOS_N == "0"} { + ad_connect adc_lane_0 axi_ad4858/lane_0 + ad_connect adc_lane_1 axi_ad4858/lane_1 + ad_connect adc_lane_2 axi_ad4858/lane_2 + ad_connect adc_lane_3 axi_ad4858/lane_3 + ad_connect adc_lane_4 axi_ad4858/lane_4 + ad_connect adc_lane_5 axi_ad4858/lane_5 + ad_connect adc_lane_6 axi_ad4858/lane_6 + ad_connect adc_lane_7 axi_ad4858/lane_7 + ad_connect scko axi_ad4858/scko + ad_connect scki axi_ad4858/scki + +} else { + ad_connect axi_ad4858/external_fast_clk adc_fast_clk + + ad_connect sdo_p axi_ad4858/sdo_p + ad_connect sdo_n axi_ad4858/sdo_n + ad_connect scko_p axi_ad4858/scko_p + ad_connect scko_n axi_ad4858/scko_n + ad_connect scki_p axi_ad4858/scki_p + ad_connect scki_n axi_ad4858/scki_n +} + +ad_connect busy axi_ad4858/busy +ad_connect lvds_cmos_n axi_ad4858/lvds_cmos_n + +# adc-path channel pack + +ad_ip_instance util_cpack2 ad4858_adc_pack +ad_ip_parameter ad4858_adc_pack CONFIG.NUM_OF_CHANNELS 8 +ad_ip_parameter ad4858_adc_pack CONFIG.SAMPLE_DATA_WIDTH 32 + +ad_connect adc_clk ad4858_adc_pack/clk +ad_connect adc_reset ad4858_adc_pack/reset +ad_connect axi_ad4858/adc_valid ad4858_adc_pack/fifo_wr_en +ad_connect ad4858_adc_pack/packed_fifo_wr ad4858_dma/fifo_wr +ad_connect ad4858_adc_pack/fifo_wr_overflow axi_ad4858/adc_dovf + +for {set i 0} {$i < 8} {incr i} { + ad_connect axi_ad4858/adc_data_$i ad4858_adc_pack/fifo_wr_data_$i + ad_connect axi_ad4858/adc_enable_$i ad4858_adc_pack/enable_$i +} + +ad_connect sys_cpu_clk system_cpu_clk + +ad_connect sys_200m_clk axi_ad4858/delay_clk +ad_connect axi_pwm_gen/pwm_0 axi_ad4858/cnvs + +# interrupts + +ad_cpu_interrupt ps-10 mb-10 ad4858_dma/irq + +# cpu / memory interconnects + +ad_cpu_interconnect 0x43c00000 axi_ad4858 +ad_cpu_interconnect 0x43d00000 axi_pwm_gen +ad_cpu_interconnect 0x43e00000 ad4858_dma +ad_cpu_interconnect 0x44000000 adc_clkgen + +ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1 +ad_mem_hp1_interconnect $sys_dma_clk ad4858_dma/m_dest_axi +ad_connect $sys_dma_resetn ad4858_dma/m_dest_axi_aresetn diff --git a/projects/ad4858_fmcz/zed/Makefile b/projects/ad4858_fmcz/zed/Makefile new file mode 100644 index 0000000000..9693e3d5ad --- /dev/null +++ b/projects/ad4858_fmcz/zed/Makefile @@ -0,0 +1,27 @@ +#################################################################################### +## Copyright (c) 2018 - 2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := ad4858_fmcz_zed + +M_DEPS += ../common/ad4858_fmcz_bd.tcl +M_DEPS += ../../scripts/adi_pd.tcl +M_DEPS += ../../common/zed/zed_system_constr.xdc +M_DEPS += ../../common/zed/zed_system_bd.tcl +M_DEPS += ../../../library/common/ad_iobuf.v + +LIB_DEPS += axi_ad4858 +LIB_DEPS += axi_clkgen +LIB_DEPS += axi_dmac +LIB_DEPS += axi_hdmi_tx +LIB_DEPS += axi_i2s_adi +LIB_DEPS += axi_pwm_gen +LIB_DEPS += axi_spdif_tx +LIB_DEPS += axi_sysid +LIB_DEPS += sysid_rom +LIB_DEPS += util_i2c_mixer +LIB_DEPS += util_pack/util_cpack2 + +include ../../scripts/project-xilinx.mk diff --git a/projects/ad4858_fmcz/zed/README.rst b/projects/ad4858_fmcz/zed/README.rst new file mode 100644 index 0000000000..810ca97daa --- /dev/null +++ b/projects/ad4858_fmcz/zed/README.rst @@ -0,0 +1,9 @@ +- Connect on FMC LPC +- VADJ = 1.8V to 3.3V +Make sure that all power supply source/voltage selection jumpers are +properly placed according to your use case on both the eval board and zed. + +The default interface at build is CMOS. To explicitly select an interface: + +- make LVDS_CMOS_N=0 for CMOS interface +- make LVDS_CMOS_N=1 for LVDS interface diff --git a/projects/ad4858_fmcz/zed/system_bd.tcl b/projects/ad4858_fmcz/zed/system_bd.tcl new file mode 100644 index 0000000000..0d9b0ac4cf --- /dev/null +++ b/projects/ad4858_fmcz/zed/system_bd.tcl @@ -0,0 +1,16 @@ +############################################################################### +## Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source $ad_hdl_dir/projects/common/zed/zed_system_bd.tcl +source ../common/ad4858_fmcz_bd.tcl +source $ad_hdl_dir/projects/scripts/adi_pd.tcl + +#system ID +set mem_init_sys_path [get_env_param ADI_PROJECT_DIR ""]mem_init_sys.txt; +ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 +ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/$mem_init_sys_path" +ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 +set sys_cstring "LVDS_CMOS_N=$LVDS_CMOS_N" +sysid_gen_sys_init_file $sys_cstring diff --git a/projects/ad4858_fmcz/zed/system_constr.tcl b/projects/ad4858_fmcz/zed/system_constr.tcl new file mode 100644 index 0000000000..74167d40bd --- /dev/null +++ b/projects/ad4858_fmcz/zed/system_constr.tcl @@ -0,0 +1,53 @@ +############################################################################### +## Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +if {![info exists LVDS_CMOS_N]} { + set LVDS_CMOS_N $::env(LVDS_CMOS_N) +} + +# AD4858 +set_property -dict {PACKAGE_PIN L21 IOSTANDARD LVCMOS25} [get_ports lvds_cmos_n] ; ## C10 FMC_LPC_LA06_P +set_property -dict {PACKAGE_PIN P18 IOSTANDARD LVCMOS25} [get_ports pd] ; ## H08 FMC_LPC_LA02_N +set_property -dict {PACKAGE_PIN P17 IOSTANDARD LVCMOS25} [get_ports cnv] ; ## H07 FMC_LPC_LA02_P +set_property -dict {PACKAGE_PIN L22 IOSTANDARD LVCMOS25} [get_ports busy] ; ## C11 FMC_LPC_LA06_N + +# SPI +set_property -dict {PACKAGE_PIN R20 IOSTANDARD LVCMOS25} [get_ports csck] ; ## D14 FMC_LPC_LA09_P +set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS25} [get_ports csdio] ; ## D17 FMC_LPC_LA13_P +set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS25} [get_ports cs_n] ; ## D18 FMC_LPC_LA13_N +set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVCMOS25} [get_ports csd0] ; ## D27 FMC_LPC_LA26_N + +# LVDS +if {$LVDS_CMOS_N == 1} { + set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVDS_25} [get_ports scki_p] ; ## D08 FMC_LPC_LA01_CC_P # SCKI+ + set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVDS_25} [get_ports scki_n] ; ## D09 FMC_LPC_LA01_CC_N # SCKI- + set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sdo_p] ; ## C26 FMC_LPC_LA27_P # SD0+ + set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports sdo_n] ; ## C27 FMC_LPC_LA27_N # SD0- + set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports scko_p] ; ## D20 FMC_LPC_LA17_CC_P # scko+ + set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports scko_n] ; ## D21 FMC_LPC_LA17_CC_N # scko- + + create_clock -period 2.5 -name scko [get_ports scko_p] + set_false_path -from [get_clocks scko] -to [get_clocks -of_objects [get_pins i_system_wrapper/system_i/adc_clkgen/inst/i_mmcm_drp/i_mmcm/CLKOUT0]] + +# CMOS +} else { + + set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVCMOS25} [get_ports scki] ; ## D20 FMC_LPC_LA17_CC_P # scko+ + set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVCMOS25} [get_ports scko] ; ## D21 FMC_LPC_LA17_CC_N # scko- + set_property -dict {PACKAGE_PIN N19 IOSTANDARD LVCMOS25} [get_ports sdo[0]] ; ## D08 FMC_LPC_LA01_CC_P # SCKI+ + set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS25} [get_ports sdo[1]] ; ## C15 FMC_LPC_LA10_N + set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports sdo[2]] ; ## D09 FMC_LPC_LA01_CC_N # SCKI- + set_property -dict {PACKAGE_PIN K19 IOSTANDARD LVCMOS25} [get_ports sdo[3]] ; ## C18 FMC_LPC_LA14_P + set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports sdo[4]] ; ## D11 FMC_LPC_LA05_P + set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS25} [get_ports sdo[5]] ; ## C26 FMC_LPC_LA27_P # SD0+ + set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS25} [get_ports sdo[6]] ; ## D12 FMC_LPC_LA05_N # SD0- + set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS25} [get_ports sdo[7]] ; ## C27 FMC_LPC_LA27_N + + set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {scko_IBUF}] + + create_clock -name scko_cmos -period 10 [get_ports scko] + set_max_delay -from [get_clocks scko_cmos] -to [get_clocks -of_objects [get_pins i_system_wrapper/system_i/adc_clkgen/inst/i_mmcm_drp/i_mmcm/CLKOUT0]] 10.0 + set_min_delay -from [get_clocks scko_cmos] -to [get_clocks -of_objects [get_pins i_system_wrapper/system_i/adc_clkgen/inst/i_mmcm_drp/i_mmcm/CLKOUT0]] 1.0 +} diff --git a/projects/ad4858_fmcz/zed/system_project.tcl b/projects/ad4858_fmcz/zed/system_project.tcl new file mode 100644 index 0000000000..4d918c3347 --- /dev/null +++ b/projects/ad4858_fmcz/zed/system_project.tcl @@ -0,0 +1,38 @@ +############################################################################### +## Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +# if the interface is not build defined, set CMOS as default inferface +# make LVDS_CMOS_N=1 for LVDS interface +set LVDS_CMOS_N 0 +if [info exists ::env(LVDS_CMOS_N)] { + set LVDS_CMOS_N $::env(LVDS_CMOS_N) +} else { + set env(LVDS_CMOS_N) $LVDS_CMOS_N +} + +adi_project ad4858_fmcz_zed 0 [list \ + LVDS_CMOS_N $LVDS_CMOS_N \ +] + +if {$LVDS_CMOS_N == "0"} { + adi_project_files {} [list \ + "system_top_cmos.v" \ + ] +} else { + adi_project_files {} [list \ + "system_top_lvds.v" \ + ] +} + +adi_project_files {} [list \ + "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" \ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "system_constr.tcl"] + +adi_project_run ad4858_fmcz_zed diff --git a/projects/ad4858_fmcz/zed/system_top_cmos.v b/projects/ad4858_fmcz/zed/system_top_cmos.v new file mode 100644 index 0000000000..d6e6dc529e --- /dev/null +++ b/projects/ad4858_fmcz/zed/system_top_cmos.v @@ -0,0 +1,238 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout [31:0] gpio_bd, + + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [15:0] hdmi_data, + + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + output i2s_sdata_out, + input i2s_sdata_in, + + output spdif, + + inout iic_scl, + inout iic_sda, + inout [ 1:0] iic_mux_scl, + inout [ 1:0] iic_mux_sda, + + input otg_vbusoc, + + output scki, + input scko, + input [ 7:0] sdo, + + input busy, + output cnv, + output pd, + output lvds_cmos_n, + + input csd0, //spiad_sdo + output reg csck, //spiad_sck + output reg csdio,//spiad_sdi + output reg cs_n //spiad_csn +); + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + wire [ 1:0] iic_mux_scl_i_s; + wire [ 1:0] iic_mux_scl_o_s; + wire iic_mux_scl_t_s; + wire [ 1:0] iic_mux_sda_i_s; + wire [ 1:0] iic_mux_sda_o_s; + wire iic_mux_sda_t_s; + + assign gpio_i[63:32] = gpio_o[63:32]; + assign pd = gpio_o[32]; + + wire spiad_sck_s; + wire spiad_csn_s; + reg [ 4:0] cnt_cs_up = 3'd0; + + always @(posedge cpu_clk) begin + csck <= spiad_sck_s; + csdio <= spiad_sdi_s; + if (spiad_csn_s == 1'b0) begin + cs_n <= 1'b0; + cnt_cs_up <= 3'd0; + end else if (cnt_cs_up == 5'h1f) begin + cs_n <= 1'b0; + cnt_cs_up <= cnt_cs_up; + end else begin + cs_n <= 1'b1; + cnt_cs_up <= cnt_cs_up + 3'd1; + end + end + + // instantiations + + ad_iobuf #( + .DATA_WIDTH(32) + ) i_iobuf ( + .dio_t(gpio_t[31:0]), + .dio_i(gpio_o[31:0]), + .dio_o(gpio_i[31:0]), + .dio_p(gpio_bd)); + + ad_iobuf #( + .DATA_WIDTH(2) + ) i_iic_mux_scl ( + .dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}), + .dio_i(iic_mux_scl_o_s), + .dio_o(iic_mux_scl_i_s), + .dio_p(iic_mux_scl)); + + ad_iobuf #( + .DATA_WIDTH(2) + ) i_iic_mux_sda ( + .dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}), + .dio_i(iic_mux_sda_o_s), + .dio_o(iic_mux_sda_i_s), + .dio_p(iic_mux_sda)); + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .i2s_bclk (i2s_bclk), + .i2s_lrclk (i2s_lrclk), + .i2s_mclk (i2s_mclk), + .i2s_sdata_in (i2s_sdata_in), + .i2s_sdata_out (i2s_sdata_out), + .iic_fmc_scl_io (iic_scl), + .iic_fmc_sda_io (iic_sda), + .iic_mux_scl_i (iic_mux_scl_i_s), + .iic_mux_scl_o (iic_mux_scl_o_s), + .iic_mux_scl_t (iic_mux_scl_t_s), + .iic_mux_sda_i (iic_mux_sda_i_s), + .iic_mux_sda_o (iic_mux_sda_o_s), + .iic_mux_sda_t (iic_mux_sda_t_s), + .otg_vbusoc (otg_vbusoc), + .spdif (spdif), + .system_cpu_clk (cpu_clk), + .spi0_clk_i (spiad_sck_s), + .spi0_clk_o (spiad_sck_s), + .spi0_csn_0_o (spiad_csn_s), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (csd0), + .spi0_sdo_i (csd0), + .spi0_sdo_o (spiad_sdi_s), + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .spi1_sdo_o (), + .scki (scki), + .scko (scko), + .adc_lane_0 (sdo[0]), + .adc_lane_1 (sdo[1]), + .adc_lane_2 (sdo[2]), + .adc_lane_3 (sdo[3]), + .adc_lane_4 (sdo[4]), + .adc_lane_5 (sdo[5]), + .adc_lane_6 (sdo[6]), + .adc_lane_7 (sdo[7]), + .busy (busy), + .cnv (cnv), + .lvds_cmos_n (lvds_cmos_n)); + +endmodule diff --git a/projects/ad4858_fmcz/zed/system_top_lvds.v b/projects/ad4858_fmcz/zed/system_top_lvds.v new file mode 100644 index 0000000000..355b5c06f0 --- /dev/null +++ b/projects/ad4858_fmcz/zed/system_top_lvds.v @@ -0,0 +1,237 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout [31:0] gpio_bd, + + output hdmi_out_clk, + output hdmi_vsync, + output hdmi_hsync, + output hdmi_data_e, + output [15:0] hdmi_data, + + output i2s_mclk, + output i2s_bclk, + output i2s_lrclk, + output i2s_sdata_out, + input i2s_sdata_in, + + output spdif, + + inout iic_scl, + inout iic_sda, + inout [ 1:0] iic_mux_scl, + inout [ 1:0] iic_mux_sda, + + input otg_vbusoc, + + output scki_p, + output scki_n, + input scko_p, + input scko_n, + input sdo_p, + input sdo_n, + + input busy, + output cnv, + output pd, + output lvds_cmos_n, + + input csd0, //spiad_sdo + output reg csck, //spiad_sck + output reg csdio,//spiad_sdi + output reg cs_n //spiad_csn +); + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + wire [ 1:0] iic_mux_scl_i_s; + wire [ 1:0] iic_mux_scl_o_s; + wire iic_mux_scl_t_s; + wire [ 1:0] iic_mux_sda_i_s; + wire [ 1:0] iic_mux_sda_o_s; + wire iic_mux_sda_t_s; + + assign gpio_i[63:32] = gpio_o[63:32]; + assign pd = gpio_o[32]; + + wire spiad_sck_s; + wire spiad_csn_s; + reg [ 4:0] cnt_cs_up = 3'd0; + + always @(posedge cpu_clk) begin + csck <= spiad_sck_s; + csdio <= spiad_sdi_s; + if (spiad_csn_s == 1'b0) begin + cs_n <= 1'b0; + cnt_cs_up <= 3'd0; + end else if (cnt_cs_up == 5'h1f) begin + cs_n <= 1'b0; + cnt_cs_up <= cnt_cs_up; + end else begin + cs_n <= 1'b1; + cnt_cs_up <= cnt_cs_up + 3'd1; + end + end + + // instantiations + + ad_iobuf #( + .DATA_WIDTH(32) + ) i_iobuf ( + .dio_t(gpio_t[31:0]), + .dio_i(gpio_o[31:0]), + .dio_o(gpio_i[31:0]), + .dio_p(gpio_bd)); + + ad_iobuf #( + .DATA_WIDTH(2) + ) i_iic_mux_scl ( + .dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}), + .dio_i(iic_mux_scl_o_s), + .dio_o(iic_mux_scl_i_s), + .dio_p(iic_mux_scl)); + + ad_iobuf #( + .DATA_WIDTH(2) + ) i_iic_mux_sda ( + .dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}), + .dio_i(iic_mux_sda_o_s), + .dio_o(iic_mux_sda_i_s), + .dio_p(iic_mux_sda)); + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .i2s_bclk (i2s_bclk), + .i2s_lrclk (i2s_lrclk), + .i2s_mclk (i2s_mclk), + .i2s_sdata_in (i2s_sdata_in), + .i2s_sdata_out (i2s_sdata_out), + .iic_fmc_scl_io (iic_scl), + .iic_fmc_sda_io (iic_sda), + .iic_mux_scl_i (iic_mux_scl_i_s), + .iic_mux_scl_o (iic_mux_scl_o_s), + .iic_mux_scl_t (iic_mux_scl_t_s), + .iic_mux_sda_i (iic_mux_sda_i_s), + .iic_mux_sda_o (iic_mux_sda_o_s), + .iic_mux_sda_t (iic_mux_sda_t_s), + .otg_vbusoc (otg_vbusoc), + .spdif (spdif), + .system_cpu_clk (cpu_clk), + .spi0_clk_i (spiad_sck_s), + .spi0_clk_o (spiad_sck_s), + .spi0_csn_0_o (spiad_csn_s), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (csd0), + .spi0_sdo_i (csd0), + .spi0_sdo_o (spiad_sdi_s), + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .spi1_sdo_o (), + .scki_p (scki_p), + .scki_n (scki_n), + .scko_p (scko_p), + .scko_n (scko_n), + .sdo_p (sdo_p), + .sdo_n (sdo_n), + .busy (busy), + .cnv (cnv), + .lvds_cmos_n (lvds_cmos_n)); + +endmodule