From c9e90be8b9fe875848bb3d7b550e1f23776e8e92 Mon Sep 17 00:00:00 2001 From: Jorge Marques Date: Tue, 19 Nov 2024 15:11:25 -0300 Subject: [PATCH] docs: Add AD4052-ARDZ project Describe EVAL-AD4052-ARDZ support with coraz7s. Signed-off-by: Jorge Marques --- docs/projects/ad4052_ardz/ad4052_hdl.svg | 2618 ++++++++++++++++++++++ docs/projects/ad4052_ardz/index.rst | 320 +++ docs/projects/index.rst | 1 + 3 files changed, 2939 insertions(+) create mode 100644 docs/projects/ad4052_ardz/ad4052_hdl.svg create mode 100644 docs/projects/ad4052_ardz/index.rst diff --git a/docs/projects/ad4052_ardz/ad4052_hdl.svg b/docs/projects/ad4052_ardz/ad4052_hdl.svg new file mode 100644 index 0000000000..c635b198c3 --- /dev/null +++ b/docs/projects/ad4052_ardz/ad4052_hdl.svg @@ -0,0 +1,2618 @@ + + + +image/svg+xmlEthernetUARTDDRxSPII2CInterruptsTimerReceive pathMEMORY INTERCONNECTCora Z7sDE10-NanoARDUINO SHIELD CONNECTORAD4052_DMA SYS_CLK =100MHzSPI_CLK = 150 MHzDAC core frameARM (Zynq)Zynq SoC SPI ENGINE FRAMEWORKCSSDISCLK 25MHzAXIREGMAPINTER-CONNECTEXECUTIONOFFLOADSDIAXI CLKGENAXI PWMGENGP1CNV64b32btriggers0_ctrls1_ctrloffload_ctrlm_ctrlSDOGP0 diff --git a/docs/projects/ad4052_ardz/index.rst b/docs/projects/ad4052_ardz/index.rst new file mode 100644 index 0000000000..efc93881b1 --- /dev/null +++ b/docs/projects/ad4052_ardz/index.rst @@ -0,0 +1,320 @@ +.. _ad4052-ardz: + +AD4052-ARDZ HDL project +================================================================================ + +Overview +-------------------------------------------------------------------------------- + +The HDL reference design for the :adi:`AD4050`, :adi:`AD4052`, :adi:`AD4056`, and +:adi:`AD4058` . +They are versatile, 16-bit/12-bit, successive approximation register (SAR) +analog-to-digital converters (ADCs) that enable low-power, high-density data +acquisition solutions without sacrificing precision. These ADCs offer a unique +balance of performance and power efficiency, plus innovative features for +seamlessly switching between high-resolution and low-power modes tailored to the +immediate needs of the system. + +The :adi:`AD4050`/:adi:`AD4052`/:adi:`AD4056`/:adi:`AD4058` are ideal for +battery-powered, compact data acquisition and edge sensing applications. + +The :adi:`EVAL-AD4050-ARDZ`/:adi:`EVAL-AD4052-ARDZ` evaluation boards enable +quick and easy evaluation of the performance and features of the :adi:`AD4050` +or the :adi:`AD4052`, respectively. +The AD4050 and AD4052 are compact, low power, 12-bit or 16-bit (respectively) +Easy Drive successive approximation register (SAR) analog-to-digital converters +(ADCs). + +This project has a :ref:`spi_engine` instance to control and acquire data from +the precision ADC. +This instance provides support for capturing continuous samples at the maximum +sample rate. + +Supported boards +------------------------------------------------------------------------------- + +- :adi:`EVAL-AD4050-ARDZ` +- :adi:`EVAL-AD4052-ARDZ` + +Supported devices +------------------------------------------------------------------------------- + +- :adi:`AD4050` +- :adi:`AD4052` +- :adi:`AD4056` +- :adi:`AD4058` + +Supported carriers +------------------------------------------------------------------------------- + +- :xilinx:`Cora Z7-07S ` + Arduino shield connector +- :intel:`DE10-Nano ` + Arduino shield connector + +Block design +------------------------------------------------------------------------------- + +The data path and clock domains are depicted in the below diagram: + +.. image:: ad4052_hdl.svg + :width: 800 + :align: center + :alt: AD4052-ARDZ block diagram + +CPU/Memory interconnects addresses +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The addresses are dependent on the architecture of the FPGA, having an offset +added to the base address from HDL (see more at :ref:`architecture`). + +.. table:: Cora Z7S + + ======================== =========== + Instance Address + ======================== =========== + spi_adc_axi_regmap 0x44A0_0000 + spi_adc_dmac 0x44A3_0000 + axi_iic_eeprom 0x44A4_0000 + spi_clkgen 0x44A7_0000 + adc_trigger_gen 0x44B0_0000 + ======================== =========== + +.. table:: DE10-Nano + + ======================== =========== + Instance Address + ======================== =========== + axi_dmac_0 0x0002_0000 + axi_spi_engine_0 0x0003_0000 + pwm_trigger 0x0004_0000 + spi_clk_pll_reconfig 0x0005_0000 + ======================== =========== + +I2C connections +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. list-table:: Cora Z7s + :header-rows: 1 + + * - I2C type + - I2C manager instance + - Alias + - Address + - Device Address + - I2C subordinate + * - PS + - axi_iic_eeprom + - axi_iic_eeprom_io + - 0x44A4_0000 + - 0x52 + - EEPROM + +.. list-table:: DE10-Nano + :header-rows: 1 + + * - I2C type + - I2C manager instance + - Alias + - Address + - Device Address + - I2C subordinate + * - PS + - i2c1 + - sys_hps_i2c1 + - --- + - 0x52 + - --- + +Device address considering the EEPROM address pins ``A0=0``, ``A1=1``, ``A2=0``. + +SPI connections +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +.. list-table:: + :widths: 25 25 25 25 + :header-rows: 1 + + * - SPI type + - SPI manager instance + - SPI subordinate + - CS + * - PL + - axi_spi_engine + - ad4052 + - 0 + +GPIOs +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The Software GPIO number is calculated as follows: + +- Cora Z7S: the offset is 54 + +.. list-table:: + :widths: 25 25 25 25 + :header-rows: 2 + + * - GPIO signal + - Direction + - HDL GPIO EMIO + - Software GPIO + * - + - (from FPGA view) + - + - Zynq-7000 + * - adc_cnv + - OUTPUT + - 34 + - 88 + * - adc_gp1 + - INOUT + - 33 + - 87 + * - adc_gp0 + - INOUT + - 32 + - 86 + +- DE10-Nano: the offset is 32 + +.. list-table:: + :widths: 25 25 25 25 + :header-rows: 2 + + * - GPIO signal + - Direction + - HDL GPIO EMIO + - Software GPIO + * - + - (from FPGA view) + - + - DE10-Nano + * - adc_cnv + - OUTPUT + - 34 + - 2 + * - adc_gp1 + - INPUT + - 33 + - 1 + * - adc_gp0 + - INPUT + - 32 + - 0 + +Interrupts +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Below are the Programmable Logic interrupts used in this project. + +=================== === ========== =========== +Instance name HDL Linux Zynq Actual Zynq +=================== === ========== =========== +axi_adc_dma 13 57 89 +spi_adc_axi_regmap 12 56 88 +axi_iic_eeprom 11 55 87 +=================== === ========== =========== + +================ === =============== ================ +Instance name HDL Linux DE10-Nano Actual DE10-Nano +================ === =============== ================ +axi_dmac_0 4 44 76 +axi_spi_engine_0 3 43 75 +================ === =============== ================ + +Building the HDL project +------------------------------------------------------------------------------- + +The design is built upon ADI's generic HDL reference design framework. +ADI distributes the bit/elf files of these projects as part of the +:dokuwiki:`ADI Kuiper Linux `. +If you want to build the sources, ADI makes them available on the +:git-hdl:`HDL repository `. To get the source you must +`clone `__ +the HDL repository, and then build the project as follows: + +**Linux/Cygwin/WSL** + +.. shell:: + + $cd hdl/projects/ad4052_ardz/coraz7s + $make + +.. shell:: + + $cd hdl/projects/ad4052_ardz/de10nano + $make + +A more comprehensive build guide can be found in the :ref:`build_hdl` user guide. + +Resources +------------------------------------------------------------------------------- + +Hardware related +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- Product datasheets: + + - :adi:`AD4050` + - :adi:`AD4052` + +HDL related +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :git-hdl:`AD4052-ARDZ HDL project source code ` + +.. list-table:: + :widths: 30 35 35 + :header-rows: 1 + + * - IP name + - Source code link + - Documentation link + * - AXI_PWM_GEN + - :git-hdl:`library/axi_pwm_gen ` + - :ref:`here ` + * - AXI_CLKGEN + - :git-hdl:`library/axi_dmac ` * + - :ref:`here ` + * - AXI_DMAC + - :git-hdl:`library/axi_dmac ` + - :ref:`here ` + * - AXI_HDMI_TX + - :git-hdl:`library/axi_hdmi_tx ` ** + - :ref:`here ` + * - AXI_SYSID + - :git-hdl:`library/axi_sysid ` + - :ref:`here ` + * - AXI_SPI_ENGINE + - :git-hdl:`library/spi_engine/axi_spi_engine ` + - :ref:`here ` + * - SPI_ENGINE_EXECUTION + - :git-hdl:`library/spi_engine/spi_engine_execution ` + - :ref:`here ` + * - SPI_ENGINE_INTERCONNECT + - :git-hdl:`library/spi_engine/spi_engine_interconnect ` + - :ref:`here ` + * - SPI_ENGINE_OFFLOAD + - :git-hdl:`library/spi_engine/spi_engine_offload` + - :ref:`here ` + * - SYSID_ROM + - :git-hdl:`library/sysid_rom ` + - :ref:`here ` + +.. admonition:: Legend + :class: note + + - ``*`` instantiated only for Cora Z7S + - ``**`` instantiated only for DE10-Nano + +- :ref:`SPI Engine Framework documentation ` + +Software related +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +- :git-linux:`AD4052 Linux driver ad4052.c ` + +.. include:: ../common/more_information.rst + +.. include:: ../common/support.rst diff --git a/docs/projects/index.rst b/docs/projects/index.rst index 8fa7c61b11..2441c06434 100644 --- a/docs/projects/index.rst +++ b/docs/projects/index.rst @@ -25,6 +25,7 @@ Contents AD411x-AD717x AD4134-FMC AD4170-ASDZ + AD4052-ARDZ AD4630-FMC/AD4030-FMC/ADAQ4224-FMC AD469X-EVB AD485X-FMCZ