From b5ef692a21adcc2ea4d4398ad2e21d357bbca7fa Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Tue, 23 May 2023 15:02:02 +0300 Subject: [PATCH] adi_regmap_dac.txt: DDS phase extend capabilities --- docs/regmap/adi_regmap_dac.txt | 131 ++++++++++++++++++++++++++------- 1 file changed, 105 insertions(+), 26 deletions(-) diff --git a/docs/regmap/adi_regmap_dac.txt b/docs/regmap/adi_regmap_dac.txt index 525e637c29..a3766867e5 100644 --- a/docs/regmap/adi_regmap_dac.txt +++ b/docs/regmap/adi_regmap_dac.txt @@ -108,7 +108,7 @@ FIELD [14] 0x0 SYMB_8_16B RW -Select number of bits for symbol format mode (1 represents 8b, 0 represents 16b) +Select number of bits for symbol format mode (1 represents 8b, 0 represents 16b) ENDFIELD FIELD @@ -239,7 +239,7 @@ FIELD [0] 0x0 STATUS RO -Interface status, if set indicates no errors. If not set, there +Interface status, if set indicates no errors. If not set, there are errors, software may try resetting the cores. ENDFIELD @@ -297,7 +297,7 @@ FIELD [27:16] 0x00 DRP_ADDRESS[11:0] RW -DRP address, designs that contain more than one DRP accessible primitives +DRP address, designs that contain more than one DRP accessible primitives have selects based on the most significant bits (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1). ENDFIELD @@ -329,7 +329,7 @@ FIELD [16] 0x0 DRP_STATUS RO -If set indicates busy (access pending). The read data may not be valid if +If set indicates busy (access pending). The read data may not be valid if this bit is set (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1). ENDFIELD @@ -415,7 +415,7 @@ FIELD [7:0] 0x00 USR_CHANMAX[7:0] RW -This indicates the maximum number of inputs for the channel data multiplexers. User may add +This indicates the maximum number of inputs for the channel data multiplexers. User may add different processing modules as inputs to the dac. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). ENDFIELD @@ -469,15 +469,24 @@ REG_CHAN_CNTRL_1 DAC Channel Control & Status (channel - 0) ENDREG +FIELD +[21:16] 0x000 +DDS_PHASE_DW[5:0] +R +The DDS phase data width offers the HDL parameter configuration with the same name. +This information is used in conjunction with REG_CHAN_CNTRL_9 and REG_CHAN_CNTRL_10. +More info at https://wiki.analog.com/resources/fpga/docs/dds +ENDFIELD + FIELD [15:0] 0x0000 DDS_SCALE_1[15:0] RW -The DDS scale for tone 1. Defines the amplitude of the tone. The format is -1.1.14 fixed point (signed, integer, fractional). The DDS in general runs on -16-bits, note that if you do use both channels and set both scale to 0x4000, -it is over-range. The final output is (channel_1_fullscale * scale_1) + -(channel_2 * scale_2). +The DDS scale for tone 1. Sets the amplitude of the tone. The format is +1.1.14 fixed point (signed, integer, fractional). The DDS in general runs on +16-bits, note that if you do use both channels and set both scale to 0x4000, +it is over-range. The final output is (tone_1_fullscale * scale_1) + +(tone_2_fullscale * scale_2). NOT-APPLICABLE if DDS_DISABLE is set (0x1). ENDFIELD @@ -494,7 +503,7 @@ FIELD [31:16] 0x0000 DDS_INIT_1[15:0] RW -The DDS phase initialization for tone 1. Defines the initial phase offset of +The DDS phase initialization for tone 1. Sets the initial phase offset of the tone. NOT-APPLICABLE if DDS_DISABLE is set (0x1). ENDFIELD @@ -503,10 +512,12 @@ FIELD [15:0] 0x0000 DDS_INCR_1[15:0] RW -Defines the resolution of the phase accumulator. Its value can be defined by -INCR = (f_out * 2^16) * clkratio / f_if; where f_out is the generated -output frequency, and f_if is the frequency of the digital interface, and +Sets the frequency of the phase accumulator. Its value can be calculated by +INCR = (f_out * 2^16) * clkratio / f_if; where f_out is the generated +output frequency, and f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. +If DDS_PHASE_DW is greater than 16(from REG_CHAN_CNTRL_1), the phase +increment for tone 1 is extended in REG_CHAN_CNTRL_9. NOT-APPLICABLE if DDS_DISABLE is set (0x1). ENDFIELD @@ -523,11 +534,11 @@ FIELD [15:0] 0x0000 DDS_SCALE_2[15:0] RW -The DDS scale for tone 1. Defines the amplitude of the tone. The format is -1.1.14 fixed point (signed, integer, fractional). The DDS in general runs on -16-bits, note that if you do use both channels and set both scale to 0x4000, -it is over-range. The final output is (channel_1_fullscale * scale_1) + -(channel_2 * scale_2). +The DDS scale for tone 2. Sets the amplitude of the tone. The format is +1.1.14 fixed point (signed, integer, fractional). The DDS in general runs on +16-bits, note that if you do use both channels and set both scale to 0x4000, +it is over-range. The final output is (tone_1_fullscale * scale_1) + +(tone_2_fullscale * scale_2). NOT-APPLICABLE if DDS_DISABLE is set (0x1). ENDFIELD @@ -544,8 +555,9 @@ FIELD [31:16] 0x0000 DDS_INIT_2[15:0] RW -The DDS phase initialization for tone 1. Defines the initial phase offset of -the tone. +The DDS phase initialization for tone 2. Sets the initial phase offset of +the tone. If DDS_PHASE_DW is greater than 16(from REG_CHAN_CNTRL_1), the phase +init for tone 2 is extended in REG_CHAN_CNTRL_10. NOT-APPLICABLE if DDS_DISABLE is set (0x1). ENDFIELD @@ -553,10 +565,12 @@ FIELD [15:0] 0x0000 DDS_INCR_2[15:0] RW -Defines the resolution of the phase accumulator. Its value can be defined by -INCR = (f_out * 2^16) * clkratio / f_if; where f_out is the generated -output frequency, and f_if is the frequency of the digital interface, and +Sets the frequency of the phase accumulator. Its value can be calculated by +INCR = (f_out * 2^16) * clkratio / f_if; where f_out is the generated +output frequency, and f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. +If DDS_PHASE_DW is greater than 16(from REG_CHAN_CNTRL_1), the phase +increment for tone 2 is extended in REG_CHAN_CNTRL_10. NOT-APPLICABLE if DDS_DISABLE is set (0x1). ENDFIELD @@ -737,7 +751,7 @@ FIELD [31:16] 0x0000 USR_INTERPOLATION_M[15:0] RW -This holds the user interpolation M value of the channel that is currently being selected on +This holds the user interpolation M value of the channel that is currently being selected on the multiplexer above. The total interpolation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1). ENDFIELD @@ -764,7 +778,7 @@ FIELD [0] 0x0 DAC_IQ_MODE[0] RW -Enable complex mode. In this mode the driven data to the DAC must be a sequence +Enable complex mode. In this mode the driven data to the DAC must be a sequence of I and Q sample pairs. ENDFIELD @@ -778,6 +792,71 @@ ENDFIELD ############################################################################################ ############################################################################################ +REG +0x010B +REG_CHAN_CNTRL_9 +DAC Channel Control & Status (channel - 0) +ENDREG + +FIELD +[31:16] 0x0000 +DDS_INIT_1_EXTENDED[15:0] +RW +The extended DDS phase initialization for tone 1. Sets the initial phase offset of +the tone. +The extended init(phase) value should be calculated according to DDS_PHASE_DW +value from REG_CHAN_CNTRL_1 +NOT-APPLICABLE if DDS_DISABLE is set (0x1). +ENDFIELD + +FIELD +[15:0] 0x0000 +DDS_INCR_1_EXTENDED[15:0] +RW +Sets the frequency of tone 1's phase accumulator. Its value can be +calculated by INCR = (f_out * 2^phaseDW) * clkratio / f_if; +Where f_out is the generated output frequency, DDS_PHASE_DW value can be found +in REG_CHAN_CNTRL_1 in case DDS_PHASE_DW is not 16, f_if is the frequency of +the digital interface, and clock_ratio is the ratio between the sampling clock +and the interface clock. +NOT-APPLICABLE if DDS_DISABLE is set (0x1). +ENDFIELD + +############################################################################################ +############################################################################################ + +REG +0x010C +REG_CHAN_CNTRL_10 +DAC Channel Control & Status (channel - 0) +ENDREG + +FIELD +[31:16] 0x0000 +DDS_INIT_2_EXTENDED[15:0] +RW +The extended DDS phase initialization for tone 2. Sets the initial phase offset of +the tone. +The extended init(phase) value should be calculated according to DDS_PHASE_DW +value from REG_CHAN_CNTRL_1 +NOT-APPLICABLE if DDS_DISABLE is set (0x1). +ENDFIELD + +FIELD +[15:0] 0x0000 +DDS_INCR_2_EXTENDED[15:0] +RW +Sets the frequency of tone 2's phase accumulator. Its value can be +calculated by INCR = (f_out * 2^phaseDW) * clkratio / f_if; +Where f_out is the generated output frequency, DDS_PHASE_DW value can be found +in REG_CHAN_CNTRL_1 in case DDS_PHASE_DW is not 16, f_if is the frequency of +the digital interface, and clock_ratio is the ratio between the sampling clock +and the interface clock. +NOT-APPLICABLE if DDS_DISABLE is set (0x1). +ENDFIELD + +############################################################################################ +############################################################################################ REG 0x0110 REG_*