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- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + d="m 5.77,0 -8.65,5 0,-10 8.65,5 z" + id="path18753-0-6-8" /> + inkscape:window-height="1009" + inkscape:window-x="1909" + inkscape:window-y="-11" + inkscape:window-maximized="1"> + id="grid4147" /> @@ -3354,980 +879,718 @@ inkscape:label="Layer 1" inkscape:groupmode="layer" id="layer1" - transform="translate(0,542.12572)"> + transform="translate(0,-552.36202)"> - -   -   -       -   -   - - - REGMAP - - - - AXI ADC TRIGGER - ADC ch A [15:0] -   - - - - - - - - - - - - - ADC ch B [15:0] - - - - - - - - + style="display:inline;opacity:1;fill:#000000;fill-opacity:0;fill-rule:nonzero;stroke:#000000;stroke-width:2.00000012;stroke-linecap:square;stroke-linejoin:round;stroke-miterlimit:0;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" + id="rect4477" + width="499.31705" + height="469.91263" + x="88.143837" + y="566.01422" />   + id="tspan10881" + x="185.66757" + y="845.47211" />   - + id="tspan5705" + x="305.91162" + y="598.41553" + style="font-size:25.08472824px" /> Externaltrigger control + id="tspan11706" + x="707.54004" + y="778.37616" /> + trigger_i[1:0] + x="338.00705" + y="1002.5098" + id="tspan10800" + style="font-size:17.5px;text-align:center;text-anchor:middle">Register Map + trigger_o[1:0] + id="tspan4389" + x="-893.63354" + y="560.71167" + style="font-size:17.5px">AD9963 INTERFACE CMOS trigger_t[1:0] + id="tspan4414" + x="595" + y="620.16473" + style="font-size:15.00000095px">TX_CLK + I[1] + id="tspan4439" + x="595" + y="649.48358" + style="font-size:15.00000095px">TX_IQ + I[0] + id="tspan4464" + x="595" + y="680.16473" + style="font-size:15.00000095px">TX_DATA +   + id="tspan4414-8" + x="595" + y="849.63312" + style="font-size:15.00000095px">TRX_CLK +   - + id="tspan4439-4" + x="595" + y="881.63324" + style="font-size:15.00000095px">TRX_IQ +   + id="tspan4464-6" + x="595" + y="914.18268" + style="font-size:15.00000095px">TRX_DATA + style="fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:2;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" + id="rect4554-2" + width="275.68262" + height="200.67418" + x="241.4856" + y="782.63196" /> - - - - Ch AMUX + style="display:inline;opacity:1;fill:#ffcccc;fill-opacity:1;fill-rule:nonzero;stroke:#a01414;stroke-width:1;stroke-linecap:square;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" + id="rect4870-8-2-6" + width="239.80785" + height="148.57904" + x="260.88922" + y="815.41888" /> + style="display:inline;opacity:1;fill:#ffcccc;fill-opacity:1;fill-rule:nonzero;stroke:#a01414;stroke-width:1;stroke-linecap:square;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" + id="rect4870-9-3-8" + width="239.80785" + height="148.57904" + x="257.83521" + y="812.32996" /> OutMUX + id="tspan4966-3" + x="318.29858" + y="837.70789" + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:17.5px;font-family:Arial;-inkscape-font-specification:'Arial Bold';fill:#000000;fill-opacity:1">RX CHANNEL - - trigger_out -   -    - trigger_in(LA) - up_triggerd_o[1:0] - - -  32 bitdelaycounter - + sodipodi:nodetypes="ccccc" /> + + + + + + + + + + + ADC data +embeddedtriger(bit 15) -   -   ADC ch A - IQ ADC ch B + x="327.18192" + y="920.45154" + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:12.5px;font-family:Arial;-inkscape-font-specification:'Arial Bold';text-align:center;text-anchor:middle;stroke-width:1;stroke-miterlimit:4;stroke-dasharray:none" + id="tspan5900-6">Corr + + + style="shape-rendering:crispEdges" + id="g4581-2" + transform="translate(72.146239,261.17086)"> + transform="matrix(0,-1.1885989,1.1885989,0,-59.978473,-122.17314)" + y="367.16461" + x="-667.7301" + height="37.394592" + width="36.778587" + id="rect11202-0" + style="display:inline;opacity:1;fill:none;fill-opacity:1;fill-rule:nonzero;stroke:#a01414;stroke-width:0.84132671;stroke-linecap:round;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" /> + PNMON Ch BMUX + sodipodi:linespacing="125%" + id="text4574" + y="907.2666" + x="414.8551" + style="font-style:normal;font-weight:normal;font-size:12.5px;line-height:125%;font-family:Arial;letter-spacing:0px;word-spacing:0px;display:inline;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" + xml:space="preserve">DC Filter + + + ChannelTrigger + id="tspan5140" + x="339.24268" + y="803.23248" + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:17.5px;font-family:Arial;-inkscape-font-specification:'Arial Bold';fill:#000000;fill-opacity:1">RX CORE + + + style="stroke-width:1;stroke-miterlimit:4;stroke-dasharray:none;shape-rendering:crispEdges" + id="g5965" + transform="translate(71.3477,-20.47514)"> + y="675.90021" + x="314.08371" + height="63.554653" + width="75.863747" + id="rect4899" + style="opacity:1;fill:none;fill-opacity:1;fill-rule:nonzero;stroke:#0f3296;stroke-width:1;stroke-linecap:square;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;shape-rendering:crispEdges" /> CH A + transform="scale(1.0058158,0.99421783)" + sodipodi:linespacing="125%" + id="text4576-6" + y="709.1687" + x="350.12421" + style="font-style:normal;font-weight:normal;font-size:9.91771126px;line-height:125%;font-family:Arial;letter-spacing:0px;word-spacing:0px;display:inline;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" + xml:space="preserve">IQ Correction - + + + + CH B + style="font-style:normal;font-weight:normal;font-size:4.54513264px;line-height:125%;font-family:Arial;letter-spacing:0px;word-spacing:0px;opacity:1;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;shape-rendering:crispEdges" + x="292.30197" + y="711.45038" + id="text11622" + sodipodi:linespacing="125%">PRBS Pin 0(Ti)triggerdetect + id="tspan11628" + x="270.89429" + y="692.98926" + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:12.5px;font-family:Arial;-inkscape-font-specification:'Arial Bold';stroke-width:1;stroke-miterlimit:4;stroke-dasharray:none">PATTERN Pin 1(To)triggerdetect - + id="tspan11632" + x="295.38791" + y="675.26074" + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:12.5px;font-family:Arial;-inkscape-font-specification:'Arial Bold';stroke-width:1;stroke-miterlimit:4;stroke-dasharray:none">DDS trigger_out_la + id="tspan11636" + x="294.35275" + y="656.90442" + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:12.5px;font-family:Arial;-inkscape-font-specification:'Arial Bold';stroke-width:1;stroke-miterlimit:4;stroke-dasharray:none">DMA + sodipodi:nodetypes="ccccc" /> + sodipodi:nodetypes="cc" /> + sodipodi:nodetypes="cc" /> + TX CHANNEL + id="path34982-7-5-9-2" + d="m 522.87897,718.1378 0,-6.1966 -28.90705,0 c 0,0 -0.0827,-5.53177 -0.083,-8.24218 -1.7e-4,-2.71041 0.082,-8.24219 0.082,-8.24219 l 28.90813,0 0,-6.19659 14.64737,14.43878 z" + style="fill:#c8c8c8;fill-opacity:1;fill-rule:evenodd;stroke:#0f3296;stroke-width:1;stroke-linecap:round;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;shape-rendering:crispEdges" /> + sodipodi:nodetypes="cccsccccc" /> 2 FFsync - + id="tspan5140-3" + x="340.36829" + y="597.0163" + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:17.5px;font-family:Arial;-inkscape-font-specification:'Arial Bold';fill:#000000;fill-opacity:1">TX CORE - -   32 bitholdoffcounter + transform="matrix(-1,0,0,1,389.35044,-132.99876)" + style="display:inline;fill:#0f3296;fill-opacity:1;stroke:#0f3296;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" + id="g5816" /> + + + + + + + + + + + DAC_FIFO_I + DAC_FIFO_Q + ADC_FIFO_I + + id="tspan7846-3-0" + x="97.835014" + y="911.52161">ADC_FIFO_Q + + + State hold + id="tspan8079" + x="22.192762" + y="1014.7585">S_AXI_MM + - diff --git a/_images/block_diagram11.svg b/_images/block_diagram11.svg index e94f990e33..e0f4dae75a 100644 --- a/_images/block_diagram11.svg +++ b/_images/block_diagram11.svg @@ -1,63 +1,4 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - image/svg+xml - - - - - - - - - Register Map - - - - S_AXI_MM - - - - - - MMCM - clk - clk2 - clk_0 - clk_1 - CLKIN1 - CLKIN2 - - - - BUFG - BUFG - - - CLKOUT0 - CLKOUT1 - - \ No newline at end of file + + + +
DMA_FIFO
DMA_FIFO
ADC
DATA
PROCESSING
ADC...
REGISTER
MAP
REGISTER...
LVDS OR CMOS
INTERFACE
LVDS OR CMOS...
AXI SLAVE
AXI SLAVE
LVDS OR CMOS
LVDS OR CMOSText is not SVG - cannot display \ No newline at end of file diff --git a/_images/block_diagram12.svg b/_images/block_diagram12.svg index 4384f9d685..8b1ed331df 100644 --- a/_images/block_diagram12.svg +++ b/_images/block_diagram12.svg @@ -16,7 +16,7 @@ id="svg2" version="1.1" inkscape:version="0.91 r13725" - sodipodi:docname="axi_dac_interpolate.svg"> + sodipodi:docname="axi_adc_decimate.svg"> image/svg+xml - + @@ -850,12 +850,12 @@ id="layer1" transform="translate(0,-752.36203)"> + width="638.54614" + height="235.86682" + x="100.22995" + y="782.36804" /> + transform="translate(-73.93485,111.79084)"> Interpolation byDecimation by Interpolation byDecimation by Interpolation byDecimation by Interpolation + sodipodi:role="line">Decimation Interpolation byDecimation by Interpolation + sodipodi:role="line">Decimation + transform="translate(-75.39434,112.42077)"> + transform="translate(76.327317,111.01986)"> + transform="translate(75.932007,105.7299)"> CHANNEL_B + width="290.69589" + height="91.70903" + x="121.118" + y="803.55511" /> + width="290.69611" + height="91.664299" + x="121.08652" + y="903.57385" /> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Store-and-forwardData Buffer + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + +   +   +       +   +   + + + REGMAP + + + + AXI ADC TRIGGER + ADC ch A [15:0] +   + + + + + + + + + + + + + ADC ch B [15:0] + + + + + + + + +   +   + + Externaltrigger control + trigger_i[1:0] + trigger_o[1:0] + trigger_t[1:0] + I[1] + I[0] +   +   + +   + + + + + + Ch AMUX + + OutMUX + + + trigger_out +   +    + trigger_in(LA) + up_triggerd_o[1:0] + + +  32 bitdelaycounter + + + ADC data +embeddedtriger(bit 15) +   +   ADC ch A + ADC ch B + + + + Ch BMUX + ChannelTrigger + + + CH A + + + CH B + Pin 0(Ti)triggerdetect + Pin 1(To)triggerdetect + + trigger_out_la + + + + + + 2 FFsync + + + +   32 bitholdoffcounter + + + State hold - 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- -
DMA AXIS
DMA AXIS
DMA_CLK
DMA_CLK
TX core
TX core
DMA
interface
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TPG
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FIFO
FIFO
CSC
CSC
Data
Clipping
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Data 
interleaving
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Chroma
subsampling
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DATA_24
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VGA_GREEN
VGA_GREEN
VGA_BLUE
VGA_BLUE
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DATA_16
Embedded
Sync
Embedded...
DATA_16_ES
DATA_16_ES
Data 
splitting
Data...
HSYNC/VSYNC/DE
HSYNC/VSYNC...
Sync
Signals
Sync...
HDMI_OUT_CLK
HDMI_OUT_CLK
VGA_OUT_CLK
VGA_OUT_CLK
REFERENCE_CLK
REFERENCE_...
S_AXI_LITE
S_AXI_LITE
Register Map
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  + style="fill:none;fill-opacity:1;stroke:#000000;stroke-width:2;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" + id="rect817" + width="343.51617" + height="214.86215" + x="148.8501" + y="-39.523445" /> s_axi - - -   - - + xml:space="preserve" + style="font-style:normal;font-weight:normal;font-size:19.8442688px;line-height:1.25;font-family:sans-serif;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1.48832011" + x="185.40535" + y="12.319815" + id="text821" + transform="scale(0.93758119,1.0665743)">Register Map Register Map - - - - axi_pwm_gen_1 - - - - axi_pwm_gen_1 - - - - axi_pwm_gen_1 - - - - axi_pwm_gen_1 - - - - offsetcounter - - - + xml:space="preserve" + style="font-style:normal;font-weight:normal;font-size:19.8442688px;line-height:1.25;font-family:sans-serif;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1.48832011" + x="195.31564" + y="97.282433" + id="text827" + transform="scale(0.93758119,1.0665743)">FSM external_sync - - - equal - - - pwm 0 - - - pwp 1 - - - - equal - - - - equal - - + xml:space="preserve" + style="font-style:normal;font-weight:normal;font-size:19.8442688px;line-height:1.25;font-family:sans-serif;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1.48832011" + x="300.77356" + y="73.363045" + id="text831" + transform="scale(0.93758119,1.0665743)">Tacho measurementPWM generatorTemperature read + + + - - offset_1 - - + style="fill:none;stroke:#000000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;marker-start:url(#EmptyTriangleInL);marker-end:url(#EmptyTriangleOutL)" + d="M 238.19217,96.05085 H 274.742" + id="path843" + inkscape:connector-curvature="0" /> + style="fill:none;stroke:#000000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;marker-start:url(#EmptyTriangleInL-3);marker-end:url(#EmptyTriangleOutL-2)" + d="M 209.19268,76.577872 V 27.042479" + id="path843-4" + inkscape:connector-curvature="0" /> + style="fill:none;stroke:#000000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;marker-end:url(#marker5102)" + d="M 493.08041,129.04571 H 555.673" + id="path5040" + inkscape:connector-curvature="0" /> - - offset_2 - - offset_15 - - - - - + style="fill:none;stroke:#000000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;marker-start:url(#marker5553);marker-end:url(#marker5483)" + d="M 82.098308,6.538604 H 167.25212" + id="path5042" + inkscape:connector-curvature="0" /> - pwm 2 + style="fill:none;stroke:#000000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;marker-end:url(#marker6013)" + d="M 81.178455,132.04619 H 147.44331" + id="path5044" + inkscape:connector-curvature="0" /> + style="fill:none;stroke:#000000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;marker-end:url(#marker5102-4)" + d="M 493.08041,65.88905 H 555.673" + id="path5040-1" + inkscape:connector-curvature="0" /> pwm 15 - + id="tspan8157" + x="109.04962" + y="98.224869" + style="stroke-width:0.42094442" /> sync + id="tspan8161" + x="88.261047" + y="-3.9233534" + style="stroke-width:1.48832011;font-size:16px">S_AXI sync + id="tspan8165" + x="86.582794" + y="115.14221" + style="stroke-width:1.48832011;font-size:16px">Tacho sync - - - equal - - + id="tspan8169" + x="540.28192" + y="52.419346" + style="line-height:1.25;stroke-width:1.48832011;font-size:16px">PWM sync - - offset_0 - - - + id="tspan8173" + x="540.8924" + y="111.64744" + style="font-size:16px;stroke-width:1.48832011">Irq diff --git a/_images/block_diagram18.svg b/_images/block_diagram18.svg index 75b78dd6be..8599be1e90 100644 --- a/_images/block_diagram18.svg +++ b/_images/block_diagram18.svg @@ -2,6 +2,7 @@ + inkscape:version="0.47 r22583" + sodipodi:docname="axi_hdmi_rx_core.svg"> + id="defs4"> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + inkscape:stockid="TriangleInM"> + + + + + + + inkscape:stockid="TriangleInM"> + inkscape:isstock="true"> + inkscape:connector-curvature="0" + id="path9683" + d="m 5.77,0 -8.65,5 0,-10 8.65,5 z" + style="fill:#000000;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:1pt;stroke-opacity:1" + transform="scale(-0.4,-0.4)" /> + + + + id="path15645-20-64" + d="m 5.77,0 -8.65,5 0,-10 8.65,5 z" + style="fill:#000000;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:1pt;stroke-opacity:1" + transform="scale(-0.4,-0.4)" /> + id="path15645-1-5-00" + d="m 5.77,0 -8.65,5 0,-10 8.65,5 z" + style="fill:#000000;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:1pt;stroke-opacity:1" + transform="scale(-0.4,-0.4)" /> + + + + + + + + + + + + + + + + + + + + + + + + + refY="0" + refX="0" + id="marker9429-1" + style="overflow:visible" + inkscape:isstock="true"> + id="path9431-4" + d="m 5.77,0 -8.65,5 0,-10 8.65,5 z" + style="fill:#000000;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:1pt;stroke-opacity:1" + transform="scale(0.4,0.4)" + inkscape:connector-curvature="0" /> + + + + + + + + + + + + + refY="0" + refX="0" + id="marker11392-2-4-3-5" + style="overflow:visible" + inkscape:isstock="true" + inkscape:collect="always"> @@ -148,33 +1055,43 @@ borderopacity="1.0" inkscape:pageopacity="0.0" inkscape:pageshadow="2" - inkscape:zoom="2.0000001" - inkscape:cx="175.42523" - inkscape:cy="67.747576" + inkscape:zoom="1.4142136" + inkscape:cx="295.6191" + inkscape:cy="224.35276" inkscape:document-units="px" inkscape:current-layer="layer1" - showgrid="true" + showgrid="false" + width="800mm" + units="px" inkscape:window-width="1920" - inkscape:window-height="1001" - inkscape:window-x="1181" - inkscape:window-y="1346" + inkscape:window-height="924" + inkscape:window-x="0" + inkscape:window-y="25" inkscape:window-maximized="1" - scale-x="1" - units="px" - viewbox-height="230.82" - fit-margin-top="0" - fit-margin-left="0" - fit-margin-right="0" - fit-margin-bottom="0" /> + showguides="true" + inkscape:snap-grids="true" + inkscape:snap-text-baseline="true" + inkscape:snap-bbox="true" + inkscape:bbox-nodes="false" + inkscape:snap-nodes="false"> + + + id="metadata7"> image/svg+xml - + @@ -182,170 +1099,483 @@ inkscape:label="Layer 1" inkscape:groupmode="layer" id="layer1" - transform="translate(-69.106348,58.128533)"> + transform="translate(0,-652.36204)"> + style="color:#000000;fill:#aaccee;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.99999994;marker:none;visibility:visible;display:inline;overflow:visible;enable-background:accumulate" + id="rect3004" + width="510" + height="162" + x="151.57715" + y="751.60675" /> + + Register MapCSC + - - + id="tspan8761" + x="698.60443" + y="826.05334" + style="font-size:15px"> to DMA + + style="fill:none;stroke:#000000;stroke-width:2;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:0;stroke-opacity:1;stroke-dasharray:none;marker-end:url(#marker11148)" + d="m 280.02465,793.81801 0,43.49369 227.52051,0" + id="path9555" + inkscape:connector-curvature="0" + sodipodi:nodetypes="ccc" /> + + + EmbededSync + + + Register Map + SYNC + x="63.315952" + y="793.07391" + id="tspan10877" + style="font-size:15px">CLK S_AXI + id="tspan10881" + x="212.33582" + y="1075.9921" /> ROM1DATA + + id="tspan8761-0" + x="66.052895" + y="875.20013" + style="font-size:15px;fill:#000000">S_AXI_Lite ROM2 + + id="tspan11706" + x="734.20831" + y="1008.8961" /> - - + id="g4501" + transform="translate(25.277141,243.24474)"> + + Super Sampling + + + + TPM Sync monitor + + + + + + + Datainterleave + + + 16 + (SYS ROM)16 + + id="tspan3534-5" + x="397.4523" + y="782.66571" + style="font-size:12.50000095px">24 + + + + (PR ROM)32 + + + - + id="tspan3534-5-6-1" + x="663.52057" + y="803.65088" + style="font-size:12.50000095px">64 + + + + + Rx core diff --git a/_images/block_diagram19.svg b/_images/block_diagram19.svg index dc10b53b31..83d81f0de2 100644 --- a/_images/block_diagram19.svg +++ b/_images/block_diagram19.svg @@ -1,532 +1,4 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - image/svg+xml - - - - - - - - OFFLOAD FSM - - - - AXI REGISTERMAP - BYPASS - - S_AXIS - - AXI_MM - SOURCE - M_AXIS - - DESTINATION - - - M_STORAGE_AXIS - S_STORAGE_AXIS - - Storage Unit - - + + + +
DMA AXIS
DMA AXIS
DMA_CLK
DMA_CLK
TX core
TX core
DMA
interface
DMA...
TPG
TPG
FIFO
FIFO
CSC
CSC
Data
Clipping
Data...
Data 
interleaving
Data...
Chroma
subsampling
Chroma...
DATA_36
DATA_36
DATA_24
DATA_24
VGA_RED
VGA_RED
VGA_GREEN
VGA_GREEN
VGA_BLUE
VGA_BLUE
DATA_16
DATA_16
Embedded
Sync
Embedded...
DATA_16_ES
DATA_16_ES
Data 
splitting
Data...
HSYNC/VSYNC/DE
HSYNC/VSYNC...
Sync
Signals
Sync...
HDMI_OUT_CLK
HDMI_OUT_CLK
VGA_OUT_CLK
VGA_OUT_CLK
REFERENCE_CLK
REFERENCE_...
S_AXI_LITE
S_AXI_LITE
Register Map
Register MapText is not SVG - cannot display \ No newline at end of file diff --git a/_images/block_diagram2.svg b/_images/block_diagram2.svg index d4688c36fa..b73c3a3951 100644 --- a/_images/block_diagram2.svg +++ b/_images/block_diagram2.svg @@ -1,4 +1,487 @@ - - - -
DMA_FIFO
DMA_FIFO
ADC
DATA
PROCESSING
ADC...
REGISTER
MAP
REGISTER...
AD7768
INTERFACE
AD7768...
AXI SLAVE
AXI SLAVE
ADC INTERFACE
ADC INTERFACEText is not SVG - cannot display \ No newline at end of file + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + DB[15:0]WRn/RDn + + + + + INPUT + OUTPUT + + + + + + + + S_AXI_LITE + WR_FIFO + + REGISTERMAP + + + CONTROL  + PARALLEL INTERFACE + + BUSY + + burst_length + + + + + + + + 15:0 + adc_data + adc_valid + adc_sync + + diff --git a/_images/block_diagram20.svg b/_images/block_diagram20.svg index a130c28fe4..844cb8deff 100644 --- a/_images/block_diagram20.svg +++ b/_images/block_diagram20.svg @@ -1,4 +1,1715 @@ - - - -
MII/GMII
MII/GMII
RMII
RMII
mac_txd[3:0]
mac_txd[...
mac_tx_en
mac_tx_en
mac_tx_er
mac_tx_er
mii_col
mii_col
mii_crs
mii_crs
mii_rxd[3:0]
mii_rxd[...
mii_rx_clk
mii_rx_c...
mii_rx_dv
mii_rx_dv
mii_rx_er
mii_rx_er
mii_tx_clk
mii_tx_c...
util_mii_to_rmii
util_mii_t...
rmii_txd[1:0]
rmii_txd...
rmii_tx_en
rmii_tx_...
phy_crs_dv
phy_crs_...
phy_rxd[1:0]
phy_rxd[...
phy_rx_er
phy_rx_er
ref_clk
ref_clk
reset_n
reset_n
Zynq-7000/Zynq Ultrascale+ MPSoC - PS Gigabit Ethernet MAC
Zynq-7000/Zynq Ultra...
RMII ADIN1300 PHY
RMII ADIN1...
FPGA
FPGAText is not SVG - cannot display \ No newline at end of file + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + +   + s_axi + + +   + + + Register Map + + + + axi_pwm_gen_1 + + + + axi_pwm_gen_1 + + + + axi_pwm_gen_1 + + + + axi_pwm_gen_1 + + + + offsetcounter + + + + external_sync + + + equal + + + pwm 0 + + + pwp 1 + + + + equal + + + + equal + + + + + offset_1 + + + + + + + offset_2 + + offset_15 + + + + + + + pwm 2 + + pwm 15 + + sync + sync + sync + + + equal + + + sync + + offset_0 + + + + + diff --git a/_images/block_diagram21.svg b/_images/block_diagram21.svg index f280e32f22..75b78dd6be 100644 --- a/_images/block_diagram21.svg +++ b/_images/block_diagram21.svg @@ -9,1902 +9,343 @@ xmlns="http://www.w3.org/2000/svg" xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd" xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape" - width="800" - height="600" - viewBox="0 0 800.00001 600" - id="svg2" + width="500" + height="250" + viewBox="0 0 500 250" version="1.1" - inkscape:version="0.91 r13725" - sodipodi:docname="rfifo_hdl.svg"> + id="svg8" + inkscape:version="0.92.3 (2405546, 2018-03-11)" + sodipodi:docname="sysid1.svg"> + id="defs2"> - - - - - - - - - - - - + inkscape:stockid="EmptyTriangleOutL"> + inkscape:stockid="EmptyTriangleInL"> - - - - - - - - - - - - - - - - - - - - - - - - + inkscape:collect="always"> - - - - - - - - - + id="path996-6" + d="M 5.77,0 -2.88,5 V -5 Z" + style="fill:#ffffff;fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;stroke-opacity:1" + transform="matrix(-0.8,0,0,-0.8,4.8,0)" /> + id="path1005-7" + d="M 5.77,0 -2.88,5 V -5 Z" + style="fill:#ffffff;fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;stroke-opacity:1" + transform="matrix(0.8,0,0,0.8,-4.8,0)" /> - - - - - - - - - + inkscape:stockid="EmptyTriangleOutL"> + transform="matrix(0.8,0,0,0.8,-4.8,0)" + style="fill:#ffffff;fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;stroke-opacity:1" + d="M 5.77,0 -2.88,5 V -5 Z" + id="path5100-4" /> - - - - - - - - - + inkscape:stockid="EmptyTriangleInL"> + transform="matrix(-0.8,0,0,-0.8,4.8,0)" + style="fill:#ffffff;fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;stroke-opacity:1" + d="M 5.77,0 -2.88,5 V -5 Z" + id="path5551-7" + inkscape:connector-curvature="0" /> + inkscape:isstock="true" + inkscape:collect="always"> + id="path5481-9" + d="M 5.77,0 -2.88,5 V -5 Z" + style="fill:#ffffff;fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;stroke-opacity:1" + transform="matrix(0.8,0,0,0.8,-4.8,0)" + inkscape:connector-curvature="0" /> - + + + + + + image/svg+xml + + + + + + + + Register Map + + + + + S_AXI + ROM1 + ROM2 + - - + id="path11045" + d="m 293.73134,53.121467 c -9.64471,0.485613 -12.27445,6.973262 -13.03816,15.428815 -1.32366,14.654957 2.95802,35.221298 -13.96183,40.696188" + style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - image/svg+xml - - - - - - - - - - DMA - DAC - - - - - din_data_0 [N:1] - din_enable_0 - din_valid_0 - - - - - din_data_1 [N:1] - din_enable_1 - din_valid_1 - - - - din_data_7 [N:1] - din_enable_7 - din_valid_7 - - - - din_unf - DMA_RESET - DMA_CLK - - - - - - - dout_data_0 [M:1] - dout_enable_0 - dout_valid_0 - - dout_unf - DAC_RESET - DAC_CLK - - - - + id="path11045-6" + d="m 293.73134,165.37148 c -9.64471,-0.48561 -12.27445,-6.97326 -13.03816,-15.42882 -1.32366,-14.65496 2.95802,-35.2213 -13.96183,-40.69619" + style="fill:none;stroke:#000000;stroke-width:1px;stroke-linecap:butt;stroke-linejoin:miter;stroke-opacity:1" /> + - dout_data_1 [M:1] - (SYS ROM)dout_enable_1 + x="420.72916" + y="69.219727" + style="stroke-width:1.48832011" + id="tspan823-5-6" /> dout_valid_1 - - - - (PR ROM)dout_data_7 [M:1] - dout_enable_7 - dout_valid_7 - - - + x="420.72916" + y="132.49216" + style="stroke-width:1.48832011" + id="tspan823-5-6-9" /> - - ASYNC_MEM - Data stream controller - WR_ADDR - DATA_VALID - - RD_ADDR - CLK_DAC - CLK_DMA - - - CLK_DMA - CLK_DAC - valid_[n] - - Clock Domain Crossing - CLK_DMA - CLK_DAC - - - - - - - - - - - - - - dout_enable [7:0] - dout_valid [7:0] - din_enable_n - din_valid_n - RFIFO - - - - 8x[N:1] - - - - 8x[M:1] - - dout_valid_0 - - - dout_valid [7:0] - - - - - - - WR_ADDR - RD_ADDR + style="fill:none;fill-opacity:1;stroke:#000000;stroke-width:1.37463558;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" + id="rect841-6" + width="96.523468" + height="46.561604" + x="388.60941" + y="76.968307" /> diff --git a/_images/block_diagram22.svg b/_images/block_diagram22.svg new file mode 100644 index 0000000000..dc10b53b31 --- /dev/null +++ b/_images/block_diagram22.svg @@ -0,0 +1,532 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + OFFLOAD FSM + + + + AXI REGISTERMAP + BYPASS + + S_AXIS + + AXI_MM + SOURCE + M_AXIS + + DESTINATION + + + M_STORAGE_AXIS + S_STORAGE_AXIS + + Storage Unit + + diff --git a/_images/block_diagram23.svg b/_images/block_diagram23.svg new file mode 100644 index 0000000000..a130c28fe4 --- /dev/null +++ b/_images/block_diagram23.svg @@ -0,0 +1,4 @@ + + + +
MII/GMII
MII/GMII
RMII
RMII
mac_txd[3:0]
mac_txd[...
mac_tx_en
mac_tx_en
mac_tx_er
mac_tx_er
mii_col
mii_col
mii_crs
mii_crs
mii_rxd[3:0]
mii_rxd[...
mii_rx_clk
mii_rx_c...
mii_rx_dv
mii_rx_dv
mii_rx_er
mii_rx_er
mii_tx_clk
mii_tx_c...
util_mii_to_rmii
util_mii_t...
rmii_txd[1:0]
rmii_txd...
rmii_tx_en
rmii_tx_...
phy_crs_dv
phy_crs_...
phy_rxd[1:0]
phy_rxd[...
phy_rx_er
phy_rx_er
ref_clk
ref_clk
reset_n
reset_n
Zynq-7000/Zynq Ultrascale+ MPSoC - PS Gigabit Ethernet MAC
Zynq-7000/Zynq Ultra...
RMII ADIN1300 PHY
RMII ADIN1...
FPGA
FPGAText is not SVG - cannot display \ No newline at end of file diff --git a/_images/block_diagram24.svg b/_images/block_diagram24.svg new file mode 100644 index 0000000000..f280e32f22 --- /dev/null +++ b/_images/block_diagram24.svg @@ -0,0 +1,1910 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + DMA + DAC + + + + + din_data_0 [N:1] + din_enable_0 + din_valid_0 + + + + + din_data_1 [N:1] + din_enable_1 + din_valid_1 + + + + din_data_7 [N:1] + din_enable_7 + din_valid_7 + + + + din_unf + DMA_RESET + DMA_CLK + + + + + + + dout_data_0 [M:1] + dout_enable_0 + dout_valid_0 + + dout_unf + DAC_RESET + DAC_CLK + + + + + + + dout_data_1 [M:1] + dout_enable_1 + dout_valid_1 + + + + dout_data_7 [M:1] + dout_enable_7 + dout_valid_7 + + + + + + ASYNC_MEM + Data stream controller + WR_ADDR + DATA_VALID + + RD_ADDR + CLK_DAC + CLK_DMA + + + CLK_DMA + CLK_DAC + valid_[n] + + Clock Domain Crossing + CLK_DMA + CLK_DAC + + + + + + + + + + + + + + dout_enable [7:0] + dout_valid [7:0] + din_enable_n + din_valid_n + RFIFO + + + + 8x[N:1] + + + + 8x[M:1] + + dout_valid_0 + + + dout_valid [7:0] + + + + + + + WR_ADDR + RD_ADDR + + diff --git a/_images/block_diagram3.svg b/_images/block_diagram3.svg index b1f995fda0..d4688c36fa 100644 --- a/_images/block_diagram3.svg +++ b/_images/block_diagram3.svg @@ -1,4 +1,4 @@ -
DMA_FIFO
DMA_FIFO
ADC
DATA
PROCESSING
ADC...
REGISTER
MAP
REGISTER...
AD777x
INTERFACE
AD777x...
AXI SLAVE
AXI SLAVE
ADC INTERFACE
ADC INTERFACEText is not SVG - cannot display \ No newline at end of file +
DMA_FIFO
DMA_FIFO
ADC
DATA
PROCESSING
ADC...
REGISTER
MAP
REGISTER...
AD7768
INTERFACE
AD7768...
AXI SLAVE
AXI SLAVE
ADC INTERFACE
ADC INTERFACEText is not SVG - cannot display \ No newline at end of file diff --git a/_images/block_diagram4.svg b/_images/block_diagram4.svg index 7d9659bc5a..b1f995fda0 100644 --- a/_images/block_diagram4.svg +++ b/_images/block_diagram4.svg @@ -1,289 +1,4 @@ - - - - - - - - - - - - - - - - image/svg+xml - - - - - - - - - - - - AXI SLAVE - - REGISTERMAP - - - LVDS INTERFACE - - - - - ADC DATAPROCESSING - - - LVDS - - DMA FIFO - - + + + +
DMA_FIFO
DMA_FIFO
ADC
DATA
PROCESSING
ADC...
REGISTER
MAP
REGISTER...
AD777x
INTERFACE
AD777x...
AXI SLAVE
AXI SLAVE
ADC INTERFACE
ADC INTERFACEText is not SVG - cannot display \ No newline at end of file diff --git a/_images/block_diagram6.svg b/_images/block_diagram6.svg index 081ca4a14c..1db67d3b2c 100644 --- a/_images/block_diagram6.svg +++ b/_images/block_diagram6.svg @@ -2,6 +2,7 @@ + sodipodi:docname="axi_ad9361.svg"> - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + inkscape:window-width="1920" + inkscape:window-height="1005" + inkscape:window-x="1911" + inkscape:window-y="-9" + inkscape:window-maximized="1"> + id="grid4147" /> @@ -97,224 +864,910 @@ inkscape:label="Layer 1" inkscape:groupmode="layer" id="layer1" - transform="translate(-13.131983,-537.92376)"> + transform="translate(0,-552.36202)"> + + + + + - - - + x="338.00705" + y="1002.5098" + id="tspan10800" + style="font-size:17.5px;text-align:center;text-anchor:middle">Register Map + + AD9361 INTERFACE LVDS/CMOS + sodipodi:nodetypes="cc" /> + CLK_OUT + + FRAME_OUT + + DATA_OUT + + CLK_IN + + FRAME_IN + AXI SLAVE + id="tspan4464-6" + x="601.59485" + y="914.18268" + style="font-size:15.00000095px">DATA_IN + style="fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:2;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" + id="rect4554-2" + width="275.68262" + height="200.67418" + x="241.4856" + y="782.63196" /> + + + + REGISTERRX CHANNEL + + + + + + + + + + + + + + MAP + id="tspan5432-7" + x="328.60651" + y="907.61011" + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:12.5px;font-family:Arial;-inkscape-font-specification:'Arial Bold';text-align:center;text-anchor:middle;stroke-width:1;stroke-miterlimit:4;stroke-dasharray:none">IQ Corr + + + style="shape-rendering:crispEdges" + id="g4581-2" + transform="translate(72.146239,261.17086)"> + transform="matrix(0,-1.1885989,1.1885989,0,-59.978473,-122.17314)" + y="367.16461" + x="-667.7301" + height="37.394592" + width="36.778587" + id="rect11202-0" + style="display:inline;opacity:1;fill:none;fill-opacity:1;fill-rule:nonzero;stroke:#a01414;stroke-width:0.84132671;stroke-linecap:round;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" /> JESD LINK TO DMADATA ORDERING + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:12.5px;font-family:Arial;-inkscape-font-specification:'Arial Bold';text-align:center;text-anchor:middle" + y="646.26959" + x="398.66266" + id="tspan11368-8" + sodipodi:role="line">PNMON - DC Filter + + + + + + + + RX CORE + + + + + + + + IQC + + + + + + + PRBS + + id="tspan11628" + x="270.89429" + y="692.98926" + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:12.5px;font-family:Arial;-inkscape-font-specification:'Arial Bold';stroke-width:1;stroke-miterlimit:4;stroke-dasharray:none">PATTERN + DDS + DMA + + + + TX CHANNEL + + + + + TX CORE + id="g7938" + transform="translate(-16.000001,194)"> + y="552.77344" + x="126.2047" + height="72.407516" + width="113.65318" + id="rect4554-2-5-6" + style="fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:2;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /> ADC DATAPROCESSING&PRBS MONITORING + style="font-size:17.5px;text-align:center;text-anchor:middle" + y="584.26892" + x="182.5314" + id="tspan7449" + sodipodi:role="line">TDDCONTROL + + + + + + + + + + + + + + + + + + + + JESD FIFO - + id="tspan7846" + x="96.700409" + y="614.9624">DAC_FIFO_I0 DMA FIFO + id="tspan7846-3" + x="93.961151" + y="653.88196">DAC_FIFO_Q0 + DAC_FIFO_I1 + DAC_FIFO_Q1 + ADC_FIFO_I0 + ADC_FIFO_Q0 + ADC_FIFO_I1 + ADC_FIFO_Q1 + + + + S_AXI_MM + + + + + + diff --git a/_images/block_diagram7.svg b/_images/block_diagram7.svg index 0234fc9798..7d9659bc5a 100644 --- a/_images/block_diagram7.svg +++ b/_images/block_diagram7.svg @@ -2,900 +2,45 @@ + inkscape:version="0.91 r13725" + sodipodi:docname="adc_lvds.svg" + inkscape:export-filename="D:\Git\ghdl\docs\block_diagrams\axi_ad9265\axi_ad9265.png" + inkscape:export-xdpi="400" + inkscape:export-ydpi="400"> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + id="grid5420" + originx="-13.131982" + originy="-164.43837" /> @@ -936,6 +88,7 @@ image/svg+xml + @@ -943,477 +96,194 @@ inkscape:label="Layer 1" inkscape:groupmode="layer" id="layer1" - transform="translate(-18.205785,-566.84345)"> - + transform="translate(-13.131983,-537.92376)">   -   -   -   - - Register Map - - AD9783 LVDS INTERFACE - - CLK_IN_P + id="tspan4216" + x="108.82646" + y="336.35623" + style="font-size:20px" /> + + + + sodipodi:nodetypes="ccccccccc" /> CLK_IN_N + id="tspan4198" + x="35.742157" + y="647.38458" + style="font-size:10px">AXI SLAVE - - - - - - PRBS + style="opacity:1;fill:#d7d7d7;fill-opacity:0.35294118;fill-rule:nonzero;stroke:#000000;stroke-width:2.5;stroke-linecap:round;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" + id="rect4204" + width="72.5" + height="122.5" + x="139.0587" + y="591.32355" /> DDS - REGISTERDMA - - - TX CHANNEL - - - TX CORE - + x="174.79601" + y="662.5296" + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-family:sans-serif;-inkscape-font-specification:'sans-serif Bold';text-align:center;text-anchor:middle" + id="tspan4251">MAP - - + id="g4357" + transform="translate(-13.89132,-73.70117)"> + + LVDS INTERFACE - 64b - - - - 64b - DAC_DMA_I - DAC_DMA_Q -   + id="tspan4297" + x="274.52353" + y="600.3385" /> - + id="g4362" + transform="translate(-72.906712,199.45373)"> + + ADC DATAPROCESSING - S_AXI_MM - - AXI_AD9783 + sodipodi:nodetypes="ccccccccc" /> CLK_OUT_P + id="tspan4198-0" + x="42.579056" + y="784.05139" + style="font-size:10px">LVDS - CLK_OUT_N - - - - 16b - - - - 16b - DAC_OUT_P + sodipodi:nodetypes="ccccccccc" /> DAC_OUT_N + id="tspan4198-8" + x="353.8385" + y="701.73163" + style="font-size:10px">DMA FIFO diff --git a/_images/block_diagram8.svg b/_images/block_diagram8.svg index e0f4dae75a..081ca4a14c 100644 --- a/_images/block_diagram8.svg +++ b/_images/block_diagram8.svg @@ -1,4 +1,320 @@ - - - -
DMA_FIFO
DMA_FIFO
ADC
DATA
PROCESSING
ADC...
REGISTER
MAP
REGISTER...
LVDS OR CMOS
INTERFACE
LVDS OR CMOS...
AXI SLAVE
AXI SLAVE
LVDS OR CMOS
LVDS OR CMOSText is not SVG - cannot display \ No newline at end of file + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + + AXI SLAVE + + REGISTERMAP + + + JESD LINK TO DMADATA ORDERING + + + + + ADC DATAPROCESSING&PRBS MONITORING + + + JESD FIFO + + DMA FIFO + + diff --git a/_images/block_diagram9.svg b/_images/block_diagram9.svg index 8b1ed331df..0234fc9798 100644 --- a/_images/block_diagram9.svg +++ b/_images/block_diagram9.svg @@ -2,21 +2,20 @@ + inkscape:version="1.1.1 (3bf5ae0d25, 2021-09-20)" + sodipodi:docname="axi_ad9783.svg" + xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape" + xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd" + xmlns="http://www.w3.org/2000/svg" + xmlns:svg="http://www.w3.org/2000/svg" + xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" + xmlns:cc="http://creativecommons.org/ns#" + xmlns:dc="http://purl.org/dc/elements/1.1/"> @@ -44,9 +43,9 @@ inkscape:stockid="TriangleOutM"> @@ -104,9 +103,9 @@ inkscape:stockid="TriangleOutM"> + transform="scale(0.4)" /> + transform="scale(0.4)" /> + inkscape:swatch="solid"> + transform="scale(0.4)" /> @@ -233,9 +232,9 @@ + transform="scale(-0.4)" /> @@ -263,9 +262,9 @@ + transform="scale(-0.4)" /> + transform="scale(-0.4)" /> + transform="scale(-0.4)" /> @@ -323,9 +322,9 @@ + transform="scale(-0.4)" /> + transform="scale(-0.4)" /> @@ -368,9 +367,9 @@ + transform="scale(-0.4)" /> + transform="scale(-0.4)" /> + transform="scale(-0.4)" /> @@ -426,9 +425,9 @@ orient="auto" inkscape:stockid="TriangleInM"> @@ -442,9 +441,9 @@ inkscape:isstock="true"> + transform="scale(-0.4)" /> + transform="scale(-0.4)" /> @@ -503,9 +502,9 @@ + transform="scale(-0.4)" /> + transform="scale(-0.4)" /> @@ -548,9 +547,9 @@ + transform="scale(-0.4)" /> + transform="scale(-0.4)" /> + transform="scale(-0.4)" /> + transform="scale(-0.4)" /> + transform="scale(0.4)" /> @@ -786,9 +785,9 @@ orient="auto" inkscape:stockid="TriangleInM"> @@ -803,9 +802,99 @@ + + + + + + + + + + d="M 5.77,0 -2.88,5 V -5 Z" + id="path18753-0-0" /> + + + + + + + + + + inkscape:window-height="1018" + inkscape:window-x="-6" + inkscape:window-y="-6" + inkscape:window-maximized="1" + inkscape:pagecheckerboard="0" + fit-margin-top="0" + fit-margin-left="0" + fit-margin-right="0" + fit-margin-bottom="0"> + id="grid4147" + originx="-18.205785" + originy="-14.481434" /> @@ -840,7 +936,6 @@ image/svg+xml - @@ -848,515 +943,477 @@ inkscape:label="Layer 1" inkscape:groupmode="layer" id="layer1" - transform="translate(0,-752.36203)"> + transform="translate(-18.205785,-566.84345)"> + width="493.2551" + height="280.08105" + x="18.97311" + y="567.61078" /> + x="103.08754" + y="822.79993" + style="font-size:12.5px;line-height:1.25">  + x="190.86754" + y="640.01111" + style="font-size:25.0847px;line-height:1.25">  + x="441.96735" + y="761.41437" + style="font-size:40px;line-height:1.25">    + + Register Map + + AD9783 LVDS INTERFACE + + CLK_IN_P + + CLK_IN_N + + + + + + + PRBS + DDS + DMA + + + TX CHANNEL + + + TX CORE + - - - - CHANNEL_A + transform="matrix(-1,0,0,1,370.43196,155.55804)" + style="display:inline;fill:#c8c8c8;fill-opacity:1;stroke:#c8c8c8;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" + id="g5812-8" /> + + + 64b + + + + 64b + DAC_DMA_I + DAC_DMA_Q - - ProgrammableCIC - Decimation by5/50/500/5000/50000 - - - - ProgrammableCIC - Decimation by5/50/500/5000/50000 - + id="flowPara8024" + style="font-size:15px;line-height:1.25">  - - CompensationFIR - Decimation by2 - - - - Arbitrary Decimation + transform="matrix(-1.0000001,0,0,1.0000001,267.16957,272.87019)" + style="display:inline;fill:#c8c8c8;fill-opacity:1;stroke:none;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" + id="g5327"> + - - - CompensationFIR - Decimation by2 - - - - Arbitrary Decimation - - - - - - CHANNEL_B - - - - - - CHANNEL_A - - - - - - CHANNEL_B - - - + id="tspan8079" + x="49.316456" + y="823.90955" + style="font-size:15px;line-height:1.25">S_AXI_MM + + AXI_AD9783 + + CLK_OUT_P + + CLK_OUT_N - - ScaleCompensation - + transform="matrix(-0.53393616,0,0,1.0124586,574.76564,201.18615)" + style="display:inline;fill:#c8c8c8;fill-opacity:1;stroke:#c8c8c8;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" + id="g5812-8-3-6"> + + 16b - - ScaleCompensation - + transform="matrix(-0.53392514,0,0,1.0125305,574.76309,161.93301)" + style="display:inline;fill:#c8c8c8;fill-opacity:1;stroke:#c8c8c8;stroke-width:0.999639;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" + id="g5812-8-3-8-2"> + + 16b + DAC_OUT_P + DAC_OUT_N diff --git a/genindex.html b/genindex.html index d465444521..fe59c48f33 100644 --- a/genindex.html +++ b/genindex.html @@ -153,12 +153,15 @@
  • IP Cores
    • AXI AD3552R
    • AXI AD7606x
      • +
    • AXI AD7616
    • AXI AD7768
    • AXI AD777x
    • AXI AD9265
      • +
    • AXI AD9361
    • AXI AD9467
    • AXI AD9671
    • AXI AD9783
      • +
    • AXI AD9963
    • AXI ADAQ8092
    • AXI ADC Decimate
    • AXI ADC Trigger
      • diff --git a/index.html b/index.html index 088240bf5b..65c395f102 100644 --- a/index.html +++ b/index.html @@ -159,12 +159,15 @@
    • IP Cores
      • AXI AD3552R
      • AXI AD7606x
        • +
      • AXI AD7616
      • AXI AD7768
      • AXI AD777x
      • AXI AD9265
        • +
      • AXI AD9361
      • AXI AD9467
      • AXI AD9671
      • AXI AD9783
        • +
      • AXI AD9963
      • AXI ADAQ8092
      • AXI ADC Decimate
      • AXI ADC Trigger
        • diff --git a/library/axi_ad3552r/index.html b/library/axi_ad3552r/index.html index bc46c708d1..4e56e03d0a 100644 --- a/library/axi_ad3552r/index.html +++ b/library/axi_ad3552r/index.html @@ -173,12 +173,15 @@
      • IP Cores
        • AXI AD3552R
        • AXI AD7606x
          • +
        • AXI AD7616
        • AXI AD7768
        • AXI AD777x
        • AXI AD9265
          • +
        • AXI AD9361
        • AXI AD9467
        • AXI AD9671
        • AXI AD9783
          • +
        • AXI AD9963
        • AXI ADAQ8092
        • AXI ADC Decimate
        • AXI ADC Trigger
          • diff --git a/library/axi_ad7606x/index.html b/library/axi_ad7606x/index.html index 51ee43c746..31965b12da 100644 --- a/library/axi_ad7606x/index.html +++ b/library/axi_ad7606x/index.html @@ -18,7 +18,7 @@ - + @@ -180,12 +180,15 @@
        • IP Cores
          • AXI AD3552R
          • AXI AD7606x
            • +
          • AXI AD7616
          • AXI AD7768
          • AXI AD777x
          • AXI AD9265
            • +
          • AXI AD9361
          • AXI AD9467
          • AXI AD9671
          • AXI AD9783
            • +
          • AXI AD9963
          • AXI ADAQ8092
          • AXI ADC Decimate
          • AXI ADC Trigger
            • @@ -2189,7 +2192,248 @@

            Register Map +
            +
            +
            +
            + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

            DWORD

            BYTE

            Reg Name

            Description

            BITS

            Field Name

            Type

            Default Value

            Description

            0x00x0REG_VERSION
            +

            Version and Scratch Registers

            +
            +

            		[31:0]VERSION[31:0]RO0x00020101
            +

            Version number. Unique to all cores.

            +
            +
            0x10x4REG_ID
            +

            Core ID

            +
            +

            		[31:0]ID[31:0]RO0x00000000
            +

            Instance identifier number.

            +
            +
            0x20x8REG_SCRATCH
            +

            Version and Scratch Registers

            +
            +

            		[31:0]SCRATCH[31:0]RW0x00000000
            +

            Scratch register.

            +
            +
            0x30xcREG_CORE_MAGIC
            +

            Identification number

            +
            +

            		[31:0]CORE_MAGIC[31:0]RW0x504c5347
            +

            Identification number.

            +
            +
            0x40x10REG_RSTN
            +

            Reset and load values

            +
            +

            		[1:1]LOAD_CONFIGWO0x0
            +

            Loads the new values written in the config registers.

            +
            +

            		[0:0]RESETRW0x0
            +

            Reset, default is (0x0).

            +
            +
            0x60x18REG_CONFIG
            +

            Features enable register

            +
            +

            		[2:2]EXT_SYNC_ALIGNRW0x0
            +

            If active the ext_sync will trigger a phase align at each neg-edge. Otherwise the phase align will be armed by a load config toggle.

            +
            +

            		[1:1]FORCE_ALIGNRW0x0
            +

            If active the current active pulses are immediately stopped and realigned. Otherwise, the synchronized pulses will start only after all running pulse periods end.

            +
            +

            		[0:0]START_AT_SYNCRW0x1
            +

            If active, the pulses will start after the trigger event. Otherwise each pulse will start after a period equal to the one for which it is set. Default valew can be overwritten at build time through parameters.

            +
            +
            0x50x14REG_NB_PULSES
            +

            Number of pulses

            +
            +

            		[31:0]NB_PULSESRO0x00000000
            +

            Number of configurable pulses.

            +
            +
            0x100x40REG_PULSE_X_PERIOD
            +

            Pulse x period

            +
            +

            		[31:0]PULSE_X_PERIOD[31:0] - base + 'h4 for each channel -> e.g. CH3 period - 'h4CRW0x00000000
            +

            Pulse x duration, defined in number of clock cycles.

            +
            +
            0x200x80REG_PULSE_X_WIDTH
            +

            Pulse x width

            +
            +

            		[31:0]PULSE_X_WIDTH[31:0] - base + 'h4 for each channel -> e.g. CH3 width - 'h8CRW0x00000000
            +

            Pulse x width (high time), defined in number of clock cycles.

            +
            +
            0x300xc0REG_PULSE_X_OFFSET
            +

            Pulse x offset

            +
            +

            		[31:0]PULSE_X_OFFSET[31:0] - base + 'h4 for each channel -> e.g. CH3 offset - 'hCCRW0x00000000
            +

            Pulse x offset, defined in number of clock cycles.

            +
            +
            +
            +
            +
            +
            + +

            Theory of operation#

            The axi_ad7606x IP can be configured in various operation modes, this feature @@ -2437,7 +2681,7 @@

            References   - + diff --git a/library/axi_ad7616/index.html b/library/axi_ad7616/index.html new file mode 100644 index 0000000000..58392e6fdd --- /dev/null +++ b/library/axi_ad7616/index.html @@ -0,0 +1,854 @@ + + + + + + + + AXI AD7616 — HDL documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
            +
            + + + +
            +
            + + +
            +
            + +
            + +
            + + +
            + + Evaluation Boards + University Program + HDL + no-OS + Hardware Python Interfaces + Precision Converters Firmware + Doctools + Precision Toolbox + + +
            +
            +
            +
            +
            On this page
            + +
            + +
            +
            + + + + +
            +
            +
            +
            + +
            +

            AXI AD7616#

            +

            The AXI AD7616 IP core +can be used to interface the AD7616 device using an +FPGA. The core has a AXI Memory Map interface for configuration, supports the +parallel data interface of the device, and has a simple FIFO interface for the +DMAC.

            +
            +

            Files#

            +
            + + + + + + + + + + + + + + + + + +

            Name

            Description

            library/axi_ad7616/axi_ad7616.v

            Verilog source for the AXI AD7616.

            library/axi_ad7616/axi_ad7616_control.v

            Verilog source for the AXI AD7616 control.

            library/axi_ad7616/axi_ad7616_pif.v

            Verilog source for the AXI AD7616 parallel interface.

            +
            +
            +
            +

            Block Diagram#

            +AXI AD7616 block diagram
            +
            +

            Configuration Parameters#

            +
            +
            + + + + + + + + + + + + + + + +

            Name

            Description

            Default Value

            Choices/Range

            ID
            +

            Core ID should be unique for each IP in the system

            +
            +            		0

            +
            +
            +
            +
            +

            Interface#

            +
            +
            +
            +
            + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

            Physical Port

            Logical Port

            Direction

            Dependency

            s_axi_awaddrAWADDR

            in [15:0]

            s_axi_awprotAWPROT

            in [2:0]

            s_axi_awvalidAWVALID

            in

            s_axi_awreadyAWREADY

            out

            s_axi_wdataWDATA

            in [31:0]

            s_axi_wstrbWSTRB

            in [3:0]

            s_axi_wvalidWVALID

            in

            s_axi_wreadyWREADY

            out

            s_axi_brespBRESP

            out [1:0]

            s_axi_bvalidBVALID

            out

            s_axi_breadyBREADY

            in

            s_axi_araddrARADDR

            in [15:0]

            s_axi_arprotARPROT

            in [2:0]

            s_axi_arvalidARVALID

            in

            s_axi_arreadyARREADY

            out

            s_axi_rdataRDATA

            out [31:0]

            s_axi_rrespRRESP

            out [1:0]

            s_axi_rvalidRVALID

            out

            s_axi_rreadyRREADY

            in

            +
            +
            +
            +
            +
            +
            +
            +
            + + + + + + + + + + + + + + + +

            Physical Port

            Logical Port

            Direction

            Dependency

            s_axi_aclkCLK

            in

            +
            +
            +
            +
            +
            +
            +
            +
            + + + + + + + + + + + + + + + +

            Physical Port

            Logical Port

            Direction

            Dependency

            s_axi_aresetnRST

            in

            +
            +
            +
            +
            +
            +
            +
            +
            + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

            Physical Port

            Direction

            Dependency

            Description

            rx_cs_n

            out

            +

            Active low chip select

            +
            +
            rx_db_o

            out [15:0]

            +

            Parallel data out

            +
            +
            rx_db_i

            in [15:0]

            +

            Parallel data in

            +
            +
            rx_db_t

            out

            +

            Active high 3-state T pin for IOBUF

            +
            +
            rx_rd_n

            out

            +

            Active low parallel data read control

            +
            +
            rx_wr_n

            out

            +

            Active low parallel data write control

            +
            +
            rx_trigger

            in

            +

            End of conversion signal

            +
            +
            adc_valid

            out

            +

            Shows when a valid data is available on the bus

            +
            +
            adc_data

            out [15:0]

            +

            Data bus

            +
            +
            adc_sync

            out

            +

            Shows the first valid beat on a sequence

            +
            +
            +
            +
            +
            +
            +
            +
            +

            Register Map#

            +
            +
            +
            +
            +
            + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

            DWORD

            BYTE

            Reg Name

            Description

            BITS

            Field Name

            Type

            Default Value

            Description

            0x1000x400VERSION
            +

            Version and Scratch Registers.

            +
            +

            		[31:0]VERSIONRO0x00001002
            +

            Version number

            +
            +
            0x1010x404ID
            +

            Instance identifier number.

            +
            +

            		[31:0]IDRO0x00000000
            +

            Version number

            +
            +
            0x1020x408SCRATCH
            +

            Scratch register.

            +
            +

            		[31:0]SCRATCHRW0x00000000
            +

            Version number

            +
            +
            0x1100x440UP_CNTRL
            +

            ADC Interface Control & Status.

            +
            +

            		[1:1]CNVST_ENRW0x0
            +

            Enable the CNVST pulse generator of core.

            +
            +

            		[0:0]RESETNRW0x0
            +

            Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.

            +
            +
            0x1110x444UP_CONV_RATE
            +

            ADC Interface Control & Status.

            +
            +

            		[31:0]UP_CONV_RATERW0x00000000
            +

            Rate of the conversion pulse signal, it’s relative to the system clock (s_axis_clk).

            +
            +
            0x1120x448UP_BURST_LENGTH
            +

            ADC Interface Control & Status.

            +
            +

            		[4:0]UP_BURST_LENGTHRW0x00
            +

            Define the actual burst length. The value must be equal to burst length - 1 . This register is active just on PARALLEL mode.

            +
            +
            0x1130x44cUP_READ_DATA
            +

            ADC Interface Control & Status.

            +
            +

            		[31:0]UP_READ_DATARO0x00000000
            +

            This register can be used to read the device registers on PARALLEL software mode.

            +
            +
            0x1140x450UP_WRITE_DATA
            +

            ADC Interface Control & Status.

            +
            +

            		[31:0]UP_WRITE_DATAWO0x00000000
            +

            This register can be used to read the device registers on PARALLEL software mode.

            +
            +
            +
            +
            +
            +
            + + + + + + + + + + + + + + + + + + + + + +

            Access Type

            Name

            Description

            RO

            Read-only

            Reads will return the current register value. Writes have no effect.

            RW

            Read-write

            Reads will return the current register value. Writes will change the current register value.

            WO

            Write-only

            Writes will change the current register value. Reads have no effect.

            +
            +
            +
            +
            +
            + + + +
            +
            +   + + +
            + +
            +
            +
            + +
            + + + +
            + ©2024, Analog Devices, Inc. + + | + Made with Sphinx + & Doctools + +
            + + \ No newline at end of file diff --git a/library/axi_ad7768/index.html b/library/axi_ad7768/index.html index 6e01851969..c18ea82fd3 100644 --- a/library/axi_ad7768/index.html +++ b/library/axi_ad7768/index.html @@ -19,7 +19,7 @@ - + @@ -172,12 +172,15 @@
          • IP Cores

            • Block Diagram#

            -AXI AD7768 block diagram
            +AXI AD7768 block diagram

            Configuration Parameters#

            @@ -2224,7 +2227,7 @@

            References   - +

            diff --git a/library/axi_ad777x/index.html b/library/axi_ad777x/index.html index 3185f699ed..3b485f9e81 100644 --- a/library/axi_ad777x/index.html +++ b/library/axi_ad777x/index.html @@ -172,12 +172,15 @@
          • IP Cores

            • Block Diagram#

            -AXI AD777x block diagram
            +AXI AD777x block diagram

            Configuration Parameters#

            diff --git a/library/axi_ad9265/index.html b/library/axi_ad9265/index.html index 7ab8ebca01..642ce22d18 100644 --- a/library/axi_ad9265/index.html +++ b/library/axi_ad9265/index.html @@ -18,7 +18,7 @@ - + @@ -172,12 +172,15 @@
          • IP Cores

            • Block Diagram#

            -AXI AD9265 block diagram
            +AXI AD9265 block diagram

            Configuration Parameters#

            @@ -2313,7 +2316,7 @@

            References   - +

            diff --git a/library/axi_ad9361/index.html b/library/axi_ad9361/index.html new file mode 100644 index 0000000000..99fb444247 --- /dev/null +++ b/library/axi_ad9361/index.html @@ -0,0 +1,4626 @@ + + + + + + + + AXI AD9361 — HDL documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
            +
            + + + +
            +
            + + +
            +
            + +
            + +
            + + +
            + + Evaluation Boards + University Program + HDL + no-OS + Hardware Python Interfaces + Precision Converters Firmware + Doctools + Precision Toolbox + + +
            +
            +
            +
            +
            On this page
            + +
            + +
            +
            + + + + +
            +
            +
            +
            + +
            +

            AXI AD9361#

            +

            The AXI AD9361 IP core +can be used to interface the AD9361 device. +This documentation only covers the IP core and requires that one must be +familiar with the device for a complete and better understanding.

            +

            More about the generic framework interfacing ADCs can be read in Generic AXI ADC, +and interfacing DACs in Generic AXI DAC.

            +
            +

            Features#

            +
              +

            • AXI Lite control/status interface

              • +

            • PRBS monitoring

              • +

            • Hardware and software DC filtering

              • +

            • IQ correction

              • +

            • Internal DDS

              • +

            • Programmable line delays

              • +

            • Receive and transmit loop back

              • +

            • Supports both Altera and AMD Xilinx devices

              • +
            +
            +
            +

            Files#

            +
            + + + + + + + + + + + + + + + + + + + + + + + +

            Name

            Description

            library/axi_ad9361/axi_ad9361.v

            Verilog source for the AXI AD9361.

            library/common/up_adc_common.v

            Verilog source for the ADC Common regmap.

            library/common/up_adc_channel.v

            Verilog source for the ADC Channel regmap.

            library/common/up_dac_common.v

            Verilog source for the DAC Common regmap.

            library/common/up_dac_channel.v

            Verilog source for the DAC Channel regmap.

            +
            +
            +
            +

            Block Diagram#

            +AXI AD9361 block diagram
            +
            +

            Functional Description#

            +

            The axi_ad9361 cores architecture contains:

            + +
            +

            Device (AD9361) Interface Description#

            +

            The IP supports both LVDS and CMOS Dual Port Full Duplex interfaces +(configurable, see parameters section). It avoids all the programmable flavors +of the device interface mess. The interface is in fact quite simple, in LVDS +mode samples require two active clock edges and in CMOS mode a single edge. The +samples are then delineated in-order using the FRAME signal. This is applicable +to both DDR and SDR modes. There is a limitation though, the IP core does NOT +support swapping of the data ports in CMOS mode. This option is left as a +constraint. As an example the PZSDR projects uses SWAP on some boards based on +the board layout.

            +

            Let’s consider the 2R2T configuration, each frame consists of 4 samples in each +direction. In LVDS-DDR mode that is 8 clock edges (4 full clock cycles) +identified by a frame pattern of 8’b11110000. The IP interface logic simply +collects data on consecutive 8 edges and deframes using the FRAME signal and +outputs the samples. The device does the same in the transmit direction. In CMOS +mode, the same is done over 4 clock edges.

            +

            The interface also provides a single clock tree for the entire core. This clock +uses a global buffer that has the minimum skew all across the die. On Altera +devices, this is done via the PLL and because the LVDS cores do NOT support a +serialization factor of 2, runs at half the interface clock frequency. +On AMD Xilinx devices, this is done via the BUFG and the core and interface runs +at the same clock frequency.

            +
            +

            Altera#

            +

            The core is tested to work only on Cyclone V Arrow SOC Kit. Since Altera does +half-thought board designs that do not favor FMC bank allocations, we are +incapable of validating the core on other devices.

            +
            +
            +

            AMD Xilinx#

            +
            +
            Alternative Clocking Methods#
            +
              +

            1. Using MMCM 2. Using BUFIO/BUFR

              2. +
            +
            +
            +
            Alternative Use Models#
            +

            1. Interface Logic Only 2. Disable DSP Functions 3. Removing AXI interface and +Processor Control

            +
            +
            +
            +
            +

            Internal Interface Description#

            +

            The main purpose of all (including this) ADI IP cores is to provide a common, +well-defined internal interface within the FPGA. This interface consists of the +following signals per channel.

            +
            +

            ENABLE#

            +

            The enable signal is strictly for software use and is controlled by the +corresponding register bit. The core simply reflects the programmed bit as an +output port. In ADI reference projects, this bit is used to activate the channel +of interest. It is then used by the PACK/UNPACK cores to route the data based on +total number of channels and the selected number of channels. As an example, +AXI_AD9361 supports a total of 4 channels 16bits each. This corresponds to a +packed channel data width of 64bits. If software enables only two channels the +packed 64bits of data is exclusively shared by the enabled 2 channels (each +channel gets 32 bits of data).

            +
            +
            +

            VALID#

            +

            The valid signal is sourced by the core to indicate a valid sample on the DATA +port. In the receive (ADC) direction this indicates a valid sample and in the +transmit (DAC) direction this indicates the current sample is being read by the +core. The valid is simply a ‘reflective’ of the ‘sampling rate’. Note that he +cores always run at the interface clock. This is to avoid any customized clock +handling or transfer within this core. However in many cases interface clock may +not be the sampling clock. As an example for AD9361 the interface clock is +244Mhz for a sampling clock of 61MHz. That is each channel’s sampling rate is +61MHz. This translates into the VALID signal being asserted once every 4 clocks. +In cores where sampling rate is same as the interface clock, VALID is always +asserted and may be safely ignored.

            +

            A common interpretation of this is that all channels has the same VALID +behavior. This is NOT necessarily true. A majority of use cases may have this as +a result of data path equivalency. However, if software decides to +enable/disable functions differently among channels, the VALID signals of those +channels will NOT be the same.

            +
            +
            +

            DATA#

            +

            The DATA is the raw Analog samples. It follows two simple rules.

            +
              +

            1. The samples are always 16bits, regardless of the ADC/DAC data width. That is +the source or destination is intended to handle samples as 16bits. In the +transmit direction, if the DAC data width is less than 16bits, the most +significant bits are used. In the receive direction, if the ADC data width is +less than 16bits, the most significant bits are sign extended. This allows +the same source or destination portable across different ADC/DAC data widths. +In other words, if the source is generating a 16bits tone the signal appears +the same across a 12bit, 14bit or 16bit DAC with only the corresponding +amplitude change. The source can thus be independent of the number of bits +supported by DAC. In the receive direction, the samples are sign extended. +Thus the destination always receives a 16bit sample with different amplitude +levels corresponding to the number of bits supported by the ADC. This may +seem to break the symmetry rule, but in most DSP functions the samples are +rounded up towards the MSB as only precision is allowed to lost or gained at +the expense of the LSB bits. The MSB bits retains all the physical nature of +the signal.

              2. +

            2. The DATA is received and transmitted with most significant sample “newest” +regardless of the channel width. In other words the most significant sample +is the “newest” sample. If the total channel width is 64bits, it carries 4 +samples (16bits) per clock. If we were to name these samples as S3 (bits 63 +down to 48), S2 (bits 47 down to 32), S1 (bits 31 down to 16) and S0 (bits 15 +down to 0), the following is true. In the transmit direction, S0 is sent +first and S3 is sent last to the DAC. The analog samples are S0, S1, S2 and +S3 across time with S0 being the oldest and S3 being the newest sample. In +the receive direction, S0 carries the oldest sample received and S3 carries +the newest sample from the ADC.

              3. +
            +
            +
            +
            +
            +

            Configuration Parameters#

            +
            +
            + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

            Name

            Description

            Default Value

            Choices/Range

            ID
            +

            Core ID should be unique for each IP in the system

            +
            +            		0

            MODE_1R1T
            +

            Used to select between 2RX2TX (0) and 1RX1TX (1) mode.

            +
            +            		0

            FPGA_TECHNOLOGY
            +

            Used to select between devices

            +
            +            		0

            Unknown (0), 7series (1), ultrascale (2), ultrascale+ (3), versal (4)

            FPGA_FAMILY

            Fpga Family.

            		0

            Unknown (0), artix (1), kintex (2), virtex (3), zynq (4), versalprime (5), versalaicore (6), versalpremium (7)

            SPEED_GRADE

            Speed Grade.

            		0

            Unknown (0), -1 (10), -1L (11), -1H (12), -1HV (13), -1LV (14), -2 (20), -2L (21), -2LV (22), -2MP (23), -2LVC (24), -2LVI (25), -3 (30)

            DEV_PACKAGE

            Dev Package.

            		0

            Unknown (0), rf (1), fl (2), ff (3), fb (4), hc (5), fh (6), cs (7), cp (8), ft (9), fg (10), sb (11), rb (12), rs (13), cl (14), sf (15), ba (16), fa (17), fs (18), fi (19), vs (20), ls (21)

            TDD_DISABLE
            +

            Setting this parameter the TDD control will not be implemented in the core.

            +
            +            		0

            PPS_RECEIVER_ENABLE

            Pps Receiver Enable.

            		0

            CMOS_OR_LVDS_N
            +

            Defines the physical interface type, set 1 for CMOS and 0 for LVDS

            +
            +            		0

            ADC_INIT_DELAY

            Adc Init Delay.

            		0

            ADC_DATAPATH_DISABLE
            +

            If set, the data path processing logic is not generated in the RX path, and the raw data is pushed directly to the DMA interface.

            +
            +            		0

            ADC_USERPORTS_DISABLE
            +

            Disable the User Control ports in receive path.

            +
            +            		0

            ADC_DATAFORMAT_DISABLE
            +

            Disable the Data Format control module.

            +
            +            		0

            ADC_DCFILTER_DISABLE
            +

            Disable the DC Filter module.

            +
            +            		0

            ADC_IQCORRECTION_DISABLE
            +

            Disable the IQ Correction module in receive path.

            +
            +            		0

            DAC_INIT_DELAY

            Dac Init Delay.

            		0

            DAC_CLK_EDGE_SEL

            Dac Clk Edge Sel.

            		0

            DAC_IODELAY_ENABLE
            +

            Set IO_DELAY control in transmit path.

            +
            +            		0

            DAC_DATAPATH_DISABLE
            +

            If set, the data path processing logic is not generated in the TX path, and the raw data is pushed directly to the physical interface.

            +
            +            		0

            DAC_DDS_DISABLE
            +

            Disable the DDS modules in transmit path.

            +
            +            		0

            DAC_DDS_TYPE

            Dac Dds Type.

            		1

            DAC_DDS_PHASE_DW

            Dac Dds Phase Dw.

            		16

            DAC_DDS_CORDIC_DW

            Dac Dds Cordic Dw.

            		14

            DAC_DDS_CORDIC_PHASE_DW

            Dac Dds Cordic Phase Dw.

            		13

            DAC_USERPORTS_DISABLE
            +

            Disable the User Control ports in transmit path.

            +
            +            		0

            DAC_IQCORRECTION_DISABLE
            +

            Disable the IQ Correction module in transmit path.

            +
            +            		0

            IO_DELAY_GROUP
            +

            The delay group name which is set for the delay controller

            +
            +            		dev_if_delay_group

            IODELAY_CTRL

            Iodelay Ctrl.

            		1

            MIMO_ENABLE

            Mimo Enable.

            		0

            USE_SSI_CLK

            Use Ssi Clk.

            		1

            DELAY_REFCLK_FREQUENCY

            Delay Refclk Frequency.

            		200

            RX_NODPA

            Rx Nodpa.

            		0

            +
            +
            +
            +
            +

            Interface#

            +
            +
            +
            +
            + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

            Physical Port

            Logical Port

            Direction

            Dependency

            s_axi_awaddrAWADDR

            in [15:0]

            s_axi_awprotAWPROT

            in [2:0]

            s_axi_awvalidAWVALID

            in

            s_axi_awreadyAWREADY

            out

            s_axi_wdataWDATA

            in [31:0]

            s_axi_wstrbWSTRB

            in [3:0]

            s_axi_wvalidWVALID

            in

            s_axi_wreadyWREADY

            out

            s_axi_brespBRESP

            out [1:0]

            s_axi_bvalidBVALID

            out

            s_axi_breadyBREADY

            in

            s_axi_araddrARADDR

            in [15:0]

            s_axi_arprotARPROT

            in [2:0]

            s_axi_arvalidARVALID

            in

            s_axi_arreadyARREADY

            out

            s_axi_rdataRDATA

            out [31:0]

            s_axi_rrespRRESP

            out [1:0]

            s_axi_rvalidRVALID

            out

            s_axi_rreadyRREADY

            in

            +
            +
            +
            +
            +
            +
            +
            +
            + + + + + + + + + + + + + + + +

            Physical Port

            Logical Port

            Direction

            Dependency

            s_axi_aclkCLK

            in

            +
            +
            +
            +
            +
            +
            +
            +
            + + + + + + + + + + + + + + + +

            Physical Port

            Logical Port

            Direction

            Dependency

            s_axi_aresetnRST

            in

            +
            +
            +
            +
            +
            +
            +
            +
            + + + + + + + + + + + + + + + +

            Physical Port

            Logical Port

            Direction

            Dependency

            clkCLK

            in

            +
            +
            +
            +
            +
            +
            +
            +
            + + + + + + + + + + + + + + + +

            Physical Port

            Logical Port

            Direction

            Dependency

            l_clkCLK

            out

            +
            +
            +
            +
            +
            +
            +
            +
            + + + + + + + + + + + + + + + +

            Physical Port

            Logical Port

            Direction

            Dependency

            delay_clkCLK

            in

            +
            +
            +
            +
            +
            +
            +
            +
            + + + + + + + + + + + + + + + +

            Physical Port

            Logical Port

            Direction

            Dependency

            rstRST

            out

            +
            +
            +
            +
            +
            +
            +
            +
            + + + + + + + + + + + + + + + +

            Physical Port

            Logical Port

            Direction

            Dependency

            gps_pps_irqINTERRUPT

            out

            +
            +
            +
            +
            +
            +
            +
            +
            + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

            Physical Port

            Direction

            Dependency

            Description

            rx_clk_in_p

            in

            		CMOS_OR_LVDS_N == 0
            +

            LVDS input clock

            +
            +
            rx_clk_in_n

            in

            		CMOS_OR_LVDS_N == 0
            +

            LVDS input clock

            +
            +
            rx_frame_in_p

            in

            		CMOS_OR_LVDS_N == 0
            +

            LVDS input frame signal

            +
            +
            rx_frame_in_n

            in

            		CMOS_OR_LVDS_N == 0
            +

            LVDS input frame signal

            +
            +
            rx_data_in_p

            in [5:0]

            		CMOS_OR_LVDS_N == 0
            +

            LVDS input data lines

            +
            +
            rx_data_in_n

            in [5:0]

            		CMOS_OR_LVDS_N == 0
            +

            LVDS input data lines

            +
            +
            rx_clk_in

            in

            		CMOS_OR_LVDS_N == 1
            +

            CMOS input clock

            +
            +
            rx_frame_in

            in

            		CMOS_OR_LVDS_N == 1
            +

            CMOS input frame signal

            +
            +
            rx_data_in

            in [11:0]

            		CMOS_OR_LVDS_N == 1
            +

            CMOS input data lines

            +
            +
            tx_clk_out_p

            out

            		CMOS_OR_LVDS_N == 0
            +

            LVDS output clock

            +
            +
            tx_clk_out_n

            out

            		CMOS_OR_LVDS_N == 0
            +

            LVDS output clock

            +
            +
            tx_frame_out_p

            out

            		CMOS_OR_LVDS_N == 0
            +

            LVDS output frame signal

            +
            +
            tx_frame_out_n

            out

            		CMOS_OR_LVDS_N == 0
            +

            LVDS output frame signal

            +
            +
            tx_data_out_p

            out [5:0]

            		CMOS_OR_LVDS_N == 0
            +

            LVDS output data lines

            +
            +
            tx_data_out_n

            out [5:0]

            		CMOS_OR_LVDS_N == 0
            +

            LVDS output data lines

            +
            +
            tx_clk_out

            out

            		CMOS_OR_LVDS_N == 1
            +

            CMOS output clock

            +
            +
            tx_frame_out

            out

            		CMOS_OR_LVDS_N == 1
            +

            CMOS output frame signal

            +
            +
            tx_data_out

            out [11:0]

            		CMOS_OR_LVDS_N == 1
            +

            CMOS output data lines

            +
            +
            enable

            out

            +

            ENSM control signal, see User Guide for more information

            +
            +
            txnrx

            out

            +

            ENSM control signal, see User Guide for more information

            +
            +
            dac_sync_in

            in

            +

            Synchronization signal of the transmit path for slave devices (ID>0)

            +
            +
            dac_sync_out

            out

            +

            Synchronization signal of the transmit path for master device (ID==0)

            +
            +
            tdd_sync

            in

            +

            SYNC input for frame synchronization in TDD mode

            +
            +
            tdd_sync_cntr

            out

            +

            SYNC output for frame synchronization in TDD mode

            +
            +
            gps_pps

            in

            adc_dovf

            in

            +

            Data overflow, must be connected to the DMA

            +
            +
            adc_r1_mode

            out

            +

            If set, core is functioning in single channel mode (one I/Q pair)

            +
            +
            dac_dunf

            in

            +

            Data underflow, must be connected to the DMA

            +
            +
            dac_r1_mode

            out

            +

            If set, core is functioning in single channel mode (one I/Q pair)

            +
            +
            up_enable

            in

            +

            GPI control of the ENABLE line in TDD mode, when HDL TDD control is DISABLED

            +
            +
            up_txnrx

            in

            +

            GPI control of the TXNRX line in TDD mode, when HDL TDD control is DISABLED

            +
            +
            up_dac_gpio_in

            in [31:0]

            +

            GPI ports connected to the AXI memory map for custom use

            +
            +
            up_dac_gpio_out

            out [31:0]

            +

            GPI ports connected to the AXI memory map for custom use

            +
            +
            up_adc_gpio_in

            in [31:0]

            +

            GPI ports connected to the AXI memory map for custom use

            +
            +
            up_adc_gpio_out

            out [31:0]

            +

            GPO ports connected to the AXI memory map for custom use

            +
            +
            adc_enable_i*

            out

            +

            If set, the channel is enabled (one for each channel)

            +
            +
            adc_valid_i*

            out

            +

            Indicates valid data at the current channel (one for each channel)

            +
            +
            adc_data_i*

            out [15:0]

            +

            Received data output (one for each channel)

            +
            +
            adc_enable_q*

            out

            +

            If set, the channel is enabled (one for each channel)

            +
            +
            adc_valid_q*

            out

            +

            Indicates valid data at the current channel (one for each channel)

            +
            +
            adc_data_q*

            out [15:0]

            +

            Received data output (one for each channel)

            +
            +
            dac_enable_i*

            out

            +

            If set, the channel is enabled (one for each channel)

            +
            +
            dac_valid_i*

            out

            +

            Indicates valid data request at the current channel (one for each channel)

            +
            +
            dac_data_i*

            in [15:0]

            +

            Transmitted data output (one for each channel)

            +
            +
            dac_enable_q*

            out

            +

            If set, the channel is enabled (one for each channel)

            +
            +
            dac_valid_q*

            out

            +

            Indicates valid data request at the current channel (one for each channel)

            +
            +
            dac_data_q*

            in [15:0]

            +

            Transmitted data output (one for each channel)

            +
            +
            +
            +
            +
            +
            +
            +
            +

            Register Map#

            +

            The register map of the core contains instances of several generic register maps +like ADC common, ADC channel, DAC common, DAC channel etc. The following table +presents the base addresses of each instance, after that can be found the +detailed description of each generic register map. The absolute address of a +register should be calculated by adding the instance base address to the +registers relative address.

            +
            + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
            Register Map base addresses for axi_ad9361#

            DWORD

            BYTE

            Name

            Description

            0x0000

            0x0000

            BASE

            See the Base table for more details.

            0x0000

            0x0000

            RX COMMON

            See the ADC Common table for more details.

            0x0000

            0x0000

            RX CHANNELS

            See the ADC Channel table for more details.

            0x1000

            0x4000

            TX COMMON

            See the DAC Common table for more details.

            0x1000

            0x4000

            TX CHANNELS

            See the DAC Channel table for more details.

            0x2000

            0x8000

            TDD CONTROL

            See the Transceiver TDD Control table for more details.

            +
            +
            +
            +
            +
            +
            + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

            DWORD

            BYTE

            Reg Name

            Description

            BITS

            Field Name

            Type

            Default Value

            Description

            0x00x0VERSION
            +

            Version and Scratch Registers

            +
            +

            		[31:0]VERSIONRO0x00000000
            +

            Version number. Unique to all cores.

            +
            +
            0x10x4ID
            +

            Version and Scratch Registers

            +
            +

            		[31:0]IDRO0x00000000
            +

            Instance identifier number.

            +
            +
            0x20x8SCRATCH
            +

            Version and Scratch Registers

            +
            +

            		[31:0]SCRATCHRW0x00000000
            +

            Scratch register.

            +
            +
            0x30xcCONFIG
            +

            Version and Scratch Registers

            +
            +

            		[0:0]IQCORRECTION_DISABLERO0x0
            +

            If set, indicates that the IQ Correction module was not implemented. (as a result of a configuration of the IP instance)

            +
            +

            		[1:1]DCFILTER_DISABLERO0x0
            +

            If set, indicates that the DC Filter module was not implemented. (as a result of a configuration of the IP instance)

            +
            +

            		[2:2]DATAFORMAT_DISABLERO0x0
            +

            If set, indicates that the Data Format module was not implemented. (as a result of a configuration of the IP instance)

            +
            +

            		[3:3]USERPORTS_DISABLERO0x0
            +

            If set, indicates that the logic related to the User Data Format (e.g. decimation) was not implemented. (as a result of a configuration of the IP instance)

            +
            +

            		[4:4]MODE_1R1TRO0x0
            +

            If set, indicates that the core was implemented in 1 channel mode. (e.g. refer to AD9361 data sheet)

            +
            +

            		[5:5]DELAY_CONTROL_DISABLERO0x0
            +

            If set, indicates that the delay control is disabled for this IP. (as a result of a configuration of the IP instance)

            +
            +

            		[6:6]DDS_DISABLERO0x0
            +

            If set, indicates that the DDS is disabled for this IP. (as a result of a configuration of the IP instance)

            +
            +

            		[7:7]CMOS_OR_LVDS_NRO0x0
            +

            CMOS or LVDS mode is used for the interface. (as a result of a configuration of the IP instance)

            +
            +

            		[8:8]PPS_RECEIVER_ENABLERO0x0
            +

            If set, indicates the PPS receiver is enabled. (as a result of a configuration of the IP instance)

            +
            +

            		[9:9]SCALECORRECTION_ONLYRO0x0
            +

            If set, indicates that the IQ Correction module implements only scale correction. IQ correction must be enabled. (as a result of a configuration of the IP instance)

            +
            +

            		[12:12]EXT_SYNCRO0x0
            +

            If set the transport layer cores (ADC/DAC) have implemented the support for external synchronization signal.

            +
            +

            		[13:13]RD_RAW_DATARO0x0
            +

            If set, the ADC has the capability to read raw data in register CHAN_RAW_DATA from adc_channel.

            +
            +
            0x40x10PPS_IRQ_MASK
            +

            PPS Interrupt mask

            +
            +

            		[0:0]PPS_IRQ_MASKRW0x1
            +

            Mask bit for the 1PPS receiver interrupt

            +
            +
            0x70x1cFPGA_INFO
            +

            FPGA device information library/scripts/adi_intel_device_info_enc.tcl (Intel encoded values) library/scripts/adi_xilinx_device_info_enc.tcl (Xilinx encoded values)

            +
            +

            		[31:24]FPGA_TECHNOLOGYRO0x00
            +

            Encoded value describing the technology/generation of the FPGA device (arria 10/7series)

            +
            +

            		[23:16]FPGA_FAMILYRO0x00
            +

            Encoded value describing the family variant of the FPGA device(e.g., SX, GX, GT or zynq, kintex, virtex)

            +
            +

            		[15:8]SPEED_GRADERO0x00
            +

            Encoded value describing the FPGA’s speed-grade

            +
            +

            		[7:0]DEV_PACKAGERO0x00
            +

            Encoded value describing the device package. The package might affect high-speed interfaces

            +
            +
            +
            +
            +
            +
            +
            +
            +
            +
            +
            +
            + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

            DWORD

            BYTE

            Reg Name

            Description

            BITS

            Field Name

            Type

            Default Value

            Description

            0x100x40RSTN
            +

            ADC Interface Control & Status

            +
            +

            		[2:2]CE_NRW0x0
            +

            Clock enable, default is enabled(0x0). An inverse version of the signal is exported out of the module to control clock enables

            +
            +

            		[1:1]MMCM_RSTNRW0x0
            +

            MMCM reset only (required for DRP access). Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.

            +
            +

            		[0:0]RSTNRW0x0
            +

            Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.

            +
            +
            0x110x44CNTRL
            +

            ADC Interface Control & Status

            +
            +

            		[16:16]SDR_DDR_NRW0x0
            +

            Interface type (1 represents SDR, 0 represents DDR)

            +
            +

            		[15:15]SYMB_OPRW0x0
            +

            Select symbol data format mode (0x1)

            +
            +

            		[14:14]SYMB_8_16BRW0x0
            +

            Select number of bits for symbol format mode (1 represents 8b, 0 represents 16b)

            +
            +

            		[12:8]NUM_LANESRW0x00
            +

            Number of active lanes (1 : CSSI 1-lane, LSSI 1-lane, 2 : LSSI 2-lane, 4 : CSSI 4-lane). For AD7768, AD7768-4 and AD777x number of active lanes : 1/2/4/8 where supported.

            +
            +

            		[3:3]SYNCRW0x0
            +

            Initialize synchronization between multiple ADCs

            +
            +

            		[2:2]R1_MODERW0x0
            +

            Select number of RF channels 1 (0x1) or 2 (0x0).

            +
            +

            		[1:1]DDR_EDGESELRW0x0
            +

            Select rising edge (0x0) or falling edge (0x1) for the first part of a sample (if applicable) followed by the successive edges for the remaining parts. This only controls how the sample is delineated from the incoming data post DDR registers.

            +
            +

            		[0:0]PIN_MODERW0x0
            +

            Select interface pin mode to be clock multiplexed (0x1) or pin multiplexed (0x0). In clock multiplexed mode, samples are received on alternative clock edges. In pin multiplexed mode, samples are interleaved or grouped on the pins at the same clock edge.

            +
            +
            0x120x48CNTRL_2
            +

            ADC Interface Control & Status

            +
            +

            		[1:1]EXT_SYNC_ARMRW0x0
            +

            Setting this bit will arm the trigger mechanism sensitive to an external sync signal. Once the external sync signal goes high it synchronizes channels within a ADC, and across multiple instances. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.

            +
            +

            		[2:2]EXT_SYNC_DISARMRW0x0
            +

            Setting this bit will disarm the trigger mechanism sensitive to an external sync signal. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.

            +
            +

            		[8:8]MANUAL_SYNC_REQUESTRW0x0
            +

            Setting this bit will issue an external sync event if it is hooked up inside the fabric. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.

            +
            +
            0x130x4cCNTRL_3
            +

            ADC Interface Control & Status

            +
            +

            		[8:8]CRC_ENRW0x0
            +

            Setting this bit will enable the CRC generation.

            +
            +

            		[7:0]CUSTOM_CONTROLRW0x00
            +

            Select output format decode mode.(for ADAQ8092: bit 0 - enables digital output randomizer decode , bit 1 - enables alternate bit polarity decode).

            +
            +
            0x150x54CLK_FREQ
            +

            ADC Interface Control & Status

            +
            +

            		[31:0]CLK_FREQRO0x00000000
            +

            Interface clock frequency. This is relative to the processor clock and in many cases is 100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be the same as the interface clock- software must consider device specific implementation parameters to calculate the final sampling clock.

            +
            +
            0x160x58CLK_RATIO
            +

            ADC Interface Control & Status

            +
            +

            		[31:0]CLK_RATIORO0x00000000
            +

            Interface clock ratio - as a factor actual received clock. This is implementation specific and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr).

            +
            +
            0x170x5cSTATUS
            +

            ADC Interface Control & Status

            +
            +

            		[4:4]ADC_CTRL_STATUSRO0x0
            +

            If set, indicates that the device’​s register data is available on the data bus.

            +
            +

            		[3:3]PN_ERRRO0x0
            +

            If set, indicates pn error in one or more channels.

            +
            +

            		[2:2]PN_OOSRO0x0
            +

            If set, indicates pn oos in one or more channels.

            +
            +

            		[1:1]OVER_RANGERO0x0
            +

            If set, indicates over range in one or more channels.

            +
            +

            		[0:0]STATUSRO0x0
            +

            Interface status, if set indicates no errors. If not set, there are errors, software may try resetting the cores.

            +
            +
            0x180x60DELAY_CNTRL
            +

            ADC Interface Control & Status(‘’Deprecated from version 9’’)

            +
            +

            		[17:17]DELAY_SELRW0x0
            +

            Delay select, a 0x0 to 0x1 transition in this register initiates a delay access controlled by the registers below.

            +
            +

            		[16:16]DELAY_RWNRW0x0
            +

            Delay read (0x1) or write (0x0), the delay is accessed directly (no increment or decrement) with an address corresponding to each pin, and data corresponding to the total delay.

            +
            +

            		[15:8]DELAY_ADDRESSRW0x00
            +

            Delay address, the range depends on the interface pins, data pins are usually at the lower range.

            +
            +

            		[4:0]DELAY_WDATARW0x00
            +

            Delay write data, a value of 1 corresponds to (1/200)ns for most devices.

            +
            +
            0x190x64DELAY_STATUS
            +

            ADC Interface Control & Status(‘’Deprecated from version 9’’)

            +
            +

            		[9:9]DELAY_LOCKEDRO0x0
            +

            Indicates delay locked (0x1) state. If this bit is read 0x0, delay control has failed to calibrate the elements.

            +
            +

            		[8:8]DELAY_STATUSRO0x0
            +

            If set, indicates busy status (access pending). The read data may not be valid if this bit is set.

            +
            +

            		[4:0]DELAY_RDATARO0x00
            +

            Delay read data, current delay value in the elements

            +
            +
            0x1a0x68SYNC_STATUS
            +

            ADC Synchronization Status register

            +
            +

            		[0:0]ADC_SYNCRO0x0
            +

            ADC synchronization status. Will be set to 1 after the synchronization has been completed or while waiting for the synchronization signal in JESD204 systems.

            +
            +
            0x1c0x70DRP_CNTRL
            +

            ADC Interface Control & Status

            +
            +

            		[28:28]DRP_RWNRW0x0
            +

            DRP read (0x1) or write (0x0) select (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).

            +
            +

            		[27:16]DRP_ADDRESSRW0x000
            +

            DRP address, designs that contain more than one DRP accessible primitives have selects based on the most significant bits (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).

            +
            +

            		[15:0]RESERVEDRO0x0000
            +

            Reserved for backward compatibility.

            +
            +
            0x1d0x74DRP_STATUS
            +

            ADC Interface Control & Status

            +
            +

            		[17:17]DRP_LOCKEDRO0x0
            +

            If set indicates that the DRP has been locked.

            +
            +

            		[16:16]DRP_STATUSRO0x0
            +

            If set indicates busy (access pending). The read data may not be valid if this bit is set (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).

            +
            +

            		[15:0]RESERVEDRO0x0000
            +

            Reserved for backward compatibility.

            +
            +
            0x1e0x78DRP_WDATA
            +

            ADC DRP Write Data

            +
            +

            		[15:0]DRP_WDATARW0x0000
            +

            DRP write data (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).

            +
            +
            0x1f0x7cDRP_RDATA
            +

            ADC DRP Read Data

            +
            +

            		[15:0]DRP_RDATARO0x0000
            +

            DRP read data (does not include GTX lanes).

            +
            +
            0x200x80ADC_CONFIG_WR
            +

            ADC Write Configuration ​Data

            +
            +

            		[31:0]ADC_CONFIG_WRRW0x00000000
            +

            Custom ​Write to the available registers.

            +
            +
            0x210x84ADC_CONFIG_RD
            +

            ADC Read Configuration ​Data

            +
            +

            		[31:0]ADC_CONFIG_RDRO0x00000000
            +

            Custom read of the available registers.

            +
            +
            0x220x88UI_STATUS
            +

            User Interface Status

            +
            +

            		[2:2]UI_OVFRW1C0x0
            +

            User Interface overflow. If set, indicates an overflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.

            +
            +

            		[1:1]UI_UNFRW1C0x0
            +

            User Interface underflow. If set, indicates an underflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.

            +
            +

            		[0:0]UI_RESERVEDRW1C0x0
            +

            Reserved for backward compatibility.

            +
            +
            0x230x8cADC_CONFIG_CTRL
            +

            ADC RD/WR configuration

            +
            +

            		[31:0]ADC_CONFIG_CTRLRW0x00000000
            +

            Control RD/WR requests to the device’​s register map: bit 1 - RD (‘b1) , WR (‘b0), bit 0 - enable WR/RD operation.

            +
            +
            0x280xa0USR_CNTRL_1
            +

            ADC Interface Control & Status

            +
            +

            		[7:0]USR_CHANMAXRW0x00
            +

            This indicates the maximum number of inputs for the channel data multiplexers. User may add different processing modules post data capture as another input to this common multiplexer. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

            +
            +
            0x290xa4ADC_START_CODE
            +

            ADC Synchronization start word

            +
            +

            		[31:0]ADC_START_CODERW0x00000000
            +

            This sets the startcode that is used by the ADCs for synchronization NOT-APPLICABLE if START_CODE_DISABLE is set (0x1).

            +
            +
            0x2e0xb8ADC_GPIO_IN
            +

            ADC GPIO inputs

            +
            +

            		[31:0]ADC_GPIO_INRO0x00000000
            +

            This reads auxiliary GPI pins of the ADC core

            +
            +
            0x2f0xbcADC_GPIO_OUT
            +

            ADC GPIO outputs

            +
            +

            		[31:0]ADC_GPIO_OUTRW0x00000000
            +

            This controls auxiliary GPO pins of the ADC core NOT-APPLICABLE if GPIO_DISABLE is set (0x1).

            +
            +
            0x300xc0PPS_COUNTER
            +

            PPS Counter register

            +
            +

            		[31:0]PPS_COUNTERRO0x00000000
            +

            Counts the core clock cycles (can be a device clock or interface clock) between two 1PPS pulse.

            +
            +
            0x310xc4PPS_STATUS
            +

            PPS Status register

            +
            +

            		[0:0]PPS_STATUSRO0x0
            +

            If this bit is asserted there is no incomming 1PPS signal. Maybe the source is out of sync or it’s not active.

            +
            +
            +
            +
            +
            +
            +
            +
            +
            +
            +
            +
            + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

            DWORD

            BYTE

            Reg Name

            Description

            BITS

            Field Name

            Type

            Default Value

            Description

            0x100 + 0x16*n0x400 + 0x58*nCHAN_CNTRLn
            +

            ADC Interface Control & Status Where n is from 0 to 15.

            +
            +

            		[11:11]ADC_LB_OWRRW0x0
            +

            If set, forces ADC_DATA_SEL to 1, enabling data loopback

            +
            +

            		[10:10]ADC_PN_SEL_OWRRW0x0
            +

            If set, forces ADC_PN_SEL to 0x9, device specific pn (e.g. ad9361) If both ADC_PN_TYPE_OWR and ADC_PN_SEL_OWR are set, they are ignored

            +
            +

            		[9:9]IQCOR_ENBRW0x0
            +

            if set, enables IQ correction or scale correction. NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).

            +
            +

            		[8:8]DCFILT_ENBRW0x0
            +

            if set, enables DC filter (to disable DC offset, set offset value to 0x0). NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1).

            +
            +

            		[6:6]FORMAT_SIGNEXTRW0x0
            +

            if set, enables sign extension (applicable only in 2’s complement mode). The data is always sign extended to the nearest byte boundary. NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1).

            +
            +

            		[5:5]FORMAT_TYPERW0x0
            +

            Select offset binary (0x1) or 2’s complement (0x0) data type. This sets the incoming data type and is required by the post processing modules for any data conversion. NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1).

            +
            +

            		[4:4]FORMAT_ENABLERW0x0
            +

            Enable data format conversion (see register bits above). NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1).

            +
            +

            		[3:3]RESERVEDRO0x0
            +

            Reserved for backward compatibility.

            +
            +

            		[2:2]RESERVEDRO0x0
            +

            Reserved for backward compatibility.

            +
            +

            		[1:1]ADC_PN_TYPE_OWRRW0x0
            +

            If set, forces ADC_PN_SEL to 0x1, modified pn23 If both ADC_PN_TYPE_OWR and ADC_PN_SEL_OWR are set, they are ignored

            +
            +

            		[0:0]ENABLERW0x0
            +

            If set, enables channel. A 0x0 to 0x1 transition transfers all the control signals to the respective channel processing module. If a channel is part of a complex signal (I/Q), even channel is the master and the odd channel is the slave. Though a single control is used, both must be individually selected.

            +
            +
            0x101 + 0x16*n0x404 + 0x58*nCHAN_STATUSn
            +

            ADC Interface Control & Status Where n is from 0 to 15.

            +
            +

            		[12:12]CRC_ERRRW1C0x0
            +

            CRC errors. If set, indicates CRC error. Software must first clear this bit before initiating a transfer and monitor afterwards.

            +
            +

            		[11:4]STATUS_HEADERRO0x00
            +

            The status header sent by the ADC.(compatible with AD7768/AD7768-4/AD777x).

            +
            +

            		[2:2]PN_ERRRW1C0x0
            +

            PN errors. If set, indicates spurious mismatches in sync state. This bit is cleared if OOS is set and is only indicates errors when OOS is cleared.

            +
            +

            		[1:1]PN_OOSRW1C0x0
            +

            PN Out Of Sync. If set, indicates an OOS status. OOS is set, if 64 consecutive patterns mismatch from the expected pattern. It is cleared, when 16 consecutive patterns match the expected pattern.

            +
            +

            		[0:0]OVER_RANGERW1C0x0
            +

            If set, indicates over range. Note that over range is independent of the data path, it indicates an over range over a data transfer period. Software must first clear this bit before initiating a transfer and monitor afterwards.

            +
            +
            0x102 + 0x16*n0x408 + 0x58*nCHAN_RAW_DATAn
            +

            ADC Raw Data Reading Where n is from 0 to 15.

            +
            +

            		[31:0]ADC_READ_DATARO0x00000000
            +

            Raw data read from the ADC.

            +
            +
            0x104 + 0x16*n0x410 + 0x58*nCHAN_CNTRLn_1
            +

            ADC Interface Control & Status Where n is from 0 to 15.

            +
            +

            		[31:16]DCFILT_OFFSETRW0x0000
            +

            DC removal (if equipped) offset. This is a 2’s complement number added to the incoming data to remove a known DC offset. NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1).

            +
            +

            		[15:0]DCFILT_COEFFRW0x0000
            +

            DC removal filter (if equipped) coefficient. The format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1).

            +
            +
            0x105 + 0x16*n0x414 + 0x58*nCHAN_CNTRLn_2
            +

            ADC Interface Control & Status Where n is from 0 to 15.

            +
            +

            		[31:16]IQCOR_COEFF_1RW0x0000
            +

            IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the scale value and the format is 1.1.14 (sign, integer and fractional bits). If matrix multiplication is used, this is the channel I coefficient and the format is 1.1.14 (sign, integer and fractional bits). If SCALECORRECTION_ONLY is set, this implements the scale value correction for the current channel with the format 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).

            +
            +

            		[15:0]IQCOR_COEFF_2RW0x0000
            +

            IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the offset value and the format is 2’s complement. If matrix multiplication is used, this is the channel Q coefficient and the format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).

            +
            +
            0x106 + 0x16*n0x418 + 0x58*nCHAN_CNTRLn_3
            +

            ADC Interface Control & Status Where n is from 0 to 15.

            +
            +

            		[19:16]ADC_PN_SELRW0x0
            +

            Selects the PN monitor sequence type (available only if ADC supports it). \ - 0x0: pn9a (device specific, modified pn9) \ - 0x1: pn23a (device specific, modified pn23) \ - 0x4: pn7 (standard O.150) \ - 0x5: pn15 (standard O.150) \ - 0x6: pn23 (standard O.150) \ - 0x7: pn31 (standard O.150) \ - 0x9: pnX (device specific, e.g. ad9361) \ - 0x0A: Nibble ramp (Device specific e.g. adrv9001) \ - 0x0B: 16 bit ramp (Device specific e.g. adrv9001) \

            +
            +

            		[3:0]ADC_DATA_SELRW0x0
            +

            Selects the data source to DMA. 0x0: input data (ADC) 0x1: loopback data (DAC)

            +
            +
            0x108 + 0x16*n0x420 + 0x58*nCHAN_USR_CNTRLn_1
            +

            ADC Interface Control & Status Where n is from 0 to 15.

            +
            +

            		[25:25]USR_DATATYPE_BERO0x0
            +

            The user data type format- if set, indicates big endian (default is little endian). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

            +
            +

            		[24:24]USR_DATATYPE_SIGNEDRO0x0
            +

            The user data type format- if set, indicates signed (2’s complement) data (default is unsigned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

            +
            +

            		[23:16]USR_DATATYPE_SHIFTRO0x00
            +

            The user data type format- the amount of right shift for actual samples within the total number of bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

            +
            +

            		[15:8]USR_DATATYPE_TOTAL_BITSRO0x00
            +

            The user data type format- number of total bits used for a sample. The total number of bits must be an integer multiple of 8 (byte aligned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

            +
            +

            		[7:0]USR_DATATYPE_BITSRO0x00
            +

            The user data type format- number of bits in a sample. This indicates the actual sample data bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

            +
            +
            0x109 + 0x16*n0x424 + 0x58*nCHAN_USR_CNTRLn_2
            +

            ADC Interface Control & Status Where n is from 0 to 15.

            +
            +

            		[31:16]USR_DECIMATION_MRW0x0000
            +

            This holds the user decimation M value of the channel that is currently being selected on the multiplexer above. The total decimation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

            +
            +

            		[15:0]USR_DECIMATION_NRW0x0000
            +

            This holds the user decimation N value of the channel that is currently being selected on the multiplexer above. The total decimation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

            +
            +
            0x10a + 0x16*n0x428 + 0x58*nCHAN_CNTRLn_4
            +

            ADC Interface Control & Status Where n is from 0 to 15.

            +
            +

            		[31:3]RESERVEDRO0x00000000
            +

            Reserved for backward compatibility.

            +
            +

            		[2:0]SOFTSPANRW0x7
            +

            Softspan configuration register.

            +
            +
            +
            +
            +
            +
            +
            +
            +
            +
            +
            +
            + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

            DWORD

            BYTE

            Reg Name

            Description

            BITS

            Field Name

            Type

            Default Value

            Description

            0x100x40RSTN
            +

            DAC Interface Control & Status

            +
            +

            		[2:2]CE_NRW0x0
            +

            Clock enable, default is enabled(0x0). An inverse version of the signal is exported out of the module to control clock enables

            +
            +

            		[1:1]MMCM_RSTNRW0x0
            +

            MMCM reset only (required for DRP access). Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.

            +
            +

            		[0:0]RSTNRW0x0
            +

            Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.

            +
            +
            0x110x44CNTRL_1
            +

            DAC Interface Control & Status

            +
            +

            		[0:0]SYNCRW0x0
            +

            Setting this bit synchronizes channels within a DAC, and across multiple instances. This bit self clears.

            +
            +

            		[1:1]EXT_SYNC_ARMRW0x0
            +

            Setting this bit will arm the trigger mechanism sensitive to an external sync signal. Once the external sync signal goes high it synchronizes channels within a DAC, and across multiple instances. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.

            +
            +

            		[2:2]EXT_SYNC_DISARMRW0x0
            +

            Setting this bit will disarm the trigger mechanism sensitive to an external sync signal. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.

            +
            +

            		[8:8]MANUAL_SYNC_REQUESTRW0x0
            +

            Setting this bit will issue an external sync event if it is hooked up inside the fabric. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.

            +
            +
            0x120x48CNTRL_2
            +

            DAC Interface Control & Status

            +
            +

            		[16:16]SDR_DDR_NRW0x0
            +

            Interface type (1 represents SDR, 0 represents DDR)

            +
            +

            		[15:15]SYMB_OPRW0x0
            +

            Select data symbol format mode (0x1)

            +
            +

            		[14:14]SYMB_8_16BRW0x0
            +

            Select number of bits for symbol format mode (1 represents 8b, 0 represents 16b)

            +
            +

            		[12:8]NUM_LANESRW0x00
            +

            Number of active lanes (1 : CSSI 1-lane, LSSI 1-lane, 2 : LSSI 2-lane, 4 : CSSI 4-lane)

            +
            +

            		[7:7]PAR_TYPERW0x0
            +

            Select parity even (0x0) or odd (0x1).

            +
            +

            		[6:6]PAR_ENBRW0x0
            +

            Select parity (0x1) or frame (0x0) mode.

            +
            +

            		[5:5]R1_MODERW0x0
            +

            Select number of RF channels 1 (0x1) or 2 (0x0).

            +
            +

            		[4:4]DATA_FORMATRW0x0
            +

            Select data format 2’s complement (0x0) or offset binary (0x1). NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1).

            +
            +

            		[3:0]RESERVEDNA0x0
            +

            Reserved

            +
            +
            0x130x4cRATECNTRL
            +

            DAC Interface Control & Status

            +
            +

            		[7:0]RATERW0x00
            +

            The effective dac rate (the maximum possible rate is dependent on the interface clock). The samples are generated at 1/RATE of the interface clock.

            +
            +
            0x140x50FRAME
            +

            DAC Interface Control & Status

            +
            +

            		[0:0]FRAMERW0x0
            +

            The use of frame is device specific. Usually setting this bit to 1 generates a FRAME (1 DCI clock period) pulse on the interface. This bit self clears.

            +
            +
            0x150x54STATUS1
            +

            DAC Interface Control & Status

            +
            +

            		[31:0]CLK_FREQRO0x00000000
            +

            Interface clock frequency. This is relative to the processor clock and in many cases is 100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be the same as the interface clock- software must consider device specific implementation parameters to calculate the final sampling clock.

            +
            +
            0x160x58STATUS2
            +

            DAC Interface Control & Status

            +
            +

            		[31:0]CLK_RATIORO0x00000000
            +

            Interface clock ratio - as a factor actual received clock. This is implementation specific and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr).

            +
            +
            0x170x5cSTATUS3
            +

            DAC Interface Control & Status

            +
            +

            		[0:0]STATUSRO0x0
            +

            Interface status, if set indicates no errors. If not set, there are errors, software may try resetting the cores.

            +
            +
            0x180x60DAC_CLKSEL
            +

            DAC Interface Control & Status

            +
            +

            		[0:0]DAC_CLKSELRW0x0
            +

            Allows changing of the clock polarity. Note: its default value is CLK_EDGE_SEL

            +
            +
            0x1a0x68SYNC_STATUS
            +

            DAC Synchronization Status register

            +
            +

            		[0:0]DAC_SYNC_STATUSRO0x0
            +

            DAC synchronization status. Will be set to 1 while waiting for the external synchronization signal This bit has an effect only the EXT_SYNC synthesis parameter is set.

            +
            +
            0x1c0x70DRP_CNTRL
            +

            DRP Control & Status

            +
            +

            		[28:28]DRP_RWNRW0x0
            +

            DRP read (0x1) or write (0x0) select (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).

            +
            +

            		[27:16]DRP_ADDRESSRW0x000
            +

            DRP address, designs that contain more than one DRP accessible primitives have selects based on the most significant bits (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).

            +
            +

            		[15:0]RESERVEDRO0x0000
            +

            Reserved for backwards compatibility

            +
            +
            0x1d0x74DRP_STATUS
            +

            DAC Interface Control & Status

            +
            +

            		[17:17]DRP_LOCKEDRO0x0
            +

            If set indicates the MMCM/PLL is locked

            +
            +

            		[16:16]DRP_STATUSRO0x0
            +

            If set indicates busy (access pending). The read data may not be valid if this bit is set (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).

            +
            +

            		[15:0]RESERVEDRO0x0000
            +

            Reserved for backwards compatibility

            +
            +
            0x1e0x78DRP_WDATA
            +

            DAC Interface Control & Status

            +
            +

            		[15:0]DRP_WDATARW0x0000
            +

            DRP write data (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).

            +
            +
            0x1f0x7cDRP_RDATA
            +

            DAC Interface Control & Status

            +
            +

            		[15:0]DRP_RDATARO0x0000
            +

            DRP read data (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).

            +
            +
            0x200x80DAC_CUSTOM_RD
            +

            DAC Read Configuration Data

            +
            +

            		[31:0]DAC_CUSTOM_RDRO0x00000000
            +

            Custom Read of the available registers.

            +
            +
            0x210x84DAC_CUSTOM_WR
            +

            DAC Write Configuration Data

            +
            +

            		[31:0]DAC_CUSTOM_WRRW0x00000000
            +

            Custom Write of the available registers.

            +
            +
            0x220x88UI_STATUS
            +

            User Interface Status

            +
            +

            		[4:4]IF_BUSYRO0x0
            +

            Interface busy. If set, indicates that the data interface is busy.

            +
            +

            		[1:1]UI_OVFRW1C0x0
            +

            User Interface overflow. If set, indicates an overflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.

            +
            +

            		[0:0]UI_UNFRW1C0x0
            +

            User Interface underflow. If set, indicates an underflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.

            +
            +
            0x230x8cDAC_CUSTOM_CTRL
            +

            DAC Control Configuration Data

            +
            +

            		[31:0]DAC_CUSTOM_CTRLRW0x00000000
            +

            Custom Control of the available registers.

            +
            +
            0x280xa0USR_CNTRL_1
            +

            DAC User Control & Status

            +
            +

            		[7:0]USR_CHANMAXRW0x00
            +

            This indicates the maximum number of inputs for the channel data multiplexers. User may add different processing modules as inputs to the dac. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

            +
            +
            0x2e0xb8DAC_GPIO_IN
            +

            DAC GPIO inputs

            +
            +

            		[31:0]DAC_GPIO_INRO0x00000000
            +

            This reads auxiliary GPI pins of the DAC core

            +
            +
            0x2f0xbcDAC_GPIO_OUT
            +

            DAC GPIO outputs

            +
            +

            		[31:0]DAC_GPIO_OUTRW0x00000000
            +

            This controls auxiliary GPO pins of the DAC core NOT-APPLICABLE if GPIO_DISABLE is set (0x1).

            +
            +
            +
            +
            +
            +
            +
            +
            +
            +
            +
            +
            + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

            DWORD

            BYTE

            Reg Name

            Description

            BITS

            Field Name

            Type

            Default Value

            Description

            0x100 + 0x16*n0x400 + 0x58*nCHAN_CNTRLn_1
            +

            DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

            +
            +

            		[21:16]DDS_PHASE_DWRO0x00
            +

            The DDS phase data width offers the HDL parameter configuration with the same name. This information is used in conjunction with CHAN_CNTRL_9 and CHAN_CNTRL_10. More info at AD Direct Digital Synthesis.

            +
            +

            		[15:0]DDS_SCALE_1RW0x0000
            +

            The DDS scale for tone 1. Sets the amplitude of the tone. The format is 1.1.14 fixed point (signed, integer, fractional). The DDS in general runs on 16-bits, note that if you do use both channels and set both scale to 0x4000, it is over-range. The final output is (tone_1_fullscale * scale_1) + (tone_2_fullscale * scale_2). NOT-APPLICABLE if DDS_DISABLE is set (0x1).

            +
            +
            0x101 + 0x16*n0x404 + 0x58*nCHAN_CNTRLn_2
            +

            DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

            +
            +

            		[31:16]DDS_INIT_1RW0x0000
            +

            The DDS phase initialization for tone 1. Sets the initial phase offset of the tone. NOT-APPLICABLE if DDS_DISABLE is set (0x1).

            +
            +

            		[15:0]DDS_INCR_1RW0x0000
            +

            Sets the frequency of the phase accumulator. Its value can be calculated by \(INCR = (f_{out} * 2^{16}) * clkratio / f_{if}\); where f_out is the generated output frequency, and f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. If DDS_PHASE_DW is greater than 16(from CHAN_CNTRL_1), the phase increment for tone 1 is extended in CHAN_CNTRL_9. NOT-APPLICABLE if DDS_DISABLE is set (0x1).

            +
            +
            0x102 + 0x16*n0x408 + 0x58*nCHAN_CNTRLn_3
            +

            DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

            +
            +

            		[15:0]DDS_SCALE_2RW0x0000
            +

            The DDS scale for tone 2. Sets the amplitude of the tone. The format is 1.1.14 fixed point (signed, integer, fractional). The DDS in general runs on 16-bits, note that if you do use both channels and set both scale to 0x4000, it is over-range. The final output is (tone_1_fullscale * scale_1) + (tone_2_fullscale * scale_2). NOT-APPLICABLE if DDS_DISABLE is set (0x1).

            +
            +
            0x103 + 0x16*n0x40c + 0x58*nCHAN_CNTRLn_4
            +

            DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

            +
            +

            		[31:16]DDS_INIT_2RW0x0000
            +

            The DDS phase initialization for tone 2. Sets the initial phase offset of the tone. If DDS_PHASE_DW is greater than 16(from CHAN_CNTRL_1), the phase init for tone 2 is extended in CHAN_CNTRL_10. NOT-APPLICABLE if DDS_DISABLE is set (0x1).

            +
            +

            		[15:0]DDS_INCR_2RW0x0000
            +

            Sets the frequency of the phase accumulator. Its value can be calculated by \(INCR = (f_{out} * 2^{16}) * clkratio / f_{if}\); where f_out is the generated output frequency, and f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. If DDS_PHASE_DW is greater than 16(from CHAN_CNTRL_1), the phase increment for tone 2 is extended in CHAN_CNTRL_10. NOT-APPLICABLE if DDS_DISABLE is set (0x1).

            +
            +
            0x104 + 0x16*n0x410 + 0x58*nCHAN_CNTRLn_5
            +

            DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

            +
            +

            		[31:16]DDS_PATT_2RW0x0000
            +

            The DDS data pattern for this channel.

            +
            +

            		[15:0]DDS_PATT_1RW0x0000
            +

            The DDS data pattern for this channel.

            +
            +
            0x105 + 0x16*n0x414 + 0x58*nCHAN_CNTRLn_6
            +

            DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

            +
            +

            		[2:2]IQCOR_ENBRW0x0
            +

            if set, enables IQ correction. NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1).

            +
            +

            		[1:1]DAC_LB_OWRRW0x0
            +

            If set, forces DAC_DDS_SEL to 0x8, loopback If DAC_LB_OWR and DAC_PN_OWR are both set, they are ignored

            +
            +

            		[0:0]DAC_PN_OWRRW0x0
            +

            IF set, forces DAC_DDS_SEL to 0x09, device specific pnX If DAC_LB_OWR and DAC_PN_OWR are both set, they are ignored

            +
            +
            0x106 + 0x16*n0x418 + 0x58*nCHAN_CNTRLn_7
            +

            DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

            +
            +

            		[3:0]DAC_DDS_SELRW0x0
            +

            Select internal data sources (available only if the DAC supports it). \ - 0x00: internal tone (DDS) \ - 0x01: pattern (SED) \ - 0x02: input data (DMA) \ - 0x03: 0x00 \ - 0x04: inverted pn7 \ - 0x05: inverted pn15 \ - 0x06: pn7 (standard O.150) \ - 0x07: pn15 (standard O.150) \ - 0x08: loopback data (ADC) \ - 0x09: pnX (Device specific e.g. ad9361) \ - 0x0A: Nibble ramp (Device specific e.g. adrv9001) \ - 0x0B: 16 bit ramp (Device specific e.g. adrv9001) \

            +
            +
            0x107 + 0x16*n0x41c + 0x58*nCHAN_CNTRLn_8
            +

            DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

            +
            +

            		[31:16]IQCOR_COEFF_1RW0x0000
            +

            IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the scale value and the format is 1.1.14 (sign, integer and fractional bits). If matrix multiplication is used, this is the channel I coefficient and the format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).

            +
            +

            		[15:0]IQCOR_COEFF_2RW0x0000
            +

            IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the offset value and the format is 2’s complement. If matrix multiplication is used, this is the channel Q coefficient and the format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).

            +
            +
            0x108 + 0x16*n0x420 + 0x58*nUSR_CNTRLn_3
            +

            DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

            +
            +

            		[25:25]USR_DATATYPE_BERW0x0
            +

            The user data type format- if set, indicates big endian (default is little endian). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

            +
            +

            		[24:24]USR_DATATYPE_SIGNEDRW0x0
            +

            The user data type format- if set, indicates signed (2’s complement) data (default is unsigned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

            +
            +

            		[23:16]USR_DATATYPE_SHIFTRW0x00
            +

            The user data type format- the amount of right shift for actual samples within the total number of bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

            +
            +

            		[15:8]USR_DATATYPE_TOTAL_BITSRW0x00
            +

            The user data type format- number of total bits used for a sample. The total number of bits must be an integer multiple of 8 (byte aligned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

            +
            +

            		[7:0]USR_DATATYPE_BITSRW0x00
            +

            The user data type format- number of bits in a sample. This indicates the actual sample data bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

            +
            +
            0x109 + 0x16*n0x424 + 0x58*nUSR_CNTRLn_4
            +

            DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

            +
            +

            		[31:16]USR_INTERPOLATION_MRW0x0000
            +

            This holds the user interpolation M value of the channel that is currently being selected on the multiplexer above. The total interpolation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

            +
            +

            		[15:0]USR_INTERPOLATION_NRW0x0000
            +

            This holds the user interpolation N value of the channel that is currently being selected on the multiplexer above. The total interpolation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

            +
            +
            0x10a + 0x16*n0x428 + 0x58*nUSR_CNTRLn_5
            +

            DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

            +
            +

            		[0:0]DAC_IQ_MODERW0x0
            +

            Enable complex mode. In this mode the driven data to the DAC must be a sequence of I and Q sample pairs.

            +
            +

            		[1:1]DAC_IQ_SWAPRW0x0
            +

            Allows IQ swapping in complex mode. Only takes effect if complex mode is enabled.

            +
            +
            0x10b + 0x16*n0x42c + 0x58*nCHAN_CNTRLn_9
            +

            DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

            +
            +

            		[31:16]DDS_INIT_1_EXTENDEDRW0x0000
            +

            The extended DDS phase initialization for tone 1. Sets the initial phase offset of the tone. The extended init(phase) value should be calculated according to DDS_PHASE_DW value from CHAN_CNTRL_1 NOT-APPLICABLE if DDS_DISABLE is set (0x1).

            +
            +

            		[15:0]DDS_INCR_1_EXTENDEDRW0x0000
            +

            Sets the frequency of tone 1’s phase accumulator. Its value can be calculated by \(INCR = (f_{out} * 2^{phaseDW}) * clkratio / f_{if}\); Where f_out is the generated output frequency, DDS_PHASE_DW value can be found in CHAN_CNTRL_1 in case DDS_PHASE_DW is not 16, f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. NOT-APPLICABLE if DDS_DISABLE is set (0x1).

            +
            +
            0x10c + 0x16*n0x430 + 0x58*nCHAN_CNTRLn_10
            +

            DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

            +
            +

            		[31:16]DDS_INIT_2_EXTENDEDRW0x0000
            +

            The extended DDS phase initialization for tone 2. Sets the initial phase offset of the tone. The extended init(phase) value should be calculated according to DDS_PHASE_DW value from CHAN_CNTRL_2 NOT-APPLICABLE if DDS_DISABLE is set (0x1).

            +
            +

            		[15:0]DDS_INCR_2_EXTENDEDRW0x0000
            +

            Sets the frequency of tone 2’s phase accumulator. Its value can be calculated by \(INCR = (f_{out} * 2^{phaseDW}) * clkratio / f_{if}\); Where f_out is the generated output frequency, DDS_PHASE_DW value can be found in CHAN_CNTRL_2 in case DDS_PHASE_DW is not 16, f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. NOT-APPLICABLE if DDS_DISABLE is set (0x1).

            +
            +
            +
            +
            +
            +
            +
            +
            +
            +
            +
            +
            + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

            DWORD

            BYTE

            Reg Name

            Description

            BITS

            Field Name

            Type

            Default Value

            Description

            0x100x40TDD_CONTROL_0
            +

            TDD Control & Status

            +
            +

            		[5:5]TDD_GATED_TX_DMAPATHRW0x0
            +

            If this bit is set, the core requests data from the TX DMA, just when the data path is active. Otherwise will requests continuously on the adjusted rate. The purpose of this feature is to facilitate debug. This bit must be SET to preserve data integrity.

            +
            +

            		[4:4]TDD_GATED_RX_DMAPATHRW0x0
            +

            If this bit is set, the core provides data for the RX DMA, just when the data path is active. Otherwise will provides continuously on the adjusted rate. The purpose of this feature is to facilitate debug. This bit must be SET to preserve data integrity.

            +
            +

            		[3:3]TDD_TXONLYRW0x0
            +

            If this bit is set- the TDD controller ignores all the TX_* timing registers below and assumes continuous receive operation within a frame.

            +
            +

            		[2:2]TDD_RXONLYRW0x0
            +

            If this bit is set- the TDD controller ignores all the RX_* timing registers below and assumes continuous transmit operation within a frame.

            +
            +

            		[1:1]TDD_SECONDARYRW0x0
            +

            Enable the secondary transmit/receive on the active frame. If this bit is clear - the controller only uses the _1 timing registers below. If this bit is set - the controller uses the _1 and _2 timing registers below.

            +
            +

            		[0:0]TDD_ENABLERW0x0
            +

            If set, enables the TDD controller- software must set this bit after programming all the registers that controls the tdd timing. Any device settings needs to be done (for example bring the AD9361 to the alert state) prior to to setting this bit. The controller keeps the frame counters in reset if this bit is reset. A 0 to 1 transition in this bit starts the frame counter and tdd mode of operation.

            +
            +
            0x110x44TDD_CONTROL_1
            +

            TDD Control & Status

            +
            +

            		[7:0]TDD_BURST_COUNTRW0x00
            +

            If set to 0x0 and enabled (TDD_ENABLE is set) - the controller operates in TDD mode as long as the TDD_ENABLE bit is set. If set to a non-zero value, the controller operates for the set number of frames and stops.

            +
            +
            0x120x48TDD_CONTROL_2
            +

            TDD Control & Status

            +
            +

            		[23:0]TDD_COUNTER_INITRW0x000000
            +

            The controller sets the frame counter to this value when starting TDD operation. This is the starting offset value for the TDD frame counter.

            +
            +
            0x130x4cTDD_FRAME_LENGTH
            +

            TDD Control & Status

            +
            +

            		[23:0]TDD_FRAME_LENGTHRW0x000000
            +

            The frame length is the terminal count for the 10ms counter running at the digital interface clock- as an example for a 245.76MHz clock it is 0x258000.

            +
            +
            0x140x50TDD_SYNC_TERMINAL_TYPE
            +

            TDD Control & Status

            +
            +

            		[0:0]TDD_SYNC_TERMINAL_TYPERW0x0
            +

            Set this bit, if the current terminal will generate the syncronization pulse, reset otherwise.

            +
            +
            0x180x60TDD_STATUS
            +

            TDD Control & Status

            +
            +

            		[0:0]TDD_RXTX_VCO_OVERLAPRO0x0
            +

            This bit is asserted, if exist a time interval when both the TX and RX VCOs are powered up.

            +
            +

            		[1:1]TDD_RXTX_RF_OVERLAPRO0x0
            +

            This bit is asserted, if exist a time interval when both the TX and RX RF datapath are powered up.

            +
            +
            0x200x80TDD_VCO_RX_ON_1
            +

            TDD Control & Status

            +
            +

            		[23:0]TDD_VCO_RX_ON_1RW0x000000
            +

            Defines the offset (from frame count equal zero), when the RX VCO powers up at the first time. The controller enables the receive VCO, when the frame count reaches this value. The VCO may have to be enabled before data can be received. The user needs to make sure, that the RF device is in a state, from where this operation is valid.

            +
            +
            0x210x84TDD_VCO_RX_OFF_1
            +

            TDD Control & Status

            +
            +

            		[23:0]TDD_VCO_RX_OFF_1RW0x000000
            +

            Defines the offset (from frame count equal zero), when the RX VCO powers down at the first time. The controller disables the receive VCO, when the frame count reaches this value. The user needs to make sure, that the RF device is in a state, from where this operation is valid.

            +
            +
            0x220x88TDD_VCO_TX_ON_1
            +

            TDD Control & Status

            +
            +

            		[23:0]TDD_VCO_TX_ON_1RW0x000000
            +

            Defines the offset (from frame count equal zero), when the TX VCO powers up at the first time. The controller enables the transmit VCO, when the frame count reaches this value. The user needs to make sure, that the RF device is in a state, from where this operation is valid.

            +
            +
            0x230x8cTDD_VCO_TX_OFF_1
            +

            TDD Control & Status

            +
            +

            		[23:0]TDD_VCO_TX_OFF_1RW0x000000
            +

            Defines the offset (from frame count equal zero), when the TX VCO powers down at the first time. The controller disables the transmit VCO when the frame count reaches this value. The user needs to make sure, that the RF device is in a state, from where this operation is valid.

            +
            +
            0x240x90TDD_RX_ON_1
            +

            TDD Control & Status

            +
            +

            		[23:0]TDD_RX_ON_1RW0x000000
            +

            Defines the offset (from frame count equal zero), when the RX data path is activated at the first time. The controller enables the receive chain when the frame count reaches this value. The user needs to make sure, that the RF device is in a state, from where this operation is valid.

            +
            +
            0x250x94TDD_RX_OFF_1
            +

            TDD Control & Status

            +
            +

            		[23:0]TDD_RX_OFF_1RW0x000000
            +

            Defines the offset (from frame count equal zero), when the RX data path is deactivated the first time. The controller disables the receive chain when the frame count reaches this value. The user needs to make sure, that the RF device is in a state, from where this operation is valid.

            +
            +
            0x260x98TDD_TX_ON_1
            +

            TDD Control & Status

            +
            +

            		[23:0]TDD_TX_ON_1RW0x000000
            +

            Defines the offset (from frame count equal zero), when the TX data path is activated at the first time. The controller enables the transmit chain, when the frame count reaches this value. This register and the TX_DP_ON register controls the delay between the data path being activated and the time to actually push the transmit data through the transmit chain in the device.

            +
            +
            0x270x9cTDD_TX_OFF_1
            +

            TDD Control & Status

            +
            +

            		[23:0]TDD_TX_OFF_1RW0x000000
            +

            Defines the offset (from frame count equal zero), when the TX data path is deactivated at the first time. The controller disables the transmit chain, when the frame count reaches this value. This register and the TX_DP_OFF register controls the delay between the data path being deactivated and the time to actually stop transmitting data through the transmit chain in the device.

            +
            +
            0x280xa0TDD_RX_DP_ON_1
            +

            TDD Control & Status

            +
            +

            		[23:0]TDD_RX_DP_ON_1RW0x000000
            +

            Defines the offset (from frame count equal zero), when the controller starts to accept data from the digital interface for receive.

            +
            +
            0x290xa4TDD_RX_DP_OFF_1
            +

            TDD Control & Status

            +
            +

            		[23:0]TDD_RX_DP_OFF_1RW0x000000
            +

            Defines the offset (from frame count equal zero), when the controller stops to accept data from the digital interface for receive.

            +
            +
            0x2a0xa8TDD_TX_DP_ON_1
            +

            TDD Control & Status

            +
            +

            		[23:0]TDD_TX_DP_ON_1RW0x000000
            +

            Defines the offset (from frame count equal zero), when the controller starts to request data from the system memory for transmit. The data rate is controlled by the TDD controller.

            +
            +
            0x2b0xacTDD_TX_DP_OFF_1
            +

            TDD Control & Status

            +
            +

            		[23:0]TDD_TX_DP_OFF_1RW0x000000
            +

            Defines the offset (from frame count equal zero), when the controller stop requesting data from the system memory for transmit.

            +
            +
            0x300xc0TDD_VCO_RX_ON_2
            +

            TDD Control & Status

            +
            +

            		[23:0]TDD_VCO_RX_ON_2RW0x000000
            +

            The secondary pointer for VCO_RX_ON.

            +
            +
            0x310xc4TDD_VCO_RX_OFF_2
            +

            TDD Control & Status

            +
            +

            		[23:0]TDD_VCO_RX_OFF_2RW0x000000
            +

            The secondary pointer for VCO_RX_OFF.

            +
            +
            0x320xc8TDD_VCO_TX_ON_2
            +

            TDD Control & Status

            +
            +

            		[23:0]TDD_VCO_TX_ON_2RW0x000000
            +

            The secondary pointer for VCO_TX_ON.

            +
            +
            0x330xccTDD_VCO_TX_OFF_2
            +

            TDD Control & Status

            +
            +

            		[23:0]TDD_VCO_TX_OFF_2RW0x000000
            +

            The secondary pointer for VCO_TX_OFF.

            +
            +
            0x340xd0TDD_RX_ON_2
            +

            TDD Control & Status

            +
            +

            		[23:0]TDD_RX_ON_2RW0x000000
            +

            The secondary pointer for RX_ON.

            +
            +
            0x350xd4TDD_RX_OFF_2
            +

            TDD Control & Status

            +
            +

            		[23:0]TDD_RX_OFF_2RW0x000000
            +

            The secondary pointer for RX_OFF.

            +
            +
            0x360xd8TDD_TX_ON_2
            +

            TDD Control & Status

            +
            +

            		[23:0]TDD_TX_ON_2RW0x000000
            +

            The secondary pointer for TX_ON.

            +
            +
            0x370xdcTDD_TX_OFF_2
            +

            TDD Control & Status

            +
            +

            		[23:0]TDD_TX_OFF_2RW0x000000
            +

            The secondary pointer for TX_OFF.

            +
            +
            0x380xe0TDD_RX_DP_ON_2
            +

            TDD Control & Status

            +
            +

            		[23:0]TDD_RX_DP_ON_2RW0x000000
            +

            The secondary pointer for RX_DP_ON.

            +
            +
            0x390xe4TDD_RX_DP_OFF_2
            +

            TDD Control & Status

            +
            +

            		[23:0]TDD_RX_DP_OFF_2RW0x000000
            +

            The secondary pointer for RX_DP_OFF.

            +
            +
            0x3a0xe8TDD_TX_DP_ON_2
            +

            TDD Control & Status

            +
            +

            		[23:0]TDD_TX_DP_ON_2RW0x000000
            +

            The secondary pointer for TX_DP_ON.

            +
            +
            0x3b0xecTDD_TX_DP_OFF_2
            +

            TDD Control & Status

            +
            +

            		[23:0]TDD_TX_DP_OFF_2RW0x000000
            +

            The secondary pointer for TX_DP_OFF.

            +
            +
            +
            +
            +
            +
            +
            +
            +
            +

            Software Guidelines#

            +

            The software for this IP can be found as part of the FMCOMMS2/3/4/5 +Reference Design at: projects/ad9361 +Linux is supported also using ADI Linux repository.

            +
            +
            +

            References#

            + +
            +
            + + + +
            +
            +   + + +
            + +
            +
            +
            + +
            + + + +
            + ©2024, Analog Devices, Inc. + + | + Made with Sphinx + & Doctools + +
            + + \ No newline at end of file diff --git a/library/axi_ad9467/index.html b/library/axi_ad9467/index.html index 15e771663b..e0eb2d5ca6 100644 --- a/library/axi_ad9467/index.html +++ b/library/axi_ad9467/index.html @@ -19,7 +19,7 @@ - + @@ -172,12 +172,15 @@
          • IP Cores

            • Block Diagram#

            -AXI AD9467 block diagram
            +AXI AD9467 block diagram

            Configuration Parameters#

            @@ -2272,7 +2275,7 @@

            References   - +

            diff --git a/library/axi_ad9671/index.html b/library/axi_ad9671/index.html index fd1af208e6..9ac3476d1f 100644 --- a/library/axi_ad9671/index.html +++ b/library/axi_ad9671/index.html @@ -171,12 +171,15 @@
          • IP Cores

            • Block Diagram#

            -AXI AD9671 block diagram +AXI AD9671 block diagram

            Configuration Parameters#

            diff --git a/library/axi_ad9783/index.html b/library/axi_ad9783/index.html index 144093545a..01598d66c7 100644 --- a/library/axi_ad9783/index.html +++ b/library/axi_ad9783/index.html @@ -19,7 +19,7 @@ - + @@ -182,12 +182,15 @@
          • IP Cores

            • Configuration Parameters#

            @@ -2210,7 +2213,7 @@

            References   - + diff --git a/library/axi_ad9963/index.html b/library/axi_ad9963/index.html new file mode 100644 index 0000000000..fbd6fcd96f --- /dev/null +++ b/library/axi_ad9963/index.html @@ -0,0 +1,3612 @@ + + + + + + + + AXI AD9963 — HDL documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
            +
            + + + +
            +
            + + +
            +
            + +
            + +
            + + +
            + + Evaluation Boards + University Program + HDL + no-OS + Hardware Python Interfaces + Precision Converters Firmware + Doctools + Precision Toolbox + + +
            +
            +
            +
            +
            On this page
            + +
            + +
            +
            + + + + +
            +
            +
            +
            + +
            +

            AXI AD9963#

            +

            The AXI AD9963 IP core +can be used to interface the AD9963 chip. +It features a dual 12 bit ADC working up to 100MSPS and a dual 12 bit DAC with up +to 170MSPS. It also features a DLL which can provide clock for both the ADC +and the DAC path.

            +

            More about the generic framework interfacing ADCs can be read in Generic AXI ADC +and interfacing DACs in Generic AXI DAC.

            +
            +

            Features#

            +
              +

            • AXI Lite control/status interface

              • +

            • PRBS monitoring

              • +

            • Hardware DC filtering

              • +

            • IQ/Scale correction

              • +

            • Internal DDS

              • +

            • Programmable line delays

              • +

            • Supports AMD Xilinx devices

              • +
            +
            +
            +

            Files#

            +
            + + + + + + + + + + + + + + + + + + + + + + + +

            Name

            Description

            library/axi_ad9963/axi_ad9963.v

            Verilog source for the AXI AD9963.

            library/common/up_adc_common.v

            Verilog source for the ADC Common regmap.

            library/common/up_adc_channel.v

            Verilog source for the ADC Channel regmap.

            library/common/up_dac_common.v

            Verilog source for the DAC Common regmap.

            library/common/up_dac_channel.v

            Verilog source for the DAC Channel regmap.

            +
            +
            +
            +

            Block Diagram#

            +AXI AD9963 block diagram
            +
            +

            Configuration Parameters#

            +
            +
            + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

            Name

            Description

            Default Value

            Choices/Range

            ID
            +

            Core ID should be unique for each IP in the system

            +
            +            		0

            FPGA_TECHNOLOGY
            +

            Used to select between devices.

            +
            +            		0

            Unknown (0), 7series (1), ultrascale (2), ultrascale+ (3), versal (4)

            FPGA_FAMILY

            Fpga Family.

            		0

            Unknown (0), artix (1), kintex (2), virtex (3), zynq (4), versalprime (5), versalaicore (6), versalpremium (7)

            SPEED_GRADE

            Speed Grade.

            		0

            Unknown (0), -1 (10), -1L (11), -1H (12), -1HV (13), -1LV (14), -2 (20), -2L (21), -2LV (22), -2MP (23), -2LVC (24), -2LVI (25), -3 (30)

            DEV_PACKAGE

            Dev Package.

            		0

            Unknown (0), rf (1), fl (2), ff (3), fb (4), hc (5), fh (6), cs (7), cp (8), ft (9), fg (10), sb (11), rb (12), rs (13), cl (14), sf (15), ba (16), fa (17), fs (18), fi (19), vs (20), ls (21)

            ADC_IODELAY_ENABLE
            +

            Enable IODELAY for tuning the TRX interface

            +
            +            		0

            IO_DELAY_GROUP
            +

            The delay group name which is set for the delay controller

            +
            +            		dev_if_delay_group

            IODELAY_ENABLE

            Iodelay Enable.

            		0

            DAC_DDS_TYPE

            Dac Dds Type.

            		1

            DAC_DDS_CORDIC_DW

            Dac Dds Cordic Dw.

            		14

            DAC_DDS_CORDIC_PHASE_DW

            Dac Dds Cordic Phase Dw.

            		13

            DAC_DATAPATH_DISABLE
            +

            Disable DAC processing blocks. Disables DDS

            +
            +            		0

            ADC_USERPORTS_DISABLE
            +

            Disable ADC userports

            +
            +            		0

            ADC_DATAFORMAT_DISABLE
            +

            Disable ADC data format processing block

            +
            +            		0

            ADC_DCFILTER_DISABLE
            +

            Disable ADC dc filtering processing block

            +
            +            		0

            ADC_IQCORRECTION_DISABLE
            +

            Disable ADC IQ corection processing block

            +
            +            		0

            ADC_SCALECORRECTION_ONLY
            +

            If IQ correction block is enabled and only the scale needs to be corrected, this should be set to 1

            +
            +            		1

            DELAY_REFCLK_FREQUENCY

            Delay Refclk Frequency.

            		200

            +
            +
            +
            +
            +

            Interface#

            +
            +
            +
            +
            + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

            Physical Port

            Logical Port

            Direction

            Dependency

            s_axi_awaddrAWADDR

            in [15:0]

            s_axi_awprotAWPROT

            in [2:0]

            s_axi_awvalidAWVALID

            in

            s_axi_awreadyAWREADY

            out

            s_axi_wdataWDATA

            in [31:0]

            s_axi_wstrbWSTRB

            in [3:0]

            s_axi_wvalidWVALID

            in

            s_axi_wreadyWREADY

            out

            s_axi_brespBRESP

            out [1:0]

            s_axi_bvalidBVALID

            out

            s_axi_breadyBREADY

            in

            s_axi_araddrARADDR

            in [15:0]

            s_axi_arprotARPROT

            in [2:0]

            s_axi_arvalidARVALID

            in

            s_axi_arreadyARREADY

            out

            s_axi_rdataRDATA

            out [31:0]

            s_axi_rrespRRESP

            out [1:0]

            s_axi_rvalidRVALID

            out

            s_axi_rreadyRREADY

            in

            +
            +
            +
            +
            +
            +
            +
            +
            + + + + + + + + + + + + + + + +

            Physical Port

            Logical Port

            Direction

            Dependency

            s_axi_aclkCLK

            in

            +
            +
            +
            +
            +
            +
            +
            +
            + + + + + + + + + + + + + + + +

            Physical Port

            Logical Port

            Direction

            Dependency

            s_axi_aresetnRST

            in

            +
            +
            +
            +
            +
            +
            +
            +
            + + + + + + + + + + + + + + + +

            Physical Port

            Logical Port

            Direction

            Dependency

            trx_clkCLK

            in

            +
            +
            +
            +
            +
            +
            +
            +
            + + + + + + + + + + + + + + + +

            Physical Port

            Logical Port

            Direction

            Dependency

            tx_clkCLK

            in

            +
            +
            +
            +
            +
            +
            +
            +
            + + + + + + + + + + + + + + + +

            Physical Port

            Logical Port

            Direction

            Dependency

            delay_clkCLK

            in

            		ADC_IODELAY_ENABLE = 1
            +
            +
            +
            +
            +
            +
            +
            +
            + + + + + + + + + + + + + + + +

            Physical Port

            Logical Port

            Direction

            Dependency

            adc_clkCLK

            out

            +
            +
            +
            +
            +
            +
            +
            +
            + + + + + + + + + + + + + + + +

            Physical Port

            Logical Port

            Direction

            Dependency

            adc_rstRST

            out

            +
            +
            +
            +
            +
            +
            +
            +
            + + + + + + + + + + + + + + + +

            Physical Port

            Logical Port

            Direction

            Dependency

            dac_clkCLK

            out

            +
            +
            +
            +
            +
            +
            +
            +
            + + + + + + + + + + + + + + + +

            Physical Port

            Logical Port

            Direction

            Dependency

            dac_rstRST

            out

            +
            +
            +
            +
            +
            +
            +
            +
            + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

            Physical Port

            Direction

            Dependency

            Description

            trx_iq

            in

            +

            CMOS input channel selection

            +
            +
            trx_data

            in [11:0]

            +

            CMOS input data

            +
            +
            tx_iq

            out

            +

            CMOS output channel selection

            +
            +
            tx_data

            out [11:0]

            +

            CMOS output data

            +
            +
            dac_sync_in

            in

            +

            DAC synchronization signal. It is generated by the master core and used by all the cores in the system. Only one of the IPs should be master

            +
            +
            dac_sync_out

            out

            +

            DAC synchronization signal. It is generated by the master core and used by all the cores in the system. Only one of the cores should be master

            +
            +
            adc_enable_i

            out

            +

            Set when the channel I is enabled, activated by software

            +
            +
            adc_valid_i

            out

            +

            Set when valid data is available on the channel I

            +
            +
            adc_data_i

            out [15:0]

            +

            Channel I data bus

            +
            +
            adc_enable_q

            out

            +

            Set when the channel Q is enabled, activated by software

            +
            +
            adc_valid_q

            out

            +

            Set when valid data is available on the channel Q

            +
            +
            adc_data_q

            out [15:0]

            +

            Channel Q data bus

            +
            +
            adc_dovf

            in

            +

            Data overflow input, from the DMA

            +
            +
            dac_enable_i

            out

            +

            Set when the channel I is enabled, activated by software

            +
            +
            dac_valid_i

            out

            +

            Set when valid data is available on the channel I

            +
            +
            dac_data_i

            in [15:0]

            +

            Channel I data bus

            +
            +
            dma_valid_i

            in

            dac_enable_q

            out

            +

            Set when the channel Q is enabled, activated by software

            +
            +
            dac_valid_q

            out

            +

            Set when valid data is available on the channel Q

            +
            +
            dac_data_q

            in [15:0]

            +

            Channel Q data bus

            +
            +
            dma_valid_q

            in

            dac_dunf

            in

            +

            Data underflow input from the DMA

            +
            +
            +
            +
            +
            +
            +
            +
            +

            Detailed Description#

            +

            The TRX (ADC) interface is set at 100 MSPS, full duplex mode, double data rate +(DDR), two channels. The clock comes from the AD9963 chip.

            +

            The TX (DAC) interface works at 75MSPS data rate with interpolation by 2 on the +AD9963 chip. The DAC path inside AD9963 chip works at 150MHz, pushing part of +the spurs outside the 100MHz bandwidth. The design assumes that the 75MHz clock +is not available in the FPGA. In order to reduce the number of PLL used in the +FPGA, we are using AD9963 and a BUFR (divide by 2) to generate this clock. When +the clock is generated by AD9963, DDR transfer is not available. The TX +interface works at 150 MHz, SDR.

            +
            +
            +

            Register Map#

            +

            The register map of the core contains instances of several generic register maps +like ADC common, ADC channel, DAC common, DAC channel etc. The following table +presents the base addresses of each instance, after that can be found the +detailed description of each generic register map. The absolute address of a +register should be calculated by adding the instance base address to the +registers relative address.

            +
            + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
            Register Map base addresses for axi_ad9361#

            DWORD

            BYTE

            Name

            Description

            0x0000

            0x0000

            BASE

            See the Base table for more details.

            0x0000

            0x0000

            RX COMMON

            See the ADC Common table for more details.

            0x0000

            0x0000

            RX CHANNELS

            See the ADC Channel table for more details.

            0x1000

            0x4000

            TX COMMON

            See the DAC Common table for more details.

            0x1000

            0x4000

            TX CHANNELS

            See the DAC Channel table for more details.

            +
            +
            +
            +
            +
            +
            + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

            DWORD

            BYTE

            Reg Name

            Description

            BITS

            Field Name

            Type

            Default Value

            Description

            0x00x0VERSION
            +

            Version and Scratch Registers

            +
            +

            		[31:0]VERSIONRO0x00000000
            +

            Version number. Unique to all cores.

            +
            +
            0x10x4ID
            +

            Version and Scratch Registers

            +
            +

            		[31:0]IDRO0x00000000
            +

            Instance identifier number.

            +
            +
            0x20x8SCRATCH
            +

            Version and Scratch Registers

            +
            +

            		[31:0]SCRATCHRW0x00000000
            +

            Scratch register.

            +
            +
            0x30xcCONFIG
            +

            Version and Scratch Registers

            +
            +

            		[0:0]IQCORRECTION_DISABLERO0x0
            +

            If set, indicates that the IQ Correction module was not implemented. (as a result of a configuration of the IP instance)

            +
            +

            		[1:1]DCFILTER_DISABLERO0x0
            +

            If set, indicates that the DC Filter module was not implemented. (as a result of a configuration of the IP instance)

            +
            +

            		[2:2]DATAFORMAT_DISABLERO0x0
            +

            If set, indicates that the Data Format module was not implemented. (as a result of a configuration of the IP instance)

            +
            +

            		[3:3]USERPORTS_DISABLERO0x0
            +

            If set, indicates that the logic related to the User Data Format (e.g. decimation) was not implemented. (as a result of a configuration of the IP instance)

            +
            +

            		[4:4]MODE_1R1TRO0x0
            +

            If set, indicates that the core was implemented in 1 channel mode. (e.g. refer to AD9361 data sheet)

            +
            +

            		[5:5]DELAY_CONTROL_DISABLERO0x0
            +

            If set, indicates that the delay control is disabled for this IP. (as a result of a configuration of the IP instance)

            +
            +

            		[6:6]DDS_DISABLERO0x0
            +

            If set, indicates that the DDS is disabled for this IP. (as a result of a configuration of the IP instance)

            +
            +

            		[7:7]CMOS_OR_LVDS_NRO0x0
            +

            CMOS or LVDS mode is used for the interface. (as a result of a configuration of the IP instance)

            +
            +

            		[8:8]PPS_RECEIVER_ENABLERO0x0
            +

            If set, indicates the PPS receiver is enabled. (as a result of a configuration of the IP instance)

            +
            +

            		[9:9]SCALECORRECTION_ONLYRO0x0
            +

            If set, indicates that the IQ Correction module implements only scale correction. IQ correction must be enabled. (as a result of a configuration of the IP instance)

            +
            +

            		[12:12]EXT_SYNCRO0x0
            +

            If set the transport layer cores (ADC/DAC) have implemented the support for external synchronization signal.

            +
            +

            		[13:13]RD_RAW_DATARO0x0
            +

            If set, the ADC has the capability to read raw data in register CHAN_RAW_DATA from adc_channel.

            +
            +
            0x40x10PPS_IRQ_MASK
            +

            PPS Interrupt mask

            +
            +

            		[0:0]PPS_IRQ_MASKRW0x1
            +

            Mask bit for the 1PPS receiver interrupt

            +
            +
            0x70x1cFPGA_INFO
            +

            FPGA device information library/scripts/adi_intel_device_info_enc.tcl (Intel encoded values) library/scripts/adi_xilinx_device_info_enc.tcl (Xilinx encoded values)

            +
            +

            		[31:24]FPGA_TECHNOLOGYRO0x00
            +

            Encoded value describing the technology/generation of the FPGA device (arria 10/7series)

            +
            +

            		[23:16]FPGA_FAMILYRO0x00
            +

            Encoded value describing the family variant of the FPGA device(e.g., SX, GX, GT or zynq, kintex, virtex)

            +
            +

            		[15:8]SPEED_GRADERO0x00
            +

            Encoded value describing the FPGA’s speed-grade

            +
            +

            		[7:0]DEV_PACKAGERO0x00
            +

            Encoded value describing the device package. The package might affect high-speed interfaces

            +
            +
            +
            +
            +
            +
            +
            +
            +
            +
            +
            +
            + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

            DWORD

            BYTE

            Reg Name

            Description

            BITS

            Field Name

            Type

            Default Value

            Description

            0x100x40RSTN
            +

            ADC Interface Control & Status

            +
            +

            		[2:2]CE_NRW0x0
            +

            Clock enable, default is enabled(0x0). An inverse version of the signal is exported out of the module to control clock enables

            +
            +

            		[1:1]MMCM_RSTNRW0x0
            +

            MMCM reset only (required for DRP access). Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.

            +
            +

            		[0:0]RSTNRW0x0
            +

            Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.

            +
            +
            0x110x44CNTRL
            +

            ADC Interface Control & Status

            +
            +

            		[16:16]SDR_DDR_NRW0x0
            +

            Interface type (1 represents SDR, 0 represents DDR)

            +
            +

            		[15:15]SYMB_OPRW0x0
            +

            Select symbol data format mode (0x1)

            +
            +

            		[14:14]SYMB_8_16BRW0x0
            +

            Select number of bits for symbol format mode (1 represents 8b, 0 represents 16b)

            +
            +

            		[12:8]NUM_LANESRW0x00
            +

            Number of active lanes (1 : CSSI 1-lane, LSSI 1-lane, 2 : LSSI 2-lane, 4 : CSSI 4-lane). For AD7768, AD7768-4 and AD777x number of active lanes : 1/2/4/8 where supported.

            +
            +

            		[3:3]SYNCRW0x0
            +

            Initialize synchronization between multiple ADCs

            +
            +

            		[2:2]R1_MODERW0x0
            +

            Select number of RF channels 1 (0x1) or 2 (0x0).

            +
            +

            		[1:1]DDR_EDGESELRW0x0
            +

            Select rising edge (0x0) or falling edge (0x1) for the first part of a sample (if applicable) followed by the successive edges for the remaining parts. This only controls how the sample is delineated from the incoming data post DDR registers.

            +
            +

            		[0:0]PIN_MODERW0x0
            +

            Select interface pin mode to be clock multiplexed (0x1) or pin multiplexed (0x0). In clock multiplexed mode, samples are received on alternative clock edges. In pin multiplexed mode, samples are interleaved or grouped on the pins at the same clock edge.

            +
            +
            0x120x48CNTRL_2
            +

            ADC Interface Control & Status

            +
            +

            		[1:1]EXT_SYNC_ARMRW0x0
            +

            Setting this bit will arm the trigger mechanism sensitive to an external sync signal. Once the external sync signal goes high it synchronizes channels within a ADC, and across multiple instances. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.

            +
            +

            		[2:2]EXT_SYNC_DISARMRW0x0
            +

            Setting this bit will disarm the trigger mechanism sensitive to an external sync signal. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.

            +
            +

            		[8:8]MANUAL_SYNC_REQUESTRW0x0
            +

            Setting this bit will issue an external sync event if it is hooked up inside the fabric. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.

            +
            +
            0x130x4cCNTRL_3
            +

            ADC Interface Control & Status

            +
            +

            		[8:8]CRC_ENRW0x0
            +

            Setting this bit will enable the CRC generation.

            +
            +

            		[7:0]CUSTOM_CONTROLRW0x00
            +

            Select output format decode mode.(for ADAQ8092: bit 0 - enables digital output randomizer decode , bit 1 - enables alternate bit polarity decode).

            +
            +
            0x150x54CLK_FREQ
            +

            ADC Interface Control & Status

            +
            +

            		[31:0]CLK_FREQRO0x00000000
            +

            Interface clock frequency. This is relative to the processor clock and in many cases is 100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be the same as the interface clock- software must consider device specific implementation parameters to calculate the final sampling clock.

            +
            +
            0x160x58CLK_RATIO
            +

            ADC Interface Control & Status

            +
            +

            		[31:0]CLK_RATIORO0x00000000
            +

            Interface clock ratio - as a factor actual received clock. This is implementation specific and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr).

            +
            +
            0x170x5cSTATUS
            +

            ADC Interface Control & Status

            +
            +

            		[4:4]ADC_CTRL_STATUSRO0x0
            +

            If set, indicates that the device’​s register data is available on the data bus.

            +
            +

            		[3:3]PN_ERRRO0x0
            +

            If set, indicates pn error in one or more channels.

            +
            +

            		[2:2]PN_OOSRO0x0
            +

            If set, indicates pn oos in one or more channels.

            +
            +

            		[1:1]OVER_RANGERO0x0
            +

            If set, indicates over range in one or more channels.

            +
            +

            		[0:0]STATUSRO0x0
            +

            Interface status, if set indicates no errors. If not set, there are errors, software may try resetting the cores.

            +
            +
            0x180x60DELAY_CNTRL
            +

            ADC Interface Control & Status(‘’Deprecated from version 9’’)

            +
            +

            		[17:17]DELAY_SELRW0x0
            +

            Delay select, a 0x0 to 0x1 transition in this register initiates a delay access controlled by the registers below.

            +
            +

            		[16:16]DELAY_RWNRW0x0
            +

            Delay read (0x1) or write (0x0), the delay is accessed directly (no increment or decrement) with an address corresponding to each pin, and data corresponding to the total delay.

            +
            +

            		[15:8]DELAY_ADDRESSRW0x00
            +

            Delay address, the range depends on the interface pins, data pins are usually at the lower range.

            +
            +

            		[4:0]DELAY_WDATARW0x00
            +

            Delay write data, a value of 1 corresponds to (1/200)ns for most devices.

            +
            +
            0x190x64DELAY_STATUS
            +

            ADC Interface Control & Status(‘’Deprecated from version 9’’)

            +
            +

            		[9:9]DELAY_LOCKEDRO0x0
            +

            Indicates delay locked (0x1) state. If this bit is read 0x0, delay control has failed to calibrate the elements.

            +
            +

            		[8:8]DELAY_STATUSRO0x0
            +

            If set, indicates busy status (access pending). The read data may not be valid if this bit is set.

            +
            +

            		[4:0]DELAY_RDATARO0x00
            +

            Delay read data, current delay value in the elements

            +
            +
            0x1a0x68SYNC_STATUS
            +

            ADC Synchronization Status register

            +
            +

            		[0:0]ADC_SYNCRO0x0
            +

            ADC synchronization status. Will be set to 1 after the synchronization has been completed or while waiting for the synchronization signal in JESD204 systems.

            +
            +
            0x1c0x70DRP_CNTRL
            +

            ADC Interface Control & Status

            +
            +

            		[28:28]DRP_RWNRW0x0
            +

            DRP read (0x1) or write (0x0) select (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).

            +
            +

            		[27:16]DRP_ADDRESSRW0x000
            +

            DRP address, designs that contain more than one DRP accessible primitives have selects based on the most significant bits (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).

            +
            +

            		[15:0]RESERVEDRO0x0000
            +

            Reserved for backward compatibility.

            +
            +
            0x1d0x74DRP_STATUS
            +

            ADC Interface Control & Status

            +
            +

            		[17:17]DRP_LOCKEDRO0x0
            +

            If set indicates that the DRP has been locked.

            +
            +

            		[16:16]DRP_STATUSRO0x0
            +

            If set indicates busy (access pending). The read data may not be valid if this bit is set (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).

            +
            +

            		[15:0]RESERVEDRO0x0000
            +

            Reserved for backward compatibility.

            +
            +
            0x1e0x78DRP_WDATA
            +

            ADC DRP Write Data

            +
            +

            		[15:0]DRP_WDATARW0x0000
            +

            DRP write data (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).

            +
            +
            0x1f0x7cDRP_RDATA
            +

            ADC DRP Read Data

            +
            +

            		[15:0]DRP_RDATARO0x0000
            +

            DRP read data (does not include GTX lanes).

            +
            +
            0x200x80ADC_CONFIG_WR
            +

            ADC Write Configuration ​Data

            +
            +

            		[31:0]ADC_CONFIG_WRRW0x00000000
            +

            Custom ​Write to the available registers.

            +
            +
            0x210x84ADC_CONFIG_RD
            +

            ADC Read Configuration ​Data

            +
            +

            		[31:0]ADC_CONFIG_RDRO0x00000000
            +

            Custom read of the available registers.

            +
            +
            0x220x88UI_STATUS
            +

            User Interface Status

            +
            +

            		[2:2]UI_OVFRW1C0x0
            +

            User Interface overflow. If set, indicates an overflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.

            +
            +

            		[1:1]UI_UNFRW1C0x0
            +

            User Interface underflow. If set, indicates an underflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.

            +
            +

            		[0:0]UI_RESERVEDRW1C0x0
            +

            Reserved for backward compatibility.

            +
            +
            0x230x8cADC_CONFIG_CTRL
            +

            ADC RD/WR configuration

            +
            +

            		[31:0]ADC_CONFIG_CTRLRW0x00000000
            +

            Control RD/WR requests to the device’​s register map: bit 1 - RD (‘b1) , WR (‘b0), bit 0 - enable WR/RD operation.

            +
            +
            0x280xa0USR_CNTRL_1
            +

            ADC Interface Control & Status

            +
            +

            		[7:0]USR_CHANMAXRW0x00
            +

            This indicates the maximum number of inputs for the channel data multiplexers. User may add different processing modules post data capture as another input to this common multiplexer. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

            +
            +
            0x290xa4ADC_START_CODE
            +

            ADC Synchronization start word

            +
            +

            		[31:0]ADC_START_CODERW0x00000000
            +

            This sets the startcode that is used by the ADCs for synchronization NOT-APPLICABLE if START_CODE_DISABLE is set (0x1).

            +
            +
            0x2e0xb8ADC_GPIO_IN
            +

            ADC GPIO inputs

            +
            +

            		[31:0]ADC_GPIO_INRO0x00000000
            +

            This reads auxiliary GPI pins of the ADC core

            +
            +
            0x2f0xbcADC_GPIO_OUT
            +

            ADC GPIO outputs

            +
            +

            		[31:0]ADC_GPIO_OUTRW0x00000000
            +

            This controls auxiliary GPO pins of the ADC core NOT-APPLICABLE if GPIO_DISABLE is set (0x1).

            +
            +
            0x300xc0PPS_COUNTER
            +

            PPS Counter register

            +
            +

            		[31:0]PPS_COUNTERRO0x00000000
            +

            Counts the core clock cycles (can be a device clock or interface clock) between two 1PPS pulse.

            +
            +
            0x310xc4PPS_STATUS
            +

            PPS Status register

            +
            +

            		[0:0]PPS_STATUSRO0x0
            +

            If this bit is asserted there is no incomming 1PPS signal. Maybe the source is out of sync or it’s not active.

            +
            +
            +
            +
            +
            +
            +
            +
            +
            +
            +
            +
            + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

            DWORD

            BYTE

            Reg Name

            Description

            BITS

            Field Name

            Type

            Default Value

            Description

            0x100 + 0x16*n0x400 + 0x58*nCHAN_CNTRLn
            +

            ADC Interface Control & Status Where n is from 0 to 15.

            +
            +

            		[11:11]ADC_LB_OWRRW0x0
            +

            If set, forces ADC_DATA_SEL to 1, enabling data loopback

            +
            +

            		[10:10]ADC_PN_SEL_OWRRW0x0
            +

            If set, forces ADC_PN_SEL to 0x9, device specific pn (e.g. ad9361) If both ADC_PN_TYPE_OWR and ADC_PN_SEL_OWR are set, they are ignored

            +
            +

            		[9:9]IQCOR_ENBRW0x0
            +

            if set, enables IQ correction or scale correction. NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).

            +
            +

            		[8:8]DCFILT_ENBRW0x0
            +

            if set, enables DC filter (to disable DC offset, set offset value to 0x0). NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1).

            +
            +

            		[6:6]FORMAT_SIGNEXTRW0x0
            +

            if set, enables sign extension (applicable only in 2’s complement mode). The data is always sign extended to the nearest byte boundary. NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1).

            +
            +

            		[5:5]FORMAT_TYPERW0x0
            +

            Select offset binary (0x1) or 2’s complement (0x0) data type. This sets the incoming data type and is required by the post processing modules for any data conversion. NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1).

            +
            +

            		[4:4]FORMAT_ENABLERW0x0
            +

            Enable data format conversion (see register bits above). NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1).

            +
            +

            		[3:3]RESERVEDRO0x0
            +

            Reserved for backward compatibility.

            +
            +

            		[2:2]RESERVEDRO0x0
            +

            Reserved for backward compatibility.

            +
            +

            		[1:1]ADC_PN_TYPE_OWRRW0x0
            +

            If set, forces ADC_PN_SEL to 0x1, modified pn23 If both ADC_PN_TYPE_OWR and ADC_PN_SEL_OWR are set, they are ignored

            +
            +

            		[0:0]ENABLERW0x0
            +

            If set, enables channel. A 0x0 to 0x1 transition transfers all the control signals to the respective channel processing module. If a channel is part of a complex signal (I/Q), even channel is the master and the odd channel is the slave. Though a single control is used, both must be individually selected.

            +
            +
            0x101 + 0x16*n0x404 + 0x58*nCHAN_STATUSn
            +

            ADC Interface Control & Status Where n is from 0 to 15.

            +
            +

            		[12:12]CRC_ERRRW1C0x0
            +

            CRC errors. If set, indicates CRC error. Software must first clear this bit before initiating a transfer and monitor afterwards.

            +
            +

            		[11:4]STATUS_HEADERRO0x00
            +

            The status header sent by the ADC.(compatible with AD7768/AD7768-4/AD777x).

            +
            +

            		[2:2]PN_ERRRW1C0x0
            +

            PN errors. If set, indicates spurious mismatches in sync state. This bit is cleared if OOS is set and is only indicates errors when OOS is cleared.

            +
            +

            		[1:1]PN_OOSRW1C0x0
            +

            PN Out Of Sync. If set, indicates an OOS status. OOS is set, if 64 consecutive patterns mismatch from the expected pattern. It is cleared, when 16 consecutive patterns match the expected pattern.

            +
            +

            		[0:0]OVER_RANGERW1C0x0
            +

            If set, indicates over range. Note that over range is independent of the data path, it indicates an over range over a data transfer period. Software must first clear this bit before initiating a transfer and monitor afterwards.

            +
            +
            0x102 + 0x16*n0x408 + 0x58*nCHAN_RAW_DATAn
            +

            ADC Raw Data Reading Where n is from 0 to 15.

            +
            +

            		[31:0]ADC_READ_DATARO0x00000000
            +

            Raw data read from the ADC.

            +
            +
            0x104 + 0x16*n0x410 + 0x58*nCHAN_CNTRLn_1
            +

            ADC Interface Control & Status Where n is from 0 to 15.

            +
            +

            		[31:16]DCFILT_OFFSETRW0x0000
            +

            DC removal (if equipped) offset. This is a 2’s complement number added to the incoming data to remove a known DC offset. NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1).

            +
            +

            		[15:0]DCFILT_COEFFRW0x0000
            +

            DC removal filter (if equipped) coefficient. The format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1).

            +
            +
            0x105 + 0x16*n0x414 + 0x58*nCHAN_CNTRLn_2
            +

            ADC Interface Control & Status Where n is from 0 to 15.

            +
            +

            		[31:16]IQCOR_COEFF_1RW0x0000
            +

            IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the scale value and the format is 1.1.14 (sign, integer and fractional bits). If matrix multiplication is used, this is the channel I coefficient and the format is 1.1.14 (sign, integer and fractional bits). If SCALECORRECTION_ONLY is set, this implements the scale value correction for the current channel with the format 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).

            +
            +

            		[15:0]IQCOR_COEFF_2RW0x0000
            +

            IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the offset value and the format is 2’s complement. If matrix multiplication is used, this is the channel Q coefficient and the format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).

            +
            +
            0x106 + 0x16*n0x418 + 0x58*nCHAN_CNTRLn_3
            +

            ADC Interface Control & Status Where n is from 0 to 15.

            +
            +

            		[19:16]ADC_PN_SELRW0x0
            +

            Selects the PN monitor sequence type (available only if ADC supports it). \ - 0x0: pn9a (device specific, modified pn9) \ - 0x1: pn23a (device specific, modified pn23) \ - 0x4: pn7 (standard O.150) \ - 0x5: pn15 (standard O.150) \ - 0x6: pn23 (standard O.150) \ - 0x7: pn31 (standard O.150) \ - 0x9: pnX (device specific, e.g. ad9361) \ - 0x0A: Nibble ramp (Device specific e.g. adrv9001) \ - 0x0B: 16 bit ramp (Device specific e.g. adrv9001) \

            +
            +

            		[3:0]ADC_DATA_SELRW0x0
            +

            Selects the data source to DMA. 0x0: input data (ADC) 0x1: loopback data (DAC)

            +
            +
            0x108 + 0x16*n0x420 + 0x58*nCHAN_USR_CNTRLn_1
            +

            ADC Interface Control & Status Where n is from 0 to 15.

            +
            +

            		[25:25]USR_DATATYPE_BERO0x0
            +

            The user data type format- if set, indicates big endian (default is little endian). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

            +
            +

            		[24:24]USR_DATATYPE_SIGNEDRO0x0
            +

            The user data type format- if set, indicates signed (2’s complement) data (default is unsigned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

            +
            +

            		[23:16]USR_DATATYPE_SHIFTRO0x00
            +

            The user data type format- the amount of right shift for actual samples within the total number of bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

            +
            +

            		[15:8]USR_DATATYPE_TOTAL_BITSRO0x00
            +

            The user data type format- number of total bits used for a sample. The total number of bits must be an integer multiple of 8 (byte aligned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

            +
            +

            		[7:0]USR_DATATYPE_BITSRO0x00
            +

            The user data type format- number of bits in a sample. This indicates the actual sample data bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

            +
            +
            0x109 + 0x16*n0x424 + 0x58*nCHAN_USR_CNTRLn_2
            +

            ADC Interface Control & Status Where n is from 0 to 15.

            +
            +

            		[31:16]USR_DECIMATION_MRW0x0000
            +

            This holds the user decimation M value of the channel that is currently being selected on the multiplexer above. The total decimation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

            +
            +

            		[15:0]USR_DECIMATION_NRW0x0000
            +

            This holds the user decimation N value of the channel that is currently being selected on the multiplexer above. The total decimation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

            +
            +
            0x10a + 0x16*n0x428 + 0x58*nCHAN_CNTRLn_4
            +

            ADC Interface Control & Status Where n is from 0 to 15.

            +
            +

            		[31:3]RESERVEDRO0x00000000
            +

            Reserved for backward compatibility.

            +
            +

            		[2:0]SOFTSPANRW0x7
            +

            Softspan configuration register.

            +
            +
            +
            +
            +
            +
            +
            +
            +
            +
            +
            +
            + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

            DWORD

            BYTE

            Reg Name

            Description

            BITS

            Field Name

            Type

            Default Value

            Description

            0x100x40RSTN
            +

            DAC Interface Control & Status

            +
            +

            		[2:2]CE_NRW0x0
            +

            Clock enable, default is enabled(0x0). An inverse version of the signal is exported out of the module to control clock enables

            +
            +

            		[1:1]MMCM_RSTNRW0x0
            +

            MMCM reset only (required for DRP access). Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.

            +
            +

            		[0:0]RSTNRW0x0
            +

            Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.

            +
            +
            0x110x44CNTRL_1
            +

            DAC Interface Control & Status

            +
            +

            		[0:0]SYNCRW0x0
            +

            Setting this bit synchronizes channels within a DAC, and across multiple instances. This bit self clears.

            +
            +

            		[1:1]EXT_SYNC_ARMRW0x0
            +

            Setting this bit will arm the trigger mechanism sensitive to an external sync signal. Once the external sync signal goes high it synchronizes channels within a DAC, and across multiple instances. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.

            +
            +

            		[2:2]EXT_SYNC_DISARMRW0x0
            +

            Setting this bit will disarm the trigger mechanism sensitive to an external sync signal. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.

            +
            +

            		[8:8]MANUAL_SYNC_REQUESTRW0x0
            +

            Setting this bit will issue an external sync event if it is hooked up inside the fabric. This bit has an effect only the EXT_SYNC synthesis parameter is set. This bit self clears.

            +
            +
            0x120x48CNTRL_2
            +

            DAC Interface Control & Status

            +
            +

            		[16:16]SDR_DDR_NRW0x0
            +

            Interface type (1 represents SDR, 0 represents DDR)

            +
            +

            		[15:15]SYMB_OPRW0x0
            +

            Select data symbol format mode (0x1)

            +
            +

            		[14:14]SYMB_8_16BRW0x0
            +

            Select number of bits for symbol format mode (1 represents 8b, 0 represents 16b)

            +
            +

            		[12:8]NUM_LANESRW0x00
            +

            Number of active lanes (1 : CSSI 1-lane, LSSI 1-lane, 2 : LSSI 2-lane, 4 : CSSI 4-lane)

            +
            +

            		[7:7]PAR_TYPERW0x0
            +

            Select parity even (0x0) or odd (0x1).

            +
            +

            		[6:6]PAR_ENBRW0x0
            +

            Select parity (0x1) or frame (0x0) mode.

            +
            +

            		[5:5]R1_MODERW0x0
            +

            Select number of RF channels 1 (0x1) or 2 (0x0).

            +
            +

            		[4:4]DATA_FORMATRW0x0
            +

            Select data format 2’s complement (0x0) or offset binary (0x1). NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1).

            +
            +

            		[3:0]RESERVEDNA0x0
            +

            Reserved

            +
            +
            0x130x4cRATECNTRL
            +

            DAC Interface Control & Status

            +
            +

            		[7:0]RATERW0x00
            +

            The effective dac rate (the maximum possible rate is dependent on the interface clock). The samples are generated at 1/RATE of the interface clock.

            +
            +
            0x140x50FRAME
            +

            DAC Interface Control & Status

            +
            +

            		[0:0]FRAMERW0x0
            +

            The use of frame is device specific. Usually setting this bit to 1 generates a FRAME (1 DCI clock period) pulse on the interface. This bit self clears.

            +
            +
            0x150x54STATUS1
            +

            DAC Interface Control & Status

            +
            +

            		[31:0]CLK_FREQRO0x00000000
            +

            Interface clock frequency. This is relative to the processor clock and in many cases is 100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be the same as the interface clock- software must consider device specific implementation parameters to calculate the final sampling clock.

            +
            +
            0x160x58STATUS2
            +

            DAC Interface Control & Status

            +
            +

            		[31:0]CLK_RATIORO0x00000000
            +

            Interface clock ratio - as a factor actual received clock. This is implementation specific and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr).

            +
            +
            0x170x5cSTATUS3
            +

            DAC Interface Control & Status

            +
            +

            		[0:0]STATUSRO0x0
            +

            Interface status, if set indicates no errors. If not set, there are errors, software may try resetting the cores.

            +
            +
            0x180x60DAC_CLKSEL
            +

            DAC Interface Control & Status

            +
            +

            		[0:0]DAC_CLKSELRW0x0
            +

            Allows changing of the clock polarity. Note: its default value is CLK_EDGE_SEL

            +
            +
            0x1a0x68SYNC_STATUS
            +

            DAC Synchronization Status register

            +
            +

            		[0:0]DAC_SYNC_STATUSRO0x0
            +

            DAC synchronization status. Will be set to 1 while waiting for the external synchronization signal This bit has an effect only the EXT_SYNC synthesis parameter is set.

            +
            +
            0x1c0x70DRP_CNTRL
            +

            DRP Control & Status

            +
            +

            		[28:28]DRP_RWNRW0x0
            +

            DRP read (0x1) or write (0x0) select (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).

            +
            +

            		[27:16]DRP_ADDRESSRW0x000
            +

            DRP address, designs that contain more than one DRP accessible primitives have selects based on the most significant bits (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).

            +
            +

            		[15:0]RESERVEDRO0x0000
            +

            Reserved for backwards compatibility

            +
            +
            0x1d0x74DRP_STATUS
            +

            DAC Interface Control & Status

            +
            +

            		[17:17]DRP_LOCKEDRO0x0
            +

            If set indicates the MMCM/PLL is locked

            +
            +

            		[16:16]DRP_STATUSRO0x0
            +

            If set indicates busy (access pending). The read data may not be valid if this bit is set (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).

            +
            +

            		[15:0]RESERVEDRO0x0000
            +

            Reserved for backwards compatibility

            +
            +
            0x1e0x78DRP_WDATA
            +

            DAC Interface Control & Status

            +
            +

            		[15:0]DRP_WDATARW0x0000
            +

            DRP write data (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).

            +
            +
            0x1f0x7cDRP_RDATA
            +

            DAC Interface Control & Status

            +
            +

            		[15:0]DRP_RDATARO0x0000
            +

            DRP read data (does not include GTX lanes). NOT-APPLICABLE if DRP_DISABLE is set (0x1).

            +
            +
            0x200x80DAC_CUSTOM_RD
            +

            DAC Read Configuration Data

            +
            +

            		[31:0]DAC_CUSTOM_RDRO0x00000000
            +

            Custom Read of the available registers.

            +
            +
            0x210x84DAC_CUSTOM_WR
            +

            DAC Write Configuration Data

            +
            +

            		[31:0]DAC_CUSTOM_WRRW0x00000000
            +

            Custom Write of the available registers.

            +
            +
            0x220x88UI_STATUS
            +

            User Interface Status

            +
            +

            		[4:4]IF_BUSYRO0x0
            +

            Interface busy. If set, indicates that the data interface is busy.

            +
            +

            		[1:1]UI_OVFRW1C0x0
            +

            User Interface overflow. If set, indicates an overflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.

            +
            +

            		[0:0]UI_UNFRW1C0x0
            +

            User Interface underflow. If set, indicates an underflow occurred during data transfer at the user interface (FIFO interface). Software must write a 0x1 to clear this register bit.

            +
            +
            0x230x8cDAC_CUSTOM_CTRL
            +

            DAC Control Configuration Data

            +
            +

            		[31:0]DAC_CUSTOM_CTRLRW0x00000000
            +

            Custom Control of the available registers.

            +
            +
            0x280xa0USR_CNTRL_1
            +

            DAC User Control & Status

            +
            +

            		[7:0]USR_CHANMAXRW0x00
            +

            This indicates the maximum number of inputs for the channel data multiplexers. User may add different processing modules as inputs to the dac. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

            +
            +
            0x2e0xb8DAC_GPIO_IN
            +

            DAC GPIO inputs

            +
            +

            		[31:0]DAC_GPIO_INRO0x00000000
            +

            This reads auxiliary GPI pins of the DAC core

            +
            +
            0x2f0xbcDAC_GPIO_OUT
            +

            DAC GPIO outputs

            +
            +

            		[31:0]DAC_GPIO_OUTRW0x00000000
            +

            This controls auxiliary GPO pins of the DAC core NOT-APPLICABLE if GPIO_DISABLE is set (0x1).

            +
            +
            +
            +
            +
            +
            +
            +
            +
            +
            +
            +
            + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

            DWORD

            BYTE

            Reg Name

            Description

            BITS

            Field Name

            Type

            Default Value

            Description

            0x100 + 0x16*n0x400 + 0x58*nCHAN_CNTRLn_1
            +

            DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

            +
            +

            		[21:16]DDS_PHASE_DWRO0x00
            +

            The DDS phase data width offers the HDL parameter configuration with the same name. This information is used in conjunction with CHAN_CNTRL_9 and CHAN_CNTRL_10. More info at AD Direct Digital Synthesis.

            +
            +

            		[15:0]DDS_SCALE_1RW0x0000
            +

            The DDS scale for tone 1. Sets the amplitude of the tone. The format is 1.1.14 fixed point (signed, integer, fractional). The DDS in general runs on 16-bits, note that if you do use both channels and set both scale to 0x4000, it is over-range. The final output is (tone_1_fullscale * scale_1) + (tone_2_fullscale * scale_2). NOT-APPLICABLE if DDS_DISABLE is set (0x1).

            +
            +
            0x101 + 0x16*n0x404 + 0x58*nCHAN_CNTRLn_2
            +

            DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

            +
            +

            		[31:16]DDS_INIT_1RW0x0000
            +

            The DDS phase initialization for tone 1. Sets the initial phase offset of the tone. NOT-APPLICABLE if DDS_DISABLE is set (0x1).

            +
            +

            		[15:0]DDS_INCR_1RW0x0000
            +

            Sets the frequency of the phase accumulator. Its value can be calculated by \(INCR = (f_{out} * 2^{16}) * clkratio / f_{if}\); where f_out is the generated output frequency, and f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. If DDS_PHASE_DW is greater than 16(from CHAN_CNTRL_1), the phase increment for tone 1 is extended in CHAN_CNTRL_9. NOT-APPLICABLE if DDS_DISABLE is set (0x1).

            +
            +
            0x102 + 0x16*n0x408 + 0x58*nCHAN_CNTRLn_3
            +

            DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

            +
            +

            		[15:0]DDS_SCALE_2RW0x0000
            +

            The DDS scale for tone 2. Sets the amplitude of the tone. The format is 1.1.14 fixed point (signed, integer, fractional). The DDS in general runs on 16-bits, note that if you do use both channels and set both scale to 0x4000, it is over-range. The final output is (tone_1_fullscale * scale_1) + (tone_2_fullscale * scale_2). NOT-APPLICABLE if DDS_DISABLE is set (0x1).

            +
            +
            0x103 + 0x16*n0x40c + 0x58*nCHAN_CNTRLn_4
            +

            DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

            +
            +

            		[31:16]DDS_INIT_2RW0x0000
            +

            The DDS phase initialization for tone 2. Sets the initial phase offset of the tone. If DDS_PHASE_DW is greater than 16(from CHAN_CNTRL_1), the phase init for tone 2 is extended in CHAN_CNTRL_10. NOT-APPLICABLE if DDS_DISABLE is set (0x1).

            +
            +

            		[15:0]DDS_INCR_2RW0x0000
            +

            Sets the frequency of the phase accumulator. Its value can be calculated by \(INCR = (f_{out} * 2^{16}) * clkratio / f_{if}\); where f_out is the generated output frequency, and f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. If DDS_PHASE_DW is greater than 16(from CHAN_CNTRL_1), the phase increment for tone 2 is extended in CHAN_CNTRL_10. NOT-APPLICABLE if DDS_DISABLE is set (0x1).

            +
            +
            0x104 + 0x16*n0x410 + 0x58*nCHAN_CNTRLn_5
            +

            DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

            +
            +

            		[31:16]DDS_PATT_2RW0x0000
            +

            The DDS data pattern for this channel.

            +
            +

            		[15:0]DDS_PATT_1RW0x0000
            +

            The DDS data pattern for this channel.

            +
            +
            0x105 + 0x16*n0x414 + 0x58*nCHAN_CNTRLn_6
            +

            DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

            +
            +

            		[2:2]IQCOR_ENBRW0x0
            +

            if set, enables IQ correction. NOT-APPLICABLE if DAC_DP_DISABLE is set (0x1).

            +
            +

            		[1:1]DAC_LB_OWRRW0x0
            +

            If set, forces DAC_DDS_SEL to 0x8, loopback If DAC_LB_OWR and DAC_PN_OWR are both set, they are ignored

            +
            +

            		[0:0]DAC_PN_OWRRW0x0
            +

            IF set, forces DAC_DDS_SEL to 0x09, device specific pnX If DAC_LB_OWR and DAC_PN_OWR are both set, they are ignored

            +
            +
            0x106 + 0x16*n0x418 + 0x58*nCHAN_CNTRLn_7
            +

            DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

            +
            +

            		[3:0]DAC_DDS_SELRW0x0
            +

            Select internal data sources (available only if the DAC supports it). \ - 0x00: internal tone (DDS) \ - 0x01: pattern (SED) \ - 0x02: input data (DMA) \ - 0x03: 0x00 \ - 0x04: inverted pn7 \ - 0x05: inverted pn15 \ - 0x06: pn7 (standard O.150) \ - 0x07: pn15 (standard O.150) \ - 0x08: loopback data (ADC) \ - 0x09: pnX (Device specific e.g. ad9361) \ - 0x0A: Nibble ramp (Device specific e.g. adrv9001) \ - 0x0B: 16 bit ramp (Device specific e.g. adrv9001) \

            +
            +
            0x107 + 0x16*n0x41c + 0x58*nCHAN_CNTRLn_8
            +

            DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

            +
            +

            		[31:16]IQCOR_COEFF_1RW0x0000
            +

            IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the scale value and the format is 1.1.14 (sign, integer and fractional bits). If matrix multiplication is used, this is the channel I coefficient and the format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).

            +
            +

            		[15:0]IQCOR_COEFF_2RW0x0000
            +

            IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the offset value and the format is 2’s complement. If matrix multiplication is used, this is the channel Q coefficient and the format is 1.1.14 (sign, integer and fractional bits). NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).

            +
            +
            0x108 + 0x16*n0x420 + 0x58*nUSR_CNTRLn_3
            +

            DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

            +
            +

            		[25:25]USR_DATATYPE_BERW0x0
            +

            The user data type format- if set, indicates big endian (default is little endian). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

            +
            +

            		[24:24]USR_DATATYPE_SIGNEDRW0x0
            +

            The user data type format- if set, indicates signed (2’s complement) data (default is unsigned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

            +
            +

            		[23:16]USR_DATATYPE_SHIFTRW0x00
            +

            The user data type format- the amount of right shift for actual samples within the total number of bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

            +
            +

            		[15:8]USR_DATATYPE_TOTAL_BITSRW0x00
            +

            The user data type format- number of total bits used for a sample. The total number of bits must be an integer multiple of 8 (byte aligned). NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

            +
            +

            		[7:0]USR_DATATYPE_BITSRW0x00
            +

            The user data type format- number of bits in a sample. This indicates the actual sample data bits. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

            +
            +
            0x109 + 0x16*n0x424 + 0x58*nUSR_CNTRLn_4
            +

            DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

            +
            +

            		[31:16]USR_INTERPOLATION_MRW0x0000
            +

            This holds the user interpolation M value of the channel that is currently being selected on the multiplexer above. The total interpolation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

            +
            +

            		[15:0]USR_INTERPOLATION_NRW0x0000
            +

            This holds the user interpolation N value of the channel that is currently being selected on the multiplexer above. The total interpolation factor is of the form M/N. NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

            +
            +
            0x10a + 0x16*n0x428 + 0x58*nUSR_CNTRLn_5
            +

            DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

            +
            +

            		[0:0]DAC_IQ_MODERW0x0
            +

            Enable complex mode. In this mode the driven data to the DAC must be a sequence of I and Q sample pairs.

            +
            +

            		[1:1]DAC_IQ_SWAPRW0x0
            +

            Allows IQ swapping in complex mode. Only takes effect if complex mode is enabled.

            +
            +
            0x10b + 0x16*n0x42c + 0x58*nCHAN_CNTRLn_9
            +

            DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

            +
            +

            		[31:16]DDS_INIT_1_EXTENDEDRW0x0000
            +

            The extended DDS phase initialization for tone 1. Sets the initial phase offset of the tone. The extended init(phase) value should be calculated according to DDS_PHASE_DW value from CHAN_CNTRL_1 NOT-APPLICABLE if DDS_DISABLE is set (0x1).

            +
            +

            		[15:0]DDS_INCR_1_EXTENDEDRW0x0000
            +

            Sets the frequency of tone 1’s phase accumulator. Its value can be calculated by \(INCR = (f_{out} * 2^{phaseDW}) * clkratio / f_{if}\); Where f_out is the generated output frequency, DDS_PHASE_DW value can be found in CHAN_CNTRL_1 in case DDS_PHASE_DW is not 16, f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. NOT-APPLICABLE if DDS_DISABLE is set (0x1).

            +
            +
            0x10c + 0x16*n0x430 + 0x58*nCHAN_CNTRLn_10
            +

            DAC Channel Control & Status (channel - 0) Where n is from 0 to 15.

            +
            +

            		[31:16]DDS_INIT_2_EXTENDEDRW0x0000
            +

            The extended DDS phase initialization for tone 2. Sets the initial phase offset of the tone. The extended init(phase) value should be calculated according to DDS_PHASE_DW value from CHAN_CNTRL_2 NOT-APPLICABLE if DDS_DISABLE is set (0x1).

            +
            +

            		[15:0]DDS_INCR_2_EXTENDEDRW0x0000
            +

            Sets the frequency of tone 2’s phase accumulator. Its value can be calculated by \(INCR = (f_{out} * 2^{phaseDW}) * clkratio / f_{if}\); Where f_out is the generated output frequency, DDS_PHASE_DW value can be found in CHAN_CNTRL_2 in case DDS_PHASE_DW is not 16, f_if is the frequency of the digital interface, and clock_ratio is the ratio between the sampling clock and the interface clock. NOT-APPLICABLE if DDS_DISABLE is set (0x1).

            +
            +
            +
            +
            +
            +
            +
            +
            +
            +

            Design Guidelines#

            +

            In order to reduce the power and resource utilization, all the unused features +should be disabled.

            +
            +
            +

            Software Guidelines#

            +

            For RX PRBS data, when 2’s complement mode is selected, each new word is the 1 +bit shifted version of the previous word. Steps to do in order to test the PRBS +on the RX path:

            +
              +

            1. Write to AD9963 SPI register 0x51 the value 1, which enables the BIST core..

              2. +

            2. Write to AD9963 SPI register 0x51 the value 7.

              3. +

            3. Read register 0x404 from the AD9361 ADC core (should read value 2 or 6).

              4. +

            4. Write back to register 0x404 from the AD9361 ADC core the value read above

              5. +

            5. Read register 0x404 from the AD9361 ADC core. +It should read 0x0 if the RX path is working correctly for channel 1

              6. +

            6. Perform steps 3-6 with register 0x444. +This will validate the RX path for channel 2.

              7. +
            +

            If the TRX path does not work correctly, the output current on the TRX pins can +be changed by writing to register 0x63.

            +

            The TX interface testing is done by writing 1024 samples of PRBS data and +checking the BIST signature values for both the I and the Q side. Interpolation +should not be active during the BIST testing.

            +
            +
            +

            References#

            + +
            +
            + + + +
            +
            +   + + +
            + +
            +
            +
            + +
            + + + +
            + ©2024, Analog Devices, Inc. + + | + Made with Sphinx + & Doctools + +
            + + \ No newline at end of file diff --git a/library/axi_adaq8092/index.html b/library/axi_adaq8092/index.html index 300d6ca667..b4406bd386 100644 --- a/library/axi_adaq8092/index.html +++ b/library/axi_adaq8092/index.html @@ -19,7 +19,7 @@ - + @@ -172,12 +172,15 @@
          • IP Cores

            • Block Diagram#

            -AXI ADAQ8092 block diagram
            +AXI ADAQ8092 block diagram

            Configuration Parameters#

            @@ -2370,7 +2373,7 @@

            References   - +

            diff --git a/library/axi_adc_decimate/index.html b/library/axi_adc_decimate/index.html index c7fed74fe8..8912215a0c 100644 --- a/library/axi_adc_decimate/index.html +++ b/library/axi_adc_decimate/index.html @@ -169,12 +169,15 @@
          • IP Cores

            • Block Diagram#

            -AXI ADC Decimate block diagram
            +AXI ADC Decimate block diagram

            Configuration Parameters#

            diff --git a/library/axi_adc_trigger/index.html b/library/axi_adc_trigger/index.html index fcaa6452ae..16a235adec 100644 --- a/library/axi_adc_trigger/index.html +++ b/library/axi_adc_trigger/index.html @@ -172,12 +172,15 @@
          • IP Cores

            • Block Diagram#

            -AXI ADC Trigger block diagram
            +AXI ADC Trigger block diagram

            Submodules#

            Block Diagram#

            -AXI CLK Generator block diagram
            +AXI CLK Generator block diagram

            Configuration Parameters#

            diff --git a/library/axi_dac_interpolate/index.html b/library/axi_dac_interpolate/index.html index 7ab51577fb..3edc5f101a 100644 --- a/library/axi_dac_interpolate/index.html +++ b/library/axi_dac_interpolate/index.html @@ -169,12 +169,15 @@
          • IP Cores

            • Block Diagram#

            -AXI DAC Interpolate block diagram
            +AXI DAC Interpolate block diagram

            Configuration Parameters#

            @@ -720,7 +723,7 @@

            Detailed DescriptionAt the end of the filter blocks, there is an arbitrary interpolation zero-order hold block which holds the value for a configurable number of samples.

            The axi_dac_interpolate also controls the data flow, being the middle man -between axi_ad9963: as the main data flow controller (consumer) and the DMA, +between AXI AD9963: as the main data flow controller (consumer) and the DMA, a subordinate in the path. This control is done through registers:

            Block Diagram#

            -AXI DMAC block diagram
            +AXI DMAC block diagram

            Configuration Parameters#

            diff --git a/library/axi_fan_control/index.html b/library/axi_fan_control/index.html index 977374bafa..716e3cc8f3 100644 --- a/library/axi_fan_control/index.html +++ b/library/axi_fan_control/index.html @@ -175,12 +175,15 @@
          • IP Cores

            • Block Diagram#

            -AXI Fan Control block diagram
            +AXI Fan Control block diagram

            Configuration Parameters#

            diff --git a/library/axi_hdmi_rx/index.html b/library/axi_hdmi_rx/index.html index b864899567..b809fed5b7 100644 --- a/library/axi_hdmi_rx/index.html +++ b/library/axi_hdmi_rx/index.html @@ -171,12 +171,15 @@
          • IP Cores

            • Block Diagram#

            -AXI HDMI RX block diagram
            +AXI HDMI RX block diagram

            Configuration Parameters#

            diff --git a/library/axi_hdmi_tx/index.html b/library/axi_hdmi_tx/index.html index eb3751000d..4a77cf1aab 100644 --- a/library/axi_hdmi_tx/index.html +++ b/library/axi_hdmi_tx/index.html @@ -172,12 +172,15 @@
          • IP Cores

            • Block Diagram#

            -AXI HDMI TX block diagram
            +AXI HDMI TX block diagram

            Configuration Parameters#

            diff --git a/library/axi_laser_driver/index.html b/library/axi_laser_driver/index.html index 731728771f..4f17b00e49 100644 --- a/library/axi_laser_driver/index.html +++ b/library/axi_laser_driver/index.html @@ -166,12 +166,15 @@
          • IP Cores

            • Block Diagram#

            -AXI PWM Generator block diagram
            +AXI PWM Generator block diagram

            Configuration Parameters#

            diff --git a/library/axi_sysid/index.html b/library/axi_sysid/index.html index 7797974f41..8561ab76b9 100644 --- a/library/axi_sysid/index.html +++ b/library/axi_sysid/index.html @@ -182,12 +182,15 @@
          • IP Cores

            • Block Diagram#

            -AXI System ID block diagram
            +AXI System ID block diagram

            Configuration Parameters#

            diff --git a/library/axi_tdd/index.html b/library/axi_tdd/index.html index fb76326d51..04f63cb431 100644 --- a/library/axi_tdd/index.html +++ b/library/axi_tdd/index.html @@ -168,12 +168,15 @@
          • IP Cores

            • Block Diagram#

            -Data Offload block diagram
            +Data Offload block diagram

            Configuration Parameters#

            diff --git a/library/i3c_controller/i3c_controller_core.html b/library/i3c_controller/i3c_controller_core.html index 920e1f9b06..f090180e86 100644 --- a/library/i3c_controller/i3c_controller_core.html +++ b/library/i3c_controller/i3c_controller_core.html @@ -164,12 +164,15 @@
          • IP Cores

            • Block Diagram#

            -Template IP block diagram
            +Template IP block diagram

            Configuration Parameters#

            diff --git a/library/util_axis_fifo/index.html b/library/util_axis_fifo/index.html index e7d7080803..f9d05832fa 100644 --- a/library/util_axis_fifo/index.html +++ b/library/util_axis_fifo/index.html @@ -166,12 +166,15 @@
          • IP Cores
            • -
              -

            • ADDRESS_WIDTH_PERSPECTIVE is 0 and FIFO_LIMITED is 0 - This means that the

              • -
            -
            -

            address specified is from the perspective of the Slave interface. Since +is < M_DATA_WIDTH, leading to a smaller FIFO implementation.

            +

          • ADDRESS_WIDTH_PERSPECTIVE is 0 and FIFO_LIMITED is 0 - This means that the +address specified is from the perspective of the Slave interface. Since the limit is disable the FIFO size will remain the same if the S_DATA_WIDTH -is < M_DATA_WIDTH, leading to a bigger FIFO implementation.

            -
            • +is < M_DATA_WIDTH, leading to a bigger FIFO implementation.

            +

          diff --git a/library/util_extract/index.html b/library/util_extract/index.html index 71de7e7f6b..72b5c4203e 100644 --- a/library/util_extract/index.html +++ b/library/util_extract/index.html @@ -164,12 +164,15 @@
        • IP Cores
          • AXI AD3552R
          • AXI AD7606x
            • +
          • AXI AD7616
          • AXI AD7768
          • AXI AD777x
          • AXI AD9265
            • +
          • AXI AD9361
          • AXI AD9467
          • AXI AD9671
          • AXI AD9783
            • +
          • AXI AD9963
          • AXI ADAQ8092
          • AXI ADC Decimate
          • AXI ADC Trigger
            • diff --git a/library/util_mii_to_rmii/index.html b/library/util_mii_to_rmii/index.html index 88dc4e1089..0ed61eaffe 100644 --- a/library/util_mii_to_rmii/index.html +++ b/library/util_mii_to_rmii/index.html @@ -174,12 +174,15 @@
          • IP Cores
            • AXI AD3552R
            • AXI AD7606x
              • +
            • AXI AD7616
            • AXI AD7768
            • AXI AD777x
            • AXI AD9265
              • +
            • AXI AD9361
            • AXI AD9467
            • AXI AD9671
            • AXI AD9783
              • +
            • AXI AD9963
            • AXI ADAQ8092
            • AXI ADC Decimate
            • AXI ADC Trigger
              • @@ -322,7 +325,7 @@

              Files#

              Block Diagram#

              -Util MII to RMII block diagram
              +Util MII to RMII block diagram

              Configuration Parameters#

              diff --git a/library/util_pack/util_cpack2.html b/library/util_pack/util_cpack2.html index 8dde03e4b5..eb8030ce10 100644 --- a/library/util_pack/util_cpack2.html +++ b/library/util_pack/util_cpack2.html @@ -166,12 +166,15 @@
            • IP Cores

              • Block Diagram#

              -Util RFIFO block diagram
              +Util RFIFO block diagram

              Timing Diagram#

              Util RFIFO timing diagram diff --git a/library/util_var_fifo/index.html b/library/util_var_fifo/index.html index 1938d4b44d..f070204cd6 100644 --- a/library/util_var_fifo/index.html +++ b/library/util_var_fifo/index.html @@ -167,12 +167,15 @@
            • IP Cores
              • AXI AD3552R
              • AXI AD7606x
                • +
              • AXI AD7616
              • AXI AD7768
              • AXI AD777x
              • AXI AD9265
                • +
              • AXI AD9361
              • AXI AD9467
              • AXI AD9671
              • AXI AD9783
                • +
              • AXI AD9963
              • AXI ADAQ8092
              • AXI ADC Decimate
              • AXI ADC Trigger
                • diff --git a/library/util_wfifo/index.html b/library/util_wfifo/index.html index 1dd282b8d4..c1ae41729a 100644 --- a/library/util_wfifo/index.html +++ b/library/util_wfifo/index.html @@ -165,12 +165,15 @@
              • IP Cores
                • AXI AD3552R
                • AXI AD7606x
                  • +
                • AXI AD7616
                • AXI AD7768
                • AXI AD777x
                • AXI AD9265
                  • +
                • AXI AD9361
                • AXI AD9467
                • AXI AD9671
                • AXI AD9783
                  • +
                • AXI AD9963
                • AXI ADAQ8092
                • AXI ADC Decimate
                • AXI ADC Trigger
                  • diff --git a/library/xilinx/index.html b/library/xilinx/index.html index 78807f3244..18ee39d655 100644 --- a/library/xilinx/index.html +++ b/library/xilinx/index.html @@ -162,12 +162,15 @@
                • IP Cores
                  • AXI AD3552R
                  • AXI AD7606x
                    • +
                  • AXI AD7616
                  • AXI AD7768
                  • AXI AD777x
                  • AXI AD9265
                    • +
                  • AXI AD9361
                  • AXI AD9467
                  • AXI AD9671
                  • AXI AD9783
                    • +
                  • AXI AD9963
                  • AXI ADAQ8092
                  • AXI ADC Decimate
                  • AXI ADC Trigger
                    • diff --git a/library/xilinx/util_adxcvr/index.html b/library/xilinx/util_adxcvr/index.html index 7d5634066d..3b28b1e8d3 100644 --- a/library/xilinx/util_adxcvr/index.html +++ b/library/xilinx/util_adxcvr/index.html @@ -179,12 +179,15 @@
                  • IP Cores
                    • AXI AD3552R
                    • AXI AD7606x
                      • +
                    • AXI AD7616
                    • AXI AD7768
                    • AXI AD777x
                    • AXI AD9265
                      • +
                    • AXI AD9361
                    • AXI AD9467
                    • AXI AD9671
                    • AXI AD9783
                      • +
                    • AXI AD9963
                    • AXI ADAQ8092
                    • AXI ADC Decimate
                    • AXI ADC Trigger
                      • diff --git a/objects.inv b/objects.inv index f1d95f8ef2..cb4d6320ba 100644 Binary files a/objects.inv and b/objects.inv differ diff --git a/projects/ad4134_fmc/index.html b/projects/ad4134_fmc/index.html index 5c54f56be7..a74372a9b8 100644 --- a/projects/ad4134_fmc/index.html +++ b/projects/ad4134_fmc/index.html @@ -183,12 +183,15 @@
                    • IP Cores
                      • AXI AD3552R
                      • AXI AD7606x
                        • +
                      • AXI AD7616
                      • AXI AD7768
                      • AXI AD777x
                      • AXI AD9265
                        • +
                      • AXI AD9361
                      • AXI AD9467
                      • AXI AD9671
                      • AXI AD9783
                        • +
                      • AXI AD9963
                      • AXI ADAQ8092
                      • AXI ADC Decimate
                      • AXI ADC Trigger
                        • diff --git a/projects/ad4630_fmc/index.html b/projects/ad4630_fmc/index.html index 245c72cac6..3a6d9f7d51 100644 --- a/projects/ad4630_fmc/index.html +++ b/projects/ad4630_fmc/index.html @@ -190,12 +190,15 @@
                      • IP Cores
                        • AXI AD3552R
                        • AXI AD7606x
                          • +
                        • AXI AD7616
                        • AXI AD7768
                        • AXI AD777x
                        • AXI AD9265
                          • +
                        • AXI AD9361
                        • AXI AD9467
                        • AXI AD9671
                        • AXI AD9783
                          • +
                        • AXI AD9963
                        • AXI ADAQ8092
                        • AXI ADC Decimate
                        • AXI ADC Trigger
                          • diff --git a/projects/ad469x_fmc/index.html b/projects/ad469x_fmc/index.html index a33113fd65..52132fcda2 100644 --- a/projects/ad469x_fmc/index.html +++ b/projects/ad469x_fmc/index.html @@ -183,12 +183,15 @@
                        • IP Cores
                          • AXI AD3552R
                          • AXI AD7606x
                            • +
                          • AXI AD7616
                          • AXI AD7768
                          • AXI AD777x
                          • AXI AD9265
                            • +
                          • AXI AD9361
                          • AXI AD9467
                          • AXI AD9671
                          • AXI AD9783
                            • +
                          • AXI AD9963
                          • AXI ADAQ8092
                          • AXI ADC Decimate
                          • AXI ADC Trigger
                            • diff --git a/projects/ad5766_sdz/index.html b/projects/ad5766_sdz/index.html index d90d9b6660..ab81b1ef33 100644 --- a/projects/ad5766_sdz/index.html +++ b/projects/ad5766_sdz/index.html @@ -184,12 +184,15 @@
                          • IP Cores
                            • AXI AD3552R
                            • AXI AD7606x
                              • +
                            • AXI AD7616
                            • AXI AD7768
                            • AXI AD777x
                            • AXI AD9265
                              • +
                            • AXI AD9361
                            • AXI AD9467
                            • AXI AD9671
                            • AXI AD9783
                              • +
                            • AXI AD9963
                            • AXI ADAQ8092
                            • AXI ADC Decimate
                            • AXI ADC Trigger
                              • diff --git a/projects/ad7134_fmc/index.html b/projects/ad7134_fmc/index.html index 4d7fd1b81b..96927ab7b3 100644 --- a/projects/ad7134_fmc/index.html +++ b/projects/ad7134_fmc/index.html @@ -183,12 +183,15 @@
                            • IP Cores
                              • AXI AD3552R
                              • AXI AD7606x
                                • +
                              • AXI AD7616
                              • AXI AD7768
                              • AXI AD777x
                              • AXI AD9265
                                • +
                              • AXI AD9361
                              • AXI AD9467
                              • AXI AD9671
                              • AXI AD9783
                                • +
                              • AXI AD9963
                              • AXI ADAQ8092
                              • AXI ADC Decimate
                              • AXI ADC Trigger
                                • diff --git a/projects/ad719x_asdz/index.html b/projects/ad719x_asdz/index.html index 4a3296e6d4..f765f5ef32 100644 --- a/projects/ad719x_asdz/index.html +++ b/projects/ad719x_asdz/index.html @@ -180,12 +180,15 @@
                              • IP Cores
                                • AXI AD3552R
                                • AXI AD7606x
                                  • +
                                • AXI AD7616
                                • AXI AD7768
                                • AXI AD777x
                                • AXI AD9265
                                  • +
                                • AXI AD9361
                                • AXI AD9467
                                • AXI AD9671
                                • AXI AD9783
                                  • +
                                • AXI AD9963
                                • AXI ADAQ8092
                                • AXI ADC Decimate
                                • AXI ADC Trigger
                                  • diff --git a/projects/ad738x_fmc/index.html b/projects/ad738x_fmc/index.html index 3adf89a8b8..32cb30f2f0 100644 --- a/projects/ad738x_fmc/index.html +++ b/projects/ad738x_fmc/index.html @@ -183,12 +183,15 @@
                                • IP Cores
                                  • AXI AD3552R
                                  • AXI AD7606x
                                    • +
                                  • AXI AD7616
                                  • AXI AD7768
                                  • AXI AD777x
                                  • AXI AD9265
                                    • +
                                  • AXI AD9361
                                  • AXI AD9467
                                  • AXI AD9671
                                  • AXI AD9783
                                    • +
                                  • AXI AD9963
                                  • AXI ADAQ8092
                                  • AXI ADC Decimate
                                  • AXI ADC Trigger
                                    • diff --git a/projects/ad7606x_fmc/index.html b/projects/ad7606x_fmc/index.html index 3fcf90b804..dd7b4ec4a3 100644 --- a/projects/ad7606x_fmc/index.html +++ b/projects/ad7606x_fmc/index.html @@ -192,12 +192,15 @@
                                  • IP Cores
                                    • AXI AD3552R
                                    • AXI AD7606x
                                      • +
                                    • AXI AD7616
                                    • AXI AD7768
                                    • AXI AD777x
                                    • AXI AD9265
                                      • +
                                    • AXI AD9361
                                    • AXI AD9467
                                    • AXI AD9671
                                    • AXI AD9783
                                      • +
                                    • AXI AD9963
                                    • AXI ADAQ8092
                                    • AXI ADC Decimate
                                    • AXI ADC Trigger
                                      • diff --git a/projects/ad7616_sdz/index.html b/projects/ad7616_sdz/index.html index db4cfc6ab1..2677223b0d 100644 --- a/projects/ad7616_sdz/index.html +++ b/projects/ad7616_sdz/index.html @@ -193,12 +193,15 @@
                                    • IP Cores
                                      • AXI AD3552R
                                      • AXI AD7606x
                                        • +
                                      • AXI AD7616
                                      • AXI AD7768
                                      • AXI AD777x
                                      • AXI AD9265
                                        • +
                                      • AXI AD9361
                                      • AXI AD9467
                                      • AXI AD9671
                                      • AXI AD9783
                                        • +
                                      • AXI AD9963
                                      • AXI ADAQ8092
                                      • AXI ADC Decimate
                                      • AXI ADC Trigger
                                        • diff --git a/projects/ad7768evb/index.html b/projects/ad7768evb/index.html index bc2305c1bd..f0d935bbb1 100644 --- a/projects/ad7768evb/index.html +++ b/projects/ad7768evb/index.html @@ -186,12 +186,15 @@
                                      • IP Cores
                                        • AXI AD3552R
                                        • AXI AD7606x
                                          • +
                                        • AXI AD7616
                                        • AXI AD7768
                                        • AXI AD777x
                                        • AXI AD9265
                                          • +
                                        • AXI AD9361
                                        • AXI AD9467
                                        • AXI AD9671
                                        • AXI AD9783
                                          • +
                                        • AXI AD9963
                                        • AXI ADAQ8092
                                        • AXI ADC Decimate
                                        • AXI ADC Trigger
                                          • diff --git a/projects/ad9081_fmca_ebz/index.html b/projects/ad9081_fmca_ebz/index.html index 568b808acf..7838ca7427 100644 --- a/projects/ad9081_fmca_ebz/index.html +++ b/projects/ad9081_fmca_ebz/index.html @@ -200,12 +200,15 @@
                                        • IP Cores
                                          • AXI AD3552R
                                          • AXI AD7606x
                                            • +
                                          • AXI AD7616
                                          • AXI AD7768
                                          • AXI AD777x
                                          • AXI AD9265
                                            • +
                                          • AXI AD9361
                                          • AXI AD9467
                                          • AXI AD9671
                                          • AXI AD9783
                                            • +
                                          • AXI AD9963
                                          • AXI ADAQ8092
                                          • AXI ADC Decimate
                                          • AXI ADC Trigger
                                            • diff --git a/projects/ad9434_fmc/index.html b/projects/ad9434_fmc/index.html index 39d09d4ae8..921e4f43ef 100644 --- a/projects/ad9434_fmc/index.html +++ b/projects/ad9434_fmc/index.html @@ -183,12 +183,15 @@
                                          • IP Cores
                                            • AXI AD3552R
                                            • AXI AD7606x
                                              • +
                                            • AXI AD7616
                                            • AXI AD7768
                                            • AXI AD777x
                                            • AXI AD9265
                                              • +
                                            • AXI AD9361
                                            • AXI AD9467
                                            • AXI AD9671
                                            • AXI AD9783
                                              • +
                                            • AXI AD9963
                                            • AXI ADAQ8092
                                            • AXI ADC Decimate
                                            • AXI ADC Trigger
                                              • diff --git a/projects/ad9783_ebz/index.html b/projects/ad9783_ebz/index.html index f113188afe..c18ff1a3d6 100644 --- a/projects/ad9783_ebz/index.html +++ b/projects/ad9783_ebz/index.html @@ -184,12 +184,15 @@
                                            • IP Cores
                                              • AXI AD3552R
                                              • AXI AD7606x
                                                • +
                                              • AXI AD7616
                                              • AXI AD7768
                                              • AXI AD777x
                                              • AXI AD9265
                                                • +
                                              • AXI AD9361
                                              • AXI AD9467
                                              • AXI AD9671
                                              • AXI AD9783
                                                • +
                                              • AXI AD9963
                                              • AXI ADAQ8092
                                              • AXI ADC Decimate
                                              • AXI ADC Trigger
                                                • diff --git a/projects/adaq7980_sdz/index.html b/projects/adaq7980_sdz/index.html index 04b2780df8..6200378d93 100644 --- a/projects/adaq7980_sdz/index.html +++ b/projects/adaq7980_sdz/index.html @@ -183,12 +183,15 @@
                                              • IP Cores
                                                • AXI AD3552R
                                                • AXI AD7606x
                                                  • +
                                                • AXI AD7616
                                                • AXI AD7768
                                                • AXI AD777x
                                                • AXI AD9265
                                                  • +
                                                • AXI AD9361
                                                • AXI AD9467
                                                • AXI AD9671
                                                • AXI AD9783
                                                  • +
                                                • AXI AD9963
                                                • AXI ADAQ8092
                                                • AXI ADC Decimate
                                                • AXI ADC Trigger
                                                  • diff --git a/projects/adrv9026/index.html b/projects/adrv9026/index.html index efa00d1f44..c0eb3a62c5 100644 --- a/projects/adrv9026/index.html +++ b/projects/adrv9026/index.html @@ -191,12 +191,15 @@
                                                • IP Cores
                                                  • AXI AD3552R
                                                  • AXI AD7606x
                                                    • +
                                                  • AXI AD7616
                                                  • AXI AD7768
                                                  • AXI AD777x
                                                  • AXI AD9265
                                                    • +
                                                  • AXI AD9361
                                                  • AXI AD9467
                                                  • AXI AD9671
                                                  • AXI AD9783
                                                    • +
                                                  • AXI AD9963
                                                  • AXI ADAQ8092
                                                  • AXI ADC Decimate
                                                  • AXI ADC Trigger
                                                    • diff --git a/projects/cn0363/index.html b/projects/cn0363/index.html index aa9b780073..8822ae456c 100644 --- a/projects/cn0363/index.html +++ b/projects/cn0363/index.html @@ -184,12 +184,15 @@
                                                  • IP Cores
                                                    • AXI AD3552R
                                                    • AXI AD7606x
                                                      • +
                                                    • AXI AD7616
                                                    • AXI AD7768
                                                    • AXI AD777x
                                                    • AXI AD9265
                                                      • +
                                                    • AXI AD9361
                                                    • AXI AD9467
                                                    • AXI AD9671
                                                    • AXI AD9783
                                                      • +
                                                    • AXI AD9963
                                                    • AXI ADAQ8092
                                                    • AXI ADC Decimate
                                                    • AXI ADC Trigger
                                                      • diff --git a/projects/cn0540/index.html b/projects/cn0540/index.html index 450237dcba..e442b407c4 100644 --- a/projects/cn0540/index.html +++ b/projects/cn0540/index.html @@ -185,12 +185,15 @@
                                                    • IP Cores
                                                      • AXI AD3552R
                                                      • AXI AD7606x
                                                        • +
                                                      • AXI AD7616
                                                      • AXI AD7768
                                                      • AXI AD777x
                                                      • AXI AD9265
                                                        • +
                                                      • AXI AD9361
                                                      • AXI AD9467
                                                      • AXI AD9671
                                                      • AXI AD9783
                                                        • +
                                                      • AXI AD9963
                                                      • AXI ADAQ8092
                                                      • AXI ADC Decimate
                                                      • AXI ADC Trigger
                                                        • diff --git a/projects/cn0561/index.html b/projects/cn0561/index.html index a616049b04..01017becdd 100644 --- a/projects/cn0561/index.html +++ b/projects/cn0561/index.html @@ -183,12 +183,15 @@
                                                      • IP Cores
                                                        • AXI AD3552R
                                                        • AXI AD7606x
                                                          • +
                                                        • AXI AD7616
                                                        • AXI AD7768
                                                        • AXI AD777x
                                                        • AXI AD9265
                                                          • +
                                                        • AXI AD9361
                                                        • AXI AD9467
                                                        • AXI AD9671
                                                        • AXI AD9783
                                                          • +
                                                        • AXI AD9963
                                                        • AXI ADAQ8092
                                                        • AXI ADC Decimate
                                                        • AXI ADC Trigger
                                                          • diff --git a/projects/cn0585/index.html b/projects/cn0585/index.html index d3885cb972..6609bd34eb 100644 --- a/projects/cn0585/index.html +++ b/projects/cn0585/index.html @@ -184,12 +184,15 @@
                                                        • IP Cores
                                                          • AXI AD3552R
                                                          • AXI AD7606x
                                                            • +
                                                          • AXI AD7616
                                                          • AXI AD7768
                                                          • AXI AD777x
                                                          • AXI AD9265
                                                            • +
                                                          • AXI AD9361
                                                          • AXI AD9467
                                                          • AXI AD9671
                                                          • AXI AD9783
                                                            • +
                                                          • AXI AD9963
                                                          • AXI ADAQ8092
                                                          • AXI ADC Decimate
                                                          • AXI ADC Trigger
                                                            • diff --git a/projects/common/more_information.html b/projects/common/more_information.html index 1825413cad..63d97b30cd 100644 --- a/projects/common/more_information.html +++ b/projects/common/more_information.html @@ -157,12 +157,15 @@
                                                          • IP Cores
                                                            • AXI AD3552R
                                                            • AXI AD7606x
                                                              • +
                                                            • AXI AD7616
                                                            • AXI AD7768
                                                            • AXI AD777x
                                                            • AXI AD9265
                                                              • +
                                                            • AXI AD9361
                                                            • AXI AD9467
                                                            • AXI AD9671
                                                            • AXI AD9783
                                                              • +
                                                            • AXI AD9963
                                                            • AXI ADAQ8092
                                                            • AXI ADC Decimate
                                                            • AXI ADC Trigger
                                                              • diff --git a/projects/common/support.html b/projects/common/support.html index d285b3a011..d9c1f45425 100644 --- a/projects/common/support.html +++ b/projects/common/support.html @@ -157,12 +157,15 @@
                                                            • IP Cores
                                                              • AXI AD3552R
                                                              • AXI AD7606x
                                                                • +
                                                              • AXI AD7616
                                                              • AXI AD7768
                                                              • AXI AD777x
                                                              • AXI AD9265
                                                                • +
                                                              • AXI AD9361
                                                              • AXI AD9467
                                                              • AXI AD9671
                                                              • AXI AD9783
                                                                • +
                                                              • AXI AD9963
                                                              • AXI ADAQ8092
                                                              • AXI ADC Decimate
                                                              • AXI ADC Trigger
                                                                • diff --git a/projects/index.html b/projects/index.html index 3e97211692..e2d3e1e382 100644 --- a/projects/index.html +++ b/projects/index.html @@ -162,12 +162,15 @@
                                                              • IP Cores
                                                                • AXI AD3552R
                                                                • AXI AD7606x
                                                                  • +
                                                                • AXI AD7616
                                                                • AXI AD7768
                                                                • AXI AD777x
                                                                • AXI AD9265
                                                                  • +
                                                                • AXI AD9361
                                                                • AXI AD9467
                                                                • AXI AD9671
                                                                • AXI AD9783
                                                                  • +
                                                                • AXI AD9963
                                                                • AXI ADAQ8092
                                                                • AXI ADC Decimate
                                                                • AXI ADC Trigger
                                                                  • diff --git a/projects/pulsar_adc/index.html b/projects/pulsar_adc/index.html index e240776123..27eb6a3ca1 100644 --- a/projects/pulsar_adc/index.html +++ b/projects/pulsar_adc/index.html @@ -189,12 +189,15 @@
                                                                • IP Cores
                                                                  • AXI AD3552R
                                                                  • AXI AD7606x
                                                                    • +
                                                                  • AXI AD7616
                                                                  • AXI AD7768
                                                                  • AXI AD777x
                                                                  • AXI AD9265
                                                                    • +
                                                                  • AXI AD9361
                                                                  • AXI AD9467
                                                                  • AXI AD9671
                                                                  • AXI AD9783
                                                                    • +
                                                                  • AXI AD9963
                                                                  • AXI ADAQ8092
                                                                  • AXI ADC Decimate
                                                                  • AXI ADC Trigger
                                                                    • diff --git a/projects/pulsar_lvds/index.html b/projects/pulsar_lvds/index.html index 9c66804655..296edb2c69 100644 --- a/projects/pulsar_lvds/index.html +++ b/projects/pulsar_lvds/index.html @@ -183,12 +183,15 @@
                                                                  • IP Cores
                                                                    • AXI AD3552R
                                                                    • AXI AD7606x
                                                                      • +
                                                                    • AXI AD7616
                                                                    • AXI AD7768
                                                                    • AXI AD777x
                                                                    • AXI AD9265
                                                                      • +
                                                                    • AXI AD9361
                                                                    • AXI AD9467
                                                                    • AXI AD9671
                                                                    • AXI AD9783
                                                                      • +
                                                                    • AXI AD9963
                                                                    • AXI ADAQ8092
                                                                    • AXI ADC Decimate
                                                                    • AXI ADC Trigger
                                                                      • diff --git a/projects/template/index.html b/projects/template/index.html index 0b47306723..1cc7f4a11b 100644 --- a/projects/template/index.html +++ b/projects/template/index.html @@ -192,12 +192,15 @@
                                                                    • IP Cores
                                                                      • AXI AD3552R
                                                                      • AXI AD7606x
                                                                        • +
                                                                      • AXI AD7616
                                                                      • AXI AD7768
                                                                      • AXI AD777x
                                                                      • AXI AD9265
                                                                        • +
                                                                      • AXI AD9361
                                                                      • AXI AD9467
                                                                      • AXI AD9671
                                                                      • AXI AD9783
                                                                        • +
                                                                      • AXI AD9963
                                                                      • AXI ADAQ8092
                                                                      • AXI ADC Decimate
                                                                      • AXI ADC Trigger
                                                                        • diff --git a/search.html b/search.html index 7876d41c7d..53818603f1 100644 --- a/search.html +++ b/search.html @@ -160,12 +160,15 @@
                                                                      • IP Cores
                                                                        • AXI AD3552R
                                                                        • AXI AD7606x
                                                                          • +
                                                                        • AXI AD7616
                                                                        • AXI AD7768
                                                                        • AXI AD777x
                                                                        • AXI AD9265
                                                                          • +
                                                                        • AXI AD9361
                                                                        • AXI AD9467
                                                                        • AXI AD9671
                                                                        • AXI AD9783
                                                                          • +
                                                                        • AXI AD9963
                                                                        • AXI ADAQ8092
                                                                        • AXI ADC Decimate
                                                                        • AXI ADC Trigger
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18, 30, 31, 32, 35, 51, 52, 53, 56, 57, 58, 60, 63, 64, 67, 68, 73, 77, 80, 84, 87, 88, 89, 93, 94, 95, 96, 97, 103], "intel": [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 21, 31, 32, 35, 51, 52, 53, 73, 77, 84, 87, 92, 94, 95, 96, 97, 103], "tool": [0, 21, 35, 46, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 83, 85, 86, 87, 88, 92, 93, 94, 95, 101, 102], "chain": [0, 10, 11, 14, 15, 25, 35, 64, 66, 73, 76, 85, 87], "user": [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 14, 20, 22, 23, 24, 25, 30, 31, 32, 35, 39, 46, 51, 55, 58, 60, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 85, 86, 87, 88, 89, 92, 93, 95, 96, 97, 101, 102, 103], "guid": [0, 2, 7, 8, 12, 17, 18, 30, 31, 32, 34, 35, 55, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 85, 86, 87, 89, 93, 95, 98, 100], "ip": [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 31, 32, 33, 34, 35, 36, 43, 44, 45, 46, 50, 55, 59, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 85, 86, 87, 88, 90, 92, 93, 94, 95, 96, 97, 100, 102, 103, 104], "core": [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 23, 24, 25, 27, 28, 29, 31, 32, 33, 34, 35, 36, 37, 39, 40, 43, 45, 46, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 64, 70, 71, 73, 88, 89, 92, 93, 94, 98, 100, 101, 103], "s_axis_axi_aclks_axi_aresetndac_clkdma_datavalid_in_dmavalid_in_dma_secdata_in_adata_in_bvalid_in_avalid_in_bsdio_iexternal_syncdac_data_readydac_sclkdac_csnsdio_osdio_tsync_ext_deviceaxi_ad3552r": 1, "The": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 85, 86, 87, 88, 89, 91, 93, 94, 95, 96, 97, 98, 100, 101, 102, 103], "can": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 31, 32, 33, 34, 35, 36, 38, 39, 40, 41, 42, 43, 44, 46, 48, 51, 52, 53, 55, 58, 59, 60, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 85, 86, 87, 88, 89, 90, 92, 93, 95, 96, 97, 98, 99, 101, 102, 104], "low": [1, 2, 8, 11, 12, 14, 15, 20, 21, 23, 25, 26, 27, 31, 32, 33, 34, 36, 38, 39, 42, 43, 44, 45, 52, 53, 55, 63, 64, 66, 67, 68, 69, 72, 74, 76, 78, 80, 81, 85, 86, 93, 96, 97, 100, 102], "drift": [1, 64], "ultra": 1, "fast": [1, 15, 39, 67, 72, 88], "16": [1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 29, 31, 32, 33, 34, 35, 36, 38, 39, 43, 45, 46, 51, 52, 54, 56, 57, 64, 65, 66, 69, 70, 71, 73, 75, 76, 77, 79, 81, 86, 87, 88, 89, 93, 96, 97, 98, 103], "bit": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 29, 31, 32, 33, 34, 35, 36, 38, 39, 46, 48, 51, 54, 56, 57, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 85, 86, 87, 88, 89, 93, 96, 97, 103], "accuraci": [1, 24, 76, 78], "current": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 31, 32, 33, 34, 35, 36, 39, 40, 43, 51, 52, 53, 58, 60, 62, 64, 65, 69, 72, 73, 79, 80, 81, 89, 92, 93, 96, 97, 98, 102], "output": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 21, 22, 23, 24, 25, 27, 29, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 45, 46, 49, 51, 52, 53, 54, 56, 58, 59, 60, 62, 64, 66, 67, 68, 72, 78, 79, 85, 86, 87, 88, 89, 93, 96, 97, 98, 100], "digit": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 20, 25, 30, 38, 51, 63, 64, 66, 67, 69, 70, 71, 72, 74, 75, 76, 77, 78, 80, 81, 85, 86, 93, 95, 96, 97, 99], "convert": [1, 4, 10, 15, 16, 17, 18, 22, 24, 25, 38, 46, 55, 62, 63, 64, 66, 67, 69, 70, 71, 72, 73, 74, 75, 76, 77, 80, 81, 85, 86, 87, 91, 96, 97, 100], "dac": [1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 20, 24, 25, 30, 31, 33, 34, 35, 38, 51, 57, 58, 66, 75, 79, 81, 96, 98, 101], "multipl": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 15, 17, 18, 19, 23, 24, 31, 32, 33, 34, 35, 36, 38, 43, 44, 51, 58, 60, 64, 74, 76, 77, 87, 89, 92, 93, 96, 97, 98, 100], "voltag": [1, 12, 13, 38, 64, 66, 69, 70, 71, 72, 74, 79, 86, 102], "span": [1, 15, 66, 85], "rang": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21, 22, 23, 24, 25, 26, 27, 29, 31, 32, 33, 34, 35, 36, 43, 44, 45, 46, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 62, 63, 64, 66, 67, 68, 69, 70, 72, 75, 79, 80, 85, 86, 88, 93, 96, 97], "base": [1, 2, 3, 4, 5, 6, 7, 9, 11, 13, 15, 16, 17, 18, 20, 21, 22, 23, 25, 29, 31, 32, 33, 34, 35, 36, 39, 51, 52, 53, 56, 57, 63, 64, 65, 66, 67, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 85, 86, 87, 89, 90, 92], "vivado": [1, 3, 4, 5, 6, 7, 9, 22, 23, 26, 27, 33, 34, 36, 43, 44, 45, 46, 50, 51, 88, 92, 98, 100, 102, 103], "compat": [1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 31, 32, 33, 34, 51, 64, 66, 69, 75, 76, 79, 89, 96, 97], "8b": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "read": [1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 31, 32, 33, 34, 36, 39, 46, 48, 51, 52, 53, 57, 59, 64, 89, 91, 93, 95, 96], "write": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 31, 32, 33, 34, 36, 40, 41, 48, 51, 52, 53, 59, 66, 73, 78, 87, 89, 97, 98, 102], "sdr": [1, 2, 3, 4, 5, 6, 7, 8, 9, 17, 18, 31, 32, 33, 34, 35, 51, 64, 90, 96, 97], "ddr": [1, 2, 3, 4, 5, 6, 7, 8, 9, 17, 18, 25, 31, 32, 46, 51, 64, 73, 74, 87, 96, 97], "16b": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "data": [1, 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 17, 19, 20, 24, 27, 28, 29, 30, 35, 36, 37, 39, 40, 41, 43, 44, 45, 46, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 85, 86, 87, 88, 89, 93, 95, 96, 97, 98, 100, 101], "stream": [1, 8, 11, 12, 18, 20, 27, 28, 29, 30, 33, 34, 36, 37, 38, 39, 40, 43, 44, 45, 46, 49, 54, 56, 57, 65, 73, 99], "clk_in": [1, 3, 4], "8": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 29, 31, 32, 33, 34, 35, 36, 39, 42, 43, 44, 45, 46, 48, 50, 51, 52, 56, 57, 58, 60, 62, 64, 67, 69, 70, 72, 76, 79, 81, 87, 88, 89, 93, 96, 97, 98], "4": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 23, 24, 25, 26, 27, 29, 31, 32, 33, 34, 35, 36, 39, 41, 45, 46, 48, 51, 52, 53, 56, 57, 58, 60, 62, 63, 64, 66, 67, 69, 70, 72, 74, 76, 79, 80, 81, 86, 87, 88, 89, 96, 97, 98, 101, 102, 103], "updat": [1, 23, 25, 27, 29, 36, 39, 48, 66, 87, 89, 92, 93, 102, 103], "rate": [1, 7, 8, 10, 12, 14, 15, 16, 18, 20, 24, 25, 31, 32, 33, 34, 52, 55, 58, 60, 62, 64, 65, 66, 68, 69, 70, 71, 72, 73, 74, 75, 77, 79, 80, 85, 87, 97], "select": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 15, 16, 18, 19, 20, 24, 31, 32, 33, 34, 35, 41, 42, 43, 46, 48, 51, 55, 64, 66, 70, 71, 72, 73, 87, 89, 94, 96, 97, 101], "input": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 16, 17, 18, 19, 20, 22, 23, 24, 25, 26, 29, 31, 32, 33, 34, 35, 37, 40, 41, 42, 49, 51, 52, 53, 54, 57, 58, 59, 60, 62, 63, 64, 67, 68, 69, 70, 71, 72, 74, 76, 77, 79, 80, 85, 86, 88, 89, 93, 96, 97, 100], "sourc": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 26, 27, 31, 32, 33, 34, 35, 36, 41, 43, 44, 45, 46, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 85, 86, 87, 88, 89, 91, 92, 93, 96, 97, 98, 101, 102], "dma": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 14, 15, 17, 18, 20, 24, 25, 27, 28, 29, 31, 32, 51, 56, 57, 58, 59, 60, 64, 70, 71, 78, 87, 96, 97], "adc": [1, 3, 4, 5, 6, 7, 8, 9, 13, 14, 15, 16, 18, 20, 24, 25, 28, 29, 30, 32, 33, 34, 35, 38, 47, 51, 54, 56, 60, 63, 64, 65, 67, 68, 69, 70, 71, 72, 74, 76, 78, 79, 80, 81, 84, 86, 97, 101], "test_ramp": 1, "out": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 31, 32, 33, 34, 36, 38, 43, 44, 45, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 64, 70, 71, 72, 73, 77, 78, 79, 85, 87, 92, 93, 96, 97, 102, 103], "clock": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 18, 19, 20, 21, 23, 26, 27, 29, 36, 39, 41, 42, 43, 44, 45, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 63, 65, 66, 67, 68, 69, 70, 71, 72, 76, 78, 79, 80, 81, 85, 86, 88, 93, 96, 97, 101, 102], "sclk": [1, 39, 42, 43, 46], "frequenc": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16, 17, 18, 19, 22, 25, 31, 32, 33, 34, 39, 46, 51, 55, 62, 63, 64, 66, 67, 70, 71, 72, 77, 78, 79, 80, 87, 93, 96, 97], "when": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 14, 15, 16, 20, 21, 22, 23, 24, 25, 27, 28, 29, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 42, 44, 45, 51, 52, 53, 55, 56, 57, 58, 60, 62, 64, 66, 73, 85, 87, 88, 89, 91, 92, 93, 96, 97, 98, 102, 103], "i": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 85, 86, 88, 89, 91, 92, 93, 95, 96, 97, 98, 100, 101, 103, 104], "2": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 29, 31, 32, 33, 34, 35, 36, 38, 39, 41, 43, 45, 46, 47, 48, 51, 52, 54, 55, 58, 60, 62, 66, 67, 69, 70, 71, 72, 76, 77, 78, 79, 80, 85, 86, 87, 88, 89, 92, 96, 97, 101, 102, 103], "mode": [1, 3, 4, 5, 6, 7, 8, 9, 11, 12, 14, 15, 19, 20, 21, 23, 24, 27, 28, 29, 31, 32, 33, 34, 42, 46, 51, 52, 53, 55, 62, 63, 65, 66, 67, 69, 72, 76, 80, 89, 93, 96, 97], "have": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 27, 30, 31, 32, 33, 34, 35, 36, 41, 44, 46, 51, 62, 63, 64, 65, 66, 67, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 84, 85, 86, 87, 88, 89, 91, 92, 93, 95, 96, 97, 98, 100, 101, 102, 103], "maximum": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 14, 15, 17, 18, 19, 20, 21, 24, 25, 26, 31, 32, 33, 34, 36, 41, 46, 51, 59, 63, 64, 65, 66, 72, 75, 79, 80, 89, 93, 96, 97, 102], "132mhz": 1, "synchron": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 14, 17, 18, 19, 20, 21, 23, 24, 26, 27, 29, 33, 35, 37, 41, 43, 44, 45, 50, 51, 52, 53, 54, 56, 57, 59, 72, 73, 78, 87, 92, 93, 96, 97], "capabl": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 23, 31, 32, 46, 51, 63, 67, 72, 79, 80, 96, 97, 102], "set": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 31, 32, 36, 38, 42, 45, 46, 47, 51, 52, 53, 56, 57, 62, 66, 70, 71, 73, 76, 79, 85, 86, 87, 89, 92, 93, 96, 97, 98, 101, 102, 103], "an": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 16, 17, 18, 19, 20, 21, 23, 24, 25, 27, 28, 29, 31, 32, 33, 34, 35, 36, 38, 39, 43, 46, 51, 52, 53, 54, 56, 57, 59, 63, 64, 65, 66, 67, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 85, 86, 88, 91, 92, 93, 95, 96, 97, 98, 100, 101, 103], "name": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 29, 31, 32, 33, 34, 36, 37, 39, 40, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 85, 86, 87, 88, 89, 92, 96, 97, 98, 100, 101, 102], "axi_ad3552r": [1, 81, 92], "v": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 26, 27, 31, 32, 33, 34, 35, 36, 39, 43, 44, 45, 48, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 64, 66, 69, 70, 71, 72, 76, 86, 87, 88, 89, 93, 96, 97, 98, 100, 102], "axi_ad3552r_channel": 1, "channel": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 19, 20, 23, 24, 25, 30, 31, 32, 33, 34, 35, 38, 39, 41, 51, 54, 58, 60, 63, 64, 66, 67, 70, 71, 72, 73, 77, 78, 80, 81, 85, 87, 98, 99, 100], "axi_ad3552r_cor": 1, "axi_ad3552r_if": 1, "modul": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 13, 15, 17, 18, 20, 21, 23, 25, 27, 29, 31, 32, 33, 34, 39, 40, 42, 48, 51, 52, 55, 56, 57, 63, 64, 65, 66, 67, 72, 75, 78, 80, 87, 88, 89, 92, 93, 96, 97, 98, 100, 101, 102], "axi_ad3552r_if_tb": 1, "testbench": 1, "setup": [1, 33, 34, 73, 78, 81, 102, 103], "axi_ad3552r_ip": 1, "gener": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 16, 18, 19, 20, 22, 23, 24, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 38, 39, 42, 43, 44, 45, 46, 50, 51, 52, 59, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 85, 86, 87, 88, 89, 91, 92, 94, 95, 99], "integr": [1, 2, 3, 4, 9, 23, 25, 26, 27, 31, 32, 33, 34, 35, 36, 43, 44, 45, 50, 58, 60, 64, 66, 69, 72, 76, 77, 79, 88, 89, 90, 92, 98], "default": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 31, 32, 33, 34, 36, 39, 43, 44, 45, 46, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 62, 66, 69, 70, 71, 73, 77, 79, 85, 86, 87, 88, 89, 93, 96, 97, 98, 101], "valu": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 29, 31, 32, 33, 34, 36, 39, 40, 41, 43, 44, 45, 46, 48, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 62, 73, 74, 77, 87, 93, 96, 97, 98, 101], "choic": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21, 22, 23, 25, 26, 27, 31, 32, 33, 34, 36, 43, 44, 45, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 62, 96, 97], "id": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 15, 16, 17, 18, 19, 21, 23, 25, 27, 29, 30, 31, 32, 33, 34, 36, 39, 51, 91, 96, 97, 98, 99], "should": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 23, 24, 25, 27, 29, 31, 32, 33, 34, 35, 36, 39, 42, 52, 53, 54, 59, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 83, 85, 86, 87, 88, 89, 92, 93, 95, 96, 97, 98, 100, 101, 102, 103], "uniqu": [1, 2, 3, 4, 5, 6, 7, 8, 9, 13, 15, 17, 18, 19, 21, 23, 31, 32, 33, 34, 36, 51, 89, 93, 96, 97, 98], "each": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 13, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 31, 32, 33, 34, 35, 36, 37, 39, 41, 46, 51, 54, 56, 57, 62, 63, 67, 70, 71, 72, 73, 77, 78, 80, 87, 88, 89, 90, 92, 93, 96, 97, 98, 100, 102], "0": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 29, 31, 32, 33, 34, 35, 36, 37, 39, 41, 43, 44, 45, 46, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 85, 86, 87, 88, 89, 93, 96, 97, 98, 100, 101, 102, 103], "fpga_technologi": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 18, 31, 32, 51, 96, 97], "encod": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 31, 32, 33, 34, 43, 51, 73, 77, 87, 96, 97], "describ": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 16, 22, 24, 29, 31, 32, 33, 51, 73, 77, 87, 88, 92, 93, 96, 97, 102], "technologi": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 31, 32, 35, 51, 62, 93, 96, 97], "arria": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 15, 31, 32, 35, 51, 73, 87, 96, 97, 102], "10": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15, 16, 19, 21, 25, 27, 31, 32, 33, 34, 35, 39, 46, 48, 51, 55, 62, 64, 70, 71, 72, 73, 77, 86, 87, 88, 96, 97, 98, 101, 102], "7seri": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 18, 31, 32, 51, 96, 97], "unknown": [1, 5, 6, 7, 8, 9, 11, 12, 13, 15, 18, 29, 31, 32, 62, 89], "1": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 29, 31, 32, 33, 34, 35, 36, 37, 38, 39, 41, 42, 43, 44, 45, 46, 48, 50, 51, 52, 53, 54, 55, 56, 57, 58, 60, 62, 66, 67, 69, 70, 71, 72, 73, 74, 76, 77, 78, 79, 80, 85, 86, 87, 88, 89, 92, 96, 97, 98, 101, 102, 103], "ultrascal": [1, 5, 6, 7, 8, 9, 12, 13, 16, 18, 25, 31, 32, 55, 62, 73, 75, 77, 87, 88, 89, 102], "3": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 29, 31, 32, 33, 34, 35, 36, 39, 41, 43, 46, 48, 51, 55, 62, 66, 69, 70, 71, 72, 73, 76, 77, 79, 87, 88, 89, 96, 97, 101, 102, 103], "versal": [1, 5, 6, 7, 8, 9, 12, 13, 18, 31, 32, 73, 87, 88, 102], "fpga_famili": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 31, 32, 51, 96, 97], "famili": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 15, 25, 31, 32, 38, 46, 47, 51, 68, 69, 85, 86, 88, 96, 97, 102], "variant": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 31, 32, 46, 51, 80, 96, 97], "e": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 15, 16, 17, 18, 21, 23, 24, 25, 29, 31, 32, 33, 34, 35, 39, 41, 46, 51, 73, 87, 88, 89, 92, 93, 96, 97, 98, 102], "g": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 15, 17, 18, 21, 24, 25, 29, 31, 32, 33, 34, 39, 41, 51, 73, 87, 88, 89, 92, 93, 96, 97, 98, 102], "sx": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 31, 32, 51, 96, 97], "gx": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 31, 32, 51, 96, 97], "gt": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 31, 32, 51, 62, 96, 97], "artix": [1, 5, 6, 7, 8, 9, 12, 13, 15, 31, 32, 88], "kintex": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 15, 31, 32, 51, 88, 96, 97], "virtex": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 15, 31, 32, 51, 88, 89, 96, 97], "zynq": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 16, 17, 18, 25, 31, 32, 46, 51, 55, 63, 64, 65, 66, 67, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 85, 86, 87, 88, 89, 96, 97, 102], "versalprim": [1, 5, 6, 7, 8, 9, 12, 13, 31, 32], "5": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 22, 23, 25, 27, 29, 31, 32, 33, 34, 35, 36, 39, 46, 48, 51, 52, 53, 62, 63, 64, 66, 67, 69, 70, 71, 72, 73, 76, 79, 80, 81, 85, 86, 87, 88, 89, 92, 96, 97, 101, 103], "versalaicor": [1, 5, 6, 7, 8, 9, 12, 13, 31, 32], "6": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16, 17, 18, 19, 20, 21, 22, 23, 25, 26, 27, 29, 31, 32, 33, 34, 35, 39, 48, 51, 57, 62, 70, 73, 79, 86, 87, 88, 89, 96, 97], "versalpremium": [1, 5, 6, 7, 8, 9, 12, 13, 31, 32], "7": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 29, 31, 32, 33, 34, 36, 37, 39, 43, 44, 45, 46, 48, 50, 51, 52, 53, 62, 63, 67, 72, 73, 76, 79, 80, 86, 87, 88, 93, 96, 97, 98, 102], "speed_grad": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 31, 32, 51, 96, 97], "": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 14, 15, 16, 19, 21, 22, 23, 24, 27, 29, 31, 32, 33, 34, 36, 39, 43, 45, 48, 51, 52, 53, 55, 56, 57, 58, 60, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 85, 86, 87, 88, 89, 93, 94, 95, 96, 97, 98, 101], "speed": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 15, 16, 18, 24, 25, 26, 27, 31, 32, 33, 34, 35, 51, 59, 62, 63, 67, 68, 69, 70, 71, 80, 85, 86, 89, 96, 97, 102], "grade": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 27, 31, 32, 51, 96, 97], "1l": [1, 5, 6, 7, 8, 9, 12, 13, 31, 32], "11": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 15, 21, 25, 27, 29, 31, 32, 33, 34, 35, 39, 48, 51, 55, 73, 77, 79, 87, 88, 96], "1h": [1, 5, 6, 7, 8, 9, 12, 13, 31, 32], "12": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 15, 16, 19, 21, 25, 26, 27, 29, 31, 32, 33, 34, 35, 38, 39, 46, 48, 51, 59, 62, 63, 64, 65, 66, 67, 69, 70, 71, 72, 73, 74, 75, 76, 78, 79, 80, 85, 87, 88, 93, 96, 97], "1hv": [1, 5, 6, 7, 8, 9, 12, 13, 31, 32], "13": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 15, 19, 21, 23, 25, 31, 32, 33, 34, 36, 39, 48, 51, 59, 63, 64, 65, 66, 67, 69, 70, 71, 72, 73, 74, 76, 77, 78, 79, 80, 81, 85, 86, 87, 88, 96, 97, 100, 101], "1lv": [1, 5, 6, 7, 8, 9, 12, 13, 31, 32], "14": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 14, 21, 24, 25, 26, 27, 31, 32, 33, 34, 35, 39, 46, 48, 51, 66, 69, 77, 85, 87, 88, 96, 97, 98, 103], "20": [1, 5, 6, 7, 8, 9, 12, 13, 16, 25, 27, 29, 31, 32, 33, 34, 38, 62, 66, 71, 73, 77, 87, 88], "2l": [1, 5, 6, 7, 8, 9, 12, 13, 31, 32], "21": [1, 5, 6, 7, 8, 9, 12, 13, 23, 24, 25, 27, 29, 31, 32, 33, 34, 87, 88, 97, 103], "2lv": [1, 5, 6, 7, 8, 9, 12, 13, 31, 32], "22": [1, 5, 6, 7, 8, 9, 12, 13, 25, 27, 29, 31, 32, 87, 88, 103], "2mp": [1, 5, 6, 7, 8, 9, 12, 13, 31, 32], "23": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 15, 18, 24, 25, 27, 29, 31, 32, 33, 34, 36, 51, 87, 88, 96, 97, 103], "2lvc": [1, 5, 6, 7, 8, 9, 12, 13, 31, 32], "24": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 15, 17, 18, 23, 24, 25, 27, 29, 31, 32, 33, 34, 36, 38, 43, 46, 51, 63, 64, 67, 72, 73, 78, 79, 87, 88, 96, 97], "2lvi": [1, 5, 6, 7, 8, 9, 12, 13, 31, 32], "25": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 16, 24, 25, 31, 32, 33, 34, 35, 51, 55, 62, 72, 87, 88, 96, 97], "30": [1, 5, 6, 7, 8, 9, 12, 13, 23, 25, 26, 27, 31, 32, 46, 72, 87, 88], "dev_packag": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 31, 32, 51, 96, 97], "packag": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 23, 29, 31, 32, 33, 34, 51, 64, 66, 69, 72, 76, 89, 96, 97, 98], "might": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 15, 31, 32, 33, 34, 40, 42, 51, 73, 88, 89, 96, 97, 98, 103], "affect": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 15, 31, 32, 33, 34, 39, 41, 51, 62, 89, 96, 97], "high": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 14, 15, 16, 18, 20, 21, 24, 25, 27, 31, 32, 33, 34, 35, 36, 38, 39, 46, 51, 58, 60, 62, 66, 68, 69, 70, 71, 72, 74, 75, 76, 79, 85, 86, 89, 96, 97, 102], "rf": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 23, 25, 51, 73, 77, 89, 90, 96, 97], "fl": [1, 5, 6, 7, 8, 9, 12, 13, 31, 32], "ff": [1, 5, 6, 7, 8, 9, 12, 13, 15, 24, 25, 31, 32], "fb": [1, 5, 6, 7, 8, 9, 12, 13, 31, 32], "hc": [1, 5, 6, 7, 8, 9, 12, 13, 31, 32], "fh": [1, 5, 6, 7, 8, 9, 12, 13, 31, 32], "c": [1, 5, 6, 7, 8, 9, 12, 13, 15, 16, 25, 41, 42, 43, 46, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 85, 86, 87, 89, 96, 97, 101], "cp": [1, 5, 6, 7, 8, 9, 12, 13, 31, 32, 62], "ft": [1, 5, 6, 7, 8, 9, 12, 13, 31, 32], "9": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 16, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 39, 48, 51, 62, 64, 72, 79, 87, 88, 89, 93, 96, 97, 103], "fg": [1, 5, 6, 7, 8, 9, 12, 13, 31, 32], "sb": [1, 5, 6, 7, 8, 9, 12, 13, 31, 32], "rb": [1, 5, 6, 7, 8, 9, 12, 13, 31, 32], "r": [1, 5, 6, 7, 8, 9, 12, 13, 31, 32, 33, 34, 39, 48], "cl": [1, 5, 6, 7, 8, 9, 12, 13, 31, 32], "sf": [1, 5, 6, 7, 8, 9, 12, 13, 31, 32], "15": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 31, 32, 33, 34, 36, 37, 39, 43, 44, 45, 46, 48, 49, 50, 51, 53, 56, 57, 73, 87, 88, 89, 93, 96, 97, 98, 101, 103], "ba": [1, 5, 6, 7, 8, 9, 12, 13, 31, 32], "fa": [1, 5, 6, 7, 8, 9, 12, 13, 31, 32], "17": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 14, 20, 25, 27, 29, 31, 32, 33, 51, 87, 88, 89, 96, 97, 103], "f": [1, 5, 6, 7, 8, 9, 12, 13, 16, 25, 31, 32, 33, 34, 73, 77, 87], "18": [1, 5, 6, 7, 8, 9, 12, 13, 14, 20, 25, 31, 32, 33, 34, 38, 46, 70, 77, 85, 86, 87, 88, 103], "fi": [1, 5, 6, 7, 8, 9, 12, 13, 31, 32], "19": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 14, 15, 20, 25, 27, 29, 31, 32, 33, 34, 51, 87, 88, 89, 96, 103], "l": [1, 5, 6, 7, 8, 9, 12, 13, 16, 31, 32, 33, 34, 87, 89], "dds_disabl": [1, 2, 3, 4, 5, 6, 7, 8, 9, 24, 31, 32, 51, 96, 97], "dd": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "disabl": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 14, 15, 18, 20, 21, 23, 24, 25, 27, 29, 31, 32, 33, 34, 36, 51, 53, 70, 87, 96, 97, 103], "dds_type": [1, 24, 32], "type": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 31, 32, 33, 34, 36, 51, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 85, 86, 87, 88, 89, 93, 96, 97, 100, 102, 103], "dds_cordic_dw": [1, 32], "cordic": [1, 8, 24, 32], "dw": [1, 96, 97], "dds_cordic_phase_dw": [1, 32], "phase": [1, 8, 32, 35, 39, 70, 72, 85, 86, 97], "s_axi": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 27, 31, 32, 33, 34, 36, 51, 52, 53, 57], "standard": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 14, 19, 20, 24, 31, 32, 33, 34, 35, 37, 44, 51, 65, 66, 69, 78, 88, 89, 92, 96, 97, 102], "slave": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 16, 19, 20, 22, 23, 31, 51, 52, 53, 63, 67, 80], "memori": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 22, 23, 27, 28, 31, 32, 33, 34, 36, 38, 40, 46, 51, 58, 59, 60, 62, 89, 98, 100], "physic": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 26, 27, 31, 32, 33, 34, 36, 39, 42, 43, 44, 45, 46, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 73, 77, 87, 88, 89, 96, 97, 101], "port": [1, 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 26, 27, 30, 31, 32, 33, 34, 36, 43, 44, 45, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 62, 84, 87, 88, 89, 93, 94, 96, 97, 98], "logic": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 36, 38, 39, 42, 43, 44, 45, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 62, 63, 64, 65, 66, 67, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 85, 86, 87, 92, 93, 96, 97, 98, 99, 101], "direct": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 26, 27, 29, 30, 31, 32, 33, 34, 35, 36, 37, 40, 42, 43, 44, 45, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 63, 64, 65, 66, 67, 70, 71, 72, 73, 75, 76, 77, 78, 79, 80, 81, 85, 86, 87, 89, 93, 97, 98, 99, 100], "depend": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 26, 27, 29, 31, 32, 33, 34, 35, 36, 38, 39, 41, 42, 43, 44, 45, 46, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 63, 64, 65, 66, 67, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 85, 86, 87, 88, 89, 92, 96, 97, 98], "s_axi_awaddr": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51], "awaddr": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51], "s_axi_awprot": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51], "awprot": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51], "s_axi_awvalid": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51], "awvalid": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51], "s_axi_awreadi": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51], "awreadi": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51], "s_axi_wdata": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51], "wdata": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51], "31": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 31, 32, 33, 34, 36, 51, 53, 54, 58, 59, 60, 62, 87, 88, 93, 96, 97, 98, 100], "s_axi_wstrb": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51], "wstrb": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51], "s_axi_wvalid": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51], "wvalid": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51], "s_axi_wreadi": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51], "wreadi": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51], "s_axi_bresp": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51], "bresp": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51], "s_axi_bvalid": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51], "bvalid": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51], "s_axi_breadi": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51], "breadi": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51], "s_axi_araddr": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51], "araddr": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51], "s_axi_arprot": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51], "arprot": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51], "s_axi_arvalid": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51], "arvalid": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51], "s_axi_arreadi": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51], "arreadi": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51], "s_axi_rdata": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51], "rdata": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51], "s_axi_rresp": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51], "rresp": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51], "s_axi_rvalid": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51], "rvalid": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51], "s_axi_rreadi": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51], "rreadi": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51], "s_axi_aclk": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 46, 51, 98, 100], "clk": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 30, 31, 32, 33, 34, 36, 39, 41, 43, 44, 46, 48, 50, 51, 54, 55, 56, 57, 58, 59, 60, 93, 99], "s_axi_aresetn": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 46, 51, 98, 100], "rst": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51, 55, 58, 59, 60, 87, 91, 93], "dac_clk": [1, 14, 97], "dma_data": 1, "from": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 29, 31, 32, 33, 34, 35, 36, 37, 38, 39, 41, 43, 44, 45, 46, 47, 48, 50, 51, 52, 53, 54, 55, 56, 57, 59, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 83, 85, 86, 87, 88, 89, 91, 92, 93, 95, 96, 97, 98, 100, 101, 102, 103, 104], "dmac": [1, 2, 17, 18, 20, 30, 99], "valid_in_dma": 1, "valid": [1, 2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 16, 17, 20, 24, 25, 27, 31, 32, 33, 34, 36, 37, 41, 46, 49, 51, 53, 54, 56, 57, 58, 59, 60, 89, 90, 93, 96, 97, 102, 103], "valid_in_dma_sec": 1, "secondari": [1, 13, 22], "need": [1, 3, 4, 5, 6, 7, 9, 11, 12, 14, 15, 16, 17, 18, 21, 24, 25, 27, 31, 33, 34, 35, 36, 39, 41, 46, 51, 57, 58, 60, 62, 63, 67, 70, 71, 73, 74, 80, 85, 86, 88, 89, 95, 98, 102, 103], "dac_data_readi": 1, "readi": [1, 3, 4, 7, 12, 15, 24, 25, 33, 34, 37, 41, 46, 49, 57, 96], "signal": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 16, 17, 18, 19, 20, 21, 23, 24, 29, 38, 39, 46, 51, 52, 54, 55, 56, 57, 59, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 76, 77, 78, 79, 80, 81, 85, 86, 87, 88, 89, 93, 96, 97, 102], "data_in_a": 1, "adc_data": [1, 3, 5, 6, 7, 20, 31], "data_in_b": 1, "valid_in_a": 1, "valid_in_b": 1, "dac_sclk": 1, "serial": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 17, 18, 27, 29, 31, 32, 33, 34, 35, 36, 46, 51, 62, 63, 64, 66, 67, 76, 80, 85, 86, 88, 96, 97], "dac_csn": 1, "chip": [1, 2, 3, 4, 5, 6, 7, 8, 9, 41, 42, 43, 48, 51, 55, 63, 67, 69, 70, 71, 73, 74, 80, 87], "sdio_i": 1, "sdio_o": 1, "sdio_t": 1, "o": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 17, 18, 20, 24, 25, 29, 31, 32, 51, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 83, 85, 86, 87, 88, 89, 90, 93, 96, 97], "buffer": [1, 8, 12, 14, 29, 33, 35, 36, 42, 46, 52, 64, 66, 69, 70, 71, 72, 73, 74, 76, 85, 86, 87, 88, 102], "control": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 18, 19, 20, 23, 30, 31, 32, 36, 38, 39, 41, 42, 43, 44, 45, 51, 52, 53, 56, 57, 59, 63, 64, 65, 66, 67, 69, 70, 71, 76, 77, 79, 80, 85, 89, 96, 97, 98, 99, 100], "external_sync": [1, 21], "extern": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 14, 15, 16, 19, 20, 21, 23, 24, 25, 27, 28, 33, 34, 36, 38, 39, 40, 43, 46, 51, 59, 63, 66, 67, 69, 70, 71, 72, 73, 74, 75, 80, 86, 87, 88, 93, 96, 97, 98], "flag": [1, 3, 4, 5, 12, 14, 15, 19, 21, 27, 29], "anoth": [1, 2, 3, 4, 5, 6, 7, 9, 14, 15, 20, 25, 29, 31, 41, 51, 87, 96, 102], "sync_ext_devic": 1, "start_sync": 1, "top": [1, 3, 4, 5, 6, 7, 9, 13, 17, 18, 21, 23, 29, 42, 51, 72, 88, 89, 93, 96, 97, 101, 102], "instanti": [1, 3, 4, 5, 6, 7, 9, 12, 13, 16, 17, 18, 22, 24, 32, 42, 51, 62, 64, 70, 71, 79, 80, 85, 86, 89, 93, 96, 97, 98, 101, 102], "handl": [1, 3, 4, 5, 6, 7, 9, 13, 17, 18, 19, 24, 25, 26, 31, 32, 35, 43, 51, 88, 92, 96, 97], "state": [1, 2, 3, 4, 5, 6, 7, 9, 12, 14, 15, 16, 19, 21, 23, 25, 27, 29, 31, 32, 36, 39, 42, 43, 44, 45, 51, 52, 53, 87, 93, 96, 102], "machin": [1, 14, 16, 25, 29, 43, 45, 79, 85, 93], "quad": [1, 7, 12, 31, 32, 33, 34, 35, 62, 63, 67, 69, 73, 80], "spi": [1, 3, 4, 5, 6, 7, 9, 30, 47, 51, 89, 98, 99], "For": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 20, 21, 24, 25, 27, 29, 31, 32, 33, 34, 35, 36, 38, 39, 41, 51, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 83, 85, 86, 87, 88, 89, 92, 93, 96, 97, 98, 101, 102, 103], "common": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 17, 18, 31, 32, 38, 46, 51, 64, 69, 70, 71, 76, 85, 87, 88, 92, 96, 97, 98, 101], "ar": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 29, 31, 32, 33, 34, 35, 36, 37, 38, 39, 41, 42, 43, 44, 45, 46, 47, 50, 51, 52, 53, 54, 56, 57, 58, 60, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 83, 85, 86, 87, 88, 89, 91, 93, 95, 96, 97, 98, 100, 101, 102, 103, 104], "axi_ad3552r_dac_common": 1, "dword": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 27, 31, 32, 33, 34, 36, 51, 96, 97], "byte": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 31, 32, 33, 34, 36, 51, 52, 53, 55, 96, 97], "reg": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 31, 32, 33, 34, 36, 51, 93, 96, 97, 98], "field": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 31, 32, 34, 35, 36, 39, 51, 85, 93, 96, 97], "0x11": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16, 17, 18, 20, 23, 31, 32, 51, 73, 96, 97], "0x44": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16, 17, 18, 20, 23, 31, 32, 36, 51, 96, 97], "cntrl_1": [1, 8, 32, 97, 98], "statu": [1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16, 17, 18, 19, 20, 23, 24, 25, 27, 31, 32, 35, 36, 51, 52, 56, 57, 74, 89, 92, 96, 97, 98], "ext_sync_arm": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "rw": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 27, 31, 32, 33, 34, 36, 51, 96, 97, 98], "0x0": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 27, 31, 32, 33, 34, 36, 51, 62, 96, 97], "arm": [1, 2, 3, 4, 5, 6, 7, 8, 9, 17, 18, 21, 23, 31, 32, 51, 88, 89, 96, 97], "trigger": [1, 2, 3, 4, 5, 6, 7, 8, 9, 14, 20, 21, 23, 25, 28, 29, 30, 31, 32, 34, 38, 40, 41, 45, 46, 51, 54, 59, 64, 65, 96, 97, 99], "mechan": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 16, 25, 31, 32, 33, 46, 51, 96, 97], "sensit": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 64, 93, 96, 97], "sync": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 15, 17, 18, 23, 24, 25, 27, 29, 31, 32, 34, 36, 37, 39, 41, 43, 44, 51, 56, 73, 87, 96, 97], "onc": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 15, 22, 25, 31, 32, 33, 34, 44, 51, 87, 89, 96, 97, 101], "goe": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 73, 96, 97], "within": [1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 24, 29, 31, 32, 37, 51, 62, 72, 76, 87, 89, 96, 97, 98], "across": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 33, 34, 46, 51, 85, 89, 93, 96, 97, 103], "instanc": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 15, 16, 19, 21, 23, 24, 25, 31, 32, 33, 34, 36, 51, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 85, 86, 87, 88, 93, 96, 97, 98, 102], "effect": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 27, 31, 32, 33, 34, 36, 41, 51, 93, 96, 97], "onli": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 32, 33, 34, 35, 36, 39, 41, 42, 46, 51, 58, 59, 60, 62, 63, 64, 67, 70, 71, 73, 79, 80, 84, 85, 86, 87, 88, 89, 92, 93, 96, 97, 98, 101, 102, 103], "ext_sync": [1, 2, 3, 4, 5, 6, 7, 8, 9, 21, 31, 32, 51, 96, 97], "synthesi": [1, 2, 3, 4, 5, 6, 7, 8, 9, 22, 23, 25, 30, 51, 88, 93, 96, 97, 99, 102], "self": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 31, 32, 34, 51, 86, 96, 97], "clear": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 14, 15, 16, 17, 18, 19, 20, 23, 25, 27, 29, 31, 32, 33, 34, 36, 40, 51, 89, 96, 97], "0x12": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 16, 18, 20, 23, 29, 31, 32, 51, 73, 96, 97], "0x48": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 16, 18, 20, 23, 31, 32, 51, 96, 97], "cntrl_2": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "sdr_ddr_n": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97, 98], "repres": [1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 17, 18, 19, 24, 31, 32, 33, 34, 42, 51, 87, 96, 97], "symb_8_16b": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97, 98], "number": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 29, 31, 32, 33, 34, 35, 36, 39, 41, 43, 44, 45, 46, 48, 50, 51, 52, 53, 54, 56, 57, 58, 59, 60, 62, 63, 64, 65, 66, 67, 70, 71, 72, 73, 76, 77, 78, 79, 80, 85, 86, 87, 88, 89, 96, 97, 98, 101], "symbol": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 93, 96, 97], "format": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 14, 17, 18, 19, 24, 28, 29, 30, 31, 32, 33, 34, 38, 51, 84, 87, 96, 97, 103], "0x21": [1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 19, 23, 25, 27, 31, 32, 33, 34, 36, 51, 96, 97], "0x84": [1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 19, 23, 25, 27, 31, 32, 33, 34, 36, 51, 96, 97], "dac_custom_wr": [1, 8, 32, 97], "data_writ": 1, "0x000000": [1, 15, 18, 33, 34], "lsb": [1, 15, 23, 25, 31, 32, 33, 34, 56, 86], "0x22": [1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 19, 25, 27, 31, 32, 33, 34, 36, 51, 96, 97], "0x88": [1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 19, 25, 27, 31, 32, 33, 34, 36, 51, 96, 97], "ui_statu": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "if_busi": [1, 8, 32, 97], "ro": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 27, 31, 32, 33, 34, 36, 51, 96, 97, 98], "busi": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 15, 31, 32, 36, 40, 43, 46, 51, 64, 65, 76, 96, 97], "If": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 18, 19, 20, 21, 23, 24, 25, 27, 29, 31, 32, 33, 34, 35, 36, 37, 39, 40, 42, 45, 48, 51, 52, 53, 58, 59, 60, 71, 73, 87, 88, 89, 92, 95, 96, 97, 98, 102, 103], "indic": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 15, 16, 17, 18, 20, 22, 24, 25, 27, 29, 31, 32, 33, 34, 40, 43, 46, 51, 52, 53, 55, 56, 57, 76, 89, 93, 96, 97, 102], "0x23": [1, 2, 3, 4, 5, 6, 7, 8, 9, 16, 31, 32, 51, 96, 97], "0x8c": [1, 2, 3, 4, 5, 6, 7, 8, 9, 16, 31, 32, 51, 96, 97], "dac_custom_ctrl": [1, 8, 32, 97], "address": [1, 2, 3, 4, 5, 6, 7, 9, 12, 13, 22, 23, 25, 27, 31, 32, 35, 36, 39, 40, 48, 51, 52, 53, 58, 59, 60, 100], "0x00": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 14, 15, 16, 20, 22, 23, 24, 25, 27, 31, 32, 33, 34, 36, 39, 51, 96, 97], "start": [1, 2, 3, 4, 5, 6, 7, 9, 11, 12, 16, 17, 18, 20, 22, 23, 24, 25, 27, 29, 31, 32, 33, 34, 39, 40, 41, 44, 51, 55, 72, 73, 74, 75, 77, 78, 79, 85, 87, 89, 93, 96, 98, 101, 102], "fsm": [1, 23, 35], "transfer": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 14, 25, 27, 31, 32, 36, 40, 41, 46, 51, 52, 53, 55, 73, 87, 96, 97], "transfer_data": 1, "singl": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 15, 16, 23, 31, 33, 34, 38, 44, 46, 51, 56, 57, 64, 65, 69, 70, 71, 76, 86, 87, 88, 89, 93, 96, 98, 102], "access": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 27, 28, 29, 31, 32, 33, 34, 36, 38, 43, 44, 51, 63, 67, 80, 89, 96, 97, 98, 100], "return": [1, 10, 11, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 33, 34, 36, 89], "chang": [1, 5, 8, 9, 10, 11, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 27, 32, 33, 34, 36, 41, 46, 68, 73, 75, 77, 87, 89, 91, 92, 93, 97, 98, 101, 103], "axi_ad3552r_dac_channel": 1, "0x100": [1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 17, 18, 24, 25, 27, 31, 32, 33, 34, 36, 51, 96, 97], "0x400": [1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 17, 18, 22, 24, 31, 32, 51, 96, 97], "chan_cntrl0_7": 1, "dac_dds_sel": [1, 8, 24, 32, 97], "intern": [1, 12, 16, 23, 24, 27, 29, 31, 32, 33, 34, 36, 39, 41, 43, 44, 45, 46, 58, 60, 62, 64, 69, 70, 73, 74, 86, 87, 93, 96, 97, 100], "support": [1, 3, 4, 5, 6, 7, 8, 9, 12, 16, 20, 22, 23, 24, 27, 29, 36, 39, 42, 43, 46, 51, 52, 53, 56, 57, 58, 60, 62, 88, 91, 92, 94, 95, 96, 97, 102, 103, 104], "tone": [1, 8, 24, 32, 97], "0x01": [1, 8, 18, 19, 20, 24, 27, 32, 39, 97], "pattern": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 18, 20, 24, 29, 31, 32, 51, 96, 97], "sed": [1, 8, 24, 32, 97], "0x02": [1, 8, 24, 32, 33, 34, 36, 97], "0x03": [1, 8, 14, 24, 32, 33, 34, 97], "0x04": [1, 8, 24, 32, 36, 97], "invert": [1, 8, 24, 32, 62, 93, 97], "pn7": [1, 2, 3, 4, 5, 6, 7, 8, 9, 24, 31, 32, 51, 96, 97], "0x05": [1, 8, 15, 24, 32, 36, 97], "pn15": [1, 2, 3, 4, 5, 6, 7, 8, 9, 24, 31, 32, 51, 96, 97], "0x06": [1, 8, 24, 32, 97], "150": [1, 2, 3, 4, 5, 6, 7, 8, 9, 24, 31, 32, 51, 87, 96, 97], "0x07": [1, 8, 24, 32, 97], "0x08": [1, 8, 24, 32, 97], "loopback": [1, 2, 3, 4, 5, 6, 7, 8, 9, 24, 31, 32, 51, 96, 97], "0x09": [1, 8, 24, 32, 73, 97], "pnx": [1, 2, 3, 4, 5, 6, 7, 8, 9, 24, 31, 32, 51, 96, 97], "ad9361": [1, 2, 3, 4, 5, 6, 7, 8, 9, 23, 24, 31, 32, 51, 96, 97], "0x0a": [1, 2, 3, 4, 5, 6, 7, 8, 9, 24, 31, 32, 51, 73, 96, 97], "nibbl": [1, 2, 3, 4, 5, 6, 7, 8, 9, 24, 31, 32, 51, 55, 96, 97], "ramp": [1, 2, 3, 4, 5, 6, 7, 8, 9, 24, 31, 32, 51, 96, 97], "adrv9001": [1, 2, 3, 4, 5, 6, 7, 8, 9, 24, 31, 32, 51, 96, 97], "0x0b": [1, 2, 3, 4, 5, 6, 7, 8, 9, 24, 31, 32, 51, 96, 97], "0x116": 1, "0x458": 1, "chan_cntrl1_7": 1, "templat": [1, 30, 88, 102], "version": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 16, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 39, 51, 54, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 83, 85, 86, 87, 92, 93, 94, 96, 97, 98], "scratch": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 16, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51, 96, 97], "0x00000000": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 15, 16, 17, 18, 19, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51, 96, 97, 98], "0x1": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 27, 31, 32, 33, 34, 36, 51, 62, 96, 97], "0x4": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 16, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51, 96, 97], "identifi": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 15, 21, 25, 29, 31, 32, 33, 39, 51, 89, 93, 96, 97], "0x2": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 15, 16, 18, 19, 20, 21, 22, 23, 25, 27, 31, 32, 33, 34, 36, 51, 96, 97], "0x8": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 15, 16, 19, 20, 21, 22, 23, 24, 25, 27, 31, 32, 33, 34, 36, 51, 96, 97], "0x3": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 15, 16, 18, 19, 20, 21, 22, 23, 25, 31, 32, 33, 34, 36, 51, 96, 97], "0xc": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 15, 16, 20, 21, 22, 23, 25, 31, 32, 33, 34, 36, 51, 96, 97], "config": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 14, 18, 21, 25, 31, 32, 33, 34, 46, 51, 89, 96, 97, 101], "iqcorrection_dis": [1, 2, 3, 4, 5, 6, 7, 8, 9, 24, 31, 32, 51, 96, 97], "iq": [1, 2, 3, 4, 5, 6, 7, 8, 9, 24, 31, 32, 51, 96, 97], "correct": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 14, 16, 24, 29, 31, 32, 33, 34, 46, 51, 56, 58, 60, 62, 93, 96, 97], "wa": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 15, 16, 19, 22, 23, 25, 27, 31, 32, 33, 34, 35, 39, 40, 44, 51, 54, 64, 70, 71, 73, 85, 86, 87, 88, 89, 96, 97, 98, 102], "implement": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 16, 17, 18, 20, 22, 23, 24, 25, 28, 29, 31, 32, 33, 34, 35, 38, 40, 41, 43, 46, 50, 51, 52, 53, 62, 73, 78, 88, 89, 93, 95, 96, 97, 98, 102], "result": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 14, 16, 24, 31, 32, 36, 39, 51, 64, 70, 71, 73, 85, 86, 87, 93, 96, 97, 102], "dcfilter_dis": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "dc": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 67, 72, 78, 79, 96, 97], "filter": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 14, 16, 20, 25, 31, 32, 46, 51, 63, 64, 66, 67, 70, 71, 72, 74, 80, 90, 96, 97], "dataformat_dis": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "userports_dis": [1, 2, 3, 4, 5, 6, 7, 8, 9, 24, 31, 32, 51, 96, 97], "relat": [1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 20, 31, 32, 33, 34, 51, 96, 97, 98, 102], "decim": [1, 2, 3, 4, 5, 6, 7, 8, 9, 14, 20, 30, 31, 32, 51, 63, 64, 67, 72, 80, 96, 97, 99], "mode_1r1t": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "sheet": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 64, 85, 96, 97], "delay_control_dis": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "delai": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 14, 16, 20, 21, 23, 24, 31, 32, 33, 38, 39, 43, 45, 46, 48, 51, 52, 96, 97], "cmos_or_lvds_n": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "cmo": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51], "lvd": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 35, 51, 72, 74, 84, 87, 88, 102], "pps_receiver_en": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "pp": [1, 2, 3, 4, 5, 6, 7, 8, 9, 23, 31, 32, 51, 96, 97], "receiv": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 15, 17, 18, 23, 25, 27, 29, 31, 32, 34, 35, 36, 37, 39, 43, 45, 46, 51, 56, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 83, 85, 86, 87, 97, 102], "enabl": [1, 3, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 23, 24, 25, 27, 29, 31, 32, 33, 34, 35, 36, 40, 42, 44, 45, 51, 52, 53, 55, 56, 57, 58, 59, 60, 62, 63, 64, 67, 71, 72, 73, 80, 85, 87, 93, 96, 97], "scalecorrection_onli": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "scale": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 14, 24, 31, 32, 51, 73, 77, 96, 97], "must": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 15, 16, 17, 18, 19, 20, 21, 23, 24, 25, 29, 31, 32, 33, 34, 35, 39, 40, 48, 51, 56, 58, 60, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 85, 86, 87, 88, 89, 92, 93, 96, 97, 98, 102, 103], "transport": [1, 2, 3, 4, 5, 6, 7, 8, 9, 33, 34, 51, 73, 87, 96, 97, 101], "layer": [1, 2, 3, 4, 5, 6, 7, 8, 9, 33, 34, 46, 51, 62, 73, 77, 87, 96, 97, 101], "rd_raw_data": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "raw": [1, 2, 3, 4, 5, 6, 7, 8, 9, 14, 16, 25, 27, 31, 32, 33, 34, 36, 51, 78, 96, 97], "chan_raw_data": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "adc_channel": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "0x10": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 23, 25, 27, 31, 32, 33, 34, 36, 51, 96, 97], "pps_irq_mask": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "interrupt": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 19, 31, 32, 44, 51, 96, 97, 101], "mask": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 15, 16, 20, 27, 31, 32, 33, 34, 36, 51, 96, 97], "1pp": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "0x7": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 20, 25, 31, 32, 51, 96, 97], "0x1c": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 20, 25, 31, 32, 51, 96, 97], "fpga_info": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 31, 32, 51, 96, 97], "inform": [1, 2, 3, 4, 5, 6, 7, 8, 9, 13, 15, 16, 17, 18, 20, 22, 24, 25, 27, 41, 51, 52, 53, 55, 61, 88, 89, 91, 92, 95, 96, 97, 99], "adi_intel_device_info_enc": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "adi_xilinx_device_info_enc": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "axi_ad": [1, 2, 3, 4, 5, 6, 7, 8, 9, 24, 31, 32, 51, 96, 97], "0x40": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16, 17, 18, 20, 21, 23, 25, 27, 31, 32, 33, 34, 36, 51, 96, 97], "rstn": [1, 2, 3, 4, 5, 6, 7, 8, 9, 13, 16, 17, 18, 31, 32, 51, 96, 97], "ce_n": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "invers": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 33, 34, 39, 51, 62, 96, 97], "export": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 89, 96, 97, 102], "mmcm_rstn": [1, 2, 3, 4, 5, 6, 7, 8, 9, 13, 31, 32, 51, 96, 97], "mmcm": [1, 2, 3, 4, 5, 6, 7, 8, 9, 13, 31, 32, 51, 96, 97], "reset": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 23, 24, 25, 26, 27, 31, 32, 34, 36, 39, 40, 43, 44, 45, 50, 51, 52, 53, 55, 56, 57, 59, 66, 81, 93, 96, 97, 101], "drp": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 16, 31, 32, 51, 96, 97], "IN": [1, 2, 3, 4, 5, 6, 7, 8, 9, 13, 16, 31, 32, 51, 70, 73, 75, 78, 79, 81, 86, 87, 96, 97], "bring": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 16, 17, 18, 21, 31, 32, 33, 34, 51, 96, 97], "up": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 16, 17, 18, 20, 21, 23, 24, 25, 27, 31, 32, 33, 34, 36, 41, 51, 56, 57, 62, 63, 64, 66, 67, 69, 70, 71, 73, 74, 75, 80, 85, 89, 92, 96, 97, 98, 101, 102], "ext_sync_disarm": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "disarm": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "manual_sync_request": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 34, 51, 96, 97], "issu": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 33, 34, 51, 89, 96, 97, 102, 103], "event": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 14, 15, 20, 21, 23, 24, 25, 27, 28, 29, 31, 32, 33, 34, 37, 38, 39, 40, 45, 51, 96, 97], "hook": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "insid": [1, 2, 3, 4, 5, 6, 7, 8, 9, 14, 16, 19, 22, 31, 32, 41, 46, 51, 62, 88, 89, 92, 93, 96, 97, 98, 100, 101, 102], "fabric": [1, 2, 3, 4, 5, 6, 7, 8, 9, 24, 31, 32, 33, 34, 51, 73, 96, 97], "symb_op": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "num_lan": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 33, 34, 51, 96, 97], "activ": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 14, 15, 16, 17, 18, 21, 23, 25, 27, 31, 32, 33, 34, 36, 39, 40, 43, 44, 45, 51, 52, 53, 55, 56, 57, 73, 93, 96, 97, 100], "lane": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 25, 31, 32, 35, 51, 62, 64, 73, 87, 89, 96, 97, 98, 101], "cssi": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "lssi": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "par_typ": [1, 8, 32, 97], "pariti": [1, 8, 32, 97], "even": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 15, 27, 29, 31, 32, 33, 34, 40, 51, 59, 88, 93, 96, 97], "odd": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "par_enb": [1, 8, 32, 97], "frame": [1, 8, 17, 18, 23, 29, 31, 32, 33, 34, 35, 55, 73, 77, 87, 96, 97], "r1_mode": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "data_format": [1, 8, 32, 97], "complement": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 24, 31, 32, 51, 96, 97], "offset": [1, 2, 3, 4, 5, 6, 7, 8, 9, 13, 21, 22, 23, 24, 31, 32, 33, 34, 51, 52, 53, 63, 64, 65, 66, 67, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 85, 86, 87, 88, 93, 96, 97], "binari": [1, 2, 3, 4, 5, 6, 7, 8, 9, 24, 31, 32, 51, 93, 96, 97], "NOT": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 24, 25, 31, 32, 51, 87, 89, 96, 97], "applic": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 14, 15, 22, 23, 24, 25, 27, 33, 34, 35, 36, 38, 47, 51, 64, 66, 68, 69, 75, 76, 77, 78, 85, 86, 89, 96, 97], "dac_dp_dis": [1, 8, 24, 32, 97], "reserv": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 15, 18, 22, 25, 29, 31, 32, 33, 34, 39, 48, 51, 93, 96, 97, 98], "na": [1, 8, 32, 97], "0x13": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 14, 18, 20, 23, 31, 32, 51, 73, 96, 97], "0x4c": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 14, 18, 20, 23, 31, 32, 51, 96, 97], "ratecntrl": [1, 8, 32, 97], "possibl": [1, 8, 11, 15, 16, 18, 23, 24, 25, 29, 32, 33, 34, 36, 38, 42, 46, 64, 76, 89, 92, 93, 97, 102, 103], "sampl": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 14, 15, 17, 18, 20, 24, 25, 29, 31, 32, 33, 34, 35, 36, 39, 51, 55, 56, 57, 59, 63, 64, 65, 67, 69, 70, 71, 72, 73, 74, 75, 77, 78, 79, 80, 86, 87, 96, 97], "0x14": [1, 8, 10, 11, 12, 14, 15, 19, 20, 21, 23, 25, 32, 33, 34, 36, 97], "0x50": [1, 8, 10, 12, 13, 14, 16, 20, 23, 27, 32, 64, 97], "usual": [1, 2, 3, 4, 5, 6, 7, 8, 9, 25, 31, 32, 51, 56, 57, 87, 88, 89, 96, 97, 103], "dci": [1, 8, 32, 97], "period": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 13, 16, 19, 21, 23, 24, 29, 31, 32, 33, 34, 46, 51, 96, 97], "puls": [1, 2, 3, 4, 5, 6, 7, 8, 9, 13, 19, 21, 23, 24, 31, 32, 34, 51, 96, 97], "0x15": [1, 2, 3, 4, 5, 6, 7, 8, 9, 14, 17, 18, 20, 23, 31, 32, 51, 96, 97], "0x54": [1, 2, 3, 4, 5, 6, 7, 8, 9, 14, 16, 17, 18, 20, 23, 31, 32, 51, 96, 97], "status1": [1, 8, 32, 97], "clk_freq": [1, 2, 3, 4, 5, 6, 7, 8, 9, 17, 18, 31, 32, 51, 96, 97], "rel": [1, 2, 3, 4, 5, 6, 7, 8, 9, 17, 18, 21, 23, 31, 32, 33, 34, 39, 51, 89, 96, 97], "processor": [1, 2, 3, 4, 5, 6, 7, 8, 9, 17, 18, 19, 31, 32, 33, 34, 51, 64, 73, 85, 88, 89, 96, 97, 100], "mani": [1, 2, 3, 4, 5, 6, 7, 8, 9, 17, 18, 23, 25, 31, 32, 33, 34, 51, 52, 53, 76, 78, 85, 87, 89, 93, 96, 97], "case": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 14, 15, 16, 17, 18, 19, 23, 24, 27, 29, 31, 32, 33, 34, 36, 39, 41, 46, 51, 52, 53, 55, 56, 57, 62, 70, 71, 85, 86, 87, 88, 89, 92, 93, 96, 97, 98, 102, 103, 104], "100mhz": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 16, 17, 18, 19, 20, 22, 26, 27, 31, 32, 33, 34, 46, 51, 96, 97], "unsign": [1, 2, 3, 4, 5, 6, 7, 8, 9, 17, 18, 19, 24, 27, 29, 31, 32, 33, 34, 51, 96, 97], "assum": [1, 2, 3, 4, 5, 6, 7, 8, 9, 17, 18, 19, 25, 29, 31, 32, 33, 34, 36, 42, 45, 46, 51, 54, 89, 92, 96, 97, 103], "minimum": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 17, 18, 19, 24, 31, 32, 33, 34, 39, 41, 46, 51, 66, 96, 97], "523khz": [1, 2, 3, 4, 5, 6, 7, 8, 9, 17, 18, 19, 31, 32, 33, 34, 51, 96, 97], "554thz": [1, 2, 3, 4, 5, 6, 7, 8, 9, 17, 18, 19, 31, 32, 51, 96, 97], "actual": [1, 2, 3, 4, 5, 6, 7, 8, 9, 14, 17, 18, 24, 29, 31, 32, 33, 34, 46, 51, 52, 53, 63, 64, 65, 66, 67, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 85, 86, 87, 88, 89, 91, 96, 97, 102], "clk_ratio": [1, 2, 3, 4, 5, 6, 7, 8, 9, 17, 18, 24, 31, 32, 51, 96, 97], "see": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 15, 17, 18, 21, 24, 27, 29, 30, 31, 32, 33, 34, 35, 41, 44, 46, 51, 56, 57, 62, 63, 64, 65, 66, 67, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 84, 85, 86, 87, 88, 89, 92, 96, 97, 98, 101, 102], "below": [1, 2, 3, 4, 5, 6, 7, 8, 9, 14, 16, 17, 18, 21, 24, 27, 29, 31, 32, 33, 34, 36, 46, 51, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 85, 86, 87, 88, 89, 91, 93, 96, 97], "note": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 15, 17, 18, 24, 25, 31, 32, 33, 34, 39, 51, 53, 55, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 83, 85, 86, 87, 92, 96, 97, 103], "mai": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 17, 18, 22, 25, 31, 32, 33, 34, 35, 39, 41, 42, 51, 56, 57, 79, 89, 92, 93, 96, 97, 102, 103], "same": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 14, 15, 17, 18, 20, 21, 23, 24, 25, 29, 31, 32, 33, 34, 37, 38, 39, 41, 44, 46, 51, 53, 56, 57, 62, 73, 80, 85, 88, 89, 93, 95, 96, 97, 98, 103], "consid": [1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 17, 18, 29, 31, 32, 33, 34, 51, 56, 57, 91, 96, 97], "calcul": [1, 2, 3, 4, 5, 6, 7, 8, 9, 16, 17, 18, 24, 31, 32, 33, 34, 41, 51, 63, 64, 65, 66, 67, 70, 71, 72, 76, 78, 79, 80, 85, 86, 96, 97], "final": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 17, 18, 20, 24, 31, 32, 34, 51, 55, 78, 88, 89, 96, 97], "0x16": [1, 2, 3, 4, 5, 6, 7, 8, 9, 14, 17, 18, 23, 24, 31, 32, 51, 96, 97, 98], "0x58": [1, 2, 3, 4, 5, 6, 7, 8, 9, 14, 17, 18, 23, 24, 31, 32, 51, 96, 97], "status2": [1, 8, 32, 97], "ratio": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 14, 17, 18, 21, 25, 31, 32, 33, 34, 51, 53, 58, 60, 62, 64, 70, 71, 78, 96, 97], "factor": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 14, 17, 18, 24, 31, 32, 35, 51, 57, 96, 97], "ani": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 16, 17, 18, 20, 23, 25, 27, 29, 31, 32, 33, 34, 35, 36, 46, 51, 56, 57, 58, 60, 78, 87, 89, 91, 92, 93, 95, 96, 97, 98, 102], "parallel": [1, 2, 3, 4, 5, 6, 7, 9, 17, 18, 24, 31, 32, 33, 34, 36, 43, 44, 50, 51, 63, 67, 80, 89, 96, 97], "convers": [1, 2, 3, 4, 5, 6, 7, 8, 9, 17, 18, 25, 31, 32, 33, 34, 51, 55, 64, 69, 74, 75, 86, 96, 97], "qdr": [1, 2, 3, 4, 5, 6, 7, 8, 9, 17, 18, 31, 32, 51, 96, 97], "0x17": [1, 2, 3, 4, 5, 6, 7, 8, 9, 13, 14, 18, 23, 31, 32, 51, 96, 97], "0x5c": [1, 2, 3, 4, 5, 6, 7, 8, 9, 13, 14, 18, 23, 31, 32, 51, 96, 97], "status3": [1, 8, 32, 97], "error": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 15, 16, 18, 27, 31, 32, 33, 34, 51, 55, 62, 72, 93, 96, 97, 102], "try": [1, 2, 3, 4, 5, 6, 7, 8, 9, 18, 31, 32, 51, 89, 93, 96, 97, 103], "0x18": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 14, 17, 18, 19, 20, 21, 23, 25, 31, 32, 33, 34, 51, 96, 97], "0x60": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 14, 17, 18, 23, 27, 31, 32, 51, 96, 97], "dac_clksel": [1, 8, 32, 97], "allow": [1, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 23, 24, 25, 27, 28, 29, 31, 32, 33, 34, 35, 36, 38, 39, 44, 45, 46, 51, 54, 56, 57, 59, 63, 64, 66, 67, 69, 72, 74, 76, 80, 86, 93, 97], "polar": [1, 2, 3, 4, 5, 6, 7, 8, 9, 23, 31, 32, 39, 51, 62, 96, 97], "its": [1, 8, 15, 16, 18, 19, 21, 23, 25, 27, 29, 32, 33, 34, 36, 38, 46, 47, 53, 56, 57, 63, 67, 74, 80, 87, 89, 92, 93, 97, 101, 102], "clk_edge_sel": [1, 8, 32, 97], "0x1a": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 18, 31, 32, 51, 96, 97], "0x68": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 18, 31, 32, 51, 96, 97], "sync_statu": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 34, 51, 96, 97], "dac_sync_statu": [1, 8, 32, 97], "Will": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 43, 51, 54, 96, 97], "while": [1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 21, 23, 25, 29, 31, 32, 33, 34, 36, 38, 51, 64, 68, 69, 70, 71, 76, 85, 89, 96, 97, 98], "wait": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 14, 15, 16, 21, 23, 29, 31, 32, 36, 39, 41, 51, 96, 97, 101], "0x70": [1, 2, 3, 4, 5, 6, 7, 8, 9, 13, 31, 32, 51, 96, 97], "drp_cntrl": [1, 2, 3, 4, 5, 6, 7, 8, 9, 13, 31, 32, 51, 96, 97], "28": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 25, 31, 32, 33, 34, 51, 55, 87, 88, 96, 97], "drp_rwn": [1, 2, 3, 4, 5, 6, 7, 8, 9, 13, 31, 32, 51, 96, 97], "doe": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 15, 16, 25, 27, 29, 31, 32, 33, 34, 39, 51, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 85, 86, 87, 89, 92, 93, 95, 96, 97, 98, 103], "includ": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 15, 27, 29, 31, 32, 33, 34, 35, 51, 64, 67, 69, 74, 75, 85, 89, 91, 93, 96, 97, 98, 101], "gtx": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 31, 32, 51, 62, 88, 96, 97], "drp_disabl": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "27": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 25, 31, 32, 33, 34, 51, 72, 87, 88, 96, 97], "drp_address": [1, 2, 3, 4, 5, 6, 7, 8, 9, 13, 31, 32, 51, 96, 97], "0x000": [1, 2, 3, 4, 5, 6, 7, 8, 9, 13, 15, 31, 32, 33, 34, 51, 96, 97], "more": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15, 18, 20, 21, 22, 23, 24, 25, 27, 29, 36, 40, 46, 51, 56, 57, 61, 88, 89, 91, 92, 93, 96, 97, 98, 101, 102], "than": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15, 16, 20, 22, 23, 24, 25, 31, 32, 33, 34, 36, 40, 51, 59, 63, 67, 78, 80, 88, 89, 93, 96, 97, 98, 101], "one": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 21, 22, 23, 24, 25, 27, 29, 31, 32, 33, 34, 35, 36, 39, 40, 41, 44, 46, 51, 55, 56, 57, 59, 62, 64, 72, 87, 88, 89, 92, 93, 96, 97, 98, 101, 102, 103], "primit": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 16, 31, 32, 42, 51, 62, 96, 97], "most": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 13, 25, 29, 31, 32, 42, 46, 51, 76, 79, 89, 96, 97, 102, 103], "signific": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 13, 25, 29, 31, 32, 35, 51, 96, 97], "0x0000": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 17, 18, 24, 27, 31, 32, 33, 34, 51, 96, 97], "backward": [1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 31, 32, 33, 34, 51, 96, 97], "0x1d": [1, 2, 3, 4, 5, 6, 7, 8, 9, 13, 31, 32, 51, 96, 97], "0x74": [1, 2, 3, 4, 5, 6, 7, 8, 9, 13, 31, 32, 51, 96, 97], "drp_statu": [1, 2, 3, 4, 5, 6, 7, 8, 9, 13, 31, 32, 51, 96, 97], "drp_lock": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "pll": [1, 8, 12, 13, 32, 35, 96, 97], "lock": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 13, 31, 32, 51, 89, 96, 97], "pend": [1, 2, 3, 4, 5, 6, 7, 8, 9, 13, 15, 31, 32, 33, 34, 36, 51, 96, 97], "0x1e": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "0x78": [1, 2, 3, 4, 5, 6, 7, 8, 9, 29, 31, 32, 51, 96, 97], "drp_wdata": [1, 2, 3, 4, 5, 6, 7, 8, 9, 13, 31, 32, 51, 96, 97], "0x1f": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "0x7c": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "drp_rdata": [1, 2, 3, 4, 5, 6, 7, 8, 9, 13, 31, 32, 51, 96, 97], "0x20": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 15, 16, 17, 20, 21, 23, 25, 27, 31, 32, 33, 34, 36, 51, 96, 97], "0x80": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 15, 16, 17, 21, 23, 25, 27, 31, 32, 33, 34, 36, 51, 96, 97], "dac_custom_rd": [1, 8, 32, 97], "custom": [1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 22, 31, 32, 33, 34, 35, 46, 51, 58, 60, 88, 92, 94, 96, 97, 98], "ui_ovf": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "rw1c": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 15, 16, 17, 18, 19, 20, 23, 25, 31, 32, 33, 34, 36, 51, 96, 97], "overflow": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 15, 17, 18, 24, 25, 31, 32, 51, 56, 60, 96, 97], "occur": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 15, 16, 27, 29, 31, 32, 33, 34, 36, 39, 40, 51, 96, 97], "dure": [1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 25, 27, 29, 31, 32, 33, 34, 39, 51, 62, 89, 96, 97, 98], "fifo": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 15, 20, 25, 29, 30, 31, 32, 41, 51, 54, 56, 57, 58, 60, 99], "ui_unf": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "underflow": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 14, 15, 17, 18, 25, 31, 32, 51, 58, 96, 97], "0x28": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 20, 31, 32, 51, 96, 97], "0xa0": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 31, 32, 33, 34, 51, 96, 97], "usr_cntrl_1": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "usr_chanmax": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "multiplex": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 19, 20, 24, 31, 32, 38, 51, 96, 97], "add": [1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 25, 31, 32, 41, 51, 52, 53, 73, 87, 88, 89, 90, 96, 97, 98, 101, 102, 104], "differ": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 14, 15, 16, 17, 19, 21, 23, 25, 29, 31, 32, 33, 34, 35, 37, 38, 41, 44, 46, 51, 52, 53, 55, 56, 62, 64, 73, 78, 80, 85, 86, 87, 88, 89, 92, 93, 96, 97, 103], "process": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 15, 16, 17, 18, 24, 25, 31, 32, 33, 34, 35, 36, 38, 39, 43, 46, 51, 58, 60, 66, 69, 76, 77, 78, 85, 88, 89, 92, 93, 96, 97, 102], "0x2e": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 19, 31, 32, 51, 96, 97], "0xb8": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 19, 31, 32, 51, 96, 97], "dac_gpio_in": [1, 8, 32, 97], "gpio": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 89, 96, 97, 102], "auxiliari": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "gpi": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "pin": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 14, 18, 19, 20, 39, 46, 51, 62, 63, 64, 66, 67, 69, 70, 71, 73, 75, 80, 81, 86, 88, 96, 97, 98, 100, 102], "0x2f": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 31, 32, 51, 96, 97], "0xbc": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 31, 32, 51, 96, 97], "dac_gpio_out": [1, 8, 32, 97], "gpo": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "gpio_dis": [1, 2, 3, 4, 5, 6, 7, 8, 9, 31, 32, 51, 96, 97], "n": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 15, 16, 23, 24, 27, 31, 32, 33, 34, 39, 46, 48, 51, 54, 62, 73, 77, 89, 93, 96, 97, 98, 102], "chan_cntrln_1": [1, 2, 3, 4, 5, 6, 7, 8, 9, 24, 31, 32, 51, 96, 97], "where": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 15, 16, 20, 22, 23, 24, 25, 27, 31, 32, 33, 34, 41, 46, 51, 64, 68, 73, 77, 87, 89, 92, 93, 96, 97, 98, 102], "dds_phase_dw": [1, 8, 24, 32, 97], "width": [1, 8, 10, 13, 16, 19, 21, 22, 23, 24, 29, 32, 33, 34, 36, 37, 43, 44, 45, 46, 49, 50, 51, 52, 53, 54, 56, 57, 58, 59, 60, 62, 93, 97, 98], "offer": [1, 8, 24, 32, 36, 38, 46, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 83, 85, 86, 87, 97], "hdl": [1, 2, 3, 4, 5, 6, 7, 8, 9, 24, 25, 31, 32, 41, 46, 51, 55, 82, 91, 94, 95, 96, 97, 101, 103, 104], "conjunct": [1, 8, 24, 32, 97], "chan_cntrl_9": [1, 8, 24, 32, 97], "chan_cntrl_10": [1, 8, 24, 32, 97], "info": [1, 8, 12, 14, 21, 22, 24, 29, 32, 36, 49, 62, 89, 97], "ad": [1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 25, 30, 31, 32, 35, 39, 46, 51, 63, 64, 65, 66, 67, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 85, 86, 87, 88, 89, 93, 96, 97, 98, 99, 101, 102], "dds_scale_1": [1, 8, 24, 32, 97], "amplitud": [1, 8, 11, 24, 32, 79, 97], "fix": [1, 8, 15, 22, 24, 32, 33, 34, 39, 41, 93, 97, 102], "point": [1, 8, 14, 15, 16, 22, 23, 24, 25, 32, 33, 34, 36, 37, 66, 89, 97], "sign": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 14, 24, 31, 32, 35, 51, 54, 96, 97, 102], "integ": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 14, 24, 31, 32, 33, 34, 51, 96, 97], "fraction": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 14, 24, 31, 32, 51, 96, 97], "run": [1, 3, 4, 5, 6, 7, 8, 9, 15, 19, 20, 21, 22, 23, 24, 25, 31, 32, 33, 34, 36, 46, 62, 64, 68, 70, 71, 72, 73, 74, 77, 85, 86, 87, 88, 89, 97, 98, 102, 103], "you": [1, 3, 4, 5, 6, 8, 9, 24, 25, 31, 32, 33, 34, 35, 51, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 85, 86, 87, 88, 89, 92, 95, 97, 98, 99, 101, 102, 103], "do": [1, 8, 12, 15, 16, 24, 25, 27, 32, 33, 34, 35, 36, 46, 52, 88, 89, 92, 93, 97, 102, 103], "both": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 15, 16, 20, 23, 24, 25, 27, 29, 31, 32, 33, 34, 37, 40, 51, 52, 53, 62, 63, 64, 67, 69, 70, 73, 80, 86, 88, 89, 93, 96, 97, 102], "0x4000": [1, 8, 24, 32, 97], "over": [1, 2, 3, 4, 5, 6, 7, 8, 9, 13, 15, 19, 21, 24, 27, 28, 31, 32, 33, 36, 38, 46, 51, 68, 78, 85, 89, 92, 96, 97], "tone_1_fullscal": [1, 8, 24, 32, 97], "scale_1": [1, 8, 24, 32, 97], "tone_2_fullscal": [1, 8, 24, 32, 97], "scale_2": [1, 8, 24, 32, 97], "0x101": [1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 17, 18, 24, 31, 32, 51, 96, 97], "0x404": [1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 17, 18, 24, 31, 32, 51, 96, 97], "chan_cntrln_2": [1, 2, 3, 4, 5, 6, 7, 8, 9, 24, 31, 32, 51, 96, 97], "dds_init_1": [1, 8, 24, 32, 97], "initi": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 15, 22, 23, 24, 31, 32, 33, 51, 57, 96, 97, 98], "dds_incr_1": [1, 8, 24, 32, 97], "accumul": [1, 8, 15, 24, 32, 55, 97], "Its": [1, 8, 15, 16, 24, 32, 33, 34, 97], "incr": [1, 8, 18, 24, 32, 97], "f_": [1, 8, 24, 32, 39, 46, 48, 97], "clkratio": [1, 8, 24, 32, 97], "f_out": [1, 8, 24, 32, 97], "f_if": [1, 8, 24, 32, 97], "clock_ratio": [1, 8, 24, 32, 97], "between": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 14, 15, 18, 19, 20, 21, 23, 24, 25, 29, 31, 32, 33, 34, 35, 37, 40, 41, 44, 46, 51, 52, 53, 55, 58, 60, 62, 75, 86, 88, 92, 96, 97, 102], "greater": [1, 8, 11, 16, 24, 32, 33, 34, 97], "chan_cntrl_1": [1, 8, 24, 32, 97], "increment": [1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 21, 24, 25, 31, 32, 33, 34, 36, 51, 96, 97, 98, 103], "extend": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 24, 31, 32, 34, 51, 54, 67, 70, 93, 96, 97], "0x102": [1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 18, 24, 31, 32, 51, 96, 97], "0x408": [1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 18, 24, 31, 32, 51, 96, 97], "chan_cntrln_3": [1, 2, 3, 4, 5, 6, 7, 8, 9, 24, 31, 32, 51, 96, 97, 98], "dds_scale_2": [1, 8, 24, 32, 97], "0x103": [1, 8, 15, 24, 32, 97], "0x40c": [1, 8, 15, 24, 32, 97], "chan_cntrln_4": [1, 2, 3, 4, 5, 6, 7, 8, 9, 24, 31, 32, 51, 96, 97], "dds_init_2": [1, 8, 24, 32, 97], "init": [1, 8, 22, 24, 32, 97], "dds_incr_2": [1, 8, 24, 32, 97], "0x104": [1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 24, 25, 31, 32, 33, 34, 36, 51, 96, 97], "0x410": [1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 24, 31, 32, 51, 96, 97], "chan_cntrln_5": [1, 8, 24, 32, 97], "dds_patt_2": [1, 8, 24, 32, 97], "dds_patt_1": [1, 8, 24, 32, 97], "0x105": [1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 24, 31, 32, 51, 96, 97], "0x414": [1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 24, 31, 32, 51, 96, 97], "chan_cntrln_6": [1, 8, 24, 32, 97], "iqcor_enb": [1, 2, 3, 4, 5, 6, 7, 8, 9, 24, 31, 32, 51, 96, 97], "dac_lb_owr": [1, 8, 24, 32, 97], "forc": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 24, 25, 31, 32, 51, 93, 96, 97], "dac_pn_owr": [1, 8, 24, 32, 97], "thei": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 15, 16, 22, 23, 24, 27, 29, 31, 32, 33, 34, 35, 37, 41, 46, 51, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 85, 86, 87, 89, 91, 93, 96, 97, 98, 104], "ignor": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 15, 20, 23, 24, 25, 27, 29, 31, 32, 33, 34, 51, 89, 92, 96, 97], "IF": [1, 8, 24, 31, 32, 33, 35, 87, 97], "0x106": [1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 24, 31, 32, 51, 96, 97], "0x418": [1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 24, 31, 32, 51, 96, 97], "chan_cntrln_7": [1, 8, 24, 32, 97], "0x107": [1, 8, 15, 24, 32, 97], "0x41c": [1, 8, 15, 24, 32, 97], "chan_cntrln_8": [1, 8, 24, 32, 97], "iqcor_coeff_1": [1, 2, 3, 4, 5, 6, 7, 8, 9, 24, 31, 32, 51, 96, 97], "equip": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 14, 17, 18, 24, 31, 32, 35, 51, 64, 76, 85, 86, 96, 97], "coeffici": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 14, 24, 31, 32, 51, 96, 97], "matrix": [1, 2, 3, 4, 5, 6, 7, 8, 9, 24, 31, 32, 51, 96, 97], "iqcor_coeff_2": [1, 2, 3, 4, 5, 6, 7, 8, 9, 24, 31, 32, 51, 96, 97], "q": [1, 2, 3, 4, 5, 6, 7, 8, 9, 24, 31, 32, 34, 51, 69, 73, 77, 96, 97], "0x108": [1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 24, 31, 32, 33, 34, 36, 51, 96, 97], "0x420": [1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 24, 31, 32, 51, 96, 97], "usr_cntrln_3": [1, 8, 24, 32, 97], "usr_datatype_b": [1, 2, 3, 4, 5, 6, 7, 8, 9, 24, 31, 32, 51, 96, 97], "big": [1, 2, 3, 4, 5, 6, 7, 8, 9, 24, 31, 32, 51, 96, 97], "endian": [1, 2, 3, 4, 5, 6, 7, 8, 9, 24, 31, 32, 51, 96, 97], "littl": [1, 2, 3, 4, 5, 6, 7, 8, 9, 24, 31, 32, 51, 96, 97], "usr_datatype_sign": [1, 2, 3, 4, 5, 6, 7, 8, 9, 24, 31, 32, 51, 96, 97], "usr_datatype_shift": [1, 2, 3, 4, 5, 6, 7, 8, 9, 24, 31, 32, 51, 96, 97], "amount": [1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 24, 31, 32, 33, 39, 46, 51, 96, 97], "right": [1, 2, 3, 4, 5, 6, 7, 8, 9, 19, 24, 27, 31, 32, 51, 89, 93, 96, 97], "shift": [1, 2, 3, 4, 5, 6, 7, 8, 9, 24, 31, 32, 39, 43, 45, 51, 96, 97], "total": [1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 24, 31, 32, 33, 34, 39, 41, 51, 89, 96, 97], "usr_datatype_total_bit": [1, 2, 3, 4, 5, 6, 7, 8, 9, 24, 31, 32, 51, 96, 97], "align": [1, 2, 3, 4, 5, 6, 7, 8, 9, 23, 24, 25, 31, 32, 35, 51, 56, 62, 93, 96, 97], "usr_datatype_bit": [1, 2, 3, 4, 5, 6, 7, 8, 9, 24, 31, 32, 51, 96, 97], "0x109": [1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 24, 31, 32, 51, 96, 97], "0x424": [1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 24, 31, 32, 51, 96, 97], "usr_cntrln_4": [1, 8, 24, 32, 97], "usr_interpolation_m": [1, 8, 24, 32, 97], "hold": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 14, 15, 16, 20, 22, 24, 27, 31, 32, 33, 34, 43, 46, 51, 70, 74, 96, 97], "interpol": [1, 8, 16, 24, 30, 32, 97, 99], "m": [1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 24, 31, 32, 33, 34, 39, 41, 51, 62, 87, 96, 97], "being": [1, 2, 3, 4, 5, 6, 7, 8, 9, 14, 15, 23, 24, 31, 32, 33, 34, 35, 39, 44, 46, 51, 54, 85, 88, 89, 92, 93, 96, 97, 103], "abov": [1, 2, 3, 4, 5, 6, 7, 8, 9, 12, 16, 18, 23, 24, 25, 27, 31, 32, 34, 36, 41, 42, 51, 58, 60, 88, 89, 93, 96, 97, 98, 102], "form": [1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 24, 25, 26, 31, 32, 33, 34, 35, 46, 51, 78, 87, 96, 97], "usr_interpolation_n": [1, 8, 24, 32, 97], "0x10a": [1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 24, 31, 32, 51, 96, 97], "0x428": [1, 2, 3, 4, 5, 6, 7, 8, 9, 15, 24, 31, 32, 51, 96, 97], "usr_cntrln_5": [1, 8, 24, 32, 97], "dac_iq_mod": [1, 8, 24, 32, 97], "complex": [1, 2, 3, 4, 5, 6, 7, 8, 9, 24, 29, 31, 32, 51, 63, 67, 80, 85, 93, 96, 97], "In": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 15, 16, 17, 18, 19, 23, 24, 25, 27, 31, 32, 33, 34, 36, 40, 42, 46, 51, 52, 53, 55, 62, 64, 67, 70, 71, 73, 74, 78, 85, 86, 88, 89, 92, 93, 96, 97, 98, 101, 102, 103, 104], "driven": [1, 8, 20, 24, 25, 27, 32, 36, 69, 70, 71, 88, 97, 100], "sequenc": [1, 2, 3, 4, 5, 6, 7, 8, 9, 19, 24, 27, 29, 31, 32, 33, 51, 71, 96, 97], "pair": [1, 8, 15, 24, 29, 32, 71, 97, 101], "dac_iq_swap": [1, 8, 24, 32, 97], "swap": [1, 8, 24, 32, 89, 97, 101], "take": [1, 6, 7, 8, 24, 25, 32, 33, 34, 35, 41, 44, 46, 52, 53, 78, 87, 88, 97, 98], "0x10b": [1, 8, 15, 24, 32, 97], "0x42c": [1, 8, 15, 24, 32, 97], "chan_cntrln_9": [1, 8, 24, 32, 97], "dds_init_1_extend": [1, 8, 24, 32, 97], "accord": [1, 3, 4, 8, 21, 24, 31, 32, 33, 34, 39, 53, 55, 97], "dds_incr_1_extend": [1, 8, 24, 32, 97], "phasedw": [1, 8, 24, 32, 97], "found": [1, 2, 5, 6, 8, 9, 13, 24, 25, 31, 32, 46, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 85, 86, 87, 88, 89, 90, 92, 93, 95, 96, 97, 98, 102, 104], "0x10c": [1, 8, 15, 16, 24, 32, 97], "0x430": [1, 8, 15, 24, 32, 97], "chan_cntrln_10": [1, 8, 24, 32, 97], "dds_init_2_extend": [1, 8, 24, 32, 97], "chan_cntrl_2": [1, 8, 24, 32, 97], "dds_incr_2_extend": [1, 8, 24, 32, 97], "done": [1, 3, 4, 5, 6, 7, 8, 9, 14, 15, 20, 23, 24, 31, 32, 33, 44, 51, 70, 71, 75, 85, 86, 89, 101, 103], "through": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 14, 15, 17, 18, 20, 21, 23, 24, 28, 29, 31, 32, 33, 34, 35, 36, 51, 56, 57, 59, 62, 64, 66, 73, 75, 78, 81, 87, 93, 95, 96, 97], "connect": [1, 3, 4, 5, 6, 7, 8, 9, 12, 18, 25, 27, 31, 32, 33, 34, 35, 36, 38, 40, 42, 44, 46, 51, 62, 93, 100, 101], "io": [1, 3, 4, 5, 6, 9, 11, 15, 17, 20, 33, 34, 46, 51, 62, 81, 88, 96, 97, 102], "move": [1, 3, 4, 5, 6, 7, 9, 15, 51], "befor": [1, 2, 3, 4, 5, 6, 7, 9, 11, 12, 15, 16, 19, 20, 23, 25, 29, 31, 33, 39, 48, 51, 52, 53, 59, 73, 89, 92, 93, 96, 98, 102, 103], "level": [1, 3, 4, 5, 6, 7, 9, 11, 14, 16, 20, 21, 24, 26, 27, 31, 32, 33, 34, 35, 36, 38, 39, 42, 43, 51, 52, 53, 66, 68, 71, 75, 76, 89, 93, 96, 97, 102], "program": [1, 3, 4, 5, 6, 8, 9, 12, 15, 17, 18, 27, 28, 34, 36, 38, 40, 45, 51, 74, 89, 92, 94], "your": [1, 3, 4, 5, 6, 9, 25, 35, 51, 62, 68, 73, 74, 77, 87, 90, 92, 98, 99, 102, 103], "linux": [1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 28, 29, 33, 34, 38, 51, 55, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 83, 85, 86, 87, 88, 102, 103], "dual": [1, 7, 8, 24, 25, 27, 29, 31, 32, 35, 38, 55, 64, 69, 71, 73, 75, 77, 78, 81, 88], "33": [1, 25, 63, 64, 67, 71, 73, 78, 79, 80, 81, 86, 87, 88], "mup": [1, 81], "multispan": [1, 81], "multi": [1, 12, 43, 81, 93, 98], "driver": [1, 2, 12, 15, 17, 18, 27, 28, 29, 30, 33, 34, 35, 38, 55, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 83, 85, 86, 87, 89, 99], "ad3552r_evb": 1, "adi": [1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15, 16, 20, 22, 25, 30, 31, 32, 33, 34, 35, 36, 46, 51, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 85, 86, 87, 89, 90, 92, 94, 95, 100, 103, 104], "7000": [1, 3, 4, 5, 6, 9, 51, 55, 63, 64, 65, 66, 67, 70, 71, 72, 73, 74, 76, 78, 79, 80, 81, 85, 86, 87, 88], "soc": [1, 3, 4, 5, 6, 9, 17, 18, 51, 64, 88, 89, 102], "overview": [1, 3, 4, 5, 6, 9, 28, 38, 51], "pinout": [1, 2, 3, 4, 5, 6, 9, 51], "s_axis_axi_aclks_axi_aresetnexternal_clkrx_db_irx_busyfirst_dataadc_dovfadc_clkadc_resetrx_cs_nrx_db_orx_db_trx_rd_nrx_wr_nadc_validadc_data_": 2, "adc_enable_": [2, 3, 4, 9], "axi_ad7606x": [2, 70, 92], "simpl": [2, 8, 15, 25, 33, 34, 39, 46, 52, 53, 57, 62, 70, 71, 90, 96, 102], "about": [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 14, 20, 22, 25, 27, 35, 36, 52, 53, 62, 87, 88, 89, 92, 98, 102], "framework": [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 20, 30, 31, 32, 37, 38, 43, 46, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 85, 86, 87, 89, 95, 96, 97, 102], "up_adc_channel": [2, 3, 4, 5, 6, 7, 51, 96], "up_adc_common": [2, 3, 4, 5, 6, 7, 9, 51, 96], "descript": [2, 12, 13, 15, 19, 22, 24, 26, 27, 29, 31, 32, 33, 34, 36, 37, 39, 40, 42, 43, 44, 45, 47, 48, 49, 50, 54, 55, 58, 60, 62, 63, 66, 67, 69, 70, 71, 72, 79, 80, 85, 86, 88, 93, 96, 97, 98, 100, 104], "regmap": [2, 5, 6, 7, 8, 21, 92, 96, 97, 98, 101], "dev_config": [2, 70], "defin": [2, 8, 11, 12, 15, 16, 18, 19, 20, 21, 23, 25, 28, 29, 32, 33, 34, 35, 37, 38, 43, 46, 52, 53, 56, 57, 58, 60, 62, 64, 70, 71, 73, 77, 85, 86, 87, 88, 89, 92, 93, 96, 97, 98, 100, 102], "which": [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 27, 28, 29, 33, 34, 35, 36, 37, 38, 39, 41, 42, 43, 45, 46, 48, 49, 51, 52, 53, 54, 59, 62, 64, 65, 66, 70, 73, 75, 78, 79, 81, 85, 87, 88, 89, 92, 93, 96, 97, 100, 102, 103], "adc_to_dma_n_bit": 2, "transmit": [2, 8, 11, 12, 14, 17, 18, 23, 25, 29, 32, 33, 35, 37, 43, 62, 64, 67, 73, 75, 87, 102], "32": [2, 8, 11, 15, 16, 22, 23, 24, 25, 29, 31, 32, 33, 34, 36, 43, 46, 52, 54, 56, 57, 58, 59, 60, 63, 64, 65, 66, 67, 70, 71, 72, 73, 76, 77, 78, 79, 80, 81, 85, 86, 87, 88, 93, 96, 97, 101], "adc_n_bit": 2, "external_clk": 2, "option": [2, 11, 12, 15, 18, 23, 25, 29, 32, 33, 34, 43, 46, 63, 64, 67, 69, 70, 72, 74, 76, 80, 85, 86, 89, 93, 96, 97, 101], "No": [2, 10, 12, 14, 29, 33, 34, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 83, 85, 86, 87, 93], "ye": [2, 64, 70], "adc_clk": [2, 3, 4, 5, 6, 7, 9, 10, 96], "adc_reset": [2, 3, 4, 70], "correspond": [2, 3, 4, 5, 6, 7, 8, 9, 12, 15, 16, 19, 20, 23, 31, 32, 33, 34, 39, 51, 73, 89, 96, 102], "rx_cs_n": 2, "rx_db_o": 2, "rx_db_i": 2, "rx_db_t": 2, "t": [2, 11, 15, 23, 24, 25, 26, 27, 29, 34, 39, 41, 48, 73, 77, 87, 89, 91, 92, 98, 102, 103], "iobuf": 2, "rx_rd_n": 2, "rx_wr_n": 2, "rx_busi": 2, "first_data": 2, "first": [2, 3, 4, 5, 6, 7, 8, 9, 14, 15, 17, 18, 19, 22, 23, 24, 27, 29, 31, 33, 34, 35, 36, 41, 44, 51, 52, 53, 56, 73, 87, 88, 89, 91, 93, 96, 97, 98, 101, 102, 103], "bu": [2, 3, 4, 5, 6, 7, 9, 10, 11, 15, 16, 20, 23, 24, 25, 26, 27, 28, 29, 31, 32, 33, 34, 36, 37, 38, 39, 43, 44, 45, 46, 51, 52, 53, 56, 57, 58, 60, 76, 78, 96, 97, 98, 100], "adc_dovf": [2, 3, 4, 5, 6, 7, 9, 31, 96], "adc_valid": [2, 3, 4, 5, 6, 7, 9, 20, 31], "show": [2, 21, 23, 31, 32, 33, 42, 62, 87, 89, 93, 100], "adc_data_": [2, 3, 4], "sever": [2, 7, 8, 17, 18, 33, 34, 55, 88, 89, 102], "like": [2, 8, 15, 24, 25, 33, 34, 68, 75, 87, 88, 89, 91, 96, 97, 98, 102, 103], "pwm": [2, 16, 19, 30, 46, 64, 99], "follow": [2, 3, 4, 5, 6, 7, 8, 9, 10, 14, 15, 16, 18, 19, 20, 21, 22, 23, 25, 27, 29, 31, 32, 33, 34, 35, 36, 37, 39, 42, 46, 51, 53, 55, 58, 60, 62, 63, 64, 65, 66, 67, 69, 70, 71, 72, 73, 75, 76, 77, 78, 79, 80, 85, 86, 87, 88, 89, 93, 94, 96, 97, 98, 100, 101, 102, 103], "tabl": [2, 8, 29, 33, 46, 62, 73, 74, 77, 87, 102], "present": [2, 8, 15, 22, 29, 33, 34, 38, 39, 44, 46, 47, 55, 57, 64, 74, 75, 87, 91, 95, 96, 97, 98, 102], "after": [2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 15, 16, 19, 20, 21, 23, 24, 25, 27, 29, 31, 33, 34, 36, 39, 40, 41, 44, 48, 51, 55, 63, 67, 80, 86, 89, 93, 95, 96, 98, 101, 102, 103], "detail": [2, 8, 12, 13, 15, 22, 33, 34, 73, 75, 87, 89, 95, 96, 97], "cntrl": [2, 3, 4, 5, 6, 7, 9, 17, 31, 51, 96], "ad7768": [2, 4, 5, 6, 7, 9, 30, 31, 38, 51, 79, 84, 96, 99], "ad777x": [2, 3, 5, 6, 7, 9, 30, 31, 51, 96, 99], "ddr_edgesel": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "rise": [2, 3, 4, 5, 6, 7, 8, 9, 11, 14, 16, 17, 18, 20, 27, 31, 32, 33, 34, 36, 51, 55, 96], "edg": [2, 3, 4, 5, 6, 7, 8, 9, 11, 14, 17, 18, 20, 21, 24, 31, 32, 33, 34, 35, 39, 51, 55, 64, 69, 86, 96], "fall": [2, 3, 4, 5, 6, 7, 8, 9, 11, 14, 16, 17, 18, 20, 24, 27, 31, 33, 36, 51, 55, 69, 96], "part": [2, 3, 4, 5, 6, 7, 8, 9, 15, 24, 31, 34, 35, 38, 41, 47, 51, 66, 68, 70, 74, 85, 86, 88, 89, 93, 96, 97, 100, 101, 102, 104], "success": [2, 3, 4, 5, 6, 7, 9, 12, 31, 51, 64, 69, 70, 71, 76, 85, 86, 89, 96], "remain": [2, 3, 4, 5, 6, 7, 9, 12, 31, 33, 34, 36, 39, 40, 51, 53, 66, 80, 93, 96], "how": [2, 3, 4, 5, 6, 7, 9, 15, 23, 25, 31, 33, 34, 46, 51, 52, 53, 58, 60, 63, 65, 66, 67, 68, 69, 70, 71, 73, 74, 76, 80, 87, 89, 90, 92, 94, 95, 96], "delin": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "incom": [2, 3, 4, 5, 6, 7, 8, 9, 17, 27, 31, 33, 43, 51, 96], "post": [2, 3, 4, 5, 6, 7, 9, 12, 31, 51, 96], "pin_mod": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "altern": [2, 3, 4, 5, 6, 7, 9, 15, 31, 51, 69, 73, 89, 96], "interleav": [2, 3, 4, 5, 6, 7, 9, 18, 31, 51, 56, 57, 64, 96], "group": [2, 3, 4, 5, 6, 7, 9, 15, 27, 31, 33, 51, 93, 96, 98], "cntrl_3": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "crc_en": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "custom_control": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "decod": [2, 3, 4, 5, 6, 7, 9, 12, 31, 33, 34, 51, 96], "adaq8092": [2, 3, 4, 5, 6, 7, 30, 31, 51, 96, 99], "random": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "adc_ctrl_statu": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "pn_err": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "pn": [2, 3, 4, 5, 6, 7, 9, 31, 32, 51, 96, 97], "pn_oo": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "oo": [2, 3, 4, 5, 6, 7, 9, 17, 18, 31, 51, 96], "over_rang": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "delay_cntrl": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "deprec": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "delay_sel": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "transit": [2, 3, 4, 5, 6, 7, 9, 11, 15, 21, 23, 25, 31, 33, 34, 39, 51, 96], "delay_rwn": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "directli": [2, 3, 4, 5, 6, 7, 9, 12, 18, 20, 31, 34, 36, 42, 51, 70, 85, 89, 96], "decrement": [2, 3, 4, 5, 6, 7, 9, 15, 31, 36, 51, 96], "delay_address": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "lower": [2, 3, 4, 5, 6, 7, 9, 11, 20, 25, 31, 33, 34, 44, 46, 51, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 83, 85, 86, 87, 93, 96, 97, 98], "delay_wdata": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "200": [2, 3, 4, 5, 6, 7, 9, 16, 25, 31, 51, 58, 60, 70, 96], "0x19": [2, 3, 4, 5, 6, 7, 9, 12, 17, 18, 31, 51, 96], "0x64": [2, 3, 4, 5, 6, 7, 9, 12, 14, 17, 18, 31, 51, 96], "delay_statu": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "delay_lock": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "fail": [2, 3, 4, 5, 6, 7, 9, 12, 16, 31, 51, 89, 92, 96, 102], "calibr": [2, 3, 4, 5, 6, 7, 9, 25, 31, 51, 64, 70, 96], "element": [2, 3, 4, 5, 6, 7, 9, 27, 29, 31, 51, 96], "delay_rdata": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "adc_sync": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "complet": [2, 3, 4, 5, 6, 7, 8, 9, 12, 15, 16, 23, 25, 27, 30, 31, 33, 34, 36, 40, 41, 44, 51, 68, 74, 77, 79, 84, 88, 93, 96, 102], "jesd204": [2, 3, 4, 5, 6, 7, 9, 12, 30, 31, 32, 51, 73, 77, 87, 92, 96, 99], "design": [2, 8, 10, 12, 13, 15, 16, 24, 25, 31, 32, 33, 34, 35, 38, 41, 42, 44, 46, 47, 55, 58, 60, 61, 83, 84, 89, 90, 92, 93, 94, 95, 96, 97, 100, 103], "adc_config_wr": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "adc_config_rd": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "ui_reserv": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "adc_config_ctrl": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "rd": [2, 3, 4, 5, 6, 7, 9, 31, 34, 51, 96], "wr": [2, 3, 4, 5, 6, 7, 9, 12, 31, 51, 96], "request": [2, 3, 4, 5, 6, 7, 8, 9, 12, 14, 15, 16, 27, 29, 31, 32, 51, 57, 91, 96, 100], "b1": [2, 3, 4, 5, 6, 7, 9, 24, 29, 31, 51, 62, 93, 96], "b0": [2, 3, 4, 5, 6, 7, 9, 24, 29, 31, 34, 43, 51, 93, 96], "captur": [2, 3, 4, 5, 6, 7, 9, 11, 20, 25, 29, 31, 33, 34, 51, 54, 64, 65, 73, 74, 79, 80, 96], "0x29": [2, 3, 4, 5, 6, 7, 9, 12, 19, 31, 51, 96], "0xa4": [2, 3, 4, 5, 6, 7, 9, 12, 19, 31, 51, 96], "adc_start_cod": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "word": [2, 3, 4, 5, 6, 7, 8, 9, 11, 24, 31, 33, 34, 36, 39, 40, 46, 48, 51, 52, 53, 59, 96], "startcod": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "start_code_dis": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "adc_gpio_in": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "adc_gpio_out": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "0x30": [2, 3, 4, 5, 6, 7, 9, 11, 12, 16, 20, 21, 27, 31, 33, 34, 36, 51, 96, 101], "0xc0": [2, 3, 4, 5, 6, 7, 8, 9, 12, 16, 21, 27, 31, 33, 34, 36, 51, 96], "pps_counter": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "counter": [2, 3, 4, 5, 6, 7, 9, 11, 12, 19, 20, 21, 23, 24, 31, 33, 39, 43, 51, 89, 93, 96], "count": [2, 3, 4, 5, 6, 7, 9, 11, 17, 20, 23, 27, 31, 32, 33, 36, 41, 51, 57, 64, 81, 93, 96, 97, 102], "cycl": [2, 3, 4, 5, 6, 7, 9, 11, 12, 13, 15, 16, 18, 21, 23, 24, 25, 26, 29, 31, 33, 34, 39, 41, 46, 51, 55, 57, 59, 64, 87, 96], "two": [2, 3, 4, 5, 6, 7, 8, 9, 11, 14, 15, 21, 22, 24, 25, 28, 29, 31, 33, 34, 35, 39, 44, 46, 51, 56, 57, 59, 62, 63, 64, 67, 80, 81, 87, 88, 89, 92, 93, 96, 97, 98, 100, 102], "0x31": [2, 3, 4, 5, 6, 7, 9, 12, 16, 27, 31, 33, 34, 36, 51, 96], "0xc4": [2, 3, 4, 5, 6, 7, 9, 12, 16, 27, 31, 33, 34, 36, 51, 96], "pps_statu": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "assert": [2, 3, 4, 5, 6, 7, 9, 12, 15, 16, 17, 19, 25, 27, 31, 32, 33, 34, 36, 37, 39, 40, 43, 45, 51, 52, 53, 55, 56, 57, 59, 96, 97], "mayb": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "chan_cntrln": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "adc_lb_owr": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "adc_data_sel": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "adc_pn_sel_owr": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "adc_pn_sel": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "0x9": [2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 20, 31, 51, 96], "adc_pn_type_owr": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "dcfilt_enb": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "format_signext": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "extens": [2, 3, 4, 5, 6, 7, 9, 31, 38, 51, 72, 89, 93, 96], "alwai": [2, 3, 4, 5, 6, 7, 8, 9, 11, 15, 17, 23, 24, 25, 27, 29, 31, 32, 33, 34, 36, 39, 46, 48, 51, 56, 57, 59, 64, 87, 88, 89, 92, 93, 96, 98, 102], "nearest": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "boundari": [2, 3, 4, 5, 6, 7, 9, 18, 25, 31, 33, 34, 51, 52, 53, 55, 96], "format_typ": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "format_en": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "modifi": [2, 3, 4, 5, 6, 7, 9, 16, 18, 23, 27, 31, 33, 34, 36, 39, 48, 51, 88, 89, 90, 94, 95, 96, 98, 102], "pn23": [2, 3, 4, 5, 6, 7, 8, 9, 31, 51, 96], "A": [2, 3, 4, 5, 6, 7, 9, 10, 11, 12, 14, 15, 16, 19, 22, 24, 25, 29, 31, 32, 33, 34, 38, 39, 44, 51, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 85, 86, 87, 88, 89, 90, 92, 96, 97, 98, 102], "respect": [2, 3, 4, 5, 6, 7, 8, 9, 12, 27, 31, 51, 58, 60, 72, 85, 93, 96, 102], "master": [2, 3, 4, 5, 6, 7, 9, 31, 51, 52, 53, 64, 96], "though": [2, 3, 4, 5, 6, 7, 9, 10, 12, 29, 31, 51, 89, 96, 103], "individu": [2, 3, 4, 5, 6, 7, 9, 23, 31, 33, 34, 42, 46, 51, 56, 57, 89, 93, 96, 97], "chan_statusn": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "crc_err": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "monitor": [2, 3, 4, 5, 6, 7, 8, 9, 12, 15, 16, 17, 35, 39, 51, 64, 74, 77, 78, 96, 97], "afterward": [2, 3, 4, 5, 6, 7, 8, 9, 31, 51, 88, 96, 98, 102], "status_head": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "header": [2, 3, 4, 5, 6, 7, 9, 27, 29, 31, 33, 34, 51, 80, 93, 96, 98], "sent": [2, 3, 4, 5, 6, 7, 8, 9, 27, 29, 31, 33, 34, 51, 96], "spuriou": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "mismatch": [2, 3, 4, 5, 6, 7, 9, 15, 17, 31, 33, 51, 89, 96], "Of": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "64": [2, 3, 4, 5, 6, 7, 8, 9, 15, 18, 23, 24, 25, 31, 32, 33, 34, 46, 51, 52, 53, 55, 56, 57, 58, 60, 72, 73, 77, 87, 88, 96], "consecut": [2, 3, 4, 5, 6, 7, 9, 15, 16, 17, 24, 31, 33, 34, 51, 64, 96, 100], "expect": [2, 3, 4, 5, 6, 7, 8, 9, 12, 15, 17, 31, 32, 33, 34, 51, 89, 96], "It": [2, 3, 4, 5, 6, 7, 8, 9, 12, 14, 15, 18, 20, 22, 24, 25, 26, 27, 28, 31, 32, 33, 34, 36, 37, 38, 39, 40, 43, 44, 46, 51, 52, 53, 54, 57, 59, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 83, 85, 86, 87, 88, 89, 96, 97, 98, 100, 102, 103], "match": [2, 3, 4, 5, 6, 7, 9, 15, 16, 23, 25, 31, 33, 34, 36, 51, 59, 93, 96, 98], "independ": [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 23, 24, 31, 33, 34, 51, 55, 63, 67, 77, 80, 88, 89, 93, 96, 100], "path": [2, 3, 4, 5, 6, 7, 9, 11, 14, 15, 17, 18, 19, 20, 24, 29, 31, 33, 34, 35, 46, 51, 52, 58, 60, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 75, 76, 77, 78, 79, 80, 81, 85, 86, 87, 88, 89, 91, 95, 96, 97, 98, 101, 102], "chan_raw_datan": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "adc_read_data": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "dcfilt_offset": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "remov": [2, 3, 4, 5, 6, 7, 9, 27, 31, 36, 51, 66, 67, 73, 79, 87, 89, 91, 96, 102], "known": [2, 3, 4, 5, 6, 7, 9, 31, 33, 51, 73, 89, 96], "dcfilt_coeff": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "pn9a": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "pn9": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "pn23a": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "0x5": [2, 3, 4, 5, 6, 7, 9, 11, 12, 15, 19, 20, 21, 23, 25, 31, 33, 34, 36, 51, 96], "0x6": [2, 3, 4, 5, 6, 7, 9, 11, 12, 19, 20, 21, 25, 31, 33, 34, 51, 96], "pn31": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "chan_usr_cntrln_1": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "chan_usr_cntrln_2": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "usr_decimation_m": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "usr_decimation_n": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "softspan": [2, 3, 4, 5, 6, 7, 9, 31, 51, 96], "featur": [2, 27, 29, 61, 63, 67, 69, 70, 72, 75, 76, 78, 80, 85, 89, 92, 94, 102], "thu": [2, 8, 15, 25, 36, 39, 41, 85, 88, 93, 103], "abl": [2, 16, 31, 32, 33, 34, 36, 37, 39, 44, 46, 89, 95, 101, 103], "other": [2, 8, 12, 14, 15, 16, 17, 22, 23, 24, 25, 29, 31, 32, 33, 34, 35, 36, 39, 40, 41, 43, 46, 56, 57, 64, 74, 78, 87, 88, 89, 92, 93, 96, 97, 98, 99, 100, 101, 102, 103], "mention": [2, 24, 87, 88, 89, 98], "wai": [2, 5, 15, 24, 25, 33, 34, 35, 41, 46, 74, 87, 89, 93, 102], "As": [2, 8, 12, 25, 33, 34, 39, 89, 104], "regard": [2, 6, 13, 15, 20, 22, 24, 33, 34, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 83, 85, 86, 87, 89, 92, 96, 97], "workflow": 2, "db": [2, 64, 71, 72], "don": [2, 25, 27, 29, 34, 89, 91, 92, 98, 102], "care": [2, 27, 29, 34, 44, 88], "besid": [2, 12, 33, 34, 46, 92, 96, 97], "wr_n": 2, "rd_n": 2, "also": [2, 3, 4, 5, 6, 7, 8, 11, 12, 14, 15, 16, 18, 20, 23, 24, 25, 27, 29, 32, 33, 34, 36, 39, 41, 46, 51, 64, 68, 72, 73, 74, 78, 85, 87, 88, 89, 93, 98, 102, 103], "order": [2, 7, 8, 12, 14, 15, 16, 20, 23, 25, 33, 34, 35, 36, 70, 87, 92, 93, 101, 102], "make": [2, 8, 16, 25, 31, 36, 38, 41, 44, 46, 47, 58, 60, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 85, 86, 87, 88, 91, 93, 95, 98, 101, 102, 103], "time": [2, 3, 4, 5, 8, 11, 15, 16, 19, 20, 22, 23, 24, 25, 29, 33, 34, 37, 38, 39, 40, 41, 43, 52, 53, 55, 60, 63, 64, 67, 80, 87, 88, 89, 92, 95, 101, 102, 103], "x": [2, 15, 21, 22, 33, 34, 35, 66, 69, 73, 77, 81, 88, 89, 96, 97], "db0": 2, "db2": 2, "obtain": [2, 8, 16, 17, 18, 22, 46, 88, 89, 93], "page": [2, 30, 46, 62, 73, 77, 81, 84, 87, 88, 90, 91, 92, 95, 96, 97, 102], "datasheet": [2, 8, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 85, 86, 87], "illustr": [2, 23, 55, 100], "recommend": [2, 15, 29, 31, 32, 33, 34, 36, 55, 89, 93, 95, 103], "provid": [2, 8, 12, 15, 16, 18, 20, 22, 23, 25, 27, 29, 31, 32, 33, 34, 35, 36, 39, 46, 52, 53, 55, 56, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 83, 85, 86, 87, 88, 90, 94, 95, 96, 97, 102], "document": [2, 7, 8, 12, 19, 22, 30, 33, 34, 55, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 84, 85, 86, 87, 88, 89, 92, 93, 94, 96, 97, 99, 102], "eval": [2, 8, 35, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 78, 79, 80, 81, 85, 86], "fmc": [2, 5, 6, 9, 17, 18, 35, 66, 68, 69, 70, 71, 72, 73, 75, 76, 77, 80, 81, 84, 85, 86, 87, 88, 92], "s_axis_axi_aclks_axi_aresetnclk_inadc_dovfready_indata_inadc_sshotadc_clkadc_resetadc_dataadc_syncadc_validadc_crc_ch_mismatchadc_enable_": 3, "adc_valid_": [3, 4], "axi_ad7768": [3, 72, 89, 92], "line": [3, 4, 5, 6, 8, 9, 17, 18, 19, 22, 25, 31, 32, 33, 34, 36, 42, 43, 44, 45, 46, 50, 51, 62, 64, 70, 87, 89, 91, 92, 93, 96, 97, 98, 102], "crc": [3, 4, 5, 6, 7, 9, 31, 33, 34, 51, 96], "real": [3, 4, 5, 15, 25, 52, 53], "quartu": [3, 4, 5, 7, 9, 23, 26, 27, 51, 88, 89, 92, 98, 102, 103], "axi_ad7768_if": 3, "axi_ad7768_ip": [3, 89], "axi_ad7768_hw": 3, "num_channel": [3, 31, 32], "domain": [3, 4, 5, 6, 9, 10, 14, 15, 18, 25, 26, 27, 31, 32, 33, 34, 36, 43, 44, 45, 46, 50, 52, 53, 56, 57, 59, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 75, 76, 77, 78, 79, 80, 81, 85, 86, 87, 93], "ready_in": [3, 4], "data_in": [3, 4, 54, 59, 93], "adc_sshot": 3, "shot": [3, 19, 25], "adc_crc_ch_mismatch": [3, 4], "deseri": [3, 4], "check": [3, 4, 12, 13, 14, 15, 16, 22, 25, 29, 33, 34, 36, 41, 46, 68, 73, 87, 88, 92, 103], "algorithm": [3, 4, 35, 78], "basic": [3, 4, 5, 6, 9, 28, 29, 51, 62, 89, 92, 93, 95], "oper": [3, 4, 5, 6, 7, 9, 16, 25, 27, 28, 29, 42, 46, 51, 52, 53, 63, 64, 66, 67, 68, 69, 70, 71, 72, 73, 74, 76, 77, 80, 85, 86, 87, 89, 93, 96], "own": [3, 4, 5, 6, 9, 15, 41, 89, 90, 99, 102], "suport": [3, 4], "s_axis_axi_aclks_axi_aresetnclk_inadc_dovfready_insync_adc_misodata_inadc_clkadc_resetsync_adc_mosiadc_validadc_crc_ch_mismatchadc_enable_": 4, "axi_ad777x": [4, 51, 92], "ad7770": 4, "ad7771": 4, "ad7779": 4, "axi_ad777x_if": 4, "axi_ad777x_ip": 4, "axi_ad777x_hw": 4, "sync_adc_mosi": 4, "syncron": 4, "sync_adc_miso": 4, "s_axis_axi_aclks_axi_aresetndelay_clkadc_clk_in_padc_clk_in_nadc_clk_in_padc_data_in_padc_data_in_nadc_or_in_padc_or_in_nadc_dovfadc_clkadc_rstadc_validadc_enableadc_dataaxi_ad9265": 5, "axi_ad9265": 5, "dev": [5, 6, 7, 9, 13, 31, 32], "adc_datapath_dis": [5, 9], "datapath": [5, 9, 33, 34, 62], "taken": [5, 9, 39, 48, 87, 102], "io_delay_group": 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29, 31, 32, 33, 34, 41, 55, 57, 87, 88, 89, 96, 97, 98], "along": [5, 9, 85, 96, 97, 103], "latenc": [5, 6, 9, 15, 28, 31, 34, 38, 46, 59, 72, 81], "prb": [5, 6, 7, 8, 32], "analyz": [5, 6, 11, 14, 30, 34, 99], "chan_cntrl_3": [5, 31], "up_delay_cntrl": [5, 6, 9], "dynam": [5, 6, 9, 11, 13, 20, 21, 25, 27, 32, 34, 35, 36, 48, 62, 64, 69, 72, 74, 75, 79, 86, 96, 97], "reconfigur": [5, 6, 9, 12, 13, 16, 22, 31, 32, 33, 62, 96, 97], "help": [5, 9, 33, 34, 35, 46, 70, 88, 95, 98, 102, 104], "compens": [5, 9, 10, 14, 16, 75], "trace": [5, 9], "pcb": [5, 9, 46, 72, 85], "procedur": [5, 6, 7, 27, 29, 33, 34, 88, 89, 102], "develop": [5, 6, 18, 35, 46, 63, 64, 67, 80, 81, 88, 89, 92, 93, 95, 96, 97, 102, 103], "nativ": [5, 6, 9], "card": [5, 6, 9, 64, 68, 70, 85, 88, 102], "125ebz": 5, "s_axis_axi_aclks_axi_aresetndelay_clkadc_clk_in_padc_clk_in_nadc_data_in_padc_data_in_nadc_or_in_padc_or_in_nadc_dovfadc_clkadc_validadc_enableadc_dataaxi_ad9467": 6, "axi_ad9467": [6, 89], "dev_if_delay_group": 6, "delay_refclk_frequ": 6, "refclk": [6, 12, 87], "axi_ad9467_if": [6, 97], "end": [6, 10, 11, 14, 15, 16, 20, 21, 23, 25, 27, 29, 36, 39, 62, 64, 69, 70, 88, 92, 93, 98, 102], "seri": [6, 7, 10, 12, 13, 14, 16, 18, 20, 38, 62, 88, 102], "look": [6, 25, 27, 33, 68, 75, 79, 87, 88, 89, 97, 98, 102], "ug472": [6, 13], "ug471": 6, "ug953": [6, 13], "ebz": [6, 35, 73, 84, 87, 89], "s_axis_axi_aclks_axi_aresetnrx_clkrx_sofrx_validrx_dataadc_dovfadc_sync_inadc_raddr_inrx_readyadc_clkadc_validadc_enableadc_dataadc_sync_outadc_raddr_outaxi_ad9671": 7, "octal": 7, "ultrasound": [7, 35], "af": 7, "demodul": [7, 69], "jesd": [7, 31, 32, 33, 34, 73, 87, 89], "altera": [7, 17, 18, 35, 52, 53, 56, 57, 58, 60, 96, 97], "axi_ad9671": 7, "supprt": 7, "quad_or_dual_n": 7, "rx_clk": [7, 55, 96], "40": [7, 16, 31, 32, 33, 34, 46, 62, 64, 69, 71, 72, 73, 76, 77, 79, 86, 87, 88, 97], "rx_sof": [7, 33, 96], "rx_valid": [7, 33, 96], "placehold": [7, 22, 91], "rx_data": [7, 96], "127": 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"surviv": [7, 35], "transceiv": [7, 12, 62, 77, 90, 96, 97, 98, 101, 102], "s_axis_axi_aclks_axi_aresetndac_clk_in_pdac_clk_in_ndac_dunfdac_ddata_": 8, "dac_clk_out_pdac_clk_out_ndac_data_out_pdac_data_out_ndac_div_clkdac_rstdac_validdac_enable_": 8, "resolut": [8, 15, 17, 18, 19, 31, 32, 33, 34, 46, 63, 67, 75, 79, 80, 86, 96, 97], "500": [8, 10, 14, 31, 33, 35, 38, 46, 73, 74, 75, 85], "msp": [8, 31, 33, 35, 38, 46, 64, 67, 69, 71, 73, 74, 75, 77, 80, 85, 86], "cover": [8, 19, 25, 102], "familiar": [8, 41, 92, 95], "better": [8, 24, 33, 41, 79, 89], "understand": [8, 35, 62, 89, 93, 95, 96, 97], "bist": 8, "test": [8, 15, 18, 31, 32, 33, 34, 46, 64, 76, 79, 86, 89, 102, 103, 104], "up_dac_common": [8, 97], "up_dac_channel": [8, 97], "architectur": [8, 12, 15, 33, 34, 35, 41, 62, 63, 64, 65, 66, 67, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 85, 86, 87, 93, 94, 102], "tree": [8, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 83, 85, 86, 87, 91], "entir": [8, 89, 93], "global": [8, 12, 89, 93, 102], "skew": [8, 33], "die": [8, 85], "On": [8, 12, 25, 27, 29, 70, 86, 89], "via": [8, 12, 15, 16, 22, 25, 31, 32, 33, 34, 36, 43, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 83, 85, 86, 87], "bufgce_div": 8, "dac_clk_in_p": [8, 51], "divid": [8, 20, 39, 43, 55, 62, 85, 87, 88, 92, 93, 102], "main": [8, 14, 16, 19, 20, 24, 25, 28, 33, 34, 38, 55, 58, 60, 64, 67, 89, 92, 93, 95, 96, 97, 102, 103], "purpos": [8, 11, 15, 16, 23, 33, 34, 35, 46, 64, 88, 93, 95, 98], "well": [8, 15, 23, 28, 33, 34, 35, 36, 37, 38, 40, 73, 74, 78, 89, 100], "consist": [8, 14, 22, 24, 28, 29, 33, 34, 37, 38, 40, 43, 44, 46, 49, 56, 57, 73, 81, 87, 93, 101], "per": [8, 12, 15, 17, 18, 20, 23, 26, 29, 31, 32, 33, 34, 39, 41, 56, 57, 62, 64, 70, 71, 72, 73, 77, 87, 89, 93, 96, 97, 101], "except": [8, 23, 25, 29, 64, 89, 93], "becaus": [8, 24, 25, 29, 39, 46, 52, 53, 56, 57, 58, 60, 64, 68, 71, 73, 75, 87, 88, 89, 91], "simpli": [8, 10, 25, 41, 46, 56, 57, 89, 102], "reflect": [8, 23, 25, 31, 32, 33, 34, 52, 53], "interest": [8, 29, 89], "upack": [8, 30, 58, 99], "serd": 8, "chosen": [8, 11, 20, 24, 25, 35], "we": [8, 21, 25, 33, 34, 35, 41, 46, 58, 60, 62, 73, 77, 88, 89, 92, 95, 98, 102, 104], "4096": [8, 15, 29, 52], "rule": [8, 23, 33, 34, 39, 58, 60, 88, 89, 93, 102], "less": [8, 11, 15, 16, 18, 20, 24, 29, 33, 34, 36, 59, 63, 64, 67, 80, 89], "destin": [8, 15, 46, 52, 53], "portabl": [8, 35, 102], "appear": [8, 12, 46, 88, 89, 101, 102], "newest": 8, "regardless": [8, 32, 33, 34, 39, 64, 70, 71], "carri": [8, 15, 29, 34, 37, 42, 49], "were": [8, 11, 15, 16, 17, 18, 19, 20, 23, 25, 27, 33, 34, 36, 64, 70, 71, 73, 85, 86, 87, 89, 98, 102], "s3": 8, "63": [8, 15, 17, 18, 25, 51, 52, 53, 56, 57, 58, 60, 77, 87, 88], "down": [8, 11, 19, 20, 25, 33, 34, 46, 88, 92], "48": [8, 67, 72, 73, 87, 88], "s2": 8, "47": [8, 67, 73, 87, 88], "s1": [8, 41, 70], "s0": [8, 41], "true": [8, 15, 18, 19, 21, 25, 33, 34, 41, 52, 70, 71, 93], "last": [8, 11, 15, 20, 25, 29, 33, 34, 36, 39, 89, 93, 96, 97, 98, 102], "oldest": 8, "differenti": [8, 34, 62, 64, 69, 70, 85, 93, 100], "dac_clk_out_": 8, "dac_clk_in_": 8, "dac_data_out_": 8, "dco": [8, 97], "engin": [8, 25, 27, 30, 42, 47, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 83, 85, 86, 87, 98, 99], "latch": [8, 43, 46, 64, 93], "dss": 8, "figur": [8, 46], "mean": [8, 14, 15, 16, 23, 25, 27, 29, 32, 33, 34, 36, 37, 40, 41, 44, 53, 62, 73, 77, 87, 88, 89, 92, 103], "find": [8, 15, 62, 73, 74, 75, 77, 78, 79, 87, 88, 89, 92, 95, 96, 97, 99, 101, 102], "proper": [8, 27, 34, 36, 68, 89, 103], "smp_dly": 8, "properli": [8, 15, 16, 29, 33, 34, 44, 92, 93], "adder": 8, "synchroniz": 8, "perform": [8, 15, 16, 31, 33, 34, 35, 38, 39, 46, 66, 68, 71, 72, 74, 75, 76, 77, 78, 85, 86, 89, 93, 102], "dac_div_clk": [8, 51], "written": [8, 11, 12, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 27, 29, 33, 34, 36, 40, 52, 53, 59, 70, 71, 87, 93], "0x1b": [8, 18], "sum": [8, 18, 24], "zero": [8, 12, 14, 15, 16, 17, 23, 25, 32, 52], "To": [8, 10, 11, 12, 14, 15, 16, 20, 21, 27, 29, 31, 32, 33, 34, 36, 41, 46, 58, 60, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 85, 86, 87, 89, 91, 92, 95, 96, 97, 100, 102], "continu": [8, 11, 14, 15, 16, 23, 24, 25, 27, 33, 34, 36, 63, 64, 65, 67, 79, 80, 89], "maintain": [8, 16, 33, 68, 102, 104], "unchang": 8, "These": [8, 14, 22, 33, 34, 35, 74, 75, 76, 87, 88, 89, 95, 96, 97, 98], "content": [8, 15, 22, 27, 29, 33, 34, 36, 40, 88, 89, 98], "give": [8, 18, 27, 33, 44, 59, 63, 67, 75, 80, 87, 89, 93], "what": [8, 16, 24, 25, 29, 36, 46, 58, 60, 74, 88, 89, 98], "devicetre": 8, "dac_dds_typ": 8, "polynomi": [8, 24, 32], "dac_dds_cordic_dw": 8, "dac_dds_cordic_phase_dw": 8, "dac_datapath_dis": 8, "sure": [8, 16, 31, 44, 89, 91, 98, 102, 103], "appropri": [8, 25, 42, 74, 96, 97], "dcop": 8, "dac_clk_in_n": [8, 51], "dac_clk_out_p": [8, 51], "dcip": 8, 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33, 34, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 85, 86, 87, 88, 89, 90, 91, 92, 96, 97, 98, 99, 101, 102, 104], "axi_adc_decim": 10, "anyth": [10, 35], "higher": [10, 11, 16, 33, 34, 44, 46, 68, 70, 71, 85], "lite": [10, 11, 12, 14, 15, 16, 20, 22, 23, 27, 31, 32, 33, 34, 36, 46, 73, 89, 98], "section": [10, 14, 15, 16, 24, 31, 32, 33, 34, 41, 64, 72, 73, 74, 75, 77, 87, 88, 89, 92, 93, 96, 97, 101, 102], "cic": [10, 14, 16], "programm": [10, 13, 14, 16, 19, 35, 38, 39, 43, 63, 64, 65, 66, 67, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 85, 86, 87, 88], "fir": [10, 14, 16, 90], "peripher": [10, 11, 13, 14, 16, 17, 18, 19, 20, 22, 23, 25, 26, 27, 28, 29, 35, 36, 43, 44, 45, 50, 51, 52, 53, 54, 56, 57, 58, 59, 60, 63, 67, 73, 80, 85, 87, 89, 96, 97, 98, 102], "correction_dis": [10, 14], "adc_data_a": 10, "adc_data_b": 10, "b": [10, 11, 14, 25, 46, 66, 69, 70, 72, 81, 86], "adc_valid_a": 10, "adc_valid_b": 10, "adc_dec_data_a": 10, "adc_dec_data_b": 10, "adc_dec_valid_a": 10, "adc_dec_valid_b": 10, "adc_data_r": 10, "adc_oversampling_en": 10, "oversampl": [10, 69, 70, 71], "some": [10, 14, 21, 24, 25, 27, 29, 33, 34, 41, 42, 46, 56, 57, 70, 71, 73, 75, 85, 86, 87, 88, 89, 92, 93, 94, 95, 97, 98, 102, 104], "lead": [10, 14, 15, 39, 53, 69, 72, 86, 93], "lot": [10, 89, 92, 102], "avoid": [10, 14, 15, 24, 25, 27, 46, 73, 93, 100], "reduc": [10, 23, 25, 31, 32, 33, 34, 35, 36, 39, 53, 55, 58, 60, 64, 69, 72, 85, 86, 93], "50": [10, 14, 16, 55, 66, 72, 73, 77, 79, 87, 88], "5000": [10, 12, 13, 14, 16], "50000": [10, 14], "At": [10, 14, 16, 33, 55, 87, 89, 95, 98, 102], "semant": [10, 14, 15, 16, 19, 20, 22, 23, 25, 27, 33, 34, 36, 98], "version_major": [10, 14, 15, 16, 19, 20, 22, 23, 25, 27, 33, 34, 36, 98], "0x0001": [10, 16, 19, 22, 25, 33, 34, 36], "version_minor": [10, 14, 15, 16, 19, 20, 22, 23, 25, 27, 33, 34, 36, 98], "version_patch": [10, 14, 15, 16, 19, 20, 22, 23, 25, 27, 33, 34, 36, 98], "debug": [10, 14, 15, 16, 19, 20, 22, 23, 25, 27, 33, 34, 36, 89, 103], "decimation_ratio": 10, "decimation_stage_en": 10, "filtered_decimation_ratio": 10, "05": [10, 15], "26": [10, 25, 87, 88], "correction_enable_b": [10, 14], "multipli": [10, 14, 24, 33, 34], "correction_coefficient_b": [10, 14], "correction_enable_a": [10, 14], "correction_coefficient_a": [10, 14], "correction_coeffici": [10, 14], "amplif": [10, 14], "s_axis_axi_aclks_axi_aresetnclkresettrigger_intrigger_idata_adata_bdata_valid_adata_valid_btrigger_otrigger_tdata_a_trigdata_b_trigdata_valid_a_trigdata_valid_b_trigtrigger_outtrigger_out_lafifo_depthaxi_adc_trigg": 11, "limit": [11, 18, 24, 31, 32, 33, 34, 46, 53, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 74, 75, 76, 77, 78, 79, 80, 81, 83, 85, 86, 88, 89, 93], "mix": [11, 20, 29, 93], "instrument": [11, 35, 64, 76, 78, 85], "axi_adc_trigg": 11, "limit_a": 11, "0x0014": 11, "threshold": [11, 15, 16, 33], "function": [11, 14, 15, 19, 20, 21, 25, 33, 34, 35, 41, 43, 46, 52, 64, 66, 72, 74, 77, 78, 88, 89, 93, 96, 97, 100, 101, 104], "trigger_function_a": 11, "0x0018": 11, "hysteresi": [11, 16], "0x001c": 11, "0x0024": 11, "0x0028": 11, "0x002c": 11, "ti": [11, 14, 20, 70, 96], "config_trigger_i": 11, "0x004": [11, 15, 33, 34], "m2k": 11, "eas": [11, 29, 64, 74, 85, 92, 96, 97], "daisi": [11, 66, 76], "io_select": [11, 20], "0x000c": 11, "mux": [11, 42], "trigger_mux_a": 11, "0x0020": 11, "combin": [11, 12, 20, 25, 27, 33, 34, 35, 36, 44, 72, 88, 93, 102], "trigger_mux_b": 11, "0x0030": 11, "trigger_out_control": 11, "0x0034": 11, "holdoff": 11, "trigger_holdoff": [11, 20], "0x0048": 11, "silent": 11, "trigger_delai": [11, 20], "0x0040": 11, "trigger_out_hold_pin": 11, "0x004c": 11, "sign_bit": 11, "out_pin_hold_n": 11, "trigger_in": [11, 20], "trigger_i": [11, 14, 20], "trigger_o": 11, "trigger_t": 11, "data_a": 11, "data_b": 11, "data_valid_a": 11, "data_valid_b": 11, "data_a_trig": 11, "embed": [11, 17, 18, 25, 33, 54, 72, 73, 88], "data_b_trig": 11, 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14, 20], "low_level": [11, 14, 20], "function_a": 11, "passthrough": 11, "hysteresis_a": 11, "OR": [11, 12, 20, 27, 36, 54, 93], "AND": [11, 20, 64], "xor": [11, 20], "negat": 11, "0x24": [11, 12, 16, 20], "limit_b": 11, "0xa": [11, 20], "function_b": 11, "trigger_function_b": 11, "0xb": [11, 20], "0x2c": [11, 12, 19, 20], "hysteresis_b": 11, "0xd": [11, 20], "0x34": [11, 20, 27, 29, 36], "embedded_trigg": 11, "keep": [11, 14, 15, 16, 24, 33, 87, 92, 98, 103], "futur": [11, 15, 22, 39, 89, 98], "feed": 11, "util_extract": [11, 54], "trigger_mux_out": [11, 20], "la": 11, "0xe": [11, 20], "0x38": [11, 20, 27, 36], "bypass": [11, 12, 17, 18, 20, 25, 34, 59, 64, 66, 70], "0xf": [11, 20], "0x3c": [11, 20, 36], "sinc": [11, 15, 20, 22, 27, 29, 33, 34, 39, 46, 53, 72, 87, 89, 98, 101], "condit": [11, 15, 20, 22, 27, 33, 34, 35, 38, 41, 64, 73, 76, 87, 96, 97], "met": [11, 20, 33, 34, 46, 89], "off": [11, 20, 72, 85, 89], "interv": [11, 16, 20, 21], "next": [11, 15, 19, 20, 23, 27, 29, 33, 34, 35, 40, 41, 46, 64, 87, 89, 93, 98], "until": [11, 12, 14, 15, 20, 24, 25, 27, 32, 33, 34, 36, 39, 40, 41, 44, 52, 53, 55, 64, 66], "load": [11, 15, 16, 19, 20, 21, 73], "inact": 11, "those": [11, 15, 16, 17, 18, 19, 20, 23, 25, 29, 33, 34, 36, 89, 96, 97, 102], "hardwar": [11, 12, 15, 16, 17, 18, 19, 20, 22, 23, 25, 29, 35, 36, 92, 94], "s_axis_axi_aclks_axi_aresetnm_axiup_pll_rstup_cm_": 12, "up_es_": [12, 62], "up_ch_": 12, "up_statusaxi_adxcvr": 12, "configur": [12, 20, 24, 35, 40, 41, 46, 61, 63, 66, 67, 74, 76, 78, 80, 88, 89, 96, 97, 98, 101, 102], "highspe": [12, 35], "There": [12, 14, 16, 20, 22, 23, 24, 25, 29, 35, 46, 58, 60, 64, 74, 88, 89, 92, 93, 98, 101, 102], "separ": [12, 17, 18, 33, 38, 46, 69, 73, 85, 87, 89, 91, 92, 93, 102], "due": [12, 33, 34, 41, 46, 62, 73, 77, 80, 87, 89], "small": [12, 25, 43, 58, 60, 77], "util_adxcvr": [12, 33, 34, 35, 61, 73, 77, 87, 101], "axi4": [12, 15, 31, 32, 33, 34, 36, 46, 52, 89, 98], "broadcast": [12, 27, 29], "statist": [12, 33, 35], "ey": [12, 18], "scan": [12, 93], "phy": [12, 34, 42, 55, 73, 77, 87], "adi_jesd204": 12, "link_manag": 12, "xcvr": [12, 87], "itself": [12, 25, 29, 33, 34, 89, 98], "stack": [12, 23, 29, 35], "identif": [12, 16, 21, 22, 23, 25, 31, 32], "num_of_lan": [12, 101], "xcvr_type": [12, 62], "gtpe2_not_support": [12, 62], "gtxe2": [12, 35, 62], "gthe2_not_support": [12, 62], "gtze2_not_support": [12, 62], "gthe3": [12, 35, 62], "gtye3_not_support": [12, 62], "gtre4_not_support": [12, 62], "gthe4": [12, 35, 62], "gtye4": [12, 35, 62], "gtme4_not_support": [12, 62], "link_mod": [12, 33, 34, 62], "64b66b": [12, 31, 33, 34, 62, 73, 77, 87], "8b10b": [12, 33, 34, 62, 73, 77, 87], "cyclon": [12, 87, 88], "stratix": 12, "fpga_voltag": [12, 13], "mv": [12, 13], "wich": 12, "suppli": [12, 22, 35, 64, 66, 69, 70, 71, 72, 76, 85, 86, 88], "tx_or_rx_n": [12, 62, 101], "otherwis": [12, 15, 19, 21, 25, 27, 33, 34, 40, 41, 89, 95, 96, 97, 102, 103], "qpll_enabl": [12, 62, 101], "qpll": [12, 62], "lpm_or_dfe_n": 12, "lpm": [12, 62], "Or": [12, 103], "dfe": [12, 62], "b000": [12, 15], "tx_diffctrl": 12, "diffctrl": 12, "b01000": 12, "tx_postcursor": 12, "postcursor": 12, "b00000": 12, "tx_precursor": 12, "precursor": 12, "sys_clk_sel": 12, "sy": [12, 22], "sel": [12, 62], "b11": [12, 93], "out_clk_sel": 12, "b100": [12, 33], "subordin": [12, 14, 27, 36, 37, 43, 44, 45, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 85, 86, 87, 98, 100], "mhz": [12, 25, 31, 33, 35, 46, 55, 58, 60, 62, 64, 66, 73, 75, 77, 87, 93], "m_axi": [12, 15, 52, 53], "m_axi_awaddr": 12, "m_axi_awprot": 12, "m_axi_awvalid": 12, "m_axi_awreadi": 12, "m_axi_wdata": 12, "m_axi_wstrb": 12, "m_axi_wvalid": 12, "m_axi_wreadi": 12, "m_axi_bresp": 12, "m_axi_bvalid": 12, "m_axi_breadi": 12, "m_axi_araddr": 12, "m_axi_arprot": 12, "m_axi_arvalid": 12, "m_axi_arreadi": 12, "m_axi_rdata": 12, "m_axi_rresp": 12, "m_axi_rvalid": 12, "m_axi_rreadi": 12, "up_pll_rst": [12, 101], "up_cm_": [12, 62], "pll_lock": 12, "fpll": 12, "up_statu": 12, "axi_xcvr": 12, "gp": 12, "w": [12, 15, 35, 39, 48, 93], "resetn": [12, 23, 25, 43, 44, 50], "held": [12, 21], "report": [12, 31, 33], "status_32": 12, "up_pll_lock": 12, "channel_n_readi": 12, "generic_info": 12, "0x140": [12, 13, 16, 27], "board": [12, 18, 22, 25, 38, 46, 55, 89, 92, 94, 104], "power": [12, 15, 28, 33, 34, 38, 43, 46, 59, 63, 64, 66, 67, 69, 71, 72, 74, 76, 79, 80, 85, 86, 88, 102], "atx": 12, "stabl": [12, 15, 17, 33, 34, 40, 76, 89, 92], "automat": [12, 15, 20, 22, 25, 27, 33, 34, 36, 53, 64, 89, 102, 103], "just": [12, 15, 25, 46, 62, 73, 88, 89, 91, 92, 96, 97, 101, 102], "ident": 12, "basi": [12, 39, 44, 72, 78], "share": [12, 20, 25, 46, 62, 64, 73, 85, 101], "them": [12, 15, 16, 23, 33, 34, 44, 46, 85, 87, 88, 89, 93, 98, 101, 102, 103, 104], "chose": [12, 46], "equal": [12, 15, 16, 21, 23, 24, 33, 34, 36, 39, 58, 60, 93], "0x0008": 12, "swing": [12, 86], "transmitt": [12, 18, 31, 32, 33, 34, 35, 77, 78, 88], "cursor": 12, "pre": [12, 25, 28, 29, 34, 38, 43, 64], "emphasi": 12, "rxoutclk": 12, "txoutclk": 12, "bufstatus_rst": 12, "bufstatu": 12, "either": [12, 15, 16, 18, 20, 29, 33, 34, 35, 40, 46, 62, 72, 87, 88, 93, 102, 104], "els": [12, 35, 89, 93], "bufststatu": 12, "buftatu": 12, "consult": [12, 15, 85], "search": [12, 62, 89, 96, 97, 98, 101], "rxbufstatu": 12, "txbufstatu": 12, "pll_lock_n": 12, "cpll": [12, 62, 73, 77], "did": [12, 29, 33, 34], "lpm_dfe_n": 12, "sysclk_sel": 12, "sysclksel": 12, "gth": [12, 62, 88, 98], "gty": [12, 62, 88, 98], "pllclksel": 12, "indirectli": 12, "outclk_sel": 12, "01": [12, 22, 27, 33, 34, 55, 63, 67, 80], "aka": [12, 33, 34], "204b": [12, 31, 32, 33, 34], "204c": [12, 31, 32, 33, 34], "cm_sel": 12, "0xff": [12, 39], "cm_control": 12, "cm_wr": 12, "cm_addr": 12, "cm_wdata": 12, "cm_statu": 12, "cm_busi": 12, "idl": [12, 15, 23, 27, 39, 41], "cm_rdata": 12, "ch_sel": 12, "ch_control": 12, "ch_wr": 12, "ch_addr": 12, "ch_wdata": 12, "ch_statu": 12, "ch_busi": 12, "ch_rdata": 12, "es_sel": 12, "es_req": 12, "auto": [12, 19, 25, 88, 93, 102], "es_control_1": 12, "es_prescal": 12, "0x2a": [12, 19], "0xa8": [12, 19], "es_control_2": 12, "es_voffset_rang": 12, "es_voffset_step": 12, "es_voffset_max": 12, "es_voffset_min": 12, "0x2b": [12, 19], "0xac": [12, 19], "es_control_3": 12, "es_hoffset_max": 12, "es_hoffset_min": 12, "0xb0": [12, 19, 27], "es_control_4": 12, "es_hoffset_step": 12, "0x2d": [12, 19], "0xb4": [12, 19], "es_control_5": 12, "es_startaddr": 12, "es_statu": 12, "es_reset": 12, "es_resetn": [12, 98], "eyescanreset": [12, 98], "0x32": [12, 16, 27, 33, 34], "0xc8": [12, 16, 27, 33, 34], "0x180": [12, 27], "prbs_cntrl": 12, "prbsforceerr": 12, "checker": [12, 31], "side": [12, 15, 25, 41, 52, 53, 88, 93, 98], "prbscntreset": 12, "prbssel": 12, "put": [12, 15, 25, 33, 87, 89], "non": [12, 14, 15, 23, 33, 34, 89, 93, 94, 98, 102], "stop": [12, 14, 15, 21, 23, 25, 27, 29, 36, 39, 89], "normal": [12, 27, 32, 33, 34, 35, 56, 57, 89, 93], "dataflow": 12, "inject": 12, "instead": [12, 15, 20, 29, 33, 34, 42, 59, 64, 89, 93], "0x61": [12, 16, 19, 22, 23, 25, 33, 34], "0x184": 12, "prbs_statu": 12, "prbserr": 12, "sticki": 12, "prbslock": 12, "free": [12, 15, 19, 27, 36, 41, 63, 89, 93, 98, 101], "xclk": 12, "deassert": [12, 31, 32, 33, 40], "necessari": [12, 19, 25, 36, 62, 63, 64, 65, 67, 74, 80, 88, 89, 93, 96, 97, 102], "addr": [12, 33, 34, 41], "soon": [12, 25, 33, 34, 92], "reason": [12, 15, 23, 33, 34, 64, 89, 93, 102], "finish": [12, 14, 15, 16, 29, 41], "immun": 12, "abort": [12, 15], "further": [12, 22, 36], "That": [12, 57, 89, 103], "00": [12, 19, 22, 23, 25, 27, 36, 39, 55, 98], "qpll1": [12, 73], "qpll0": [12, 73, 77], "001": [12, 33], "010": [12, 33], "011": 12, "101": [12, 18, 67, 73], "outclkpc": 12, "outclkpma": 12, "progdivclk": 12, "expos": [12, 15, 46, 62], "gigabit": [12, 35, 55, 62, 96, 97], "without": [12, 14, 15, 16, 18, 25, 27, 29, 34, 35, 36, 40, 44, 54, 56, 57, 64, 79, 85, 93, 102, 103], "bringup": [12, 25], "under": [12, 23, 33, 34, 35, 46, 88, 89, 93, 98, 101], "exact": [12, 41], "record": [12, 15, 33, 34], "detect": [12, 16, 17, 20, 33, 55, 70, 78], "stai": [12, 15, 16, 32, 33, 34, 38, 40, 44], "alon": [12, 89], "suffici": [12, 29], "get": [12, 17, 24, 25, 33, 40, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 85, 86, 87, 88, 89, 92], "s_axis_axi_aclks_axi_aresetnclkclk2clk_": 13, "axi_clkgen": [13, 18, 46, 63, 64, 65, 66, 67, 69, 70, 71, 72, 74, 76, 79, 80, 81, 85, 86, 89], "wrapper": [13, 62, 89, 96, 97, 102], "ad_mmcm_drp": 13, "amd": [13, 16, 21, 30, 35, 52, 53, 56, 57, 58, 60, 73, 77, 84, 87, 94, 95, 103], "clksel_en": 13, "clksel": 13, "en": [13, 15, 31, 56, 62, 87, 88, 93], "clkin_period": 13, "clkin1": [13, 46], "clkin2_period": 13, "clkin2": 13, "vco_div": [13, 46], "divclk_divid": 13, "vco_mul": [13, 46], "clkfbout_mult_f": 13, "49": [13, 67, 72, 73, 87, 88], "clk0_div": [13, 46], "clkout0_divide_f": 13, "clk0_phase": 13, "clkout0_phas": 13, "clk1_div": 13, "clkout1_divid": 13, "clk1_phase": 13, "clkout1_phas": 13, "enable_clkin2": 13, "fals": [13, 15, 27, 36, 43, 45, 52, 93], "enable_clkout1": 13, "clk2": 13, "clk_": 13, "clk_sel": 13, "betwen": 13, "mmcm_statu": 13, "mmcm_lock": 13, "s_axis_axi_aclks_axi_aresetndac_clkdac_rstdac_data_adac_data_bdac_valid_adac_valid_bdma_valid_adma_valid_bdac_enable_adac_enable_btrigger_itrigger_adctrigger_ladma_ready_adma_ready_bdac_int_data_adac_int_data_bdac_valid_out_adac_valid_out_bunderflowaxi_dac_interpol": 14, "axi_dac_interpol": 14, "dac_data_a": 14, "dac_data_b": 14, "dac_valid_a": 14, "dac_valid_b": 14, "dma_valid_a": 14, "dma_valid_b": 14, "dma_ready_a": 14, "dma_ready_b": 14, "dac_enable_a": 14, "dac_enable_b": 14, "dac_int_data_a": 14, "dac_int_data_b": 14, "dac_valid_out_a": 14, "dac_valid_out_b": 14, "trigger_adc": [14, 20], "trigger_la": 14, "too": [14, 19, 34, 58, 60, 87, 101, 103], "bad": 14, "usb": [14, 88], "bandwidth": [14, 18, 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15, "burst_": [15, 23], "cross": [15, 18, 25, 33, 46, 52, 53], "4kb": [15, 25], "interface_description_2": 15, "cache_": 15, "axi_": [15, 96, 97], "axcach": 15, "axprot": 15, "irq_mask": [15, 16, 27, 36], "transfer_complet": 15, "transfer_queu": 15, "irq_pend": [15, 16, 19, 27, 33, 34, 36], "queu": 15, "queue": 15, "irq_sourc": [15, 16, 19, 27, 33, 34, 36], "togeth": [15, 16, 19, 22, 38, 47, 81, 87, 101], "hwdesc": 15, "resum": 15, "again": [15, 89, 102], "transfer_id": 15, "transfer_don": 15, "transfer_submit": 15, "back": [15, 18, 25, 33, 34, 41, 58, 62, 64, 93, 96, 97], "re": [15, 25, 33, 34, 38, 39, 40, 44, 45, 46, 64, 69, 87, 89, 91, 102, 104], "occurr": [15, 33, 34], "partial_reporting_en": 15, "partial": [15, 22, 25], "caus": [15, 24, 93], "eventu": 15, "dest_address": 15, "src_address": 15, "x_length": 15, "max": [15, 17, 18, 23, 24, 25, 33, 34, 42, 43, 46, 58, 60], "y_length": 15, "row": 15, "dest_strid": 15, "src_stride": 15, "transfer_0_don": 15, "transfer_1_don": 15, "transfer_2_don": 15, "transfer_3_don": 15, "partial_transfer_don": 15, "partial_transfer_length": 15, "partial_transfer_id": 15, "active_transfer_id": 15, "usag": [15, 33, 56, 57, 89, 93], "0x10d": 15, "0x434": 15, "current_dest_address": 15, "0x10e": 15, "0x438": 15, "current_src_address": 15, "0x112": [15, 18], "0x448": [15, 18], "transfer_progress": 15, "0x113": 15, "0x44c": 15, "partial_length": 15, "moment": [15, 33, 34, 52, 53], "smaller": [15, 22, 25, 33, 34, 35, 53], "0x114": [15, 16, 36], "0x450": 15, "0x115": 15, "0x454": 15, "descriptor_id": 15, "segment": 15, "0x11f": 15, "0x47c": 15, "sg_address": 15, "0x124": 15, "0x490": 15, "dest_address_high": 15, "bigger": [15, 53], "0x125": 15, "0x494": 15, "src_address_high": 15, "0x126": 15, "0x498": 15, "current_dest_address_high": 15, "0x127": 15, "0x49c": 15, "current_src_address_high": 15, "0x12f": 15, "0x4bc": 15, "sg_address_high": 15, "accept": [15, 18, 25, 27, 29, 32, 33, 34, 37, 39, 41, 69], "intent": [15, 25, 41, 93], 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39, 40, 48, 88, 89, 93], "primari": [15, 25, 33, 34], "distinguish": [15, 33, 34], "0x008": [15, 33, 34], "yield": [15, 27, 29, 33, 34], "previous": [15, 33, 34, 40], "associ": [15, 23, 27, 33, 34, 41, 76, 85], "0x00c": [15, 33, 34], "ensur": [15, 16, 18, 27, 29, 31, 32, 33, 34, 46, 62, 66], "exist": [15, 23, 33, 34, 36, 73, 77, 87, 88, 89, 97, 102, 103], "three": [15, 29, 34, 35, 36, 42, 52, 53, 56, 57, 62, 64, 67, 72, 78, 96, 97, 102], "close": [15, 33, 34, 35, 46, 89, 93], "particular": [15, 25, 29, 33, 34, 35, 46, 92, 93], "0x088": [15, 33, 34], "0x080": [15, 33, 34], "propag": [15, 27, 33, 34, 36], "prevent": [15, 33, 34, 102], "0x084": [15, 33, 34], "upstream": [15, 27, 33, 34, 36], "acknowledg": [15, 27, 29, 33, 34, 36, 100], "0x3ff": 15, "1079": 15, "1080": [15, 17, 18], "room": [15, 52, 53], "becom": [15, 33, 39, 41, 52, 53, 72], "specifi": [15, 16, 20, 22, 31, 32, 39, 53, 69, 72, 76, 86, 87, 88, 89, 92, 93, 100, 102, 103], "act": [15, 22, 25, 39], "ahead": 15, "intervent": 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101, 102, 103, 104], "vector": [15, 93], "call": [15, 88, 89, 92, 96, 97, 98, 100, 101, 102], "contigu": 15, "dedic": [15, 23, 24, 77, 85, 102], "bit0": 15, "next_sg_addr": 15, "bit1": 15, "rais": [15, 33], "dest_addr": 15, "src_addr": 15, "y_len": 15, "minu": [15, 33, 34], "x_len": 15, "dst_stride": 15, "replic": 15, "loop": [15, 58, 62, 64, 76], "similar": [15, 25, 29, 33, 34, 35, 85, 89, 101], "howev": [15, 16, 29, 33, 34, 73, 76, 80, 89], "distinct": 15, "advantag": [15, 29, 35], "fewer": [15, 35, 93], "treat": [15, 25, 39, 93], "improv": [15, 25, 64, 69, 72, 93], "primarili": [15, 18], "unit": [15, 43, 96, 97], "packet": [15, 25, 52, 53, 55], "begin": [15, 16, 23, 34, 91, 93], "qualifi": [15, 25, 31, 32, 93], "permiss": 15, "b1111": [15, 56, 57], "b010": [15, 33], "polici": 15, "leav": [15, 34, 42, 89, 93, 102], "mod": 15, "min": [15, 18, 24, 33, 43, 46], "widest": 15, "restrict": [15, 29, 62, 73], "relax": [15, 46, 64], "strobe": [15, 25], "discard": [15, 27, 29, 36], "fine": 15, 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"software-guidelines-1"], [51, "software-guidelines"], [62, "software-guidelines"]], "References": [[1, "references"], [2, "references"], [3, "references"], [4, "references"], [5, "references"], [6, "references"], [7, "references"], [8, "references"], [9, "references"], [10, "references"], [11, "references"], [13, "references"], [14, "references"], [16, "references"], [17, "references"], [18, "references"], [20, "references"], [51, "references"], [55, "references"], [62, "references"], [89, "references"], [96, "references"], [97, "references"], [100, "references"]], "AXI AD7606x": [[2, "axi-ad7606x"]], "Theory of operation": [[2, "theory-of-operation"]], "ADC Register Mode (AD7606x familiy)": [[2, "adc-register-mode-ad7606x-familiy"]], "ADC Read Mode (AD7606B/C-16)": [[2, "adc-read-mode-ad7606b-c-16"]], "ADC Read Mode (AD7606C-18)": [[2, "adc-read-mode-ad7606c-18"]], "ADC Read Mode with CRC enabled (AD7606B/C-16)": [[2, "adc-read-mode-with-crc-enabled-ad7606b-c-16"]], "ADC Read Mode with CRC enabled (AD7606C-18)": [[2, "adc-read-mode-with-crc-enabled-ad7606c-18"]], "ADC Read Mode with Status enabled (AD7606B/C-16)": [[2, "adc-read-mode-with-status-enabled-ad7606b-c-16"]], "ADC Read Mode with Status enabled (AD7606C-18)": [[2, "adc-read-mode-with-status-enabled-ad7606c-18"]], "ADC Read Mode with Status and CRC enabled (AD7606B/C-16)": [[2, "adc-read-mode-with-status-and-crc-enabled-ad7606b-c-16"]], "ADC Read Mode with Status and CRC enabled (AD7606C-18)": [[2, "adc-read-mode-with-status-and-crc-enabled-ad7606c-18"]], "Software Support": [[2, "software-support"], [15, "software-support"], [31, "software-support"], [32, "software-support"], [33, "software-support"], [34, "software-support"], [35, "software-support"], [55, "software-support"]], "AXI AD7768": [[3, "axi-ad7768"]], "AXI AD777x": [[4, "axi-ad777x"]], "AXI AD9265": [[5, "axi-ad9265"]], "AXI AD9467": [[6, "axi-ad9467"]], "AXI AD9671": [[7, "axi-ad9671"]], "AXI AD9783": [[8, "axi-ad9783"]], "Functional Description": [[8, "functional-description"]], "Device Interface Description": [[8, "device-interface-description"]], "Internal Interface Description": [[8, "internal-interface-description"]], "VALID": [[8, "valid"]], "ENABLE": [[8, "enable"]], "DATA": [[8, "data"]], "Parallel data port interface": [[8, "parallel-data-port-interface"]], "Calibration of the device": [[8, "calibration-of-the-device"]], "Register Map base addresses for axi_ad9783": [[8, "id2"]], "AXI ADAQ8092": [[9, "axi-adaq8092"]], "AXI ADC Decimate": [[10, "axi-adc-decimate"]], "AXI ADC Trigger": [[11, "axi-adc-trigger"]], "Submodules": [[11, "submodules"]], "AXI_ADXCVR": [[12, "axi-adxcvr"]], "Intel Devices": [[12, "intel-devices"]], "Parameters": [[12, "parameters"], [12, "parameters-1"], [24, "parameters"]], "Interfaces": [[12, "interfaces"], [12, "id3"], [17, "interfaces"], [18, "interfaces"], [28, "interfaces"], [35, "interfaces"], [38, "interfaces"], [47, "interfaces"], [100, "interfaces"]], "AMD Xilinx Devices": [[12, "amd-xilinx-devices"]], "Table 1": [[12, "table-1"]], "Table 2": [[12, "table-2"]], "Physical layer PRBS testing": [[12, "physical-layer-prbs-testing"]], "TX link procedure": [[12, "tx-link-procedure"]], "RX link procedure": [[12, "rx-link-procedure"]], "More Information": [[12, "more-information"], [31, "more-information"], [32, "more-information"], [33, "more-information"], [34, "more-information"], [62, "more-information"]], "Reference": [[12, "reference"]], "AXI CLK Generator": [[13, "axi-clk-generator"]], "AXI DAC Interpolate": [[14, "axi-dac-interpolate"]], "AXI DMAC": [[15, "axi-dmac"]], "Utilization": [[15, "utilization"], [25, "utilization"]], "Theory of Operation": [[15, "theory-of-operation"], [22, "theory-of-operation"], [23, "theory-of-operation"], [31, "theory-of-operation"], [32, "theory-of-operation"], [33, "theory-of-operation"], [34, "theory-of-operation"], [36, "theory-of-operation"], [40, "theory-of-operation"], [43, "theory-of-operation"], [44, "theory-of-operation"], [50, "theory-of-operation"], [55, "theory-of-operation"]], "HDL Synthesis Settings": [[15, "hdl-synthesis-settings"]], "Sizing of the internal store-and-forward data buffer": [[15, "sizing-of-the-internal-store-and-forward-data-buffer"]], "Interfaces and Signals": [[15, "interfaces-and-signals"], [25, "interfaces-and-signals"], [31, "interfaces-and-signals"], [32, "interfaces-and-signals"], [33, "interfaces-and-signals"], [34, "interfaces-and-signals"]], "Register Map Configuration Interface": [[15, "register-map-configuration-interface"], [25, "register-map-configuration-interface"], [33, "register-map-configuration-interface"], [34, "register-map-configuration-interface"]], "Data Interfaces": [[15, "data-interfaces"]], "AXI-Streaming subordinate": [[15, "axi-streaming-subordinate"]], "Configuration Interface": [[15, "configuration-interface"], [31, "configuration-interface"], [33, "configuration-interface"], [34, "configuration-interface"]], "Peripheral Identification": [[15, "peripheral-identification"]], "Interrupt Handling": [[15, "interrupt-handling"], [33, "interrupt-handling"], [34, "interrupt-handling"]], "Transfer Configuration": [[15, "transfer-configuration"], [15, "id2"]], "Transfer Submission": [[15, "transfer-submission"]], "Transfer Status": [[15, "transfer-status"]], "Transfer length reporting": [[15, "transfer-length-reporting"]], "Transfer Tear-down": [[15, "transfer-tear-down"]], "Interrupts": [[15, "interrupts"], [16, "interrupts"], [27, "interrupts"], [33, "interrupts"], [34, "interrupts"], [36, "interrupts"], [63, "interrupts"], [64, "interrupts"], [65, "interrupts"], [66, "interrupts"], [67, "interrupts"], [69, "interrupts"], [70, "interrupts"], [71, "interrupts"], [72, "interrupts"], [73, "interrupts"], [74, "interrupts"], [75, "interrupts"], [76, "interrupts"], [77, "interrupts"], [78, "interrupts"], [79, "interrupts"], [80, "interrupts"], [81, "interrupts"], [85, "interrupts"], [86, "interrupts"], [87, "interrupts"], [88, "interrupts"]], "2D Transfers": [[15, "d-transfers"]], "Cyclic Transfers": [[15, "cyclic-transfers"]], "Scatter-Gather Transfers": [[15, "scatter-gather-transfers"]], "Descriptor Structure": [[15, "descriptor-structure"]], "Transfer Start Synchronization": [[15, "transfer-start-synchronization"]], "Cache Coherency": [[15, "cache-coherency"]], "Diagnostics interface": [[15, "diagnostics-interface"]], "Limitations": [[15, "limitations"], [73, "limitations"], [87, "limitations"]], "AXI 4kByte Address Boundary": [[15, "axi-4kbyte-address-boundary"]], "Address Alignment": [[15, "address-alignment"]], "Transfer Length Alignment": [[15, "transfer-length-alignment"]], "Scatter-Gather Datapath Width": [[15, "scatter-gather-datapath-width"]], "Known Issues": [[15, "known-issues"]], "Technical Support": [[15, "technical-support"], [31, "technical-support"], [32, "technical-support"], [33, "technical-support"], [34, "technical-support"]], "Glossary": [[15, "glossary"]], "AXI Fan Control": [[16, "axi-fan-control"]], "Clocking": [[16, "clocking"], [22, "clocking"]], "Running independently": [[16, "running-independently"]], "Software control and customization": [[16, "software-control-and-customization"]], "AXI HDMI RX": [[17, "axi-hdmi-rx"]], "Detailed description": [[17, "detailed-description"], [18, "detailed-description"]], "Design considerations": [[17, "design-considerations"], [18, "design-considerations"]], "Software support": [[17, "software-support"], [18, "software-support"]], "AXI HDMI TX": [[18, "axi-hdmi-tx"]], "Examples for different data width configurations": [[18, "examples-for-different-data-width-configurations"]], "AXI Laser Driver": [[19, "axi-laser-driver"]], "AXI Logic Analyzer": [[20, "axi-logic-analyzer"]], "AXI PWM Generator": [[21, "axi-pwm-generator"]], "Channel phase alignment": [[21, "channel-phase-alignment"]], "Software bringup (software reset)": [[21, "software-bringup-software-reset"]], "Force align": [[21, "force-align"]], "Start at sync": [[21, "start-at-sync"]], "Timing Diagrams and examples": [[21, "timing-diagrams-and-examples"]], "AXI System ID": [[22, "axi-system-id"], [22, "id1"], [22, "id2"]], "System ID ROM": [[22, "system-id-rom"], [22, "id3"]], "Data Format": [[22, "data-format"]], "Common Header": [[22, "common-header"]], "Internal Use Area": [[22, "internal-use-area"]], "Working with the Core": [[22, "working-with-the-core"]], "AXI TDD": [[23, "axi-tdd"]], "AD Direct Digital Synthesis": [[24, "ad-direct-digital-synthesis"]], "DDS basics": [[24, "dds-basics"]], "ADI DDS module": [[24, "adi-dds-module"]], "Control": [[24, "control"]], "Config": [[24, "config"]], "DDS_SCALE": [[24, "dds-scale"]], "PHASE - DDS_INIT": [[24, "phase-dds-init"]], "FREQUENCY - DDS_INCR": [[24, "frequency-dds-incr"]], "STRUCTURE": [[24, "structure"]], "ad_dds": [[24, "id1"]], "ad_dds_2": [[24, "ad-dds-2"]], "ad_dds_1": [[24, "ad-dds-1"]], "ad_dds_sine_*": [[24, "ad-dds-sine"]], "CLOCK RATIO": [[24, "clock-ratio"]], "Data Offload": [[25, "data-offload"], [99, "data-offload"]], "General Use Cases": [[25, "general-use-cases"]], "Generic Architecture": [[25, "generic-architecture"]], "AXI4 Lite Memory Mapped Subordinate (S_AXI4_LITE)": [[25, "axi4-lite-memory-mapped-subordinate-s-axi4-lite"]], "Supported Data Interfaces": [[25, "supported-data-interfaces"]], "AXI4 Stream Interface (S_AXIS | M_AXIS)": [[25, "axi4-stream-interface-s-axis-m-axis"]], "AXIS Source and Destination Interface to the Storage Unit": [[25, "axis-source-and-destination-interface-to-the-storage-unit"]], "Initialization Request Interface": [[25, "initialization-request-interface"]], "Synchronization Modes": [[25, "synchronization-modes"]], "Clock Tree": [[25, "clock-tree"]], "Data Path": [[25, "data-path"]], "Used Storage Elements": [[25, "used-storage-elements"]], "Data Width Manipulation": [[25, "data-width-manipulation"]], "Xilinx\u2019s MIG vs. Intel\u2019s EMIF": [[25, "xilinx-s-mig-vs-intel-s-emif"]], "Internal Cyclic Buffer Support for the TX Path": [[25, "internal-cyclic-buffer-support-for-the-tx-path"]], "Control Path - Offload FSM": [[25, "control-path-offload-fsm"]], "Linux Driver": [[25, "linux-driver"]], "I3C Controller Core": [[26, "i3c-controller-core"]], "Signal and Interface Pins": [[26, "signal-and-interface-pins"], [27, "signal-and-interface-pins"], [31, "signal-and-interface-pins"], [32, "signal-and-interface-pins"], [36, "signal-and-interface-pins"], [43, "signal-and-interface-pins"], [44, "signal-and-interface-pins"], [45, "signal-and-interface-pins"], [50, "signal-and-interface-pins"]], "I3C Controller Host Interface": [[27, "i3c-controller-host-interface"]], "FIFO Threshold Interrupts": [[27, "fifo-threshold-interrupts"], [36, "fifo-threshold-interrupts"]], "Pending Interrupts": [[27, "pending-interrupts"]], "I3C Controller": [[28, "i3c-controller"]], "Sub-modules": [[28, "sub-modules"], [38, "sub-modules"], [47, "sub-modules"]], "Software": [[28, "software"], [38, "software"], [47, "software"]], "Control Interface": [[29, "control-interface"]], "Instruction Set Specification": [[29, "instruction-set-specification"]], "Command Descriptors": [[29, "command-descriptors"]], "CCC Instruction": [[29, "ccc-instruction"]], "Private Transfer": [[29, "private-transfer"]], "Command Receipts": [[29, "command-receipts"]], "Error codes": [[29, "error-codes"]], "In-Band Interrupts": [[29, "in-band-interrupts"]], "SDI and SDO": [[29, "sdi-and-sdo"]], "Dynamic Address Assignment": [[29, "dynamic-address-assignment"]], "Word Command Interface": [[29, "word-command-interface"]], "Configuration Registers": [[29, "configuration-registers"], [39, "configuration-registers"], [48, "configuration-registers"]], "Offload Interface": [[29, "offload-interface"]], "The Block RAM Offload": [[29, "the-block-ram-offload"]], "Debugging Tips": [[29, "debugging-tips"]], "IP Cores": [[30, "ip-cores"]], "ADC JESD204B/C Transport Peripheral": [[31, "adc-jesd204b-c-transport-peripheral"]], "Synthesis Configuration Parameters": [[31, "synthesis-configuration-parameters"], [32, "synthesis-configuration-parameters"]], "Link layer interface": [[31, "link-layer-interface"], [32, "link-layer-interface"]], "Application layer interface": [[31, "application-layer-interface"], [32, "application-layer-interface"]], "Clock Monitor": [[31, "clock-monitor"], [32, "clock-monitor"], [33, "clock-monitor"], [34, "clock-monitor"]], "Data Formatter": [[31, "data-formatter"]], "PRBS Check": [[31, "prbs-check"]], "External synchronization": [[31, "external-synchronization"], [32, "external-synchronization"]], "Restrictions": [[31, "restrictions"], [32, "restrictions"], [33, "restrictions"], [34, "restrictions"]], "Supported Devices": [[31, "supported-devices"], [32, "supported-devices"], [33, "supported-devices"], [34, "supported-devices"]], "JESD204B Analog-to-Digital Converters": [[31, "jesd204b-analog-to-digital-converters"], [33, "jesd204b-analog-to-digital-converters"], [35, "jesd204b-analog-to-digital-converters"]], "JESD204B RF Transceivers": [[31, "jesd204b-rf-transceivers"], [32, "jesd204b-rf-transceivers"], [33, "jesd204b-rf-transceivers"], [34, "jesd204b-rf-transceivers"], [35, "jesd204b-rf-transceivers"]], "JESD204B/C Mixed-Signal Front Ends": [[31, "jesd204b-c-mixed-signal-front-ends"], [32, "jesd204b-c-mixed-signal-front-ends"], [33, "jesd204b-c-mixed-signal-front-ends"], [34, "jesd204b-c-mixed-signal-front-ends"], [35, "jesd204b-c-mixed-signal-front-ends"]], "DAC JESD204B/C Transport Peripheral": [[32, "dac-jesd204b-c-transport-peripheral"]], "Data paths": [[32, "data-paths"]], "JESD204B Digital-to-Analog Converters": [[32, "jesd204b-digital-to-analog-converters"], [34, "jesd204b-digital-to-analog-converters"], [35, "jesd204b-digital-to-analog-converters"]], "JESD204B/C Link Receive Peripheral": [[33, "jesd204b-c-link-receive-peripheral"]], "AXI JESD204 RX Synthesis Configuration Parameters": [[33, "axi-jesd204-rx-synthesis-configuration-parameters"]], "JESD204 RX Synthesis Configuration Parameters": [[33, "jesd204-rx-synthesis-configuration-parameters"]], "AXI JESD204 RX Signal and Interface Pins": [[33, "axi-jesd204-rx-signal-and-interface-pins"]], "JESD204 RX Signal and Interface Pins": [[33, "jesd204-rx-signal-and-interface-pins"]], "JESD204 Control Signals": [[33, "jesd204-control-signals"]], "Transceiver Interface (RX_PHYn)": [[33, "transceiver-interface-rx-phyn"]], "User Data Interface (RX_DATA)": [[33, "user-data-interface-rx-data"]], "Peripheral Identification and HDL Synthesis Settings": [[33, "peripheral-identification-and-hdl-synthesis-settings"], [34, "peripheral-identification-and-hdl-synthesis-settings"]], "Link Control": [[33, "link-control"], [34, "link-control"]], "Multi-link Control": [[33, "multi-link-control"], [34, "multi-link-control"]], "Link Configuration": [[33, "link-configuration"], [34, "link-configuration"]], "SYSREF Handling": [[33, "sysref-handling"], [34, "sysref-handling"]], "Link Status": [[33, "link-status"], [34, "link-status"]], "Lane Status": [[33, "lane-status"]], "8B/10B Link Lane Status Fields": [[33, "b-10b-link-lane-status-fields"]], "64B/66B Link Lane Status Fields": [[33, "b-66b-link-lane-status-fields"]], "8B/10B Link ILAS Configuration Data": [[33, "b-10b-link-ilas-configuration-data"]], "8B/10B Link": [[33, "b-10b-link"], [34, "b-10b-link"]], "8B/10B Link State Machine": [[33, "b-10b-link-state-machine"], [34, "b-10b-link-state-machine"]], "RESET phase": [[33, "reset-phase"], [33, "axi-jesd204-rx-reset-phase-1"]], "WAIT FOR PHY phase": [[33, "wait-for-phy-phase"]], "CGS phase": [[33, "cgs-phase"]], "DATA phase": [[33, "data-phase"], [33, "axi-jesd204-rx-data-phase-1"]], "8B/10B Multi-endpoint RX link establishment": [[33, "b-10b-multi-endpoint-rx-link-establishment"]], "64B/66B Link": [[33, "b-66b-link"], [34, "b-66b-link"]], "64B/66B Link State Machine": [[33, "b-66b-link-state-machine"]], "WAIT BS phase": [[33, "wait-bs-phase"]], "BLOCK SYNC phase": [[33, "block-sync-phase"]], "64B/66B Link Extended MultiBlock Alignment State Machine": [[33, "b-66b-link-extended-multiblock-alignment-state-machine"]], "EMB INIT State": [[33, "emb-init-state"]], "EMB HUNT State": [[33, "emb-hunt-state"]], "EMB LOCK State": [[33, "emb-lock-state"]], "Dual clock operation": [[33, "dual-clock-operation"], [34, "dual-clock-operation"]], "64b/66b Link latency reduction": [[33, "b-66b-link-latency-reduction"]], "Additional Information": [[33, "additional-information"], [35, "additional-information"]], "JESD204B/C Link Transmit Peripheral": [[34, "jesd204b-c-link-transmit-peripheral"]], "AXI JESD204 TX Synthesis Configuration Parameters": [[34, "axi-jesd204-tx-synthesis-configuration-parameters"]], "JESD204 TX Synthesis Configuration Parameters": [[34, "jesd204-tx-synthesis-configuration-parameters"]], "AXI JESD204 TX Signal and Interface Pins": [[34, "axi-jesd204-tx-signal-and-interface-pins"]], "JESD204 TX Signal and Interface Pins": [[34, "jesd204-tx-signal-and-interface-pins"]], "JESD204B Control Signals": [[34, "jesd204b-control-signals"]], "Transceiver Interface (TX_PHYn)": [[34, "transceiver-interface-tx-phyn"]], "User Data Interface (TX_DATA)": [[34, "user-data-interface-tx-data"]], "ILAS Configuration Data": [[34, "ilas-configuration-data"]], "Manual Synchronization Request": [[34, "manual-synchronization-request"]], "Wait Phase (WAIT)": [[34, "wait-phase-wait"]], "Code Group Synchronization Phase (CGS)": [[34, "code-group-synchronization-phase-cgs"]], "Initial Lane Alignment Sequence Phase (ILAS)": [[34, "initial-lane-alignment-sequence-phase-ilas"]], "User Data Phase (DATA)": [[34, "user-data-phase-data"]], "8B/10B Multi-endpoint TX link establishment": [[34, "b-10b-multi-endpoint-tx-link-establishment"]], "Diagnostics": [[34, "diagnostics"]], "JESD204 Interface Framework": [[35, "jesd204-interface-framework"]], "How to Obtain a License": [[35, "how-to-obtain-a-license"]], "FPGA HDL Support": [[35, "fpga-hdl-support"]], "Physical Layer": [[35, "physical-layer"]], "Link Layer": [[35, "link-layer"]], "Transport Layer": [[35, "transport-layer"]], "Linux": [[35, "linux"]], "No-OS": [[35, "no-os"]], "Tutorial": [[35, "tutorial"]], "Example Projects": [[35, "example-projects"]], "Technical Articles": [[35, "technical-articles"]], "JESD204B Rapid Prototyping Platforms": [[35, "jesd204b-rapid-prototyping-platforms"]], "JESD204B Clocking Solutions": [[35, "jesd204b-clocking-solutions"]], "AXI SPI Engine Module": [[36, "axi-spi-engine-module"]], "FIFOs": [[36, "fifos"]], "Synchronization Events": [[36, "synchronization-events"]], "SYNC_EVENT Interrupt": [[36, "sync-event-interrupt"]], "SPI Engine Control Interface": [[37, "spi-engine-control-interface"]], "Signal Pins": [[37, "signal-pins"], [40, "signal-pins"], [42, "signal-pins"], [49, "signal-pins"]], "SPI Engine": [[38, "spi-engine"], [101, "spi-engine"]], "Related IP Cores": [[38, "related-ip-cores"], [47, "related-ip-cores"]], "Examples": [[38, "examples"], [47, "examples"], [88, "examples"]], "Additional Resources": [[38, "additional-resources"], [47, "additional-resources"]], "SPI Engine Instruction Set Specification": [[39, "spi-engine-instruction-set-specification"]], "Instructions": [[39, "instructions"], [48, "instructions"]], "Transfer Instruction": [[39, "transfer-instruction"], [48, "transfer-instruction"]], "Chip-Select Instruction": [[39, "chip-select-instruction"]], "Configuration Write Instruction": [[39, "configuration-write-instruction"]], "Synchronize Instruction": [[39, "synchronize-instruction"]], "Sleep Instruction": [[39, "sleep-instruction"]], "CS Invert Mask Instruction": [[39, "cs-invert-mask-instruction"]], "SPI Configuration Register": [[39, "spi-configuration-register"]], "Prescaler Configuration Register": [[39, "prescaler-configuration-register"]], "Dynamic Transfer Length Register": [[39, "dynamic-transfer-length-register"]], "SPI Engine Offload Control Interface": [[40, "spi-engine-offload-control-interface"]], "SPI Engine Pipeline Delays": [[41, "spi-engine-pipeline-delays"]], "Instruction Execution": [[41, "instruction-execution"]], "Detailed Delays": [[41, "detailed-delays"]], "Offload Module": [[41, "offload-module"]], "Interconnect Module": [[41, "interconnect-module"]], "Execution Module": [[41, "execution-module"]], "AXI Module": [[41, "axi-module"]], "SPI Bus Interface": [[42, "spi-bus-interface"]], "IO configuration": [[42, "io-configuration"]], "Example Verilog IO configuration": [[42, "example-verilog-io-configuration"]], "SPI Engine Execution Module": [[43, "spi-engine-execution-module"]], "SPI Engine Interconnect Module": [[44, "spi-engine-interconnect-module"]], "SPI Engine Offload Module": [[45, "spi-engine-offload-module"]], "SPI Engine Tutorial - PulSAR-ADC": [[46, "spi-engine-tutorial-pulsar-adc"]], "Evaluating the target device": [[46, "evaluating-the-target-device"]], "SPI Engine hierarchy instantiation": [[46, "spi-engine-hierarchy-instantiation"]], "SPI Engine reference clock": [[46, "spi-engine-reference-clock"]], "AD7984 Timing diagram": [[46, "ad7984-timing-diagram"]], "Sample rate control": [[46, "sample-rate-control"]], "DMA setup": [[46, "dma-setup"]], "System Top": [[46, "system-top"]], "System Constraints": [[46, "system-constraints"]], "Testbench": [[46, "testbench"]], "Evaluating the result": [[46, "evaluating-the-result"]], "Software section": [[46, "software-section"]], "Framework Template": [[47, "framework-template"]], "Template Instruction Set Specification": [[48, "template-instruction-set-specification"]], "Other Instruction": [[48, "other-instruction"]], "Yet Another Instruction": [[48, "yet-another-instruction"]], "Template Register": [[48, "template-register"]], "Template Interface": [[49, "template-interface"]], "Template Module": [[50, "template-module"]], "IP Template": [[51, "ip-template"]], "AXI Stream FIFO": [[52, "axi-stream-fifo"]], "Asymmetric AXI Stream FIFO": [[53, "asymmetric-axi-stream-fifo"]], "Status Signal Delays": [[53, "status-signal-delays"]], "FIFO Depth Calculation": [[53, "fifo-depth-calculation"]], "Util Extract": [[54, "util-extract"]], "Util MII to RMII": [[55, "util-mii-to-rmii"]], "Receive Transactions": [[55, "receive-transactions"]], "Transmit Transactions": [[55, "transmit-transactions"]], "Channel CPACK Utility": [[56, "channel-cpack-utility"]], "Channel UPACK Utility": [[57, "channel-upack-utility"]], "Util RFIFO": [[58, "util-rfifo"]], "Timing Diagram": [[58, "timing-diagram"]], "Util VAR FIFO": [[59, "util-var-fifo"]], "Util WFIFO": [[60, "util-wfifo"]], "AMD Xilinx Specific IPs": [[61, "amd-xilinx-specific-ips"]], "UTIL_ADXCVR core for AMD Xilinx devices": [[62, "util-adxcvr-core-for-amd-xilinx-devices"]], "Microprocessor clock and reset": [[62, "microprocessor-clock-and-reset"]], "PLL reference clock": [[62, "pll-reference-clock"]], "RX interface": [[62, "rx-interface"]], "TX interface": [[62, "tx-interface"]], "Common DRP Interface": [[62, "common-drp-interface"]], "Channel DRP Interface": [[62, "channel-drp-interface"]], "Eye Scan DRP Interface": [[62, "eye-scan-drp-interface"]], "Physical constraints considerations": [[62, "physical-constraints-considerations"]], "AD4134-FMC HDL project": [[63, "ad4134-fmc-hdl-project"]], "Overview": [[63, "overview"], [64, "overview"], [65, "overview"], [66, "overview"], [67, "overview"], [68, "overview"], [69, "overview"], [70, "overview"], [71, "overview"], [72, "overview"], [73, "overview"], [74, "overview"], [75, "overview"], [76, "overview"], [78, "overview"], [79, "overview"], [80, "overview"], [81, "overview"], [85, "overview"], [86, "overview"], [87, "overview"]], "Supported boards": [[63, "supported-boards"], [64, "supported-boards"], [65, "supported-boards"], [66, "supported-boards"], [67, "supported-boards"], [68, "supported-boards"], [69, "supported-boards"], [70, "supported-boards"], [71, "supported-boards"], [72, "supported-boards"], [73, "supported-boards"], [74, "supported-boards"], [75, "supported-boards"], [76, "supported-boards"], [77, "supported-boards"], [78, "supported-boards"], [79, "supported-boards"], [80, "supported-boards"], [81, "supported-boards"], [85, "supported-boards"], [86, "supported-boards"], [87, "supported-boards"]], "Supported devices": [[63, "supported-devices"], [64, "supported-devices"], [65, "supported-devices"], [66, "supported-devices"], [67, "supported-devices"], [68, "supported-devices"], [69, "supported-devices"], [70, "supported-devices"], [71, "supported-devices"], [72, "supported-devices"], [73, "supported-devices"], [74, "supported-devices"], [75, "supported-devices"], [76, "supported-devices"], [78, "supported-devices"], [79, "supported-devices"], [80, "supported-devices"], [81, "supported-devices"], [85, "supported-devices"], [86, "supported-devices"], [87, "supported-devices"]], "Supported carriers": [[63, "supported-carriers"], [64, "supported-carriers"], [65, "supported-carriers"], [66, "supported-carriers"], [67, "supported-carriers"], [68, "supported-carriers"], [69, "supported-carriers"], [70, "supported-carriers"], [71, "supported-carriers"], [72, "supported-carriers"], [73, "supported-carriers"], [74, "supported-carriers"], [75, "supported-carriers"], [76, "supported-carriers"], [77, "supported-carriers"], [78, "supported-carriers"], [79, "supported-carriers"], [80, "supported-carriers"], [81, "supported-carriers"], [85, "supported-carriers"], [86, "supported-carriers"], [87, "supported-carriers"]], "Block design": [[63, "block-design"], [64, "block-design"], [65, "block-design"], [66, "block-design"], [67, "block-design"], [68, "block-design"], [69, "block-design"], [70, "block-design"], [71, "block-design"], [72, "block-design"], [73, "block-design"], [74, "block-design"], [75, "block-design"], [76, "block-design"], [77, "block-design"], [78, "block-design"], [79, "block-design"], [80, "block-design"], [81, "block-design"], [85, "block-design"], [86, "block-design"], [87, "block-design"]], "Block diagram": [[63, "block-diagram"], [64, "block-diagram"], [65, "block-diagram"], [66, "block-diagram"], [67, "block-diagram"], [68, "block-diagram"], [69, "block-diagram"], [70, "block-diagram"], [71, "block-diagram"], [72, "block-diagram"], [73, "block-diagram"], [74, "block-diagram"], [75, "block-diagram"], [76, "block-diagram"], [77, "block-diagram"], [78, "block-diagram"], [79, "block-diagram"], [80, "block-diagram"], [81, "block-diagram"], [85, "block-diagram"], [86, "block-diagram"], [87, "block-diagram"]], "Jumper setup": [[63, "jumper-setup"], [66, "jumper-setup"], [67, "jumper-setup"], [69, "jumper-setup"], [70, "jumper-setup"], [71, "jumper-setup"], [72, "jumper-setup"], [79, "jumper-setup"], [80, "jumper-setup"]], "CPU/Memory interconnects addresses": [[63, "cpu-memory-interconnects-addresses"], [64, "cpu-memory-interconnects-addresses"], [65, "cpu-memory-interconnects-addresses"], [66, "cpu-memory-interconnects-addresses"], [67, "cpu-memory-interconnects-addresses"], [69, "cpu-memory-interconnects-addresses"], [70, "cpu-memory-interconnects-addresses"], [71, "cpu-memory-interconnects-addresses"], [72, "cpu-memory-interconnects-addresses"], [73, "cpu-memory-interconnects-addresses"], [74, "cpu-memory-interconnects-addresses"], [75, "cpu-memory-interconnects-addresses"], [76, "cpu-memory-interconnects-addresses"], [77, "cpu-memory-interconnects-addresses"], [78, "cpu-memory-interconnects-addresses"], [79, "cpu-memory-interconnects-addresses"], [80, "cpu-memory-interconnects-addresses"], [81, "cpu-memory-interconnects-addresses"], [85, "cpu-memory-interconnects-addresses"], [86, "cpu-memory-interconnects-addresses"], [87, "cpu-memory-interconnects-addresses"], [88, "cpu-memory-interconnects-addresses"]], "SPI connections": [[63, "spi-connections"], [64, "spi-connections"], [65, "spi-connections"], [66, "spi-connections"], [67, "spi-connections"], [68, "spi-connections"], [69, "spi-connections"], [70, "spi-connections"], [71, "spi-connections"], [73, "spi-connections"], [74, "spi-connections"], [75, "spi-connections"], [76, "spi-connections"], [77, "spi-connections"], [78, "spi-connections"], [79, "spi-connections"], [80, "spi-connections"], [81, "spi-connections"], [85, "spi-connections"], [87, "spi-connections"]], "GPIOs": [[63, "gpios"], [64, "gpios"], [65, "gpios"], [66, "gpios"], [67, "gpios"], [70, "gpios"], [71, "gpios"], [72, "gpios"], [73, "gpios"], [76, "gpios"], [77, "gpios"], [78, "gpios"], [79, "gpios"], [80, "gpios"], [81, "gpios"], [85, "gpios"], [86, "gpios"], [87, "gpios"], [88, "gpios"]], "Building the HDL project": [[63, "building-the-hdl-project"], [64, "building-the-hdl-project"], [65, "building-the-hdl-project"], [66, "building-the-hdl-project"], [67, "building-the-hdl-project"], [68, "building-the-hdl-project"], [69, "building-the-hdl-project"], [70, "building-the-hdl-project"], [71, "building-the-hdl-project"], [72, "building-the-hdl-project"], [73, "building-the-hdl-project"], [74, "building-the-hdl-project"], [75, "building-the-hdl-project"], [76, "building-the-hdl-project"], [77, "building-the-hdl-project"], [78, "building-the-hdl-project"], [79, "building-the-hdl-project"], [80, "building-the-hdl-project"], [81, "building-the-hdl-project"], [85, "building-the-hdl-project"], [86, "building-the-hdl-project"], [87, "building-the-hdl-project"]], "Resources": [[63, "resources"], [64, "resources"], [65, "resources"], [66, "resources"], [67, "resources"], [68, "resources"], [69, "resources"], [70, "resources"], [71, "resources"], [72, "resources"], [73, "resources"], [74, "resources"], [75, "resources"], [76, "resources"], [77, "resources"], [78, "resources"], [79, "resources"], [80, "resources"], [81, "resources"], [85, "resources"], [86, "resources"], [87, "resources"]], "Hardware related": [[63, "hardware-related"], [64, "hardware-related"], [65, "hardware-related"], [66, "hardware-related"], [67, "hardware-related"], [68, "hardware-related"], [69, "hardware-related"], [70, "hardware-related"], [71, "hardware-related"], [72, "hardware-related"], [73, "hardware-related"], [74, "hardware-related"], [75, "hardware-related"], [76, "hardware-related"], [77, "hardware-related"], [78, "hardware-related"], [79, "hardware-related"], [80, "hardware-related"], [81, "hardware-related"], [85, "hardware-related"], [86, "hardware-related"], [87, "hardware-related"]], "HDL related": [[63, "hdl-related"], [64, "hdl-related"], [65, "hdl-related"], [66, "hdl-related"], [67, "hdl-related"], [68, "hdl-related"], [69, "hdl-related"], [70, "hdl-related"], [71, "hdl-related"], [72, "hdl-related"], [73, "hdl-related"], [74, "hdl-related"], [75, "hdl-related"], [76, "hdl-related"], [77, "hdl-related"], [78, "hdl-related"], [79, "hdl-related"], [80, "hdl-related"], [81, "hdl-related"], [85, "hdl-related"], [86, "hdl-related"], [87, "hdl-related"]], "Software related": [[63, "software-related"], [64, "software-related"], [65, "software-related"], [66, "software-related"], [67, "software-related"], [68, "software-related"], [69, "software-related"], [70, "software-related"], [71, "software-related"], [72, "software-related"], [73, "software-related"], [74, "software-related"], [75, "software-related"], [76, "software-related"], [77, "software-related"], [78, "software-related"], [79, "software-related"], [80, "software-related"], [81, "software-related"], [85, "software-related"], [87, "software-related"]], "More information": [[63, "more-information"], [64, "more-information"], [65, "more-information"], [66, "more-information"], [67, "more-information"], [68, "more-information"], [69, "more-information"], [70, "more-information"], [71, "more-information"], [72, "more-information"], [73, "more-information"], [74, "more-information"], [75, "more-information"], [76, "more-information"], [77, "more-information"], [78, "more-information"], [79, "more-information"], [80, "more-information"], [81, "more-information"], [82, "more-information"], [85, "more-information"], [86, "more-information"], [87, "more-information"]], "Support": [[63, "support"], [64, "support"], [65, "support"], [66, "support"], [67, "support"], [68, "support"], [69, "support"], [70, "support"], [71, "support"], [72, "support"], [73, "support"], [74, "support"], [75, "support"], [76, "support"], [77, "support"], [78, "support"], [79, "support"], [80, "support"], [81, "support"], [83, "support"], [85, "support"], [86, "support"], [87, "support"]], "AD4630-FMC HDL project": [[64, "ad4630-fmc-hdl-project"]], "SPI mode - transfer zone 1": [[64, "spi-mode-transfer-zone-1"]], "SPI mode - transfer zone 2": [[64, "spi-mode-transfer-zone-2"]], "Echo clock mode - transfer zone 2": [[64, "echo-clock-mode-transfer-zone-2"]], "Configuration modes": [[64, "configuration-modes"], [70, "configuration-modes"], [71, "configuration-modes"], [73, "configuration-modes"], [77, "configuration-modes"], [85, "configuration-modes"], [86, "configuration-modes"], [87, "configuration-modes"]], "Legend": [[64, null], [64, null], [64, null], [67, null], [70, null], [70, null], [70, null], [70, null], [71, null], [71, null], [71, null], [71, null], [79, null], [79, null], [80, null], [80, null], [85, null], [85, null], [86, null]], "I2C connections": [[64, "i2c-connections"], [65, "i2c-connections"], [66, "i2c-connections"], [69, "i2c-connections"], [70, "i2c-connections"], [71, "i2c-connections"], [72, "i2c-connections"], [76, "i2c-connections"], [78, "i2c-connections"], [79, "i2c-connections"], [81, "i2c-connections"], [85, "i2c-connections"], [86, "i2c-connections"], [87, "i2c-connections"]], "Systems related": [[64, "systems-related"], [73, "systems-related"], [74, "systems-related"], [75, "systems-related"], [77, "systems-related"], [78, "systems-related"], [79, "systems-related"], [81, "systems-related"], [87, "systems-related"]], "AD469X-FMC HDL project": [[65, "ad469x-fmc-hdl-project"]], "AD5766-SDZ HDL project": [[66, "ad5766-sdz-hdl-project"]], "AD7134-FMC HDL project": [[67, "ad7134-fmc-hdl-project"]], "AD719X-ASDZ HDL project": [[68, "ad719x-asdz-hdl-project"]], "Software considerations": [[68, "software-considerations"], [73, "software-considerations"], [75, "software-considerations"], [87, "software-considerations"]], "AD738x_FMC HDL project": [[69, "ad738x-fmc-hdl-project"]], "AD7606X-FMCZ HDL project": [[70, "ad7606x-fmcz-hdl-project"]], "AD7606x_FMCZ serial interface": [[70, "ad7606x-fmcz-serial-interface"]], "AD7606x_FMCZ parallel interface": [[70, "ad7606x-fmcz-parallel-interface"]], "Connections and hardware changes": [[70, "connections-and-hardware-changes"], [71, "connections-and-hardware-changes"]], "AD7616-SDZ HDL project": [[71, "ad7616-sdz-hdl-project"]], "Other required hardware": [[71, "other-required-hardware"], [85, "other-required-hardware"]], "AD7616_SDZ serial interface": [[71, "ad7616-sdz-serial-interface"]], "AD7616_SDZ parallel interface": [[71, "ad7616-sdz-parallel-interface"]], "AD7768-EVB HDL project": [[72, "ad7768-evb-hdl-project"]], "AD7768-EVB": [[72, "ad7768-evb"]], "AD9081/AD9082/AD9986/AD9988 HDL project": [[73, "ad9081-ad9082-ad9986-ad9988-hdl-project"]], "Example block design for Single link; M=8; L=4": [[73, "example-block-design-for-single-link-m-8-l-4"], [77, "example-block-design-for-single-link-m-8-l-4"]], "Example block design for Single link; M=4; L=8": [[73, "example-block-design-for-single-link-m-4-l-8"]], "Example block design for Single link; M=2; L=8; JESD204C": [[73, "example-block-design-for-single-link-m-2-l-8-jesd204c"]], "Clock scheme": [[73, "clock-scheme"], [74, "clock-scheme"], [75, "clock-scheme"], [77, "clock-scheme"], [87, "clock-scheme"]], "ZCU102": [[73, "zcu102"]], "VCU118": [[73, "vcu118"]], "ADC - crossbar config": [[73, "adc-crossbar-config"]], "DAC - crossbar config": [[73, "dac-crossbar-config"]], "AD9434-FMC HDL project": [[74, "ad9434-fmc-hdl-project"]], "AD9783-EBZ HDL project": [[75, "ad9783-ebz-hdl-project"]], "ADAQ7980-SDZ HDL project": [[76, "adaq7980-sdz-hdl-project"]], "ADRV9026 HDL reference design": [[77, "adrv9026-hdl-reference-design"]], "Other considerations": [[77, "other-considerations"]], "ADC - lane mapping": [[77, "adc-lane-mapping"]], "DAC - lane mapping": [[77, "dac-lane-mapping"]], "CN0363 HDL project": [[78, "cn0363-hdl-project"]], "CN0540 HDL project": [[79, "cn0540-hdl-project"]], "CN0561 HDL project": [[80, "cn0561-hdl-project"]], "CN0585 HDL project": [[81, "cn0585-hdl-project"]], "Projects": [[84, "projects"]], "PULSAR-ADC HDL project": [[85, "pulsar-adc-hdl-project"]], "PulSAR_ADC_PMDZ": [[85, "pulsar-adc-pmdz"]], "PulSAR_ADC_FMC": [[85, "pulsar-adc-fmc"]], "PULSAR-LVDS HDL project": [[86, "pulsar-lvds-hdl-project"]], "Jumper setup AD7625/AD7626": [[86, "jumper-setup-ad7625-ad7626"]], "Jumper setup AD7960/AD7961": [[86, "jumper-setup-ad7960-ad7961"]], "Project template": [[87, "project-template"]], "ADC - crossbar config *** THIS IS JUST AN EXAMPLE ***": [[87, "adc-crossbar-config-this-is-just-an-example"]], "DAC - crossbar config *** THIS IS JUST AN EXAMPLE ***": [[87, "dac-crossbar-config-this-is-just-an-example"]], "HDL Architecture": [[88, "hdl-architecture"]], "How they\u2019re instantiated": [[88, "how-they-re-instantiated"]], "Example": [[88, "example"]], "Typical project diagram": [[88, "typical-project-diagram"]], "Base Design": [[88, "base-design"]], "Microprocessor": [[88, "microprocessor"]], "Memory Interface Controller": [[88, "memory-interface-controller"]], "Peripheral interfaces": [[88, "peripheral-interfaces"]], "SPI": [[88, "spi"]], "I2C/I2S/SPDIF": [[88, "i2c-i2s-spdif"]], "HDMI": [[88, "hdmi"]], "Connectivity": [[88, "connectivity"]], "Interrupts table": [[88, "interrupts-table"]], "Board design and capabilities": [[88, "board-design-and-capabilities"]], "AMD platforms": [[88, "amd-platforms"]], "Intel platforms": [[88, "intel-platforms"]], "VADJ values": [[88, "vadj-values"]], "File structure of a project": [[88, "file-structure-of-a-project"]], "Project files for AMD boards": [[88, "project-files-for-amd-boards"], [102, "project-files-for-amd-boards"]], "Project files for Intel boards": [[88, "project-files-for-intel-boards"], [102, "project-files-for-intel-boards"]], "Project files for Lattice boards": [[88, "project-files-for-lattice-boards"], [102, "project-files-for-lattice-boards"]], "Build a HDL project": [[89, "build-a-hdl-project"]], "Setup and check your environment": [[89, "setup-and-check-your-environment"]], "Setup the HDL repository": [[89, "setup-the-hdl-repository"]], "Building the projects": [[89, "building-the-projects"]], "Building an Intel project": [[89, "building-an-intel-project"]], "Checking the build and analyzing results": [[89, "checking-the-build-and-analyzing-results"], [89, "id1"]], "Building an AMD project": [[89, "building-an-amd-project"]], "Enabling Out-of-Context synthesis": [[89, "enabling-out-of-context-synthesis"]], "Checking the build and analyzing results of library components": [[89, "checking-the-build-and-analyzing-results-of-library-components"]], "Checking the build and analyzing results of projects": [[89, "checking-the-build-and-analyzing-results-of-projects"]], "Building a Lattice project": [[89, "building-a-lattice-project"]], "Required Lattice Provided IPs to download for projects/common/lfcpnx": [[89, "required-lattice-provided-ips-to-download-for-projects-common-lfcpnx"]], "Supported targets of make command": [[89, "supported-targets-of-make-command"]], "Tools and their versions": [[89, "tools-and-their-versions"]], "Tools": [[89, "tools"], [89, "id2"], [89, "id3"]], "Tool versions": [[89, "tool-versions"]], "Environment": [[89, "environment"]], "Linux environment setup": [[89, "linux-environment-setup"]], "Windows environment setup": [[89, "windows-environment-setup"]], "Preparing the SD card": [[89, "preparing-the-sd-card"]], "Errors, Warnings and Notes": [[89, "errors-warnings-and-notes"]], "AMD: Vivado": [[89, "amd-vivado"]], "Customize HDL projects": [[90, "customize-hdl-projects"]], "Documentation guidelines": [[91, "documentation-guidelines"]], "Templates": [[91, "templates"]], "Common sections": [[91, "common-sections"]], "HDL Git repository": [[92, "hdl-git-repository"]], "Folder structure": [[92, "folder-structure"]], "The projects are structured as follows": [[92, "the-projects-are-structured-as-follows"]], "The library are structured as follows": [[92, "the-library-are-structured-as-follows"]], "Repository releases and branches": [[92, "repository-releases-and-branches"]], "ADI HDL coding guidelines": [[93, "adi-hdl-coding-guidelines"]], "1. Introduction": [[93, "introduction"]], "2. Coding style": [[93, "coding-style"]], "A. Layout": [[93, "a-layout"]], "B. Naming Conventions": [[93, "b-naming-conventions"]], "C. Comments": [[93, "c-comments"]], "D. General": [[93, "d-general"]], "3. Annexes": [[93, "annexes"]], "Annex 1 Verilog file format": [[93, "annex-1-verilog-file-format"]], "Annex 2 VHDL file format": [[93, "annex-2-vhdl-file-format"]], "4. References": [[93, "references"]], "User Guide": [[94, "user-guide"]], "Introduction": [[95, "introduction"]], "Generic AXI ADC": [[96, "generic-axi-adc"]], "Architecture": [[96, "architecture"], [97, "architecture"]], "Receive PHY": [[96, "receive-phy"]], "ADC Channel": [[96, "adc-channel"]], "ADC Core": [[96, "adc-core"]], "LVDS or CMOS RX interface": [[96, "id2"]], "JESD RX interface": [[96, "id3"]], "Write FIFO interface": [[96, "id4"]], "AXI Memory Map Slave": [[96, "id5"], [97, "id5"]], "Typical Register Map base addresses": [[96, "typical-register-map-base-addresses"], [97, "typical-register-map-base-addresses"]], "Generic AXI DAC": [[97, "generic-axi-dac"]], "Transmit PHY": [[97, "transmit-phy"]], "DAC Channel": [[97, "dac-channel"]], "DAC Core": [[97, "dac-core"]], "LVDS or CMOS TX interface": [[97, "id2"]], "JESD TX interface": [[97, "id3"]], "Read FIFO interface": [[97, "id4"]], "Creating a new IP": [[98, "creating-a-new-ip"]], "Verilog File": [[98, "verilog-file"]], "Importing with Using Method": [[98, "importing-with-using-method"]], "Ranged Registers and Fields": [[98, "ranged-registers-and-fields"]], "Xilinx": [[98, "xilinx"]], "TCL File": [[98, "tcl-file"], [98, "id1"]], "Makefile": [[98, "makefile"], [98, "id2"]], "Intel": [[98, "intel"]], "ADI IP cores": [[99, "adi-ip-cores"]], "Frameworks": [[99, "frameworks"]], "ADC/DAC": [[99, "adc-dac"]], "DMA": [[99, "dma"]], "Video": [[99, "video"]], "Utilities": [[99, "utilities"]], "Microprocessor Interface": [[100, "microprocessor-interface"]], "uP Interface and Signals": [[100, "up-interface-and-signals"]], "Clock and reset": [[100, "id2"]], "Read interface": [[100, "id3"]], "Write interface": [[100, "id4"]], "Timing diagram": [[100, "timing-diagram"]], "AMBA AXI": [[100, "amba-axi"]], "Avalon": [[100, "avalon"]], "Use ADI IPs into your own project": [[101, "use-adi-ips-into-your-own-project"]], "Vivado": [[101, "vivado"], [101, "id1"], [101, "id2"]], "Quartus": [[101, "quartus"]], "JESD204": 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85, 88, 89, 90, 91, 92, 95, 96, 98, 99, 100, 104, 105, 106], "guid": [0, 2, 7, 9, 10, 15, 20, 21, 33, 34, 35, 37, 38, 58, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 88, 89, 90, 92, 96, 98, 101, 103], "ip": [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 34, 35, 36, 37, 38, 39, 46, 47, 48, 49, 53, 58, 62, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90, 91, 93, 95, 96, 97, 98, 99, 100, 103, 105, 106, 107], "core": [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 26, 27, 28, 30, 31, 32, 34, 35, 36, 37, 38, 39, 40, 42, 43, 46, 48, 49, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 67, 73, 74, 76, 91, 92, 95, 96, 97, 101, 103, 104, 106], "s_axis_axi_aclks_axi_aresetndac_clkdma_datavalid_in_dmavalid_in_dma_secdata_in_adata_in_bvalid_in_avalid_in_bsdio_iexternal_syncdac_data_readydac_sclkdac_csnsdio_osdio_tsync_ext_deviceaxi_ad3552r": 1, "The": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90, 91, 92, 94, 96, 97, 98, 99, 100, 101, 103, 104, 105, 106], "can": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 32, 34, 35, 36, 37, 38, 39, 41, 42, 43, 44, 45, 46, 47, 49, 51, 54, 55, 56, 58, 61, 62, 63, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90, 91, 92, 93, 95, 96, 98, 99, 100, 101, 102, 104, 105, 107], "low": [1, 2, 3, 10, 14, 15, 17, 18, 23, 24, 26, 28, 29, 30, 34, 35, 36, 37, 39, 41, 42, 45, 46, 47, 48, 55, 56, 58, 66, 67, 69, 70, 71, 72, 75, 77, 79, 81, 83, 84, 88, 89, 96, 99, 100, 103, 105], "drift": [1, 67], "ultra": 1, "fast": [1, 18, 42, 70, 75, 91], "16": [1, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 32, 34, 35, 36, 37, 38, 39, 41, 42, 46, 48, 49, 54, 55, 57, 59, 60, 67, 68, 69, 72, 73, 74, 76, 78, 79, 80, 82, 84, 89, 90, 91, 92, 96, 99, 100, 101, 106], "bit": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 32, 34, 35, 36, 37, 38, 39, 41, 42, 49, 51, 54, 57, 59, 60, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90, 91, 92, 96, 99, 100, 106], "accuraci": [1, 27, 79, 81], "current": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 32, 34, 35, 36, 37, 38, 39, 42, 43, 46, 54, 55, 56, 61, 63, 65, 67, 68, 72, 75, 76, 82, 83, 84, 92, 95, 96, 99, 100, 101, 105], "output": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 23, 24, 25, 26, 27, 28, 30, 32, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 48, 49, 52, 54, 55, 56, 57, 59, 61, 62, 63, 65, 67, 69, 70, 71, 75, 81, 82, 88, 89, 90, 91, 92, 96, 99, 100, 101, 103], "digit": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 23, 28, 33, 41, 54, 66, 67, 69, 70, 72, 73, 74, 75, 77, 78, 79, 80, 81, 83, 84, 88, 89, 96, 98, 99, 100, 102], "convert": [1, 5, 13, 18, 19, 20, 21, 25, 27, 28, 41, 49, 58, 65, 66, 67, 69, 70, 72, 73, 74, 75, 76, 77, 78, 79, 80, 83, 84, 88, 89, 90, 94, 99, 100, 103], "dac": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 23, 27, 28, 33, 34, 36, 37, 38, 41, 54, 60, 61, 69, 78, 82, 84, 99, 101, 104], "multipl": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 18, 20, 21, 22, 26, 27, 34, 35, 36, 37, 38, 39, 41, 46, 47, 54, 61, 63, 67, 77, 79, 80, 90, 92, 95, 96, 99, 100, 101, 103], "voltag": [1, 15, 16, 41, 67, 69, 72, 73, 74, 75, 77, 82, 89, 105], "span": [1, 18, 69, 88], "rang": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 24, 25, 26, 27, 28, 29, 30, 32, 34, 35, 36, 37, 38, 39, 46, 47, 48, 49, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 65, 66, 67, 69, 70, 71, 72, 73, 75, 78, 82, 83, 88, 89, 91, 96, 99, 100], "base": [1, 2, 4, 5, 6, 8, 9, 12, 14, 16, 18, 19, 20, 21, 23, 24, 25, 26, 28, 32, 34, 35, 36, 37, 38, 39, 42, 54, 55, 56, 59, 60, 66, 67, 68, 69, 70, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90, 92, 93, 95], "vivado": [1, 4, 5, 6, 8, 9, 12, 25, 26, 29, 30, 36, 37, 39, 46, 47, 48, 49, 53, 54, 91, 95, 101, 103, 105, 106], "compat": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 34, 35, 36, 37, 54, 67, 69, 72, 78, 79, 82, 92, 99, 100], "8b": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "read": [1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 32, 34, 35, 36, 37, 39, 42, 49, 51, 54, 55, 56, 60, 62, 67, 92, 94, 96, 98, 99], "write": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 32, 34, 35, 36, 37, 39, 43, 44, 51, 54, 55, 56, 62, 69, 76, 81, 90, 92, 100, 101, 105], "sdr": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 20, 21, 34, 35, 36, 37, 38, 54, 67, 93, 99, 100], "ddr": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 20, 21, 28, 34, 35, 49, 54, 67, 76, 77, 90, 99, 100], "16b": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "data": [1, 2, 3, 4, 5, 6, 8, 9, 11, 12, 13, 14, 15, 16, 17, 20, 22, 23, 27, 30, 31, 32, 33, 38, 39, 40, 42, 43, 44, 46, 47, 48, 49, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90, 91, 92, 96, 98, 99, 100, 101, 103, 104], "stream": [1, 10, 14, 15, 21, 23, 30, 31, 32, 33, 36, 37, 39, 40, 41, 42, 43, 46, 47, 48, 49, 52, 57, 59, 60, 68, 76, 102], "clk_in": [1, 4, 5], "8": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 32, 34, 35, 36, 37, 38, 39, 42, 45, 46, 47, 48, 49, 51, 53, 54, 55, 59, 60, 61, 63, 65, 67, 70, 72, 73, 75, 79, 82, 84, 90, 91, 92, 96, 99, 100, 101], "4": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 16, 17, 18, 19, 21, 22, 23, 24, 26, 27, 28, 29, 30, 32, 34, 35, 36, 37, 38, 39, 42, 44, 48, 49, 51, 54, 55, 56, 59, 60, 61, 63, 65, 66, 67, 69, 70, 72, 73, 75, 77, 79, 82, 83, 84, 89, 90, 91, 92, 99, 100, 101, 104, 105, 106], "updat": [1, 26, 28, 30, 32, 39, 42, 51, 69, 90, 92, 95, 96, 105, 106], "rate": [1, 3, 7, 9, 10, 11, 13, 15, 17, 18, 19, 21, 23, 27, 28, 34, 35, 36, 37, 55, 58, 61, 63, 65, 67, 68, 69, 71, 72, 73, 74, 75, 76, 77, 78, 80, 82, 83, 88, 90, 100], "select": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 16, 18, 19, 21, 22, 23, 27, 34, 35, 36, 37, 38, 44, 45, 46, 49, 51, 54, 58, 67, 69, 73, 74, 75, 76, 90, 92, 97, 99, 100, 104], "input": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16, 17, 19, 20, 21, 22, 23, 25, 26, 27, 28, 29, 32, 34, 35, 36, 37, 38, 40, 43, 44, 45, 52, 54, 55, 56, 57, 60, 61, 62, 63, 65, 66, 67, 70, 71, 72, 73, 74, 75, 77, 79, 80, 82, 83, 88, 89, 91, 92, 96, 99, 100, 103], "sourc": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 29, 30, 34, 35, 36, 37, 38, 39, 44, 46, 47, 48, 49, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90, 91, 92, 94, 95, 96, 99, 100, 101, 104, 105], "dma": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 17, 18, 20, 21, 23, 27, 28, 30, 31, 32, 34, 35, 54, 59, 60, 61, 62, 63, 67, 73, 74, 81, 90, 99, 100], "adc": [1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16, 17, 18, 19, 21, 23, 27, 28, 31, 32, 33, 35, 36, 37, 38, 41, 50, 54, 57, 59, 63, 66, 67, 68, 70, 71, 72, 73, 74, 75, 77, 79, 81, 82, 83, 84, 87, 89, 100, 104], "test_ramp": 1, "out": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 34, 35, 36, 37, 39, 41, 46, 47, 48, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 67, 73, 74, 75, 76, 80, 81, 82, 88, 90, 95, 96, 99, 100, 105, 106], "clock": [1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 21, 22, 23, 24, 26, 29, 30, 32, 39, 42, 44, 45, 46, 47, 48, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 66, 68, 69, 70, 71, 72, 73, 74, 75, 79, 81, 82, 83, 84, 88, 89, 91, 96, 99, 100, 104, 105], "sclk": [1, 42, 45, 46, 49], "frequenc": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 19, 20, 21, 22, 25, 28, 34, 35, 36, 37, 42, 49, 54, 58, 65, 66, 67, 69, 70, 73, 74, 75, 80, 81, 82, 83, 90, 96, 99, 100], "when": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 17, 18, 19, 23, 24, 25, 26, 27, 28, 30, 31, 32, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 45, 47, 48, 54, 55, 56, 58, 59, 60, 61, 63, 65, 67, 69, 76, 88, 90, 91, 92, 94, 95, 96, 99, 100, 101, 105, 106], "i": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 91, 92, 94, 95, 96, 98, 99, 100, 101, 103, 104, 106, 107], "2": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 32, 34, 35, 36, 37, 38, 39, 41, 42, 44, 46, 48, 49, 50, 51, 54, 55, 57, 58, 61, 63, 65, 69, 70, 72, 73, 74, 75, 79, 80, 81, 82, 83, 88, 89, 90, 91, 92, 95, 99, 100, 104, 105, 106], "mode": [1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 17, 18, 22, 23, 24, 26, 27, 30, 31, 32, 34, 35, 36, 37, 45, 49, 54, 55, 56, 58, 65, 66, 68, 69, 70, 72, 75, 79, 83, 92, 96, 99, 100], "have": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 33, 34, 35, 36, 37, 38, 39, 44, 47, 49, 54, 65, 66, 67, 68, 69, 70, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 87, 88, 89, 90, 91, 92, 94, 95, 96, 98, 99, 100, 101, 103, 104, 105, 106], "maximum": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 17, 18, 20, 21, 22, 23, 24, 27, 28, 29, 34, 35, 36, 37, 39, 44, 49, 54, 62, 66, 67, 68, 69, 75, 78, 82, 83, 92, 96, 99, 100, 105], "132mhz": 1, "synchron": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 17, 20, 21, 22, 23, 24, 26, 27, 29, 30, 32, 36, 38, 40, 44, 46, 47, 48, 53, 54, 55, 56, 57, 59, 60, 62, 75, 76, 81, 90, 95, 96, 99, 100], "capabl": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 26, 34, 35, 49, 54, 66, 70, 75, 82, 83, 99, 100, 105], "set": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 34, 35, 39, 41, 45, 48, 49, 50, 54, 55, 56, 59, 60, 65, 69, 73, 74, 76, 79, 82, 88, 89, 90, 92, 95, 96, 99, 100, 101, 104, 105, 106], "an": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 18, 19, 20, 21, 22, 23, 24, 26, 27, 28, 30, 31, 32, 34, 35, 36, 37, 38, 39, 41, 42, 46, 49, 54, 55, 56, 57, 59, 60, 62, 66, 67, 68, 69, 70, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 91, 94, 95, 96, 98, 99, 100, 101, 103, 104, 106], "name": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 32, 34, 35, 36, 37, 39, 40, 42, 43, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90, 91, 92, 95, 99, 100, 101, 103, 104, 105], "axi_ad3552r": [1, 84, 95], "v": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 34, 35, 36, 37, 38, 39, 42, 46, 47, 48, 51, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 67, 69, 72, 73, 74, 75, 79, 89, 90, 91, 92, 96, 99, 100, 101, 103, 105], "axi_ad3552r_channel": 1, "channel": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 18, 22, 23, 26, 27, 28, 33, 34, 35, 36, 37, 38, 41, 42, 44, 54, 57, 61, 63, 66, 67, 69, 70, 73, 74, 75, 76, 80, 81, 83, 84, 88, 90, 101, 102, 103], "axi_ad3552r_cor": 1, "axi_ad3552r_if": 1, "modul": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 16, 18, 20, 21, 23, 24, 26, 28, 30, 32, 34, 35, 36, 37, 42, 43, 45, 51, 54, 55, 58, 59, 60, 66, 67, 68, 69, 70, 75, 78, 81, 83, 90, 91, 92, 95, 96, 99, 100, 101, 103, 104, 105], "axi_ad3552r_if_tb": 1, "testbench": 1, "setup": [1, 36, 37, 76, 81, 84, 105, 106], "axi_ad3552r_ip": 1, "gener": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 18, 19, 21, 22, 23, 25, 26, 27, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 41, 42, 45, 46, 47, 48, 49, 53, 54, 55, 62, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90, 91, 92, 94, 95, 97, 98, 102], "integr": [1, 2, 4, 5, 7, 12, 26, 28, 29, 30, 34, 35, 36, 37, 38, 39, 46, 47, 48, 53, 61, 63, 67, 69, 72, 75, 79, 80, 82, 91, 92, 93, 95, 101], "default": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 34, 35, 36, 37, 39, 42, 46, 47, 48, 49, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 65, 69, 72, 73, 74, 76, 80, 82, 88, 89, 90, 91, 92, 96, 99, 100, 101, 104], "valu": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 32, 34, 35, 36, 37, 39, 42, 43, 44, 46, 47, 48, 49, 51, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 65, 76, 77, 80, 90, 96, 99, 100, 101, 104], "choic": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 24, 25, 26, 28, 29, 30, 34, 35, 36, 37, 39, 46, 47, 48, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 65, 99, 100], "id": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 16, 18, 19, 20, 21, 22, 24, 26, 28, 30, 32, 33, 34, 35, 36, 37, 39, 42, 54, 94, 99, 100, 101, 102], "should": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 26, 27, 28, 30, 32, 34, 35, 36, 37, 38, 39, 42, 45, 55, 56, 57, 62, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 86, 88, 89, 90, 91, 92, 95, 96, 98, 99, 100, 101, 103, 104, 105, 106], "uniqu": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16, 18, 20, 21, 22, 24, 26, 34, 35, 36, 37, 39, 54, 92, 96, 99, 100, 101], "each": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 16, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 32, 34, 35, 36, 37, 38, 39, 40, 42, 44, 49, 54, 57, 59, 60, 65, 66, 70, 73, 74, 75, 76, 80, 81, 83, 90, 91, 92, 93, 95, 96, 99, 100, 101, 103, 105], "0": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 32, 34, 35, 36, 37, 38, 39, 40, 42, 44, 46, 47, 48, 49, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90, 91, 92, 96, 99, 100, 101, 103, 104, 105, 106], "fpga_technologi": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 16, 21, 34, 35, 54, 99, 100], "encod": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 34, 35, 36, 37, 46, 54, 76, 80, 90, 99, 100], "describ": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 19, 25, 27, 32, 34, 35, 36, 54, 76, 80, 90, 91, 95, 96, 99, 100, 105], "technologi": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 16, 34, 35, 38, 54, 65, 96, 99, 100], "arria": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 18, 34, 35, 38, 54, 76, 90, 99, 100, 105], "10": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15, 16, 17, 18, 19, 22, 24, 28, 30, 34, 35, 36, 37, 38, 42, 49, 51, 54, 58, 65, 67, 73, 74, 75, 76, 80, 89, 90, 91, 99, 100, 101, 104, 105], "7seri": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 16, 21, 34, 35, 54, 99, 100], "unknown": [1, 6, 7, 8, 9, 10, 11, 12, 14, 15, 16, 18, 21, 32, 34, 35, 65, 92], "1": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 32, 34, 35, 36, 37, 38, 39, 40, 41, 42, 44, 45, 46, 47, 48, 49, 51, 53, 54, 55, 56, 57, 58, 59, 60, 61, 63, 65, 69, 70, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83, 88, 89, 90, 91, 92, 95, 99, 100, 101, 104, 105, 106], "ultrascal": [1, 6, 7, 8, 9, 10, 11, 12, 15, 16, 19, 21, 28, 34, 35, 58, 65, 76, 78, 80, 90, 91, 92, 105], "3": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 32, 34, 35, 36, 37, 38, 39, 42, 44, 46, 49, 51, 54, 58, 65, 69, 72, 73, 74, 75, 76, 79, 80, 82, 90, 91, 92, 99, 100, 104, 105, 106], "versal": [1, 6, 7, 8, 9, 10, 11, 12, 15, 16, 21, 34, 35, 76, 90, 91, 105], "fpga_famili": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 16, 34, 35, 54, 99, 100], "famili": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 16, 18, 28, 34, 35, 41, 49, 50, 54, 71, 72, 88, 89, 91, 99, 100, 105], "variant": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 34, 35, 49, 54, 83, 99, 100], "e": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 18, 19, 20, 21, 24, 26, 27, 28, 32, 34, 35, 36, 37, 38, 42, 44, 49, 54, 76, 90, 91, 92, 95, 96, 99, 100, 101, 105], "g": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 18, 20, 21, 24, 27, 28, 32, 34, 35, 36, 37, 42, 44, 54, 76, 90, 91, 92, 95, 96, 99, 100, 101, 105], "sx": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 34, 35, 54, 99, 100], "gx": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 34, 35, 54, 99, 100], "gt": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 34, 35, 54, 65, 99, 100], "artix": [1, 6, 7, 8, 9, 10, 11, 12, 15, 16, 18, 34, 35, 91], "kintex": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 16, 18, 34, 35, 54, 91, 99, 100], "virtex": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 16, 18, 34, 35, 54, 91, 92, 99, 100], "zynq": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 16, 19, 20, 21, 28, 34, 35, 49, 54, 58, 66, 67, 68, 69, 70, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90, 91, 92, 99, 100, 105], "versalprim": [1, 6, 7, 8, 9, 10, 11, 12, 15, 16, 34, 35], "5": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21, 22, 23, 24, 25, 26, 28, 30, 32, 34, 35, 36, 37, 38, 39, 42, 49, 51, 54, 55, 56, 65, 66, 67, 69, 70, 72, 73, 74, 75, 76, 79, 82, 83, 84, 88, 89, 90, 91, 92, 95, 99, 100, 104, 106], "versalaicor": [1, 6, 7, 8, 9, 10, 11, 12, 15, 16, 34, 35], "6": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 19, 20, 21, 22, 23, 24, 25, 26, 28, 29, 30, 32, 34, 35, 36, 37, 38, 42, 51, 54, 60, 65, 73, 76, 82, 89, 90, 91, 92, 99, 100], "versalpremium": [1, 6, 7, 8, 9, 10, 11, 12, 15, 16, 34, 35], "7": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 32, 34, 35, 36, 37, 39, 40, 42, 46, 47, 48, 49, 51, 53, 54, 55, 56, 65, 66, 70, 75, 76, 79, 82, 83, 89, 90, 91, 96, 99, 100, 101, 105], "speed_grad": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 16, 34, 35, 54, 99, 100], "": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 17, 18, 19, 22, 24, 25, 26, 27, 30, 32, 34, 35, 36, 37, 39, 42, 46, 48, 51, 54, 55, 56, 58, 59, 60, 61, 63, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90, 91, 92, 96, 97, 98, 99, 100, 101, 104], "speed": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 16, 18, 19, 21, 27, 28, 29, 30, 34, 35, 36, 37, 38, 54, 62, 65, 66, 70, 71, 72, 73, 74, 83, 88, 89, 92, 99, 100, 105], "grade": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 16, 30, 34, 35, 54, 99, 100], "1l": [1, 6, 7, 8, 9, 10, 11, 12, 15, 16, 34, 35], "11": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 16, 18, 24, 28, 30, 32, 34, 35, 36, 37, 38, 42, 51, 54, 58, 76, 80, 82, 90, 91, 99], "1h": [1, 6, 7, 8, 9, 10, 11, 12, 15, 16, 34, 35], "12": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15, 16, 18, 19, 22, 24, 28, 29, 30, 32, 34, 35, 36, 37, 38, 41, 42, 49, 51, 54, 62, 65, 66, 67, 68, 69, 70, 72, 73, 74, 75, 76, 77, 78, 79, 81, 82, 83, 88, 90, 91, 96, 99, 100], "1hv": [1, 6, 7, 8, 9, 10, 11, 12, 15, 16, 34, 35], "13": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 16, 18, 22, 24, 26, 28, 34, 35, 36, 37, 39, 42, 51, 54, 62, 66, 67, 68, 69, 70, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83, 84, 88, 89, 90, 91, 99, 100, 103, 104], "1lv": [1, 6, 7, 8, 9, 10, 11, 12, 15, 16, 34, 35], "14": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15, 16, 17, 24, 27, 28, 29, 30, 34, 35, 36, 37, 38, 42, 49, 51, 54, 69, 72, 80, 88, 90, 91, 99, 100, 101, 106], "20": [1, 6, 7, 8, 9, 10, 11, 12, 15, 16, 19, 28, 30, 32, 34, 35, 36, 37, 41, 65, 69, 74, 76, 80, 90, 91], "2l": [1, 6, 7, 8, 9, 10, 11, 12, 15, 16, 34, 35], "21": [1, 6, 7, 8, 9, 10, 11, 12, 15, 16, 26, 27, 28, 30, 32, 34, 35, 36, 37, 90, 91, 100, 106], "2lv": [1, 6, 7, 8, 9, 10, 11, 12, 15, 16, 34, 35], "22": [1, 6, 7, 8, 9, 10, 11, 12, 15, 16, 28, 30, 32, 34, 35, 90, 91, 106], "2mp": [1, 6, 7, 8, 9, 10, 11, 12, 15, 16, 34, 35], "23": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 16, 18, 21, 27, 28, 30, 32, 34, 35, 36, 37, 39, 54, 90, 91, 99, 100, 106], "2lvc": [1, 6, 7, 8, 9, 10, 11, 12, 15, 16, 34, 35], "24": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 16, 18, 20, 21, 26, 27, 28, 30, 32, 34, 35, 36, 37, 39, 41, 46, 49, 54, 66, 67, 70, 75, 76, 81, 82, 90, 91, 99, 100], "2lvi": [1, 6, 7, 8, 9, 10, 11, 12, 15, 16, 34, 35], "25": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 16, 19, 27, 28, 34, 35, 36, 37, 38, 54, 58, 65, 75, 90, 91, 99, 100], "30": [1, 6, 7, 8, 9, 10, 11, 12, 15, 16, 26, 28, 29, 30, 34, 35, 49, 75, 90, 91], "dev_packag": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 16, 34, 35, 54, 99, 100], "packag": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 16, 26, 32, 34, 35, 36, 37, 54, 67, 69, 72, 75, 79, 92, 99, 100, 101], "might": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 18, 34, 35, 36, 37, 43, 45, 54, 76, 91, 92, 99, 100, 101, 106], "affect": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 18, 34, 35, 36, 37, 42, 44, 54, 65, 92, 99, 100], "high": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 17, 18, 19, 21, 23, 24, 27, 28, 30, 34, 35, 36, 37, 38, 39, 41, 42, 49, 54, 61, 63, 65, 69, 71, 72, 73, 74, 75, 77, 78, 79, 82, 88, 89, 92, 99, 100, 105], "rf": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 16, 26, 28, 54, 76, 80, 92, 93, 99, 100], "fl": [1, 6, 7, 8, 9, 10, 11, 12, 15, 16, 34, 35], "ff": [1, 6, 7, 8, 9, 10, 11, 12, 15, 16, 18, 27, 28, 34, 35], "fb": [1, 6, 7, 8, 9, 10, 11, 12, 15, 16, 34, 35], "hc": [1, 6, 7, 8, 9, 10, 11, 12, 15, 16, 34, 35], "fh": [1, 6, 7, 8, 9, 10, 11, 12, 15, 16, 34, 35], "c": [1, 6, 7, 8, 9, 10, 11, 12, 15, 16, 18, 19, 28, 44, 45, 46, 49, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90, 92, 99, 100, 104], "cp": [1, 6, 7, 8, 9, 10, 11, 12, 15, 16, 34, 35, 65], "ft": [1, 6, 7, 8, 9, 10, 11, 12, 15, 16, 34, 35], "9": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 16, 17, 19, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 42, 51, 54, 65, 67, 75, 82, 90, 91, 92, 96, 99, 100, 106], "fg": [1, 6, 7, 8, 9, 10, 11, 12, 15, 16, 34, 35], "sb": [1, 6, 7, 8, 9, 10, 11, 12, 15, 16, 34, 35], "rb": [1, 6, 7, 8, 9, 10, 11, 12, 15, 16, 34, 35], "r": [1, 6, 7, 8, 9, 10, 11, 12, 15, 16, 34, 35, 36, 37, 42, 51], "cl": [1, 6, 7, 8, 9, 10, 11, 12, 15, 16, 34, 35], "sf": [1, 6, 7, 8, 9, 10, 11, 12, 15, 16, 34, 35], "15": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 32, 34, 35, 36, 37, 39, 40, 42, 46, 47, 48, 49, 51, 52, 53, 54, 56, 59, 60, 76, 90, 91, 92, 96, 99, 100, 101, 104, 106], "ba": [1, 6, 7, 8, 9, 10, 11, 12, 15, 16, 34, 35], "fa": [1, 6, 7, 8, 9, 10, 11, 12, 15, 16, 34, 35], "17": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 16, 17, 23, 28, 30, 32, 34, 35, 36, 54, 90, 91, 92, 99, 100, 106], "f": [1, 6, 7, 8, 9, 10, 11, 12, 15, 16, 19, 28, 34, 35, 36, 37, 76, 80, 90], "18": [1, 6, 7, 8, 9, 10, 11, 12, 15, 16, 17, 23, 28, 34, 35, 36, 37, 41, 49, 73, 80, 88, 89, 90, 91, 106], "fi": [1, 6, 7, 8, 9, 10, 11, 12, 15, 16, 34, 35], "19": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 16, 17, 18, 23, 28, 30, 32, 34, 35, 36, 37, 54, 90, 91, 92, 99, 106], "l": [1, 6, 7, 8, 9, 10, 11, 12, 15, 16, 19, 34, 35, 36, 37, 90, 92], "dds_disabl": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 34, 35, 54, 99, 100], "dd": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "disabl": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 17, 18, 21, 23, 24, 26, 27, 28, 30, 32, 34, 35, 36, 37, 39, 54, 56, 73, 90, 99, 100, 106], "dds_type": [1, 27, 35], "type": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 32, 34, 35, 36, 37, 39, 54, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90, 91, 92, 96, 99, 100, 103, 105, 106], "dds_cordic_dw": [1, 35], "cordic": [1, 7, 10, 11, 27, 35], "dw": [1, 7, 11, 99, 100], "dds_cordic_phase_dw": [1, 35], "phase": [1, 2, 7, 10, 11, 35, 38, 42, 73, 75, 88, 89, 100], "s_axi": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 30, 34, 35, 36, 37, 39, 54, 55, 56, 60], "standard": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 17, 22, 23, 27, 34, 35, 36, 37, 38, 40, 47, 54, 68, 69, 72, 81, 91, 92, 95, 99, 100, 105], "slave": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16, 17, 19, 22, 23, 25, 26, 34, 54, 55, 56, 66, 70, 83], "memori": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 25, 26, 30, 31, 34, 35, 36, 37, 39, 41, 43, 49, 54, 61, 62, 63, 65, 92, 101, 103], "physic": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 29, 30, 34, 35, 36, 37, 39, 42, 45, 46, 47, 48, 49, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 76, 80, 90, 91, 92, 99, 100, 104], "port": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 29, 30, 33, 34, 35, 36, 37, 39, 46, 47, 48, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 65, 87, 90, 91, 92, 96, 97, 99, 100, 101], "logic": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 39, 41, 42, 45, 46, 47, 48, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 65, 66, 67, 68, 69, 70, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90, 95, 96, 99, 100, 101, 102, 104], "direct": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 29, 30, 32, 33, 34, 35, 36, 37, 38, 39, 40, 43, 45, 46, 47, 48, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 66, 67, 68, 69, 70, 73, 74, 75, 76, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90, 92, 96, 100, 101, 102, 103], "depend": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 29, 30, 32, 34, 35, 36, 37, 38, 39, 41, 42, 44, 45, 46, 47, 48, 49, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 66, 67, 68, 69, 70, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90, 91, 92, 95, 99, 100, 101], "s_axi_awaddr": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54], "awaddr": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54], "s_axi_awprot": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54], "awprot": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54], "s_axi_awvalid": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54], "awvalid": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54], "s_axi_awreadi": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54], "awreadi": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54], "s_axi_wdata": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54], "wdata": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54], "31": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 32, 34, 35, 36, 37, 39, 54, 56, 57, 61, 62, 63, 65, 90, 91, 96, 99, 100, 101, 103], "s_axi_wstrb": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54], "wstrb": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54], "s_axi_wvalid": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54], "wvalid": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54], "s_axi_wreadi": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54], "wreadi": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54], "s_axi_bresp": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54], "bresp": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54], "s_axi_bvalid": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54], "bvalid": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54], "s_axi_breadi": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54], "breadi": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54], "s_axi_araddr": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54], "araddr": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54], "s_axi_arprot": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54], "arprot": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54], "s_axi_arvalid": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54], "arvalid": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54], "s_axi_arreadi": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54], "arreadi": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54], "s_axi_rdata": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54], "rdata": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54], "s_axi_rresp": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54], "rresp": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54], "s_axi_rvalid": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54], "rvalid": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54], "s_axi_rreadi": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54], "rreadi": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54], "s_axi_aclk": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 49, 54, 101, 103], "clk": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 33, 34, 35, 36, 37, 39, 42, 44, 46, 47, 49, 51, 53, 54, 57, 58, 59, 60, 61, 62, 63, 96, 102], "s_axi_aresetn": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 49, 54, 101, 103], "rst": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54, 58, 61, 62, 63, 90, 94, 96], "dac_clk": [1, 11, 17, 100], "dma_data": 1, "from": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 32, 34, 35, 36, 37, 38, 39, 40, 41, 42, 44, 46, 47, 48, 49, 50, 51, 53, 54, 55, 56, 57, 58, 59, 60, 62, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 86, 88, 89, 90, 91, 92, 94, 95, 96, 98, 99, 100, 101, 103, 104, 105, 106, 107], "dmac": [1, 2, 3, 20, 21, 23, 33, 102], "valid_in_dma": 1, "valid": [1, 2, 3, 4, 5, 6, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 23, 27, 28, 30, 34, 35, 36, 37, 39, 40, 44, 49, 52, 54, 56, 57, 59, 60, 61, 62, 63, 92, 93, 96, 99, 100, 105, 106], "valid_in_dma_sec": 1, "secondari": [1, 7, 16, 25], "need": [1, 4, 5, 6, 7, 8, 9, 11, 12, 14, 15, 17, 18, 19, 20, 21, 24, 27, 28, 30, 34, 36, 37, 38, 39, 42, 44, 49, 54, 60, 61, 63, 65, 66, 70, 73, 74, 76, 77, 83, 88, 89, 91, 92, 98, 101, 105, 106], "dac_data_readi": 1, "readi": [1, 4, 5, 9, 15, 18, 27, 28, 36, 37, 40, 44, 49, 52, 60, 99], "signal": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 19, 20, 21, 22, 23, 24, 26, 27, 32, 41, 42, 49, 54, 55, 57, 58, 59, 60, 62, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 81, 82, 83, 84, 88, 89, 90, 91, 92, 96, 99, 100, 105], "data_in_a": 1, "adc_data": [1, 3, 4, 6, 8, 9, 23, 34], "data_in_b": 1, "valid_in_a": 1, "valid_in_b": 1, "dac_sclk": 1, "serial": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 20, 21, 30, 32, 34, 35, 36, 37, 38, 39, 49, 54, 65, 66, 67, 69, 70, 79, 83, 88, 89, 91, 99, 100], "dac_csn": 1, "chip": [1, 2, 3, 4, 5, 6, 8, 9, 10, 11, 12, 44, 45, 46, 51, 54, 58, 66, 70, 72, 73, 74, 76, 77, 83, 90], "sdio_i": 1, "sdio_o": 1, "sdio_t": 1, "o": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 20, 21, 23, 27, 28, 32, 34, 35, 54, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 86, 88, 89, 90, 91, 92, 93, 96, 99, 100], "buffer": [1, 7, 10, 15, 17, 32, 36, 38, 39, 45, 49, 55, 67, 69, 72, 73, 74, 75, 76, 77, 79, 88, 89, 90, 91, 105], "control": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 21, 22, 23, 26, 33, 34, 35, 39, 41, 42, 44, 45, 46, 47, 48, 54, 55, 56, 59, 60, 62, 66, 67, 68, 69, 70, 72, 73, 74, 79, 80, 82, 83, 88, 92, 99, 100, 101, 102, 103], "external_sync": [1, 24], "extern": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 17, 18, 19, 22, 23, 24, 26, 27, 28, 30, 31, 36, 37, 39, 41, 42, 43, 46, 49, 54, 62, 66, 69, 70, 72, 73, 74, 75, 76, 77, 78, 83, 89, 90, 91, 96, 99, 100, 101], "flag": [1, 4, 5, 6, 15, 17, 18, 22, 24, 30, 32], "anoth": [1, 2, 4, 5, 6, 7, 8, 9, 11, 12, 17, 18, 23, 28, 32, 34, 44, 54, 90, 99, 105], "sync_ext_devic": 1, "start_sync": 1, "top": [1, 4, 5, 6, 8, 9, 12, 16, 20, 21, 24, 26, 32, 45, 54, 75, 91, 92, 96, 99, 100, 104, 105], "instanti": [1, 4, 5, 6, 8, 9, 12, 15, 16, 19, 20, 21, 25, 27, 35, 45, 54, 65, 67, 73, 74, 82, 83, 88, 89, 92, 96, 99, 100, 101, 104, 105], "handl": [1, 4, 5, 6, 7, 8, 9, 12, 16, 20, 21, 22, 27, 28, 29, 34, 35, 38, 46, 54, 91, 95, 99, 100], "state": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 15, 17, 18, 19, 22, 24, 26, 28, 30, 32, 34, 35, 39, 42, 45, 46, 47, 48, 54, 55, 56, 90, 96, 99, 105], "machin": [1, 17, 19, 28, 32, 46, 48, 82, 88, 96], "quad": [1, 9, 15, 34, 35, 36, 37, 38, 65, 66, 70, 72, 76, 83], "spi": [1, 4, 5, 6, 8, 9, 11, 12, 33, 50, 54, 92, 101, 102], "For": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 18, 23, 24, 27, 28, 30, 32, 34, 35, 36, 37, 38, 39, 41, 42, 44, 54, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 86, 88, 89, 90, 91, 92, 95, 96, 99, 100, 101, 104, 105, 106], "common": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 20, 21, 34, 35, 41, 49, 54, 67, 72, 73, 74, 79, 88, 90, 91, 95, 99, 100, 101, 104], "ar": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 32, 34, 35, 36, 37, 38, 39, 40, 41, 42, 44, 45, 46, 47, 48, 49, 50, 53, 54, 55, 56, 57, 59, 60, 61, 63, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 86, 88, 89, 90, 91, 92, 94, 96, 98, 99, 100, 101, 103, 104, 105, 106, 107], "axi_ad3552r_dac_common": 1, "dword": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 34, 35, 36, 37, 39, 54, 99, 100], "byte": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 32, 34, 35, 36, 37, 39, 54, 55, 56, 58, 99, 100], "reg": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 32, 34, 35, 36, 37, 39, 54, 96, 99, 100, 101], "field": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 32, 34, 35, 37, 38, 39, 42, 54, 88, 96, 99, 100], "0x11": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 19, 20, 21, 23, 26, 34, 35, 54, 76, 99, 100], "0x44": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 19, 20, 21, 23, 26, 34, 35, 39, 54, 99, 100], "cntrl_1": [1, 7, 10, 11, 35, 100, 101], "statu": [1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 19, 20, 21, 22, 23, 26, 27, 28, 30, 34, 35, 38, 39, 54, 55, 59, 60, 77, 92, 95, 99, 100, 101], "ext_sync_arm": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "rw": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 34, 35, 36, 37, 39, 54, 99, 100, 101], "0x0": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 34, 35, 36, 37, 39, 54, 65, 99, 100], "arm": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 20, 21, 24, 26, 34, 35, 54, 91, 92, 99, 100], "trigger": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 17, 23, 24, 26, 28, 31, 32, 33, 34, 35, 37, 41, 43, 44, 48, 49, 54, 57, 62, 67, 68, 99, 100, 102], "mechan": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 19, 28, 34, 35, 36, 49, 54, 99, 100], "sensit": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 67, 96, 99, 100], "sync": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 18, 20, 21, 26, 27, 28, 30, 32, 34, 35, 37, 39, 40, 42, 44, 46, 47, 54, 59, 76, 90, 99, 100], "onc": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 18, 25, 28, 34, 35, 36, 37, 47, 54, 90, 92, 99, 100, 104], "goe": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 76, 99, 100], "within": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 19, 27, 32, 34, 35, 40, 54, 65, 75, 79, 90, 92, 99, 100, 101], "across": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 36, 37, 49, 54, 88, 92, 96, 99, 100, 106], "instanc": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 18, 19, 22, 24, 26, 27, 28, 34, 35, 36, 37, 39, 54, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90, 91, 96, 99, 100, 101, 105], "effect": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 34, 35, 36, 37, 39, 44, 54, 96, 99, 100], "onli": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 32, 33, 34, 35, 36, 37, 38, 39, 42, 44, 45, 49, 54, 61, 62, 63, 65, 66, 67, 70, 73, 74, 76, 82, 83, 87, 88, 89, 90, 91, 92, 95, 96, 99, 100, 101, 104, 105, 106], "ext_sync": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 24, 34, 35, 54, 99, 100], "synthesi": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 25, 26, 28, 33, 54, 91, 96, 99, 100, 102, 105], "self": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 34, 35, 37, 54, 89, 99, 100], "clear": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 17, 18, 19, 20, 21, 22, 23, 26, 28, 30, 32, 34, 35, 36, 37, 39, 43, 54, 92, 99, 100], "0x12": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 19, 21, 23, 26, 32, 34, 35, 54, 76, 99, 100], "0x48": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 19, 21, 23, 26, 34, 35, 54, 99, 100], "cntrl_2": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "sdr_ddr_n": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100, 101], "repres": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 20, 21, 22, 27, 34, 35, 36, 37, 45, 54, 90, 99, 100], "symb_8_16b": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100, 101], "number": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 32, 34, 35, 36, 37, 38, 39, 42, 44, 46, 47, 48, 49, 51, 53, 54, 55, 56, 57, 59, 60, 61, 62, 63, 65, 66, 67, 68, 69, 70, 73, 74, 75, 76, 79, 80, 81, 82, 83, 88, 89, 90, 91, 92, 99, 100, 101, 104], "symbol": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 96, 99, 100], "format": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 17, 20, 21, 22, 27, 31, 32, 33, 34, 35, 36, 37, 41, 54, 87, 90, 99, 100, 106], "0x21": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 19, 22, 26, 28, 30, 34, 35, 36, 37, 39, 54, 99, 100], "0x84": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 19, 22, 26, 28, 30, 34, 35, 36, 37, 39, 54, 99, 100], "dac_custom_wr": [1, 7, 10, 11, 35, 100], "data_writ": 1, "0x000000": [1, 7, 18, 21, 36, 37], "lsb": [1, 7, 18, 26, 28, 34, 35, 36, 37, 59, 89], "0x22": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 19, 22, 28, 30, 34, 35, 36, 37, 39, 54, 99, 100], "0x88": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 19, 22, 28, 30, 34, 35, 36, 37, 39, 54, 99, 100], "ui_statu": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "if_busi": [1, 7, 10, 11, 35, 100], "ro": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 34, 35, 36, 37, 39, 54, 99, 100, 101], "busi": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 16, 18, 34, 35, 39, 43, 46, 49, 54, 67, 68, 79, 99, 100], "If": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 20, 21, 22, 23, 24, 26, 27, 28, 30, 32, 34, 35, 36, 37, 38, 39, 40, 42, 43, 45, 48, 51, 54, 55, 56, 61, 62, 63, 74, 76, 90, 91, 92, 95, 98, 99, 100, 101, 105, 106], "indic": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 16, 18, 19, 20, 21, 23, 25, 27, 28, 30, 32, 34, 35, 36, 37, 43, 46, 49, 54, 55, 56, 58, 59, 60, 79, 92, 96, 99, 100, 105], "0x23": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 19, 34, 35, 54, 99, 100], "0x8c": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 19, 34, 35, 54, 99, 100], "dac_custom_ctrl": [1, 7, 10, 11, 35, 100], "address": [1, 2, 4, 5, 6, 8, 9, 12, 15, 16, 25, 26, 28, 30, 34, 35, 38, 39, 42, 43, 51, 54, 55, 56, 61, 62, 63, 103], "0x00": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 17, 18, 19, 23, 25, 26, 27, 28, 30, 34, 35, 36, 37, 39, 42, 54, 99, 100], "start": [1, 2, 4, 5, 6, 7, 8, 9, 11, 12, 14, 15, 19, 20, 21, 23, 25, 26, 27, 28, 30, 32, 34, 35, 36, 37, 42, 43, 44, 47, 54, 58, 75, 76, 77, 78, 80, 81, 82, 88, 90, 92, 96, 99, 101, 104, 105], "fsm": [1, 26, 38], "transfer": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 17, 28, 30, 34, 35, 39, 43, 44, 49, 54, 55, 56, 58, 76, 90, 99, 100], "transfer_data": 1, "singl": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 18, 19, 26, 34, 36, 37, 41, 47, 49, 54, 59, 60, 67, 68, 72, 73, 74, 79, 89, 90, 91, 92, 96, 99, 101, 105], "access": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 32, 34, 35, 36, 37, 39, 41, 46, 47, 54, 66, 70, 83, 92, 99, 100, 101, 103], "return": [1, 3, 13, 14, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 32, 36, 37, 39, 92], "chang": [1, 3, 6, 7, 10, 11, 12, 13, 14, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 35, 36, 37, 39, 44, 49, 71, 76, 78, 80, 90, 92, 94, 95, 96, 100, 101, 104, 106], "axi_ad3552r_dac_channel": 1, "0x100": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 19, 20, 21, 27, 28, 30, 34, 35, 36, 37, 39, 54, 99, 100], "0x400": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 20, 21, 25, 27, 34, 35, 54, 99, 100], "chan_cntrl0_7": 1, "dac_dds_sel": [1, 7, 10, 11, 27, 35, 100], "intern": [1, 11, 15, 19, 26, 27, 30, 32, 34, 35, 36, 37, 39, 42, 44, 46, 47, 48, 49, 61, 63, 65, 67, 72, 73, 76, 77, 89, 90, 96, 99, 100, 103], "support": [1, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 19, 23, 25, 26, 27, 30, 32, 39, 42, 45, 46, 49, 54, 55, 56, 59, 60, 61, 63, 65, 91, 94, 95, 97, 98, 99, 100, 105, 106, 107], "tone": [1, 7, 10, 11, 27, 35, 100], "0x01": [1, 7, 10, 11, 21, 22, 23, 27, 30, 35, 42, 100], "pattern": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 21, 23, 27, 32, 34, 35, 54, 99, 100], "sed": [1, 7, 10, 11, 27, 35, 100], "0x02": [1, 7, 10, 11, 27, 35, 36, 37, 39, 100], "0x03": [1, 7, 10, 11, 17, 27, 35, 36, 37, 100], "0x04": [1, 7, 10, 11, 27, 35, 39, 100], "invert": [1, 7, 10, 11, 27, 35, 65, 96, 100], "pn7": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 34, 35, 54, 99, 100], "0x05": [1, 7, 10, 11, 18, 27, 35, 39, 100], "pn15": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 34, 35, 54, 99, 100], "0x06": [1, 7, 10, 11, 27, 35, 100], "150": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 34, 35, 54, 90, 99, 100], "0x07": [1, 7, 10, 11, 27, 35, 100], "0x08": [1, 7, 10, 11, 27, 35, 100], "loopback": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 34, 35, 54, 99, 100], "0x09": [1, 7, 10, 11, 27, 35, 76, 100], "pnx": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 34, 35, 54, 99, 100], "ad9361": [1, 2, 4, 5, 6, 8, 9, 10, 11, 12, 26, 27, 33, 34, 35, 54, 99, 100, 102], "0x0a": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 34, 35, 54, 76, 99, 100], "nibbl": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 34, 35, 54, 58, 99, 100], "ramp": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 34, 35, 54, 99, 100], "adrv9001": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 34, 35, 54, 99, 100], "0x0b": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 34, 35, 54, 99, 100], "0x116": 1, "0x458": 1, "chan_cntrl1_7": 1, "templat": [1, 33, 91, 105], "version": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 18, 19, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 42, 54, 57, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 86, 88, 89, 90, 95, 96, 97, 99, 100, 101], "scratch": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 18, 19, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54, 99, 100], "0x00000000": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 18, 19, 20, 21, 22, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54, 99, 100, 101], "0x1": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 34, 35, 36, 37, 39, 54, 65, 99, 100], "0x4": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 18, 19, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54, 99, 100], "identifi": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 18, 24, 28, 32, 34, 35, 36, 42, 54, 92, 96, 99, 100], "0x2": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 18, 19, 21, 22, 23, 24, 25, 26, 28, 30, 34, 35, 36, 37, 39, 54, 99, 100], "0x8": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 18, 19, 22, 23, 24, 25, 26, 27, 28, 30, 34, 35, 36, 37, 39, 54, 99, 100], "0x3": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 18, 19, 21, 22, 23, 24, 25, 26, 28, 34, 35, 36, 37, 39, 54, 99, 100], "0xc": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 18, 19, 23, 24, 25, 26, 28, 34, 35, 36, 37, 39, 54, 99, 100], "config": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 17, 21, 24, 28, 34, 35, 36, 37, 49, 54, 92, 99, 100, 104], "iqcorrection_dis": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 34, 35, 54, 99, 100], "iq": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 34, 35, 54, 99, 100], "correct": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 17, 19, 27, 32, 34, 35, 36, 37, 49, 54, 59, 61, 63, 65, 96, 99, 100], "wa": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 18, 19, 22, 25, 26, 28, 30, 34, 35, 36, 37, 38, 42, 43, 47, 54, 57, 67, 73, 74, 76, 88, 89, 90, 91, 92, 99, 100, 101, 105], "implement": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 18, 19, 20, 21, 23, 25, 26, 27, 28, 31, 32, 34, 35, 36, 37, 38, 41, 43, 44, 46, 49, 53, 54, 55, 56, 65, 76, 81, 91, 92, 96, 98, 99, 100, 101, 105], "result": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15, 17, 19, 27, 34, 35, 39, 42, 54, 67, 73, 74, 76, 88, 89, 90, 96, 99, 100, 105], "dcfilter_dis": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "dc": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 70, 75, 81, 82, 99, 100], "filter": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 17, 19, 23, 28, 34, 35, 49, 54, 66, 67, 69, 70, 73, 74, 75, 77, 83, 93, 99, 100], "dataformat_dis": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "userports_dis": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 34, 35, 54, 99, 100], "relat": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 19, 23, 34, 35, 36, 37, 54, 99, 100, 101, 105], "decim": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 17, 23, 33, 34, 35, 54, 66, 67, 70, 75, 83, 99, 100, 102], "mode_1r1t": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "sheet": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 67, 88, 99, 100], "delay_control_dis": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "delai": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 17, 19, 23, 24, 26, 27, 34, 35, 36, 41, 42, 46, 48, 49, 51, 54, 55, 99, 100], "cmos_or_lvds_n": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "cmo": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54], "lvd": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 38, 54, 75, 77, 87, 90, 91, 105], "pps_receiver_en": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "pp": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 26, 34, 35, 54, 99, 100], "receiv": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 18, 20, 21, 26, 28, 30, 32, 34, 35, 37, 38, 39, 40, 42, 46, 48, 49, 54, 59, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 86, 88, 89, 90, 100, 105], "enabl": [1, 3, 4, 5, 6, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 26, 27, 28, 30, 32, 34, 35, 36, 37, 38, 39, 43, 45, 47, 48, 54, 55, 56, 58, 59, 60, 61, 62, 63, 65, 66, 67, 70, 74, 75, 76, 83, 88, 90, 96, 99, 100], "scalecorrection_onli": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "scale": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 17, 27, 34, 35, 54, 76, 80, 99, 100], "must": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 16, 18, 19, 20, 21, 22, 23, 24, 26, 27, 28, 32, 34, 35, 36, 37, 38, 42, 43, 51, 54, 59, 61, 63, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90, 91, 92, 95, 96, 99, 100, 101, 105, 106], "transport": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 36, 37, 54, 76, 90, 99, 100, 104], "layer": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 36, 37, 49, 54, 65, 76, 80, 90, 99, 100, 104], "rd_raw_data": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "raw": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 17, 19, 28, 30, 34, 35, 36, 37, 39, 54, 81, 99, 100], "chan_raw_data": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "adc_channel": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "0x10": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 26, 28, 30, 34, 35, 36, 37, 39, 54, 99, 100], "pps_irq_mask": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "interrupt": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 22, 34, 35, 47, 54, 99, 100, 104], "mask": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 18, 19, 23, 30, 34, 35, 36, 37, 39, 54, 99, 100], "1pp": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "0x7": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 23, 28, 34, 35, 54, 99, 100], "0x1c": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 16, 23, 28, 34, 35, 54, 99, 100], "fpga_info": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 34, 35, 54, 99, 100], "inform": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16, 18, 19, 20, 21, 23, 25, 27, 28, 30, 44, 54, 55, 56, 58, 64, 91, 92, 94, 95, 98, 99, 100, 102], "adi_intel_device_info_enc": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "adi_xilinx_device_info_enc": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "axi_ad": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 34, 35, 54, 99, 100], "0x40": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 19, 20, 21, 23, 24, 26, 28, 30, 34, 35, 36, 37, 39, 54, 99, 100], "rstn": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16, 19, 20, 21, 34, 35, 54, 99, 100], "ce_n": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "invers": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 36, 37, 42, 54, 65, 99, 100], "export": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 92, 99, 100, 105], "mmcm_rstn": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16, 34, 35, 54, 99, 100], "mmcm": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16, 34, 35, 54, 99, 100], "reset": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 26, 27, 28, 29, 30, 34, 35, 37, 39, 42, 43, 46, 47, 48, 53, 54, 55, 56, 58, 59, 60, 62, 69, 84, 96, 99, 100, 104], "drp": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 16, 19, 34, 35, 54, 99, 100], "IN": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16, 19, 34, 35, 54, 73, 76, 78, 81, 82, 84, 89, 90, 99, 100], "bring": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 16, 19, 20, 21, 24, 34, 35, 36, 37, 54, 99, 100], "up": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 16, 19, 20, 21, 23, 24, 26, 27, 28, 30, 34, 35, 36, 37, 39, 44, 54, 59, 60, 65, 66, 67, 69, 70, 72, 73, 74, 76, 77, 78, 83, 88, 92, 95, 99, 100, 101, 104, 105], "ext_sync_disarm": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "disarm": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "manual_sync_request": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 37, 54, 99, 100], "issu": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 36, 37, 54, 92, 99, 100, 105, 106], "event": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 17, 18, 23, 24, 26, 27, 28, 30, 31, 32, 34, 35, 36, 37, 40, 41, 42, 43, 48, 54, 99, 100], "hook": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "insid": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 17, 19, 22, 25, 34, 35, 44, 49, 54, 65, 91, 92, 95, 96, 99, 100, 101, 103, 104, 105], "fabric": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 34, 35, 36, 37, 54, 76, 99, 100], "symb_op": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "num_lan": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 36, 37, 54, 99, 100], "activ": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15, 17, 18, 19, 20, 21, 24, 26, 28, 30, 34, 35, 36, 37, 39, 42, 43, 46, 47, 48, 54, 55, 56, 58, 59, 60, 76, 96, 99, 100, 103], "lane": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 16, 28, 34, 35, 38, 54, 65, 67, 76, 90, 92, 99, 100, 101, 104], "cssi": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "lssi": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "par_typ": [1, 7, 10, 11, 35, 100], "pariti": [1, 7, 10, 11, 35, 100], "even": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 18, 30, 32, 34, 35, 36, 37, 43, 54, 62, 91, 96, 99, 100], "odd": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "par_enb": [1, 7, 10, 11, 35, 100], "frame": [1, 7, 10, 11, 20, 21, 26, 32, 34, 35, 36, 37, 38, 58, 76, 80, 90, 99, 100], "r1_mode": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "data_format": [1, 7, 10, 11, 35, 100], "complement": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 27, 34, 35, 54, 99, 100], "offset": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16, 24, 25, 26, 27, 34, 35, 36, 37, 54, 55, 56, 66, 67, 68, 69, 70, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90, 91, 96, 99, 100], "binari": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 34, 35, 54, 96, 99, 100], "NOT": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 27, 28, 34, 35, 54, 90, 92, 99, 100], "applic": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 17, 18, 25, 26, 27, 28, 30, 36, 37, 38, 39, 41, 50, 54, 67, 69, 71, 72, 78, 79, 80, 81, 88, 89, 92, 99, 100], "dac_dp_dis": [1, 7, 10, 11, 27, 35, 100], "reserv": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 18, 21, 25, 28, 32, 34, 35, 36, 37, 42, 51, 54, 96, 99, 100, 101], "na": [1, 7, 10, 11, 35, 100], "0x13": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 17, 21, 23, 26, 34, 35, 54, 76, 99, 100], "0x4c": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 17, 21, 23, 26, 34, 35, 54, 99, 100], "ratecntrl": [1, 7, 10, 11, 35, 100], "possibl": [1, 7, 10, 11, 14, 18, 19, 21, 26, 27, 28, 32, 35, 36, 37, 39, 41, 45, 49, 67, 79, 92, 95, 96, 100, 105, 106], "sampl": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 17, 18, 20, 21, 23, 27, 28, 32, 34, 35, 36, 37, 38, 39, 42, 54, 58, 59, 60, 62, 66, 67, 68, 70, 72, 73, 74, 75, 76, 77, 78, 80, 81, 82, 83, 89, 90, 99, 100], "0x14": [1, 2, 7, 10, 11, 13, 14, 15, 17, 18, 22, 23, 24, 26, 28, 35, 36, 37, 39, 100], "0x50": [1, 7, 10, 11, 13, 15, 16, 17, 19, 23, 26, 30, 35, 67, 100], "usual": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 28, 34, 35, 54, 59, 60, 90, 91, 92, 99, 100, 106], "dci": [1, 7, 10, 11, 35, 100], "period": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 16, 19, 22, 24, 26, 27, 32, 34, 35, 36, 37, 49, 54, 99, 100], "puls": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16, 22, 24, 26, 27, 34, 35, 37, 54, 99, 100], "0x15": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 17, 20, 21, 23, 26, 34, 35, 54, 99, 100], "0x54": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 17, 19, 20, 21, 23, 26, 34, 35, 54, 99, 100], "status1": [1, 7, 10, 11, 35, 100], "clk_freq": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 20, 21, 34, 35, 54, 99, 100], "rel": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 20, 21, 24, 26, 34, 35, 36, 37, 42, 54, 92, 99, 100], "processor": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 20, 21, 22, 34, 35, 36, 37, 54, 67, 76, 88, 91, 92, 99, 100, 103], "mani": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 20, 21, 26, 28, 34, 35, 36, 37, 54, 55, 56, 79, 81, 88, 90, 92, 96, 99, 100], "case": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 17, 18, 19, 20, 21, 22, 26, 27, 30, 32, 34, 35, 36, 37, 39, 42, 44, 49, 54, 55, 56, 58, 59, 60, 65, 73, 74, 88, 89, 90, 91, 92, 95, 96, 99, 100, 101, 105, 106, 107], "100mhz": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 19, 20, 21, 22, 23, 25, 29, 30, 34, 35, 36, 37, 49, 54, 99, 100], "unsign": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 20, 21, 22, 27, 30, 32, 34, 35, 36, 37, 54, 99, 100], "assum": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 20, 21, 22, 28, 32, 34, 35, 36, 37, 39, 45, 48, 49, 54, 57, 92, 95, 99, 100, 106], "minimum": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 20, 21, 22, 27, 34, 35, 36, 37, 42, 44, 49, 54, 69, 99, 100], "523khz": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 20, 21, 22, 34, 35, 36, 37, 54, 99, 100], "554thz": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 20, 21, 22, 34, 35, 54, 99, 100], "actual": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 17, 20, 21, 27, 32, 34, 35, 36, 37, 49, 54, 55, 56, 66, 67, 68, 69, 70, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90, 91, 92, 94, 99, 100, 105], "clk_ratio": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 20, 21, 27, 34, 35, 54, 99, 100], "see": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 18, 20, 21, 24, 27, 30, 32, 33, 34, 35, 36, 37, 38, 44, 47, 49, 54, 59, 60, 65, 66, 67, 68, 69, 70, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 87, 88, 89, 90, 91, 92, 95, 99, 100, 101, 104, 105], "below": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 17, 19, 20, 21, 24, 27, 30, 32, 34, 35, 36, 37, 39, 49, 54, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90, 91, 92, 94, 96, 99, 100], "note": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 18, 20, 21, 27, 28, 34, 35, 36, 37, 42, 54, 56, 58, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 86, 88, 89, 90, 95, 99, 100, 106], "mai": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 16, 20, 21, 25, 28, 34, 35, 36, 37, 38, 42, 44, 45, 54, 59, 60, 82, 92, 95, 96, 99, 100, 105, 106], "same": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 17, 18, 20, 21, 23, 24, 26, 27, 28, 32, 34, 35, 36, 37, 40, 41, 42, 44, 47, 49, 54, 56, 59, 60, 65, 76, 83, 88, 91, 92, 96, 98, 99, 100, 101, 106], "consid": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 20, 21, 32, 34, 35, 36, 37, 54, 59, 60, 94, 99, 100], "calcul": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 19, 20, 21, 27, 34, 35, 36, 37, 44, 54, 66, 67, 68, 69, 70, 73, 74, 75, 79, 81, 82, 83, 88, 89, 99, 100], "final": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 20, 21, 23, 27, 34, 35, 37, 54, 58, 81, 91, 92, 99, 100], "0x16": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 17, 20, 21, 26, 27, 34, 35, 54, 99, 100, 101], "0x58": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 17, 20, 21, 26, 27, 34, 35, 54, 99, 100], "status2": [1, 7, 10, 11, 35, 100], "ratio": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 17, 20, 21, 24, 28, 34, 35, 36, 37, 54, 56, 61, 63, 65, 67, 73, 74, 81, 99, 100], "factor": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 17, 20, 21, 27, 34, 35, 38, 54, 60, 99, 100], "ani": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 18, 19, 20, 21, 23, 26, 28, 30, 32, 34, 35, 36, 37, 38, 39, 49, 54, 59, 60, 61, 63, 81, 90, 92, 94, 95, 96, 98, 99, 100, 101, 105], "parallel": [1, 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 20, 21, 27, 34, 35, 36, 37, 39, 46, 47, 53, 54, 66, 70, 83, 92, 99, 100], "convers": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 20, 21, 28, 34, 35, 36, 37, 54, 58, 67, 72, 77, 78, 89, 99, 100], "qdr": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 20, 21, 34, 35, 54, 99, 100], "0x17": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16, 17, 21, 26, 34, 35, 54, 99, 100], "0x5c": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16, 17, 21, 26, 34, 35, 54, 99, 100], "status3": [1, 7, 10, 11, 35, 100], "error": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 18, 19, 21, 30, 34, 35, 36, 37, 54, 58, 65, 75, 96, 99, 100, 105], "try": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 21, 34, 35, 54, 92, 96, 99, 100, 106], "0x18": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 17, 20, 21, 22, 23, 24, 26, 28, 34, 35, 36, 37, 54, 99, 100], "0x60": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 17, 20, 21, 26, 30, 34, 35, 54, 99, 100], "dac_clksel": [1, 7, 10, 11, 35, 100], "allow": [1, 4, 5, 6, 7, 8, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 26, 27, 28, 30, 31, 32, 34, 35, 36, 37, 38, 39, 41, 42, 47, 48, 49, 54, 57, 59, 60, 62, 66, 67, 69, 70, 72, 75, 77, 79, 83, 89, 96, 100], "polar": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 26, 34, 35, 42, 54, 65, 99, 100], "its": [1, 7, 10, 11, 18, 19, 21, 22, 24, 26, 28, 30, 32, 35, 36, 37, 39, 41, 49, 50, 56, 59, 60, 66, 70, 77, 83, 90, 92, 95, 96, 100, 104, 105], "clk_edge_sel": [1, 7, 10, 11, 35, 100], "0x1a": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 21, 34, 35, 54, 99, 100], "0x68": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 21, 34, 35, 54, 99, 100], "sync_statu": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 37, 54, 99, 100], "dac_sync_statu": [1, 7, 10, 11, 35, 100], "Will": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 46, 54, 57, 99, 100], "while": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 19, 24, 26, 28, 32, 34, 35, 36, 37, 39, 41, 54, 67, 71, 72, 73, 74, 79, 88, 92, 99, 100, 101], "wait": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 17, 18, 19, 24, 26, 32, 34, 35, 39, 42, 44, 54, 99, 100, 104], "0x70": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16, 34, 35, 54, 99, 100], "drp_cntrl": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16, 34, 35, 54, 99, 100], "28": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 16, 28, 34, 35, 36, 37, 54, 58, 90, 91, 99, 100], "drp_rwn": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16, 34, 35, 54, 99, 100], "doe": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 15, 16, 18, 19, 28, 30, 32, 34, 35, 36, 37, 42, 54, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90, 92, 95, 96, 98, 99, 100, 101, 106], "includ": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 16, 18, 30, 32, 34, 35, 36, 37, 38, 54, 67, 70, 72, 77, 78, 88, 92, 94, 96, 99, 100, 101, 104], "gtx": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 16, 34, 35, 54, 65, 91, 99, 100], "drp_disabl": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "27": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 16, 28, 34, 35, 36, 37, 54, 75, 90, 91, 99, 100], "drp_address": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16, 34, 35, 54, 99, 100], "0x000": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16, 18, 34, 35, 36, 37, 54, 99, 100], "more": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16, 17, 18, 21, 23, 24, 25, 26, 27, 28, 30, 32, 39, 43, 49, 54, 59, 60, 64, 91, 92, 94, 95, 96, 99, 100, 101, 104, 105], "than": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18, 19, 23, 25, 26, 27, 28, 34, 35, 36, 37, 39, 43, 54, 62, 66, 70, 81, 83, 91, 92, 96, 99, 100, 101, 104], "one": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 16, 17, 18, 19, 24, 25, 26, 27, 28, 30, 32, 34, 35, 36, 37, 38, 39, 42, 43, 44, 47, 49, 54, 58, 59, 60, 62, 65, 67, 75, 90, 91, 92, 95, 96, 99, 100, 101, 104, 105, 106], "primit": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 16, 19, 34, 35, 45, 54, 65, 99, 100], "most": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 16, 28, 32, 34, 35, 45, 49, 54, 79, 82, 92, 99, 100, 105, 106], "signific": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 16, 28, 32, 34, 35, 38, 54, 99, 100], "0x0000": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16, 20, 21, 27, 30, 34, 35, 36, 37, 54, 99, 100], "backward": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 34, 35, 36, 37, 54, 99, 100], "0x1d": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16, 34, 35, 54, 99, 100], "0x74": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16, 34, 35, 54, 99, 100], "drp_statu": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16, 34, 35, 54, 99, 100], "drp_lock": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "pll": [1, 7, 10, 11, 15, 16, 35, 38, 99, 100], "lock": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 16, 34, 35, 54, 92, 99, 100], "pend": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16, 18, 34, 35, 36, 37, 39, 54, 99, 100], "0x1e": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "0x78": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 32, 34, 35, 54, 99, 100], "drp_wdata": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16, 34, 35, 54, 99, 100], "0x1f": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "0x7c": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "drp_rdata": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16, 34, 35, 54, 99, 100], "0x20": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 18, 19, 20, 23, 24, 26, 28, 30, 34, 35, 36, 37, 39, 54, 99, 100], "0x80": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 18, 19, 20, 24, 26, 28, 30, 34, 35, 36, 37, 39, 54, 99, 100], "dac_custom_rd": [1, 7, 10, 11, 35, 100], "custom": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 25, 34, 35, 36, 37, 38, 49, 54, 61, 63, 91, 95, 97, 99, 100, 101], "ui_ovf": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "rw1c": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 18, 19, 20, 21, 22, 23, 26, 28, 34, 35, 36, 37, 39, 54, 99, 100], "overflow": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 18, 20, 21, 27, 28, 34, 35, 54, 59, 63, 99, 100], "occur": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 18, 19, 30, 32, 34, 35, 36, 37, 39, 42, 43, 54, 99, 100], "dure": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 19, 28, 30, 32, 34, 35, 36, 37, 42, 54, 65, 92, 99, 100, 101], "fifo": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 18, 23, 28, 32, 33, 34, 35, 44, 54, 57, 59, 60, 61, 63, 102], "ui_unf": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "underflow": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 17, 18, 20, 21, 28, 34, 35, 54, 61, 99, 100], "0x28": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 23, 34, 35, 54, 99, 100], "0xa0": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 34, 35, 36, 37, 54, 99, 100], "usr_cntrl_1": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "usr_chanmax": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "multiplex": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 22, 23, 27, 34, 35, 41, 54, 99, 100], "add": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 28, 34, 35, 44, 54, 55, 56, 76, 90, 91, 92, 93, 99, 100, 101, 104, 105, 107], "differ": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 17, 18, 19, 20, 22, 24, 26, 28, 32, 34, 35, 36, 37, 38, 40, 41, 44, 47, 49, 54, 55, 56, 58, 59, 65, 67, 76, 81, 83, 88, 89, 90, 91, 92, 95, 96, 99, 100, 106], "process": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 18, 19, 20, 21, 27, 28, 34, 35, 36, 37, 38, 39, 41, 42, 46, 49, 54, 61, 63, 69, 72, 79, 80, 81, 88, 91, 92, 95, 96, 99, 100, 105], "0x2e": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 22, 34, 35, 54, 99, 100], "0xb8": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 22, 34, 35, 54, 99, 100], "dac_gpio_in": [1, 7, 10, 11, 35, 100], "gpio": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 92, 99, 100, 105], "auxiliari": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "gpi": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "pin": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 17, 21, 22, 23, 42, 49, 54, 65, 66, 67, 69, 70, 72, 73, 74, 76, 78, 83, 84, 89, 91, 99, 100, 101, 103, 105], "0x2f": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 34, 35, 54, 99, 100], "0xbc": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 34, 35, 54, 99, 100], "dac_gpio_out": [1, 7, 10, 11, 35, 100], "gpo": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "gpio_dis": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 35, 54, 99, 100], "n": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 18, 19, 26, 27, 30, 34, 35, 36, 37, 42, 49, 51, 54, 57, 65, 76, 80, 92, 96, 99, 100, 101, 105], "chan_cntrln_1": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 34, 35, 54, 99, 100], "where": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 18, 19, 23, 25, 26, 27, 28, 30, 34, 35, 36, 37, 44, 49, 54, 67, 71, 76, 80, 90, 92, 95, 96, 99, 100, 101, 105], "dds_phase_dw": [1, 7, 10, 11, 27, 35, 100], "width": [1, 2, 7, 10, 11, 13, 16, 19, 22, 24, 25, 26, 27, 32, 35, 36, 37, 39, 40, 46, 47, 48, 49, 52, 53, 54, 55, 56, 57, 59, 60, 61, 62, 63, 65, 96, 100, 101], "offer": [1, 7, 10, 11, 27, 35, 39, 41, 49, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 86, 88, 89, 90, 100], "hdl": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 28, 34, 35, 44, 49, 54, 58, 85, 94, 97, 98, 99, 100, 104, 106, 107], "conjunct": [1, 7, 10, 11, 27, 35, 100], "chan_cntrl_9": [1, 7, 10, 11, 27, 35, 100], "chan_cntrl_10": [1, 7, 10, 11, 27, 35, 100], "info": [1, 7, 10, 11, 15, 17, 24, 25, 27, 32, 35, 39, 52, 65, 92, 100], "ad": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 28, 33, 34, 35, 38, 42, 49, 54, 66, 67, 68, 69, 70, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90, 91, 92, 96, 99, 100, 101, 102, 104, 105], "dds_scale_1": [1, 7, 10, 11, 27, 35, 100], "amplitud": [1, 7, 10, 11, 14, 27, 35, 82, 100], "fix": [1, 7, 10, 11, 18, 25, 27, 35, 36, 37, 42, 44, 96, 100, 105], "point": [1, 7, 10, 11, 17, 18, 19, 25, 26, 27, 28, 35, 36, 37, 39, 40, 69, 92, 100], "sign": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 17, 27, 34, 35, 38, 54, 57, 99, 100, 105], "integ": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 17, 27, 34, 35, 36, 37, 54, 99, 100], "fraction": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 17, 27, 34, 35, 54, 99, 100], "run": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 22, 23, 24, 25, 26, 27, 28, 34, 35, 36, 37, 39, 49, 65, 67, 71, 73, 74, 75, 76, 77, 80, 88, 89, 90, 91, 92, 100, 101, 105, 106], "you": [1, 4, 5, 6, 7, 8, 10, 11, 12, 27, 28, 34, 35, 36, 37, 38, 54, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90, 91, 92, 95, 98, 100, 101, 102, 104, 105, 106], "do": [1, 7, 10, 11, 15, 18, 19, 27, 28, 30, 35, 36, 37, 38, 39, 49, 55, 91, 92, 95, 96, 100, 105, 106], "both": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 16, 18, 19, 23, 26, 27, 28, 30, 32, 34, 35, 36, 37, 40, 43, 54, 55, 56, 65, 66, 67, 70, 72, 73, 76, 83, 89, 91, 92, 96, 99, 100, 105], "0x4000": [1, 7, 10, 11, 27, 35, 100], "over": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16, 18, 22, 24, 27, 30, 31, 34, 35, 36, 39, 41, 49, 54, 71, 81, 88, 92, 95, 99, 100], "tone_1_fullscal": [1, 7, 10, 11, 27, 35, 100], "scale_1": [1, 7, 10, 11, 27, 35, 100], "tone_2_fullscal": [1, 7, 10, 11, 27, 35, 100], "scale_2": [1, 7, 10, 11, 27, 35, 100], "0x101": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 20, 21, 27, 34, 35, 54, 99, 100], "0x404": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 20, 21, 27, 34, 35, 54, 99, 100], "chan_cntrln_2": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 34, 35, 54, 99, 100], "dds_init_1": [1, 7, 10, 11, 27, 35, 100], "initi": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 18, 25, 26, 27, 34, 35, 36, 54, 60, 99, 100, 101], "dds_incr_1": [1, 7, 10, 11, 27, 35, 100], "accumul": [1, 7, 10, 11, 18, 27, 35, 58, 100], "Its": [1, 7, 10, 11, 18, 19, 27, 35, 36, 37, 100], "incr": [1, 7, 10, 11, 21, 27, 35, 100], "f_": [1, 7, 10, 11, 27, 35, 42, 49, 51, 100], "clkratio": [1, 7, 10, 11, 27, 35, 100], "f_out": [1, 7, 10, 11, 27, 35, 100], "f_if": [1, 7, 10, 11, 27, 35, 100], "clock_ratio": [1, 7, 10, 11, 27, 35, 100], "between": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 17, 18, 21, 22, 23, 24, 26, 27, 28, 32, 34, 35, 36, 37, 38, 40, 43, 44, 47, 49, 54, 55, 56, 58, 61, 63, 65, 78, 89, 91, 95, 99, 100, 105], "greater": [1, 7, 10, 11, 14, 19, 27, 35, 36, 37, 100], "chan_cntrl_1": [1, 7, 10, 11, 27, 35, 100], "increment": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 24, 27, 28, 34, 35, 36, 37, 39, 54, 99, 100, 101, 106], "extend": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 27, 34, 35, 37, 54, 57, 70, 73, 96, 99, 100], "0x102": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 21, 27, 34, 35, 54, 99, 100], "0x408": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 21, 27, 34, 35, 54, 99, 100], "chan_cntrln_3": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 34, 35, 54, 99, 100, 101], "dds_scale_2": [1, 7, 10, 11, 27, 35, 100], "0x103": [1, 7, 10, 11, 18, 27, 35, 100], "0x40c": [1, 7, 10, 11, 18, 27, 35, 100], "chan_cntrln_4": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 34, 35, 54, 99, 100], "dds_init_2": [1, 7, 10, 11, 27, 35, 100], "init": [1, 7, 10, 11, 25, 27, 35, 100], "dds_incr_2": [1, 7, 10, 11, 27, 35, 100], "0x104": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 19, 27, 28, 34, 35, 36, 37, 39, 54, 99, 100], "0x410": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 27, 34, 35, 54, 99, 100], "chan_cntrln_5": [1, 7, 10, 11, 27, 35, 100], "dds_patt_2": [1, 7, 10, 11, 27, 35, 100], "dds_patt_1": [1, 7, 10, 11, 27, 35, 100], "0x105": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 27, 34, 35, 54, 99, 100], "0x414": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 27, 34, 35, 54, 99, 100], "chan_cntrln_6": [1, 7, 10, 11, 27, 35, 100], "iqcor_enb": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 34, 35, 54, 99, 100], "dac_lb_owr": [1, 7, 10, 11, 27, 35, 100], "forc": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 27, 28, 34, 35, 54, 96, 99, 100], "dac_pn_owr": [1, 7, 10, 11, 27, 35, 100], "thei": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 18, 19, 25, 26, 27, 30, 32, 34, 35, 36, 37, 38, 40, 44, 49, 54, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90, 92, 94, 96, 99, 100, 101, 107], "ignor": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 18, 23, 26, 27, 28, 30, 32, 34, 35, 36, 37, 54, 92, 95, 99, 100], "IF": [1, 7, 10, 11, 27, 34, 35, 36, 38, 90, 100], "0x106": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 27, 34, 35, 54, 99, 100], "0x418": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 27, 34, 35, 54, 99, 100], "chan_cntrln_7": [1, 7, 10, 11, 27, 35, 100], "0x107": [1, 7, 10, 11, 18, 27, 35, 100], "0x41c": [1, 7, 10, 11, 18, 27, 35, 100], "chan_cntrln_8": [1, 7, 10, 11, 27, 35, 100], "iqcor_coeff_1": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 34, 35, 54, 99, 100], "equip": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 17, 20, 21, 27, 34, 35, 38, 54, 67, 79, 88, 89, 99, 100], "coeffici": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 17, 27, 34, 35, 54, 99, 100], "matrix": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 34, 35, 54, 99, 100], "iqcor_coeff_2": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 34, 35, 54, 99, 100], "q": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 34, 35, 37, 54, 72, 76, 80, 99, 100], "0x108": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 19, 27, 34, 35, 36, 37, 39, 54, 99, 100], "0x420": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 27, 34, 35, 54, 99, 100], "usr_cntrln_3": [1, 7, 10, 11, 27, 35, 100], "usr_datatype_b": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 34, 35, 54, 99, 100], "big": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 34, 35, 54, 99, 100], "endian": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 34, 35, 54, 99, 100], "littl": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 34, 35, 54, 99, 100], "usr_datatype_sign": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 34, 35, 54, 99, 100], "usr_datatype_shift": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 34, 35, 54, 99, 100], "amount": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 27, 34, 35, 36, 42, 49, 54, 99, 100], "right": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 22, 27, 30, 34, 35, 54, 92, 96, 99, 100], "shift": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 34, 35, 42, 46, 48, 54, 99, 100], "total": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 27, 34, 35, 36, 37, 42, 44, 54, 92, 99, 100], "usr_datatype_total_bit": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 34, 35, 54, 99, 100], "align": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 26, 27, 28, 34, 35, 38, 54, 59, 65, 96, 99, 100], "usr_datatype_bit": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 34, 35, 54, 99, 100], "0x109": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 27, 34, 35, 54, 99, 100], "0x424": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 27, 34, 35, 54, 99, 100], "usr_cntrln_4": [1, 7, 10, 11, 27, 35, 100], "usr_interpolation_m": [1, 7, 10, 11, 27, 35, 100], "hold": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 17, 18, 19, 23, 25, 27, 30, 34, 35, 36, 37, 46, 49, 54, 73, 77, 99, 100], "interpol": [1, 7, 10, 11, 19, 27, 33, 35, 100, 102], "m": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 19, 27, 34, 35, 36, 37, 42, 44, 54, 65, 90, 99, 100], "being": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 17, 18, 26, 27, 34, 35, 36, 37, 38, 42, 47, 49, 54, 57, 88, 91, 92, 95, 96, 99, 100, 106], "abov": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 19, 21, 26, 27, 28, 30, 34, 35, 37, 39, 44, 45, 54, 61, 63, 91, 92, 96, 99, 100, 101, 105], "form": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 27, 28, 29, 34, 35, 36, 37, 38, 49, 54, 81, 90, 99, 100], "usr_interpolation_n": [1, 7, 10, 11, 27, 35, 100], "0x10a": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 27, 34, 35, 54, 99, 100], "0x428": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 27, 34, 35, 54, 99, 100], "usr_cntrln_5": [1, 7, 10, 11, 27, 35, 100], "dac_iq_mod": [1, 7, 10, 11, 27, 35, 100], "complex": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 32, 34, 35, 54, 66, 70, 83, 88, 96, 99, 100], "In": [1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 18, 19, 20, 21, 22, 26, 27, 28, 30, 34, 35, 36, 37, 39, 43, 45, 49, 54, 55, 56, 58, 65, 67, 70, 73, 74, 76, 77, 81, 88, 89, 91, 92, 95, 96, 99, 100, 101, 104, 105, 106, 107], "driven": [1, 7, 10, 11, 23, 27, 28, 30, 35, 39, 72, 73, 74, 91, 100, 103], "sequenc": [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 22, 27, 30, 32, 34, 35, 36, 54, 74, 99, 100], "pair": [1, 7, 10, 11, 18, 27, 32, 35, 74, 100, 104], "dac_iq_swap": [1, 7, 10, 11, 27, 35, 100], "swap": [1, 7, 10, 11, 27, 35, 92, 100, 104], "take": [1, 7, 8, 9, 10, 11, 27, 28, 35, 36, 37, 38, 44, 47, 49, 55, 56, 81, 90, 91, 100, 101], "0x10b": [1, 7, 10, 11, 18, 27, 35, 100], "0x42c": [1, 7, 10, 11, 18, 27, 35, 100], "chan_cntrln_9": [1, 7, 10, 11, 27, 35, 100], "dds_init_1_extend": [1, 7, 10, 11, 27, 35, 100], "accord": [1, 4, 5, 7, 10, 11, 24, 27, 34, 35, 36, 37, 42, 56, 58, 100], "dds_incr_1_extend": [1, 7, 10, 11, 27, 35, 100], "phasedw": [1, 7, 10, 11, 27, 35, 100], "found": [1, 2, 6, 7, 8, 10, 11, 12, 16, 27, 28, 34, 35, 49, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90, 91, 92, 93, 95, 96, 98, 99, 100, 101, 105, 107], "0x10c": [1, 7, 10, 11, 18, 19, 27, 35, 100], "0x430": [1, 7, 10, 11, 18, 27, 35, 100], "chan_cntrln_10": [1, 7, 10, 11, 27, 35, 100], "dds_init_2_extend": [1, 7, 10, 11, 27, 35, 100], "chan_cntrl_2": [1, 7, 10, 11, 27, 35, 100], "dds_incr_2_extend": [1, 7, 10, 11, 27, 35, 100], "done": [1, 4, 5, 6, 7, 8, 9, 10, 11, 12, 17, 18, 23, 26, 27, 34, 35, 36, 47, 54, 73, 74, 78, 88, 89, 92, 104, 106], "through": [1, 2, 4, 5, 6, 7, 8, 9, 10, 12, 14, 15, 17, 18, 20, 21, 23, 24, 26, 27, 31, 32, 34, 35, 36, 37, 38, 39, 54, 59, 60, 62, 65, 67, 69, 76, 78, 81, 84, 90, 96, 98, 99, 100], "connect": [1, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 21, 28, 30, 34, 35, 36, 37, 38, 39, 41, 43, 45, 47, 49, 54, 65, 96, 103, 104], "io": [1, 4, 5, 6, 8, 12, 14, 18, 20, 23, 36, 37, 49, 54, 65, 84, 91, 99, 100, 105], "move": [1, 4, 5, 6, 8, 9, 12, 18, 54], "befor": [1, 2, 4, 5, 6, 7, 8, 9, 11, 12, 14, 15, 18, 19, 22, 23, 26, 28, 32, 34, 36, 42, 51, 54, 55, 56, 62, 76, 92, 95, 96, 99, 101, 105, 106], "level": [1, 4, 5, 6, 7, 8, 9, 12, 14, 17, 19, 23, 24, 27, 29, 30, 34, 35, 36, 37, 38, 39, 41, 42, 45, 46, 54, 55, 56, 69, 71, 74, 78, 79, 92, 96, 99, 100, 105], "program": [1, 4, 5, 6, 7, 8, 10, 12, 15, 18, 20, 21, 30, 31, 37, 39, 41, 43, 48, 54, 77, 92, 95, 97], "your": [1, 4, 5, 6, 8, 12, 28, 38, 54, 65, 71, 76, 77, 80, 90, 93, 95, 101, 102, 105, 106], "linux": [1, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 23, 31, 32, 36, 37, 41, 54, 58, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 86, 88, 89, 90, 91, 105, 106], "dual": [1, 7, 9, 10, 11, 27, 28, 30, 32, 34, 35, 38, 41, 58, 67, 72, 74, 76, 78, 80, 81, 84, 91], "33": [1, 28, 66, 67, 70, 74, 76, 81, 82, 83, 84, 89, 90, 91], "mup": [1, 84], "multispan": [1, 84], "multi": [1, 15, 46, 84, 96, 101], "driver": [1, 2, 15, 18, 20, 21, 30, 31, 32, 33, 36, 37, 38, 41, 58, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 86, 88, 89, 90, 92, 102], "ad3552r_evb": 1, "adi": [1, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16, 17, 18, 19, 23, 25, 28, 33, 34, 35, 36, 37, 38, 39, 49, 54, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 88, 89, 90, 92, 93, 95, 97, 98, 103, 106, 107], "7000": [1, 4, 5, 6, 7, 8, 11, 12, 54, 58, 66, 67, 68, 69, 70, 73, 74, 75, 76, 77, 79, 81, 82, 83, 84, 88, 89, 90, 91], "soc": [1, 4, 5, 6, 7, 8, 11, 12, 20, 21, 54, 67, 91, 92, 105], "overview": [1, 4, 5, 6, 7, 8, 11, 12, 31, 41, 54], "pinout": [1, 2, 4, 5, 6, 7, 8, 11, 12, 54], "s_axis_axi_aclks_axi_aresetnexternal_clkrx_db_irx_busyfirst_dataadc_dovfadc_clkadc_resetrx_cs_nrx_db_orx_db_trx_rd_nrx_wr_nadc_validadc_data_": 2, "adc_enable_": [2, 4, 5, 12], "axi_ad7606x": [2, 73, 95], "simpl": [2, 3, 7, 10, 18, 28, 36, 37, 42, 49, 55, 56, 60, 65, 73, 74, 93, 99, 105], "about": [2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 17, 23, 25, 28, 30, 38, 39, 55, 56, 65, 90, 91, 92, 95, 101, 105], "framework": [2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 23, 33, 34, 35, 40, 41, 46, 49, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90, 92, 98, 99, 100, 105], "up_adc_channel": [2, 4, 5, 6, 7, 8, 9, 11, 54, 99], "up_adc_common": [2, 4, 5, 6, 7, 8, 9, 11, 12, 54, 99], "descript": [2, 3, 15, 16, 18, 22, 25, 27, 29, 30, 32, 34, 35, 36, 37, 39, 40, 42, 43, 45, 46, 47, 48, 50, 51, 52, 53, 57, 58, 61, 63, 65, 66, 69, 70, 72, 73, 74, 75, 82, 83, 88, 89, 91, 96, 99, 100, 101, 103, 107], "regmap": [2, 6, 7, 8, 9, 10, 11, 24, 95, 99, 100, 101, 104], "dev_config": [2, 73], "defin": [2, 3, 7, 10, 14, 15, 18, 19, 21, 22, 23, 24, 26, 28, 31, 32, 35, 36, 37, 38, 40, 41, 46, 49, 55, 56, 59, 60, 61, 63, 65, 67, 73, 74, 76, 80, 88, 89, 90, 91, 92, 95, 96, 99, 100, 101, 103, 105], "which": [2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 32, 36, 37, 38, 39, 40, 41, 42, 44, 45, 46, 48, 49, 51, 52, 54, 55, 56, 57, 62, 65, 67, 68, 69, 73, 76, 78, 81, 82, 84, 88, 90, 91, 92, 95, 96, 99, 100, 103, 105, 106], "adc_to_dma_n_bit": 2, "transmit": [2, 7, 10, 14, 15, 17, 20, 21, 26, 28, 32, 35, 36, 38, 40, 46, 65, 67, 70, 76, 78, 90, 105], "32": [2, 7, 10, 14, 18, 19, 25, 26, 27, 28, 32, 34, 35, 36, 37, 39, 46, 49, 55, 57, 59, 60, 61, 62, 63, 66, 67, 68, 69, 70, 73, 74, 75, 76, 79, 80, 81, 82, 83, 84, 88, 89, 90, 91, 96, 99, 100, 104], "adc_n_bit": 2, "external_clk": 2, "option": [2, 7, 14, 15, 18, 21, 26, 28, 32, 35, 36, 37, 46, 49, 66, 67, 70, 72, 73, 75, 77, 79, 83, 88, 89, 92, 96, 99, 100, 104], "No": [2, 13, 15, 17, 32, 36, 37, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 86, 88, 89, 90, 96], "ye": [2, 67, 73], "adc_clk": [2, 4, 5, 6, 8, 9, 11, 12, 13, 99], "adc_reset": [2, 4, 5, 73], "correspond": [2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 18, 19, 22, 23, 26, 34, 35, 36, 37, 42, 54, 76, 92, 99, 105], "rx_cs_n": [2, 3], "rx_db_o": [2, 3], "rx_db_i": [2, 3], "rx_db_t": [2, 3], "t": [2, 3, 14, 18, 26, 27, 28, 29, 30, 32, 37, 42, 44, 51, 76, 80, 90, 92, 94, 95, 101, 105, 106], "iobuf": [2, 3], "rx_rd_n": [2, 3], "rx_wr_n": [2, 3], "rx_busi": 2, "first_data": 2, "first": [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 17, 18, 20, 21, 22, 25, 26, 27, 30, 32, 34, 36, 37, 38, 39, 44, 47, 54, 55, 56, 59, 76, 90, 91, 92, 94, 96, 99, 100, 101, 104, 105, 106], "bu": [2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 18, 19, 23, 26, 27, 28, 29, 30, 31, 32, 34, 35, 36, 37, 39, 40, 41, 42, 46, 47, 48, 49, 54, 55, 56, 59, 60, 61, 63, 79, 81, 99, 100, 101, 103], "adc_dovf": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 99], "adc_valid": [2, 3, 4, 5, 6, 8, 9, 12, 23, 34], "show": [2, 3, 24, 26, 34, 35, 36, 45, 65, 90, 92, 96, 103], "adc_data_": [2, 4, 5], "sever": [2, 7, 9, 10, 11, 20, 21, 36, 37, 58, 91, 92, 105], "like": [2, 7, 10, 11, 18, 27, 28, 36, 37, 71, 78, 90, 91, 92, 94, 99, 100, 101, 105, 106], "pwm": [2, 19, 22, 33, 49, 67, 102], "follow": [2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 17, 18, 19, 21, 22, 23, 24, 25, 26, 28, 30, 32, 34, 35, 36, 37, 38, 39, 40, 42, 45, 49, 54, 56, 58, 61, 63, 65, 66, 67, 68, 69, 70, 72, 73, 74, 75, 76, 78, 79, 80, 81, 82, 83, 88, 89, 90, 91, 92, 96, 97, 99, 100, 101, 103, 104, 105, 106], "tabl": [2, 7, 10, 11, 32, 36, 49, 65, 76, 77, 80, 90, 105], "present": [2, 7, 10, 11, 18, 25, 32, 36, 37, 41, 42, 47, 49, 50, 58, 60, 67, 77, 78, 90, 94, 98, 99, 100, 101, 105], "after": [2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 18, 19, 22, 23, 24, 26, 27, 28, 30, 32, 34, 36, 37, 39, 42, 43, 44, 47, 51, 54, 58, 66, 70, 83, 89, 92, 96, 98, 99, 101, 104, 105, 106], "detail": [2, 7, 10, 15, 16, 18, 25, 36, 37, 76, 78, 90, 92, 98, 99, 100], "cntrl": [2, 4, 5, 6, 7, 8, 9, 11, 12, 20, 34, 54, 99], "ad7768": [2, 5, 6, 7, 8, 9, 11, 12, 33, 34, 41, 54, 82, 87, 99, 102], "ad777x": [2, 4, 6, 7, 8, 9, 11, 12, 33, 34, 54, 99, 102], "ddr_edgesel": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "rise": [2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 17, 19, 20, 21, 23, 30, 34, 35, 36, 37, 39, 54, 58, 99], "edg": [2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 17, 20, 21, 23, 24, 27, 34, 35, 36, 37, 38, 42, 54, 58, 67, 72, 89, 99], "fall": [2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 17, 19, 20, 21, 23, 27, 30, 34, 36, 39, 54, 58, 72, 99], "part": [2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 27, 34, 37, 38, 41, 44, 50, 54, 69, 71, 73, 77, 88, 89, 91, 92, 96, 99, 100, 103, 104, 105, 107], "success": [2, 4, 5, 6, 7, 8, 9, 11, 12, 15, 34, 54, 67, 72, 73, 74, 79, 88, 89, 92, 99], "remain": [2, 4, 5, 6, 7, 8, 9, 11, 12, 15, 34, 36, 37, 39, 42, 43, 54, 56, 69, 83, 96, 99], "how": [2, 4, 5, 6, 7, 8, 9, 11, 12, 18, 26, 28, 34, 36, 37, 49, 54, 55, 56, 61, 63, 66, 68, 69, 70, 71, 72, 73, 74, 76, 77, 79, 83, 90, 92, 93, 95, 97, 98, 99], "delin": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "incom": [2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 20, 30, 34, 36, 46, 54, 99], "post": [2, 4, 5, 6, 7, 8, 9, 11, 12, 15, 34, 54, 99], "pin_mod": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "altern": [2, 4, 5, 6, 8, 9, 11, 12, 18, 34, 54, 72, 76, 92, 99], "interleav": [2, 4, 5, 6, 7, 8, 9, 11, 12, 21, 34, 54, 59, 60, 67, 99], "group": [2, 4, 5, 6, 7, 8, 9, 11, 12, 18, 30, 34, 36, 54, 96, 99, 101], "cntrl_3": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "crc_en": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "custom_control": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "decod": [2, 4, 5, 6, 7, 8, 9, 11, 12, 15, 34, 36, 37, 54, 99], "adaq8092": [2, 4, 5, 6, 7, 8, 9, 11, 33, 34, 54, 99, 102], "random": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "adc_ctrl_statu": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "pn_err": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "pn": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 35, 54, 99, 100], "pn_oo": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "oo": [2, 4, 5, 6, 7, 8, 9, 11, 12, 20, 21, 34, 54, 99], "over_rang": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "delay_cntrl": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "deprec": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "delay_sel": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "transit": [2, 4, 5, 6, 7, 8, 9, 11, 12, 14, 18, 24, 26, 28, 34, 36, 37, 42, 54, 99], "delay_rwn": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "directli": [2, 4, 5, 6, 7, 8, 9, 11, 12, 15, 21, 23, 34, 37, 39, 45, 54, 73, 88, 92, 99], "decrement": [2, 4, 5, 6, 7, 8, 9, 11, 12, 18, 34, 39, 54, 99], "delay_address": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "lower": [2, 4, 5, 6, 7, 8, 9, 11, 12, 14, 23, 28, 34, 36, 37, 47, 49, 54, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 86, 88, 89, 90, 96, 99, 100, 101], "delay_wdata": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "200": [2, 4, 5, 6, 7, 8, 9, 11, 12, 19, 28, 34, 54, 61, 63, 73, 99], "0x19": [2, 4, 5, 6, 7, 8, 9, 11, 12, 15, 20, 21, 34, 54, 99], "0x64": [2, 4, 5, 6, 7, 8, 9, 11, 12, 15, 17, 20, 21, 34, 54, 99], "delay_statu": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "delay_lock": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "fail": [2, 4, 5, 6, 7, 8, 9, 11, 12, 15, 19, 34, 54, 92, 95, 99, 105], "calibr": [2, 4, 5, 6, 7, 8, 9, 11, 12, 28, 34, 54, 67, 73, 99], "element": [2, 4, 5, 6, 7, 8, 9, 11, 12, 30, 32, 34, 54, 99], "delay_rdata": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "adc_sync": [2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "complet": [2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 18, 19, 26, 28, 30, 33, 34, 36, 37, 39, 43, 44, 47, 54, 71, 77, 80, 82, 87, 91, 96, 99, 105], "jesd204": [2, 4, 5, 6, 7, 8, 9, 11, 12, 15, 33, 34, 35, 54, 76, 80, 90, 95, 99, 102], "design": [2, 7, 10, 13, 15, 16, 18, 19, 27, 28, 34, 35, 36, 37, 38, 41, 44, 45, 47, 49, 50, 58, 61, 63, 64, 86, 87, 92, 93, 95, 96, 97, 98, 99, 100, 103, 106], "adc_config_wr": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "adc_config_rd": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "ui_reserv": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "adc_config_ctrl": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "rd": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 37, 54, 99], "wr": [2, 4, 5, 6, 7, 8, 9, 11, 12, 15, 34, 54, 99], "request": [2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 17, 18, 19, 30, 32, 34, 35, 54, 60, 94, 99, 103], "b1": [2, 4, 5, 6, 7, 8, 9, 11, 12, 27, 32, 34, 54, 65, 96, 99], "b0": [2, 4, 5, 6, 7, 8, 9, 11, 12, 27, 32, 34, 37, 46, 54, 96, 99], "captur": [2, 4, 5, 6, 7, 8, 9, 11, 12, 14, 23, 28, 32, 34, 36, 37, 54, 57, 67, 68, 76, 77, 82, 83, 99], "0x29": [2, 4, 5, 6, 7, 8, 9, 11, 12, 15, 22, 34, 54, 99], "0xa4": [2, 4, 5, 6, 7, 8, 9, 11, 12, 15, 22, 34, 54, 99], "adc_start_cod": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "word": [2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 27, 34, 36, 37, 39, 42, 43, 49, 51, 54, 55, 56, 62, 99], "startcod": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "start_code_dis": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "adc_gpio_in": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "adc_gpio_out": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "0x30": [2, 4, 5, 6, 7, 8, 9, 11, 12, 14, 15, 19, 23, 24, 30, 34, 36, 37, 39, 54, 99, 104], "0xc0": [2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 19, 24, 30, 34, 36, 37, 39, 54, 99], "pps_counter": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "counter": [2, 4, 5, 6, 7, 8, 9, 11, 12, 14, 15, 22, 23, 24, 26, 27, 34, 36, 42, 46, 54, 92, 96, 99], "count": [2, 4, 5, 6, 7, 8, 9, 11, 12, 14, 20, 23, 26, 30, 34, 35, 36, 39, 44, 54, 60, 67, 84, 96, 99, 100, 105], "cycl": [2, 4, 5, 6, 7, 8, 9, 11, 12, 14, 15, 16, 18, 19, 21, 24, 26, 27, 28, 29, 32, 34, 36, 37, 42, 44, 49, 54, 58, 60, 62, 67, 90, 99], "two": [2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 17, 18, 24, 25, 27, 28, 31, 32, 34, 36, 37, 38, 42, 47, 49, 54, 59, 60, 62, 65, 66, 67, 70, 83, 84, 90, 91, 92, 95, 96, 99, 100, 101, 103, 105], "0x31": [2, 4, 5, 6, 7, 8, 9, 11, 12, 15, 19, 30, 34, 36, 37, 39, 54, 99], "0xc4": [2, 4, 5, 6, 7, 8, 9, 11, 12, 15, 19, 30, 34, 36, 37, 39, 54, 99], "pps_statu": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "assert": [2, 4, 5, 6, 7, 8, 9, 11, 12, 15, 18, 19, 20, 22, 28, 30, 34, 35, 36, 37, 39, 40, 42, 43, 46, 48, 54, 55, 56, 58, 59, 60, 62, 99, 100], "mayb": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "chan_cntrln": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "adc_lb_owr": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "adc_data_sel": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "adc_pn_sel_owr": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "adc_pn_sel": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "0x9": [2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 15, 23, 34, 54, 99], "adc_pn_type_owr": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "dcfilt_enb": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "format_signext": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "extens": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 41, 54, 75, 92, 96, 99], "alwai": [2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 14, 18, 20, 26, 27, 28, 30, 32, 34, 35, 36, 37, 39, 42, 49, 51, 54, 59, 60, 62, 67, 90, 91, 92, 95, 96, 99, 101, 105], "nearest": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "boundari": [2, 4, 5, 6, 7, 8, 9, 11, 12, 21, 28, 34, 36, 37, 54, 55, 56, 58, 99], "format_typ": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "format_en": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "modifi": [2, 4, 5, 6, 7, 8, 9, 11, 12, 19, 21, 26, 30, 34, 36, 37, 39, 42, 51, 54, 91, 92, 93, 97, 98, 99, 101, 105], "pn23": [2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 54, 99], "A": [2, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 17, 18, 19, 22, 25, 27, 28, 32, 34, 35, 36, 37, 41, 42, 47, 54, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90, 91, 92, 93, 95, 99, 100, 101, 105], "respect": [2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 30, 34, 54, 61, 63, 75, 88, 96, 99, 105], "master": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 55, 56, 67, 99], "though": [2, 4, 5, 6, 7, 8, 9, 11, 12, 13, 15, 32, 34, 54, 92, 99, 106], "individu": [2, 4, 5, 6, 7, 8, 9, 11, 12, 26, 34, 36, 37, 45, 49, 54, 59, 60, 92, 96, 99, 100], "chan_statusn": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "crc_err": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "monitor": [2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 18, 19, 20, 38, 42, 54, 67, 77, 80, 81, 99, 100], "afterward": [2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 34, 54, 91, 99, 101, 105], "status_head": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "header": [2, 4, 5, 6, 7, 8, 9, 11, 12, 30, 32, 34, 36, 37, 54, 83, 96, 99, 101], "sent": [2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 30, 32, 34, 36, 37, 54, 99], "spuriou": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "mismatch": [2, 4, 5, 6, 7, 8, 9, 11, 12, 18, 20, 34, 36, 54, 92, 99], "Of": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "64": [2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 18, 21, 26, 27, 28, 34, 35, 36, 37, 49, 54, 55, 56, 58, 59, 60, 61, 63, 75, 76, 80, 90, 91, 99], "consecut": [2, 4, 5, 6, 7, 8, 9, 11, 12, 18, 19, 20, 27, 34, 36, 37, 54, 67, 99, 103], "expect": [2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 18, 20, 34, 35, 36, 37, 54, 92, 99], "It": [2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 15, 17, 18, 21, 23, 25, 27, 28, 29, 30, 31, 34, 35, 36, 37, 39, 40, 41, 42, 43, 46, 47, 49, 54, 55, 56, 57, 60, 62, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 86, 88, 89, 90, 91, 92, 99, 100, 101, 103, 105, 106], "match": [2, 4, 5, 6, 7, 8, 9, 11, 12, 18, 19, 26, 28, 34, 36, 37, 39, 54, 62, 96, 99, 101], "independ": [2, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 26, 27, 34, 36, 37, 54, 58, 66, 70, 80, 83, 91, 92, 96, 99, 103], "path": [2, 4, 5, 6, 7, 8, 9, 11, 12, 14, 17, 18, 20, 21, 22, 23, 27, 32, 34, 36, 37, 38, 49, 54, 55, 61, 63, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90, 91, 92, 94, 98, 99, 100, 101, 104, 105], "chan_raw_datan": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "adc_read_data": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "dcfilt_offset": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "remov": [2, 4, 5, 6, 7, 8, 9, 11, 12, 30, 34, 39, 54, 69, 70, 76, 82, 90, 92, 94, 99, 105], "known": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 36, 54, 76, 92, 99], "dcfilt_coeff": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "pn9a": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "pn9": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "pn23a": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "0x5": [2, 4, 5, 6, 7, 8, 9, 11, 12, 14, 15, 18, 22, 23, 24, 26, 28, 34, 36, 37, 39, 54, 99], "0x6": [2, 4, 5, 6, 7, 8, 9, 11, 12, 14, 15, 22, 23, 24, 28, 34, 36, 37, 54, 99], "pn31": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "chan_usr_cntrln_1": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "chan_usr_cntrln_2": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "usr_decimation_m": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "usr_decimation_n": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "softspan": [2, 4, 5, 6, 7, 8, 9, 11, 12, 34, 54, 99], "axi_pwm_gen": [2, 24, 49, 66, 67, 68, 70, 72, 73, 74, 79, 83, 84, 88, 89], "reg_vers": [2, 24], "0x00020101": [2, 24], "reg_id": [2, 24], "reg_scratch": [2, 24], "reg_core_mag": [2, 24], "identif": [2, 15, 19, 24, 25, 26, 28, 34, 35], "core_mag": [2, 24], "0x504c5347": [2, 24], "reg_rstn": [2, 24], "load": [2, 14, 18, 19, 22, 23, 24, 76], "load_config": [2, 22, 24], "wo": [2, 3, 24, 30, 39], "new": [2, 9, 11, 14, 17, 18, 19, 24, 26, 27, 28, 30, 32, 33, 36, 37, 39, 40, 42, 43, 51, 87, 91, 92, 93, 95, 99, 100, 102, 105, 106, 107], "written": [2, 10, 14, 15, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 28, 30, 32, 36, 37, 39, 43, 55, 56, 62, 73, 74, 90, 96], "reg_config": [2, 24], "featur": [2, 30, 32, 64, 66, 70, 72, 73, 75, 78, 79, 81, 83, 88, 92, 95, 97, 105], "ext_sync_align": [2, 24], "neg": [2, 24, 65, 67, 69, 88, 96], "otherwis": [2, 7, 15, 18, 22, 24, 28, 30, 36, 37, 43, 44, 92, 98, 99, 100, 105, 106], "toggl": [2, 19, 24, 58], "force_align": [2, 24], "immedi": [2, 24, 26, 36, 37], "stop": [2, 7, 15, 17, 18, 24, 26, 28, 30, 32, 39, 42, 92], "realign": [2, 24], "end": [2, 3, 8, 13, 14, 17, 18, 19, 23, 24, 26, 28, 30, 32, 39, 42, 65, 67, 72, 73, 91, 95, 96, 101, 105], "start_at_sync": [2, 24], "equal": [2, 3, 7, 15, 18, 19, 24, 26, 27, 36, 37, 39, 42, 61, 63, 96], "valew": [2, 24], "overwritten": [2, 24], "time": [2, 4, 5, 6, 7, 10, 14, 18, 19, 22, 23, 25, 26, 27, 28, 32, 36, 37, 40, 41, 42, 43, 44, 46, 55, 56, 58, 63, 66, 67, 70, 83, 90, 91, 92, 95, 98, 104, 105, 106], "reg_nb_puls": [2, 24], "nb_puls": [2, 24], "reg_pulse_x_period": [2, 24], "x": [2, 18, 24, 25, 36, 37, 38, 69, 72, 76, 80, 84, 91, 92, 99, 100], "pulse_x_period": [2, 24], "h4": [2, 24], "ch3": [2, 24], "h4c": [2, 24], "durat": [2, 24, 36, 37, 42], "reg_pulse_x_width": [2, 24], "pulse_x_width": [2, 24], "h8c": [2, 24], "reg_pulse_x_offset": [2, 24], "pulse_x_offset": [2, 24], "hcc": [2, 24], "thu": [2, 7, 10, 18, 28, 39, 42, 44, 88, 91, 96, 106], "abl": [2, 19, 34, 35, 36, 37, 39, 40, 42, 47, 49, 92, 98, 104, 106], "other": [2, 7, 10, 15, 17, 18, 19, 20, 25, 26, 27, 28, 32, 34, 35, 36, 37, 38, 39, 42, 43, 44, 46, 49, 59, 60, 67, 77, 81, 90, 91, 92, 95, 96, 99, 100, 101, 102, 103, 104, 105, 106], "mention": [2, 27, 90, 91, 92, 101], "wai": [2, 6, 18, 27, 28, 36, 37, 38, 44, 49, 77, 90, 92, 96, 105], "As": [2, 7, 10, 15, 28, 36, 37, 42, 92, 107], "regard": [2, 8, 16, 18, 23, 25, 27, 36, 37, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 86, 88, 89, 90, 92, 95, 99, 100], "workflow": 2, "db": [2, 67, 74, 75], "don": [2, 28, 30, 32, 37, 92, 94, 95, 101, 105], "care": [2, 30, 32, 37, 47, 91], "besid": [2, 15, 36, 37, 49, 95, 99, 100], "wr_n": 2, "rd_n": 2, "also": [2, 4, 5, 6, 7, 8, 9, 10, 11, 14, 15, 17, 18, 19, 21, 23, 26, 27, 28, 30, 32, 35, 36, 37, 39, 42, 44, 49, 54, 67, 71, 75, 76, 77, 81, 88, 90, 91, 92, 96, 101, 105, 106], "order": [2, 7, 9, 10, 11, 15, 17, 18, 19, 23, 26, 28, 36, 37, 38, 39, 73, 90, 95, 96, 104, 105], "make": [2, 7, 10, 19, 28, 34, 39, 41, 44, 47, 49, 50, 61, 63, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90, 91, 94, 96, 98, 101, 104, 105, 106], "db0": 2, "db2": 2, "obtain": [2, 10, 19, 20, 21, 25, 49, 91, 92, 96], "page": [2, 7, 33, 49, 65, 76, 80, 84, 87, 90, 91, 93, 94, 95, 98, 99, 100, 105], "datasheet": [2, 10, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90], "illustr": [2, 26, 58, 103], "recommend": [2, 18, 32, 34, 35, 36, 37, 39, 58, 92, 96, 98, 106], "provid": [2, 7, 10, 11, 15, 18, 19, 21, 23, 25, 26, 28, 30, 32, 34, 35, 36, 37, 38, 39, 42, 49, 55, 56, 58, 59, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 86, 88, 89, 90, 91, 93, 97, 98, 99, 100, 105], "document": [2, 7, 9, 10, 15, 22, 25, 33, 36, 37, 58, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 87, 88, 89, 90, 91, 92, 95, 96, 97, 99, 100, 102, 105], "eval": [2, 10, 38, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 81, 82, 83, 84, 88, 89], "fmc": [2, 6, 7, 8, 12, 20, 21, 38, 69, 71, 72, 73, 74, 75, 76, 78, 79, 80, 83, 84, 87, 88, 89, 90, 91, 95], "s_axis_axi_aclks_axi_aresetnrx_db_irx_triggerrx_cs_nrx_db_orx_db_trx_rd_nrx_wr_nadc_validadc_dataadc_syncaxi_ad7616": 3, "axi_ad7616": [3, 74, 95], "axi_ad7616_control": 3, "axi_ad7616_pif": 3, "rx_trigger": 3, "beat": [3, 18, 28, 34, 35, 36, 37, 55, 56], "0x00001002": 3, "0x110": [3, 19, 21, 39], "0x440": [3, 21], "up_cntrl": 3, "cnvst_en": 3, "cnvst": 3, "resetn": [3, 15, 26, 28, 46, 47, 53], "softwar": [3, 9, 14, 16, 22, 26, 27, 28, 30, 32, 39, 59, 60, 64, 86, 89, 91, 92, 96, 99, 100, 106], "0x111": [3, 21], "0x444": [3, 11, 21], "up_conv_r": 3, "s_axis_clk": 3, "0x112": [3, 18, 21], "0x448": [3, 18, 21], "up_burst_length": 3, "burst": [3, 18, 26, 28, 30, 32, 44], "length": [3, 7, 14, 20, 21, 23, 25, 26, 28, 30, 32, 39, 49, 51], "just": [3, 7, 15, 18, 28, 49, 65, 76, 91, 92, 94, 95, 99, 100, 104, 105], "0x113": [3, 18], "0x44c": [3, 18], "up_read_data": 3, "0x114": [3, 18, 19, 39], "0x450": [3, 18], "up_write_data": 3, "s_axis_axi_aclks_axi_aresetnclk_inadc_dovfready_indata_inadc_sshotadc_clkadc_resetadc_dataadc_syncadc_validadc_crc_ch_mismatchadc_enable_": 4, "adc_valid_": [4, 5], "axi_ad7768": [4, 75, 92, 95], "line": [4, 5, 6, 7, 8, 10, 11, 12, 20, 21, 22, 25, 28, 34, 35, 36, 37, 39, 45, 46, 47, 48, 49, 53, 54, 65, 67, 73, 90, 92, 94, 95, 96, 99, 100, 101, 105], "crc": [4, 5, 6, 7, 8, 9, 11, 12, 34, 36, 37, 54, 99], "real": [4, 5, 6, 18, 28, 55, 56], "quartu": [4, 5, 6, 9, 12, 26, 29, 30, 54, 91, 92, 95, 101, 105, 106], "axi_ad7768_if": 4, "axi_ad7768_ip": [4, 92], "axi_ad7768_hw": 4, "num_channel": [4, 34, 35], "domain": [4, 5, 6, 8, 11, 12, 13, 17, 18, 21, 28, 29, 30, 34, 35, 36, 37, 39, 46, 47, 48, 49, 53, 55, 56, 59, 60, 62, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90, 96], "ready_in": [4, 5], "data_in": [4, 5, 57, 62, 96], "adc_sshot": 4, "shot": [4, 22, 28], "adc_crc_ch_mismatch": [4, 5], "deseri": [4, 5], "check": [4, 5, 11, 15, 16, 17, 18, 19, 25, 28, 32, 36, 37, 39, 44, 49, 71, 76, 90, 91, 95, 106], "algorithm": [4, 5, 38, 81], "basic": [4, 5, 6, 8, 12, 31, 32, 54, 65, 92, 95, 96, 98], "oper": [4, 5, 6, 7, 8, 9, 11, 12, 19, 28, 30, 31, 32, 45, 49, 54, 55, 56, 66, 67, 69, 70, 71, 72, 73, 74, 75, 76, 77, 79, 80, 83, 88, 89, 90, 92, 96, 99], "own": [4, 5, 6, 8, 12, 18, 44, 92, 93, 102, 105], "suport": [4, 5], "s_axis_axi_aclks_axi_aresetnclk_inadc_dovfready_insync_adc_misodata_inadc_clkadc_resetsync_adc_mosiadc_validadc_crc_ch_mismatchadc_enable_": 5, "axi_ad777x": [5, 54, 95], "ad7770": 5, "ad7771": 5, "ad7779": 5, "axi_ad777x_if": 5, "axi_ad777x_ip": 5, "axi_ad777x_hw": 5, "sync_adc_mosi": 5, "syncron": [5, 7], "sync_adc_miso": 5, "s_axis_axi_aclks_axi_aresetndelay_clkadc_clk_in_padc_clk_in_nadc_clk_in_padc_data_in_padc_data_in_nadc_or_in_padc_or_in_nadc_dovfadc_clkadc_rstadc_validadc_enableadc_dataaxi_ad9265": 6, "axi_ad9265": 6, "dev": [6, 7, 8, 9, 11, 12, 16, 34, 35], "adc_datapath_dis": [6, 7, 12], "datapath": [6, 7, 12, 36, 37, 65], "taken": [6, 12, 42, 51, 90, 105], "io_delay_group": [6, 7, 8, 11, 12], "adc_if_delay_group": [6, 12], "pass": [6, 8, 10, 12, 14, 20, 21, 36, 37, 59, 60, 75, 81, 92], "ibufgd": [6, 8, 10, 12], "bufg": [6, 7, 8, 10, 12], "reult": [6, 8, 12], "delay_clk": [6, 7, 8, 11, 12, 99, 100], "idelayctrl": [6, 8, 11, 12], "200mhz": [6, 8, 11, 12], "adc_clk_in_p": [6, 8, 12], "adc_clk_in_n": [6, 8, 12], "adc_rst": [6, 11, 12, 13, 34], "adc_data_in_p": [6, 8], "adc_data_in_n": [6, 8], "adc_or_in_p": [6, 8], "adc_or_in_n": [6, 8], "adc_en": [6, 8, 9], "axi_ad9265_if": 6, "rout": [6, 7, 10, 12, 67], "distribut": [6, 12, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90, 91, 92, 96], "drive": [6, 12, 14, 15, 18, 22, 23, 28, 41, 49, 60, 67, 77, 88], "circuitri": [6, 12, 28, 36, 37, 67, 69, 73, 74, 76, 77, 90], "idelaye2": [6, 8, 12], "so": [6, 8, 12, 13, 18, 19, 26, 27, 28, 36, 37, 42, 43, 60, 62, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90, 91, 92, 94, 98, 99, 100, 101, 103, 104, 105, 107], "everi": [6, 7, 12, 15, 18, 23, 26, 27, 32, 34, 35, 36, 37, 44, 58, 60, 90, 91, 92, 99, 100, 101], "along": [6, 12, 88, 99, 100, 106], "latenc": [6, 8, 12, 18, 31, 34, 37, 41, 49, 62, 75, 84], "prb": [6, 7, 8, 9, 10, 11, 35], "analyz": [6, 8, 14, 17, 33, 37, 102], "chan_cntrl_3": [6, 34], "up_delay_cntrl": [6, 8, 12], "dynam": [6, 8, 12, 14, 16, 23, 24, 28, 30, 35, 37, 38, 39, 51, 65, 67, 72, 75, 77, 78, 82, 89, 99, 100], "reconfigur": [6, 8, 12, 15, 16, 19, 25, 34, 35, 36, 65, 99, 100], "help": [6, 12, 36, 37, 38, 49, 73, 91, 98, 101, 105, 107], "compens": [6, 12, 13, 17, 19, 78], "trace": [6, 12], "pcb": [6, 12, 49, 75, 88], "procedur": [6, 8, 9, 30, 32, 36, 37, 91, 92, 105], "develop": [6, 8, 21, 38, 49, 66, 67, 70, 83, 84, 91, 92, 95, 96, 98, 99, 100, 105, 106], "nativ": [6, 8, 12], "card": [6, 8, 12, 67, 71, 73, 88, 91, 105], "125ebz": 6, "s_axis_axi_aclks_axi_aresetnclkdelay_clkrx_clk_in_prx_clk_in_nrx_frame_in_prx_frame_in_nrx_data_in_prx_data_in_nrx_clk_inrx_frame_inrx_data_indac_sync_intdd_syncgps_ppsadc_dovfdac_dunfup_enableup_txnrxup_dac_gpio_inup_adc_gpio_indac_data_i": 7, "dac_data_q": [7, 11], "l_clkrstgps_pps_irqtx_clk_out_ptx_clk_out_ntx_frame_out_ptx_frame_out_ntx_data_out_ptx_data_out_ntx_clk_outtx_frame_outtx_data_outenabletxnrxdac_sync_outtdd_sync_cntradc_r1_modedac_r1_modeup_dac_gpio_outup_adc_gpio_outadc_enable_i": 7, "adc_valid_i": [7, 11], "adc_data_i": [7, 11], "adc_enable_q": [7, 11], "adc_valid_q": [7, 11], "adc_data_q": [7, 11], "dac_enable_i": [7, 11], "dac_valid_i": [7, 11], "dac_enable_q": [7, 11], "dac_valid_q": [7, 11], "cover": [7, 10, 22, 28, 105], "familiar": [7, 10, 44, 95, 98], "better": [7, 10, 27, 36, 44, 82, 92], "understand": [7, 10, 38, 65, 92, 96, 98, 99, 100], "lite": [7, 11, 13, 14, 15, 17, 18, 19, 23, 25, 26, 30, 34, 35, 36, 37, 39, 49, 76, 92, 101], "hardwar": [7, 11, 14, 15, 18, 19, 20, 21, 22, 23, 25, 26, 28, 32, 38, 39, 95, 97], "programm": [7, 11, 13, 16, 17, 19, 22, 38, 41, 42, 46, 66, 67, 68, 69, 70, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90, 91], "loop": [7, 18, 61, 65, 67, 79], "back": [7, 11, 18, 21, 28, 36, 37, 44, 61, 65, 67, 96, 99, 100], "up_dac_common": [7, 10, 11, 100], "up_dac_channel": [7, 10, 11, 100], "architectur": [7, 10, 15, 18, 36, 37, 38, 44, 65, 66, 67, 68, 69, 70, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90, 96, 97, 105], "either": [7, 15, 18, 19, 21, 23, 32, 36, 37, 38, 43, 49, 65, 75, 90, 91, 96, 105, 107], "full": [7, 11, 18, 27, 28, 30, 38, 39, 55, 56, 59, 60, 67, 76, 88, 90, 92], "duplex": [7, 11, 26, 28], "tdd": [7, 33, 76, 90, 102], "section": [7, 13, 17, 18, 19, 27, 34, 35, 36, 37, 44, 67, 75, 76, 77, 78, 80, 90, 91, 92, 95, 96, 99, 100, 104, 105], "avoid": [7, 13, 17, 18, 27, 28, 30, 49, 76, 96, 103], "flavor": 7, "mess": 7, "fact": [7, 19, 28, 67], "quit": [7, 60, 92], "There": [7, 15, 17, 19, 23, 25, 26, 27, 28, 32, 38, 49, 61, 63, 67, 77, 91, 92, 95, 96, 101, 104, 105], "limit": [7, 14, 21, 27, 34, 35, 36, 37, 49, 56, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 77, 78, 79, 80, 81, 82, 83, 84, 86, 88, 89, 91, 92, 96], "left": [7, 32, 36, 101], "constraint": [7, 24, 27, 28, 38, 44, 64, 76, 80, 90, 91, 92, 95], "pzsdr": 7, "some": [7, 13, 17, 24, 27, 28, 30, 32, 36, 37, 44, 45, 49, 59, 60, 73, 74, 76, 78, 88, 89, 90, 91, 92, 95, 96, 97, 98, 100, 101, 105, 107], "board": [7, 15, 21, 25, 28, 41, 49, 58, 92, 95, 97, 107], "layout": [7, 18, 34, 35, 36, 37, 38, 67], "let": [7, 24, 27, 59, 60, 92, 101, 104, 105], "2r2t": 7, "consist": [7, 10, 17, 25, 27, 31, 32, 36, 37, 40, 41, 43, 46, 47, 49, 52, 59, 60, 76, 84, 90, 96, 104], "b11110000": 7, "simpli": [7, 10, 13, 28, 44, 49, 59, 60, 92, 105], "collect": [7, 38, 59, 60, 93], "defram": [7, 34, 35, 36, 76, 80, 90, 99, 100], "tree": [7, 10, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 86, 88, 89, 90, 94], "entir": [7, 10, 92, 96], "global": [7, 10, 15, 92, 96, 105], "skew": [7, 10, 36], "die": [7, 10, 88], "On": [7, 10, 15, 28, 30, 32, 73, 89, 92], "via": [7, 10, 15, 18, 19, 25, 28, 34, 35, 36, 37, 39, 46, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 86, 88, 89, 90], "becaus": [7, 10, 27, 28, 32, 42, 49, 55, 56, 59, 60, 61, 63, 67, 71, 74, 76, 78, 90, 91, 92, 94], "half": 7, "test": [7, 10, 11, 18, 21, 34, 35, 36, 37, 49, 67, 79, 82, 89, 92, 105, 106, 107], "cyclon": [7, 15, 90, 91], "arrow": 7, "kit": [7, 70, 75, 84], "sinc": [7, 14, 18, 23, 25, 30, 32, 36, 37, 42, 49, 56, 75, 90, 92, 101, 104], "thought": [7, 92], "favor": 7, "bank": [7, 36, 37], "alloc": [7, 42, 65, 76, 92], "we": [7, 10, 11, 24, 28, 36, 37, 38, 44, 49, 61, 63, 65, 76, 80, 91, 92, 95, 98, 101, 105, 107], "incap": 7, "bufio": 7, "bufr": [7, 11], "dsp": [7, 27, 69, 72], "main": [7, 10, 17, 19, 22, 23, 27, 28, 31, 36, 37, 41, 58, 61, 63, 67, 70, 92, 95, 96, 98, 99, 100, 105, 106], "purpos": [7, 10, 14, 18, 19, 26, 36, 37, 38, 49, 67, 91, 96, 98, 101], "well": [7, 10, 18, 26, 31, 36, 37, 38, 39, 40, 41, 43, 76, 77, 81, 92, 103], "per": [7, 10, 15, 18, 20, 21, 23, 26, 29, 32, 34, 35, 36, 37, 42, 44, 59, 60, 65, 67, 73, 74, 75, 76, 80, 90, 92, 96, 99, 100, 104], "strictli": 7, "reflect": [7, 10, 26, 28, 34, 35, 36, 37, 55, 56], "interest": [7, 10, 32, 92], "pack": [7, 20, 28, 59, 95], "unpack": [7, 28, 60, 104], "16bit": [7, 20, 21], "64bit": 7, "exclus": 7, "share": [7, 15, 23, 28, 49, 65, 67, 76, 88, 104], "get": [7, 15, 20, 27, 28, 36, 43, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90, 91, 92, 95], "he": [7, 92, 96, 106], "howev": [7, 18, 19, 32, 36, 37, 76, 79, 83, 92], "244mhz": 7, "61mhz": 7, "That": [7, 15, 60, 92, 106], "translat": [7, 29, 45, 46, 60], "safe": [7, 55], "interpret": [7, 30, 32], "behavior": [7, 18, 28, 36, 37, 42, 43, 51, 91, 92, 96], "necessarili": [7, 91, 95, 105], "true": [7, 10, 18, 21, 22, 24, 28, 36, 37, 44, 55, 73, 74, 96], "major": [7, 18, 36, 37, 49, 91, 92], "equival": [7, 18, 34, 35, 65, 76], "decid": [7, 19], "among": [7, 105], "those": [7, 14, 18, 19, 20, 21, 22, 23, 26, 28, 32, 36, 37, 39, 92, 99, 100, 105], "rule": [7, 10, 26, 36, 37, 42, 61, 63, 91, 92, 96, 105], "regardless": [7, 10, 35, 36, 37, 42, 67, 73, 74], "destin": [7, 10, 18, 49, 55, 56], "intend": [7, 18, 21, 28, 35, 41, 50, 96, 98], "less": [7, 10, 14, 18, 19, 21, 23, 27, 32, 36, 37, 39, 62, 66, 67, 70, 83, 92], "portabl": [7, 10, 38, 105], "appear": [7, 10, 15, 49, 91, 92, 104, 105], "12bit": 7, "14bit": 7, "seem": 7, "break": [7, 18], "symmetri": 7, "round": [7, 36, 49], "toward": [7, 18, 21, 30, 35, 36, 37, 39], "msb": [7, 20, 26, 28, 32, 34, 35, 36, 37, 39], "precis": [7, 27, 28, 41, 49, 66, 67, 68, 70, 71, 75, 82, 83, 88], "lost": [7, 18, 58], "gain": [7, 67, 73, 75, 78, 79, 81], "expens": 7, "retain": 7, "natur": 7, "newest": [7, 10], "carri": [7, 10, 18, 32, 37, 40, 45, 52], "were": [7, 10, 14, 18, 19, 20, 21, 22, 23, 26, 28, 30, 36, 37, 39, 67, 73, 74, 76, 88, 89, 90, 92, 101, 105], "s3": [7, 10], "63": [7, 10, 18, 20, 21, 28, 54, 55, 56, 59, 60, 61, 63, 80, 90, 91], "down": [7, 10, 14, 22, 23, 28, 36, 37, 49, 91, 95], "48": [7, 10, 70, 75, 76, 90, 91], "s2": [7, 10], "47": [7, 10, 70, 76, 90, 91], "s1": [7, 10, 44, 73], "s0": [7, 10, 44], "last": [7, 10, 14, 18, 23, 28, 32, 36, 37, 39, 42, 92, 96, 99, 100, 101, 105], "oldest": [7, 10], "2rx2tx": 7, "1rx1tx": 7, "tdd_disabl": 7, "adc_init_delai": 7, "rx": [7, 9, 11, 28, 32, 33, 63, 76, 80, 90, 91, 92, 102, 104], "push": [7, 11, 17, 23, 28, 30], "adc_userports_dis": [7, 11], "adc_dataformat_dis": [7, 11], "adc_dcfilter_dis": [7, 11], "adc_iqcorrection_dis": [7, 11], "dac_init_delai": 7, "dac_clk_edge_sel": 7, "sel": [7, 15, 65], "dac_iodelay_en": 7, "io_delai": 7, "dac_datapath_dis": [7, 10, 11], "tx": [7, 10, 11, 32, 33, 61, 76, 80, 90, 102, 104], "dac_dds_dis": 7, "dac_dds_typ": [7, 10, 11], "dac_dds_phase_dw": 7, "dac_dds_cordic_dw": [7, 10, 11], "dac_dds_cordic_phase_dw": [7, 10, 11], "dac_userports_dis": 7, "dac_iqcorrection_dis": 7, "dev_if_delay_group": [7, 8, 11], "iodelay_ctrl": 7, "iodelai": [7, 11], "ctrl": [7, 46, 65], "mimo_en": 7, "mimo": [7, 80], "use_ssi_clk": 7, "ssi": 7, "delay_refclk_frequ": [7, 8, 11], "refclk": [7, 8, 11, 15, 90], "rx_nodpa": 7, "nodpa": 7, "l_clk": 7, "further": [7, 15, 25, 39], "mhz": [7, 11, 15, 28, 34, 36, 38, 49, 58, 61, 63, 65, 67, 69, 76, 78, 80, 90, 96], "seri": [7, 8, 9, 11, 13, 15, 16, 17, 19, 21, 23, 41, 65, 91, 105], "300": [7, 28], "gps_pps_irq": 7, "rx_clk_in_p": 7, "rx_clk_in_n": 7, "rx_frame_in_p": 7, "rx_frame_in_n": 7, "rx_data_in_p": 7, "rx_data_in_n": 7, "rx_clk_in": 7, "rx_frame_in": 7, "rx_data_in": 7, "tx_clk_out_p": 7, "tx_clk_out_n": 7, "tx_frame_out_p": 7, "tx_frame_out_n": 7, "tx_data_out_p": 7, "tx_data_out_n": 7, "tx_clk_out": 7, "tx_frame_out": 7, "tx_data_out": 7, "ensm": 7, "txnrx": 7, "dac_sync_in": [7, 11, 35], "dac_sync_out": [7, 11], "tdd_sync": 7, "tdd_sync_cntr": 7, "gps_pp": 7, "adc_r1_mod": 7, "dac_dunf": [7, 10, 11, 35, 54, 100], "dac_r1_mod": 7, "up_en": 7, "up_txnrx": 7, "up_dac_gpio_in": 7, "up_dac_gpio_out": 7, "up_adc_gpio_in": 7, "up_adc_gpio_out": 7, "adc_enable_i": [7, 11], "dac_data_i": [7, 11], "etc": [7, 10, 11, 18, 28, 34, 35, 36, 37, 49, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 86, 88, 89, 90, 91, 92, 95, 96, 99, 100, 105, 106], "absolut": [7, 10, 11, 36, 75, 96], "0x1000": [7, 10, 11, 25], "0x2000": 7, "0x8000": [7, 27], "transceiv": [7, 9, 15, 65, 80, 93, 99, 100, 101, 104, 105], "tdd_control_0": 7, "tdd_gated_tx_dmapath": 7, "continu": [7, 10, 14, 17, 18, 19, 26, 27, 28, 30, 36, 37, 39, 66, 67, 68, 70, 82, 83, 92], "adjust": [7, 28, 36, 37, 55, 56, 66, 69, 70, 79, 83, 92, 105], "facilit": [7, 19, 25, 92], "debug": [7, 13, 17, 18, 19, 22, 23, 25, 26, 28, 30, 36, 37, 39, 92, 106], "preserv": [7, 32, 88], "tdd_gated_rx_dmapath": 7, "tdd_txonli": 7, "tx_": [7, 28, 65], "tdd_rxonli": 7, "rx_": [7, 65], "tdd_secondari": 7, "_1": 7, "_2": 7, "tdd_enabl": 7, "alert": 7, "prior": 7, "keep": [7, 14, 17, 18, 19, 27, 36, 90, 95, 101, 106], "tdd_control_1": 7, "tdd_burst_count": 7, "long": [7, 18, 26, 43, 46, 88, 96], "non": [7, 15, 17, 18, 26, 36, 37, 92, 96, 97, 101, 105], "zero": [7, 10, 15, 17, 18, 19, 20, 26, 28, 35, 55], "tdd_control_2": 7, "tdd_counter_init": 7, "tdd_frame_length": 7, "termin": [7, 75, 82, 92], "10m": 7, "245": 7, "76mhz": 7, "0x258000": 7, "tdd_sync_terminal_typ": 7, "tdd_statu": 7, "tdd_rxtx_vco_overlap": 7, "exist": [7, 18, 26, 36, 37, 39, 76, 80, 90, 91, 92, 100, 105, 106], "interv": [7, 14, 19, 23, 24], "vco": [7, 38], "power": [7, 11, 15, 18, 31, 36, 37, 41, 46, 49, 62, 66, 67, 69, 70, 72, 74, 75, 77, 79, 82, 83, 88, 89, 91, 105], "tdd_rxtx_rf_overlap": 7, "tdd_vco_rx_on_1": 7, "reach": [7, 36, 37, 39], "sure": [7, 10, 19, 34, 47, 92, 94, 101, 105, 106], "tdd_vco_rx_off_1": 7, "tdd_vco_tx_on_1": 7, "tdd_vco_tx_off_1": 7, "0x24": [7, 14, 15, 19, 23], "0x90": [7, 19, 34, 35, 36, 37, 99, 100], "tdd_rx_on_1": 7, "0x25": 7, "0x94": 7, "tdd_rx_off_1": 7, "deactiv": [7, 36, 37, 43, 92], "0x26": 7, "0x98": 7, "tdd_tx_on_1": 7, "tx_dp_on": 7, "0x27": 7, "0x9c": 7, "tdd_tx_off_1": 7, "tx_dp_off": 7, "tdd_rx_dp_on_1": 7, "accept": [7, 18, 21, 28, 30, 32, 35, 36, 37, 40, 42, 44, 72], "tdd_rx_dp_off_1": 7, "0x2a": [7, 15, 22], "0xa8": [7, 15, 22], "tdd_tx_dp_on_1": 7, "0x2b": [7, 15, 22], "0xac": [7, 15, 22], "tdd_tx_dp_off_1": 7, "tdd_vco_rx_on_2": 7, "pointer": [7, 30, 62], "vco_rx_on": 7, "tdd_vco_rx_off_2": 7, "vco_rx_off": 7, "0x32": [7, 15, 19, 30, 36, 37], "0xc8": [7, 15, 19, 30, 36, 37], "tdd_vco_tx_on_2": 7, "vco_tx_on": 7, "0x33": [7, 30, 36, 37], "0xcc": [7, 30, 36, 37], "tdd_vco_tx_off_2": 7, "vco_tx_off": 7, "0x34": [7, 14, 23, 30, 32, 39], "0xd0": [7, 30, 39], "tdd_rx_on_2": 7, "rx_on": 7, "0x35": [7, 30, 39], "0xd4": [7, 30, 39], "tdd_rx_off_2": 7, "rx_off": 7, "0x36": [7, 30, 39], "0xd8": [7, 30, 39], "tdd_tx_on_2": 7, "tx_on": 7, "0x37": [7, 30], "0xdc": [7, 30], "tdd_tx_off_2": 7, "tx_off": 7, "0x38": [7, 14, 23, 30, 39], "0xe0": [7, 30, 39], "tdd_rx_dp_on_2": 7, "rx_dp_on": 7, "0x39": [7, 30, 39], "0xe4": [7, 30, 39], "tdd_rx_dp_off_2": 7, "rx_dp_off": 7, "0x3a": [7, 30, 39], "0xe8": [7, 30, 39], "tdd_tx_dp_on_2": 7, "0x3b": [7, 39], "0xec": [7, 39], "tdd_tx_dp_off_2": 7, "fmcomms2": [7, 91, 93, 107], "fmcomms4": 7, "s_axis_axi_aclks_axi_aresetndelay_clkadc_clk_in_padc_clk_in_nadc_data_in_padc_data_in_nadc_or_in_padc_or_in_nadc_dovfadc_clkadc_validadc_enableadc_dataaxi_ad9467": 8, "axi_ad9467": [8, 92], "axi_ad9467_if": [8, 100], "look": [8, 28, 30, 36, 71, 78, 82, 90, 91, 92, 100, 101, 105], "ug472": [8, 16], "ug471": 8, "ug953": [8, 16], "ebz": [8, 38, 76, 87, 90, 92], "s_axis_axi_aclks_axi_aresetnrx_clkrx_sofrx_validrx_dataadc_dovfadc_sync_inadc_raddr_inrx_readyadc_clkadc_validadc_enableadc_dataadc_sync_outadc_raddr_outaxi_ad9671": 9, "octal": 9, "ultrasound": [9, 38], "af": 9, "demodul": [9, 72], "jesd": [9, 34, 35, 36, 37, 76, 90, 92], "altera": [9, 20, 21, 38, 55, 56, 59, 60, 61, 63, 99, 100], "axi_ad9671": 9, "supprt": 9, "quad_or_dual_n": 9, "rx_clk": [9, 58, 99], "40": [9, 19, 34, 35, 36, 37, 49, 65, 67, 72, 74, 75, 76, 79, 80, 82, 89, 90, 91, 100], "rx_sof": [9, 36, 99], "rx_valid": [9, 36, 99], "placehold": [9, 25, 94], "rx_data": [9, 99], "127": [9, 28, 35, 56, 76, 90, 91], "128": [9, 10, 18, 28, 49, 55, 56, 59, 60, 75, 76, 80, 90, 91], "wide": [9, 15, 25, 32, 34, 35, 36, 37, 49, 66, 67, 70, 71, 72, 82, 83, 88, 101], "rx_readi": [9, 99], "tx_clk": [9, 11, 58, 100], "appli": [9, 23, 27, 30, 34, 35, 36, 37, 42, 76, 89, 90, 91, 96, 101, 104], "adc_sync_in": [9, 34], "come": [9, 10, 11, 19, 23, 26, 27, 28, 30, 49, 88, 89, 92], "adc_sync_out": 9, "adc_raddr_in": 9, "send": [9, 10, 18, 21, 27, 28, 30, 32, 36, 37, 39, 47, 48, 49, 66, 70, 83, 88], "locat": [9, 18, 25, 26, 36, 37, 71, 76, 77, 80, 90, 91, 92, 94, 99, 100, 104], "adc_raddr_out": 9, "axi_ad9671_if": 9, "split": [9, 20, 37], "comparison": [9, 14, 27, 49, 92], "jesd204b": [9, 15, 65, 76, 80, 90, 99, 100], "surviv": [9, 38], "s_axis_axi_aclks_axi_aresetndac_clk_in_pdac_clk_in_ndac_dunfdac_ddata_": 10, "dac_clk_out_pdac_clk_out_ndac_data_out_pdac_data_out_ndac_div_clkdac_rstdac_validdac_enable_": 10, "resolut": [10, 18, 20, 21, 22, 34, 35, 36, 37, 49, 66, 70, 78, 82, 83, 89, 99, 100], "500": [10, 13, 17, 34, 36, 38, 41, 49, 76, 77, 78, 88], "msp": [10, 11, 34, 36, 38, 41, 49, 67, 70, 72, 74, 76, 77, 78, 80, 83, 88, 89], "bist": [10, 11], "bufgce_div": 10, "dac_clk_in_p": [10, 54], "divid": [10, 11, 23, 42, 46, 58, 65, 88, 90, 91, 95, 96, 105], "except": [10, 26, 28, 32, 67, 92, 96], "upack": [10, 33, 61, 102], "serd": 10, "chosen": [10, 14, 23, 27, 28, 38], "4096": [10, 18, 32, 55], "differenti": [10, 37, 65, 67, 72, 73, 88, 96, 103], "dac_clk_out_": 10, "dac_clk_in_": 10, "dac_data_out_": 10, "dco": [10, 100], "engin": [10, 28, 30, 33, 45, 50, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 86, 88, 89, 90, 101, 102], "latch": [10, 46, 49, 67, 96], "dss": 10, "figur": [10, 49], "mean": [10, 17, 18, 19, 26, 28, 30, 32, 35, 36, 37, 39, 40, 43, 44, 47, 56, 65, 76, 80, 90, 91, 92, 95, 106], "find": [10, 18, 65, 76, 77, 78, 80, 81, 82, 90, 91, 92, 95, 98, 99, 100, 102, 104, 105], "proper": [10, 30, 37, 39, 71, 92, 106], "smp_dly": 10, "properli": [10, 18, 19, 32, 36, 37, 47, 95, 96], "adder": 10, "synchroniz": 10, "perform": [10, 11, 18, 19, 34, 36, 37, 38, 41, 42, 49, 69, 71, 74, 75, 77, 78, 79, 80, 81, 88, 89, 92, 96, 105], "dac_div_clk": [10, 54], "0x1b": [10, 21], "sum": [10, 21, 27], "To": [10, 13, 14, 15, 17, 18, 19, 23, 24, 30, 32, 34, 35, 36, 37, 39, 44, 49, 61, 63, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90, 92, 94, 95, 98, 99, 100, 103, 105], "maintain": [10, 19, 36, 71, 105, 107], "unchang": 10, "These": [10, 17, 25, 36, 37, 38, 77, 78, 79, 90, 91, 92, 98, 99, 100, 101], "content": [10, 18, 25, 30, 32, 36, 37, 39, 43, 91, 92, 101], "give": [10, 21, 30, 36, 47, 62, 66, 70, 78, 83, 90, 92, 96], "what": [10, 19, 27, 28, 32, 39, 49, 61, 63, 77, 91, 92, 101], "devicetre": 10, "polynomi": [10, 27, 35], "appropri": [10, 28, 45, 77, 99, 100], "dcop": 10, "dac_clk_in_n": [10, 54], "dac_clk_out_p": [10, 54], "dcip": 10, "dac_clk_out_n": [10, 54], "dac_data_out_p": [10, 54], "dac_data_out_n": [10, 54], "compar": [10, 19, 26, 34, 36, 46, 88], "dac_rst": [10, 11, 17, 35, 54], "dac_valid": [10, 23, 27, 35, 54], "dac_enable_": [10, 54], "dac_ddata_": [10, 54], "zcu102": [10, 28, 38, 78, 80, 90, 91, 92, 95, 105], "least": [10, 18, 28, 30, 36, 37, 39, 49, 59, 90, 99, 100], "good": [10, 92], "selectio": 10, "resourc": [10, 11, 26, 27, 36, 37, 65, 91, 92, 95, 97, 98, 99, 100, 105], "s_axis_axi_aclks_axi_aresetntrx_clktx_clkdelay_clktrx_iqtrx_datadac_sync_inadc_dovfdac_data_idma_valid_idac_data_qdma_valid_qdac_dunfadc_clkadc_rstdac_clkdac_rsttx_iqtx_datadac_sync_outadc_enable_iadc_valid_iadc_data_iadc_enable_qadc_valid_qadc_data_qdac_enable_idac_valid_idac_enable_qdac_valid_qaxi_ad9963": 11, "100msp": 11, "170msp": 11, "dll": 11, "amd": [11, 16, 19, 24, 33, 38, 55, 56, 59, 60, 61, 63, 76, 80, 87, 90, 97, 98, 106], "axi_ad9963": 11, "adc_iodelay_en": 11, "tune": [11, 28], "trx": 11, "iodelay_en": 11, "userport": 11, "corect": 11, "adc_scalecorrection_onli": 11, "trx_clk": 11, "deriv": [11, 19, 42, 49, 96, 97], "trx_iq": 11, "trx_data": 11, "tx_iq": 11, "tx_data": [11, 100], "dma_valid_i": 11, "dma_valid_q": 11, "100": [11, 13, 15, 17, 19, 28, 36, 49, 58, 65, 70, 76, 105], "doubl": [11, 21, 55, 56, 67, 92, 101], "75msp": 11, "150mhz": 11, "spur": 11, "outsid": [11, 62, 92], "bandwidth": [11, 17, 21, 28, 34, 36, 38, 59, 60, 66, 70, 72, 75, 76, 79, 82, 83, 90], "75mhz": 11, "reduc": [11, 13, 26, 28, 34, 35, 36, 37, 38, 39, 42, 56, 58, 61, 63, 67, 72, 75, 88, 89, 96], "util": [11, 14, 15, 17, 26, 33, 38, 41, 50, 69, 84, 88], "unus": [11, 32, 96], "previou": [11, 19, 27, 36], "step": [11, 36, 37, 38, 49, 76, 92, 95, 105], "0x51": [11, 19], "correctli": [11, 28, 36, 37, 92], "0x63": 11, "1024": [11, 18, 28, 55, 75], "signatur": 11, "side": [11, 15, 18, 28, 44, 55, 56, 91, 96, 101], "s_axis_axi_aclks_axi_aresetndelay_clkadc_clk_in_padc_clk_in_nlvds_adc_data_in1_plvds_adc_data_in1_nlvds_adc_data_in2_plvds_adc_data_in2_nlvds_adc_or_in_plvds_adc_or_in_ncmos_adc_data_in1cmos_adc_data_in2adc_dovfcmos_adc_or_in_": 12, "adc_clkadc_rstadc_validadc_data_channel1adc_data_channel2adc_enable_": 12, "axi_adaq8092": 12, "axi_adaq8092_apb_decod": 12, "axi_adaq8092_channel": 12, "axi_adaq8092_if": 12, "axi_adaq8092_rand_decod": 12, "axi_adaq8092_ip": 12, "output_mod": [12, 23], "polarity_mask": 12, "h0fffffff": 12, "lvds_adc_data_in1_p": 12, "lvds_adc_data_in1_n": 12, "lvds_adc_data_in2_p": 12, "lvds_adc_data_in2_n": 12, "lvds_adc_or_in_p": 12, "lvds_adc_or_in_n": 12, "cmos_adc_data_in1": 12, "cmos_adc_data_in2": 12, "adc_data_channel1": 12, "adc_data_channel2": 12, "cmos_adc_or_in_": 12, "channel1": 12, "channel2": 12, "s_axis_axi_aclks_axi_aresetnadc_clkadc_rstadc_data_aadc_data_badc_valid_aadc_valid_badc_dec_data_aadc_dec_data_badc_dec_valid_aadc_dec_valid_badc_data_rateadc_oversampling_enaxi_adc_decim": 13, "1000": [13, 17, 19, 49], "10000": [13, 17, 19], "100000": [13, 14, 17, 19], "arbitrari": [13, 17, 18, 19, 26, 36, 37], "drop": [13, 30, 39], "here": [13, 14, 17, 23, 36, 37, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90, 91, 92, 93, 94, 95, 99, 100, 101, 102, 104, 105, 107], "axi_adc_decim": 13, "anyth": [13, 38], "higher": [13, 14, 19, 36, 37, 47, 49, 71, 73, 74, 88], "cic": [13, 17, 19], "fir": [13, 17, 19, 93], "peripher": [13, 14, 16, 17, 19, 20, 21, 22, 23, 25, 26, 28, 29, 30, 31, 32, 38, 39, 46, 47, 48, 53, 54, 55, 56, 57, 59, 60, 61, 62, 63, 66, 70, 76, 83, 88, 90, 92, 99, 100, 101, 105], "correction_dis": [13, 17], "adc_data_a": 13, "adc_data_b": 13, "b": [13, 14, 17, 28, 49, 69, 72, 73, 75, 84, 89], "adc_valid_a": 13, "adc_valid_b": 13, "adc_dec_data_a": 13, "adc_dec_data_b": 13, "adc_dec_valid_a": 13, "adc_dec_valid_b": 13, "adc_data_r": 13, "adc_oversampling_en": 13, "oversampl": [13, 72, 73, 74], "lead": [13, 17, 18, 42, 56, 72, 75, 89, 96], "lot": [13, 92, 95, 105], "50": [13, 17, 19, 58, 69, 75, 76, 80, 82, 90, 91], "5000": [13, 15, 16, 17, 19], "50000": [13, 17], "At": [13, 17, 19, 36, 58, 90, 92, 98, 101, 105], "semant": [13, 17, 18, 19, 22, 23, 25, 26, 28, 30, 36, 37, 39, 101], "version_major": [13, 17, 18, 19, 22, 23, 25, 26, 28, 30, 36, 37, 39, 101], "0x0001": [13, 19, 22, 25, 28, 36, 37, 39], "version_minor": [13, 17, 18, 19, 22, 23, 25, 26, 28, 30, 36, 37, 39, 101], "version_patch": [13, 17, 18, 19, 22, 23, 25, 26, 28, 30, 36, 37, 39, 101], "decimation_ratio": 13, "decimation_stage_en": 13, "filtered_decimation_ratio": 13, "05": [13, 18], "26": [13, 28, 90, 91], "correction_enable_b": [13, 17], "multipli": [13, 17, 27, 36, 37], "correction_coefficient_b": [13, 17], "correction_enable_a": [13, 17], "correction_coefficient_a": [13, 17], "correction_coeffici": [13, 17], "amplif": [13, 17], "s_axis_axi_aclks_axi_aresetnclkresettrigger_intrigger_idata_adata_bdata_valid_adata_valid_btrigger_otrigger_tdata_a_trigdata_b_trigdata_valid_a_trigdata_valid_b_trigtrigger_outtrigger_out_lafifo_depthaxi_adc_trigg": 14, "mix": [14, 23, 32, 96], "instrument": [14, 38, 67, 79, 81, 88], "axi_adc_trigg": 14, "limit_a": 14, "0x0014": 14, "threshold": [14, 18, 19, 36], "function": [14, 17, 18, 22, 23, 24, 28, 36, 37, 38, 44, 46, 49, 55, 67, 69, 75, 77, 80, 81, 91, 92, 96, 99, 100, 103, 104, 107], "trigger_function_a": 14, "0x0018": 14, "hysteresi": [14, 19], "0x001c": 14, "0x0024": 14, "0x0028": 14, "0x002c": 14, "ti": [14, 17, 23, 73, 99], "config_trigger_i": 14, "0x004": [14, 18, 36, 37], "m2k": 14, "eas": [14, 32, 67, 77, 88, 95, 99, 100], "daisi": [14, 69, 79], "io_select": [14, 23], "0x000c": 14, "mux": [14, 45], "trigger_mux_a": 14, "0x0020": 14, "combin": [14, 15, 23, 28, 30, 36, 37, 38, 39, 47, 75, 91, 96, 105], "trigger_mux_b": 14, "0x0030": 14, "trigger_out_control": 14, "0x0034": 14, "holdoff": 14, "trigger_holdoff": [14, 23], "0x0048": 14, "silent": 14, "trigger_delai": [14, 23], "0x0040": 14, "trigger_out_hold_pin": 14, "0x004c": 14, "sign_bit": 14, "out_pin_hold_n": 14, "trigger_in": [14, 23], "trigger_i": [14, 17, 23], "trigger_o": 14, "trigger_t": 14, "data_a": 14, "data_b": 14, "data_valid_a": 14, "data_valid_b": 14, "data_a_trig": 14, "embed": [14, 20, 21, 28, 36, 57, 75, 76, 91], "data_b_trig": 14, "data_valid_a_trig": 14, "data_valid_b_trig": 14, "trigger_out": [14, 23, 57], "adc_trigg": 14, "plu": [14, 18, 27, 44], "variabl": [14, 23, 25, 57, 62, 73, 74, 91, 92, 95, 96, 101, 105, 106], "histori": [14, 23], "trigger_out_la": 14, "fifo_depth": [14, 23], "depth": [14, 23, 32, 55, 62], "extract": [14, 33, 36, 102], "reconstruct": [14, 36], "forward": [14, 28, 62, 67, 99, 100], "addit": [14, 18, 20, 21, 28, 30, 32, 35, 37, 39, 42, 44, 55, 56, 67, 70, 73, 81, 92, 94, 95], "pipelin": [14, 30, 36, 37, 41, 81], "introduc": [14, 34, 42, 49, 55, 56], "var": [14, 33, 102], "trigger_offset": 14, "0x00030000": 14, "trigger_o_1": 14, "trigger_o_0": 14, "trriger_o_1": 14, "0x0004": [14, 18], "trigger_i_1": 14, "trigger_i_0": 14, "trriger_o_0": 14, "io_selection_1": 14, "io_selection_0": 14, "fall_edg": [14, 17, 23], "rise_edg": [14, 17, 23], "any_edg": [14, 17, 23], "high_level": [14, 17, 23], "low_level": [14, 17, 23], "function_a": 14, "passthrough": 14, "hysteresis_a": 14, "OR": [14, 15, 23, 30, 39, 57, 96], "AND": [14, 23, 67], "xor": [14, 23], "negat": 14, "limit_b": 14, "0xa": [14, 23], "function_b": 14, "trigger_function_b": 14, "0xb": [14, 23], "0x2c": [14, 15, 22, 23], "hysteresis_b": 14, "0xd": [14, 23], "embedded_trigg": 14, "futur": [14, 18, 25, 42, 92, 101], "feed": 14, "util_extract": [14, 57], "trigger_mux_out": [14, 23], "la": 14, "0xe": [14, 23], "bypass": [14, 15, 20, 21, 23, 28, 37, 62, 67, 69, 73], "0xf": [14, 23], "0x3c": [14, 23, 39], "condit": [14, 18, 23, 25, 30, 36, 37, 38, 41, 44, 67, 76, 79, 90, 99, 100], "met": [14, 23, 36, 37, 49, 92], "off": [14, 23, 75, 88, 92], "next": [14, 18, 22, 23, 26, 30, 32, 36, 37, 38, 43, 44, 49, 67, 90, 92, 96, 101], "until": [14, 15, 17, 18, 23, 27, 28, 30, 35, 36, 37, 39, 42, 43, 44, 47, 55, 56, 58, 67, 69], "inact": 14, "s_axis_axi_aclks_axi_aresetnm_axiup_pll_rstup_cm_": 15, "up_es_": [15, 65], "up_ch_": 15, "up_statusaxi_adxcvr": 15, "configur": [15, 23, 27, 38, 43, 44, 49, 64, 66, 69, 70, 77, 79, 81, 83, 91, 92, 99, 100, 101, 104, 105], "highspe": [15, 38], "separ": [15, 20, 21, 36, 41, 49, 72, 76, 88, 90, 92, 94, 95, 96, 105], "due": [15, 36, 37, 44, 49, 65, 76, 80, 83, 90, 92], "small": [15, 28, 46, 61, 63, 80], "util_adxcvr": [15, 36, 37, 38, 64, 76, 80, 90, 104], "axi4": [15, 18, 34, 35, 36, 37, 39, 49, 55, 92, 101], "broadcast": [15, 30, 32], "statist": [15, 36, 38], "ey": [15, 21], "scan": [15, 96], "phy": [15, 37, 45, 58, 76, 80, 90], "adi_jesd204": 15, "link_manag": 15, "xcvr": [15, 90], "itself": [15, 28, 32, 36, 37, 92, 101], "stack": [15, 26, 32, 38], "num_of_lan": [15, 104], "xcvr_type": [15, 65], "gtpe2_not_support": [15, 65], "gtxe2": [15, 38, 65], "gthe2_not_support": [15, 65], "gtze2_not_support": [15, 65], "gthe3": [15, 38, 65], "gtye3_not_support": [15, 65], "gtre4_not_support": [15, 65], "gthe4": [15, 38, 65], "gtye4": [15, 38, 65], "gtme4_not_support": [15, 65], "link_mod": [15, 36, 37, 65], "64b66b": [15, 34, 36, 37, 65, 76, 80, 90], "8b10b": [15, 36, 37, 65, 76, 80, 90], "stratix": 15, "fpga_voltag": [15, 16], "mv": [15, 16], "wich": 15, "suppli": [15, 25, 38, 67, 69, 72, 73, 74, 75, 79, 88, 89, 91], "tx_or_rx_n": [15, 65, 104], "qpll_enabl": [15, 65, 104], "qpll": [15, 65], "lpm_or_dfe_n": 15, "lpm": [15, 65], "Or": [15, 106], "dfe": [15, 65], "b000": [15, 18], "tx_diffctrl": 15, "diffctrl": 15, "b01000": 15, "tx_postcursor": 15, "postcursor": 15, "b00000": 15, "tx_precursor": 15, "precursor": 15, "sys_clk_sel": 15, "sy": [15, 25], "b11": [15, 96], "out_clk_sel": 15, "b100": [15, 36], "subordin": [15, 17, 30, 39, 40, 46, 47, 48, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90, 101, 103], "m_axi": [15, 18, 55, 56], "m_axi_awaddr": 15, "m_axi_awprot": 15, "m_axi_awvalid": 15, "m_axi_awreadi": 15, "m_axi_wdata": 15, "m_axi_wstrb": 15, "m_axi_wvalid": 15, "m_axi_wreadi": 15, "m_axi_bresp": 15, "m_axi_bvalid": 15, "m_axi_breadi": 15, "m_axi_araddr": 15, "m_axi_arprot": 15, "m_axi_arvalid": 15, "m_axi_arreadi": 15, "m_axi_rdata": 15, "m_axi_rresp": 15, "m_axi_rvalid": 15, "m_axi_rreadi": 15, "up_pll_rst": [15, 104], "up_cm_": [15, 65], "pll_lock": 15, "fpll": 15, "up_statu": 15, "axi_xcvr": 15, "gp": 15, "w": [15, 18, 38, 42, 51, 96], "held": [15, 24], "report": [15, 34, 36], "status_32": 15, "up_pll_lock": 15, "channel_n_readi": 15, "generic_info": 15, "0x140": [15, 16, 19, 30], "atx": 15, "stabl": [15, 18, 20, 36, 37, 43, 79, 92, 95], "automat": [15, 18, 23, 25, 28, 30, 36, 37, 39, 56, 67, 92, 105, 106], "ident": 15, "basi": [15, 42, 47, 75, 81], "them": [15, 18, 19, 26, 36, 37, 47, 49, 88, 90, 91, 92, 96, 101, 104, 105, 106, 107], "chose": [15, 49], "0x0008": 15, "swing": [15, 89], "transmitt": [15, 21, 34, 35, 36, 37, 38, 80, 81, 91], "cursor": 15, "pre": [15, 28, 31, 32, 37, 41, 46, 67], "emphasi": 15, "rxoutclk": 15, "txoutclk": 15, "bufstatus_rst": 15, "bufstatu": 15, "els": [15, 38, 92, 96], "bufststatu": 15, "buftatu": 15, "consult": [15, 18, 88], "search": [15, 65, 92, 99, 100, 101, 104], "rxbufstatu": 15, "txbufstatu": 15, "pll_lock_n": 15, "cpll": [15, 65, 76, 80], "did": [15, 32, 36, 37], "lpm_dfe_n": 15, "sysclk_sel": 15, "sysclksel": 15, "gth": [15, 65, 91, 101], "gty": [15, 65, 91, 101], "pllclksel": 15, "indirectli": 15, "outclk_sel": 15, "01": [15, 25, 30, 36, 37, 58, 66, 70, 83], "aka": [15, 36, 37], "204b": [15, 34, 35, 36, 37], "204c": [15, 34, 35, 36, 37], "cm_sel": 15, "0xff": [15, 42], "cm_control": 15, "cm_wr": 15, "cm_addr": 15, "cm_wdata": 15, "cm_statu": 15, "cm_busi": 15, "idl": [15, 18, 26, 30, 42, 44], "cm_rdata": 15, "ch_sel": 15, "ch_control": 15, "ch_wr": 15, "ch_addr": 15, "ch_wdata": 15, "ch_statu": 15, "ch_busi": 15, "ch_rdata": 15, "es_sel": 15, "es_req": 15, "auto": [15, 22, 28, 91, 96, 105], "es_control_1": 15, "es_prescal": 15, "es_control_2": 15, "es_voffset_rang": 15, "es_voffset_step": 15, "es_voffset_max": 15, "es_voffset_min": 15, "es_control_3": 15, "es_hoffset_max": 15, "es_hoffset_min": 15, "0xb0": [15, 22, 30], "es_control_4": 15, "es_hoffset_step": 15, "0x2d": [15, 22], "0xb4": [15, 22], "es_control_5": 15, "es_startaddr": 15, "es_statu": 15, "es_reset": 15, "es_resetn": [15, 101], "eyescanreset": [15, 101], "0x180": [15, 30], "prbs_cntrl": 15, "prbsforceerr": 15, "checker": [15, 34], "prbscntreset": 15, "prbssel": 15, "put": [15, 18, 28, 36, 90, 92], "normal": [15, 30, 35, 36, 37, 38, 59, 60, 92, 96], "dataflow": 15, "inject": 15, "instead": [15, 18, 23, 32, 36, 37, 45, 62, 67, 92, 96], "0x61": [15, 19, 22, 25, 26, 28, 36, 37], "0x184": 15, "prbs_statu": 15, "prbserr": 15, "sticki": 15, "prbslock": 15, "free": [15, 18, 22, 30, 39, 44, 66, 92, 96, 101, 104], "xclk": 15, "deassert": [15, 34, 35, 36, 43], "necessari": [15, 22, 28, 39, 65, 66, 67, 68, 70, 77, 83, 91, 92, 96, 99, 100, 105], "addr": [15, 36, 37, 44], "soon": [15, 28, 36, 37, 95], "reason": [15, 18, 26, 36, 37, 67, 92, 96, 105], "finish": [15, 17, 18, 19, 32, 44], "immun": 15, "abort": [15, 18], "00": [15, 22, 25, 26, 28, 30, 39, 42, 58, 101], "qpll1": [15, 76], "qpll0": [15, 76, 80], "001": [15, 36], "010": [15, 36], "011": 15, "101": [15, 21, 70, 76], "outclkpc": 15, "outclkpma": 15, "progdivclk": 15, "expos": [15, 18, 49, 65], "gigabit": [15, 38, 58, 65, 99, 100], "without": [15, 17, 18, 19, 21, 28, 30, 32, 37, 38, 39, 43, 47, 57, 59, 60, 67, 82, 88, 96, 105, 106], "bringup": [15, 28], "under": [15, 26, 36, 37, 38, 49, 91, 92, 96, 101, 104], "exact": [15, 44], "record": [15, 18, 36, 37], "detect": [15, 19, 20, 23, 36, 58, 73, 81], "stai": [15, 18, 19, 35, 36, 37, 41, 43, 47], "alon": [15, 92], "suffici": [15, 32], "s_axis_axi_aclks_axi_aresetnclkclk2clk_": 16, "axi_clkgen": [16, 21, 49, 66, 67, 68, 69, 70, 72, 73, 74, 75, 77, 79, 82, 83, 84, 88, 89, 92], "wrapper": [16, 65, 92, 99, 100, 105], "ad_mmcm_drp": 16, "clksel_en": 16, "clksel": 16, "en": [16, 18, 34, 59, 65, 90, 91, 96], "clkin_period": 16, "clkin1": [16, 49], "clkin2_period": 16, "clkin2": 16, "vco_div": [16, 49], "divclk_divid": 16, "vco_mul": [16, 49], "clkfbout_mult_f": 16, "49": [16, 70, 75, 76, 90, 91], "clk0_div": [16, 49], "clkout0_divide_f": 16, "clk0_phase": 16, "clkout0_phas": 16, "clk1_div": 16, "clkout1_divid": 16, "clk1_phase": 16, "clkout1_phas": 16, "enable_clkin2": 16, "fals": [16, 18, 30, 39, 46, 48, 55, 96], "enable_clkout1": 16, "clk2": 16, "clk_": 16, "clk_sel": 16, "betwen": 16, "mmcm_statu": 16, "mmcm_lock": 16, "s_axis_axi_aclks_axi_aresetndac_clkdac_rstdac_data_adac_data_bdac_valid_adac_valid_bdma_valid_adma_valid_bdac_enable_adac_enable_btrigger_itrigger_adctrigger_ladma_ready_adma_ready_bdac_int_data_adac_int_data_bdac_valid_out_adac_valid_out_bunderflowaxi_dac_interpol": 17, "axi_dac_interpol": 17, "dac_data_a": 17, "dac_data_b": 17, "dac_valid_a": 17, "dac_valid_b": 17, "dma_valid_a": 17, "dma_valid_b": 17, "dma_ready_a": 17, "dma_ready_b": 17, "dac_enable_a": 17, "dac_enable_b": 17, "dac_int_data_a": 17, "dac_int_data_b": 17, "dac_valid_out_a": 17, "dac_valid_out_b": 17, "trigger_adc": [17, 23], "trigger_la": 17, "too": [17, 22, 37, 61, 63, 90, 104, 106], "bad": 17, "usb": [17, 91], "stage": [17, 25, 26, 27, 36, 37, 55, 56], "flow": [17, 22, 30, 34, 35, 36, 37, 39, 59, 92, 98, 105, 106], "middl": [17, 32], "man": 17, "ad9963": [17, 33, 102], "consum": [17, 27, 30, 31, 36, 37, 60], "trigger_config": 17, "raw_channel_data": 17, "fetch": [17, 18, 92], "desir": [17, 19, 20, 21, 27, 32, 77, 92, 96, 98, 104, 105], "paus": [17, 18, 42], "remap": 17, "dma_transfer_suspend": 17, "few": [17, 18, 21, 36, 37, 49, 92, 95, 96, 99, 100, 105], "residu": 17, "pipe": 17, "flush": 17, "By": [17, 18, 19, 22, 24, 26, 35, 36, 37, 41, 42, 61, 63, 73, 74, 81, 82, 88, 89, 92, 101], "want": [17, 19, 28, 39, 91, 92, 95, 99, 100, 101, 104, 105, 106], "stop_sync": 17, "cyclic": [17, 21, 31, 32, 49, 76], "0x0002": [17, 23, 26], "arbitrary_interpolation_ratio_a": 17, "filtered_interpol": 17, "interpolation_ratio_a": 17, "531": 17, "168": [17, 32], "783": 17, "360": [17, 27], "038": 17, "arbitrary_interpolation_ratio_b": 17, "interpolation_ratio_b": 17, "suspend_transf": 17, "en_trigger_la": [17, 23], "en_trigger_adc": [17, 23], "en_trigger_to": [17, 23], "en_trigger_ti": [17, 23], "s_axis_axi_aclks_axi_aresetnfifo_rd_clkfifo_wr_clkm_axis_aclkm_dest_axi_aclkm_sg_axi_aclkm_src_axi_aclks_axis_aclkm_dest_axi_aresetnm_sg_axi_aresetnm_src_axi_aresetns_axisfifo_wrfifo_rdm_dest_axim_sg_axim_src_axim_axisirqs_axis_xfer_reqm_axis_xfer_reqfifo_rd_xfer_reqdest_diag_level_burstsaxi_dmac": 18, "throughput": [18, 28, 44, 72, 73, 74, 88, 91], "axi3": 18, "switch": [18, 22, 23, 36, 37, 39, 69, 73, 74, 82, 91, 92, 95, 105], "lut": [18, 27, 28], "tbd": [18, 67], "axi_dmac": [18, 21, 49, 54, 66, 67, 68, 69, 70, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90], "dma_data_width_src": [18, 49], "256": [18, 28, 36, 37, 39, 47, 48, 49, 53, 54, 55, 75], "512": [18, 25, 28, 55, 75], "2048": [18, 55], "dma_data_width_dest": [18, 21, 49], "dma_data_width_sg": 18, "dma_length_width": 18, "dma_2d_transf": [18, 21, 49], "dma_sg_transf": 18, "async_clk_req_src": 18, "whether": [18, 19, 36, 37, 42, 46], "asynchron": [18, 24, 28, 30, 36, 37, 39, 44, 48, 55, 56], "async_clk_src_dest": 18, "async_clk_dest_req": 18, "async_clk_req_sg": 18, "async_clk_src_sg": 18, "async_clk_dest_sg": 18, "axi_slice_dest": [18, 49], "insert": [18, 26, 30, 36, 37, 39, 42, 65, 69, 73, 82, 89, 90, 94, 96], "extra": [18, 28, 92], "slice": [18, 26], "axi_slice_src": [18, 49], "sync_transfer_start": [18, 49], "dma_axi_protocol_dest": 18, "protocol": [18, 36, 37, 38, 40, 58], "dma_axi_protocol_src": 18, "dma_axi_protocol_sg": 18, "dma_type_dest": [18, 21, 49], "mm": [18, 28, 49, 75, 79], "dma_type_src": [18, 21, 49], "dma_axi_addr_width": 18, "max_bytes_per_burst": 18, "largest": [18, 42], "unlimit": 18, "upper": [18, 27, 96, 101], "fifo_s": 18, "axi_id_width_src": 18, "src": [18, 91, 92, 105], "axi_id_width_dest": 18, "dest": 18, "axi_id_width_sg": 18, "sg": 18, "dma_axis_id_w": 18, "dma_axis_dest_w": 18, "disable_debug_regist": 18, "enable_diagnostics_if": 18, "insight": 18, "allow_asym_mem": 18, "asym": 18, "mem": [18, 44], "cache_coher": 18, "axi_axcach": 18, "arcach": 18, "awcach": 18, "b0011": 18, "axi_axprot": 18, "irq": [18, 19, 22, 30, 35, 36, 37, 39, 104], "m_dest_axi": [18, 49], "m_dest_axi_awid": 18, "awid": 18, "m_dest_axi_awaddr": 18, "m_dest_axi_awlen": 18, "awlen": 18, "m_dest_axi_aws": 18, "awsiz": 18, "m_dest_axi_awburst": 18, "awburst": 18, "m_dest_axi_awlock": 18, "awlock": 18, "m_dest_axi_awcach": 18, "m_dest_axi_awprot": 18, "m_dest_axi_awvalid": 18, "m_dest_axi_awreadi": 18, "m_dest_axi_wid": 18, "wid": 18, "m_dest_axi_wdata": 18, "m_dest_axi_wstrb": 18, "m_dest_axi_wlast": 18, "wlast": 18, "m_dest_axi_wvalid": 18, "m_dest_axi_wreadi": 18, "m_dest_axi_bid": 18, "bid": [18, 36, 37], "m_dest_axi_bresp": 18, "m_dest_axi_bvalid": 18, "m_dest_axi_breadi": 18, "m_dest_axi_arid": 18, "arid": 18, "m_dest_axi_araddr": 18, "m_dest_axi_arlen": 18, "arlen": 18, "m_dest_axi_ars": 18, "arsiz": 18, "m_dest_axi_arburst": 18, "arburst": 18, "m_dest_axi_arlock": 18, "arlock": 18, "m_dest_axi_arcach": 18, "m_dest_axi_arprot": 18, "m_dest_axi_arvalid": 18, "m_dest_axi_arreadi": 18, "m_dest_axi_rid": 18, "rid": [18, 28], "m_dest_axi_rdata": 18, "m_dest_axi_rresp": 18, "m_dest_axi_rlast": 18, "rlast": 18, "m_dest_axi_rvalid": 18, "m_dest_axi_rreadi": 18, "m_sg_axi": 18, "m_sg_axi_awid": 18, "m_sg_axi_awaddr": 18, "m_sg_axi_awlen": 18, "m_sg_axi_aws": 18, "m_sg_axi_awburst": 18, "m_sg_axi_awlock": 18, "m_sg_axi_awcach": 18, "m_sg_axi_awprot": 18, "m_sg_axi_awvalid": 18, "m_sg_axi_awreadi": 18, "m_sg_axi_wid": 18, "m_sg_axi_wdata": 18, "m_sg_axi_wstrb": 18, "m_sg_axi_wlast": 18, "m_sg_axi_wvalid": 18, "m_sg_axi_wreadi": 18, "m_sg_axi_bid": 18, "m_sg_axi_bresp": 18, "m_sg_axi_bvalid": 18, "m_sg_axi_breadi": 18, "m_sg_axi_arid": 18, "m_sg_axi_araddr": 18, "m_sg_axi_arlen": 18, "m_sg_axi_ars": 18, "m_sg_axi_arburst": 18, "m_sg_axi_arlock": 18, "m_sg_axi_arcach": 18, "m_sg_axi_arprot": 18, "m_sg_axi_arvalid": 18, "m_sg_axi_arreadi": 18, "m_sg_axi_rid": 18, "m_sg_axi_rdata": 18, "m_sg_axi_rresp": 18, "m_sg_axi_rlast": 18, "m_sg_axi_rvalid": 18, "m_sg_axi_rreadi": 18, "m_src_axi": 18, "m_src_axi_awid": 18, "m_src_axi_awaddr": 18, "m_src_axi_awlen": 18, "m_src_axi_aws": 18, "m_src_axi_awburst": 18, "m_src_axi_awlock": 18, "m_src_axi_awcach": 18, "m_src_axi_awprot": 18, "m_src_axi_awvalid": 18, "m_src_axi_awreadi": 18, "m_src_axi_wid": 18, "m_src_axi_wdata": 18, "m_src_axi_wstrb": 18, "m_src_axi_wlast": 18, "m_src_axi_wvalid": 18, "m_src_axi_wreadi": 18, "m_src_axi_bid": 18, "m_src_axi_bresp": 18, "m_src_axi_bvalid": 18, "m_src_axi_breadi": 18, "m_src_axi_arid": 18, "m_src_axi_araddr": 18, "m_src_axi_arlen": 18, "m_src_axi_ars": 18, "m_src_axi_arburst": 18, "m_src_axi_arlock": 18, "m_src_axi_arcach": 18, "m_src_axi_arprot": 18, "m_src_axi_arvalid": 18, "m_src_axi_arreadi": 18, "m_src_axi_rid": 18, "m_src_axi_rdata": 18, "m_src_axi_rresp": 18, "m_src_axi_rlast": 18, "m_src_axi_rvalid": 18, "m_src_axi_rreadi": 18, "fifo_rd_clk": 18, "fifo_rd": 18, "fifo_wr_clk": 18, "fifo_wr": 18, "m_axis_aclk": [18, 28, 55, 56], "m_dest_axi_aclk": 18, "m_sg_axi_aclk": 18, "m_src_axi_aclk": 18, "s_axis_aclk": [18, 28, 49, 55, 56], "m_dest_axi_aresetn": 18, "m_sg_axi_aresetn": 18, "m_src_axi_aresetn": 18, "s_axis_readi": [18, 28, 55, 56, 60], "treadi": [18, 21, 28, 30, 34, 35, 36, 37, 48, 55, 56, 60], "s_axis_valid": [18, 28, 55, 56, 60], "tvalid": [18, 21, 28, 30, 34, 35, 36, 37, 48, 55, 56, 60], "s_axis_data": [18, 28, 55, 56, 60], "tdata": [18, 21, 28, 30, 34, 35, 37, 48, 55, 56, 60], "s_axis_strb": 18, "tstrb": 18, "s_axis_keep": 18, "tkeep": [18, 28, 55, 56], "s_axis_us": 18, "tuser": 18, "s_axis_id": 18, "tid": 18, "s_axis_dest": 18, "tdest": 18, "s_axis_last": [18, 28], "tlast": [18, 21, 28, 55, 56], "m_axis_readi": [18, 28, 55, 56], "m_axis_valid": [18, 28, 55, 56], "m_axis_data": [18, 28, 55, 56], "m_axis_strb": 18, "m_axis_keep": 18, "m_axis_us": 18, "m_axis_id": 18, "m_axis_dest": 18, "m_axis_last": [18, 28], "fifo_wr_en": [18, 59], "fifo_wr_din": 18, "fifo_wr_overflow": [18, 59], "fifo_wr_sync": 18, "fifo_wr_xfer_req": 18, "xfer_req": 18, "fifo_rd_en": [18, 60], "fifo_rd_dout": 18, "fifo_rd_valid": [18, 60], "fifo_rd_underflow": [18, 60], "s_axis_xfer_req": 18, "m_axis_xfer_req": 18, "fifo_rd_xfer_req": 18, "dest_diag_level_burst": 18, "62": [18, 80, 90, 91], "0x62": 18, "peripheral_id": [18, 19, 25, 26, 28, 36, 37, 39, 101], "0x444d4143": 18, "d": [18, 25, 26, 28, 32, 65, 92], "interface_description_1": 18, "bytes_per_beat_dest_log2": 18, "log2": [18, 28, 36, 37, 39], "dma_": 18, "data_": [18, 39], "width_": 18, "type_": 18, "memorymap": 18, "bytes_per_beat_src_log2": 18, "bytes_per_burst_width": 18, "bytes_": 18, "per_": 18, "burst_": [18, 26], "cross": [18, 21, 28, 36, 49, 55, 56], "4kb": [18, 28], "interface_description_2": 18, "cache_": 18, "axi_": [18, 99, 100], "axcach": 18, "axprot": 18, "irq_mask": [18, 19, 30, 39], "transfer_complet": 18, "transfer_queu": 18, "irq_pend": [18, 19, 22, 30, 36, 37, 39], "queu": 18, "queue": 18, "irq_sourc": [18, 19, 22, 30, 36, 37, 39], "togeth": [18, 19, 22, 25, 41, 50, 84, 90, 104], "hwdesc": 18, "resum": 18, "again": [18, 92, 105], "transfer_id": 18, "transfer_don": 18, "transfer_submit": 18, "re": [18, 28, 36, 37, 41, 42, 43, 47, 48, 49, 67, 72, 90, 92, 94, 105, 107], "occurr": [18, 36, 37], "partial_reporting_en": 18, "partial": [18, 25, 28], "caus": [18, 27, 96], "eventu": 18, "dest_address": 18, "src_address": 18, "x_length": 18, "max": [18, 20, 21, 26, 27, 28, 36, 37, 45, 46, 49, 61, 63], "y_length": 18, "row": 18, "dest_strid": 18, "src_stride": 18, "transfer_0_don": 18, "transfer_1_don": 18, "transfer_2_don": 18, "transfer_3_don": 18, "partial_transfer_don": 18, "partial_transfer_length": 18, "partial_transfer_id": 18, "active_transfer_id": 18, "usag": [18, 36, 59, 60, 92, 96], "0x10d": 18, "0x434": 18, "current_dest_address": 18, "0x10e": 18, "0x438": 18, "current_src_address": 18, "transfer_progress": 18, "partial_length": 18, "moment": [18, 36, 37, 55, 56], "smaller": [18, 25, 28, 36, 37, 38, 56], "0x115": 18, "0x454": 18, "descriptor_id": 18, "segment": 18, "0x11f": 18, "0x47c": 18, "sg_address": 18, "0x124": 18, "0x490": 18, "dest_address_high": 18, "bigger": [18, 56], "0x125": 18, "0x494": 18, "src_address_high": 18, "0x126": 18, "0x498": 18, "current_dest_address_high": 18, "0x127": 18, "0x49c": 18, "current_src_address_high": 18, "0x12f": 18, "0x4bc": 18, "sg_address_high": 18, "intent": [18, 28, 44, 96], "still": [18, 36, 43, 49, 71, 79, 88, 92, 106, 107], "risk": 18, "similarli": [18, 39, 45], "empti": [18, 30, 32, 39, 55, 56, 105], "determin": [18, 19, 27, 28, 34, 35, 36, 37], "buffer_width_in_byt": 18, "buffer_depth": 18, "startup": [18, 26, 28, 36, 37], "de": [18, 21, 28, 30, 36, 37, 38, 39, 58], "pressur": [18, 28, 37, 70], "submit": 18, "go": [18, 26, 28, 36, 37, 71, 76, 77, 80, 90, 91, 92, 98, 104], "enough": [18, 91, 92, 101, 105], "space": [18, 20, 21, 25, 36, 37, 55, 56, 76, 91, 96, 105], "unexpectedli": [18, 92], "shorter": [18, 32], "alreadi": [18, 28, 36, 37, 39, 44, 105], "hand": [18, 92], "queri": [18, 34, 36, 37, 39], "discoveri": [18, 36, 37], "apart": [18, 36, 37], "incompat": [18, 36, 37], "minor": [18, 36, 37, 99, 100], "patch": [18, 36, 37], "letter": [18, 36, 37, 96], "incorrect": [18, 36, 96], "primari": [18, 28, 36, 37], "distinguish": [18, 36, 37], "0x008": [18, 36, 37], "yield": [18, 30, 32, 36, 37], "previous": [18, 36, 37, 43], "associ": [18, 26, 30, 36, 37, 44, 79, 88], "0x00c": [18, 36, 37], "ensur": [18, 19, 21, 30, 32, 34, 35, 36, 37, 49, 65, 69], "three": [18, 32, 37, 38, 39, 45, 55, 56, 59, 60, 65, 67, 70, 75, 81, 99, 100, 105], "close": [18, 36, 37, 38, 49, 92, 96], "particular": [18, 28, 32, 36, 37, 38, 49, 95, 96], "0x088": [18, 36, 37], "0x080": [18, 36, 37], "propag": [18, 30, 36, 37, 39], "prevent": [18, 36, 37, 105], "0x084": [18, 36, 37], "upstream": [18, 30, 36, 37, 39], "acknowledg": [18, 30, 32, 36, 37, 39, 103], "0x3ff": 18, "1079": 18, "1080": [18, 20, 21], "room": [18, 55, 56], "becom": [18, 36, 42, 44, 55, 56, 75], "specifi": [18, 19, 23, 25, 34, 35, 42, 56, 72, 75, 79, 89, 90, 91, 92, 95, 96, 103, 105, 106], "act": [18, 25, 28, 42], "ahead": 18, "intervent": [18, 36], "gracefulli": 18, "shut": 18, "transact": [18, 29, 30, 32, 39, 42, 44, 46, 47, 48], "won": [18, 32, 37, 92], "fulfil": 18, "notif": [18, 36, 37, 39], "certain": [18, 28, 36, 37, 44, 49, 92, 96, 106], "cpu": [18, 39], "poll": 18, "handler": 18, "compos": [18, 58, 84, 96], "pad": [18, 20, 25, 28, 35, 59, 60, 91, 105], "skip": [18, 37], "second": [18, 19, 22, 25, 32, 36, 37, 47, 67, 73, 92, 106], "stride": 18, "_src": 18, "_address": 18, "_stride": 18, "_dest": 18, "restart": [18, 36], "manag": [18, 19, 28, 40, 41, 43, 44, 47, 52, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 88, 89, 90, 99, 100, 103], "overhead": [18, 28, 59, 60], "never": [18, 32, 36, 37], "execut": [18, 30, 31, 32, 39, 41, 42, 43, 45, 47, 48, 49, 67, 92, 104], "noncontigu": 18, "area": [18, 88, 92], "list": [18, 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"auto_sequence_en": 22, "predefin": [22, 55, 56], "tia_manual_config": 22, "sequencer_offset": 22, "tia_chsel_offset": 22, "sequence_auto_config": 22, "sequence_value0": 22, "sequence_value1": 22, "sequence_value2": 22, "third": [22, 97, 98], "sequence_value3": 22, "fourth": 22, "tia0_chsel_manu": 22, "tia0": 22, "manual": [22, 36, 92, 106], "tia1_chsel_manu": 22, "tia2_chsel_manu": 22, "tia3_chsel_manu": 22, "s_axis_axi_aclks_axi_aresetnclkdata_itrigger_idac_datadac_validexternal_rateexternal_validexternal_decimation_entrigger_inclk_outdata_odata_tadc_validadc_datadac_readtrigger_outtrigger_out_adcfifo_depthaxi_logic_analyz": 23, "open": [23, 92, 94, 95, 96, 101, 104, 105, 106], "drain": 23, "axi_logic_analyz": 23, "submodul": 23, "clk_out": 23, "data_i": 23, "data_o": 23, "data_t": 23, "dac_data": 23, "dac_read": 23, "external_r": 23, "external_valid": 23, "external_decimation_en": 23, "acquisit": [23, 67, 70, 72, 74, 79, 82, 88, 89], "trigger_out_adc": 23, "thing": [23, 92, 96, 105, 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"Peripheral Identification and HDL Synthesis Settings": [[36, "peripheral-identification-and-hdl-synthesis-settings"], [37, "peripheral-identification-and-hdl-synthesis-settings"]], "Link Control": [[36, "link-control"], [37, "link-control"]], "Multi-link Control": [[36, "multi-link-control"], [37, "multi-link-control"]], "Link Configuration": [[36, "link-configuration"], [37, "link-configuration"]], "SYSREF Handling": [[36, "sysref-handling"], [37, "sysref-handling"]], "Link Status": [[36, "link-status"], [37, "link-status"]], "Lane Status": [[36, "lane-status"]], "8B/10B Link Lane Status Fields": [[36, "b-10b-link-lane-status-fields"]], "64B/66B Link Lane Status Fields": [[36, "b-66b-link-lane-status-fields"]], "8B/10B Link ILAS Configuration Data": [[36, "b-10b-link-ilas-configuration-data"]], "8B/10B Link": [[36, "b-10b-link"], [37, "b-10b-link"]], "8B/10B Link State Machine": [[36, "b-10b-link-state-machine"], [37, "b-10b-link-state-machine"]], "RESET phase": [[36, "reset-phase"], [36, "axi-jesd204-rx-reset-phase-1"]], "WAIT FOR PHY phase": [[36, "wait-for-phy-phase"]], "CGS phase": [[36, "cgs-phase"]], "DATA phase": [[36, "data-phase"], [36, "axi-jesd204-rx-data-phase-1"]], "8B/10B Multi-endpoint RX link establishment": [[36, "b-10b-multi-endpoint-rx-link-establishment"]], "64B/66B Link": [[36, "b-66b-link"], [37, "b-66b-link"]], "64B/66B Link State Machine": [[36, "b-66b-link-state-machine"]], "WAIT BS phase": [[36, "wait-bs-phase"]], "BLOCK SYNC phase": [[36, "block-sync-phase"]], "64B/66B Link Extended MultiBlock Alignment State Machine": [[36, "b-66b-link-extended-multiblock-alignment-state-machine"]], "EMB INIT State": [[36, "emb-init-state"]], "EMB HUNT State": [[36, "emb-hunt-state"]], "EMB LOCK State": [[36, "emb-lock-state"]], "Dual clock operation": [[36, "dual-clock-operation"], [37, "dual-clock-operation"]], "64b/66b Link latency reduction": [[36, "b-66b-link-latency-reduction"]], "Additional Information": [[36, "additional-information"], [38, "additional-information"]], "JESD204B/C Link Transmit Peripheral": [[37, "jesd204b-c-link-transmit-peripheral"]], "AXI JESD204 TX Synthesis Configuration Parameters": [[37, "axi-jesd204-tx-synthesis-configuration-parameters"]], "JESD204 TX Synthesis Configuration Parameters": [[37, "jesd204-tx-synthesis-configuration-parameters"]], "AXI JESD204 TX Signal and Interface Pins": [[37, "axi-jesd204-tx-signal-and-interface-pins"]], "JESD204 TX Signal and Interface Pins": [[37, "jesd204-tx-signal-and-interface-pins"]], "JESD204B Control Signals": [[37, "jesd204b-control-signals"]], "Transceiver Interface (TX_PHYn)": [[37, "transceiver-interface-tx-phyn"]], "User Data Interface (TX_DATA)": [[37, "user-data-interface-tx-data"]], "ILAS Configuration Data": [[37, "ilas-configuration-data"]], "Manual Synchronization Request": [[37, "manual-synchronization-request"]], "Wait Phase (WAIT)": [[37, "wait-phase-wait"]], "Code Group Synchronization Phase (CGS)": [[37, "code-group-synchronization-phase-cgs"]], "Initial Lane Alignment Sequence Phase (ILAS)": [[37, "initial-lane-alignment-sequence-phase-ilas"]], "User Data Phase (DATA)": [[37, "user-data-phase-data"]], "8B/10B Multi-endpoint TX link establishment": [[37, "b-10b-multi-endpoint-tx-link-establishment"]], "Diagnostics": [[37, "diagnostics"]], "JESD204 Interface Framework": [[38, "jesd204-interface-framework"]], "How to Obtain a License": [[38, "how-to-obtain-a-license"]], "FPGA HDL Support": [[38, "fpga-hdl-support"]], "Physical Layer": [[38, "physical-layer"]], "Link Layer": [[38, "link-layer"]], "Transport Layer": [[38, "transport-layer"]], "Linux": [[38, "linux"]], "No-OS": [[38, "no-os"]], "Tutorial": [[38, "tutorial"]], "Example Projects": [[38, "example-projects"]], "Technical Articles": [[38, "technical-articles"]], "JESD204B Rapid Prototyping Platforms": [[38, "jesd204b-rapid-prototyping-platforms"]], "JESD204B Clocking Solutions": [[38, "jesd204b-clocking-solutions"]], "AXI SPI Engine Module": [[39, "axi-spi-engine-module"]], "FIFOs": [[39, "fifos"]], "Synchronization Events": [[39, "synchronization-events"]], "SYNC_EVENT Interrupt": [[39, "sync-event-interrupt"]], "SPI Engine Control Interface": [[40, "spi-engine-control-interface"]], "Signal Pins": [[40, "signal-pins"], [43, "signal-pins"], [45, "signal-pins"], [52, "signal-pins"]], "SPI Engine": [[41, "spi-engine"], [104, "spi-engine"]], "Related IP Cores": [[41, "related-ip-cores"], [50, "related-ip-cores"]], "Examples": [[41, "examples"], [50, "examples"], [91, "examples"]], "Additional Resources": [[41, "additional-resources"], [50, "additional-resources"]], "SPI Engine Instruction Set Specification": [[42, "spi-engine-instruction-set-specification"]], "Instructions": [[42, "instructions"], [51, "instructions"]], "Transfer Instruction": [[42, "transfer-instruction"], [51, "transfer-instruction"]], "Chip-Select Instruction": [[42, "chip-select-instruction"]], "Configuration Write Instruction": [[42, "configuration-write-instruction"]], "Synchronize Instruction": [[42, "synchronize-instruction"]], "Sleep Instruction": [[42, "sleep-instruction"]], "CS Invert Mask Instruction": [[42, "cs-invert-mask-instruction"]], "SPI Configuration Register": [[42, "spi-configuration-register"]], "Prescaler Configuration Register": [[42, "prescaler-configuration-register"]], "Dynamic Transfer Length Register": [[42, "dynamic-transfer-length-register"]], "SPI Engine Offload Control Interface": [[43, "spi-engine-offload-control-interface"]], "SPI Engine Pipeline Delays": [[44, "spi-engine-pipeline-delays"]], "Instruction Execution": [[44, "instruction-execution"]], "Detailed Delays": [[44, "detailed-delays"]], "Offload Module": [[44, "offload-module"]], "Interconnect Module": [[44, "interconnect-module"]], "Execution Module": [[44, "execution-module"]], "AXI Module": [[44, "axi-module"]], "SPI Bus Interface": [[45, "spi-bus-interface"]], "IO configuration": [[45, "io-configuration"]], "Example Verilog IO configuration": [[45, "example-verilog-io-configuration"]], "SPI Engine Execution Module": [[46, "spi-engine-execution-module"]], "SPI Engine Interconnect Module": [[47, "spi-engine-interconnect-module"]], "SPI Engine Offload Module": [[48, "spi-engine-offload-module"]], "SPI Engine Tutorial - PulSAR-ADC": [[49, "spi-engine-tutorial-pulsar-adc"]], "Evaluating the target device": [[49, "evaluating-the-target-device"]], "SPI Engine hierarchy instantiation": [[49, "spi-engine-hierarchy-instantiation"]], "SPI Engine reference clock": [[49, "spi-engine-reference-clock"]], "AD7984 Timing diagram": [[49, "ad7984-timing-diagram"]], "Sample rate control": [[49, "sample-rate-control"]], "DMA setup": [[49, "dma-setup"]], "System Top": [[49, "system-top"]], "System Constraints": [[49, "system-constraints"]], "Testbench": [[49, "testbench"]], "Evaluating the result": [[49, "evaluating-the-result"]], "Software section": [[49, "software-section"]], "Framework Template": [[50, "framework-template"]], "Template Instruction Set Specification": [[51, "template-instruction-set-specification"]], "Other Instruction": [[51, "other-instruction"]], "Yet Another Instruction": [[51, "yet-another-instruction"]], "Template Register": [[51, "template-register"]], "Template Interface": [[52, "template-interface"]], "Template Module": [[53, "template-module"]], "IP Template": [[54, "ip-template"]], "AXI Stream FIFO": [[55, "axi-stream-fifo"]], "Asymmetric AXI Stream FIFO": [[56, "asymmetric-axi-stream-fifo"]], "Status Signal Delays": [[56, "status-signal-delays"]], "FIFO Depth Calculation": [[56, "fifo-depth-calculation"]], "Util Extract": [[57, "util-extract"]], "Util MII to RMII": [[58, "util-mii-to-rmii"]], "Receive Transactions": [[58, "receive-transactions"]], "Transmit Transactions": [[58, "transmit-transactions"]], "Channel CPACK Utility": [[59, "channel-cpack-utility"]], "Channel UPACK Utility": [[60, "channel-upack-utility"]], "Util RFIFO": [[61, "util-rfifo"]], "Timing Diagram": [[61, "timing-diagram"]], "Util VAR FIFO": [[62, "util-var-fifo"]], "Util WFIFO": [[63, "util-wfifo"]], "AMD Xilinx Specific IPs": [[64, "amd-xilinx-specific-ips"]], "UTIL_ADXCVR core for AMD Xilinx devices": [[65, "util-adxcvr-core-for-amd-xilinx-devices"]], "Microprocessor clock and reset": [[65, "microprocessor-clock-and-reset"]], "PLL reference clock": [[65, "pll-reference-clock"]], "RX interface": [[65, "rx-interface"]], "TX interface": [[65, "tx-interface"]], "Common DRP Interface": [[65, "common-drp-interface"]], "Channel DRP Interface": [[65, "channel-drp-interface"]], "Eye Scan DRP Interface": [[65, "eye-scan-drp-interface"]], "Physical constraints considerations": [[65, "physical-constraints-considerations"]], "AD4134-FMC HDL project": [[66, "ad4134-fmc-hdl-project"]], "Overview": [[66, "overview"], [67, "overview"], [68, "overview"], [69, "overview"], [70, "overview"], [71, "overview"], [72, "overview"], [73, "overview"], [74, "overview"], [75, "overview"], [76, "overview"], [77, "overview"], [78, "overview"], [79, "overview"], [81, "overview"], [82, "overview"], [83, "overview"], [84, "overview"], [88, "overview"], [89, "overview"], [90, "overview"]], "Supported boards": [[66, "supported-boards"], [67, "supported-boards"], [68, "supported-boards"], [69, "supported-boards"], [70, "supported-boards"], [71, "supported-boards"], [72, "supported-boards"], [73, "supported-boards"], [74, "supported-boards"], [75, "supported-boards"], [76, "supported-boards"], [77, "supported-boards"], [78, "supported-boards"], [79, "supported-boards"], [80, "supported-boards"], [81, "supported-boards"], [82, "supported-boards"], [83, "supported-boards"], [84, "supported-boards"], [88, "supported-boards"], [89, "supported-boards"], [90, "supported-boards"]], "Supported devices": [[66, "supported-devices"], [67, "supported-devices"], [68, "supported-devices"], [69, "supported-devices"], [70, "supported-devices"], [71, "supported-devices"], [72, "supported-devices"], [73, "supported-devices"], [74, "supported-devices"], [75, "supported-devices"], [76, "supported-devices"], [77, "supported-devices"], [78, "supported-devices"], [79, "supported-devices"], [81, "supported-devices"], [82, "supported-devices"], [83, "supported-devices"], [84, "supported-devices"], [88, "supported-devices"], [89, "supported-devices"], [90, "supported-devices"]], "Supported carriers": [[66, "supported-carriers"], [67, "supported-carriers"], [68, "supported-carriers"], [69, "supported-carriers"], [70, "supported-carriers"], [71, "supported-carriers"], [72, "supported-carriers"], [73, "supported-carriers"], [74, "supported-carriers"], [75, "supported-carriers"], [76, "supported-carriers"], [77, "supported-carriers"], [78, "supported-carriers"], [79, "supported-carriers"], [80, "supported-carriers"], [81, "supported-carriers"], [82, "supported-carriers"], [83, "supported-carriers"], [84, "supported-carriers"], [88, "supported-carriers"], [89, "supported-carriers"], [90, "supported-carriers"]], "Block design": [[66, "block-design"], [67, "block-design"], [68, "block-design"], [69, "block-design"], [70, "block-design"], [71, "block-design"], [72, "block-design"], [73, "block-design"], [74, "block-design"], [75, "block-design"], [76, "block-design"], [77, "block-design"], [78, "block-design"], [79, "block-design"], [80, "block-design"], [81, "block-design"], [82, "block-design"], [83, "block-design"], [84, "block-design"], [88, "block-design"], [89, "block-design"], [90, "block-design"]], "Block diagram": [[66, "block-diagram"], [67, "block-diagram"], [68, "block-diagram"], [69, "block-diagram"], [70, "block-diagram"], [71, "block-diagram"], [72, "block-diagram"], [73, "block-diagram"], [74, "block-diagram"], [75, "block-diagram"], [76, "block-diagram"], [77, "block-diagram"], [78, "block-diagram"], [79, "block-diagram"], [80, "block-diagram"], [81, "block-diagram"], [82, "block-diagram"], [83, "block-diagram"], [84, "block-diagram"], [88, "block-diagram"], [89, "block-diagram"], [90, "block-diagram"]], "Jumper setup": [[66, "jumper-setup"], [69, "jumper-setup"], [70, "jumper-setup"], [72, "jumper-setup"], [73, "jumper-setup"], [74, "jumper-setup"], [75, "jumper-setup"], [82, "jumper-setup"], [83, "jumper-setup"]], "CPU/Memory interconnects addresses": [[66, "cpu-memory-interconnects-addresses"], [67, "cpu-memory-interconnects-addresses"], [68, "cpu-memory-interconnects-addresses"], [69, "cpu-memory-interconnects-addresses"], [70, "cpu-memory-interconnects-addresses"], [72, "cpu-memory-interconnects-addresses"], [73, "cpu-memory-interconnects-addresses"], [74, "cpu-memory-interconnects-addresses"], [75, "cpu-memory-interconnects-addresses"], [76, "cpu-memory-interconnects-addresses"], [77, "cpu-memory-interconnects-addresses"], [78, "cpu-memory-interconnects-addresses"], [79, "cpu-memory-interconnects-addresses"], [80, "cpu-memory-interconnects-addresses"], [81, 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[88, "support"], [89, "support"], [90, "support"]], "AD4630-FMC HDL project": [[67, "ad4630-fmc-hdl-project"]], "SPI mode - transfer zone 1": [[67, "spi-mode-transfer-zone-1"]], "SPI mode - transfer zone 2": [[67, "spi-mode-transfer-zone-2"]], "Echo clock mode - transfer zone 2": [[67, "echo-clock-mode-transfer-zone-2"]], "Configuration modes": [[67, "configuration-modes"], [73, "configuration-modes"], [74, "configuration-modes"], [76, "configuration-modes"], [80, "configuration-modes"], [88, "configuration-modes"], [89, "configuration-modes"], [90, "configuration-modes"]], "Legend": [[67, null], [67, null], [67, null], [70, null], [73, null], [73, null], [73, null], [73, null], [74, null], [74, null], [74, null], [74, null], [82, null], [82, null], [83, null], [83, null], [88, null], [88, null], [89, null]], "I2C connections": [[67, "i2c-connections"], [68, "i2c-connections"], [69, "i2c-connections"], [72, "i2c-connections"], [73, "i2c-connections"], [74, "i2c-connections"], [75, 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interface": [[73, "ad7606x-fmcz-serial-interface"]], "AD7606x_FMCZ parallel interface": [[73, "ad7606x-fmcz-parallel-interface"]], "Connections and hardware changes": [[73, "connections-and-hardware-changes"], [74, "connections-and-hardware-changes"]], "AD7616-SDZ HDL project": [[74, "ad7616-sdz-hdl-project"]], "Other required hardware": [[74, "other-required-hardware"], [88, "other-required-hardware"]], "AD7616_SDZ serial interface": [[74, "ad7616-sdz-serial-interface"]], "AD7616_SDZ parallel interface": [[74, "ad7616-sdz-parallel-interface"]], "AD7768-EVB HDL project": [[75, "ad7768-evb-hdl-project"]], "AD7768-EVB": [[75, "ad7768-evb"]], "AD9081/AD9082/AD9986/AD9988 HDL project": [[76, "ad9081-ad9082-ad9986-ad9988-hdl-project"]], "Example block design for Single link; M=8; L=4": [[76, "example-block-design-for-single-link-m-8-l-4"], [80, "example-block-design-for-single-link-m-8-l-4"]], "Example block design for Single link; M=4; L=8": [[76, "example-block-design-for-single-link-m-4-l-8"]], "Example block design for Single link; M=2; L=8; JESD204C": [[76, "example-block-design-for-single-link-m-2-l-8-jesd204c"]], "Clock scheme": [[76, "clock-scheme"], [77, "clock-scheme"], [78, "clock-scheme"], [80, "clock-scheme"], [90, "clock-scheme"]], "ZCU102": [[76, "zcu102"]], "VCU118": [[76, "vcu118"]], "ADC - crossbar config": [[76, "adc-crossbar-config"]], "DAC - crossbar config": [[76, "dac-crossbar-config"]], "AD9434-FMC HDL project": [[77, "ad9434-fmc-hdl-project"]], "AD9783-EBZ HDL project": [[78, "ad9783-ebz-hdl-project"]], "ADAQ7980-SDZ HDL project": [[79, "adaq7980-sdz-hdl-project"]], "ADRV9026 HDL reference design": [[80, "adrv9026-hdl-reference-design"]], "Other considerations": [[80, "other-considerations"]], "ADC - lane mapping": [[80, "adc-lane-mapping"]], "DAC - lane mapping": [[80, "dac-lane-mapping"]], "CN0363 HDL project": [[81, "cn0363-hdl-project"]], "CN0540 HDL project": [[82, "cn0540-hdl-project"]], "CN0561 HDL project": [[83, "cn0561-hdl-project"]], "CN0585 HDL project": [[84, "cn0585-hdl-project"]], "Projects": [[87, "projects"]], "PULSAR-ADC HDL project": [[88, "pulsar-adc-hdl-project"]], "PulSAR_ADC_PMDZ": [[88, "pulsar-adc-pmdz"]], "PulSAR_ADC_FMC": [[88, "pulsar-adc-fmc"]], "PULSAR-LVDS HDL project": [[89, "pulsar-lvds-hdl-project"]], "Jumper setup AD7625/AD7626": [[89, "jumper-setup-ad7625-ad7626"]], "Jumper setup AD7960/AD7961": [[89, "jumper-setup-ad7960-ad7961"]], "Project template": [[90, "project-template"]], "ADC - crossbar config *** THIS IS JUST AN EXAMPLE ***": [[90, "adc-crossbar-config-this-is-just-an-example"]], "DAC - crossbar config *** THIS IS JUST AN EXAMPLE ***": [[90, "dac-crossbar-config-this-is-just-an-example"]], "HDL Architecture": [[91, "hdl-architecture"]], "How they\u2019re instantiated": [[91, "how-they-re-instantiated"]], "Example": [[91, "example"]], "Typical project diagram": [[91, "typical-project-diagram"]], "Base Design": [[91, "base-design"]], "Microprocessor": [[91, "microprocessor"]], "Memory Interface Controller": [[91, "memory-interface-controller"]], "Peripheral interfaces": [[91, "peripheral-interfaces"]], "SPI": [[91, "spi"]], "I2C/I2S/SPDIF": [[91, "i2c-i2s-spdif"]], "HDMI": [[91, "hdmi"]], "Connectivity": [[91, "connectivity"]], "Interrupts table": [[91, "interrupts-table"]], "Board design and capabilities": [[91, "board-design-and-capabilities"]], "AMD platforms": [[91, "amd-platforms"]], "Intel platforms": [[91, "intel-platforms"]], "VADJ values": [[91, "vadj-values"]], "File structure of a project": [[91, "file-structure-of-a-project"]], "Project files for AMD boards": [[91, "project-files-for-amd-boards"], [105, "project-files-for-amd-boards"]], "Project files for Intel boards": [[91, "project-files-for-intel-boards"], [105, "project-files-for-intel-boards"]], "Project files for Lattice boards": [[91, "project-files-for-lattice-boards"], [105, "project-files-for-lattice-boards"]], "Build a HDL project": [[92, "build-a-hdl-project"]], "Setup and check your environment": [[92, "setup-and-check-your-environment"]], "Setup the HDL repository": [[92, "setup-the-hdl-repository"]], "Building the projects": [[92, "building-the-projects"]], "Building an Intel project": [[92, "building-an-intel-project"]], "Checking the build and analyzing results": [[92, "checking-the-build-and-analyzing-results"], [92, "id1"]], "Building an AMD project": [[92, "building-an-amd-project"]], "Enabling Out-of-Context synthesis": [[92, "enabling-out-of-context-synthesis"]], "Checking the build and analyzing results of library components": [[92, "checking-the-build-and-analyzing-results-of-library-components"]], "Checking the build and analyzing results of projects": [[92, "checking-the-build-and-analyzing-results-of-projects"]], "Building a Lattice project": [[92, "building-a-lattice-project"]], "Required Lattice Provided IPs to download for projects/common/lfcpnx": [[92, "required-lattice-provided-ips-to-download-for-projects-common-lfcpnx"]], "Supported targets of make command": [[92, "supported-targets-of-make-command"]], "Tools and their versions": [[92, "tools-and-their-versions"]], "Tools": [[92, "tools"], [92, "id2"], [92, "id3"]], "Tool versions": [[92, "tool-versions"]], "Environment": [[92, "environment"]], "Linux environment setup": [[92, "linux-environment-setup"]], "Windows environment setup": [[92, "windows-environment-setup"]], "Preparing the SD card": [[92, "preparing-the-sd-card"]], "Errors, Warnings and Notes": [[92, "errors-warnings-and-notes"]], "AMD: Vivado": [[92, "amd-vivado"]], "Customize HDL projects": [[93, "customize-hdl-projects"]], "Documentation guidelines": [[94, "documentation-guidelines"]], "Templates": [[94, "templates"]], "Common sections": [[94, "common-sections"]], "HDL Git repository": [[95, "hdl-git-repository"]], "Folder structure": [[95, "folder-structure"]], "The projects are structured as follows": [[95, "the-projects-are-structured-as-follows"]], "The library are structured as follows": [[95, "the-library-are-structured-as-follows"]], "Repository releases and branches": [[95, "repository-releases-and-branches"]], "ADI HDL coding guidelines": [[96, "adi-hdl-coding-guidelines"]], "1. Introduction": [[96, "introduction"]], "2. Coding style": [[96, "coding-style"]], "A. Layout": [[96, "a-layout"]], "B. Naming Conventions": [[96, "b-naming-conventions"]], "C. Comments": [[96, "c-comments"]], "D. General": [[96, "d-general"]], "3. Annexes": [[96, "annexes"]], "Annex 1 Verilog file format": [[96, "annex-1-verilog-file-format"]], "Annex 2 VHDL file format": [[96, "annex-2-vhdl-file-format"]], "4. References": [[96, "references"]], "User Guide": [[97, "user-guide"]], "Introduction": [[98, "introduction"]], "Generic AXI ADC": [[99, "generic-axi-adc"]], "Architecture": [[99, "architecture"], [100, "architecture"]], "Receive PHY": [[99, "receive-phy"]], "ADC Channel": [[99, "adc-channel"]], "ADC Core": [[99, "adc-core"]], "LVDS or CMOS RX interface": [[99, "id2"]], "JESD RX interface": [[99, "id3"]], "Write FIFO interface": [[99, "id4"]], "AXI Memory Map Slave": [[99, "id5"], [100, "id5"]], "Typical Register Map base addresses": [[99, "typical-register-map-base-addresses"], [100, "typical-register-map-base-addresses"]], "Generic AXI DAC": [[100, "generic-axi-dac"]], "Transmit PHY": [[100, "transmit-phy"]], "DAC Channel": [[100, "dac-channel"]], "DAC Core": [[100, "dac-core"]], "LVDS or CMOS TX interface": [[100, "id2"]], "JESD TX interface": [[100, "id3"]], "Read FIFO interface": [[100, "id4"]], "Creating a new IP": [[101, "creating-a-new-ip"]], "Verilog File": [[101, "verilog-file"]], "Importing with Using Method": [[101, "importing-with-using-method"]], "Ranged Registers and Fields": [[101, "ranged-registers-and-fields"]], "Xilinx": [[101, "xilinx"]], "TCL File": [[101, "tcl-file"], [101, "id1"]], "Makefile": [[101, "makefile"], [101, "id2"]], "Intel": [[101, "intel"]], "ADI IP cores": [[102, "adi-ip-cores"]], "Frameworks": [[102, "frameworks"]], "ADC/DAC": [[102, "adc-dac"]], "DMA": [[102, "dma"]], "Video": [[102, "video"]], "Utilities": [[102, "utilities"]], "Microprocessor Interface": [[103, "microprocessor-interface"]], "uP Interface and Signals": [[103, "up-interface-and-signals"]], "Clock and reset": [[103, "id2"]], "Read interface": [[103, "id3"]], "Write interface": [[103, "id4"]], "Timing diagram": [[103, "timing-diagram"]], "AMBA AXI": [[103, "amba-axi"]], "Avalon": [[103, "avalon"]], "Use ADI IPs into your own project": [[104, "use-adi-ips-into-your-own-project"]], "Vivado": [[104, "vivado"], [104, "id1"], [104, "id2"]], "Quartus": [[104, "quartus"]], "JESD204": [[104, "jesd204"]], "Porting ADI\u2019s HDL reference designs": [[105, "porting-adi-s-hdl-reference-designs"]], "Quick Compatibility Check": [[105, "quick-compatibility-check"]], "Base design files": [[105, "base-design-files"]], "Example with an AMD Xilinx board": [[105, "example-with-an-amd-xilinx-board"]], "Example with an Intel board": [[105, "example-with-an-intel-board"]], "Example with a Lattice board": [[105, "example-with-a-lattice-board"]], "Project files": [[105, "project-files"]], "Tips": [[105, "tips"]], "Generating the FMC I/O constraints": [[105, "generating-the-fmc-i-o-constraints"]], "Creating carrier common FMC connections": [[105, "creating-carrier-common-fmc-connections"]], "Releases": [[106, "releases"]], "Porting a release branch to another Tool version": [[106, "porting-a-release-branch-to-another-tool-version"]], "Release branches": [[106, "release-branches"]], "About the tools we use": [[106, "about-the-tools-we-use"]], "Third party forks": [[107, "third-party-forks"]]}, "indexentries": {}}) \ No newline at end of file diff --git a/user_guide/architecture.html b/user_guide/architecture.html index 938f886e44..388ae28f72 100644 --- a/user_guide/architecture.html +++ b/user_guide/architecture.html @@ -201,12 +201,15 @@
                                                                        • IP Cores
              • diff --git a/user_guide/ip_cores/interfaces.html b/user_guide/ip_cores/interfaces.html index 2dada4ae5c..af10fef2b9 100644 --- a/user_guide/ip_cores/interfaces.html +++ b/user_guide/ip_cores/interfaces.html @@ -169,12 +169,15 @@
            • IP Cores