From 78dcbb69c4e4dbadf8d3204ee44d7fdd60a49d8b Mon Sep 17 00:00:00 2001 From: Jem Geronimo Date: Wed, 17 May 2023 08:56:18 +0800 Subject: [PATCH] dc2677a: add initial design Signed-off-by: Jem Geronimo dc2677a: c5soc: update Makefile Signed-off-by: Jem Geronimo Readme.md: add build instructions Signed-off-by: Jem Geronimo dc2677a_qsys.tcl: set CSn and PD low by default Signed-off-by: Alexis Torreno fix spaces, indentations, and comments Signed-off-by: Jem Geronimo dc2677a/Readme.md: add useful links, list of supported parts, and build instructions Signed-off-by: Jem Geronimo edit copyright Signed-off-by: Jem Geronimo add copyright and license header to all .tcl and .sdc files Signed-off-by: Jem Geronimo dc2677a_qsys.tcl: remove empty line Signed-off-by: Jem Geronimo dc2677a: Fix critical warnings Fix critical warnings regarding unconnected pin by splitting the system_top.v in system_top_cmos.v and system_top_lvds.v --- library/Makefile | 10 +- library/axi_ltc235x/Makefile | 6 +- library/axi_ltc235x/axi_ltc235x.v | 8 +- library/axi_ltc235x/axi_ltc235x_cmos.v | 157 +++++++------- library/axi_ltc235x/axi_ltc235x_hw.tcl | 4 + library/axi_ltc235x/axi_ltc235x_lvds.v | 122 +++++------ projects/dc2677a/Makefile | 7 + projects/dc2677a/Readme.md | 36 ++++ projects/dc2677a/c5soc/Makefile | 18 ++ projects/dc2677a/c5soc/system_constr.sdc | 11 + projects/dc2677a/c5soc/system_project.tcl | 119 +++++++++++ projects/dc2677a/c5soc/system_qsys.tcl | 18 ++ projects/dc2677a/c5soc/system_top_cmos.v | 234 +++++++++++++++++++++ projects/dc2677a/c5soc/system_top_lvds.v | 242 ++++++++++++++++++++++ projects/dc2677a/common/dc2677a_qsys.tcl | 143 +++++++++++++ 15 files changed, 971 insertions(+), 164 deletions(-) create mode 100644 projects/dc2677a/Makefile create mode 100644 projects/dc2677a/Readme.md create mode 100644 projects/dc2677a/c5soc/Makefile create mode 100644 projects/dc2677a/c5soc/system_constr.sdc create mode 100644 projects/dc2677a/c5soc/system_project.tcl create mode 100644 projects/dc2677a/c5soc/system_qsys.tcl create mode 100644 projects/dc2677a/c5soc/system_top_cmos.v create mode 100644 projects/dc2677a/c5soc/system_top_lvds.v create mode 100644 projects/dc2677a/common/dc2677a_qsys.tcl diff --git a/library/Makefile b/library/Makefile index 83a3bef32bc..9f33aac7bef 100644 --- a/library/Makefile +++ b/library/Makefile @@ -1,10 +1,10 @@ -#################################################################################### -#################################################################################### -## Copyright (c) 2018 - 2023 Analog Devices, Inc. +################################################################################ +################################################################################ +## Copyright (C) 2018-2023 Analog Devices, Inc. ### SPDX short identifier: BSD-1-Clause ## Auto-generated, do not modify! -#################################################################################### -#################################################################################### +################################################################################ +################################################################################ include ../quiet.mk diff --git a/library/axi_ltc235x/Makefile b/library/axi_ltc235x/Makefile index f1d9b3ebb30..2321a36f688 100644 --- a/library/axi_ltc235x/Makefile +++ b/library/axi_ltc235x/Makefile @@ -1,8 +1,8 @@ -#################################################################################### -## Copyright (c) 2018 - 2023 Analog Devices, Inc. +############################################################################### +## Copyright (C) 2018-2023 Analog Devices, Inc. ### SPDX short identifier: BSD-1-Clause ## Auto-generated, do not modify! -#################################################################################### +############################################################################### LIBRARY_NAME := axi_ltc235x diff --git a/library/axi_ltc235x/axi_ltc235x.v b/library/axi_ltc235x/axi_ltc235x.v index 6c65c9d27a8..805f2d0fc22 100644 --- a/library/axi_ltc235x/axi_ltc235x.v +++ b/library/axi_ltc235x/axi_ltc235x.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -43,7 +43,7 @@ module axi_ltc235x #( parameter FPGA_FAMILY = 0, parameter SPEED_GRADE = 0, parameter DEV_PACKAGE = 0, - parameter [0:0] LVDS_CMOS_N = 0, + parameter LVDS_CMOS_N = 0, parameter LANE_0_ENABLE = 1, parameter LANE_1_ENABLE = 1, parameter LANE_2_ENABLE = 1, @@ -146,8 +146,8 @@ module axi_ltc235x #( LANE_2_ENABLE == 1 ? 1'b1 : 1'b0, LANE_1_ENABLE == 1 ? 1'b1 : 1'b0, LANE_0_ENABLE == 1 ? 1'b1 : 1'b0}; - localparam [ 0:0] RD_RAW_DATA = 1'b1; - localparam [ 0:0] CMOS_OR_LVDS_N = ~LVDS_CMOS_N; + localparam RD_RAW_DATA = 1'b1; + localparam CMOS_OR_LVDS_N = ~LVDS_CMOS_N; localparam [31:0] CONFIG = {RD_RAW_DATA, 5'b0, CMOS_OR_LVDS_N, 7'b0}; // internal registers diff --git a/library/axi_ltc235x/axi_ltc235x_cmos.v b/library/axi_ltc235x/axi_ltc235x_cmos.v index 5f0d1959e4e..1eedd7ef344 100644 --- a/library/axi_ltc235x/axi_ltc235x_cmos.v +++ b/library/axi_ltc235x/axi_ltc235x_cmos.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -92,83 +92,83 @@ module axi_ltc235x_cmos #( // internal registers - reg busy_m1; - reg busy_m2; - reg busy_m3; - - reg [ 4:0] scki_counter = 5'h0; - reg [ 4:0] data_counter = 5'h0; - - reg scki_i; - reg scki_d; - - reg [BW:0] adc_lane_0; - reg [BW:0] adc_lane_1; - reg [BW:0] adc_lane_2; - reg [BW:0] adc_lane_3; - reg [BW:0] adc_lane_4; - reg [BW:0] adc_lane_5; - reg [BW:0] adc_lane_6; - reg [BW:0] adc_lane_7; - - reg [BW:0] adc_data_init[7:0]; - reg [BW:0] adc_data_store[7:0]; - - reg [ 2:0] lane_0_ch = 3'd0; - reg [ 2:0] lane_1_ch = 3'd0; - reg [ 2:0] lane_2_ch = 3'd0; - reg [ 2:0] lane_3_ch = 3'd0; - reg [ 2:0] lane_4_ch = 3'd0; - reg [ 2:0] lane_5_ch = 3'd0; - reg [ 2:0] lane_6_ch = 3'd0; - reg [ 2:0] lane_7_ch = 3'd0; - - reg [ 3:0] adc_lane0_shift; - reg [ 3:0] adc_lane1_shift; - reg [ 3:0] adc_lane2_shift; - reg [ 3:0] adc_lane3_shift; - reg [ 3:0] adc_lane4_shift; - reg [ 3:0] adc_lane5_shift; - reg [ 3:0] adc_lane6_shift; - reg [ 3:0] adc_lane7_shift; - - reg [ 3:0] adc_lane0_shift_d; - reg [ 3:0] adc_lane1_shift_d; - reg [ 3:0] adc_lane2_shift_d; - reg [ 3:0] adc_lane3_shift_d; - reg [ 3:0] adc_lane4_shift_d; - reg [ 3:0] adc_lane5_shift_d; - reg [ 3:0] adc_lane6_shift_d; - reg [ 3:0] adc_lane7_shift_d; - - reg adc_valid_init; - reg adc_valid_init_d; - - reg [ 7:0] ch_data_lock = 8'hff; - reg [ 7:0] ch_capture; - reg [ 7:0] ch_captured; - - reg scko_d; - reg [7:0] sdo_d; - - reg [ 4:0] sdi_index = 5'd23; - - reg [23:0] softspan_next_int; + reg busy_m1; + reg busy_m2; + reg busy_m3; + + reg [ 4:0] scki_counter = 5'h0; + reg [ 4:0] data_counter = 5'h0; + + reg scki_i; + reg scki_d; + + reg [BW:0] adc_lane_0; + reg [BW:0] adc_lane_1; + reg [BW:0] adc_lane_2; + reg [BW:0] adc_lane_3; + reg [BW:0] adc_lane_4; + reg [BW:0] adc_lane_5; + reg [BW:0] adc_lane_6; + reg [BW:0] adc_lane_7; + + reg [BW:0] adc_data_init[7:0]; + reg [BW:0] adc_data_store[7:0]; + + reg [ 2:0] lane_0_ch = 3'd0; + reg [ 2:0] lane_1_ch = 3'd0; + reg [ 2:0] lane_2_ch = 3'd0; + reg [ 2:0] lane_3_ch = 3'd0; + reg [ 2:0] lane_4_ch = 3'd0; + reg [ 2:0] lane_5_ch = 3'd0; + reg [ 2:0] lane_6_ch = 3'd0; + reg [ 2:0] lane_7_ch = 3'd0; + + reg [ 3:0] adc_lane0_shift; + reg [ 3:0] adc_lane1_shift; + reg [ 3:0] adc_lane2_shift; + reg [ 3:0] adc_lane3_shift; + reg [ 3:0] adc_lane4_shift; + reg [ 3:0] adc_lane5_shift; + reg [ 3:0] adc_lane6_shift; + reg [ 3:0] adc_lane7_shift; + + reg [ 3:0] adc_lane0_shift_d; + reg [ 3:0] adc_lane1_shift_d; + reg [ 3:0] adc_lane2_shift_d; + reg [ 3:0] adc_lane3_shift_d; + reg [ 3:0] adc_lane4_shift_d; + reg [ 3:0] adc_lane5_shift_d; + reg [ 3:0] adc_lane6_shift_d; + reg [ 3:0] adc_lane7_shift_d; + + reg adc_valid_init; + reg adc_valid_init_d; + + reg [ 7:0] ch_data_lock = 8'hff; + reg [ 7:0] ch_capture; + reg [ 7:0] ch_captured; + + reg scko_d; + reg [ 7:0] sdo_d; + + reg [ 4:0] sdi_index = 5'd23; + + reg [23:0] softspan_next_int; // internal wires - wire start_transfer_s; + wire start_transfer_s; - wire scki_cnt_rst; + wire scki_cnt_rst; - wire acquire_data; + wire acquire_data; - wire [17:0] adc_data_raw_s [7:0]; - wire [31:0] adc_data_sign_s [7:0]; - wire [31:0] adc_data_zero_s [7:0]; - wire [31:0] adc_data_s [7:0]; - wire [ 2:0] adc_ch_id_s [7:0]; - wire [ 2:0] adc_softspan_s [7:0]; + wire [17:0] adc_data_raw_s [7:0]; + wire [31:0] adc_data_sign_s [7:0]; + wire [31:0] adc_data_zero_s [7:0]; + wire [31:0] adc_data_s [7:0]; + wire [ 2:0] adc_ch_id_s [7:0]; + wire [ 2:0] adc_softspan_s [7:0]; always @(posedge clk) begin if (rst == 1'b1) begin @@ -188,7 +188,7 @@ module axi_ltc235x_cmos #( if (rst) begin scki_counter <= 5'h0; scki_i <= 1'b1; - scki_d <= 1'b0; + scki_d <= 1'b0; end else begin scki_d <= scki_i; if (acquire_data == 1'b0) begin @@ -287,14 +287,9 @@ module axi_ltc235x_cmos #( end end - /* - lane_X_ch - channel number that lane X has - e.g., lane_0_ch = 2, means lane 0 has channel 2 - ch_data_lock[i] - locks channel i - e.g., ch_data_lock[7] = 1, means data from channel 7 has already been - sent to an active lane, channel 7 should now be locked. - Don't acquire data if all channels are all already locked. - */ + // lane_x_ch - channel corresponds to which lane, e.g. lane_0_ch stores the current channel lane 0 has + // ch_data_lock[i] - locks ch i, e.g. ch_data_lock[7] = 1 means data from channel 7 has already been sent to an active lane, channel 7 should now be locked + // dont acquire data if all channels are all already locked always @(posedge clk) begin if (start_transfer_s) begin lane_0_ch <= 3'd0; diff --git a/library/axi_ltc235x/axi_ltc235x_hw.tcl b/library/axi_ltc235x/axi_ltc235x_hw.tcl index 37ff5985679..3a1cdc40876 100644 --- a/library/axi_ltc235x/axi_ltc235x_hw.tcl +++ b/library/axi_ltc235x/axi_ltc235x_hw.tcl @@ -1,3 +1,7 @@ +############################################################################### +## Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### # ip package require qsys 14.0 diff --git a/library/axi_ltc235x/axi_ltc235x_lvds.v b/library/axi_ltc235x/axi_ltc235x_lvds.v index 1fe37041f50..ba5adb3a4e0 100644 --- a/library/axi_ltc235x/axi_ltc235x_lvds.v +++ b/library/axi_ltc235x/axi_ltc235x_lvds.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright 2023 (c) Analog Devices, Inc. All rights reserved. +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -100,96 +100,78 @@ module axi_ltc235x_lvds #( // internal registers - reg busy_m1; - reg busy_m2; - reg busy_m3; + reg busy_m1; + reg busy_m2; + reg busy_m3; - reg [ 8:0] scki_counter = 9'h0; - reg [ 8:0] data_counter = 9'h0; + reg [ 8:0] scki_counter = 9'h0; + reg [ 8:0] data_counter = 9'h0; - reg scki_i; - reg scki_d; + reg scki_i; + reg scki_d; - reg [BW_8:0] adc_lane; - reg [BW_8:0] adc_data_init; - reg [BW:0] adc_data_store[7:0]; + reg [BW_8:0] adc_lane; + reg [BW_8:0] adc_data_init; + reg [ BW:0] adc_data_store[7:0]; - reg [ 3:0] adc_lane0_shift; - reg [ 3:0] adc_lane1_shift; - reg [ 3:0] adc_lane2_shift; - reg [ 3:0] adc_lane3_shift; - reg [ 3:0] adc_lane4_shift; - reg [ 3:0] adc_lane5_shift; - reg [ 3:0] adc_lane6_shift; - reg [ 3:0] adc_lane7_shift; + reg adc_valid_init; + reg adc_valid_init_d; - reg [ 3:0] adc_lane0_shift_d; - reg [ 3:0] adc_lane1_shift_d; - reg [ 3:0] adc_lane2_shift_d; - reg [ 3:0] adc_lane3_shift_d; - reg [ 3:0] adc_lane4_shift_d; - reg [ 3:0] adc_lane5_shift_d; - reg [ 3:0] adc_lane6_shift_d; - reg [ 3:0] adc_lane7_shift_d; + reg ch_data_lock = 1; + reg ch_capture; + reg ch_captured; - reg adc_valid_init; - reg adc_valid_init_d; + reg scko_d; + reg sdo_d; - reg ch_data_lock = 1; - reg ch_capture; - reg ch_captured; + reg [ 4:0] sdi_index = 5'd23; - reg scko_d; - reg sdo_d; - - reg [ 4:0] sdi_index = 5'd23; - - reg [23:0] softspan_next_int; + reg [23:0] softspan_next_int; // internal wires - wire start_transfer_s; + wire start_transfer_s; - wire scki_cnt_rst; + wire scki_cnt_rst; - wire acquire_data; + wire acquire_data; - wire [DATA_WIDTH-1:0] adc_data_raw_s [7:0]; - wire [31:0] adc_data_sign_s [7:0]; - wire [31:0] adc_data_zero_s [7:0]; - wire [31:0] adc_data_s [7:0]; - wire [ 2:0] adc_ch_id_s [7:0]; - wire [ 2:0] adc_softspan_s [7:0]; + wire [DATA_WIDTH-1:0] adc_data_raw_s [7:0]; + wire [31:0] adc_data_sign_s [7:0]; + wire [31:0] adc_data_zero_s [7:0]; + wire [31:0] adc_data_s [7:0]; + wire [ 2:0] adc_ch_id_s [7:0]; + wire [ 2:0] adc_softspan_s [7:0]; - wire scki; - wire sdi; - wire scko; - wire sdo; + wire scki_s; + wire sdi_s; + wire scko_s; + wire sdo_s; generate if (XILINX_INTEL_N == 0) begin - assign scki_p = scki; + assign scki_p = scki_s; assign scki_n = 1'b0; - assign sdi_p = sdi; + assign sdi_p = sdi_s; assign sdi_n = 1'b0; - assign scko = scko_p; - assign sdo = sdo_p; + assign scko_s = scko_p; + assign sdo_s = sdo_p; end else begin OBUFDS obufds_scki ( .O(scki_n), .OB(scki_p), - .I(scki)); + .I(scki_s)); OBUFDS obufds_sdi ( .O(sdi_n), .OB(sdi_p), - .I(sdi)); + .I(sdi_s)); IBUFDS #( .CCIO_EN_M("TRUE"), .CCIO_EN_S("TRUE") ) ibufds_scko ( - .O(scko), + .O(scko_s), .I(scko_p), .IB(scko_n)); @@ -197,7 +179,7 @@ module axi_ltc235x_lvds #( .CCIO_EN_M("TRUE"), .CCIO_EN_S("TRUE") ) ibufds_sdo ( - .O(sdo), + .O(sdo_s), .I(sdo_p), .IB(sdo_n)); end @@ -238,21 +220,20 @@ module axi_ltc235x_lvds #( end assign scki_cnt_rst = (scki_counter == DW_8); - assign scki = scki_i & acquire_data; + assign scki_s = scki_i & acquire_data; - // capture data per lane in rx buffer on every edge of scko - // ignore when busy forced scko to 0 + // capture data per lane in rx buffer on every edge of scko_s + // ignore when busy forced scko_s to 0 always @(posedge clk) begin - scko_d <= scko; - sdo_d <= sdo; - if (scko != scko_d && scki != scki_d) begin + scko_d <= scko_s; + sdo_d <= sdo_s; + if (scko_s != scko_d && scki_s != scki_d) begin adc_lane <= {adc_lane[BW_8-1:0], sdo_d}; end end // store the data from the rx buffers when all bits are received // when data transaction window is done - // index is based by lane always @(posedge clk) begin if (rst == 1'b1) begin adc_data_init <= 'h0; @@ -265,8 +246,7 @@ module axi_ltc235x_lvds #( end end - // lane_x_data - ch corresponds to which lane - // ch_data_lock[i] - locks ch i, means dont acquire data if all ch's are lock while acquire_data = 0 + // ch_data_lock - locks all the channel, means dont acquire data if all ch's are lock while acquire_data = 0 always @(posedge clk) begin if (start_transfer_s) begin ch_data_lock <= 1'd0; @@ -398,12 +378,12 @@ module axi_ltc235x_lvds #( end end - // every negedge of clk, update index of sdi + // every negedge of clk, update index of sdi_s always @(negedge clk) begin if (start_transfer_s || rst) begin sdi_index <= 5'd23; end else begin - if (scki != scki_d && sdi_index != 5'b11111) begin + if (scki_s != scki_d && sdi_index != 5'b11111) begin sdi_index <= sdi_index - 5'b1; end end @@ -422,6 +402,6 @@ module axi_ltc235x_lvds #( end end - assign sdi = (sdi_index != 5'b11111)? softspan_next_int[sdi_index] : 1'b0; + assign sdi_s = (sdi_index != 5'b11111)? softspan_next_int[sdi_index] : 1'b0; endmodule diff --git a/projects/dc2677a/Makefile b/projects/dc2677a/Makefile new file mode 100644 index 00000000000..a3e47bd1beb --- /dev/null +++ b/projects/dc2677a/Makefile @@ -0,0 +1,7 @@ +############################################################################### +## Copyright (C) 2018-2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +############################################################################### + +include ../scripts/project-toplevel.mk diff --git a/projects/dc2677a/Readme.md b/projects/dc2677a/Readme.md new file mode 100644 index 00000000000..86908d387df --- /dev/null +++ b/projects/dc2677a/Readme.md @@ -0,0 +1,36 @@ +# DC2677A HDL Project + +Here are some pointers to help you: + * [Board Product Page](https://www.analog.com/en/design-center/evaluation-hardware-and-software/evaluation-boards-kits/dc2677a.html) + * Parts : [Buffered Octal, 18-Bit, 200ksps/Ch Differential ±10.24V ADC with 30VP-P Common Mode Range](https://www.analog.com/en/products/ltc2358-18.html) + * Project Doc: https://wiki.analog.com/resources/eval/user-guides/dc2677a + * HDL Doc: https://wiki.analog.com/resources/eval/user-guides/dc2677a + * Linux Drivers: https://wiki.analog.com/resources/tools-software/linux-drivers-all + +## Supported parts + * LTC2358-18 + * LTC2358-16 + * LTC2357-18 + * LTC2357-16 + * LTC2353-18 + * LTC2353-16 + +## Project Parameters + +LVDS_CMOS_N: + * 0 - CMOS (default) + * 1 - LVDS + +LTC235X_FAMILY: + * 0 = 2358-18 (default) + * 1 = 2358-16 + * 2 = 2357-18 + * 3 = 2357-16 + * 4 = 2353-18 + * 5 = 2353-16 + +### How to build +e.g, to build the project for **LTC2358-18** using the **CMOS Interface** +``` +make LVDS_CMOS_N=0 LTC235X_FAMILY=0 +``` diff --git a/projects/dc2677a/c5soc/Makefile b/projects/dc2677a/c5soc/Makefile new file mode 100644 index 00000000000..013f2c798be --- /dev/null +++ b/projects/dc2677a/c5soc/Makefile @@ -0,0 +1,18 @@ +############################################################################### +## Copyright (C) 2018-2023 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +############################################################################### + +PROJECT_NAME := dc2677a_c5soc + +M_DEPS += ../../scripts/adi_project_intel.tcl +M_DEPS += ../../scripts/adi_pd.tcl +M_DEPS += ../../dc2677a/common/dc2677a_qsys.tcl +M_DEPS += ../../common/c5soc/c5soc_system_qsys.tcl +M_DEPS += ../../common/c5soc/c5soc_system_assign.tcl +M_DEPS += ../../../scripts/adi_env.tcl + +LIB_DEPS += axi_hdmi_tx + +include ../../scripts/project-intel.mk diff --git a/projects/dc2677a/c5soc/system_constr.sdc b/projects/dc2677a/c5soc/system_constr.sdc new file mode 100644 index 00000000000..c43ca868d5d --- /dev/null +++ b/projects/dc2677a/c5soc/system_constr.sdc @@ -0,0 +1,11 @@ +############################################################################### +## Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +create_clock -period "20.000 ns" -name sys_clk [get_ports {sys_clk}] + +derive_pll_clocks +derive_clock_uncertainty + +set_false_path -from [get_registers *altera_reset_synchronizer:alt_rst_sync_uq1|altera_reset_synchronizer_int_chain_out*] diff --git a/projects/dc2677a/c5soc/system_project.tcl b/projects/dc2677a/c5soc/system_project.tcl new file mode 100644 index 00000000000..4eabae9efdf --- /dev/null +++ b/projects/dc2677a/c5soc/system_project.tcl @@ -0,0 +1,119 @@ +############################################################################### +## Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +set REQUIRED_QUARTUS_VERSION 22.1std.0 +set QUARTUS_PRO_ISUSED 0 +source ../../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_intel.tcl + +set LVDS_CMOS_N [get_env_param LVDS_CMOS_N 0] + # 0 - CMOS + # 1 - LVDS +set LTC235X_FAMILY [get_env_param LTC235X_FAMILY 0] + # 0 = 2358-18 + # 1 = 2358-16 + # 2 = 2357-18 + # 3 = 2357-16 + # 4 = 2353-18 + # 5 = 2353-16 + +adi_project dc2677a_c5soc [list \ + LVDS_CMOS_N $LVDS_CMOS_N \ + LTC235X_FAMILY $LTC235X_FAMILY \ +] + +source $ad_hdl_dir/projects/common/c5soc/c5soc_system_assign.tcl + +set_global_assignment -name VERILOG_FILE -remove system_top.v + +# ltc235x interface + +set_location_assignment PIN_K12 -to lvds_cmos_n ; # lvds_cmos_n 54 lvds_rxp1 +set_location_assignment PIN_G12 -to cnv ; # cnv 48 lvds_rxp0 +set_location_assignment PIN_F9 -to busy ; # busy 90 lvds_rxp7 +set_location_assignment PIN_F8 -to cs_n ; # cs_n 92 lvds_rxn7 +set_location_assignment PIN_G11 -to pd ; # pd 50 lvds_rxn0 + +if {$LVDS_CMOS_N == 1} { + # lvds + + set_global_assignment -name VERILOG_FILE system_top_lvds.v + set_global_assignment -name TOP_LEVEL_ENTITY system_top_lvds + + set_instance_assignment -name IO_STANDARD "2.5V" -to lvds_cmos_n + set_instance_assignment -name IO_STANDARD "2.5V" -to cnv + set_instance_assignment -name IO_STANDARD "2.5V" -to busy + set_instance_assignment -name IO_STANDARD "2.5V" -to cs_n + set_instance_assignment -name IO_STANDARD "2.5V" -to pd + + set_location_assignment PIN_G10 -to sdi_p ; # sdo_1 60 lvds_rxp2 / sdi_p + set_location_assignment PIN_F10 -to "sdi_p(n)" ; # sdo_2 62 lvds_rxn2 / sdi_n + set_location_assignment PIN_J10 -to scki_p ; # sdo_3 66 lvds_rxp3 / scki_p + set_location_assignment PIN_J9 -to "scki_p(n)" ; # scki 68 lvds_rxn3 / scki_n + set_location_assignment PIN_K7 -to scko_p ; # scko 72 lvds_rxp4 / scko_p + set_location_assignment PIN_K8 -to "scko_p(n)" ; # sdo_4 74 lvds_rxn4 / scko_n + set_location_assignment PIN_J7 -to sdo_p ; # sdo_5 78 lvds_rxp5 / sdo_p + set_location_assignment PIN_H7 -to "sdo_p(n)" ; # sdo_6 80 lvds_rxn5 / sdo_n + + set_instance_assignment -name IO_STANDARD "mini-LVDS_E_1R" -to sdi_p + set_instance_assignment -name IO_STANDARD "mini-LVDS_E_1R" -to scki_p + set_instance_assignment -name IO_STANDARD "LVDS" -to scko_p + set_instance_assignment -name IO_STANDARD "LVDS" -to sdo_p + + set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to scko_p + set_instance_assignment -name INPUT_TERMINATION DIFFERENTIAL -to sdo_p +} else { + # cmos + + set_global_assignment -name VERILOG_FILE system_top_cmos.v + set_global_assignment -name TOP_LEVEL_ENTITY system_top_cmos + + set_instance_assignment -name IO_STANDARD "3.3V LVCMOS" -to lvds_cmos_n + set_instance_assignment -name IO_STANDARD "3.3V LVCMOS" -to cnv + set_instance_assignment -name IO_STANDARD "3.3V LVCMOS" -to busy + set_instance_assignment -name IO_STANDARD "3.3V LVCMOS" -to cs_n + set_instance_assignment -name IO_STANDARD "3.3V LVCMOS" -to pd + + set_location_assignment PIN_G8 -to sdi ; # sdi 86 lvds_rxn6 + set_location_assignment PIN_J9 -to scki ; # scki 68 lvds_rxn3 / scki_n + set_location_assignment PIN_K7 -to scko ; # scko 72 lvds_rxp4 / scko_p + + set_instance_assignment -name IO_STANDARD "3.3V LVCMOS" -to sdi + set_instance_assignment -name IO_STANDARD "3.3V LVCMOS" -to scki + set_instance_assignment -name IO_STANDARD "3.3V LVCMOS" -to scko + + if {$LTC235X_FAMILY <= 1} { + # 2358 + set_location_assignment PIN_J12 -to sdo[0] ; # sdo_0 56 lvds_rxn1 + set_location_assignment PIN_G10 -to sdo[1] ; # sdo_1 60 lvds_rxp2 / sdi_p + set_location_assignment PIN_F10 -to sdo[2] ; # sdo_2 62 lvds_rxn2 / sdi_n + set_location_assignment PIN_J10 -to sdo[3] ; # sdo_3 66 lvds_rxp3 / scki_p + set_location_assignment PIN_K8 -to sdo[4] ; # sdo_4 74 lvds_rxn4 / scko_n + set_location_assignment PIN_J7 -to sdo[5] ; # sdo_5 78 lvds_rxp5 / sdo_p + set_location_assignment PIN_H7 -to sdo[6] ; # sdo_6 80 lvds_rxn5 / sdo_n + set_location_assignment PIN_H8 -to sdo[7] ; # sdo_7 84 lvds_rxp6 + } elseif {$LTC235X_FAMILY <= 3} { + # 2357 + set_location_assignment PIN_F10 -to sdo[0] ; # sdo_1 62 lvds_rxn2 / sdi_n + set_location_assignment PIN_J10 -to sdo[1] ; # sdo_2 66 lvds_rxp3 / scki_p + set_location_assignment PIN_K8 -to sdo[2] ; # sdo_3 74 lvds_rxn4 / scko_n + set_location_assignment PIN_J7 -to sdo[3] ; # sdo_4 78 lvds_rxp5 / sdo_p + } else { + # 2353 + set_location_assignment PIN_J10 -to sdo[0] ; # sdo_0 66 lvds_rxp3 / scki_p + set_location_assignment PIN_K8 -to sdo[1] ; # sdo_1 74 lvds_rxn4 / scko_n + } + + set_instance_assignment -name IO_STANDARD "3.3V LVCMOS" -to sdo[0] + set_instance_assignment -name IO_STANDARD "3.3V LVCMOS" -to sdo[1] + set_instance_assignment -name IO_STANDARD "3.3V LVCMOS" -to sdo[2] + set_instance_assignment -name IO_STANDARD "3.3V LVCMOS" -to sdo[3] + set_instance_assignment -name IO_STANDARD "3.3V LVCMOS" -to sdo[4] + set_instance_assignment -name IO_STANDARD "3.3V LVCMOS" -to sdo[5] + set_instance_assignment -name IO_STANDARD "3.3V LVCMOS" -to sdo[6] + set_instance_assignment -name IO_STANDARD "3.3V LVCMOS" -to sdo[7] +} + +execute_flow -compile diff --git a/projects/dc2677a/c5soc/system_qsys.tcl b/projects/dc2677a/c5soc/system_qsys.tcl new file mode 100644 index 00000000000..df675377d15 --- /dev/null +++ b/projects/dc2677a/c5soc/system_qsys.tcl @@ -0,0 +1,18 @@ +############################################################################### +## Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +source $ad_hdl_dir/projects/scripts/adi_pd.tcl +source $ad_hdl_dir/projects/common/c5soc/c5soc_system_qsys.tcl +set xilinx_intel_n 0 +source $ad_hdl_dir/projects/dc2677a/common/dc2677a_qsys.tcl + +#system ID +set_instance_parameter_value axi_sysid_0 {ROM_ADDR_BITS} {9} +set_instance_parameter_value rom_sys_0 {ROM_ADDR_BITS} {9} + +set_instance_parameter_value rom_sys_0 {PATH_TO_FILE} "[pwd]/mem_init_sys.txt" + +set sys_cstring "LVDS_CMOS_N=${ad_project_params(LVDS_CMOS_N)}" +sysid_gen_sys_init_file $sys_cstring diff --git a/projects/dc2677a/c5soc/system_top_cmos.v b/projects/dc2677a/c5soc/system_top_cmos.v new file mode 100644 index 00000000000..501ab35e5de --- /dev/null +++ b/projects/dc2677a/c5soc/system_top_cmos.v @@ -0,0 +1,234 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top_cmos ( + + // clock and resets + input sys_clk, + + // hps-ddr + output [14:0] ddr3_a, + output [ 2:0] ddr3_ba, + output ddr3_reset_n, + output ddr3_ck_p, + output ddr3_ck_n, + output ddr3_cke, + output ddr3_cs_n, + output ddr3_ras_n, + output ddr3_cas_n, + output ddr3_we_n, + inout [31:0] ddr3_dq, + inout [ 3:0] ddr3_dqs_p, + inout [ 3:0] ddr3_dqs_n, + output [ 3:0] ddr3_dm, + output ddr3_odt, + input ddr3_rzq, + + // hps-ethernet + output eth1_tx_clk, + output eth1_tx_ctl, + output [ 3:0] eth1_tx_d, + input eth1_rx_clk, + input eth1_rx_ctl, + input [ 3:0] eth1_rx_d, + output eth1_mdc, + inout eth1_mdio, + + // hps-qspi + output qspi_ss0, + output qspi_clk, + inout [ 3:0] qspi_io, + + // hps-sdio + output sdio_clk, + inout sdio_cmd, + inout [ 3:0] sdio_d, + + // hps-usb + input usb1_clk, + output usb1_stp, + input usb1_dir, + input usb1_nxt, + inout [ 7:0] usb1_d, + + // hps-spim1-lcd + output spim1_ss0, + output spim1_clk, + output spim1_mosi, + input spim1_miso, + + // hps-uart + input uart0_rx, + output uart0_tx, + + // board gpio + output [ 3:0] gpio_bd_o, + input [ 7:0] gpio_bd_i, + + // display + output vga_clk, + output vga_blank_n, + output vga_sync_n, + output vga_hsync, + output vga_vsync, + output [ 7:0] vga_red, + output [ 7:0] vga_grn, + output [ 7:0] vga_blu, + + // ltc235x interface + output lvds_cmos_n, + output cnv, + input busy, + output pd, + output cs_n, + + output sdi, + output scki, + input scko, + input [ 7:0] sdo +); + + // internal signals + wire sys_resetn; + wire [31:0] sys_gpio_bd_i; + wire [31:0] sys_gpio_bd_o; + wire [31:0] sys_gpio_i; + wire [31:0] sys_gpio_o; + + // defaults + assign vga_blank_n = 1'b1; + assign vga_sync_n = 1'b0; + + assign gpio_bd_o = sys_gpio_bd_o[3:0]; + + assign sys_gpio_bd_i[31:8] = sys_gpio_bd_o[31:8]; + assign sys_gpio_bd_i[ 7:0] = gpio_bd_i; + + assign sys_gpio_i[31:0] = sys_gpio_o[31:0]; + + assign pd = sys_gpio_o[0]; + assign cs_n = sys_gpio_o[1]; + + // instantiations + system_bd i_system_bd ( + .sys_clk_clk (sys_clk), + .sys_hps_memory_mem_a (ddr3_a), + .sys_hps_memory_mem_ba (ddr3_ba), + .sys_hps_memory_mem_ck (ddr3_ck_p), + .sys_hps_memory_mem_ck_n (ddr3_ck_n), + .sys_hps_memory_mem_cke (ddr3_cke), + .sys_hps_memory_mem_cs_n (ddr3_cs_n), + .sys_hps_memory_mem_ras_n (ddr3_ras_n), + .sys_hps_memory_mem_cas_n (ddr3_cas_n), + .sys_hps_memory_mem_we_n (ddr3_we_n), + .sys_hps_memory_mem_reset_n (ddr3_reset_n), + .sys_hps_memory_mem_dq (ddr3_dq), + .sys_hps_memory_mem_dqs (ddr3_dqs_p), + .sys_hps_memory_mem_dqs_n (ddr3_dqs_n), + .sys_hps_memory_mem_odt (ddr3_odt), + .sys_hps_memory_mem_dm (ddr3_dm), + .sys_hps_memory_oct_rzqin (ddr3_rzq), + .sys_hps_hps_io_hps_io_emac1_inst_TX_CLK (eth1_tx_clk), + .sys_hps_hps_io_hps_io_emac1_inst_TXD0 (eth1_tx_d[0]), + .sys_hps_hps_io_hps_io_emac1_inst_TXD1 (eth1_tx_d[1]), + .sys_hps_hps_io_hps_io_emac1_inst_TXD2 (eth1_tx_d[2]), + .sys_hps_hps_io_hps_io_emac1_inst_TXD3 (eth1_tx_d[3]), + .sys_hps_hps_io_hps_io_emac1_inst_RXD0 (eth1_rx_d[0]), + .sys_hps_hps_io_hps_io_emac1_inst_MDIO (eth1_mdio), + .sys_hps_hps_io_hps_io_emac1_inst_MDC (eth1_mdc), + .sys_hps_hps_io_hps_io_emac1_inst_RX_CTL (eth1_rx_ctl), + .sys_hps_hps_io_hps_io_emac1_inst_TX_CTL (eth1_tx_ctl), + .sys_hps_hps_io_hps_io_emac1_inst_RX_CLK (eth1_rx_clk), + .sys_hps_hps_io_hps_io_emac1_inst_RXD1 (eth1_rx_d[1]), + .sys_hps_hps_io_hps_io_emac1_inst_RXD2 (eth1_rx_d[2]), + .sys_hps_hps_io_hps_io_emac1_inst_RXD3 (eth1_rx_d[3]), + .sys_hps_hps_io_hps_io_qspi_inst_IO0 (qspi_io[0]), + .sys_hps_hps_io_hps_io_qspi_inst_IO1 (qspi_io[1]), + .sys_hps_hps_io_hps_io_qspi_inst_IO2 (qspi_io[2]), + .sys_hps_hps_io_hps_io_qspi_inst_IO3 (qspi_io[3]), + .sys_hps_hps_io_hps_io_qspi_inst_SS0 (qspi_ss0), + .sys_hps_hps_io_hps_io_qspi_inst_CLK (qspi_clk), + .sys_hps_hps_io_hps_io_sdio_inst_CMD (sdio_cmd), + .sys_hps_hps_io_hps_io_sdio_inst_D0 (sdio_d[0]), + .sys_hps_hps_io_hps_io_sdio_inst_D1 (sdio_d[1]), + .sys_hps_hps_io_hps_io_sdio_inst_CLK (sdio_clk), + .sys_hps_hps_io_hps_io_sdio_inst_D2 (sdio_d[2]), + .sys_hps_hps_io_hps_io_sdio_inst_D3 (sdio_d[3]), + .sys_hps_hps_io_hps_io_usb1_inst_D0 (usb1_d[0]), + .sys_hps_hps_io_hps_io_usb1_inst_D1 (usb1_d[1]), + .sys_hps_hps_io_hps_io_usb1_inst_D2 (usb1_d[2]), + .sys_hps_hps_io_hps_io_usb1_inst_D3 (usb1_d[3]), + .sys_hps_hps_io_hps_io_usb1_inst_D4 (usb1_d[4]), + .sys_hps_hps_io_hps_io_usb1_inst_D5 (usb1_d[5]), + .sys_hps_hps_io_hps_io_usb1_inst_D6 (usb1_d[6]), + .sys_hps_hps_io_hps_io_usb1_inst_D7 (usb1_d[7]), + .sys_hps_hps_io_hps_io_usb1_inst_CLK (usb1_clk), + .sys_hps_hps_io_hps_io_usb1_inst_STP (usb1_stp), + .sys_hps_hps_io_hps_io_usb1_inst_DIR (usb1_dir), + .sys_hps_hps_io_hps_io_usb1_inst_NXT (usb1_nxt), + .sys_hps_hps_io_hps_io_spim1_inst_CLK (spim1_clk), + .sys_hps_hps_io_hps_io_spim1_inst_MOSI (spim1_mosi), + .sys_hps_hps_io_hps_io_spim1_inst_MISO (spim1_miso), + .sys_hps_hps_io_hps_io_spim1_inst_SS0 (spim1_ss0), + .sys_hps_hps_io_hps_io_uart0_inst_RX (uart0_rx), + .sys_hps_hps_io_hps_io_uart0_inst_TX (uart0_tx), + .sys_gpio_bd_in_port (sys_gpio_bd_i), + .sys_gpio_bd_out_port (sys_gpio_bd_o), + .sys_gpio_in_export (sys_gpio_i), + .sys_gpio_out_export (sys_gpio_o), + .pr_rom_data_nc_rom_data ('h0), + .sys_hps_h2f_reset_reset_n (sys_resetn), + .sys_rst_reset_n (sys_resetn), + .sys_spi_MISO (1'b0), + .sys_spi_MOSI (), + .sys_spi_SCLK (), + .sys_spi_SS_n (1'b1), + .vga_out_vga_if_vga_clk (vga_clk), + .vga_out_vga_if_vga_red (vga_red), + .vga_out_vga_if_vga_green (vga_grn), + .vga_out_vga_if_vga_blue (vga_blu), + .vga_out_vga_if_vga_hsync (vga_hsync), + .vga_out_vga_if_vga_vsync (vga_vsync), + .axi_ltc235x_device_if_lvds_cmos_n (lvds_cmos_n), + .axi_ltc235x_device_if_busy (busy), + .axi_ltc235x_cnv_if_if_pwm(cnv), + .axi_ltc235x_device_if_sdo (sdo), + .axi_ltc235x_device_if_scki (scki), + .axi_ltc235x_device_if_scko (scko), + .axi_ltc235x_device_if_sdi (sdi)); + +endmodule diff --git a/projects/dc2677a/c5soc/system_top_lvds.v b/projects/dc2677a/c5soc/system_top_lvds.v new file mode 100644 index 00000000000..0a973b3ee80 --- /dev/null +++ b/projects/dc2677a/c5soc/system_top_lvds.v @@ -0,0 +1,242 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top_lvds ( + + // clock and resets + input sys_clk, + + // hps-ddr + output [14:0] ddr3_a, + output [ 2:0] ddr3_ba, + output ddr3_reset_n, + output ddr3_ck_p, + output ddr3_ck_n, + output ddr3_cke, + output ddr3_cs_n, + output ddr3_ras_n, + output ddr3_cas_n, + output ddr3_we_n, + inout [31:0] ddr3_dq, + inout [ 3:0] ddr3_dqs_p, + inout [ 3:0] ddr3_dqs_n, + output [ 3:0] ddr3_dm, + output ddr3_odt, + input ddr3_rzq, + + // hps-ethernet + output eth1_tx_clk, + output eth1_tx_ctl, + output [ 3:0] eth1_tx_d, + input eth1_rx_clk, + input eth1_rx_ctl, + input [ 3:0] eth1_rx_d, + output eth1_mdc, + inout eth1_mdio, + + // hps-qspi + output qspi_ss0, + output qspi_clk, + inout [ 3:0] qspi_io, + + // hps-sdio + output sdio_clk, + inout sdio_cmd, + inout [ 3:0] sdio_d, + + // hps-usb + input usb1_clk, + output usb1_stp, + input usb1_dir, + input usb1_nxt, + inout [ 7:0] usb1_d, + + // hps-spim1-lcd + output spim1_ss0, + output spim1_clk, + output spim1_mosi, + input spim1_miso, + + // hps-uart + input uart0_rx, + output uart0_tx, + + // board gpio + output [ 3:0] gpio_bd_o, + input [ 7:0] gpio_bd_i, + + // display + output vga_clk, + output vga_blank_n, + output vga_sync_n, + output vga_hsync, + output vga_vsync, + output [ 7:0] vga_red, + output [ 7:0] vga_grn, + output [ 7:0] vga_blu, + + // ltc235x interface + output lvds_cmos_n, + output cnv, + input busy, + output pd, + output cs_n, + + output sdi_p, + output sdi_n, + output scki_p, + output scki_n, + input scko_p, + input scko_n, + input sdo_p, + input sdo_n +); + + // internal signals + wire sys_resetn; + wire [31:0] sys_gpio_bd_i; + wire [31:0] sys_gpio_bd_o; + wire [31:0] sys_gpio_i; + wire [31:0] sys_gpio_o; + + // defaults + assign vga_blank_n = 1'b1; + assign vga_sync_n = 1'b0; + + assign gpio_bd_o = sys_gpio_bd_o[3:0]; + + assign sys_gpio_bd_i[31:8] = sys_gpio_bd_o[31:8]; + assign sys_gpio_bd_i[ 7:0] = gpio_bd_i; + + assign sys_gpio_i[31:0] = sys_gpio_o[31:0]; + + assign pd = sys_gpio_o[0]; + assign cs_n = sys_gpio_o[1]; + + // instantiations + system_bd i_system_bd ( + .sys_clk_clk (sys_clk), + .sys_hps_memory_mem_a (ddr3_a), + .sys_hps_memory_mem_ba (ddr3_ba), + .sys_hps_memory_mem_ck (ddr3_ck_p), + .sys_hps_memory_mem_ck_n (ddr3_ck_n), + .sys_hps_memory_mem_cke (ddr3_cke), + .sys_hps_memory_mem_cs_n (ddr3_cs_n), + .sys_hps_memory_mem_ras_n (ddr3_ras_n), + .sys_hps_memory_mem_cas_n (ddr3_cas_n), + .sys_hps_memory_mem_we_n (ddr3_we_n), + .sys_hps_memory_mem_reset_n (ddr3_reset_n), + .sys_hps_memory_mem_dq (ddr3_dq), + .sys_hps_memory_mem_dqs (ddr3_dqs_p), + .sys_hps_memory_mem_dqs_n (ddr3_dqs_n), + .sys_hps_memory_mem_odt (ddr3_odt), + .sys_hps_memory_mem_dm (ddr3_dm), + .sys_hps_memory_oct_rzqin (ddr3_rzq), + .sys_hps_hps_io_hps_io_emac1_inst_TX_CLK (eth1_tx_clk), + .sys_hps_hps_io_hps_io_emac1_inst_TXD0 (eth1_tx_d[0]), + .sys_hps_hps_io_hps_io_emac1_inst_TXD1 (eth1_tx_d[1]), + .sys_hps_hps_io_hps_io_emac1_inst_TXD2 (eth1_tx_d[2]), + .sys_hps_hps_io_hps_io_emac1_inst_TXD3 (eth1_tx_d[3]), + .sys_hps_hps_io_hps_io_emac1_inst_RXD0 (eth1_rx_d[0]), + .sys_hps_hps_io_hps_io_emac1_inst_MDIO (eth1_mdio), + .sys_hps_hps_io_hps_io_emac1_inst_MDC (eth1_mdc), + .sys_hps_hps_io_hps_io_emac1_inst_RX_CTL (eth1_rx_ctl), + .sys_hps_hps_io_hps_io_emac1_inst_TX_CTL (eth1_tx_ctl), + .sys_hps_hps_io_hps_io_emac1_inst_RX_CLK (eth1_rx_clk), + .sys_hps_hps_io_hps_io_emac1_inst_RXD1 (eth1_rx_d[1]), + .sys_hps_hps_io_hps_io_emac1_inst_RXD2 (eth1_rx_d[2]), + .sys_hps_hps_io_hps_io_emac1_inst_RXD3 (eth1_rx_d[3]), + .sys_hps_hps_io_hps_io_qspi_inst_IO0 (qspi_io[0]), + .sys_hps_hps_io_hps_io_qspi_inst_IO1 (qspi_io[1]), + .sys_hps_hps_io_hps_io_qspi_inst_IO2 (qspi_io[2]), + .sys_hps_hps_io_hps_io_qspi_inst_IO3 (qspi_io[3]), + .sys_hps_hps_io_hps_io_qspi_inst_SS0 (qspi_ss0), + .sys_hps_hps_io_hps_io_qspi_inst_CLK (qspi_clk), + .sys_hps_hps_io_hps_io_sdio_inst_CMD (sdio_cmd), + .sys_hps_hps_io_hps_io_sdio_inst_D0 (sdio_d[0]), + .sys_hps_hps_io_hps_io_sdio_inst_D1 (sdio_d[1]), + .sys_hps_hps_io_hps_io_sdio_inst_CLK (sdio_clk), + .sys_hps_hps_io_hps_io_sdio_inst_D2 (sdio_d[2]), + .sys_hps_hps_io_hps_io_sdio_inst_D3 (sdio_d[3]), + .sys_hps_hps_io_hps_io_usb1_inst_D0 (usb1_d[0]), + .sys_hps_hps_io_hps_io_usb1_inst_D1 (usb1_d[1]), + .sys_hps_hps_io_hps_io_usb1_inst_D2 (usb1_d[2]), + .sys_hps_hps_io_hps_io_usb1_inst_D3 (usb1_d[3]), + .sys_hps_hps_io_hps_io_usb1_inst_D4 (usb1_d[4]), + .sys_hps_hps_io_hps_io_usb1_inst_D5 (usb1_d[5]), + .sys_hps_hps_io_hps_io_usb1_inst_D6 (usb1_d[6]), + .sys_hps_hps_io_hps_io_usb1_inst_D7 (usb1_d[7]), + .sys_hps_hps_io_hps_io_usb1_inst_CLK (usb1_clk), + .sys_hps_hps_io_hps_io_usb1_inst_STP (usb1_stp), + .sys_hps_hps_io_hps_io_usb1_inst_DIR (usb1_dir), + .sys_hps_hps_io_hps_io_usb1_inst_NXT (usb1_nxt), + .sys_hps_hps_io_hps_io_spim1_inst_CLK (spim1_clk), + .sys_hps_hps_io_hps_io_spim1_inst_MOSI (spim1_mosi), + .sys_hps_hps_io_hps_io_spim1_inst_MISO (spim1_miso), + .sys_hps_hps_io_hps_io_spim1_inst_SS0 (spim1_ss0), + .sys_hps_hps_io_hps_io_uart0_inst_RX (uart0_rx), + .sys_hps_hps_io_hps_io_uart0_inst_TX (uart0_tx), + .sys_gpio_bd_in_port (sys_gpio_bd_i), + .sys_gpio_bd_out_port (sys_gpio_bd_o), + .sys_gpio_in_export (sys_gpio_i), + .sys_gpio_out_export (sys_gpio_o), + .pr_rom_data_nc_rom_data ('h0), + .sys_hps_h2f_reset_reset_n (sys_resetn), + .sys_rst_reset_n (sys_resetn), + .sys_spi_MISO (1'b0), + .sys_spi_MOSI (), + .sys_spi_SCLK (), + .sys_spi_SS_n (1'b1), + .vga_out_vga_if_vga_clk (vga_clk), + .vga_out_vga_if_vga_red (vga_red), + .vga_out_vga_if_vga_green (vga_grn), + .vga_out_vga_if_vga_blue (vga_blu), + .vga_out_vga_if_vga_hsync (vga_hsync), + .vga_out_vga_if_vga_vsync (vga_vsync), + .axi_ltc235x_device_if_lvds_cmos_n (lvds_cmos_n), + .axi_ltc235x_device_if_busy (busy), + .axi_ltc235x_cnv_if_if_pwm(cnv), + .axi_ltc235x_device_if_sdo_p (sdo_p), + .axi_ltc235x_device_if_sdo_n (sdo_n), + .axi_ltc235x_device_if_scki_p (scki_p), + .axi_ltc235x_device_if_scki_n (scki_n), + .axi_ltc235x_device_if_scko_p (scko_p), + .axi_ltc235x_device_if_scko_n (scko_n), + .axi_ltc235x_device_if_sdi_p (sdi_p), + .axi_ltc235x_device_if_sdi_n (sdi_n)); + +endmodule diff --git a/projects/dc2677a/common/dc2677a_qsys.tcl b/projects/dc2677a/common/dc2677a_qsys.tcl new file mode 100644 index 00000000000..3af926201da --- /dev/null +++ b/projects/dc2677a/common/dc2677a_qsys.tcl @@ -0,0 +1,143 @@ +############################################################################### +## Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +### SPDX short identifier: ADIBSD +############################################################################### + +# LTC235x attributes + +set LVDS_CMOS_N ${ad_project_params(LVDS_CMOS_N)} +set CHIP_SELECT_N 0 +set ADC_EXTERNAL_CLK 0 +set LTC235X_FAMILY ${ad_project_params(LTC235X_FAMILY)} +set ADC_LANE_0_ENABLE 1 +set ADC_LANE_1_ENABLE 1 + +if {$LTC235X_FAMILY <= 1} { + set ADC_NUM_CHANNELS 8 + set ADC_LANE_2_ENABLE 1 + set ADC_LANE_3_ENABLE 1 + set ADC_LANE_4_ENABLE 1 + set ADC_LANE_5_ENABLE 1 + set ADC_LANE_6_ENABLE 1 + set ADC_LANE_7_ENABLE 1 +} elseif {$LTC235X_FAMILY <= 3} { + set ADC_NUM_CHANNELS 4 + set ADC_LANE_2_ENABLE 1 + set ADC_LANE_3_ENABLE 1 + set ADC_LANE_4_ENABLE 0 + set ADC_LANE_5_ENABLE 0 + set ADC_LANE_6_ENABLE 0 + set ADC_LANE_7_ENABLE 0 +} else { + set ADC_NUM_CHANNELS 2 + set ADC_LANE_2_ENABLE 0 + set ADC_LANE_3_ENABLE 0 + set ADC_LANE_4_ENABLE 0 + set ADC_LANE_5_ENABLE 0 + set ADC_LANE_6_ENABLE 0 + set ADC_LANE_7_ENABLE 0 +} + +if {$LTC235X_FAMILY % 2 == 0} { + set ADC_DATA_WIDTH 18 +} else { + set ADC_DATA_WIDTH 16 +} + +# axi_ltc235x + +add_instance axi_ltc235x axi_ltc235x +set_instance_parameter_value axi_ltc235x {ID} {0} +set_instance_parameter_value axi_ltc235x {XILINX_INTEL_N} $xilinx_intel_n +set_instance_parameter_value axi_ltc235x {LVDS_CMOS_N} $LVDS_CMOS_N +set_instance_parameter_value axi_ltc235x {LANE_0_ENABLE} $ADC_LANE_0_ENABLE +set_instance_parameter_value axi_ltc235x {LANE_1_ENABLE} $ADC_LANE_1_ENABLE +set_instance_parameter_value axi_ltc235x {LANE_2_ENABLE} $ADC_LANE_2_ENABLE +set_instance_parameter_value axi_ltc235x {LANE_3_ENABLE} $ADC_LANE_3_ENABLE +set_instance_parameter_value axi_ltc235x {LANE_4_ENABLE} $ADC_LANE_4_ENABLE +set_instance_parameter_value axi_ltc235x {LANE_5_ENABLE} $ADC_LANE_5_ENABLE +set_instance_parameter_value axi_ltc235x {LANE_6_ENABLE} $ADC_LANE_6_ENABLE +set_instance_parameter_value axi_ltc235x {LANE_7_ENABLE} $ADC_LANE_7_ENABLE +set_instance_parameter_value axi_ltc235x {EXTERNAL_CLK} $ADC_EXTERNAL_CLK +set_instance_parameter_value axi_ltc235x {LTC235X_FAMILY} $LTC235X_FAMILY +set_instance_parameter_value axi_ltc235x {NUM_CHANNELS} $ADC_NUM_CHANNELS +set_instance_parameter_value axi_ltc235x {DATA_WIDTH} $ADC_DATA_WIDTH +add_interface axi_ltc235x_device_if conduit end +set_interface_property axi_ltc235x_device_if EXPORT_OF axi_ltc235x.device_if +add_connection sys_clk.clk axi_ltc235x.if_external_clk +add_connection sys_clk.clk axi_ltc235x.s_axi_clock +add_connection sys_clk.clk_reset axi_ltc235x.s_axi_reset + +# pwm gen + +add_instance adc_pwm_gen axi_pwm_gen +set_instance_parameter_value adc_pwm_gen {ID} {0} +set_instance_parameter_value adc_pwm_gen {ASYNC_CLK_EN} {0} +set_instance_parameter_value adc_pwm_gen {N_PWMS} {1} +set_instance_parameter_value adc_pwm_gen {PWM_EXT_SYNC} {0} +set_instance_parameter_value adc_pwm_gen {EXT_ASYNC_SYNC} {0} +set_instance_parameter_value adc_pwm_gen {PULSE_0_WIDTH} {3} +set_instance_parameter_value adc_pwm_gen {PULSE_0_PERIOD} {400} +set_instance_parameter_value adc_pwm_gen {PULSE_0_OFFSET} {0} +add_interface axi_ltc235x_cnv_if conduit end +set_interface_property axi_ltc235x_cnv_if EXPORT_OF adc_pwm_gen.if_pwm_0 +add_connection sys_clk.clk adc_pwm_gen.if_ext_clk +add_connection sys_clk.clk adc_pwm_gen.s_axi_clock +add_connection sys_clk.clk_reset adc_pwm_gen.s_axi_reset + +# pack + +add_instance util_adc_pack util_cpack2 +set_instance_parameter_value util_adc_pack {NUM_OF_CHANNELS} $ADC_NUM_CHANNELS +set_instance_parameter_value util_adc_pack {SAMPLES_PER_CHANNEL} {1} +set_instance_parameter_value util_adc_pack {SAMPLE_DATA_WIDTH} {32} +add_connection sys_clk.clk util_adc_pack.clk +add_connection sys_clk.clk_reset util_adc_pack.reset +for {set i 0} {$i < $ADC_NUM_CHANNELS} {incr i} { + add_connection axi_ltc235x.adc_ch_$i util_adc_pack.adc_ch_$i +} +add_connection util_adc_pack.if_fifo_wr_overflow axi_ltc235x.if_adc_dovf + +# dmac + +add_instance axi_adc_dma axi_dmac +set_instance_parameter_value axi_adc_dma {ID} {0} +if {$ADC_NUM_CHANNELS == 8} { + set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_SRC} {256} +} elseif {$ADC_NUM_CHANNELS == 4} { + set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_SRC} {128} +} else { + set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_SRC} {64} +} +set_instance_parameter_value axi_adc_dma {DMA_DATA_WIDTH_DEST} {64} +set_instance_parameter_value axi_adc_dma {DMA_2D_TRANSFER} {0} +set_instance_parameter_value axi_adc_dma {AXI_SLICE_DEST} {0} +set_instance_parameter_value axi_adc_dma {AXI_SLICE_SRC} {0} +set_instance_parameter_value axi_adc_dma {SYNC_TRANSFER_START} {1} +set_instance_parameter_value axi_adc_dma {CYCLIC} {0} +set_instance_parameter_value axi_adc_dma {DMA_TYPE_DEST} {0} +set_instance_parameter_value axi_adc_dma {DMA_TYPE_SRC} {2} +set_instance_parameter_value axi_adc_dma {FIFO_SIZE} {4} +add_connection sys_clk.clk axi_adc_dma.s_axi_clock +add_connection sys_clk.clk_reset axi_adc_dma.s_axi_reset +add_connection sys_clk.clk axi_adc_dma.m_dest_axi_clock +add_connection sys_clk.clk_reset axi_adc_dma.m_dest_axi_reset +add_connection sys_clk.clk axi_adc_dma.if_fifo_wr_clk +add_connection util_adc_pack.if_packed_fifo_wr_en axi_adc_dma.if_fifo_wr_en +add_connection util_adc_pack.if_packed_fifo_wr_sync axi_adc_dma.if_fifo_wr_sync +add_connection util_adc_pack.if_packed_fifo_wr_data axi_adc_dma.if_fifo_wr_din +add_connection axi_adc_dma.if_fifo_wr_overflow util_adc_pack.if_packed_fifo_wr_overflow + +# interrupts / cpu interrupts + +ad_cpu_interrupt 2 axi_adc_dma.interrupt_sender + +# cpu interconnects / address map + +ad_cpu_interconnect 0x00120000 axi_ltc235x.s_axi +ad_cpu_interconnect 0x00140000 adc_pwm_gen.s_axi +ad_cpu_interconnect 0x00100000 axi_adc_dma.s_axi + +# mem interconnects / dma interconnects + +ad_dma_interconnect axi_adc_dma.m_dest_axi 1