From 666d96f7ca1ecb8fbbfe3c16c82327b57a3efd7f Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Tue, 1 Feb 2022 21:48:06 +0200 Subject: [PATCH] ad_ip_jesd204_tpl_dac: Increase DDS phase DW support Allow upto 32 bit phase data width support. --- .../ad_ip_jesd204_tpl_dac.v | 13 +++++++----- .../ad_ip_jesd204_tpl_dac_channel.v | 13 ++++++------ .../ad_ip_jesd204_tpl_dac_core.v | 18 +++++++++------- .../ad_ip_jesd204_tpl_dac_regmap.v | 21 +++++++++++-------- 4 files changed, 37 insertions(+), 28 deletions(-) diff --git a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v index 10da617601..f7d76b1176 100644 --- a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v +++ b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac.v @@ -40,6 +40,7 @@ module ad_ip_jesd204_tpl_dac #( parameter DDS_TYPE = 1, parameter DDS_CORDIC_DW = 16, parameter DDS_CORDIC_PHASE_DW = 16, + parameter DDS_PHASE_DW = 16, parameter DATAPATH_DISABLE = 0, parameter IQCORRECTION_DISABLE = 1, parameter EXT_SYNC = 0, @@ -108,11 +109,11 @@ module ad_ip_jesd204_tpl_dac #( wire dac_dds_format; wire [NUM_CHANNELS*16-1:0] dac_dds_scale_0_s; - wire [NUM_CHANNELS*16-1:0] dac_dds_init_0_s; - wire [NUM_CHANNELS*16-1:0] dac_dds_incr_0_s; wire [NUM_CHANNELS*16-1:0] dac_dds_scale_1_s; - wire [NUM_CHANNELS*16-1:0] dac_dds_init_1_s; - wire [NUM_CHANNELS*16-1:0] dac_dds_incr_1_s; + wire [NUM_CHANNELS*DDS_PHASE_DW-1:0] dac_dds_init_0_s; + wire [NUM_CHANNELS*DDS_PHASE_DW-1:0] dac_dds_incr_0_s; + wire [NUM_CHANNELS*DDS_PHASE_DW-1:0] dac_dds_init_1_s; + wire [NUM_CHANNELS*DDS_PHASE_DW-1:0] dac_dds_incr_1_s; wire [NUM_CHANNELS*16-1:0] dac_pat_data_0_s; wire [NUM_CHANNELS*16-1:0] dac_pat_data_1_s; wire [NUM_CHANNELS*4-1:0] dac_data_sel_s; @@ -138,7 +139,8 @@ module ad_ip_jesd204_tpl_dac #( .NUM_CHANNELS (NUM_CHANNELS), .DATA_PATH_WIDTH (DATA_PATH_WIDTH), .PADDING_TO_MSB_LSB_N (PADDING_TO_MSB_LSB_N), - .NUM_PROFILES(1) + .NUM_PROFILES(1), + .DDS_PHASE_DW (DDS_PHASE_DW) ) i_regmap ( .s_axi_aclk (s_axi_aclk), .s_axi_aresetn (s_axi_aresetn), @@ -215,6 +217,7 @@ module ad_ip_jesd204_tpl_dac #( .DDS_TYPE (DDS_TYPE), .DDS_CORDIC_DW (DDS_CORDIC_DW), .DDS_CORDIC_PHASE_DW (DDS_CORDIC_PHASE_DW), + .DDS_PHASE_DW (DDS_PHASE_DW), .EXT_SYNC (EXT_SYNC) ) i_core ( .clk (link_clk), diff --git a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_channel.v b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_channel.v index cc03c453d5..ccd8a518e6 100644 --- a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_channel.v +++ b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_channel.v @@ -32,6 +32,7 @@ module ad_ip_jesd204_tpl_dac_channel #( parameter DDS_TYPE = 1, parameter DDS_CORDIC_DW = 16, parameter DDS_CORDIC_PHASE_DW = 16, + parameter DDS_PHASE_DW = 16, parameter Q_OR_I_N = 0 ) ( // dac interface @@ -55,14 +56,14 @@ module ad_ip_jesd204_tpl_dac_channel #( input dac_mask_enable, input [15:0] dac_dds_scale_0, - input [15:0] dac_dds_init_0, - input [15:0] dac_dds_incr_0, input [15:0] dac_dds_scale_1, - input [15:0] dac_dds_init_1, - input [15:0] dac_dds_incr_1, + input [DDS_PHASE_DW-1:0] dac_dds_init_0, + input [DDS_PHASE_DW-1:0] dac_dds_incr_0, + input [DDS_PHASE_DW-1:0] dac_dds_init_1, + input [DDS_PHASE_DW-1:0] dac_dds_incr_1, input [15:0] dac_pat_data_0, - input [15:0] dac_pat_data_1, + input [15:0] dac_pat_data_1, input dac_iqcor_enb, input [15:0] dac_iqcor_coeff_1, @@ -147,7 +148,7 @@ module ad_ip_jesd204_tpl_dac_channel #( ad_dds #( .DISABLE (DATAPATH_DISABLE), .DDS_DW (CONVERTER_RESOLUTION), - .PHASE_DW (16), + .PHASE_DW (DDS_PHASE_DW), .DDS_TYPE (DDS_TYPE), .CORDIC_DW (DDS_CORDIC_DW), .CORDIC_PHASE_DW (DDS_CORDIC_PHASE_DW), diff --git a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v index 9101760854..c845395229 100644 --- a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v +++ b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_core.v @@ -38,6 +38,7 @@ module ad_ip_jesd204_tpl_dac_core #( parameter DDS_TYPE = 1, parameter DDS_CORDIC_DW = 16, parameter DDS_CORDIC_PHASE_DW = 16, + parameter DDS_PHASE_DW = 16, parameter EXT_SYNC = 0 ) ( // dac interface @@ -66,11 +67,11 @@ module ad_ip_jesd204_tpl_dac_core #( input [NUM_CHANNELS-1:0] dac_mask_enable, input [NUM_CHANNELS*16-1:0] dac_dds_scale_0, - input [NUM_CHANNELS*16-1:0] dac_dds_init_0, - input [NUM_CHANNELS*16-1:0] dac_dds_incr_0, input [NUM_CHANNELS*16-1:0] dac_dds_scale_1, - input [NUM_CHANNELS*16-1:0] dac_dds_init_1, - input [NUM_CHANNELS*16-1:0] dac_dds_incr_1, + input [NUM_CHANNELS*DDS_PHASE_DW-1:0] dac_dds_init_0, + input [NUM_CHANNELS*DDS_PHASE_DW-1:0] dac_dds_incr_0, + input [NUM_CHANNELS*DDS_PHASE_DW-1:0] dac_dds_init_1, + input [NUM_CHANNELS*DDS_PHASE_DW-1:0] dac_dds_incr_1, input [NUM_CHANNELS*16-1:0] dac_pat_data_0, input [NUM_CHANNELS*16-1:0] dac_pat_data_1, @@ -188,6 +189,7 @@ module ad_ip_jesd204_tpl_dac_core #( .DDS_TYPE (DDS_TYPE), .DDS_CORDIC_DW (DDS_CORDIC_DW), .DDS_CORDIC_PHASE_DW (DDS_CORDIC_PHASE_DW), + .DDS_PHASE_DW (DDS_PHASE_DW), .IQCORRECTION_DISABLE(IQCORRECTION_DISABLE), .Q_OR_I_N(i%2) ) i_channel ( @@ -206,11 +208,11 @@ module ad_ip_jesd204_tpl_dac_core #( .dac_mask_enable (dac_mask_enable[i]), .dac_dds_scale_0 (dac_dds_scale_0[16*i+:16]), - .dac_dds_init_0 (dac_dds_init_0[16*i+:16]), - .dac_dds_incr_0 (dac_dds_incr_0[16*i+:16]), .dac_dds_scale_1 (dac_dds_scale_1[16*i+:16]), - .dac_dds_init_1 (dac_dds_init_1[16*i+:16]), - .dac_dds_incr_1 (dac_dds_incr_1[16*i+:16]), + .dac_dds_init_0 (dac_dds_init_0[DDS_PHASE_DW*i+:DDS_PHASE_DW]), + .dac_dds_incr_0 (dac_dds_incr_0[DDS_PHASE_DW*i+:DDS_PHASE_DW]), + .dac_dds_init_1 (dac_dds_init_1[DDS_PHASE_DW*i+:DDS_PHASE_DW]), + .dac_dds_incr_1 (dac_dds_incr_1[DDS_PHASE_DW*i+:DDS_PHASE_DW]), .dac_pat_data_0 (dac_pat_data_0[16*i+:16]), .dac_pat_data_1 (dac_pat_data_1[16*i+:16]), diff --git a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v index 5b3bde5c63..d94515f9ca 100644 --- a/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v +++ b/library/jesd204/ad_ip_jesd204_tpl_dac/ad_ip_jesd204_tpl_dac_regmap.v @@ -35,7 +35,8 @@ module ad_ip_jesd204_tpl_dac_regmap #( parameter NUM_CHANNELS = 2, parameter DATA_PATH_WIDTH = 16, parameter PADDING_TO_MSB_LSB_N = 0, - parameter NUM_PROFILES = 1 // Number of supported JESD profiles + parameter NUM_PROFILES = 1, // Number of supported JESD profiles + parameter DDS_PHASE_DW = 16 ) ( input s_axi_aclk, input s_axi_aresetn, @@ -78,11 +79,11 @@ module ad_ip_jesd204_tpl_dac_regmap #( output dac_dds_format, output [NUM_CHANNELS*16-1:0] dac_dds_scale_0, - output [NUM_CHANNELS*16-1:0] dac_dds_init_0, - output [NUM_CHANNELS*16-1:0] dac_dds_incr_0, output [NUM_CHANNELS*16-1:0] dac_dds_scale_1, - output [NUM_CHANNELS*16-1:0] dac_dds_init_1, - output [NUM_CHANNELS*16-1:0] dac_dds_incr_1, + output [NUM_CHANNELS*DDS_PHASE_DW-1:0] dac_dds_init_0, + output [NUM_CHANNELS*DDS_PHASE_DW-1:0] dac_dds_incr_0, + output [NUM_CHANNELS*DDS_PHASE_DW-1:0] dac_dds_init_1, + output [NUM_CHANNELS*DDS_PHASE_DW-1:0] dac_dds_incr_1, output [NUM_CHANNELS*16-1:0] dac_pat_data_0, output [NUM_CHANNELS*16-1:0] dac_pat_data_1, @@ -259,6 +260,8 @@ module ad_ip_jesd204_tpl_dac_regmap #( .COMMON_ID(6'h1 + i/16), .CHANNEL_ID (i % 16), .CHANNEL_NUMBER (i), + .DDS_PHASE_DW (DDS_PHASE_DW), + .DDS_EXT_DW (DDS_PHASE_DW > 16 ? DDS_PHASE_DW-16 : 0), .USERPORTS_DISABLE (1), .IQCORRECTION_DISABLE (IQCORRECTION_DISABLE), .XBAR_ENABLE (XBAR_ENABLE) @@ -266,11 +269,11 @@ module ad_ip_jesd204_tpl_dac_regmap #( .dac_clk (link_clk), .dac_rst (dac_rst), .dac_dds_scale_1 (dac_dds_scale_0[16*i+:16]), - .dac_dds_init_1 (dac_dds_init_0[16*i+:16]), - .dac_dds_incr_1 (dac_dds_incr_0[16*i+:16]), + .dac_dds_init_1 (dac_dds_init_0[DDS_PHASE_DW*i+:DDS_PHASE_DW]), + .dac_dds_incr_1 (dac_dds_incr_0[DDS_PHASE_DW*i+:DDS_PHASE_DW]), .dac_dds_scale_2 (dac_dds_scale_1[16*i+:16]), - .dac_dds_init_2 (dac_dds_init_1[16*i+:16]), - .dac_dds_incr_2 (dac_dds_incr_1[16*i+:16]), + .dac_dds_init_2 (dac_dds_init_1[DDS_PHASE_DW*i+:DDS_PHASE_DW]), + .dac_dds_incr_2 (dac_dds_incr_1[DDS_PHASE_DW*i+:DDS_PHASE_DW]), .dac_pat_data_1 (dac_pat_data_0[16*i+:16]), .dac_pat_data_2 (dac_pat_data_1[16*i+:16]), .dac_data_sel (dac_data_sel[4*i+:4]),