diff --git a/library/common/ad_mem.v b/library/common/ad_mem.v
index caf4609432..7150cbe39f 100644
--- a/library/common/ad_mem.v
+++ b/library/common/ad_mem.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
diff --git a/library/data_offload/data_offload.v b/library/data_offload/data_offload.v
index ca821ce704..4a091e60e0 100644
--- a/library/data_offload/data_offload.v
+++ b/library/data_offload/data_offload.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
diff --git a/library/util_axis_fifo_asym/util_axis_fifo_asym.v b/library/util_axis_fifo_asym/util_axis_fifo_asym.v
index a2aa6c74e8..b6e548cabb 100644
--- a/library/util_axis_fifo_asym/util_axis_fifo_asym.v
+++ b/library/util_axis_fifo_asym/util_axis_fifo_asym.v
@@ -1,6 +1,6 @@
 // ***************************************************************************
 // ***************************************************************************
-// Copyright (C) 2021-2023 Analog Devices, Inc. All rights reserved.
+// Copyright (C) 2021-2024 Analog Devices, Inc. All rights reserved.
 //
 // In this HDL repository, there are many different and unique modules, consisting
 // of various HDL (Verilog or VHDL) components. The individual modules are
diff --git a/library/util_axis_fifo_asym/util_axis_fifo_asym_ip.tcl b/library/util_axis_fifo_asym/util_axis_fifo_asym_ip.tcl
index 499a8cd93b..db33723d5a 100644
--- a/library/util_axis_fifo_asym/util_axis_fifo_asym_ip.tcl
+++ b/library/util_axis_fifo_asym/util_axis_fifo_asym_ip.tcl
@@ -1,5 +1,5 @@
 ###############################################################################
-## Copyright (C) 2015-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2015-2024 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################