diff --git a/projects/ad469x_fmc/index.html b/projects/ad469x_fmc/index.html index 2857c87c12..9ed8f7a6c0 100644 --- a/projects/ad469x_fmc/index.html +++ b/projects/ad469x_fmc/index.html @@ -107,6 +107,7 @@
The SPI_4WIRE configuration parameter defines if CNV signal is linked to PWM or
+to SPI_CS to enable interfacing with a single 4-wire SPI port. By default it is
+set to 0. Depending on the required pin functionality, some hardware
+modifications need to be done on the board and/or make
command:
In case we link CNV signal to PWM:
+make SPI_4WIRE=0
+
In case we link CNV signal to SPI_CS:
+make SPI_4WIRE=1
+
The addresses are dependent on the architecture of the FPGA, having an offset @@ -461,9 +477,17 @@
32
86
gpio[33]
IN
33
87
BSY_ALT_GP0 pin can be configured to function as a general-purpose input/output +(GPIO), the threshold detection alert indicator, the busy indicator, or the +second serial data output in dual-sdo MODE
1user@analog:~$ cd hdl/projects/ad469x_fmc/zed
-2user@analog:~/hdl/projects/ad469x_fmc/zed$ make
+2user@analog:~/hdl/projects/ad469x_fmc/zed$ make SPI_4WIRE=0
The result of the build, if parameters were used, will be in a folder named +by the configuration used:
+if the following command was run
+SPI_4WIRE=0
then the folder name will be:
+SPI4WIRE0
A more comprehensive build guide can be found in the Build a HDL project user guide.