From 320df5f22b62fe97cfe9fdd7155f44e5507c07f9 Mon Sep 17 00:00:00 2001 From: Jorge Marques Date: Thu, 21 Nov 2024 16:30:27 -0300 Subject: [PATCH] projects: Update addr/irq with coraz7s axi_iic_ard The axi_iic_ard is generally used to read the EVB EEPROM with Arduino uno form factor. IIC Changes: Project Old New IIC Subordinate ad4170_asdz ps-12, 44a4 ps-11, 4160 24AA32A ad57xx_ardz PS7 IIC ps-11, 4160 24AA32A pulsar_adc none ps-11, 4160 - ad719x_asdz none ps-11, 4160 - cn0579 ps-12, 44a4 ps-11, 4160 AD5696 cn0540 ps-12, 44a4 ps-11, 4160 LTC2606 cn0561 PS7 IIC ps-11, 4160 M24C02 IRQ index changes: ad4170_asdz * $hier_spi_engine 11 -> 12 ad57xx_ardz * ad57xx_dma 12 -> 13 * $hier_spi_engine 11 -> 12 cn0579 * cn0579_dma 13 -> 12 * axi_iic_ard 12 -> 11 cn0540 * $hier_spi_engine 11 -> 12 Signed-off-by: Jorge Marques --- projects/ad4170_asdz/common/ad4170_asdz_bd.tcl | 8 +------- projects/ad4170_asdz/coraz7s/system_constr.xdc | 3 --- projects/ad4170_asdz/coraz7s/system_top.v | 10 +++++----- projects/ad57xx_ardz/common/ad57xx_ardz_bd.tcl | 4 ++-- projects/ad57xx_ardz/coraz7s/system_bd.tcl | 8 -------- projects/ad57xx_ardz/coraz7s/system_constr.xdc | 3 --- projects/ad57xx_ardz/coraz7s/system_top.v | 9 +++++---- projects/ad719x_asdz/coraz7s/system_top_pmod.v | 6 ++++++ projects/cn0540/common/cn0540_bd.tcl | 8 +------- projects/cn0540/coraz7s/system_constr.xdc | 3 --- projects/cn0540/coraz7s/system_top.v | 10 +++++----- projects/cn0561/coraz7s/system_bd.tcl | 10 +--------- projects/cn0561/coraz7s/system_constr.xdc | 5 +---- projects/cn0561/coraz7s/system_top.v | 10 +++++----- projects/cn0579/common/cn0579_bd.tcl | 10 +--------- projects/cn0579/coraz7s/system_constr.xdc | 4 +--- projects/cn0579/coraz7s/system_top.v | 18 ++++++++---------- projects/pulsar_adc/coraz7s/system_top.v | 7 ++++++- 18 files changed, 48 insertions(+), 88 deletions(-) diff --git a/projects/ad4170_asdz/common/ad4170_asdz_bd.tcl b/projects/ad4170_asdz/common/ad4170_asdz_bd.tcl index ed2c72dab76..a89e1a34230 100644 --- a/projects/ad4170_asdz/common/ad4170_asdz_bd.tcl +++ b/projects/ad4170_asdz/common/ad4170_asdz_bd.tcl @@ -4,7 +4,6 @@ ############################################################################### create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 adc_spi -create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_ad4170 create_bd_port -dir I adc_data_ready @@ -22,9 +21,6 @@ set hier_spi_engine spi_ad4170 spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk -ad_ip_instance axi_iic axi_ad4170_iic -ad_connect iic_ad4170 axi_ad4170_iic/iic - # Generate a 80MHz spi_clk for the SPI Engine (targeted SCLK is 20MHz) ad_ip_instance axi_clkgen spi_clkgen @@ -76,14 +72,12 @@ ad_connect sys_cpu_resetn axi_ad4170_dma/m_dest_axi_aresetn ad_cpu_interconnect 0x44a00000 $hier_spi_engine/${hier_spi_engine}_axi_regmap ad_cpu_interconnect 0x44a30000 axi_ad4170_dma -ad_cpu_interconnect 0x44a40000 axi_ad4170_iic ad_cpu_interconnect 0x44a70000 spi_clkgen # interrupts ad_cpu_interrupt "ps-13" "mb-13" axi_ad4170_dma/irq -ad_cpu_interrupt "ps-12" "mb-12" axi_ad4170_iic/iic2intc_irpt -ad_cpu_interrupt "ps-11" "mb-11" $hier_spi_engine/irq +ad_cpu_interrupt "ps-12" "mb-12" $hier_spi_engine/irq # memory interconnects diff --git a/projects/ad4170_asdz/coraz7s/system_constr.xdc b/projects/ad4170_asdz/coraz7s/system_constr.xdc index 8860cb84f40..fa34e727ae7 100644 --- a/projects/ad4170_asdz/coraz7s/system_constr.xdc +++ b/projects/ad4170_asdz/coraz7s/system_constr.xdc @@ -15,9 +15,6 @@ set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS33} set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports ad4170_dig_aux[1]] ; ## CK_IO7 set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports ad4170_dig_aux[0]] ; ## CK_IO2 -set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports iic_eeprom_scl] ; ## CK_SCL -set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports iic_eeprom_sda] ; ## CK_SDA - # rename auto-generated clock for SPI Engine to spi_clk - 40MHz create_generated_clock -name spi_clk -source [get_pins -filter name=~*CLKIN1 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]] -master_clock clk_fpga_0 [get_pins -filter name=~*CLKOUT0 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]] diff --git a/projects/ad4170_asdz/coraz7s/system_top.v b/projects/ad4170_asdz/coraz7s/system_top.v index deb9876c820..97ab1a6f908 100644 --- a/projects/ad4170_asdz/coraz7s/system_top.v +++ b/projects/ad4170_asdz/coraz7s/system_top.v @@ -63,8 +63,8 @@ module system_top ( inout [1:0] btn, inout [5:0] led, - inout iic_eeprom_scl, - inout iic_eeprom_sda, + inout iic_ard_scl, + inout iic_ard_sda, // ad4170 input ad4170_spi_miso, @@ -141,8 +141,6 @@ module system_top ( .adc_spi_cs (ad4170_spi_csn), .adc_spi_sclk (ad4170_spi_sclk), .adc_data_ready (ad4170_dig_aux[0]), - .iic_ad4170_scl_io (iic_eeprom_scl), - .iic_ad4170_sda_io (iic_eeprom_sda), .spi0_clk_i (1'b0), .spi0_clk_o (), .spi0_csn_0_o (), @@ -160,6 +158,8 @@ module system_top ( .spi1_csn_i (1'b1), .spi1_sdi_i (1'b0), .spi1_sdo_i (1'b0), - .spi1_sdo_o()); + .spi1_sdo_o (), + .iic_ard_scl_io (iic_ard_scl), + .iic_ard_sda_io (iic_ard_sda)); endmodule diff --git a/projects/ad57xx_ardz/common/ad57xx_ardz_bd.tcl b/projects/ad57xx_ardz/common/ad57xx_ardz_bd.tcl index 4b0303bd340..35330a82881 100644 --- a/projects/ad57xx_ardz/common/ad57xx_ardz_bd.tcl +++ b/projects/ad57xx_ardz/common/ad57xx_ardz_bd.tcl @@ -71,8 +71,8 @@ ad_cpu_interconnect 0x44b10000 axi_ad57xx_clkgen # interrupts -ad_cpu_interrupt "ps-12" "mb-12" ad57xx_dma/irq -ad_cpu_interrupt "ps-11" "mb-11" $hier_spi_engine/irq +ad_cpu_interrupt "ps-13" "mb-13" ad57xx_dma/irq +ad_cpu_interrupt "ps-12" "mb-12" $hier_spi_engine/irq # memory interconnects diff --git a/projects/ad57xx_ardz/coraz7s/system_bd.tcl b/projects/ad57xx_ardz/coraz7s/system_bd.tcl index 0ae01ab4e8b..7b0ac934e5c 100644 --- a/projects/ad57xx_ardz/coraz7s/system_bd.tcl +++ b/projects/ad57xx_ardz/coraz7s/system_bd.tcl @@ -13,12 +13,4 @@ ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 sysid_gen_sys_init_file -#the eval board requires an extra i2c channel for the coraz7s project -create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_0_io - -ad_ip_parameter sys_ps7 CONFIG.PCW_I2C0_PERIPHERAL_ENABLE 1 -ad_ip_parameter sys_ps7 CONFIG.PCW_I2C0_I2C0_IO EMIO - -ad_connect iic_0_io sys_ps7/IIC_0 - source ../common/ad57xx_ardz_bd.tcl diff --git a/projects/ad57xx_ardz/coraz7s/system_constr.xdc b/projects/ad57xx_ardz/coraz7s/system_constr.xdc index 06e500b4397..a2aa8266501 100644 --- a/projects/ad57xx_ardz/coraz7s/system_constr.xdc +++ b/projects/ad57xx_ardz/coraz7s/system_constr.xdc @@ -5,9 +5,6 @@ # ad57xx interface -set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports ad57xx_ardz_scl] -set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports ad57xx_ardz_sda] - set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports ad57xx_ardz_spi_mosi] set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports ad57xx_ardz_spi_miso] set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33 IOB TRUE} [get_ports ad57xx_ardz_spi_sclk] diff --git a/projects/ad57xx_ardz/coraz7s/system_top.v b/projects/ad57xx_ardz/coraz7s/system_top.v index 32a3273bcf5..107cd1c0600 100644 --- a/projects/ad57xx_ardz/coraz7s/system_top.v +++ b/projects/ad57xx_ardz/coraz7s/system_top.v @@ -63,9 +63,10 @@ module system_top ( inout [1:0] btn, inout [5:0] led, + inout iic_ard_scl, + inout iic_ard_sda, + // ad57xx ardz - inout ad57xx_ardz_scl, - inout ad57xx_ardz_sda, input ad57xx_ardz_spi_miso, output ad57xx_ardz_spi_mosi, output ad57xx_ardz_spi_sclk, @@ -137,8 +138,6 @@ module system_top ( .gpio_i (gpio_i), .gpio_o (gpio_o), .gpio_t (gpio_t), - .iic_0_io_scl_io (ad57xx_ardz_scl), - .iic_0_io_sda_io (ad57xx_ardz_sda), .spi0_clk_i (1'b0), .spi0_clk_o (), .spi0_csn_0_o (), @@ -157,6 +156,8 @@ module system_top ( .spi1_sdi_i (1'b0), .spi1_sdo_i (1'b0), .spi1_sdo_o (), + .iic_ard_scl_io (iic_ard_scl), + .iic_ard_sda_io (iic_ard_sda), .ad57xx_spi_sdo (ad57xx_ardz_spi_mosi), .ad57xx_spi_sdo_t (), .ad57xx_spi_sdi (ad57xx_ardz_spi_miso), diff --git a/projects/ad719x_asdz/coraz7s/system_top_pmod.v b/projects/ad719x_asdz/coraz7s/system_top_pmod.v index bc6d878783d..c8f62044c60 100644 --- a/projects/ad719x_asdz/coraz7s/system_top_pmod.v +++ b/projects/ad719x_asdz/coraz7s/system_top_pmod.v @@ -63,6 +63,9 @@ module system_top ( inout [ 1:0] btn, inout [ 5:0] led, + inout iic_ard_scl, + inout iic_ard_sda, + // ad7190 spi pins output adc_spi_sclk, @@ -142,6 +145,9 @@ module system_top ( .spi0_sdo_i (1'b0), .spi0_sdo_o (adc_spi_mosi), + .iic_ard_scl_io (iic_ard_scl), + .iic_ard_sda_io (iic_ard_sda), + .spi1_clk_i (1'b0), .spi1_clk_o (), .spi1_csn_0_o (), diff --git a/projects/cn0540/common/cn0540_bd.tcl b/projects/cn0540/common/cn0540_bd.tcl index 3d056c604bd..55f6d2c18fc 100755 --- a/projects/cn0540/common/cn0540_bd.tcl +++ b/projects/cn0540/common/cn0540_bd.tcl @@ -4,7 +4,6 @@ ############################################################################### create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_engine_rtl:1.0 adc_spi -create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_cn0540 create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 xadc_mux create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 xadc_vaux1 create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_analog_io_rtl:1.0 xadc_vaux9 @@ -29,9 +28,6 @@ set hier_spi_engine spi_cn0540 spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk -ad_ip_instance axi_iic axi_iic_cn0540 -ad_connect iic_cn0540 axi_iic_cn0540/iic - # Generate a 80MHz spi_clk for the SPI Engine (targeted SCLK is 20MHz) ad_ip_instance axi_clkgen spi_clkgen @@ -100,15 +96,13 @@ ad_connect xadc_in/Vaux15 xadc_vaux15 ad_cpu_interconnect 0x44a00000 $hier_spi_engine/${hier_spi_engine}_axi_regmap ad_cpu_interconnect 0x44a30000 axi_cn0540_dma -ad_cpu_interconnect 0x44a40000 axi_iic_cn0540 ad_cpu_interconnect 0x44a50000 xadc_in ad_cpu_interconnect 0x44a70000 spi_clkgen # interrupts ad_cpu_interrupt "ps-13" "mb-13" axi_cn0540_dma/irq -ad_cpu_interrupt "ps-12" "mb-12" axi_iic_cn0540/iic2intc_irpt -ad_cpu_interrupt "ps-11" "mb-11" $hier_spi_engine/irq +ad_cpu_interrupt "ps-12" "mb-12" $hier_spi_engine/irq # memory interconnects diff --git a/projects/cn0540/coraz7s/system_constr.xdc b/projects/cn0540/coraz7s/system_constr.xdc index 0bd2f4dc09a..4b314f4a7a2 100755 --- a/projects/cn0540/coraz7s/system_constr.xdc +++ b/projects/cn0540/coraz7s/system_constr.xdc @@ -25,9 +25,6 @@ set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS33} set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS33} [get_ports cn0540_sync_in] ; ## CK_IO6 set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS33} [get_ports cn0540_drdy] ; ## CK_IO2 -set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports cn0540_scl] ; ## CK_SCL -set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports cn0540_sda] ; ## CK_SDA - # rename auto-generated clock for SPI Engine to spi_clk - 80MHz create_generated_clock -name spi_clk -source [get_pins -filter name=~*CLKIN1 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]] -master_clock clk_fpga_0 [get_pins -filter name=~*CLKOUT0 -of [get_cells -hier -filter name=~*spi_clkgen*i_mmcm]] diff --git a/projects/cn0540/coraz7s/system_top.v b/projects/cn0540/coraz7s/system_top.v index 6b319e4af88..f84ea84a987 100755 --- a/projects/cn0540/coraz7s/system_top.v +++ b/projects/cn0540/coraz7s/system_top.v @@ -63,6 +63,9 @@ module system_top ( inout [1:0] btn, inout [5:0] led, + inout iic_ard_scl, + inout iic_ard_sda, + input cn0540_xadc_mux_p, input cn0540_xadc_mux_n, input cn0540_ck_an0_p, @@ -78,9 +81,6 @@ module system_top ( input cn0540_ck_an5_p, input cn0540_ck_an5_n, - inout cn0540_scl, - inout cn0540_sda, - inout cn0540_shutdown, inout cn0540_reset_adc, inout cn0540_csb_aux, @@ -173,8 +173,6 @@ module system_top ( .adc_spi_cs (cn0540_spi_cs), .adc_spi_sclk (cn0540_spi_sclk), .adc_data_ready (cn0540_drdy), - .iic_cn0540_scl_io (cn0540_scl), - .iic_cn0540_sda_io (cn0540_sda), .spi0_clk_i (1'b0), .spi0_clk_o (), .spi0_csn_0_o (), @@ -193,6 +191,8 @@ module system_top ( .spi1_sdi_i (1'b0), .spi1_sdo_i (1'b0), .spi1_sdo_o(), + .iic_ard_scl_io (iic_ard_scl), + .iic_ard_sda_io (iic_ard_sda), .xadc_mux_v_p (cn0540_xadc_mux_p), .xadc_mux_v_n (cn0540_xadc_mux_n), .xadc_vaux1_v_p (cn0540_ck_an0_p), diff --git a/projects/cn0561/coraz7s/system_bd.tcl b/projects/cn0561/coraz7s/system_bd.tcl index f1b256fb832..5eee521f96c 100644 --- a/projects/cn0561/coraz7s/system_bd.tcl +++ b/projects/cn0561/coraz7s/system_bd.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -18,12 +18,4 @@ ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 sysid_gen_sys_init_file -#the eval board requires an extra i2c channel for the coraz7s project -create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_0_io - -ad_ip_parameter sys_ps7 CONFIG.PCW_I2C0_PERIPHERAL_ENABLE 1 -ad_ip_parameter sys_ps7 CONFIG.PCW_I2C0_I2C0_IO EMIO - -ad_connect iic_0_io sys_ps7/IIC_0 - source ../common/cn0561_bd.tcl diff --git a/projects/cn0561/coraz7s/system_constr.xdc b/projects/cn0561/coraz7s/system_constr.xdc index f7c4b71f36e..4afe0570025 100644 --- a/projects/cn0561/coraz7s/system_constr.xdc +++ b/projects/cn0561/coraz7s/system_constr.xdc @@ -1,11 +1,8 @@ ############################################################################### -## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### -set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports iic_scl] -set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports iic_sda] - set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33} [get_ports cn0561_spi_sdi] ; ## FMC_LPC_LA03_P set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33} [get_ports cn0561_spi_sdo] ; ## FMC_LPC_LA04_N set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33} [get_ports cn0561_spi_sclk] ; ## FMC_LPC_LA01_P_CC diff --git a/projects/cn0561/coraz7s/system_top.v b/projects/cn0561/coraz7s/system_top.v index 1e1e26fa571..ef27cce4faa 100644 --- a/projects/cn0561/coraz7s/system_top.v +++ b/projects/cn0561/coraz7s/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -63,8 +63,8 @@ module system_top ( inout [1:0] btn, inout [5:0] led, - inout iic_scl, - inout iic_sda, + inout iic_ard_scl, + inout iic_ard_sda, // cn0561 SPI configuration interface @@ -142,8 +142,8 @@ module system_top ( .gpio_i (gpio_i), .gpio_o (gpio_o), .gpio_t (gpio_t), - .iic_0_io_scl_io (iic_scl), - .iic_0_io_sda_io (iic_sda), + .iic_ard_scl_io (iic_ard_scl), + .iic_ard_sda_io (iic_ard_sda), .spi0_clk_i (cn0561_spi_sclk), .spi0_clk_o (cn0561_spi_sclk), .spi0_csn_0_o (cn0561_spi_cs), diff --git a/projects/cn0579/common/cn0579_bd.tcl b/projects/cn0579/common/cn0579_bd.tcl index 5b0f91ee51f..35e5f362142 100644 --- a/projects/cn0579/common/cn0579_bd.tcl +++ b/projects/cn0579/common/cn0579_bd.tcl @@ -3,18 +3,12 @@ ### SPDX short identifier: ADIBSD ############################################################################### -create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 iic_dac # ad7768-4 interface create_bd_port -dir I clk_in create_bd_port -dir I ready_in create_bd_port -dir I -from 7 -to 0 data_in -#dac iic - -ad_ip_instance axi_iic axi_iic_dac -ad_connect iic_dac axi_iic_dac/iic - # adc(cn0579-dma) ad_ip_instance axi_dmac cn0579_dma @@ -62,14 +56,12 @@ ad_connect cn0579_dma/sync cn0579_adc_pack/packed_sync # interrupts -ad_cpu_interrupt "ps-13" "mb-13" cn0579_dma/irq -ad_cpu_interrupt "ps-12" "mb-12" axi_iic_dac/iic2intc_irpt +ad_cpu_interrupt "ps-12" "mb-12" cn0579_dma/irq # cpu / memory interconnects ad_cpu_interconnect 0x44a00000 axi_ad77684_adc ad_cpu_interconnect 0x44a30000 cn0579_dma -ad_cpu_interconnect 0x44a40000 axi_iic_dac ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1 ad_mem_hp1_interconnect $sys_cpu_clk cn0579_dma/m_dest_axi diff --git a/projects/cn0579/coraz7s/system_constr.xdc b/projects/cn0579/coraz7s/system_constr.xdc index 6b70368d539..23f14114843 100644 --- a/projects/cn0579/coraz7s/system_constr.xdc +++ b/projects/cn0579/coraz7s/system_constr.xdc @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -18,8 +18,6 @@ set_property -dict {PACKAGE_PIN K18 IOSTANDARD LVCMOS33} [get_ports spi_mosi ]; ## P12.7 IO11 set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS33} [get_ports spi_miso ]; ## P12.6 IO12 set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVCMOS33} [get_ports spi_clk ]; ## P12.5 IO13 - set_property -dict {PACKAGE_PIN P16 IOSTANDARD LVCMOS33} [get_ports dac_i2c_scl]; ## P12.1 CK_SCL - set_property -dict {PACKAGE_PIN P15 IOSTANDARD LVCMOS33} [get_ports dac_i2c_sda]; ## P12.2 CK_SDA set input_clock_period 30.51; # Period of input clock fMAX_DCLK=32.768MHz set hold_time 8.5; diff --git a/projects/cn0579/coraz7s/system_top.v b/projects/cn0579/coraz7s/system_top.v index a9a758e6b67..1a5c62e1ed6 100644 --- a/projects/cn0579/coraz7s/system_top.v +++ b/projects/cn0579/coraz7s/system_top.v @@ -1,6 +1,6 @@ // *************************************************************************** // *************************************************************************** -// Copyright (C) 2023 Analog Devices, Inc. All rights reserved. +// Copyright (C) 2023-2024 Analog Devices, Inc. All rights reserved. // // In this HDL repository, there are many different and unique modules, consisting // of various HDL (Verilog or VHDL) components. The individual modules are @@ -62,6 +62,9 @@ module system_top ( inout [ 1:0] btn, inout [ 5:0] led, + inout iic_ard_scl, + inout iic_ard_sda, + input clk_in, input ready_in, input [ 3:0] data_in, @@ -71,12 +74,7 @@ module system_top ( output spi_mosi, input spi_miso, output shutdown_n, - output reset_n, - - // dac i2c - - inout dac_i2c_scl, - inout dac_i2c_sda + output reset_n ); // internal signals @@ -112,8 +110,6 @@ module system_top ( .clk_in (clk_in), .ready_in (ready_in), .data_in (data_in), - .iic_dac_scl_io (dac_i2c_scl), - .iic_dac_sda_io (dac_i2c_sda), .ddr_addr (ddr_addr), .ddr_ba (ddr_ba), .ddr_cas_n (ddr_cas_n), @@ -155,6 +151,8 @@ module system_top ( .spi1_csn_i (1'b1), .spi1_sdi_i (1'b0), .spi1_sdo_i (1'b0), - .spi1_sdo_o ()); + .spi1_sdo_o (), + .iic_ard_scl_io (iic_ard_scl), + .iic_ard_sda_io (iic_ard_sda)); endmodule diff --git a/projects/pulsar_adc/coraz7s/system_top.v b/projects/pulsar_adc/coraz7s/system_top.v index 7c265378272..e4d33cb7bf7 100644 --- a/projects/pulsar_adc/coraz7s/system_top.v +++ b/projects/pulsar_adc/coraz7s/system_top.v @@ -67,7 +67,10 @@ module system_top ( output pulsar_adc_spi_pd, inout [ 1:0] btn, - inout [ 5:0] led + inout [ 5:0] led, + + inout iic_ard_scl, + inout iic_ard_sda ); // internal signals @@ -148,6 +151,8 @@ module system_top ( .spi1_sdi_i (1'b0), .spi1_sdo_i (1'b0), .spi1_sdo_o (), + .iic_ard_scl_io (iic_ard_scl), + .iic_ard_sda_io (iic_ard_sda), .pulsar_adc_spi_cs(pulsar_adc_spi_cs), .pulsar_adc_spi_sclk(pulsar_adc_spi_sclk), .pulsar_adc_spi_sdi(pulsar_adc_spi_sdi),