From 1a2ed6c23e61ae45063b934d5214af562d5b7509 Mon Sep 17 00:00:00 2001 From: cseci Date: Tue, 1 Oct 2024 08:54:30 +0100 Subject: [PATCH] deploy: 1dd8efc2036e1b5d269037ead04287a1d5530f24 --- _images/ad408x_fmc_clock_scheme.svg | 536 ++ _images/ad408x_fmc_evb_zed_block_diagram.svg | 1672 ++++++ _images/ad57xx_coraz7s_hdl.svg | 2168 ++++++++ _images/ad57xx_de10nano_hdl.svg | 2202 ++++++++ _images/adrv904x_zcu102_jesd204c.svg | 2 +- _images/block_diagram1.svg | 1527 +++--- _images/block_diagram10.svg | 1219 ++--- _images/block_diagram11.svg | 1600 +++++- _images/block_diagram12.svg | 1366 +---- _images/block_diagram13.svg | 4611 +++-------------- _images/block_diagram14.svg | 4364 +++++++++++++++- _images/block_diagram15.svg | 1395 +---- _images/block_diagram16.svg | 1506 +++++- _images/block_diagram17.svg | 517 +- _images/block_diagram18.svg | 1638 +----- _images/block_diagram19.svg | 1585 +++++- _images/block_diagram2.svg | 1378 +++-- _images/block_diagram20.svg | 1719 +----- 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projects/pulsar_adc/index.html | 166 +- projects/pulsar_lvds/index.html | 3 + projects/template/index.html | 3 + search.html | 3 + searchindex.js | 2 +- user_guide/architecture.html | 3 + user_guide/build_hdl.html | 3 + user_guide/contributing.html | 3 + user_guide/customize_hdl.html | 3 + user_guide/docs_guidelines.html | 3 + user_guide/git_repository.html | 3 + user_guide/hdl_coding_guidelines.html | 3 + user_guide/index.html | 3 + user_guide/introduction.html | 3 + user_guide/ip_cores/axi_adc/index.html | 3 + user_guide/ip_cores/axi_dac/index.html | 3 + user_guide/ip_cores/creating_new_ip.html | 3 + user_guide/ip_cores/index.html | 3 + user_guide/ip_cores/interfaces.html | 3 + user_guide/ip_cores/use_adi_ips.html | 3 + user_guide/porting_project.html | 3 + user_guide/releases.html | 3 + user_guide/third_party.html | 3 + 168 files changed, 30463 insertions(+), 18381 deletions(-) create mode 100644 _images/ad408x_fmc_clock_scheme.svg create mode 100644 _images/ad408x_fmc_evb_zed_block_diagram.svg create mode 100644 _images/ad57xx_coraz7s_hdl.svg create mode 100644 _images/ad57xx_de10nano_hdl.svg create mode 100644 _images/block_diagram25.svg create mode 100644 library/axi_ad408x/index.html create mode 100644 projects/ad408x_fmc_evb/index.html create mode 100644 projects/ad57xx_ardz/index.html diff --git a/_images/ad408x_fmc_clock_scheme.svg b/_images/ad408x_fmc_clock_scheme.svg new file mode 100644 index 0000000000..e41c417997 --- /dev/null +++ b/_images/ad408x_fmc_clock_scheme.svg @@ -0,0 +1,536 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + FPGA + ADF4350 + CLK 25MHz + + + + + CLK_SRC_P + CLK_SRC_N + + CNV_COPY_P/FPGACLK_P + CNV_COPY_N/FPGACLK_N + + + + AD9508 + + + + + CNV_P + DCO+ + DCO- + CNV_N + + + CLK_P + CLK_N + CLK_P + CLK_N + AD4080 + + + + diff --git a/_images/ad408x_fmc_evb_zed_block_diagram.svg b/_images/ad408x_fmc_evb_zed_block_diagram.svg new file mode 100644 index 0000000000..3f4f893f63 --- /dev/null +++ b/_images/ad408x_fmc_evb_zed_block_diagram.svg @@ -0,0 +1,1672 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Ethernet + UART + DDRx + SPI + I2C + Interrupts + + Timer + + Receive path + + MEMORY INTERCONNECT + ZedBoard + + FMC CONNECTOR + + + DMA + ARM (Zynq) + + + + + + + + + + + DA_p + DA_n + + + DB_p + DB_n + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 64 + 32 + + + + + ad_serdes_in + + ad_pack + ad408x_phy + ADC COMMON + + ADC CHANNEL + UP_AXI + + + AXI-AD408X IP + DMA_CLK=100MHz + REF_CLK= DCO_CLK(400MHz) / 4 + REF_CLK= DCO_CLK(400MHz) + + + DCO_p + DCO_n + + AD4080/ADF4350/AD9508 SPI + + + diff --git a/_images/ad57xx_coraz7s_hdl.svg b/_images/ad57xx_coraz7s_hdl.svg new file mode 100644 index 0000000000..8794c75e01 --- /dev/null +++ b/_images/ad57xx_coraz7s_hdl.svg @@ -0,0 +1,2168 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + + + + + + + + + + Ethernet + UART + DDRx + SPI + I2C + Interrupts + + Timer + + + Send path + + + + MEMORY INTERCONNECT + + Cora Z7-07S + + + + AD57XX_DMA + spi_clk =140 MHz + + + + DAC core frame + + + + ARM (Zynq) + Zynq SoC + + + SPI ENGINE FRAMEWORK + SDI + SCLK + + CS (SYNCB) + + + + I2C + + + + + + + AXIREGMAP + INTER-CONNECT + EXECUTION + OFFLOAD + + + + + @100KHz + + + + + + + + + + + ARDUINO SHIELD CONNECTOR + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 32b + + + 32b + trigger + s0_ctrl + s1_ctrl + offload_ctrl + spi_engine_ctrl + m_ctrl + + SDO + + + AXIPWM GEN + + + + + + AXI CLK GEN + + + 35MHz + + + AXIGPIO + + + + + + + + + LDACB + + CLRB + + + RESETB + + + + sys_clk = 100 MHz + + + + + diff --git a/_images/ad57xx_de10nano_hdl.svg b/_images/ad57xx_de10nano_hdl.svg new file mode 100644 index 0000000000..d661bf9e24 --- /dev/null +++ b/_images/ad57xx_de10nano_hdl.svg @@ -0,0 +1,2202 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + + + + + + + + + + + Ethernet + UART + DDRx + SPI + I2C + Interrupts + + Timer + + + Send path + + + + MEMORY INTERCONNECT + + DE10-Nano + + + + AD57XX_DMA + dma_clk=80 MHz + spi_clk =140 MHz + + + + DAC core frame + + + + ARM (HPS) + Cyclone V SoC + + + SPI ENGINE FRAMEWORK + SDI + SCLK + + CS (SYNCB) + + + + I2C + + + + + + + AXIREGMAP + INTER-CONNECT + EXECUTION + OFFLOAD + + + + + @100KHz + + + + + + + + + + + ARDUINO SHIELD CONNECTOR + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 128b + + + 32b + trigger + s0_ctrl + s1_ctrl + offload_ctrl + spi_engine_ctrl + m_ctrl + + SDO + + + AXIPWM GEN + + + + + + ALTERA PLL + + + + 35MHz + + + + ALTERA PIO + + + + + + + + + + LDACB + + CLRB + + + RESETB + + + + + + sys_clk =50 MHZ + + + + diff --git a/_images/adrv904x_zcu102_jesd204c.svg b/_images/adrv904x_zcu102_jesd204c.svg index 636e5b5736..4e6a641510 100644 --- a/_images/adrv904x_zcu102_jesd204c.svg +++ b/_images/adrv904x_zcu102_jesd204c.svg @@ -1,4 +1,4 @@ -
FMC CONNECTOR
FMC CONNECTOR
XCVR
XCVR
TX LaneRate = 16.22 Gbps
TX LaneRate = 16.22 Gbps
8x
16.22Gbps
8x...
REFCLK0/1
REFCLK0/1
RX JESD LINK
RX JESD LINK
8x 64bits @245.76MHz
8x 64bits @2...
RX JESD TPL
RX JESD TPL
1x 512 bits @245.76MHz
1x 512 bits...
UTIL_CPACK
UTIL_CPACK
GlobalClock = LaneRate/66 = 245.76 MHz
GlobalClock = LaneRate/66 = 245.76 MHz
SystemClk = 100MHz
SystemClk = 100MHz
AXI DMA
AXI DMA
MEMORY INTERCONNECT
MEMORY INTERCONNECT
ZCU102
ZCU102
GLBCLK
GLBCLK
SYSREF
SYSREF
Zynq
Zynq
RX LaneRate = 16.22 Gbps
RX LaneRate = 16.22 Gbps
16x 32bits @245.76MHz
16x 32bits @...
1x 512bits @250 MHz
1x 512bits...
AXI DMA
AXI DMA
UTIL_UPACK
UTIL_UPACK
DATA_OFFLOAD
DATA_OFFLOAD
TX JESD TPL
TX JESD TPL
TX JESD LINK
TX JESD LINK
DmaClk = 250MHz
DmaClk = 250MHz
1x 512bits @250 MHz
1x 512bits...
8x 64bits @245.76MHz
8x 64bits @2...
8x
16.22Gbps
8x...
1x 512 bits @245.76MHz
1x 512 bits...
16x 32bits @245.76MHz
16x 32bits @...
1x 512 bits @245.76MHz
1x 512 bits...
1x 512 bits @245.76MHz
1x 512 bits...
DATA_OFFLOAD
DATA_OFFLOAD
\ No newline at end of file +
FMC CONNECTOR
FMC CONNECTOR
XCVR
XCVR
TX LaneRate = 16.22 Gbps
TX LaneRate = 16.22 Gbps
8x
16.22Gbps
8x...
REFCLK0/1
REFCLK0/1
RX JESD LINK
RX JESD LINK
8x 64bits @245.76MHz
8x 64bits @2...
RX JESD TPL
RX JESD TPL
1x 512 bits @245.76MHz
1x 512 bits...
UTIL_CPACK
UTIL_CPACK
GlobalClock = LaneRate/66 = 245.76 MHz
GlobalClock = LaneRate/66 = 245.76 MHz
SystemClk = 100MHz
SystemClk = 100MHz
AXI DMA
AXI DMA
MEMORY INTERCONNECT
MEMORY INTERCONNECT
ZCU102/VCK190
ZCU102/VC...
GLBCLK
GLBCLK
SYSREF
SYSREF
Versal/ZynqMP
Versal/ZynqMP
RX LaneRate = 16.22 Gbps
RX LaneRate = 16.22 Gbps
16x 32bits @245.76MHz
16x 32bits @...
1x 512bits @250 MHz
1x 512bits...
AXI DMA
AXI DMA
UTIL_UPACK
UTIL_UPACK
DATA_OFFLOAD
DATA_OFFLOAD
TX JESD TPL
TX JESD TPL
TX JESD LINK
TX JESD LINK
DmaClk = 250MHz
DmaClk = 250MHz
1x 512bits @250 MHz
1x 512bits...
8x 64bits @245.76MHz
8x 64bits @2...
8x
16.22Gbps
8x...
1x 512 bits @245.76MHz
1x 512 bits...
16x 32bits @245.76MHz
16x 32bits @...
1x 512 bits @245.76MHz
1x 512 bits...
1x 512 bits @245.76MHz
1x 512 bits...
DATA_OFFLOAD
DATA_OFFLOAD
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- - - - - - image/svg+xml - - - - - + transform="translate(-36.901624,-34.12943)"> + + + + + ad_serdes_in + + ad_pack + + ad408x_phy + ADC COMMON + + ADC CHANNEL + UP_AXI + + + + AXI-AD408X IP arhitecture - - - - - - + id="g60184" + transform="translate(2.1444043,-19.478339)"> + style="fill:none;stroke:#000000;stroke-width:0.665;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;marker-end:url(#TriangleOutM)" + d="m 34.75722,63.438628 c 31.451263,0 31.451263,0 31.451263,0" + id="path51036" /> - - - - DFMT - - - - CRCCHECK - + style="fill:none;stroke:#000000;stroke-width:0.665;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;marker-end:url(#TriangleOutM-6)" + d="m 34.974187,68.442238 c 31.451263,0 31.451263,0 31.451263,0" + id="path51036-9" /> Channel 0 + id="tspan56449" + style="font-size:3.175px;stroke-width:0.264583" + x="42.798737" + y="62.009022">dclk_in_p Channel 1 + id="tspan56449-8" + style="font-size:3.175px;stroke-width:0.264583" + x="42.533909" + y="67.386765">dclk_in_n + + + + ... + id="tspan56449-9" + style="font-size:3.175px;stroke-width:0.264583" + x="42.798737" + y="62.009022">data_a_in_p Channel 8 - - - + id="tspan56449-8-0" + style="font-size:3.175px;stroke-width:0.264583" + x="42.533909" + y="67.386765">data_a_in_n + + + + adc_clk + adc_valid + + + adc_data[31:0] + adc_dovf + + style="fill:none;stroke:#000000;stroke-width:0.665;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;marker-end:url(#TriangleOutM-45-3)" + d="m 34.75722,63.438628 c 31.451263,0 31.451263,0 31.451263,0" + id="path51036-1-6" /> + style="fill:none;stroke:#000000;stroke-width:0.665;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;marker-end:url(#TriangleOutM-6-1-7)" + d="m 34.974187,68.442238 c 31.451263,0 31.451263,0 31.451263,0" + id="path51036-9-3-1" /> PARALLELINTERFACE + id="tspan56449-9-9" + style="font-size:3.175px;stroke-width:0.264583" + x="42.798737" + y="62.009022">data_b_in_p AXI_AD7606x - - - uP CHANNEL - - - - uP COMMON - - - - uP (AXI) - - - - ... - - - - - DB_O + id="tspan56449-8-0-4" + style="font-size:3.175px;stroke-width:0.264583" + x="42.533909" + y="67.386765">data_b_in_n + + + style="fill:none;stroke:#000000;stroke-width:0.665;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;marker-end:url(#TriangleOutM-45-3-2)" + d="m 34.75722,63.438628 c 31.451263,0 31.451263,0 31.451263,0" + id="path51036-1-6-5" /> BUSY + id="tspan56449-9-9-4" + style="font-size:3.175px;stroke-width:0.264583" + x="36.977898" + y="62.009022">sync_n + FIRST_DATA - - - WR_N - + id="tspan56449-9-9-4-2" + style="font-size:3.175px;stroke-width:0.264583" + x="36.997032" + y="73.955444">delay_clk RD_N - - CS_N - DATA + id="tspan56449-8-0-4-5" + style="font-size:3.175px;stroke-width:0.264583" + x="36.71307" + y="67.386765">filter_data_ready_n + + + STAT - - ADC_CONFIG + id="tspan85727" + style="font-size:3.43958px;stroke-width:0.264583" + x="42.75819" + y="113.10739">S_AXI_MM + + + style="fill:none;stroke:#000000;stroke-width:0.665;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;marker-end:url(#TriangleOutM-8)" + d="m 34.75722,63.438628 c 31.451263,0 31.451263,0 31.451263,0" + id="path51036-3" /> - DB_I + style="fill:none;stroke:#000000;stroke-width:0.665;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;marker-end:url(#TriangleOutM-6-7)" + d="m 34.974187,68.442238 c 31.451263,0 31.451263,0 31.451263,0" + id="path51036-9-8" /> DB_T + style="font-size:3.175px;line-height:1.25;font-family:Arial;-inkscape-font-specification:'Arial, Normal';stroke-width:0.264583" + x="42.798737" + y="62.009022" + id="text56451-13">cnv_in_p DATA_F - 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@@ -879,718 +943,477 @@ inkscape:label="Layer 1" inkscape:groupmode="layer" id="layer1" - transform="translate(0,-552.36202)"> + transform="translate(-18.205785,-566.84345)"> + width="493.2551" + height="280.08105" + x="18.97311" + y="567.61078" /> + x="103.08754" + y="822.79993" + style="font-size:12.5px;line-height:1.25">  + x="190.86754" + y="640.01111" + style="font-size:25.0847px;line-height:1.25">  + x="441.96735" + y="761.41437" + style="font-size:40px;line-height:1.25">    + + style="display:inline;opacity:0.87;fill:#fffeff;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:1.52695;stroke-linecap:round;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" /> Register Map + style="font-size:17.5px;line-height:1.25;text-align:center;text-anchor:middle">Register Map + style="display:inline;opacity:0.87;fill:#fffeff;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:1.39979;stroke-linecap:round;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" /> AD9963 INTERFACE CMOS - TX_CLK - - TX_IQ - - TX_DATA + x="-788.2749" + y="384.27646" + style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:12px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal">AD9783 LVDS INTERFACE TRX_CLK - - TRX_IQ + x="50.594776" + y="642.27081" + style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.3333px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal">CLK_IN_P TRX_DATA + id="tspan4414-6-7" + x="50.594521" + y="668.99487" + style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.3332px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal;stroke-width:0.999989px">CLK_IN_N - - - RX CHANNEL - - - - - - - - - - - - - - IQ Corr - - - - - PNMON - - DC Filter - - - - RX CORE + width="202.41908" + height="175.60899" + x="137.45062" + y="622.18188" /> + width="166.61047" + height="132.32573" + x="156.06688" + y="653.31299" /> - - - IQ Correction - + width="166.61061" + height="132.32573" + x="153.52708" + y="650.65302" /> - PRBS - PATTERN + x="188.88448" + y="744.78796" + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:12.5px;line-height:1.25;font-family:Arial;-inkscape-font-specification:'Arial Bold';stroke-width:1;stroke-miterlimit:4;stroke-dasharray:none">PRBS DDS + x="191.97041" + y="725.58636" + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:12.5px;line-height:1.25;font-family:Arial;-inkscape-font-specification:'Arial Bold';stroke-width:1;stroke-miterlimit:4;stroke-dasharray:none">DDS DMA + x="190.93526" + y="707.23004" + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:12.5px;line-height:1.25;font-family:Arial;-inkscape-font-specification:'Arial Bold';stroke-width:1;stroke-miterlimit:4;stroke-dasharray:none">DMA - TX CHANNEL + x="180.92122" + y="674.56873" + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:17.5px;line-height:1.25;font-family:Arial;-inkscape-font-specification:'Arial Bold';fill:#000000;fill-opacity:1;stroke-width:1;stroke-miterlimit:4;stroke-dasharray:none">TX CHANNEL TX CORE + x="202.35014" + y="639.69751" + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:17.5px;line-height:1.25;font-family:Arial;-inkscape-font-specification:'Arial Bold';fill:#000000;fill-opacity:1">TX CORE + + 64b - - - - - - DAC_FIFO_I + id="tspan7846-38-5-3" + x="65.264023" + y="720.39014" + style="font-size:15px;line-height:1.25">64b DAC_FIFO_Q - ADC_FIFO_I + id="tspan7846" + x="34.50037" + y="703.57098" + style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.3333px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal">DAC_DMA_I ADC_FIFO_Q + id="tspan7846-3" + x="34.50037" + y="742.39026" + style="font-style:normal;font-variant:normal;font-weight:normal;font-stretch:normal;font-size:13.3333px;line-height:1.25;font-family:sans-serif;-inkscape-font-specification:'sans-serif, Normal';font-variant-ligatures:normal;font-variant-caps:normal;font-variant-numeric:normal;font-variant-east-asian:normal">DAC_DMA_Q   + S_AXI_MM + x="49.316456" + y="823.90955" + style="font-size:15px;line-height:1.25">S_AXI_MM + + AXI_AD9783 + + CLK_OUT_P + CLK_OUT_N + + + + 16b + + + + 16b + DAC_OUT_P + DAC_OUT_N diff --git a/_images/block_diagram11.svg b/_images/block_diagram11.svg index e0f4dae75a..55722fe2b8 100644 --- a/_images/block_diagram11.svg +++ b/_images/block_diagram11.svg @@ -1,4 +1,1596 @@ - - - -
DMA_FIFO
DMA_FIFO
ADC
DATA
PROCESSING
ADC...
REGISTER
MAP
REGISTER...
LVDS OR CMOS
INTERFACE
LVDS OR CMOS...
AXI SLAVE
AXI SLAVE
LVDS OR CMOS
LVDS OR CMOS
Text is not SVG - cannot display
\ No newline at end of file + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + + Register Map + + AD9963 INTERFACE CMOS + TX_CLK + + TX_IQ + + TX_DATA + + TRX_CLK + + TRX_IQ + + TRX_DATA + + + + RX CHANNEL + + + + + + + + + + + + + + IQ Corr + + + + + PNMON + + DC Filter + + + + RX CORE + + + + + IQ Correction + + + + + + PRBS + PATTERN + DDS + DMA + + + + TX CHANNEL + + + TX CORE + + + + + + + + + + + + + + DAC_FIFO_I + DAC_FIFO_Q + ADC_FIFO_I + ADC_FIFO_Q + + + + S_AXI_MM + + + diff --git a/_images/block_diagram12.svg b/_images/block_diagram12.svg index 8b1ed331df..e0f4dae75a 100644 --- a/_images/block_diagram12.svg +++ b/_images/block_diagram12.svg @@ -1,1362 +1,4 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - image/svg+xml - - - - - - - - - - - - - - - - CHANNEL_A - - - - ProgrammableCIC - Decimation by5/50/500/5000/50000 - - - - ProgrammableCIC - Decimation by5/50/500/5000/50000 - - - - CompensationFIR - Decimation by2 - - - - Arbitrary Decimation - - - - - CompensationFIR - Decimation by2 - - - - Arbitrary Decimation - - - - - - CHANNEL_B - - - - - - CHANNEL_A - - - - - - CHANNEL_B - - - - - - ScaleCompensation - - - - - ScaleCompensation - - - - + + + +
DMA_FIFO
DMA_FIFO
ADC
DATA
PROCESSING
ADC...
REGISTER
MAP
REGISTER...
LVDS OR CMOS
INTERFACE
LVDS OR CMOS...
AXI SLAVE
AXI SLAVE
LVDS OR CMOS
LVDS OR CMOS
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+ @@ -3354,980 +848,515 @@ inkscape:label="Layer 1" inkscape:groupmode="layer" id="layer1" - transform="translate(0,542.12572)"> + transform="translate(0,-752.36203)"> + style="display:inline;opacity:1;fill:#000000;fill-opacity:0;fill-rule:nonzero;stroke:#000000;stroke-width:1.72103631;stroke-linecap:square;stroke-linejoin:round;stroke-miterlimit:0;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" + id="rect4477" + width="638.54614" + height="235.86682" + x="100.22995" + y="782.36804" /> + + + + + id="g5418" + transform="translate(-73.93485,111.79084)"> + + +   + y="748.43793" + x="90.574524" + id="tspan7846" + sodipodi:role="line">CHANNEL_A + + +   -       + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:17.5px;font-family:Arial;-inkscape-font-specification:'Arial Bold';text-align:center;text-anchor:middle;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1;stroke-miterlimit:4;stroke-dasharray:none" + y="721.11584" + x="270.29984" + id="tspan6053" + sodipodi:role="line">ProgrammableCIC   + y="760.51514" + x="269.48785" + id="tspan5040" + sodipodi:role="line">Decimation by5/50/500/5000/50000 + + +   - - + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:17.5px;font-family:Arial;-inkscape-font-specification:'Arial Bold';text-align:center;text-anchor:middle;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1;stroke-miterlimit:4;stroke-dasharray:none" + y="818.68341" + x="271.29083" + id="tspan6053-8" + sodipodi:role="line">ProgrammableCIC REGMAP - - + y="858.0827" + x="270.47882" + id="tspan5040-9" + sodipodi:role="line">Decimation by5/50/500/5000/50000 + + - AXI ADC TRIGGER + y="698.55518" + x="346.95609" + height="84.377632" + width="133.26411" + id="rect4870-9-3-3-8" + style="display:inline;opacity:1;fill:#d2e6eb;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.50000006;stroke-linecap:square;stroke-linejoin:round;stroke-miterlimit:0;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" /> ADC ch A [15:0] -   - - - - - - - - - - - - + sodipodi:linespacing="125%" + id="text6051-37" + y="721.61133" + x="414.26379" + style="font-style:normal;font-weight:normal;font-size:10px;line-height:125%;font-family:Arial;text-align:center;letter-spacing:0px;word-spacing:0px;text-anchor:middle;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.50000006;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:0;stroke-dasharray:none;stroke-opacity:1;shape-rendering:crispEdges" + xml:space="preserve">CompensationFIR ADC ch B [15:0] - - - - - - - + sodipodi:linespacing="125%" + id="text5038-4" + y="761.01062" + x="413.45181" + style="font-style:normal;font-weight:normal;font-size:10px;line-height:125%;font-family:sans-serif;text-align:center;letter-spacing:0px;word-spacing:0px;text-anchor:middle;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.50000006;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:0;stroke-dasharray:none;stroke-opacity:1" + xml:space="preserve">Decimation by2 -   -   - - Externaltrigger control - trigger_i[1:0] - trigger_o[1:0] - trigger_t[1:0] - I[1] - I[0] -   -   - -   - - + id="g5376" + transform="translate(-66.353133,108.2214)" + style="stroke:none;stroke-opacity:1"> + y="699.00562" + x="491.05518" + height="84.377632" + width="133.26411" + id="rect4870-9-3-3-2" + style="display:inline;opacity:1;fill:#d2e6eb;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.56177157;stroke-linecap:square;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" /> + Arbitrary Decimation Ch AMUX - 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CH B - Pin 0(Ti)triggerdetect - Pin 1(To)triggerdetect - - trigger_out_la - - - - - - 2 FFsync + style="display:inline;opacity:1;fill:#000000;fill-opacity:0;fill-rule:nonzero;stroke:#000000;stroke-width:1.00000012;stroke-linecap:square;stroke-linejoin:round;stroke-miterlimit:0;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" + id="rect4477-2" + width="290.69589" + height="91.70903" + x="121.118" + y="803.55511" /> + style="display:inline;opacity:1;fill:#000000;fill-opacity:0;fill-rule:nonzero;stroke:#000000;stroke-width:1.00000012;stroke-linecap:square;stroke-linejoin:round;stroke-miterlimit:0;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" + id="rect4477-2-4" + width="290.69611" + height="91.664299" + x="121.08652" + y="903.57385" /> + + + ScaleCompensation + + + id="g5367-9-1" + transform="translate(229.44022,209.53854)" + style="stroke:none;stroke-width:0.50000006;stroke-miterlimit:0;stroke-dasharray:none"> + y="698.55518" + x="343.12726" + height="84.377632" + width="133.26411" + id="rect4870-9-3-3-8-4-8" + style="display:inline;opacity:1;fill:#d2e6eb;fill-opacity:1;fill-rule:nonzero;stroke:none;stroke-width:0.50000006;stroke-linecap:square;stroke-linejoin:round;stroke-miterlimit:0;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" /> + ScaleCompensation   32 bitholdoffcounter + sodipodi:linespacing="125%" + id="text5038-4-1-5" + y="761.01062" + x="413.45181" + style="font-style:normal;font-weight:normal;font-size:10px;line-height:125%;font-family:sans-serif;text-align:center;letter-spacing:0px;word-spacing:0px;text-anchor:middle;fill:#000000;fill-opacity:1;stroke:none;stroke-width:0.50000006;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:0;stroke-dasharray:none;stroke-opacity:1" + xml:space="preserve"> - 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- + + - + - + image/svg+xml - - + + - - - - Register Map - - + + + +   +   +       +   +   + + + REGMAP + + + + AXI ADC TRIGGER + ADC ch A [15:0] +   + + + + + + + + + + + + + ADC ch B [15:0] + + + + + + + + +   +   + + Externaltrigger control + trigger_i[1:0] + trigger_o[1:0] + trigger_t[1:0] + I[1] + I[0] +   +   + +   + + + + + + Ch AMUX + + OutMUX + + + trigger_out +   +    + trigger_in(LA) + up_triggerd_o[1:0] + + +  32 bitdelaycounter + + + ADC data +embeddedtriger(bit 15) +   +   ADC ch A + ADC ch B + + + + Ch BMUX + ChannelTrigger + + + CH A + + + CH B + Pin 0(Ti)triggerdetect + Pin 1(To)triggerdetect + + trigger_out_la + + + + + + 2 FFsync + + + +   32 bitholdoffcounter - S_AXI_MM - - - - - - MMCM - clk - clk2 - clk_0 - clk_1 - CLKIN1 - CLKIN2 - - - - BUFG - BUFG - - - CLKOUT0 - CLKOUT1 + + State hold - \ No newline at end of file + + diff --git a/_images/block_diagram15.svg b/_images/block_diagram15.svg index 4384f9d685..e94f990e33 100644 --- a/_images/block_diagram15.svg +++ b/_images/block_diagram15.svg @@ -1,1362 +1,63 @@ - - - - - + + + + - - + + - - + + - - + + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + - - + + - + - + image/svg+xml - - + + - - - - - - - - - - - CHANNEL_A - - - - ProgrammableCIC - Interpolation by5/50/500/5000/50000 - - - - ProgrammableCIC - Interpolation by5/50/500/5000/50000 - - - - CompensationFIR - Interpolation by2 - - - - Arbitrary Interpolation - - - - - CompensationFIR - Interpolation by2 - - - - Arbitrary Interpolation - - - - - - CHANNEL_B - - - - - - CHANNEL_A - - - - - - CHANNEL_B - - - - - - ScaleCompensation - - - - - ScaleCompensation - - + + + + Register Map + + + + S_AXI_MM + + + + + + MMCM + clk + clk2 + clk_0 + clk_1 + CLKIN1 + CLKIN2 + + + + BUFG + BUFG + + + CLKOUT0 + CLKOUT1 - + \ No newline at end of file diff --git a/_images/block_diagram16.svg b/_images/block_diagram16.svg index 094f747325..4384f9d685 100644 --- a/_images/block_diagram16.svg +++ b/_images/block_diagram16.svg @@ -1,148 +1,1362 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Store-and-forwardData Buffer + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + + + + + + + CHANNEL_A + + + + ProgrammableCIC + Interpolation by5/50/500/5000/50000 + + + + ProgrammableCIC + Interpolation by5/50/500/5000/50000 + + + + CompensationFIR + Interpolation by2 + + + + Arbitrary Interpolation + + + + + CompensationFIR + Interpolation by2 + + + + Arbitrary Interpolation + + + + + + CHANNEL_B + + + + + + CHANNEL_A + + + + + + CHANNEL_B + + + + + + ScaleCompensation + + + + + ScaleCompensation + + - - Register Map - S_AXI - s_axi_aclk - irq - - - - Transfer queue - - - - SourceDataInterface - - - - DestinationDataInterface - - - - - - - - - - - - - - - - - - AXI-MM /AXI-Streaming /FIFO - AXI-MM /AXI-Streaming /FIFO - - - - Transfermanagement - - Control - - Status - - - Transfer request - Transfer request - - Transfer response - - Transfer response - - - src_clk - - dest_clk - - - Scatter-GatherInterface - - - sg_clk - AXI-MM - diff --git a/_images/block_diagram17.svg b/_images/block_diagram17.svg index 301f9a654d..094f747325 100644 --- a/_images/block_diagram17.svg +++ b/_images/block_diagram17.svg @@ -1,373 +1,148 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - image/svg+xml - - - - - - - - Register Map - FSM - Tacho measurementPWM generatorTemperature read - - - - - - - - - - - S_AXI - Tacho - PWM - Irq + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Store-and-forwardData Buffer + + Register Map + S_AXI + s_axi_aclk + irq + + + + Transfer queue + + + + SourceDataInterface + + + + DestinationDataInterface + + + + + + + + + + + + + + + + + + AXI-MM /AXI-Streaming /FIFO + AXI-MM /AXI-Streaming /FIFO + + + + Transfermanagement + + Control + + Status + + + Transfer request + Transfer request + + Transfer response + + Transfer response + + + src_clk + + dest_clk + + + Scatter-GatherInterface + + + sg_clk + AXI-MM + diff --git a/_images/block_diagram18.svg b/_images/block_diagram18.svg index 8599be1e90..301f9a654d 100644 --- a/_images/block_diagram18.svg +++ b/_images/block_diagram18.svg @@ -2,7 +2,6 @@ + id="svg8" + inkscape:version="0.92.3 (2405546, 2018-03-11)" + sodipodi:docname="axi_fan_control.svg"> - - - - - - - - - - - - - - - - - - - - - - + id="defs2"> + inkscape:stockid="EmptyTriangleOutL"> - - - - - - + inkscape:stockid="EmptyTriangleInL"> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + inkscape:stockid="EmptyTriangleOutL" + inkscape:collect="always"> - - - - - - - - - - - - - - - + inkscape:collect="always"> - - - - - - + inkscape:collect="always"> + id="path996-6" + d="M 5.77,0 -2.88,5 V -5 Z" + style="fill:#ffffff;fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;stroke-opacity:1" + transform="matrix(-0.8,0,0,-0.8,4.8,0)" /> + id="path1005-7" + d="M 5.77,0 -2.88,5 V -5 Z" + style="fill:#ffffff;fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;stroke-opacity:1" + transform="matrix(0.8,0,0,0.8,-4.8,0)" /> - - - + inkscape:stockid="EmptyTriangleOutL"> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + transform="matrix(0.8,0,0,0.8,-4.8,0)" + style="fill:#ffffff;fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;stroke-opacity:1" + d="M 5.77,0 -2.88,5 V -5 Z" + id="path5100-4" /> - - + scale-x="1" + units="px" + viewbox-height="230.82" + fit-margin-top="0" + fit-margin-left="0" + fit-margin-right="0" + fit-margin-bottom="0" /> + id="metadata5"> image/svg+xml - + @@ -1099,483 +199,175 @@ inkscape:label="Layer 1" inkscape:groupmode="layer" id="layer1" - transform="translate(0,-652.36204)"> - - + transform="translate(-69.106348,58.128533)"> + style="fill:none;fill-opacity:1;stroke:#000000;stroke-width:2;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" + id="rect817" + width="343.51617" + height="214.86215" + x="148.8501" + y="-39.523445" /> CSC - to DMA - - - - - EmbededSync - - - Register Map - SYNC - CLK - Register Map + x="185.40535" + y="37.125149" + style="stroke-width:1.48832011" + id="tspan823" /> DATA + id="tspan825" + x="195.31564" + y="97.282433" + style="stroke-width:1.48832011;font-size:16px">FSM S_AXI_Lite - Tacho measurement - PWM generator - - - Super Sampling - - - - TPM Sync monitor - + x="300.77356" + y="122.97372" + style="stroke-width:1.48832011;font-size:16px" + id="tspan835">Temperature read + + + + style="fill:none;stroke:#000000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;marker-start:url(#EmptyTriangleInL);marker-end:url(#EmptyTriangleOutL)" + d="M 238.19217,96.05085 H 274.742" + id="path843" + inkscape:connector-curvature="0" /> + style="fill:none;stroke:#000000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;marker-start:url(#EmptyTriangleInL-3);marker-end:url(#EmptyTriangleOutL-2)" + d="M 209.19268,76.577872 V 27.042479" + id="path843-4" + inkscape:connector-curvature="0" /> - - - Datainterleave - - + style="fill:none;stroke:#000000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;marker-end:url(#marker5102)" + d="M 493.08041,129.04571 H 555.673" + id="path5040" + inkscape:connector-curvature="0" /> + style="fill:none;stroke:#000000;stroke-width:1;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;marker-start:url(#marker5553);marker-end:url(#marker5483)" + d="M 82.098308,6.538604 H 167.25212" + id="path5042" + inkscape:connector-curvature="0" /> - 16 16 + id="tspan8157" + x="109.04962" + y="98.224869" + style="stroke-width:0.42094442" /> 24 - - - - + id="tspan8161" + x="88.261047" + y="-3.9233534" + style="stroke-width:1.48832011;font-size:16px">S_AXI 32 - - + id="tspan8165" + x="86.582794" + y="115.14221" + style="stroke-width:1.48832011;font-size:16px">Tacho 64 - - - - + id="tspan8169" + x="540.28192" + y="52.419346" + style="line-height:1.25;stroke-width:1.48832011;font-size:16px">PWM Rx core + xml:space="preserve" + style="font-style:normal;font-weight:normal;font-size:19.8442688px;line-height:1.25;font-family:sans-serif;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none;stroke-width:1.48832011" + x="540.8924" + y="111.64744" + id="text8175" + transform="scale(0.93758119,1.0665743)">Irq diff --git a/_images/block_diagram19.svg b/_images/block_diagram19.svg index 83d81f0de2..8599be1e90 100644 --- a/_images/block_diagram19.svg +++ b/_images/block_diagram19.svg @@ -1,4 +1,1581 @@ - - - -
DMA AXIS
DMA AXIS
DMA_CLK
DMA_CLK
TX core
TX core
DMA
interface
DMA...
TPG
TPG
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FIFO
CSC
CSC
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Clipping
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interleaving
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Embedded
Sync
Embedded...
DATA_16_ES
DATA_16_ES
Data 
splitting
Data...
HSYNC/VSYNC/DE
HSYNC/VSYNC...
Sync
Signals
Sync...
HDMI_OUT_CLK
HDMI_OUT_CLK
VGA_OUT_CLK
VGA_OUT_CLK
REFERENCE_CLK
REFERENCE_...
S_AXI_LITE
S_AXI_LITE
Register Map
Register Map
Text is not SVG - cannot display
\ No newline at end of file + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + CSC + to DMA + + + + + EmbededSync + + + Register Map + SYNC + CLK + + DATA + S_AXI_Lite + + + + + Super Sampling + + + + TPM Sync monitor + + + + + + + Datainterleave + + + + + 16 + + 16 + 24 + + + + + 32 + + + 64 + + + + + Rx core + + diff --git a/_images/block_diagram2.svg b/_images/block_diagram2.svg index b73c3a3951..c4e1504fa6 100644 --- a/_images/block_diagram2.svg +++ b/_images/block_diagram2.svg @@ -1,6 +1,4 @@ - - + inkscape:version="1.0 (4035a4fb49, 2020-05-01)" + sodipodi:docname="axi_ad7606.svg"> + id="defs4300"> + + + + d="M 5.77,0 -2.88,5 V -5 Z" + id="path4651" /> + d="M 5.77,0 -2.88,5 V -5 Z" + id="path4641" /> + d="M 5.77,0 -2.88,5 V -5 Z" + id="path4631" /> + d="M 5.77,0 -2.88,5 V -5 Z" + id="path4621" /> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + inkscape:isstock="true"> + id="path1059-7" + d="M 5.77,0 -2.88,5 V -5 Z" + style="fill:#000000;fill-opacity:1;fill-rule:evenodd;stroke:#000000;stroke-width:1pt;stroke-opacity:1" + transform="scale(0.4)" /> + + + + + + + transform="scale(-0.4)" /> + + + + transform="scale(-0.4)" /> + + + + + + + + + + units="px" + inkscape:document-rotation="0"> + + + id="metadata4303"> image/svg+xml - + - - - DB[15:0]WRn/RDn - + id="layer1" + transform="translate(0,-802.36216)"> + id="g5889" + transform="translate(-10,144)"> + + + + + + + + + + + + DFMT + + + + CRCCHECK + + Channel 0 + Channel 1 + ... + Channel 8 + style="display:inline;opacity:1;fill:none;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:2.5;stroke-linecap:square;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" + id="rect4870-9-3-0-5-3" + width="424.11166" + height="282.98355" + x="45.182457" + y="668.24133" /> + style="display:inline;opacity:1;fill:none;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:2;stroke-linecap:square;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" + id="rect4870-9-3-0-5-34" + width="91.376862" + height="191.808" + x="354.38171" + y="689.23669" /> + + + + PARALLELINTERFACE AXI_AD7606x + + + uP CHANNEL + + + + uP COMMON + + + + uP (AXI) + + + + ... + + + + + DB_O + + BUSY + INPUT + id="tspan35272" + x="474.04669" + y="718.75049" + style="font-size:10px;line-height:1.25">FIRST_DATA + + WR_N + + OUTPUT - - - - - - - - S_AXI_LITE - WR_FIFO - - REGISTERMAP - - - CONTROL  - PARALLEL INTERFACE - - BUSY - - burst_length - - - - + id="tspan35272-7-3" + x="476.62567" + y="764.9704" + style="font-size:10px;line-height:1.25">RD_N + id="path4232-8-1-2-5" + d="m 445.14824,792.00417 h 67.92827" + style="fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:2;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;marker-end:url(#marker1061-4-9-0)" /> + CS_N + DATA + STAT + sodipodi:nodetypes="cc" + inkscape:connector-curvature="0" + id="path13119-3-5-0" + d="M 402.53325,904.0524 V 888.16618" + style="fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:2;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1;marker-start:url(#TriangleInM-2-6);marker-end:url(#marker2075-5)" /> + ADC_CONFIG + + + DB_I + DB_T + DATA_F + - 15:0 - adc_data - adc_valid - adc_sync diff --git a/_images/block_diagram20.svg b/_images/block_diagram20.svg index 844cb8deff..83d81f0de2 100644 --- a/_images/block_diagram20.svg +++ b/_images/block_diagram20.svg @@ -1,1715 +1,4 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - image/svg+xml - - - - - - - -   - s_axi - - -   - - - Register Map - - - - axi_pwm_gen_1 - - - - axi_pwm_gen_1 - - - - axi_pwm_gen_1 - - - - axi_pwm_gen_1 - - - - offsetcounter - - - - external_sync - - - equal - - - pwm 0 - - - pwp 1 - - - - equal - - - - equal - - - - - offset_1 - - - - - - - offset_2 - - offset_15 - - - - - - - pwm 2 - - pwm 15 - - sync - sync - sync - - - equal - - - sync - - offset_0 - - - - - + + + +
DMA AXIS
DMA AXIS
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DMA_CLK
TX core
TX core
DMA
interface
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HDMI_OUT_CLK
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S_AXI_LITE
Register Map
Register Map
Text is not SVG - cannot display
\ No newline at end of file diff --git a/_images/block_diagram21.svg b/_images/block_diagram21.svg index 75b78dd6be..844cb8deff 100644 --- a/_images/block_diagram21.svg +++ b/_images/block_diagram21.svg @@ -1,7 +1,6 @@ - - + id="svg2" + height="105mm" + width="205mm"> + id="defs4"> + inkscape:stockid="DotM"> + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + inkscape:stockid="TriangleInM"> + + + + style="overflow:visible" + id="marker9681" + refX="0" + refY="0" + orient="auto" + inkscape:stockid="TriangleInM"> + + + + + + + + + + id="marker12206-7" + refX="0" + refY="0" + orient="auto" + inkscape:stockid="TriangleOutM"> + id="path12208-1" /> + + + + + + + + + + id="marker11392-1" + refX="0" + refY="0" + orient="auto" + inkscape:stockid="TriangleOutM"> + id="path11394-1" /> + + + + + + + + + + + + + + + inkscape:stockid="TriangleOutM"> + + + + + + + + + + + + + id="path12476-1-2-9-3" + inkscape:connector-curvature="0" /> + inkscape:stockid="TriangleOutM"> + + + + + + + + + + + + + style="overflow:visible" + id="marker12474-7-9-2-6" + refX="0" + refY="0" + orient="auto" + inkscape:stockid="TriangleOutM"> + inkscape:window-y="-9" + inkscape:window-x="-9" + inkscape:window-height="2093" + inkscape:window-width="3840" + units="mm" + width="180mm" + showgrid="false" + inkscape:current-layer="g12973-9" + inkscape:document-units="px" + inkscape:cy="184.73009" + inkscape:cx="647.40946" + inkscape:zoom="2.4781457" + inkscape:pageshadow="2" + inkscape:pageopacity="0.0" + borderopacity="1.0" + bordercolor="#666666" + pagecolor="#ffffff" + id="base"> + + + id="metadata7"> @@ -179,173 +1137,579 @@ + inkscape:groupmode="layer" + inkscape:label="Layer 1"> + y="667.9389" + x="112.56175" + height="373.51859" + width="579.34064" + id="rect4477" + style="display:inline;fill:#000000;fill-opacity:0;fill-rule:nonzero;stroke:#000000;stroke-width:1.74925;stroke-linecap:square;stroke-linejoin:round;stroke-miterlimit:0;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;enable-background:new" /> Register Map - + id="text10879" + y="899.47211" + x="273.66757" + style="font-style:normal;font-weight:normal;line-height:0%;font-family:sans-serif;letter-spacing:0px;word-spacing:0px;fill:#000000;fill-opacity:1;stroke:none" + xml:space="preserve">  + s_axi + + +   + + style="color:#000000;display:inline;overflow:visible;visibility:visible;opacity:0.87;fill:#ffff99;fill-opacity:1;fill-rule:nonzero;stroke:#000000;stroke-width:2.18929;stroke-linecap:square;stroke-linejoin:round;stroke-miterlimit:0;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;marker:none;enable-background:new" + id="rect4867-1-6" + width="536.38409" + height="22.728928" + x="133.77641" + y="979.7132" /> + Register Map + + + + axi_pwm_gen_1 + + + + axi_pwm_gen_1 + + + + axi_pwm_gen_1 + + + + axi_pwm_gen_1 + + + + offsetcounter + + + + external_sync + + + equal + + + pwm 0 + + + pwp 1 + + + + equal + + + + equal + + + + + offset_1 + + + + + + + offset_2 + + offset_15 + + + + + + sodipodi:nodetypes="cc" + inkscape:connector-curvature="0" + id="path6277-8-0-2-1" + d="m 640.42859,780.02372 73.35202,0.125" + style="fill:none;stroke:#000000;stroke-width:2;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:0;stroke-dasharray:none;stroke-opacity:1;marker-end:url(#marker12474-7-9-5-0)" /> + x="723.4624" + y="817.22333" + id="tspan11726-6-6" + style="font-size:15px;line-height:1.25">pwm 2 + S_AXI + x="723.79462" + y="903.86609" + id="tspan11726-6-6-7" + style="font-size:15px;line-height:1.25">pwm 15 + ROM1 + x="473.4437" + y="774.64136" + style="font-size:15px;line-height:1.25;text-align:center;text-anchor:middle">sync ROM2sync + + x="471.93478" + y="932.40247" + style="font-size:15px;line-height:1.25;text-align:center;text-anchor:middle">sync - - + transform="translate(213.03009,94.75194)" + id="g5774-2-2"> + + equal - (SYS ROM) + id="path6277-8-0-2-3" + d="m 441.05038,709.59724 59.35202,0.125" + style="fill:none;stroke:#000000;stroke-width:2;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:0;stroke-dasharray:none;stroke-opacity:1;marker-end:url(#marker12474-7-9-5-9)" /> (PR ROM) - + x="472.72458" + y="704.21405" + style="font-size:15px;line-height:1.25;text-align:center;text-anchor:middle">sync + + offset_0 + + + diff --git a/_images/block_diagram22.svg b/_images/block_diagram22.svg index dc10b53b31..75b78dd6be 100644 --- a/_images/block_diagram22.svg +++ b/_images/block_diagram22.svg @@ -1,4 +1,6 @@ + + + id="svg8" + inkscape:version="0.92.3 (2405546, 2018-03-11)" + sodipodi:docname="sysid1.svg"> - - - - - - + id="defs2"> + inkscape:stockid="EmptyTriangleOutL"> + inkscape:stockid="EmptyTriangleInL"> - - - - - - + inkscape:isstock="true" + inkscape:collect="always"> + id="path5481" + d="M 5.77,0 -2.88,5 V -5 Z" + style="fill:#ffffff;fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;stroke-opacity:1" + transform="matrix(0.8,0,0,0.8,-4.8,0)" + inkscape:connector-curvature="0" /> + id="path996-6" + d="M 5.77,0 -2.88,5 V -5 Z" + style="fill:#ffffff;fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;stroke-opacity:1" + transform="matrix(-0.8,0,0,-0.8,4.8,0)" /> + id="path1005-7" + d="M 5.77,0 -2.88,5 V -5 Z" + style="fill:#ffffff;fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;stroke-opacity:1" + transform="matrix(0.8,0,0,0.8,-4.8,0)" /> - - - - - - - - - + inkscape:stockid="EmptyTriangleOutL"> + transform="matrix(0.8,0,0,0.8,-4.8,0)" + style="fill:#ffffff;fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;stroke-opacity:1" + d="M 5.77,0 -2.88,5 V -5 Z" + id="path5100-4" /> - - - - - - - - - + inkscape:stockid="EmptyTriangleInL"> + id="path5551-7" + inkscape:connector-curvature="0" /> + inkscape:isstock="true" + inkscape:collect="always"> + style="fill:#ffffff;fill-rule:evenodd;stroke:#000000;stroke-width:1.00000003pt;stroke-opacity:1" + transform="matrix(0.8,0,0,0.8,-4.8,0)" + inkscape:connector-curvature="0" /> + scale-x="1" + units="px" + viewbox-height="230.82" + fit-margin-top="0" + fit-margin-left="0" + fit-margin-right="0" + fit-margin-bottom="0" /> + id="metadata5"> image/svg+xml - + @@ -323,210 +182,170 @@ inkscape:label="Layer 1" inkscape:groupmode="layer" id="layer1" - transform="translate(0,-552.36216)"> + transform="translate(-69.106348,58.128533)"> + style="fill:none;fill-opacity:1;stroke:#000000;stroke-width:2;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" + id="rect817" + width="343.51617" + height="214.86215" + x="170.8501" + y="-39.523445" /> OFFLOAD FSM - + id="tspan819" + x="208.86998" + y="67.87204" + style="font-size:16px;stroke-width:1.48832011">Register Map + style="fill:none;fill-opacity:1;stroke:#000000;stroke-width:0.9257341;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" + id="rect837" + width="112.3101" + height="35.477028" + x="189.96289" + y="50.169117" /> - AXI REGISTERMAP - BYPASS + style="fill:none;fill-opacity:1;stroke:#000000;stroke-width:1.37463558;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" + id="rect841" + width="96.523468" + height="46.561604" + x="388.60941" + y="9.742239" /> S_AXIS - + id="tspan8157" + x="132.51425" + y="98.224869" + style="stroke-width:0.42094442" /> AXI_MM + id="tspan8161" + x="118.12513" + y="55.292774" + style="font-size:16px;stroke-width:1.48832011">S_AXI ROM1SOURCE + x="420.58072" + y="52.527092" + style="stroke-width:1.48832011" + id="tspan823-5" /> M_AXIS - - ROM2DESTINATION - + x="420.58072" + y="115.33181" + style="stroke-width:1.48832011" + id="tspan823-5-8" /> + + + + M_STORAGE_AXIS - (SYS ROM)S_STORAGE_AXIS - + x="420.72916" + y="69.219727" + style="stroke-width:1.48832011" + id="tspan823-5-6" /> Storage Unit + id="tspan819-4-1-5" + x="420.72916" + y="107.68681" + style="font-size:16px;stroke-width:1.48832011">(PR ROM) +
diff --git a/_images/block_diagram23.svg b/_images/block_diagram23.svg index a130c28fe4..dc10b53b31 100644 --- a/_images/block_diagram23.svg +++ b/_images/block_diagram23.svg @@ -1,4 +1,532 @@ - - - -
MII/GMII
MII/GMII
RMII
RMII
mac_txd[3:0]
mac_txd[...
mac_tx_en
mac_tx_en
mac_tx_er
mac_tx_er
mii_col
mii_col
mii_crs
mii_crs
mii_rxd[3:0]
mii_rxd[...
mii_rx_clk
mii_rx_c...
mii_rx_dv
mii_rx_dv
mii_rx_er
mii_rx_er
mii_tx_clk
mii_tx_c...
util_mii_to_rmii
util_mii_t...
rmii_txd[1:0]
rmii_txd...
rmii_tx_en
rmii_tx_...
phy_crs_dv
phy_crs_...
phy_rxd[1:0]
phy_rxd[...
phy_rx_er
phy_rx_er
ref_clk
ref_clk
reset_n
reset_n
Zynq-7000/Zynq Ultrascale+ MPSoC - PS Gigabit Ethernet MAC
Zynq-7000/Zynq Ultra...
RMII ADIN1300 PHY
RMII ADIN1...
FPGA
FPGA
Text is not SVG - cannot display
\ No newline at end of file + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + OFFLOAD FSM + + + + AXI REGISTERMAP + BYPASS + + S_AXIS + + AXI_MM + SOURCE + M_AXIS + + DESTINATION + + + M_STORAGE_AXIS + S_STORAGE_AXIS + + Storage Unit + + diff --git a/_images/block_diagram24.svg b/_images/block_diagram24.svg index f280e32f22..a130c28fe4 100644 --- a/_images/block_diagram24.svg +++ b/_images/block_diagram24.svg @@ -1,1910 +1,4 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - image/svg+xml - - - - - - - - - - DMA - DAC - - - - - din_data_0 [N:1] - din_enable_0 - din_valid_0 - - - - - din_data_1 [N:1] - din_enable_1 - din_valid_1 - - - - din_data_7 [N:1] - din_enable_7 - din_valid_7 - - - - din_unf - DMA_RESET - DMA_CLK - - - - - - - dout_data_0 [M:1] - dout_enable_0 - dout_valid_0 - - dout_unf - DAC_RESET - DAC_CLK - - - - - - - dout_data_1 [M:1] - dout_enable_1 - dout_valid_1 - - - - dout_data_7 [M:1] - dout_enable_7 - dout_valid_7 - - - - - - ASYNC_MEM - Data stream controller - WR_ADDR - DATA_VALID - - RD_ADDR - CLK_DAC - CLK_DMA - - - CLK_DMA - CLK_DAC - valid_[n] - - Clock Domain Crossing - CLK_DMA - CLK_DAC - - - - - - - - - - - - - - dout_enable [7:0] - dout_valid [7:0] - din_enable_n - din_valid_n - RFIFO - - - - 8x[N:1] - - - - 8x[M:1] - - dout_valid_0 - - - dout_valid [7:0] - - - - - - - WR_ADDR - RD_ADDR - - + + + +
MII/GMII
MII/GMII
RMII
RMII
mac_txd[3:0]
mac_txd[...
mac_tx_en
mac_tx_en
mac_tx_er
mac_tx_er
mii_col
mii_col
mii_crs
mii_crs
mii_rxd[3:0]
mii_rxd[...
mii_rx_clk
mii_rx_c...
mii_rx_dv
mii_rx_dv
mii_rx_er
mii_rx_er
mii_tx_clk
mii_tx_c...
util_mii_to_rmii
util_mii_t...
rmii_txd[1:0]
rmii_txd...
rmii_tx_en
rmii_tx_...
phy_crs_dv
phy_crs_...
phy_rxd[1:0]
phy_rxd[...
phy_rx_er
phy_rx_er
ref_clk
ref_clk
reset_n
reset_n
Zynq-7000/Zynq Ultrascale+ MPSoC - PS Gigabit Ethernet MAC
Zynq-7000/Zynq Ultra...
RMII ADIN1300 PHY
RMII ADIN1...
FPGA
FPGA
Text is not SVG - cannot display
\ No newline at end of file diff --git a/_images/block_diagram25.svg b/_images/block_diagram25.svg new file mode 100644 index 0000000000..f280e32f22 --- /dev/null +++ b/_images/block_diagram25.svg @@ -0,0 +1,1910 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + + DMA + DAC + + + + + din_data_0 [N:1] + din_enable_0 + din_valid_0 + + + + + din_data_1 [N:1] + din_enable_1 + din_valid_1 + + + + din_data_7 [N:1] + din_enable_7 + din_valid_7 + + + + din_unf + DMA_RESET + DMA_CLK + + + + + + + dout_data_0 [M:1] + dout_enable_0 + dout_valid_0 + + dout_unf + DAC_RESET + DAC_CLK + + + + + + + dout_data_1 [M:1] + dout_enable_1 + dout_valid_1 + + + + dout_data_7 [M:1] + dout_enable_7 + dout_valid_7 + + + + + + ASYNC_MEM + Data stream controller + WR_ADDR + DATA_VALID + + RD_ADDR + CLK_DAC + CLK_DMA + + + CLK_DMA + CLK_DAC + valid_[n] + + Clock Domain Crossing + CLK_DMA + CLK_DAC + + + + + + + + + + + + + + dout_enable [7:0] + dout_valid [7:0] + din_enable_n + din_valid_n + RFIFO + + + + 8x[N:1] + + + + 8x[M:1] + + dout_valid_0 + + + dout_valid [7:0] + + + + + + + WR_ADDR + RD_ADDR + + diff --git a/_images/block_diagram3.svg b/_images/block_diagram3.svg index d4688c36fa..b73c3a3951 100644 --- a/_images/block_diagram3.svg +++ b/_images/block_diagram3.svg @@ -1,4 +1,487 @@ - - - -
DMA_FIFO
DMA_FIFO
ADC
DATA
PROCESSING
ADC...
REGISTER
MAP
REGISTER...
AD7768
INTERFACE
AD7768...
AXI SLAVE
AXI SLAVE
ADC INTERFACE
ADC INTERFACE
Text is not SVG - cannot display
\ No newline at end of file + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + image/svg+xml + + + + + + + + + DB[15:0]WRn/RDn + + + + + INPUT + OUTPUT + + + + + + + + S_AXI_LITE + WR_FIFO + + REGISTERMAP + + + CONTROL  + PARALLEL INTERFACE + + BUSY + + burst_length + + + + + + + + 15:0 + adc_data + adc_valid + adc_sync + + diff --git a/_images/block_diagram4.svg b/_images/block_diagram4.svg index b1f995fda0..d4688c36fa 100644 --- a/_images/block_diagram4.svg +++ b/_images/block_diagram4.svg @@ -1,4 +1,4 @@ -
DMA_FIFO
DMA_FIFO
ADC
DATA
PROCESSING
ADC...
REGISTER
MAP
REGISTER...
AD777x
INTERFACE
AD777x...
AXI SLAVE
AXI SLAVE
ADC INTERFACE
ADC INTERFACE
Text is not SVG - cannot display
\ No newline at end of file +
DMA_FIFO
DMA_FIFO
ADC
DATA
PROCESSING
ADC...
REGISTER
MAP
REGISTER...
AD7768
INTERFACE
AD7768...
AXI SLAVE
AXI SLAVE
ADC INTERFACE
ADC INTERFACE
Text is not SVG - cannot display
\ No newline at end of file diff --git a/_images/block_diagram5.svg b/_images/block_diagram5.svg index 7d9659bc5a..b1f995fda0 100644 --- a/_images/block_diagram5.svg +++ b/_images/block_diagram5.svg @@ -1,289 +1,4 @@ - - - - - - - - - - - - - - - - image/svg+xml - - - - - - - - - - - - AXI SLAVE - - REGISTERMAP - - - LVDS INTERFACE - - - - - ADC DATAPROCESSING - - - LVDS - - DMA FIFO - - + + + +
DMA_FIFO
DMA_FIFO
ADC
DATA
PROCESSING
ADC...
REGISTER
MAP
REGISTER...
AD777x
INTERFACE
AD777x...
AXI SLAVE
AXI SLAVE
ADC INTERFACE
ADC INTERFACE
Text is not SVG - cannot display
\ No newline at end of file diff --git a/_images/block_diagram6.svg b/_images/block_diagram6.svg index 1db67d3b2c..7d9659bc5a 100644 --- a/_images/block_diagram6.svg +++ b/_images/block_diagram6.svg @@ -2,7 +2,6 @@ + sodipodi:docname="adc_lvds.svg" + inkscape:export-filename="D:\Git\ghdl\docs\block_diagrams\axi_ad9265\axi_ad9265.png" + inkscape:export-xdpi="400" + inkscape:export-ydpi="400"> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + inkscape:window-height="1058" + inkscape:window-x="3832" + inkscape:window-y="-8" + inkscape:window-maximized="1" + inkscape:snap-grids="true" + units="px" + fit-margin-top="0" + fit-margin-left="0" + fit-margin-right="0" + fit-margin-bottom="0"> + + id="grid5420" + originx="-13.131982" + originy="-164.43837" /> @@ -856,7 +88,7 @@ image/svg+xml - + @@ -864,910 +96,194 @@ inkscape:label="Layer 1" inkscape:groupmode="layer" id="layer1" - transform="translate(0,-552.36202)"> - - - + transform="translate(-13.131983,-537.92376)"> - - Register Map - - AD9361 INTERFACE LVDS/CMOS - - CLK_OUT - - FRAME_OUT - - DATA_OUT - - CLK_IN - - FRAME_IN + id="tspan4216" + x="108.82646" + y="336.35623" + style="font-size:20px" /> + + + + sodipodi:nodetypes="ccccccccc" /> DATA_IN + id="tspan4198" + x="35.742157" + y="647.38458" + style="font-size:10px">AXI SLAVE - - - - + style="opacity:1;fill:#d7d7d7;fill-opacity:0.35294118;fill-rule:nonzero;stroke:#000000;stroke-width:2.5;stroke-linecap:round;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" + id="rect4204" + width="72.5" + height="122.5" + x="139.0587" + y="591.32355" /> RX CHANNEL - - - - - - - - - - - - - - REGISTERIQ Corr - - + x="174.79601" + y="662.5296" + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-family:sans-serif;-inkscape-font-specification:'sans-serif Bold';text-align:center;text-anchor:middle" + id="tspan4251">MAP + id="g4357" + transform="translate(-13.89132,-73.70117)"> + y="797.44434" + x="152.72948" + height="122.5" + width="72.5" + id="rect4204-3" + style="opacity:1;fill:#d7d7d7;fill-opacity:0.35294118;fill-rule:nonzero;stroke:#000000;stroke-width:2.5;stroke-linecap:round;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" /> PNMON - - DC Filter - - - - - - - - RX CORE - - - - - - - - IQC - + id="tspan4251-9" + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-family:sans-serif;-inkscape-font-specification:'sans-serif Bold';text-align:center;text-anchor:middle" + y="856.15033" + x="190.17577" + sodipodi:role="line">LVDS INTERFACE - - - - - PRBS - PATTERN - DDS - DMA - - - - TX CHANNEL - - - - - TX CORE + id="tspan4297" + x="274.52353" + y="600.3385" /> + id="g4362" + transform="translate(-72.906712,199.45373)"> + y="445.14008" + x="300.43127" + height="122.2474" + width="88.072769" + id="rect4204-2" + style="opacity:1;fill:#d7d7d7;fill-opacity:0.35294118;fill-rule:nonzero;stroke:#000000;stroke-width:2.75260305;stroke-linecap:round;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" /> TDDCONTROL - - - - - - - - - - - + id="tspan4251-95" + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-family:sans-serif;-inkscape-font-specification:'sans-serif Bold';text-align:center;text-anchor:middle" + y="494.98859" + x="345.9368" + sodipodi:role="line">ADC DATAPROCESSING - - - - - - - - - DAC_FIFO_I0 - DAC_FIFO_Q0 - DAC_FIFO_I1 - DAC_FIFO_Q1 - ADC_FIFO_I0 - ADC_FIFO_Q0 - ADC_FIFO_I1 - ADC_FIFO_Q1 - - - + id="tspan4198-0" + x="42.579056" + y="784.05139" + style="font-size:10px">LVDS + S_AXI_MM - - - - - - + id="tspan4198-8" + x="353.8385" + y="701.73163" + style="font-size:10px">DMA FIFO diff --git a/_images/block_diagram7.svg b/_images/block_diagram7.svg index 7d9659bc5a..1db67d3b2c 100644 --- a/_images/block_diagram7.svg +++ b/_images/block_diagram7.svg @@ -2,6 +2,7 @@ + sodipodi:docname="axi_ad9361.svg"> - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + inkscape:window-width="1920" + inkscape:window-height="1005" + inkscape:window-x="1911" + inkscape:window-y="-9" + inkscape:window-maximized="1"> + id="grid4147" /> @@ -88,7 +856,7 @@ image/svg+xml - + @@ -96,194 +864,910 @@ inkscape:label="Layer 1" inkscape:groupmode="layer" id="layer1" - transform="translate(-13.131983,-537.92376)"> + transform="translate(0,-552.36202)"> + + + + + - - - + x="338.00705" + y="1002.5098" + id="tspan10800" + style="font-size:17.5px;text-align:center;text-anchor:middle">Register Map + + AD9361 INTERFACE LVDS/CMOS + sodipodi:nodetypes="cc" /> + CLK_OUT + + FRAME_OUT + + DATA_OUT + + CLK_IN + + FRAME_IN + AXI SLAVE + id="tspan4464-6" + x="601.59485" + y="914.18268" + style="font-size:15.00000095px">DATA_IN + style="fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:2;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" + id="rect4554-2" + width="275.68262" + height="200.67418" + x="241.4856" + y="782.63196" /> + + + + REGISTERRX CHANNEL + + + + + + + + + + + + + + MAP + id="tspan5432-7" + x="328.60651" + y="907.61011" + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:12.5px;font-family:Arial;-inkscape-font-specification:'Arial Bold';text-align:center;text-anchor:middle;stroke-width:1;stroke-miterlimit:4;stroke-dasharray:none">IQ Corr + + + style="shape-rendering:crispEdges" + id="g4581-2" + transform="translate(72.146239,261.17086)"> + transform="matrix(0,-1.1885989,1.1885989,0,-59.978473,-122.17314)" + y="367.16461" + x="-667.7301" + height="37.394592" + width="36.778587" + id="rect11202-0" + style="display:inline;opacity:1;fill:none;fill-opacity:1;fill-rule:nonzero;stroke:#a01414;stroke-width:0.84132671;stroke-linecap:round;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1;shape-rendering:crispEdges;enable-background:new" /> LVDS INTERFACE + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:12.5px;font-family:Arial;-inkscape-font-specification:'Arial Bold';text-align:center;text-anchor:middle" + y="646.26959" + x="398.66266" + id="tspan11368-8" + sodipodi:role="line">PNMON - DC Filter + + + + + + + + RX CORE + + + + + + + + IQC + + + + + + + PRBS + + id="tspan11628" + x="270.89429" + y="692.98926" + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-size:12.5px;font-family:Arial;-inkscape-font-specification:'Arial Bold';stroke-width:1;stroke-miterlimit:4;stroke-dasharray:none">PATTERN + DDS + DMA + + + + TX CHANNEL + + + + + TX CORE + id="g7938" + transform="translate(-16.000001,194)"> + y="552.77344" + x="126.2047" + height="72.407516" + width="113.65318" + id="rect4554-2-5-6" + style="fill:none;fill-rule:evenodd;stroke:#000000;stroke-width:2;stroke-linecap:butt;stroke-linejoin:miter;stroke-miterlimit:4;stroke-dasharray:none;stroke-opacity:1" /> ADC DATAPROCESSING + style="font-size:17.5px;text-align:center;text-anchor:middle" + y="584.26892" + x="182.5314" + id="tspan7449" + sodipodi:role="line">TDDCONTROL + + + + + + + + + + + + + + + + + + + + LVDS - + id="tspan7846" + x="96.700409" + y="614.9624">DAC_FIFO_I0 DMA FIFO + id="tspan7846-3" + x="93.961151" + y="653.88196">DAC_FIFO_Q0 + DAC_FIFO_I1 + DAC_FIFO_Q1 + ADC_FIFO_I0 + ADC_FIFO_Q0 + ADC_FIFO_I1 + ADC_FIFO_Q1 + + + + S_AXI_MM + + + + + + diff --git a/_images/block_diagram8.svg b/_images/block_diagram8.svg index 081ca4a14c..7d9659bc5a 100644 --- a/_images/block_diagram8.svg +++ b/_images/block_diagram8.svg @@ -9,17 +9,16 @@ xmlns="http://www.w3.org/2000/svg" xmlns:sodipodi="http://sodipodi.sourceforge.net/DTD/sodipodi-0.dtd" xmlns:inkscape="http://www.inkscape.org/namespaces/inkscape" - width="100%" - height="100%" + width="425" + height="350" + viewBox="0 0 425 350" id="svg2" version="1.1" inkscape:version="0.91 r13725" - sodipodi:docname="adc_jesd.svg" + sodipodi:docname="adc_lvds.svg" inkscape:export-filename="D:\Git\ghdl\docs\block_diagrams\axi_ad9265\axi_ad9265.png" inkscape:export-xdpi="400" - inkscape:export-ydpi="400" - viewBox="0 0 425 350" - preserveAspectRatio="xMidYMid slice"> + inkscape:export-ydpi="400"> image/svg+xml - + @@ -181,35 +180,20 @@ JESD LINK TO DMADATA ORDERING LVDS + id="tspan4369">INTERFACE ADC DATAPROCESSING&PRBS MONITORING + y="519.98859" + x="344.22781" + sodipodi:role="line">PROCESSING JESD FIFO + style="font-size:10px">LVDS + inkscape:version="0.91 r13725" + sodipodi:docname="adc_jesd.svg" + inkscape:export-filename="D:\Git\ghdl\docs\block_diagrams\axi_ad9265\axi_ad9265.png" + inkscape:export-xdpi="400" + inkscape:export-ydpi="400" + viewBox="0 0 425 350" + preserveAspectRatio="xMidYMid slice"> - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + id="grid5420" + originx="-13.131982" + originy="-164.43837" /> @@ -936,6 +89,7 @@ image/svg+xml + @@ -943,477 +97,224 @@ inkscape:label="Layer 1" inkscape:groupmode="layer" id="layer1" - transform="translate(-18.205785,-566.84345)"> - + transform="translate(-13.131983,-537.92376)">   -   -   -   - - Register Map - - AD9783 LVDS INTERFACE - - CLK_IN_P + id="tspan4216" + x="108.82646" + y="336.35623" + style="font-size:20px" /> + + + + sodipodi:nodetypes="ccccccccc" /> CLK_IN_N + id="tspan4198" + x="35.742157" + y="647.38458" + style="font-size:10px">AXI SLAVE - - - - - - PRBS + style="opacity:1;fill:#d7d7d7;fill-opacity:0.35294118;fill-rule:nonzero;stroke:#000000;stroke-width:2.5;stroke-linecap:round;stroke-linejoin:round;stroke-miterlimit:4;stroke-dasharray:none;stroke-dashoffset:0;stroke-opacity:1" + id="rect4204" + width="72.5" + height="122.5" + x="139.0587" + y="591.32355" /> DDS - REGISTERDMA - - - TX CHANNEL - - - TX CORE - + x="174.79601" + y="662.5296" + style="font-style:normal;font-variant:normal;font-weight:bold;font-stretch:normal;font-family:sans-serif;-inkscape-font-specification:'sans-serif Bold';text-align:center;text-anchor:middle" + id="tspan4251">MAP - - + id="g4357" + transform="translate(-13.89132,-73.70117)"> + + JESD LINK TO DMADATA ORDERING - 64b - - - - 64b - DAC_DMA_I - DAC_DMA_Q -   + id="tspan4297" + x="274.52353" + y="600.3385" /> - + id="g4362" + transform="translate(-72.906712,199.45373)"> + + ADC DATAPROCESSING&PRBS MONITORING - S_AXI_MM - - AXI_AD9783 + sodipodi:nodetypes="ccccccccc" /> CLK_OUT_P + id="tspan4198-0" + x="42.579056" + y="784.05139" + style="font-size:10px">JESD FIFO - CLK_OUT_N - - - - 16b - - - - 16b - DAC_OUT_P + sodipodi:nodetypes="ccccccccc" /> DAC_OUT_N + id="tspan4198-8" + x="353.8385" + y="701.73163" + style="font-size:10px">DMA FIFO diff --git a/genindex.html b/genindex.html index 8023e9fc82..d3aaccd9ae 100644 --- a/genindex.html +++ b/genindex.html @@ -185,6 +185,7 @@
  • AXI AD3552R
  • +
  • AXI AD408x
  • AXI AD485x
  • AXI AD7606x
  • AXI AD7616
  • @@ -234,6 +235,7 @@
  • AXI AD3552R
  • +
  • AXI AD408x
  • AXI AD485x
  • AXI AD7606x
  • AXI AD7616
  • @@ -244,6 +245,7 @@
    • AD-GMSL2ETH-SL
    • AD3552R-EVB
    • +
    • AD408X-FMC-EVB
    • AD4110-SDZ
    • AD411x-AD717x
    • AD4134-FMC
    • @@ -251,6 +253,7 @@
    • AD4630-FMC/AD4030-FMC/ADAQ4224-FMC
    • AD469X-FMC
    • AD485X-FMCZ
    • +
    • AD57XX-ARDZ
    • AD5758-SDZ
    • AD5766-SDZ
    • AD7124-4-ASDZ/AD7124-8-ASDZ
    • @@ -353,6 +356,7 @@

      ContentsADC/DAC
      • AXI AD3552R
      • +
      • AXI AD408x
      • AXI AD485x
      • AXI AD7606x
      • AXI AD7616
      • @@ -415,6 +419,7 @@

        ContentsProjects
      • AXI AD3552R
      • +
      • AXI AD408x
      • AXI AD485x
      • AXI AD7606x
      • AXI AD7616
      • @@ -254,6 +255,7 @@
        • AD-GMSL2ETH-SL
        • AD3552R-EVB
        • +
        • AD408X-FMC-EVB
        • AD4110-SDZ
        • AD411x-AD717x
        • AD4134-FMC
        • @@ -261,6 +263,7 @@
        • AD4630-FMC/AD4030-FMC/ADAQ4224-FMC
        • AD469X-FMC
        • AD485X-FMCZ
        • +
        • AD57XX-ARDZ
        • AD5758-SDZ
        • AD5766-SDZ
        • AD7124-4-ASDZ/AD7124-8-ASDZ
        • @@ -2565,7 +2568,7 @@

          References   - + diff --git a/library/axi_ad408x/index.html b/library/axi_ad408x/index.html new file mode 100644 index 0000000000..af06d2efe1 --- /dev/null +++ b/library/axi_ad408x/index.html @@ -0,0 +1,2518 @@ + + + + + + + + AXI AD408x — HDL documentation + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
          +
          + + + +
          +
          + + +
          +
          + +
          + +
          + + + + + + + + +
          +
          +
          +
          + +
          +

          AXI AD408x#

          +

          The AXI AD408x IP core can be used to interface +the AD4080 device. +This documentation only covers the IP core and requires one to be +familiar with the device, for a complete and better understanding.

          +

          More about the generic framework interfacing ADCs can be read in Generic AXI ADC.

          +
          +

          Features#

          +
            +
          • AXI Lite control/status interface

          • +
          • Programmable line delays

          • +
          • DDR data stream selection

          • +
          • Single/dual lane data stream selection

          • +
          • Bit-slip capability for synchronization

          • +
          • Filtered data support

          • +
          • Programmable decimation rate support

          • +
          • Xilinx devices compatible

          • +
          +
          +
          +

          Files#

          +
          + + + + + + + + + + + + + + + + + +

          Name

          Description

          library/axi_ad408x/axi_ad408x.v

          Verilog source for the AXI AD408x.

          library/axi_ad408x/ad408x_phy.v

          Verilog source for the AXI AD408x physical interface.

          library/axi_ad408x/axi_ad408x_ip.tcl

          IP definition file (AMD tools)

          +
          +
          +
          +

          Block Diagram#

          +AXI AD408x block diagram
          +
          +

          Configuration Parameters#

          +
          +
          + + + + + + + + + + + + + + + + + + + + +

          Name

          Description

          Default Value

          Choices/Range

          ID
          +

          Core ID should be unique for each IP in the system

          +
          +
          0

          FPGA_TECHNOLOGY
          +

          Used to select between FPGA devices, auto set in project.

          +
          +
          0

          Unknown (0), 7series (1), ultrascale (2), ultrascale+ (3), versal (4)

          +
          +
          +
          +
          +

          Interface#

          +
          +
          +
          +
          + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

          Physical Port

          Logical Port

          Direction

          Dependency

          s_axi_awaddrAWADDR

          in [15:0]

          s_axi_awprotAWPROT

          in [2:0]

          s_axi_awvalidAWVALID

          in

          s_axi_awreadyAWREADY

          out

          s_axi_wdataWDATA

          in [31:0]

          s_axi_wstrbWSTRB

          in [3:0]

          s_axi_wvalidWVALID

          in

          s_axi_wreadyWREADY

          out

          s_axi_brespBRESP

          out [1:0]

          s_axi_bvalidBVALID

          out

          s_axi_breadyBREADY

          in

          s_axi_araddrARADDR

          in [15:0]

          s_axi_arprotARPROT

          in [2:0]

          s_axi_arvalidARVALID

          in

          s_axi_arreadyARREADY

          out

          s_axi_rdataRDATA

          out [31:0]

          s_axi_rrespRRESP

          out [1:0]

          s_axi_rvalidRVALID

          out

          s_axi_rreadyRREADY

          in

          +
          +
          +
          +
          +
          +
          +
          +
          + + + + + + + + + + + + + + + +

          Physical Port

          Logical Port

          Direction

          Dependency

          s_axi_aclkCLK

          in

          +
          +
          +
          +
          +
          +
          +
          +
          + + + + + + + + + + + + + + + +

          Physical Port

          Logical Port

          Direction

          Dependency

          s_axi_aresetnRST

          in

          +
          +
          +
          +
          +
          +
          +
          +
          + + + + + + + + + + + + + + + +

          Physical Port

          Logical Port

          Direction

          Dependency

          adc_clkCLK

          out

          +
          +
          +
          +
          +
          +
          +
          +
          + + + + + + + + + + + + + + + +

          Physical Port

          Logical Port

          Direction

          Dependency

          delay_clkCLK

          in

          +
          +
          +
          +
          +
          +
          +
          +
          + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

          Physical Port

          Direction

          Dependency

          Description

          dclk_in_p

          in

          +

          LVDS input positive side of differential reference clock signal

          +
          +
          dclk_in_n

          in

          +

          LVDS input negative side of differential reference clock signal

          +
          +
          data_a_in_p

          in

          +

          LVDS input positive side of differential data line A signal

          +
          +
          data_a_in_n

          in

          +

          LVDS input negative side of differential data line A signal

          +
          +
          data_b_in_p

          in

          +

          LVDS input positive side of differential data line B signal

          +
          +
          data_b_in_n

          in

          +

          LVDS input negative side of differential data line B signal

          +
          +
          cnv_in_p

          in

          +

          LVDS input positive side of differential CNV signal

          +
          +
          cnv_in_n

          in

          +

          LVDS input negative side of differential CNV signal

          +
          +
          sync_n

          in

          +

          Signals when the clock is disabled and the design should be in reset

          +
          +
          filter_data_ready_n

          in

          +

          Signals when the filtered data is ready at the interface

          +
          +
          adc_data

          out [31:0]

          +

          Received data output

          +
          +
          adc_valid

          out

          +

          Indicates valid data

          +
          +
          adc_dovf

          in

          +

          Data overflow. Must be connected to the DMA

          +
          +
          +
          +
          +
          +
          +
          +

          Internal Interface Description#

          +

          The axi_ad408x operates as follows:

          +
            +
          • The LVDS data is deserialized by the +ad_serdes_in module with +a 1:8 ratio.

          • +
          • After deserialization, the data is sent to the +ad_pack module, which packs the 8-bit +data into a 20-bit format.

          • +
          • When the bit-slip (synchronization process) is enabled, the software +configures the ADC to output a fixed pattern, and the interface module will +adjust the data alignment until the pattern is captured.

          • +
          • When the filter is enabled, the adc_valid signal is gated by the +filter_data_ready_n signal, and the data is sent to the output only when the +filtered data is available.

          • +
          +
          +
          +
          +

          Register Map#

          +

          The register map of the core contains instances of several generic register maps +like ADC common, ADC channel, +up_delay_cntrl. +The following table presents the base addresses of each instance, after it you +can find the detailed description of each generic register map.

          +

          The absolute address of a register should be calculated by adding the instance +base address to the registers relative address.

          +
          + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
          Register Map base addresses for axi_ad408x#

          DWORD

          BYTE

          Name

          Description

          0x0000

          0x0000

          BASE

          See the Base table for more details.

          0x0000

          0x0000

          RX COMMON

          See the ADC Common table for more details.

          0x0000

          0x0000

          RX CHANNELS

          See the ADC Channel table for more details.

          0x0000

          0x0800

          IO_DELAY_CNTRL

          See the I/O Delay Control table for more details.

          +
          +
          +
          +
          +
          +
          + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

          DWORD

          BYTE

          Reg Name

          Description

          BITS

          Field Name

          Type

          Default Value

          Description

          0x00x0VERSION
          +

          Version and Scratch Registers

          +
          +

          [31:0]VERSIONRO0x00000000
          +

          Version number. Unique to all cores.

          +
          +
          0x10x4ID
          +

          Version and Scratch Registers

          +
          +

          [31:0]IDRO0x00000000
          +

          Instance identifier number.

          +
          +
          0x20x8SCRATCH
          +

          Version and Scratch Registers

          +
          +

          [31:0]SCRATCHRW0x00000000
          +

          Scratch register.

          +
          +
          0x30xcCONFIG
          +

          Version and Scratch Registers

          +
          +

          [0:0]IQCORRECTION_DISABLERO0x0
          +

          If set, indicates that the IQ Correction module was not implemented. (as a result of a configuration of the IP instance)

          +
          +

          [1:1]DCFILTER_DISABLERO0x0
          +

          If set, indicates that the DC Filter module was not implemented. (as a result of a configuration of the IP instance)

          +
          +

          [2:2]DATAFORMAT_DISABLERO0x0
          +

          If set, indicates that the Data Format module was not implemented. (as a result of a configuration of the IP instance)

          +
          +

          [3:3]USERPORTS_DISABLERO0x0
          +

          If set, indicates that the logic related to the User Data Format (e.g. decimation) was not implemented. (as a result of a configuration of the IP instance)

          +
          +

          [4:4]MODE_1R1TRO0x0
          +

          If set, indicates that the core was implemented in 1 channel mode. (e.g. refer to AD9361 data sheet)

          +
          +

          [5:5]DELAY_CONTROL_DISABLERO0x0
          +

          If set, indicates that the delay control is disabled for this IP. (as a result of a configuration of the IP instance)

          +
          +

          [6:6]DDS_DISABLERO0x0
          +

          If set, indicates that the DDS is disabled for this IP. (as a result of a configuration of the IP instance)

          +
          +

          [7:7]CMOS_OR_LVDS_NRO0x0
          +

          CMOS or LVDS mode is used for the interface. (as a result of a configuration of the IP instance)

          +
          +

          [8:8]PPS_RECEIVER_ENABLERO0x0
          +

          If set, indicates the PPS receiver is enabled. (as a result of a configuration of the IP instance)

          +
          +

          [9:9]SCALECORRECTION_ONLYRO0x0
          +

          If set, indicates that the IQ Correction module implements only scale correction. +IQ correction must be enabled. (as a result of a configuration of the IP instance)

          +
          +

          [12:12]EXT_SYNCRO0x0
          +

          If set the transport layer cores (ADC/DAC) have implemented the support for external synchronization signal.

          +
          +

          [13:13]RD_RAW_DATARO0x0
          +

          If set, the ADC has the capability to read raw data in register CHAN_RAW_DATA from adc_channel.

          +
          +
          0x40x10PPS_IRQ_MASK
          +

          PPS Interrupt mask

          +
          +

          [0:0]PPS_IRQ_MASKRW0x1
          +

          Mask bit for the 1PPS receiver interrupt

          +
          +
          0x70x1cFPGA_INFO
          +

          FPGA device information +library/scripts/adi_intel_device_info_enc.tcl (Intel encoded values) +library/scripts/adi_xilinx_device_info_enc.tcl (Xilinx encoded values)

          +
          +

          [31:24]FPGA_TECHNOLOGYRO0x00
          +

          Encoded value describing the technology/generation of the FPGA device (arria 10/7series)

          +
          +

          [23:16]FPGA_FAMILYRO0x00
          +

          Encoded value describing the family variant of the FPGA device(e.g., SX, GX, GT or zynq, kintex, virtex)

          +
          +

          [15:8]SPEED_GRADERO0x00
          +

          Encoded value describing the FPGA’s speed-grade

          +
          +

          [7:0]DEV_PACKAGERO0x00
          +

          Encoded value describing the device package. The package might affect high-speed interfaces

          +
          +
          +
          +
          +
          +
          +
          +
          +
          +
          +
          +
          + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

          DWORD

          BYTE

          Reg Name

          Description

          BITS

          Field Name

          Type

          Default Value

          Description

          0x100x40RSTN
          +

          ADC Interface Control & Status

          +
          +

          [2:2]CE_NRW0x0
          +

          Clock enable, default is enabled(0x0). An inverse version of the signal is exported out of +the module to control clock enables

          +
          +

          [1:1]MMCM_RSTNRW0x0
          +

          MMCM reset only (required for DRP access). +Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.

          +
          +

          [0:0]RSTNRW0x0
          +

          Reset, default is IN-RESET (0x0), software must write 0x1 to bring up the core.

          +
          +
          0x110x44CNTRL
          +

          ADC Interface Control & Status

          +
          +

          [16:16]SDR_DDR_NRW0x0
          +

          Interface type (1 represents SDR, 0 represents DDR)

          +
          +

          [15:15]SYMB_OPRW0x0
          +

          Select symbol data format mode (0x1)

          +
          +

          [14:14]SYMB_8_16BRW0x0
          +

          Select number of bits for symbol format mode (1 represents 8b, 0 represents 16b)

          +
          +

          [12:8]NUM_LANESRW0x00
          +

          Number of active lanes (1 : CSSI 1-lane, LSSI 1-lane, 2 : LSSI 2-lane, 4 : CSSI 4-lane). +For AD7768, AD7768-4 and AD777x number of active lanes : 1/2/4/8 where supported.

          +
          +

          [3:3]SYNCRW0x0
          +

          Initialize synchronization between multiple ADCs

          +
          +

          [2:2]R1_MODERW0x0
          +

          Select number of RF channels 1 (0x1) or 2 (0x0).

          +
          +

          [1:1]DDR_EDGESELRW0x0
          +

          Select rising edge (0x0) or falling edge (0x1) for the first part +of a sample (if applicable) followed by the successive edges for +the remaining parts. This only controls how the sample is delineated +from the incoming data post DDR registers.

          +
          +

          [0:0]PIN_MODERW0x0
          +

          Select interface pin mode to be clock multiplexed (0x1) or pin +multiplexed (0x0). In clock multiplexed mode, samples are received +on alternative clock edges. In pin multiplexed mode, samples are +interleaved or grouped on the pins at the same clock edge.

          +
          +
          0x120x48CNTRL_2
          +

          ADC Interface Control & Status

          +
          +

          [1:1]EXT_SYNC_ARMRW0x0
          +

          Setting this bit will arm the trigger mechanism sensitive to an external sync signal. +Once the external sync signal goes high it synchronizes channels within a ADC, and across multiple instances. +This bit has an effect only the EXT_SYNC synthesis parameter is set. +This bit self clears.

          +
          +

          [2:2]EXT_SYNC_DISARMRW0x0
          +

          Setting this bit will disarm the trigger mechanism sensitive to an external sync signal. +This bit has an effect only the EXT_SYNC synthesis parameter is set. +This bit self clears.

          +
          +

          [8:8]MANUAL_SYNC_REQUESTRW0x0
          +

          Setting this bit will issue an external sync event if it is hooked up inside the fabric. +This bit has an effect only the EXT_SYNC synthesis parameter is set. +This bit self clears.

          +
          +
          0x130x4cCNTRL_3
          +

          ADC Interface Control & Status

          +
          +

          [8:8]CRC_ENRW0x0
          +

          Setting this bit will enable the CRC generation.

          +
          +

          [7:0]CUSTOM_CONTROLRW0x00
          +

          Select output format decode mode.(for ADAQ8092: bit 0 - enables digital output randomizer decode +, bit 1 - enables alternate bit polarity decode).

          +
          +
          0x150x54CLK_FREQ
          +

          ADC Interface Control & Status

          +
          +

          [31:0]CLK_FREQRO0x00000000
          +

          Interface clock frequency. This is relative to the processor clock and in many cases is +100MHz. The number is represented as unsigned 16.16 format. Assuming a 100MHz processor +clock the minimum is 1.523kHz and maximum is 6.554THz. The actual interface clock +is CLK_FREQ * CLK_RATIO (see below). Note that the actual sampling clock may not be +the same as the interface clock- software must consider device specific implementation +parameters to calculate the final sampling clock.

          +
          +
          0x160x58CLK_RATIO
          +

          ADC Interface Control & Status

          +
          +

          [31:0]CLK_RATIORO0x00000000
          +

          Interface clock ratio - as a factor actual received clock. This is implementation specific +and depends on any serial to parallel conversion and interface type (ddr/sdr/qdr).

          +
          +
          0x170x5cSTATUS
          +

          ADC Interface Control & Status

          +
          +

          [4:4]ADC_CTRL_STATUSRO0x0
          +

          If set, indicates that the device’​s register data is available on the data bus.

          +
          +

          [3:3]PN_ERRRO0x0
          +

          If set, indicates pn error in one or more channels.

          +
          +

          [2:2]PN_OOSRO0x0
          +

          If set, indicates pn oos in one or more channels.

          +
          +

          [1:1]OVER_RANGERO0x0
          +

          If set, indicates over range in one or more channels.

          +
          +

          [0:0]STATUSRO0x0
          +

          Interface status, if set indicates no errors. If not set, there +are errors, software may try resetting the cores.

          +
          +
          0x180x60DELAY_CNTRL
          +

          ADC Interface Control & Status(Deprecated from version 9)

          +
          +

          [17:17]DELAY_SELRW0x0
          +

          Delay select, a 0x0 to 0x1 transition in this register initiates +a delay access controlled by the registers below.

          +
          +

          [16:16]DELAY_RWNRW0x0
          +

          Delay read (0x1) or write (0x0), the delay is accessed directly +(no increment or decrement) with an address corresponding to each pin, +and data corresponding to the total delay.

          +
          +

          [15:8]DELAY_ADDRESSRW0x00
          +

          Delay address, the range depends on the interface pins, data pins +are usually at the lower range.

          +
          +

          [4:0]DELAY_WDATARW0x00
          +

          Delay write data, a value of 1 corresponds to (1/200)ns for most devices.

          +
          +
          0x190x64DELAY_STATUS
          +

          ADC Interface Control & Status(Deprecated from version 9)

          +
          +

          [9:9]DELAY_LOCKEDRO0x0
          +

          Indicates delay locked (0x1) state. If this bit is read 0x0, delay control +has failed to calibrate the elements.

          +
          +

          [8:8]DELAY_STATUSRO0x0
          +

          If set, indicates busy status (access pending). The read data may not be +valid if this bit is set.

          +
          +

          [4:0]DELAY_RDATARO0x00
          +

          Delay read data, current delay value in the elements

          +
          +
          0x1a0x68SYNC_STATUS
          +

          ADC Synchronization Status register

          +
          +

          [0:0]ADC_SYNCRO0x0
          +

          ADC synchronization status. Will be set to 1 after the synchronization has been completed +or while waiting for the synchronization signal in JESD204 systems.

          +
          +
          0x1c0x70DRP_CNTRL
          +

          ADC Interface Control & Status

          +
          +

          [28:28]DRP_RWNRW0x0
          +

          DRP read (0x1) or write (0x0) select (does not include GTX lanes). +NOT-APPLICABLE if DRP_DISABLE is set (0x1).

          +
          +

          [27:16]DRP_ADDRESSRW0x000
          +

          DRP address, designs that contain more than one DRP accessible primitives +have selects based on the most significant bits (does not include GTX lanes). +NOT-APPLICABLE if DRP_DISABLE is set (0x1).

          +
          +

          [15:0]RESERVEDRO0x0000
          +

          Reserved for backward compatibility.

          +
          +
          0x1d0x74DRP_STATUS
          +

          ADC Interface Control & Status

          +
          +

          [17:17]DRP_LOCKEDRO0x0
          +

          If set indicates that the DRP has been locked.

          +
          +

          [16:16]DRP_STATUSRO0x0
          +

          If set indicates busy (access pending). The read data may not be valid if +this bit is set (does not include GTX lanes). +NOT-APPLICABLE if DRP_DISABLE is set (0x1).

          +
          +

          [15:0]RESERVEDRO0x0000
          +

          Reserved for backward compatibility.

          +
          +
          0x1e0x78DRP_WDATA
          +

          ADC DRP Write Data

          +
          +

          [15:0]DRP_WDATARW0x0000
          +

          DRP write data (does not include GTX lanes). +NOT-APPLICABLE if DRP_DISABLE is set (0x1).

          +
          +
          0x1f0x7cDRP_RDATA
          +

          ADC DRP Read Data

          +
          +

          [15:0]DRP_RDATARO0x0000
          +

          DRP read data (does not include GTX lanes).

          +
          +
          0x200x80ADC_CONFIG_WR
          +

          ADC Write Configuration ​Data

          +
          +

          [31:0]ADC_CONFIG_WRRW0x00000000
          +

          Custom ​Write to the available registers.

          +
          +
          0x210x84ADC_CONFIG_RD
          +

          ADC Read Configuration ​Data

          +
          +

          [31:0]ADC_CONFIG_RDRO0x00000000
          +

          Custom read of the available registers.

          +
          +
          0x220x88UI_STATUS
          +

          User Interface Status

          +
          +

          [2:2]UI_OVFRW1C0x0
          +

          User Interface overflow. If set, indicates an overflow occurred during data transfer at +the user interface (FIFO interface). Software must write a 0x1 to clear this register +bit.

          +
          +

          [1:1]UI_UNFRW1C0x0
          +

          User Interface underflow. If set, indicates an underflow occurred during data transfer at +the user interface (FIFO interface). Software must write a 0x1 to clear this register +bit.

          +
          +

          [0:0]UI_RESERVEDRW1C0x0
          +

          Reserved for backward compatibility.

          +
          +
          0x230x8cADC_CONFIG_CTRL
          +

          ADC RD/WR configuration

          +
          +

          [31:0]ADC_CONFIG_CTRLRW0x00000000
          +

          Control RD/WR requests to the device’​s register map: bit 1 - RD (‘b1) , WR (‘b0), bit 0 - enable WR/RD operation.

          +
          +
          0x280xa0USR_CNTRL_1
          +

          ADC Interface Control & Status

          +
          +

          [7:0]USR_CHANMAXRW0x00
          +

          This indicates the maximum number of inputs for the channel data multiplexers. User may add +different processing modules post data capture as another input to this common multiplexer. +NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

          +
          +
          0x290xa4ADC_START_CODE
          +

          ADC Synchronization start word

          +
          +

          [31:0]ADC_START_CODERW0x00000000
          +

          This sets the startcode that is used by the ADCs for synchronization +NOT-APPLICABLE if START_CODE_DISABLE is set (0x1).

          +
          +
          0x2e0xb8ADC_GPIO_IN
          +

          ADC GPIO inputs

          +
          +

          [31:0]ADC_GPIO_INRO0x00000000
          +

          This reads auxiliary GPI pins of the ADC core

          +
          +
          0x2f0xbcADC_GPIO_OUT
          +

          ADC GPIO outputs

          +
          +

          [31:0]ADC_GPIO_OUTRW0x00000000
          +

          This controls auxiliary GPO pins of the ADC core +NOT-APPLICABLE if GPIO_DISABLE is set (0x1).

          +
          +
          0x300xc0PPS_COUNTER
          +

          PPS Counter register

          +
          +

          [31:0]PPS_COUNTERRO0x00000000
          +

          Counts the core clock cycles (can be a device clock or interface clock) between two 1PPS pulse.

          +
          +
          0x310xc4PPS_STATUS
          +

          PPS Status register

          +
          +

          [0:0]PPS_STATUSRO0x0
          +

          If this bit is asserted there is no incomming 1PPS signal. Maybe the source is out of sync or it’s not active.

          +
          +
          +
          +
          +
          +
          +
          +
          +
          +
          +
          +
          + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

          DWORD

          BYTE

          Reg Name

          Description

          BITS

          Field Name

          Type

          Default Value

          Description

          0x100 + 0x16*n0x400 + 0x58*nCHAN_CNTRLn
          +

          ADC Interface Control & Status +Where n is from 0 to 15.

          +
          +

          [11:11]ADC_LB_OWRRW0x0
          +

          If set, forces ADC_DATA_SEL to 1, enabling data loopback

          +
          +

          [10:10]ADC_PN_SEL_OWRRW0x0
          +

          If set, forces ADC_PN_SEL to 0x9, device specific pn (e.g. ad9361) +If both ADC_PN_TYPE_OWR and ADC_PN_SEL_OWR are set, they are ignored

          +
          +

          [9:9]IQCOR_ENBRW0x0
          +

          if set, enables IQ correction or scale correction. +NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).

          +
          +

          [8:8]DCFILT_ENBRW0x0
          +

          if set, enables DC filter (to disable DC offset, set offset value to 0x0). +NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1).

          +
          +

          [6:6]FORMAT_SIGNEXTRW0x0
          +

          if set, enables sign extension (applicable only in 2’s complement mode). The data is +always sign extended to the nearest byte boundary. +NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1).

          +
          +

          [5:5]FORMAT_TYPERW0x0
          +

          Select offset binary (0x1) or 2’s complement (0x0) data type. This sets the incoming +data type and is required by the post processing modules for any data conversion. +NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1).

          +
          +

          [4:4]FORMAT_ENABLERW0x0
          +

          Enable data format conversion (see register bits above). +NOT-APPLICABLE if DATAFORMAT_DISABLE is set (0x1).

          +
          +

          [3:3]RESERVEDRO0x0
          +

          Reserved for backward compatibility.

          +
          +

          [2:2]RESERVEDRO0x0
          +

          Reserved for backward compatibility.

          +
          +

          [1:1]ADC_PN_TYPE_OWRRW0x0
          +

          If set, forces ADC_PN_SEL to 0x1, modified pn23 +If both ADC_PN_TYPE_OWR and ADC_PN_SEL_OWR are set, they are ignored

          +
          +

          [0:0]ENABLERW0x0
          +

          If set, enables channel. A 0x0 to 0x1 transition transfers all the control signals +to the respective channel processing module. If a channel is part of a complex +signal (I/Q), even channel is the master and the odd channel is the slave. +Though a single control is used, both must be individually selected.

          +
          +
          0x101 + 0x16*n0x404 + 0x58*nCHAN_STATUSn
          +

          ADC Interface Control & Status +Where n is from 0 to 15.

          +
          +

          [12:12]CRC_ERRRW1C0x0
          +

          CRC errors. If set, indicates CRC error. Software must first clear this bit before initiating a transfer and monitor afterwards.

          +
          +

          [11:4]STATUS_HEADERRO0x00
          +

          The status header sent by the ADC.(compatible with AD7768/AD7768-4/AD777x).

          +
          +

          [2:2]PN_ERRRW1C0x0
          +

          PN errors. If set, indicates spurious mismatches in sync state. This bit is cleared +if OOS is set and is only indicates errors when OOS is cleared.

          +
          +

          [1:1]PN_OOSRW1C0x0
          +

          PN Out Of Sync. If set, indicates an OOS status. OOS is set, if 64 consecutive patterns +mismatch from the expected pattern. It is cleared, when 16 consecutive patterns match +the expected pattern.

          +
          +

          [0:0]OVER_RANGERW1C0x0
          +

          If set, indicates over range. Note that over range is independent of the data path, +it indicates an over range over a data transfer period. Software must first clear +this bit before initiating a transfer and monitor afterwards.

          +
          +
          0x102 + 0x16*n0x408 + 0x58*nCHAN_RAW_DATAn
          +

          ADC Raw Data Reading +Where n is from 0 to 15.

          +
          +

          [31:0]ADC_READ_DATARO0x00000000
          +

          Raw data read from the ADC.

          +
          +
          0x104 + 0x16*n0x410 + 0x58*nCHAN_CNTRLn_1
          +

          ADC Interface Control & Status +Where n is from 0 to 15.

          +
          +

          [31:16]DCFILT_OFFSETRW0x0000
          +

          DC removal (if equipped) offset. This is a 2’s complement number added to the incoming +data to remove a known DC offset. +NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1).

          +
          +

          [15:0]DCFILT_COEFFRW0x0000
          +

          DC removal filter (if equipped) coefficient. The format is 1.1.14 (sign, integer and +fractional bits). +NOT-APPLICABLE if DCFILTER_DISABLE is set (0x1).

          +
          +
          0x105 + 0x16*n0x414 + 0x58*nCHAN_CNTRLn_2
          +

          ADC Interface Control & Status +Where n is from 0 to 15.

          +
          +

          [31:16]IQCOR_COEFF_1RW0x0000
          +

          IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the scale value +and the format is 1.1.14 (sign, integer and fractional bits). If matrix multiplication is used, +this is the channel I coefficient and the format is 1.1.14 (sign, integer and fractional bits). +If SCALECORRECTION_ONLY is set, this implements the scale value correction for the current channel +with the format 1.1.14 (sign, integer and fractional bits). +NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).

          +
          +

          [15:0]IQCOR_COEFF_2RW0x0000
          +

          IQ correction (if equipped) coefficient. If scale & offset is implemented, this is the offset value +and the format is 2’s complement. If matrix multiplication is used, this is the channel Q coefficient +and the format is 1.1.14 (sign, integer and fractional bits). +NOT-APPLICABLE if IQCORRECTION_DISABLE is set (0x1).

          +
          +
          0x106 + 0x16*n0x418 + 0x58*nCHAN_CNTRLn_3
          +

          ADC Interface Control & Status +Where n is from 0 to 15.

          +
          +

          [19:16]ADC_PN_SELRW0x0
          +

          Selects the PN monitor sequence type (available only if ADC supports it).

          +
            +
          • 0x0: pn9a (device specific, modified pn9)

          • +
          • 0x1: pn23a (device specific, modified pn23)

          • +
          • 0x4: pn7 (standard O.150)

          • +
          • 0x5: pn15 (standard O.150)

          • +
          • 0x6: pn23 (standard O.150)

          • +
          • 0x7: pn31 (standard O.150)

          • +
          • 0x9: pnX (device specific, e.g. ad9361)

          • +
          • 0x0A: Nibble ramp (Device specific e.g. adrv9001)

          • +
          • 0x0B: 16 bit ramp (Device specific e.g. adrv9001)

          • +
          +
          +

          [3:0]ADC_DATA_SELRW0x0
          +

          Selects the data source to DMA. +0x0: input data (ADC) +0x1: loopback data (DAC)

          +
          +
          0x108 + 0x16*n0x420 + 0x58*nCHAN_USR_CNTRLn_1
          +

          ADC Interface Control & Status +Where n is from 0 to 15.

          +
          +

          [25:25]USR_DATATYPE_BERO0x0
          +

          The user data type format- if set, indicates big endian (default is little endian). +NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

          +
          +

          [24:24]USR_DATATYPE_SIGNEDRO0x0
          +

          The user data type format- if set, indicates signed (2’s complement) data (default is unsigned). +NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

          +
          +

          [23:16]USR_DATATYPE_SHIFTRO0x00
          +

          The user data type format- the amount of right shift for actual samples within the total number +of bits. +NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

          +
          +

          [15:8]USR_DATATYPE_TOTAL_BITSRO0x00
          +

          The user data type format- number of total bits used for a sample. The total number of bits must +be an integer multiple of 8 (byte aligned). +NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

          +
          +

          [7:0]USR_DATATYPE_BITSRO0x00
          +

          The user data type format- number of bits in a sample. This indicates the actual sample data bits. +NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

          +
          +
          0x109 + 0x16*n0x424 + 0x58*nCHAN_USR_CNTRLn_2
          +

          ADC Interface Control & Status +Where n is from 0 to 15.

          +
          +

          [31:16]USR_DECIMATION_MRW0x0000
          +

          This holds the user decimation M value of the channel that is currently being selected on +the multiplexer above. The total decimation factor is of the form M/N. +NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

          +
          +

          [15:0]USR_DECIMATION_NRW0x0000
          +

          This holds the user decimation N value of the channel that is currently being selected on +the multiplexer above. The total decimation factor is of the form M/N. +NOT-APPLICABLE if USERPORTS_DISABLE is set (0x1).

          +
          +
          0x10a + 0x16*n0x428 + 0x58*nCHAN_CNTRLn_4
          +

          ADC Interface Control & Status +Where n is from 0 to 15.

          +
          +

          [31:3]RESERVEDRO0x00000000
          +

          Reserved for backward compatibility.

          +
          +

          [2:0]SOFTSPANRW0x7
          +

          Softspan configuration register.

          +
          +
          +
          +
          +
          +
          +
          +
          +
          +
          +
          +
          + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

          DWORD

          BYTE

          Reg Name

          Description

          BITS

          Field Name

          Type

          Default Value

          Description

          0x0 + 0x1*n0x0 + 0x4*nDELAY_CONTROL_n
          +

          Delay Control & Status +Where n is from 0 to 15.

          +
          +

          [4:0]DELAY_CONTROL_IO_nRW0x00
          +

          Tap value for input/output delay primitive of the n’th interface line. If the delay controller is +not locked (indicate issues with delay_clk), the read-back value of this register will be 0xFFFFFFFF. +Otherwise will be the last set up value.

          +
          +
          +
          +
          +
          +
          +
          +
          +
          +

          Design Guidelines#

          +

          The control of the AD408x chip is done through a SPI interface, which is needed +at system level.

          +

          The ADC interface signals must be connected directly to the top file of the +design, as I/O primitives are part of the IP.

          +

          The example design uses a DMA to move the data from the output of the IP to +memory.

          +

          If the data needs to be processed in HDL before moving it to the memory, it can be +done at the output of the IP (at system level) or inside of the ADC channel +module (at IP level).

          +

          The example design uses a processor to program all the registers. If no +processor is available in your system, you can create your own IP starting from +the interface module.

          +
          +
          +

          Software Guidelines#

          +
          + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
          Main registers used to control the AXI AD408x IP#

          Name

          Register

          BIT

          Description

          BITSLIP_ENABLE

          0x44 (ADC Common)

          3

          Enables the sync process.

          NUM_LANES

          0x44 (ADC Common)

          [12:8]

          Controls the number of lanes enabled.

          FILTER_ENABLE

          0x4C (ADC Common)

          0

          Controls the filter status.

          SELF_SYNC

          0x4C (ADC Common)

          1

          Controls if the data capture synchronization is done through CNV signal or bit-slip.

          SYNC_STATUS

          0x68 (ADC Common)

          0

          States the synchronization status.

          +
          +
          +
          +

          Software Suppport#

          + +
          +
          +

          References#

          + +
          +
          + + + +
          + + +
          +
          +
          + +
          + + + +
          + ©2024, Analog Devices, Inc. + + | + Made with Sphinx + & Doctools + +
          + + \ No newline at end of file diff --git a/library/axi_ad485x/index.html b/library/axi_ad485x/index.html index 5d53399171..d6da5511b4 100644 --- a/library/axi_ad485x/index.html +++ b/library/axi_ad485x/index.html @@ -19,7 +19,7 @@ - + @@ -218,6 +218,7 @@

      • AXI AD3552R
      • +
      • AXI AD408x
      • AXI AD485x
      • AXI AD7606x
      • AXI AD7616
      • @@ -267,6 +268,7 @@
      • AXI AD3552R
      • +
      • AXI AD408x
      • AXI AD485x
      • AXI AD7606x
      • AXI AD7616
      • @@ -261,6 +262,7 @@
      • AXI AD3552R
      • +
      • AXI AD408x
      • AXI AD485x
      • AXI AD7606x
      • AXI AD7616
      • @@ -249,6 +250,7 @@
      • AXI AD3552R
      • +
      • AXI AD408x
      • AXI AD485x
      • AXI AD7606x
      • AXI AD7616
      • @@ -253,6 +254,7 @@
      • AXI AD3552R
      • +
      • AXI AD408x
      • AXI AD485x
      • AXI AD7606x
      • AXI AD7616
      • @@ -253,6 +254,7 @@
      • AXI AD3552R
      • +
      • AXI AD408x
      • AXI AD485x
      • AXI AD7606x
      • AXI AD7616
      • @@ -253,6 +254,7 @@
      • AXI AD3552R
      • +
      • AXI AD408x
      • AXI AD485x
      • AXI AD7606x
      • AXI AD7616
      • @@ -269,6 +270,7 @@
      • AXI AD3552R
      • +
      • AXI AD408x
      • AXI AD485x
      • AXI AD7606x
      • AXI AD7616
      • @@ -253,6 +254,7 @@
      • AXI AD3552R
      • +
      • AXI AD408x
      • AXI AD485x
      • AXI AD7606x
      • AXI AD7616
      • @@ -252,6 +253,7 @@
      • AXI AD3552R
      • +
      • AXI AD408x
      • AXI AD485x
      • AXI AD7606x
      • AXI AD7616
      • @@ -264,6 +265,7 @@
      • AXI AD3552R
      • +
      • AXI AD408x
      • AXI AD485x
      • AXI AD7606x
      • AXI AD7616
      • @@ -254,6 +255,7 @@
      • AXI AD3552R
      • +
      • AXI AD408x
      • AXI AD485x
      • AXI AD7606x
      • AXI AD7616
      • @@ -253,6 +254,7 @@
      • AXI AD3552R
      • +
      • AXI AD408x
      • AXI AD485x
      • AXI AD7606x
      • AXI AD7616
      • @@ -250,6 +251,7 @@
      • AXI AD3552R
      • +
      • AXI AD408x
      • AXI AD485x
      • AXI AD7606x
      • AXI AD7616
      • @@ -253,6 +254,7 @@
      • AXI AD3552R
      • +
      • AXI AD408x
      • AXI AD485x
      • AXI AD7606x
      • AXI AD7616
      • @@ -250,6 +251,7 @@
      • AXI AD3552R
      • +
      • AXI AD408x
      • AXI AD485x
      • AXI AD7606x
      • AXI AD7616
      • @@ -299,6 +300,7 @@
      • AXI AD3552R
      • +
      • AXI AD408x
      • AXI AD485x
      • AXI AD7606x
      • AXI AD7616
      • @@ -256,6 +257,7 @@
      • AXI AD3552R
      • +
      • AXI AD408x
      • AXI AD485x
      • AXI AD7606x
      • AXI AD7616
      • @@ -252,6 +253,7 @@
      • AXI AD3552R
      • +
      • AXI AD408x
      • AXI AD485x
      • AXI AD7606x
      • AXI AD7616
      • @@ -253,6 +254,7 @@
      • AXI AD3552R
      • +
      • AXI AD408x
      • AXI AD485x
      • AXI AD7606x
      • AXI AD7616
      • @@ -248,6 +249,7 @@
      • AXI AD3552R
      • +
      • AXI AD408x
      • AXI AD485x
      • AXI AD7606x
      • AXI AD7616
      • @@ -249,6 +250,7 @@
      • AXI AD3552R
      • +
      • AXI AD408x
      • AXI AD485x
      • AXI AD7606x
      • AXI AD7616
      • @@ -257,6 +258,7 @@
      • AXI AD3552R
      • +
      • AXI AD408x
      • AXI AD485x
      • AXI AD7606x
      • AXI AD7616
      • @@ -265,6 +266,7 @@
      • AXI AD3552R
      • +
      • AXI AD408x
      • AXI AD485x
      • AXI AD7606x
      • AXI AD7616
      • @@ -250,6 +251,7 @@
      • AXI AD3552R
      • +
      • AXI AD408x
      • AXI AD485x
      • AXI AD7606x
      • AXI AD7616
      • @@ -263,6 +264,7 @@
      • AXI AD3552R
      • +
      • AXI AD408x
      • AXI AD485x
      • AXI AD7606x
      • AXI AD7616
      • @@ -248,6 +249,7 @@
      • AXI AD3552R
      • +
      • AXI AD408x
      • AXI AD485x
      • AXI AD7606x
      • AXI AD7616
      • @@ -281,6 +282,7 @@
      • AXI AD3552R
      • +
      • AXI AD408x
      • AXI AD485x
      • AXI AD7606x
      • AXI AD7616
      • @@ -245,6 +246,7 @@
      • AXI AD3552R
      • +
      • AXI AD408x
      • AXI AD485x
      • AXI AD7606x
      • AXI AD7616
      • @@ -251,6 +252,7 @@
      • AXI AD3552R
      • +
      • AXI AD408x
      • AXI AD485x
      • AXI AD7606x
      • AXI AD7616
      • @@ -246,6 +247,7 @@
      • AXI AD3552R
      • +
      • AXI AD408x
      • AXI AD485x
      • AXI AD7606x
      • AXI AD7616
      • @@ -262,6 +263,7 @@
      • AXI AD3552R
      • +
      • AXI AD408x
      • AXI AD485x
      • AXI AD7606x
      • AXI AD7616
      • @@ -248,6 +249,7 @@
        • AD-GMSL2ETH-SL
        • AD3552R-EVB
        • +
        • AD408X-FMC-EVB
        • AD4110-SDZ
        • AD411x-AD717x
        • AD4134-FMC
        • @@ -255,6 +257,7 @@
        • AD4630-FMC/AD4030-FMC/ADAQ4224-FMC
        • AD469X-FMC
        • AD485X-FMCZ
        • +
        • AD57XX-ARDZ
        • AD5758-SDZ
        • AD5766-SDZ
        • AD7124-4-ASDZ/AD7124-8-ASDZ
        • @@ -323,6 +326,7 @@

          ADC/DAC
          • AXI AD3552R
          • +
          • AXI AD408x
          • AXI AD485x
          • AXI AD7606x
          • AXI AD7616
          • diff --git a/library/jesd204/ad_ip_jesd204_tpl_adc/index.html b/library/jesd204/ad_ip_jesd204_tpl_adc/index.html index 37f3b92618..e155f46fc5 100644 --- a/library/jesd204/ad_ip_jesd204_tpl_adc/index.html +++ b/library/jesd204/ad_ip_jesd204_tpl_adc/index.html @@ -222,6 +222,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -271,6 +272,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -270,6 +271,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -319,6 +320,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -298,6 +299,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -269,6 +270,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -256,6 +257,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -244,6 +245,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -250,6 +251,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -258,6 +259,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -245,6 +246,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -251,6 +252,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -248,6 +249,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -246,6 +247,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -246,6 +247,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -245,6 +246,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -258,6 +259,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -246,6 +247,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -251,6 +252,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -242,6 +243,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -244,6 +245,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -252,6 +253,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -248,6 +249,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -253,6 +254,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -246,6 +247,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -255,6 +256,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -248,6 +249,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -248,6 +249,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -249,6 +250,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -249,6 +250,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -247,6 +248,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -243,6 +244,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -260,6 +261,7 @@
          • AD-GMSL2ETH-SL
          • AD3552R-EVB
          • +
          • AD408X-FMC-EVB
          • AD4110-SDZ
          • AD411x-AD717x
          • AD4134-FMC
          • @@ -267,6 +269,7 @@
          • AD4630-FMC/AD4030-FMC/ADAQ4224-FMC
          • AD469X-FMC
          • AD485X-FMCZ
          • +
          • AD57XX-ARDZ
          • AD5758-SDZ
          • AD5766-SDZ
          • AD7124-4-ASDZ/AD7124-8-ASDZ
          • diff --git a/objects.inv b/objects.inv index f12523d707c345bd670fddcfd1b7e15e0ae35398..e0111aaf1e12e405c0db94ae5983dec74bee3d6e 100644 GIT binary patch delta 5516 zcmV;76?5v;E3GV$g@2M~rQtl4^dSw|9h1@WUGh`qitFIGfV60C}|~*^35{a z|M|IIuYOUFbDnS${WibSg$K#)<&Ia)g@c9B%K~ zm+Kk({QZ-wXgEBk6+os5{*|*Jjor@w*XQixWH}y=_aU5?am2cUhCE%C|soG3_iI_RM z*mr=XfD69ZH-F%Zdkj1|?*J=--yJd}YciJrvRfJF2^S4budy219)D)_=_K6vw19&?o#?hF1Q4r7 z$DHG*MJJ2{rgMIOB>p?$|6NQ*^1q3z_+)q* z{5EOEGFrd|kIq$t5tn{ryg2K4H?@ERK5O1hafyLP;|{PC zaKWQ-1BOckJU+ch!elMspn0-p!}Sz}Pfo*)MhUp+$*FEC{POcBw@Jp!Wo1KG`9qnM zuSaRIUKg7qDPm(8FEpJ;^SlHK{P&dC$tt>i-G9{2S(R6u`?RiBCt3X*S1ZzJQ^?Vv za~Kq#&e_-N+pCk$cfYaQEB68NZT!!yTAm!A#r1Xt1Ev&z9wl^y7IC!aTc!jU2r$l^ z&S%m8e7>DS+NYygbXO*uYFm_bw8+YQ`<#`@3b!V%c3Uo(K}BXi^E9je2>V#0g=sCf zI)5da%M`@EWpZ$BL6NXEoH?JqrM95t`)jL@eLZU{`PcYjavc0>wIa4snXbNE)4z)w z|J#-PYjS*X66`cu5my0ESKY?+@8ZVqH*!{HPwQlB<9Ah7#!tI^nH@pprA3)lM`@WQ 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        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -263,6 +264,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -262,6 +263,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -263,6 +264,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -264,6 +265,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -264,6 +265,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -271,6 +272,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -265,6 +266,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -266,6 +267,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -261,6 +262,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -265,6 +266,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -261,6 +262,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -267,6 +268,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -261,6 +262,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -266,6 +267,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -273,6 +274,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -274,6 +275,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -267,6 +268,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -262,6 +263,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -281,6 +282,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -266,6 +267,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -264,6 +265,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -264,6 +265,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -273,6 +274,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -267,6 +268,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -265,6 +266,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -262,6 +263,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -264,6 +265,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -265,6 +266,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -272,6 +273,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -273,6 +275,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -265,6 +266,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -238,6 +239,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -238,6 +239,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -243,6 +244,7 @@
        • AXI AD3552R
        • +
        • AXI AD408x
        • AXI AD485x
        • AXI AD7606x
        • AXI AD7616
        • @@ -263,6 +264,7 @@
          • AD-GMSL2ETH-SL
          • AD3552R-EVB
          • +
          • AD408X-FMC-EVB
          • AD4110-SDZ
          • AD411x-AD717x
          • AD4134-FMC
          • @@ -270,6 +272,7 @@
          • AD4630-FMC/AD4030-FMC/ADAQ4224-FMC
          • AD469X-FMC
          • AD485X-FMCZ
          • +
          • AD57XX-ARDZ
          • AD5758-SDZ
          • AD5766-SDZ
          • AD7124-4-ASDZ/AD7124-8-ASDZ
          • diff --git a/projects/pulsar_adc/index.html b/projects/pulsar_adc/index.html index 254855827c..34a001539f 100644 --- a/projects/pulsar_adc/index.html +++ b/projects/pulsar_adc/index.html @@ -102,7 +102,11 @@