From 19f10deecd99f90e5682084d45fe31fc28b00d0f Mon Sep 17 00:00:00 2001 From: Ionut Podgoreanu Date: Wed, 20 Nov 2024 06:42:47 +0200 Subject: [PATCH] Add Cache Coherency support on Ultrascale projects Signed-off-by: Ionut Podgoreanu --- .../common/ad9081_fmca_ebz_bd.tcl | 14 +++-- projects/ad9083_evb/common/ad9083_evb_bd.tcl | 9 ++- projects/ad9656_fmc/common/ad9656_fmc_bd.tcl | 9 ++- projects/ad9694_fmc/common/ad9694_fmc_bd.tcl | 9 ++- projects/ad9695_fmc/common/ad9695_fmc_bd.tcl | 9 ++- projects/ad9783_ebz/common/ad9783_ebz_bd.tcl | 11 +++- .../common/ad_fmclidar1_ebz_bd.tcl | 11 +++- projects/adrv9001/common/adrv9001_bd.tcl | 18 ++++-- projects/adrv9009/common/adrv9009_bd.tcl | 19 ++++-- .../adrv9009zu11eg/common/adrv2crr_fmc_bd.tcl | 13 +++- .../common/adrv9009zu11eg_bd.tcl | 36 ++++------- projects/adrv9026/common/adrv9026_bd.tcl | 14 +++-- projects/adrv904x/common/adrv904x_bd.tcl | 14 +++-- projects/adrv9371x/common/adrv9371x_bd.tcl | 17 ++++-- projects/common/zcu102/zcu102_system_bd.tcl | 4 +- .../dac_fmc_ebz/common/dac_fmc_ebz_bd.tcl | 11 +++- projects/daq2/common/daq2_bd.tcl | 16 +++-- projects/daq3/common/daq3_bd.tcl | 8 ++- projects/daq3/zcu102/system_bd.tcl | 10 ++-- projects/fmcomms2/common/fmcomms2_bd.tcl | 18 ++++-- projects/fmcomms5/common/fmcomms5_bd.tcl | 15 +++-- projects/fmcomms8/common/fmcomms8_bd.tcl | 19 ++++-- projects/scripts/adi_board.tcl | 60 +++++++++++-------- 23 files changed, 241 insertions(+), 123 deletions(-) diff --git a/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl b/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl index 138220ba75..2dd1044a6d 100644 --- a/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl +++ b/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl @@ -24,6 +24,10 @@ if {![info exists ADI_PHY_SEL]} { set ADI_PHY_SEL 1 } +if {![info exists CACHE_COHERENCY]} { + set CACHE_COHERENCY false +} + source $ad_hdl_dir/projects/common/xilinx/data_offload_bd.tcl source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl source $ad_hdl_dir/library/axi_tdd/scripts/axi_tdd.tcl @@ -316,6 +320,7 @@ if {$INTF_CFG != "TX"} { } else { ad_ip_parameter axi_mxfe_rx_dma CONFIG.DMA_DATA_WIDTH_DEST [expr min(512, $adc_dma_data_width)] } + ad_ip_parameter axi_mxfe_rx_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY } # Instantiate DAC (Tx) path @@ -384,6 +389,7 @@ if {$INTF_CFG != "RX"} { ad_ip_parameter axi_mxfe_tx_dma CONFIG.DMA_DATA_WIDTH_SRC [expr min(512, $dac_dma_data_width)] } ad_ip_parameter axi_mxfe_tx_dma CONFIG.DMA_DATA_WIDTH_DEST $dac_dma_data_width + ad_ip_parameter axi_mxfe_tx_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY } if {$ADI_PHY_SEL == 1} { @@ -490,8 +496,8 @@ if {$INTF_CFG != "TX"} { if {$ADI_PHY_SEL == 1} { ad_mem_hp0_interconnect $sys_cpu_clk axi_mxfe_rx_xcvr/m_axi } - ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1 - ad_mem_hp1_interconnect $sys_dma_clk axi_mxfe_rx_dma/m_dest_axi + ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1 $CACHE_COHERENCY + ad_mem_hp1_interconnect $sys_dma_clk axi_mxfe_rx_dma/m_dest_axi $CACHE_COHERENCY # Interrupts ad_cpu_interrupt ps-13 mb-12 axi_mxfe_rx_dma/irq @@ -541,8 +547,8 @@ if {$INTF_CFG != "RX"} { ad_cpu_interconnect 0x7c430000 axi_mxfe_tx_dma ad_cpu_interconnect 0x7c440000 $dac_data_offload_name # GT / ADC - ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2 - ad_mem_hp2_interconnect $sys_dma_clk axi_mxfe_tx_dma/m_src_axi + ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2 $CACHE_COHERENCY + ad_mem_hp2_interconnect $sys_dma_clk axi_mxfe_tx_dma/m_src_axi $CACHE_COHERENCY # Interrupts ad_cpu_interrupt ps-12 mb-13 axi_mxfe_tx_dma/irq diff --git a/projects/ad9083_evb/common/ad9083_evb_bd.tcl b/projects/ad9083_evb/common/ad9083_evb_bd.tcl index e2381c0eb1..cadbabc886 100644 --- a/projects/ad9083_evb/common/ad9083_evb_bd.tcl +++ b/projects/ad9083_evb/common/ad9083_evb_bd.tcl @@ -3,6 +3,10 @@ ### SPDX short identifier: ADIBSD ############################################################################### +if {![info exists CACHE_COHERENCY]} { + set CACHE_COHERENCY false +} + source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl # RX parameters @@ -57,6 +61,7 @@ ad_ip_instance axi_dmac axi_ad9083_rx_dma [list \ DMA_LENGTH_WIDTH 31 \ DMA_DATA_WIDTH_DEST 128 \ DMA_DATA_WIDTH_SRC $adc_dma_data_width \ + CACHE_COHERENT $CACHE_COHERENCY \ ] # common cores @@ -171,8 +176,8 @@ ad_mem_hp1_interconnect $sys_cpu_clk axi_ad9083_rx_xcvr/m_axi # interconnect (mem/dac) -ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2 -ad_mem_hp2_interconnect $sys_dma_clk axi_ad9083_rx_dma/m_dest_axi +ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2 $CACHE_COHERENCY +ad_mem_hp2_interconnect $sys_dma_clk axi_ad9083_rx_dma/m_dest_axi $CACHE_COHERENCY # interrupts diff --git a/projects/ad9656_fmc/common/ad9656_fmc_bd.tcl b/projects/ad9656_fmc/common/ad9656_fmc_bd.tcl index e5b1379dc1..648917a9aa 100644 --- a/projects/ad9656_fmc/common/ad9656_fmc_bd.tcl +++ b/projects/ad9656_fmc/common/ad9656_fmc_bd.tcl @@ -3,6 +3,10 @@ ### SPDX short identifier: ADIBSD ############################################################################### +if {![info exists CACHE_COHERENCY]} { + set CACHE_COHERENCY false +} + # RX parameters set RX_NUM_OF_LANES 4 ; # L set RX_NUM_OF_CONVERTERS 4 ; # M @@ -48,6 +52,7 @@ ad_ip_instance axi_dmac axi_ad9656_rx_dma [list \ AXI_SLICE_SRC false \ DMA_DATA_WIDTH_DEST 128 \ FIFO_SIZE 32 \ + CACHE_COHERENT $CACHE_COHERENCY \ ] # common cores @@ -115,8 +120,8 @@ ad_mem_hp0_interconnect $sys_cpu_clk axi_ad9656_rx_xcvr/m_axi # interconnect (mem/dac) -ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP1 -ad_mem_hp2_interconnect $sys_dma_clk axi_ad9656_rx_dma/m_dest_axi +ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP1 $CACHE_COHERENCY +ad_mem_hp2_interconnect $sys_dma_clk axi_ad9656_rx_dma/m_dest_axi $CACHE_COHERENCY # interrupts diff --git a/projects/ad9694_fmc/common/ad9694_fmc_bd.tcl b/projects/ad9694_fmc/common/ad9694_fmc_bd.tcl index 918575d27c..42fc64ca13 100644 --- a/projects/ad9694_fmc/common/ad9694_fmc_bd.tcl +++ b/projects/ad9694_fmc/common/ad9694_fmc_bd.tcl @@ -3,6 +3,10 @@ ### SPDX short identifier: ADIBSD ############################################################################### +if {![info exists CACHE_COHERENCY]} { + set CACHE_COHERENCY false +} + # RX parameters set RX_NUM_OF_LANES $ad_project_params(RX_JESD_L) ; # L set RX_NUM_OF_CONVERTERS $ad_project_params(RX_JESD_M) ; # M @@ -62,6 +66,7 @@ ad_ip_instance axi_dmac axi_ad9694_rx_dma [list \ DMA_LENGTH_WIDTH 24 \ DMA_DATA_WIDTH_DEST 128 \ DMA_DATA_WIDTH_SRC $adc_dma_data_width \ + CACHE_COHERENT $CACHE_COHERENCY \ ] # common cores @@ -168,8 +173,8 @@ ad_mem_hp0_interconnect $sys_cpu_clk axi_ad9694_rx_xcvr/m_axi # interconnect (mem/dac) -ad_mem_hp2_interconnect dma_clk_wiz/clk_out1 sys_ps7/S_AXI_HP1 -ad_mem_hp2_interconnect dma_clk_wiz/clk_out1 axi_ad9694_rx_dma/m_dest_axi +ad_mem_hp2_interconnect dma_clk_wiz/clk_out1 sys_ps7/S_AXI_HP1 $CACHE_COHERENCY +ad_mem_hp2_interconnect dma_clk_wiz/clk_out1 axi_ad9694_rx_dma/m_dest_axi $CACHE_COHERENCY # interrupts diff --git a/projects/ad9695_fmc/common/ad9695_fmc_bd.tcl b/projects/ad9695_fmc/common/ad9695_fmc_bd.tcl index 42ea0addcc..9981044c7e 100644 --- a/projects/ad9695_fmc/common/ad9695_fmc_bd.tcl +++ b/projects/ad9695_fmc/common/ad9695_fmc_bd.tcl @@ -3,6 +3,10 @@ ### SPDX short identifier: ADIBSD ############################################################################### +if {![info exists CACHE_COHERENCY]} { + set CACHE_COHERENCY false +} + # RX parameters set RX_NUM_OF_LANES $ad_project_params(RX_JESD_L) ; # L set RX_NUM_OF_CONVERTERS $ad_project_params(RX_JESD_M) ; # M @@ -62,6 +66,7 @@ ad_ip_instance axi_dmac axi_ad9695_rx_dma [list \ DMA_LENGTH_WIDTH 24 \ DMA_DATA_WIDTH_DEST 128 \ DMA_DATA_WIDTH_SRC $adc_dma_data_width \ + CACHE_COHERENT $CACHE_COHERENCY \ ] # common cores @@ -159,8 +164,8 @@ ad_mem_hp0_interconnect $sys_cpu_clk axi_ad9695_rx_xcvr/m_axi # interconnect (mem/dac) -ad_mem_hp2_interconnect dma_clk_wiz/clk_out1 sys_ps7/S_AXI_HP1 -ad_mem_hp2_interconnect dma_clk_wiz/clk_out1 axi_ad9695_rx_dma/m_dest_axi +ad_mem_hp2_interconnect dma_clk_wiz/clk_out1 sys_ps7/S_AXI_HP1 $CACHE_COHERENCY +ad_mem_hp2_interconnect dma_clk_wiz/clk_out1 axi_ad9695_rx_dma/m_dest_axi $CACHE_COHERENCY # interrupts diff --git a/projects/ad9783_ebz/common/ad9783_ebz_bd.tcl b/projects/ad9783_ebz/common/ad9783_ebz_bd.tcl index e4f87a6a9e..3d833a07fc 100755 --- a/projects/ad9783_ebz/common/ad9783_ebz_bd.tcl +++ b/projects/ad9783_ebz/common/ad9783_ebz_bd.tcl @@ -1,8 +1,12 @@ ############################################################################### -## Copyright (C) 2022-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### +if {![info exists CACHE_COHERENCY]} { + set CACHE_COHERENCY false +} + # dac interface create_bd_port -dir O dci_p @@ -27,6 +31,7 @@ ad_ip_parameter axi_ad9783_dma CONFIG.AXI_SLICE_SRC 1 ad_ip_parameter axi_ad9783_dma CONFIG.DMA_DATA_WIDTH_DEST 128 ad_ip_parameter axi_ad9783_dma CONFIG.DMA_DATA_WIDTH_SRC 128 ad_ip_parameter axi_ad9783_dma CONFIG.DMA_AXI_PROTOCOL_SRC 1 +ad_ip_parameter axi_ad9783_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY # dac-path channel upack @@ -66,8 +71,8 @@ ad_cpu_interconnect 0x7c420000 axi_ad9783_dma # interconnect (mem/dac) -ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2 -ad_mem_hp2_interconnect $sys_dma_clk axi_ad9783_dma/m_src_axi +ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2 $CACHE_COHERENCY +ad_mem_hp2_interconnect $sys_dma_clk axi_ad9783_dma/m_src_axi $CACHE_COHERENCY ad_connect $sys_dma_resetn axi_ad9783_dma/m_src_axi_aresetn # interrupts diff --git a/projects/ad_fmclidar1_ebz/common/ad_fmclidar1_ebz_bd.tcl b/projects/ad_fmclidar1_ebz/common/ad_fmclidar1_ebz_bd.tcl index ab4db3551b..b0e50bef0e 100644 --- a/projects/ad_fmclidar1_ebz/common/ad_fmclidar1_ebz_bd.tcl +++ b/projects/ad_fmclidar1_ebz/common/ad_fmclidar1_ebz_bd.tcl @@ -1,10 +1,14 @@ ############################################################################### -## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2019-2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl +if {![info exists CACHE_COHERENCY]} { + set CACHE_COHERENCY false +} + # interfaces and IO ports create_bd_port -dir I spi_vco_csn_i @@ -57,6 +61,7 @@ ad_ip_instance axi_dmac ad9694_dma [list \ DMA_DATA_WIDTH_DEST 64 \ SYNC_TRANSFER_START 1 \ FIFO_SIZE 32 \ + CACHE_COHERENT $CACHE_COHERENCY \ ] # 3-wire SPI for clock synthesizer & VCO - 12.5MHz SCLK rate @@ -199,8 +204,8 @@ ad_mem_hp3_interconnect $sys_cpu_clk axi_ad9694_xcvr/m_axi # interconnect (mem/dac) -ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2 -ad_mem_hp2_interconnect $sys_dma_clk ad9694_dma/m_dest_axi +ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2 $CACHE_COHERENCY +ad_mem_hp2_interconnect $sys_dma_clk ad9694_dma/m_dest_axi $CACHE_COHERENCY # interrupts diff --git a/projects/adrv9001/common/adrv9001_bd.tcl b/projects/adrv9001/common/adrv9001_bd.tcl index 3f43c362ed..a358b463be 100644 --- a/projects/adrv9001/common/adrv9001_bd.tcl +++ b/projects/adrv9001/common/adrv9001_bd.tcl @@ -3,6 +3,10 @@ ### SPDX short identifier: ADIBSD ############################################################################### +if {![info exists CACHE_COHERENCY]} { + set CACHE_COHERENCY false +} + # create debug ports create_bd_port -dir O adc1_div_clk create_bd_port -dir O adc2_div_clk @@ -85,6 +89,7 @@ ad_ip_parameter axi_adrv9001_rx1_dma CONFIG.AXI_SLICE_SRC 0 ad_ip_parameter axi_adrv9001_rx1_dma CONFIG.AXI_SLICE_DEST 0 ad_ip_parameter axi_adrv9001_rx1_dma CONFIG.DMA_2D_TRANSFER 0 ad_ip_parameter axi_adrv9001_rx1_dma CONFIG.DMA_DATA_WIDTH_SRC 64 +ad_ip_parameter axi_adrv9001_rx1_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY ad_ip_instance util_cpack2 util_adc_1_pack { \ NUM_OF_CHANNELS 4 \ @@ -102,6 +107,7 @@ ad_ip_parameter axi_adrv9001_rx2_dma CONFIG.AXI_SLICE_SRC 0 ad_ip_parameter axi_adrv9001_rx2_dma CONFIG.AXI_SLICE_DEST 0 ad_ip_parameter axi_adrv9001_rx2_dma CONFIG.DMA_2D_TRANSFER 0 ad_ip_parameter axi_adrv9001_rx2_dma CONFIG.DMA_DATA_WIDTH_SRC 32 +ad_ip_parameter axi_adrv9001_rx2_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY ad_ip_instance util_cpack2 util_adc_2_pack { \ NUM_OF_CHANNELS 2 \ @@ -119,6 +125,7 @@ ad_ip_parameter axi_adrv9001_tx1_dma CONFIG.AXI_SLICE_SRC 0 ad_ip_parameter axi_adrv9001_tx1_dma CONFIG.AXI_SLICE_DEST 0 ad_ip_parameter axi_adrv9001_tx1_dma CONFIG.DMA_2D_TRANSFER 0 ad_ip_parameter axi_adrv9001_tx1_dma CONFIG.DMA_DATA_WIDTH_DEST 64 +ad_ip_parameter axi_adrv9001_tx1_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY ad_ip_instance util_upack2 util_dac_1_upack { \ NUM_OF_CHANNELS 4 \ @@ -136,6 +143,7 @@ ad_ip_parameter axi_adrv9001_tx2_dma CONFIG.AXI_SLICE_SRC 0 ad_ip_parameter axi_adrv9001_tx2_dma CONFIG.AXI_SLICE_DEST 0 ad_ip_parameter axi_adrv9001_tx2_dma CONFIG.DMA_2D_TRANSFER 0 ad_ip_parameter axi_adrv9001_tx2_dma CONFIG.DMA_DATA_WIDTH_DEST 32 +ad_ip_parameter axi_adrv9001_tx2_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY ad_ip_instance util_upack2 util_dac_2_upack { \ NUM_OF_CHANNELS 2 \ @@ -282,11 +290,11 @@ ad_cpu_interconnect 0x44A60000 axi_adrv9001_tx2_dma # memory inteconnect -ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1 -ad_mem_hp1_interconnect $sys_cpu_clk axi_adrv9001_rx1_dma/m_dest_axi -ad_mem_hp1_interconnect $sys_cpu_clk axi_adrv9001_rx2_dma/m_dest_axi -ad_mem_hp1_interconnect $sys_cpu_clk axi_adrv9001_tx1_dma/m_src_axi -ad_mem_hp1_interconnect $sys_cpu_clk axi_adrv9001_tx2_dma/m_src_axi +ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1 $CACHE_COHERENCY +ad_mem_hp1_interconnect $sys_cpu_clk axi_adrv9001_rx1_dma/m_dest_axi $CACHE_COHERENCY +ad_mem_hp1_interconnect $sys_cpu_clk axi_adrv9001_rx2_dma/m_dest_axi $CACHE_COHERENCY +ad_mem_hp1_interconnect $sys_cpu_clk axi_adrv9001_tx1_dma/m_src_axi $CACHE_COHERENCY +ad_mem_hp1_interconnect $sys_cpu_clk axi_adrv9001_tx2_dma/m_src_axi $CACHE_COHERENCY ad_connect $sys_cpu_resetn axi_adrv9001_rx1_dma/m_dest_axi_aresetn ad_connect $sys_cpu_resetn axi_adrv9001_rx2_dma/m_dest_axi_aresetn diff --git a/projects/adrv9009/common/adrv9009_bd.tcl b/projects/adrv9009/common/adrv9009_bd.tcl index 2232f9e95e..189503850e 100644 --- a/projects/adrv9009/common/adrv9009_bd.tcl +++ b/projects/adrv9009/common/adrv9009_bd.tcl @@ -9,6 +9,10 @@ # [TX/RX/RX_OS]_JESD_S : Number of samples per frame # [TX/RX/RX_OS]_JESD_NP : Number of bits per sample +if {![info exists CACHE_COHERENCY]} { + set CACHE_COHERENCY false +} + set MAX_TX_NUM_OF_LANES 4 set MAX_RX_NUM_OF_LANES 2 set MAX_RX_OS_NUM_OF_LANES 2 @@ -109,6 +113,7 @@ ad_ip_parameter axi_adrv9009_tx_dma CONFIG.DMA_DATA_WIDTH_DEST $dac_data_width ad_ip_parameter axi_adrv9009_tx_dma CONFIG.MAX_BYTES_PER_BURST 256 ad_ip_parameter axi_adrv9009_tx_dma CONFIG.AXI_SLICE_DEST true ad_ip_parameter axi_adrv9009_tx_dma CONFIG.AXI_SLICE_SRC true +ad_ip_parameter axi_adrv9009_tx_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_data_width $dac_fifo_address_width @@ -161,6 +166,7 @@ ad_ip_parameter axi_adrv9009_rx_dma CONFIG.DMA_DATA_WIDTH_SRC $adc_dma_data_widt ad_ip_parameter axi_adrv9009_rx_dma CONFIG.MAX_BYTES_PER_BURST 256 ad_ip_parameter axi_adrv9009_rx_dma CONFIG.AXI_SLICE_DEST true ad_ip_parameter axi_adrv9009_rx_dma CONFIG.AXI_SLICE_SRC true +ad_ip_parameter axi_adrv9009_rx_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY # adc-os peripherals @@ -206,6 +212,7 @@ ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.DMA_DATA_WIDTH_SRC [expr $RX_OS_SA ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.MAX_BYTES_PER_BURST 256 ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.AXI_SLICE_DEST true ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.AXI_SLICE_SRC true +ad_ip_parameter axi_adrv9009_rx_os_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY # common cores @@ -453,12 +460,12 @@ ad_mem_hp0_interconnect $sys_cpu_clk axi_adrv9009_rx_os_xcvr/m_axi # interconnect (mem/dac) -ad_mem_hp1_interconnect $sys_dma_clk sys_ps7/S_AXI_HP1 -ad_mem_hp1_interconnect $sys_dma_clk axi_adrv9009_rx_os_dma/m_dest_axi -ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2 -ad_mem_hp2_interconnect $sys_dma_clk axi_adrv9009_rx_dma/m_dest_axi -ad_mem_hp3_interconnect $sys_dma_clk sys_ps7/S_AXI_HP3 -ad_mem_hp3_interconnect $sys_dma_clk axi_adrv9009_tx_dma/m_src_axi +ad_mem_hp1_interconnect $sys_dma_clk sys_ps7/S_AXI_HP1 $CACHE_COHERENCY +ad_mem_hp1_interconnect $sys_dma_clk axi_adrv9009_rx_os_dma/m_dest_axi $CACHE_COHERENCY +ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2 $CACHE_COHERENCY +ad_mem_hp2_interconnect $sys_dma_clk axi_adrv9009_rx_dma/m_dest_axi $CACHE_COHERENCY +ad_mem_hp3_interconnect $sys_dma_clk sys_ps7/S_AXI_HP3 $CACHE_COHERENCY +ad_mem_hp3_interconnect $sys_dma_clk axi_adrv9009_tx_dma/m_src_axi $CACHE_COHERENCY # interrupts diff --git a/projects/adrv9009zu11eg/common/adrv2crr_fmc_bd.tcl b/projects/adrv9009zu11eg/common/adrv2crr_fmc_bd.tcl index 1c84a20578..7ba2899032 100644 --- a/projects/adrv9009zu11eg/common/adrv2crr_fmc_bd.tcl +++ b/projects/adrv9009zu11eg/common/adrv2crr_fmc_bd.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2019-2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -29,6 +29,9 @@ ad_ip_parameter i2s_tx_dma CONFIG.ASYNC_CLK_REQ_SRC 0 ad_ip_parameter i2s_tx_dma CONFIG.DMA_2D_TRANSFER 0 ad_ip_parameter i2s_tx_dma CONFIG.DMA_DATA_WIDTH_DEST 32 ad_ip_parameter i2s_tx_dma CONFIG.DMA_DATA_WIDTH_SRC 64 +ad_ip_parameter i2s_tx_dma CONFIG.CACHE_COHERENT 1 +ad_ip_parameter i2s_tx_dma CONFIG.AXI_AXCACHE 0b1111 +ad_ip_parameter i2s_tx_dma CONFIG.AXI_AXPROT 0b010 ad_ip_instance axi_dmac i2s_rx_dma ad_ip_parameter i2s_rx_dma CONFIG.DMA_TYPE_SRC 1 @@ -42,6 +45,9 @@ ad_ip_parameter i2s_rx_dma CONFIG.ASYNC_CLK_REQ_SRC 0 ad_ip_parameter i2s_rx_dma CONFIG.DMA_2D_TRANSFER 0 ad_ip_parameter i2s_rx_dma CONFIG.DMA_DATA_WIDTH_DEST 64 ad_ip_parameter i2s_rx_dma CONFIG.DMA_DATA_WIDTH_SRC 32 +ad_ip_parameter i2s_rx_dma CONFIG.CACHE_COHERENT 1 +ad_ip_parameter i2s_rx_dma CONFIG.AXI_AXCACHE 0b1111 +ad_ip_parameter i2s_rx_dma CONFIG.AXI_AXPROT 0b010 # i2s connections @@ -95,8 +101,9 @@ ad_cpu_interconnect 0x41000000 i2s_rx_dma ad_cpu_interconnect 0x41001000 i2s_tx_dma ad_cpu_interconnect 0x42000000 axi_i2s_adi -ad_mem_hp0_interconnect sys_cpu_clk i2s_tx_dma/m_src_axi -ad_mem_hp0_interconnect sys_cpu_clk i2s_rx_dma/m_dest_axi +ad_mem_hpc0_interconnect sys_cpu_clk sys_ps8/S_AXI_HPC0 +ad_mem_hpc0_interconnect sys_cpu_clk i2s_tx_dma/m_src_axi +ad_mem_hpc0_interconnect sys_cpu_clk i2s_rx_dma/m_dest_axi # interrupts diff --git a/projects/adrv9009zu11eg/common/adrv9009zu11eg_bd.tcl b/projects/adrv9009zu11eg/common/adrv9009zu11eg_bd.tcl index 57a9f249a1..754b625985 100644 --- a/projects/adrv9009zu11eg/common/adrv9009zu11eg_bd.tcl +++ b/projects/adrv9009zu11eg/common/adrv9009zu11eg_bd.tcl @@ -284,6 +284,9 @@ ad_ip_parameter axi_adrv9009_som_tx_dma CONFIG.AXI_SLICE_DEST 1 ad_ip_parameter axi_adrv9009_som_tx_dma CONFIG.DMA_2D_TRANSFER 0 ad_ip_parameter axi_adrv9009_som_tx_dma CONFIG.DMA_DATA_WIDTH_DEST $dac_data_width ad_ip_parameter axi_adrv9009_som_tx_dma CONFIG.DMA_DATA_WIDTH_SRC 128 +ad_ip_parameter axi_adrv9009_som_tx_dma CONFIG.CACHE_COHERENT 1 +ad_ip_parameter axi_adrv9009_som_tx_dma CONFIG.AXI_AXCACHE 0b1111 +ad_ip_parameter axi_adrv9009_som_tx_dma CONFIG.AXI_AXPROT 0b010 ad_ip_instance axi_adxcvr axi_adrv9009_som_rx_xcvr ad_ip_parameter axi_adrv9009_som_rx_xcvr CONFIG.NUM_OF_LANES $MAX_RX_NUM_OF_LANES @@ -319,6 +322,9 @@ ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.FIFO_SIZE 32 ad_ip_parameter axi_adrv9009_som_rx_dma MAX_BYTES_PER_BURST 256 ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.DMA_DATA_WIDTH_SRC $adc_dma_data_width ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.DMA_DATA_WIDTH_DEST 128 +ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.CACHE_COHERENT 1 +ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.AXI_AXCACHE 0b1111 +ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.AXI_AXPROT 0b010 ad_ip_instance axi_adxcvr axi_adrv9009_som_obs_xcvr ad_ip_parameter axi_adrv9009_som_obs_xcvr CONFIG.NUM_OF_LANES $MAX_RX_OS_NUM_OF_LANES @@ -352,6 +358,9 @@ ad_ip_parameter axi_adrv9009_som_obs_dma CONFIG.FIFO_SIZE 32 ad_ip_parameter axi_adrv9009_som_obs_dma MAX_BYTES_PER_BURST 256 ad_ip_parameter axi_adrv9009_som_obs_dma CONFIG.DMA_DATA_WIDTH_SRC [expr 32*$RX_OS_NUM_OF_LANES] ad_ip_parameter axi_adrv9009_som_obs_dma CONFIG.DMA_DATA_WIDTH_DEST 128 +ad_ip_parameter axi_adrv9009_som_obs_dma CONFIG.CACHE_COHERENT 1 +ad_ip_parameter axi_adrv9009_som_obs_dma CONFIG.AXI_AXCACHE 0b1111 +ad_ip_parameter axi_adrv9009_som_obs_dma CONFIG.AXI_AXPROT 0b010 ad_ip_instance util_adxcvr util_adrv9009_som_xcvr ad_ip_parameter util_adrv9009_som_xcvr CONFIG.RX_NUM_OF_LANES [expr $MAX_RX_NUM_OF_LANES+$MAX_RX_OS_NUM_OF_LANES] @@ -755,23 +764,10 @@ ad_mem_hp0_interconnect sys_cpu_clk axi_adrv9009_som_obs_xcvr/m_axi # interconnect (mem/dac) -ad_ip_parameter sys_ps8 CONFIG.PSU__USE__S_AXI_GP3 1 -ad_connect sys_dma_clk sys_ps8/saxihp1_fpd_aclk -ad_connect sys_dma_clk axi_adrv9009_som_obs_dma/m_dest_axi_aclk -ad_connect sys_dma_resetn axi_adrv9009_som_obs_dma/m_dest_axi_aresetn -ad_connect axi_adrv9009_som_obs_dma/m_dest_axi sys_ps8/S_AXI_HP1_FPD - -ad_ip_parameter sys_ps8 CONFIG.PSU__USE__S_AXI_GP4 1 -ad_connect sys_dma_clk sys_ps8/saxihp2_fpd_aclk -ad_connect sys_dma_clk axi_adrv9009_som_rx_dma/m_dest_axi_aclk -ad_connect sys_dma_resetn axi_adrv9009_som_rx_dma/m_dest_axi_aresetn -ad_connect axi_adrv9009_som_rx_dma/m_dest_axi sys_ps8/S_AXI_HP2_FPD - -ad_ip_parameter sys_ps8 CONFIG.PSU__USE__S_AXI_GP5 1 -ad_connect sys_dma_clk sys_ps8/saxihp3_fpd_aclk -ad_connect sys_dma_clk axi_adrv9009_som_tx_dma/m_src_axi_aclk -ad_connect sys_dma_resetn axi_adrv9009_som_tx_dma/m_src_axi_aresetn -ad_connect axi_adrv9009_som_tx_dma/m_src_axi sys_ps8/S_AXI_HP3_FPD +ad_mem_hpc1_interconnect sys_dma_clk sys_ps8/S_AXI_HPC1 +ad_mem_hpc1_interconnect sys_dma_clk axi_adrv9009_som_obs_dma/m_dest_axi +ad_mem_hpc1_interconnect sys_dma_clk axi_adrv9009_som_rx_dma/m_dest_axi +ad_mem_hpc1_interconnect sys_dma_clk axi_adrv9009_som_tx_dma/m_src_axi # interrupts @@ -782,11 +778,5 @@ ad_cpu_interrupt ps-11 mb-14 axi_adrv9009_som_obs_jesd/irq ad_cpu_interrupt ps-12 mb-13 axi_adrv9009_som_tx_jesd/irq ad_cpu_interrupt ps-13 mb-12 axi_adrv9009_som_rx_jesd/irq -create_bd_addr_seg -range 0x80000000 -offset 0x00000000 \ - [get_bd_addr_spaces axi_adrv9009_som_obs_dma/m_dest_axi] [get_bd_addr_segs sys_ps8/SAXIGP3/HP1_DDR_LOW] SEG_sys_ps8_HP1_DDR_LOW -create_bd_addr_seg -range 0x80000000 -offset 0x00000000 \ - [get_bd_addr_spaces axi_adrv9009_som_rx_dma/m_dest_axi] [get_bd_addr_segs sys_ps8/SAXIGP4/HP2_DDR_LOW] SEG_sys_ps8_HP2_DDR_LOW -create_bd_addr_seg -range 0x80000000 -offset 0x00000000 \ - [get_bd_addr_spaces axi_adrv9009_som_tx_dma/m_src_axi] [get_bd_addr_segs sys_ps8/SAXIGP5/HP3_DDR_LOW] SEG_sys_ps8_HP3_DDR_LOW create_bd_addr_seg -range 0x80000000 -offset 0x80000000 \ [get_bd_addr_spaces axi_tx_fifo/axi] [get_bd_addr_segs ddr4_1/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_ddr4_1_C0_DDR4_ADDRESS_BLOCK diff --git a/projects/adrv9026/common/adrv9026_bd.tcl b/projects/adrv9026/common/adrv9026_bd.tcl index 68b3148075..3570ad80b4 100644 --- a/projects/adrv9026/common/adrv9026_bd.tcl +++ b/projects/adrv9026/common/adrv9026_bd.tcl @@ -7,6 +7,10 @@ if {![info exists ADI_PHY_SEL]} { set ADI_PHY_SEL 1 } +if {![info exists CACHE_COHERENCY]} { + set CACHE_COHERENCY false +} + if {![info exists INTF_CFG]} { set INTF_CFG RXTX } @@ -102,6 +106,7 @@ ad_ip_parameter axi_adrv9026_tx_dma CONFIG.DMA_DATA_WIDTH_DEST $dac_dma_data_wid ad_ip_parameter axi_adrv9026_tx_dma CONFIG.MAX_BYTES_PER_BURST 256 ad_ip_parameter axi_adrv9026_tx_dma CONFIG.DMA_DATA_WIDTH_SRC 128 ad_ip_parameter axi_adrv9026_tx_dma CONFIG.FIFO_SIZE 32 +ad_ip_parameter axi_adrv9026_tx_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_dma_data_width $dac_fifo_address_width if {$ADI_PHY_SEL == 1} { @@ -147,6 +152,7 @@ ad_ip_parameter axi_adrv9026_rx_dma CONFIG.DMA_DATA_WIDTH_SRC [expr 32*$RX_NUM_O ad_ip_parameter axi_adrv9026_rx_dma CONFIG.MAX_BYTES_PER_BURST 4096 ad_ip_parameter axi_adrv9026_rx_dma CONFIG.DMA_DATA_WIDTH_DEST 128 ad_ip_parameter axi_adrv9026_rx_dma CONFIG.FIFO_SIZE 32 +ad_ip_parameter axi_adrv9026_rx_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY # xcvr interfaces @@ -364,10 +370,10 @@ if {$ADI_PHY_SEL == 1} { # interconnect (mem/dac) -ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2 -ad_mem_hp2_interconnect $sys_dma_clk axi_adrv9026_rx_dma/m_dest_axi -ad_mem_hp3_interconnect $sys_dma_clk sys_ps7/S_AXI_HP3 -ad_mem_hp3_interconnect $sys_dma_clk axi_adrv9026_tx_dma/m_src_axi +ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2 $CACHE_COHERENCY +ad_mem_hp2_interconnect $sys_dma_clk axi_adrv9026_rx_dma/m_dest_axi $CACHE_COHERENCY +ad_mem_hp3_interconnect $sys_dma_clk sys_ps7/S_AXI_HP3 $CACHE_COHERENCY +ad_mem_hp3_interconnect $sys_dma_clk axi_adrv9026_tx_dma/m_src_axi $CACHE_COHERENCY # interrupts diff --git a/projects/adrv904x/common/adrv904x_bd.tcl b/projects/adrv904x/common/adrv904x_bd.tcl index 9a00113962..fb3c2cca7b 100644 --- a/projects/adrv904x/common/adrv904x_bd.tcl +++ b/projects/adrv904x/common/adrv904x_bd.tcl @@ -7,6 +7,10 @@ if {![info exists ADI_PHY_SEL]} { set ADI_PHY_SEL 1 } +if {![info exists CACHE_COHERENCY]} { + set CACHE_COHERENCY false +} + if {![info exists INTF_CFG]} { set INTF_CFG RXTX } @@ -142,6 +146,7 @@ ad_ip_parameter axi_adrv904x_tx_dma CONFIG.CYCLIC 1 ad_ip_parameter axi_adrv904x_tx_dma CONFIG.MAX_BYTES_PER_BURST 4096 ad_ip_parameter axi_adrv904x_tx_dma CONFIG.DMA_DATA_WIDTH_SRC [expr min(512, $dac_dma_data_width)] ad_ip_parameter axi_adrv904x_tx_dma CONFIG.DMA_DATA_WIDTH_DEST $dac_dma_data_width +ad_ip_parameter axi_adrv904x_tx_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY # adc peripherals if {$ADI_PHY_SEL == 1} { @@ -198,6 +203,7 @@ ad_ip_instance axi_dmac axi_adrv904x_rx_dma ad_ip_parameter axi_adrv904x_rx_dma CONFIG.CYCLIC 0 ad_ip_parameter axi_adrv904x_rx_dma CONFIG.DMA_DATA_WIDTH_SRC $adc_dma_data_width ad_ip_parameter axi_adrv904x_rx_dma CONFIG.DMA_DATA_WIDTH_DEST [expr min(512, $adc_dma_data_width)] + ad_ip_parameter axi_adrv904x_rx_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY set tx_ref_clk tx_ref_clk_0 set rx_ref_clk rx_ref_clk_0 @@ -454,10 +460,10 @@ if {$ADI_PHY_SEL == 1} { } # interconnect (mem/dac) -ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2 -ad_mem_hp2_interconnect $sys_dma_clk axi_adrv904x_rx_dma/m_dest_axi -ad_mem_hp3_interconnect $sys_dma_clk sys_ps7/S_AXI_HP3 -ad_mem_hp3_interconnect $sys_dma_clk axi_adrv904x_tx_dma/m_src_axi +ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2 $CACHE_COHERENCY +ad_mem_hp2_interconnect $sys_dma_clk axi_adrv904x_rx_dma/m_dest_axi $CACHE_COHERENCY +ad_mem_hp3_interconnect $sys_dma_clk sys_ps7/S_AXI_HP3 $CACHE_COHERENCY +ad_mem_hp3_interconnect $sys_dma_clk axi_adrv904x_tx_dma/m_src_axi $CACHE_COHERENCY # interrupts diff --git a/projects/adrv9371x/common/adrv9371x_bd.tcl b/projects/adrv9371x/common/adrv9371x_bd.tcl index 3945e69e36..ccd5b13ddd 100644 --- a/projects/adrv9371x/common/adrv9371x_bd.tcl +++ b/projects/adrv9371x/common/adrv9371x_bd.tcl @@ -10,6 +10,10 @@ # [TX/RX/RX_OS]_JESD_S : Number of samples per frame # [TX/RX/RX_OS]_JESD_NP : Number of bits per sample +if {![info exists CACHE_COHERENCY]} { + set CACHE_COHERENCY false +} + set MAX_TX_NUM_OF_LANES 4 set MAX_RX_NUM_OF_LANES 2 set MAX_RX_OS_NUM_OF_LANES 2 @@ -100,6 +104,7 @@ ad_ip_parameter axi_ad9371_tx_dma CONFIG.ASYNC_CLK_SRC_DEST 1 ad_ip_parameter axi_ad9371_tx_dma CONFIG.ASYNC_CLK_REQ_SRC 1 ad_ip_parameter axi_ad9371_tx_dma CONFIG.DMA_2D_TRANSFER 0 ad_ip_parameter axi_ad9371_tx_dma CONFIG.DMA_DATA_WIDTH_DEST $dac_dma_data_width +ad_ip_parameter axi_ad9371_tx_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_dma_data_width $dac_fifo_address_width @@ -148,6 +153,7 @@ ad_ip_parameter axi_ad9371_rx_dma CONFIG.DMA_2D_TRANSFER 0 ad_ip_parameter axi_ad9371_rx_dma CONFIG.DMA_DATA_WIDTH_SRC [expr $RX_SAMPLE_WIDTH * \ $RX_NUM_OF_CONVERTERS * \ $RX_SAMPLES_PER_CHANNEL] +ad_ip_parameter axi_ad9371_rx_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY ad_add_decimation_filter "rx_fir_decimator" 8 $RX_NUM_OF_CONVERTERS 1 {122.88} {122.88} \ "$ad_hdl_dir/library/util_fir_int/coefile_int.coe" @@ -197,6 +203,7 @@ ad_ip_parameter axi_ad9371_rx_os_dma CONFIG.DMA_2D_TRANSFER 0 ad_ip_parameter axi_ad9371_rx_os_dma CONFIG.DMA_DATA_WIDTH_SRC [expr $RX_OS_SAMPLE_WIDTH * \ $RX_OS_NUM_OF_CONVERTERS * \ $RX_OS_SAMPLES_PER_CHANNEL] +ad_ip_parameter axi_ad9371_rx_os_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY # common cores @@ -385,11 +392,11 @@ ad_mem_hp3_interconnect $sys_cpu_clk axi_ad9371_rx_os_xcvr/m_axi # interconnect (mem/dac) -ad_mem_hp1_interconnect $sys_dma_clk sys_ps7/S_AXI_HP1 -ad_mem_hp1_interconnect $sys_dma_clk axi_ad9371_tx_dma/m_src_axi -ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2 -ad_mem_hp2_interconnect $sys_dma_clk axi_ad9371_rx_dma/m_dest_axi -ad_mem_hp2_interconnect $sys_dma_clk axi_ad9371_rx_os_dma/m_dest_axi +ad_mem_hp1_interconnect $sys_dma_clk sys_ps7/S_AXI_HP1 $CACHE_COHERENCY +ad_mem_hp1_interconnect $sys_dma_clk axi_ad9371_tx_dma/m_src_axi $CACHE_COHERENCY +ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2 $CACHE_COHERENCY +ad_mem_hp2_interconnect $sys_dma_clk axi_ad9371_rx_dma/m_dest_axi $CACHE_COHERENCY +ad_mem_hp2_interconnect $sys_dma_clk axi_ad9371_rx_os_dma/m_dest_axi $CACHE_COHERENCY # interrupts diff --git a/projects/common/zcu102/zcu102_system_bd.tcl b/projects/common/zcu102/zcu102_system_bd.tcl index c3ded4ac11..2b281cdd3e 100644 --- a/projects/common/zcu102/zcu102_system_bd.tcl +++ b/projects/common/zcu102/zcu102_system_bd.tcl @@ -1,8 +1,10 @@ ############################################################################### -## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2016-2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### +set CACHE_COHERENCY true + # create board design # default ports diff --git a/projects/dac_fmc_ebz/common/dac_fmc_ebz_bd.tcl b/projects/dac_fmc_ebz/common/dac_fmc_ebz_bd.tcl index b8b7678257..cc1e88bd4a 100644 --- a/projects/dac_fmc_ebz/common/dac_fmc_ebz_bd.tcl +++ b/projects/dac_fmc_ebz/common/dac_fmc_ebz_bd.tcl @@ -1,10 +1,14 @@ ############################################################################### -## Copyright (C) 2019-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2019-2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl +if {![info exists CACHE_COHERENCY]} { + set CACHE_COHERENCY false +} + set JESD_M $ad_project_params(JESD_M) set JESD_L $ad_project_params(JESD_L) set NUM_LINKS $ad_project_params(NUM_LINKS) @@ -52,6 +56,7 @@ ad_ip_instance axi_dmac dac_dma [list \ DMA_TYPE_DEST 1 \ DMA_DATA_WIDTH_SRC 64 \ DMA_DATA_WIDTH_DEST $dac_dma_data_width \ + CACHE_COHERENT $CACHE_COHERENCY \ ] ad_dacfifo_create axi_dac_fifo \ @@ -130,8 +135,8 @@ ad_cpu_interconnect 0x7c420000 dac_dma # interconnect (mem/dac) -ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1 -ad_mem_hp1_interconnect sys_cpu_clk dac_dma/m_src_axi +ad_mem_hp1_interconnect sys_cpu_clk sys_ps7/S_AXI_HP1 $CACHE_COHERENCY +ad_mem_hp1_interconnect sys_cpu_clk dac_dma/m_src_axi $CACHE_COHERENCY # interrupts diff --git a/projects/daq2/common/daq2_bd.tcl b/projects/daq2/common/daq2_bd.tcl index 7564f78405..3531ca94c0 100644 --- a/projects/daq2/common/daq2_bd.tcl +++ b/projects/daq2/common/daq2_bd.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -13,6 +13,10 @@ source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl source $ad_hdl_dir/projects/common/xilinx/data_offload_bd.tcl +if {![info exists CACHE_COHERENCY]} { + set CACHE_COHERENCY false +} + # JESD204B interface configurations set TX_NUM_OF_LANES $ad_project_params(TX_JESD_L) ; # L @@ -66,6 +70,7 @@ ad_ip_instance axi_dmac axi_ad9144_dma [list \ CYCLIC 0 \ DMA_DATA_WIDTH_SRC 128 \ DMA_DATA_WIDTH_DEST $dac_data_width \ + CACHE_COHERENT $CACHE_COHERENCY \ ] ad_data_offload_create axi_ad9144_offload \ @@ -115,6 +120,7 @@ ad_ip_instance axi_dmac axi_ad9680_dma [list \ CYCLIC 0 \ DMA_DATA_WIDTH_SRC $adc_data_width \ DMA_DATA_WIDTH_DEST 64 \ + CACHE_COHERENT $CACHE_COHERENCY \ ] ad_data_offload_create axi_ad9680_offload \ @@ -237,10 +243,10 @@ ad_mem_hp3_interconnect $sys_cpu_clk axi_ad9680_xcvr/m_axi # interconnect (mem/dac) -ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1 -ad_mem_hp1_interconnect $sys_cpu_clk axi_ad9144_dma/m_src_axi -ad_mem_hp2_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP2 -ad_mem_hp2_interconnect $sys_cpu_clk axi_ad9680_dma/m_dest_axi +ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1 $CACHE_COHERENCY +ad_mem_hp1_interconnect $sys_cpu_clk axi_ad9144_dma/m_src_axi $CACHE_COHERENCY +ad_mem_hp2_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP2 $CACHE_COHERENCY +ad_mem_hp2_interconnect $sys_cpu_clk axi_ad9680_dma/m_dest_axi $CACHE_COHERENCY # interrupts diff --git a/projects/daq3/common/daq3_bd.tcl b/projects/daq3/common/daq3_bd.tcl index 7abc567374..ef1112b54f 100644 --- a/projects/daq3/common/daq3_bd.tcl +++ b/projects/daq3/common/daq3_bd.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -12,6 +12,10 @@ source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl +if {![info exists CACHE_COHERENCY]} { + set CACHE_COHERENCY false +} + # TX parameters set TX_NUM_OF_LANES $ad_project_params(TX_JESD_L) ; # L set TX_NUM_OF_CONVERTERS $ad_project_params(TX_JESD_M) ; # M @@ -70,6 +74,7 @@ ad_ip_parameter axi_ad9152_dma CONFIG.DMA_2D_TRANSFER 0 ad_ip_parameter axi_ad9152_dma CONFIG.CYCLIC 0 ad_ip_parameter axi_ad9152_dma CONFIG.DMA_DATA_WIDTH_SRC 128 ad_ip_parameter axi_ad9152_dma CONFIG.DMA_DATA_WIDTH_DEST $dac_data_width +ad_ip_parameter axi_ad9152_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY ad_dacfifo_create $dac_fifo_name $dac_data_width $dac_data_width $dac_fifo_address_width @@ -107,6 +112,7 @@ ad_ip_parameter axi_ad9680_dma CONFIG.DMA_2D_TRANSFER 0 ad_ip_parameter axi_ad9680_dma CONFIG.CYCLIC 0 ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_SRC $adc_data_width ad_ip_parameter axi_ad9680_dma CONFIG.DMA_DATA_WIDTH_DEST 64 +ad_ip_parameter axi_ad9680_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY if {$sys_zynq == 0 || $sys_zynq == 1} { ad_adcfifo_create $adc_fifo_name $adc_data_width $adc_data_width $adc_fifo_address_width diff --git a/projects/daq3/zcu102/system_bd.tcl b/projects/daq3/zcu102/system_bd.tcl index a18f49d66d..2841818a34 100644 --- a/projects/daq3/zcu102/system_bd.tcl +++ b/projects/daq3/zcu102/system_bd.tcl @@ -83,9 +83,9 @@ ad_connect axi_ad9680_dma/fifo_wr_clk util_daq3_xcvr/rx_out_clk_0 ad_connect axi_ad9680_cpack/packed_fifo_wr axi_ad9680_dma/fifo_wr ad_connect axi_ad9680_cpack/fifo_wr_overflow axi_ad9680_tpl_core/adc_dovf -ad_mem_hp0_interconnect sys_cpu_clk sys_ps7/S_AXI_HP0 +ad_mem_hp0_interconnect sys_cpu_clk sys_ps8/S_AXI_HP0 ad_mem_hp0_interconnect sys_cpu_clk axi_ad9680_xcvr/m_axi -ad_mem_hp1_interconnect sys_dma_clk sys_ps7/S_AXI_HP1 -ad_mem_hp1_interconnect sys_dma_clk axi_ad9680_dma/m_dest_axi -ad_mem_hp3_interconnect sys_dma_clk sys_ps7/S_AXI_HP3 -ad_mem_hp3_interconnect sys_dma_clk axi_ad9152_dma/m_src_axi +ad_mem_hpc0_interconnect sys_dma_clk sys_ps8/S_AXI_HPC0 +ad_mem_hpc0_interconnect sys_dma_clk axi_ad9680_dma/m_dest_axi +ad_mem_hpc1_interconnect sys_dma_clk sys_ps8/S_AXI_HPC1 +ad_mem_hpc1_interconnect sys_dma_clk axi_ad9152_dma/m_src_axi diff --git a/projects/fmcomms2/common/fmcomms2_bd.tcl b/projects/fmcomms2/common/fmcomms2_bd.tcl index 04d08b790e..40e1c60a1d 100644 --- a/projects/fmcomms2/common/fmcomms2_bd.tcl +++ b/projects/fmcomms2/common/fmcomms2_bd.tcl @@ -3,6 +3,10 @@ ### SPDX short identifier: ADIBSD ############################################################################### +if {![info exists CACHE_COHERENCY]} { + set CACHE_COHERENCY false +} + # fmcomms2 create_bd_port -dir I rx_clk_in_p @@ -145,6 +149,7 @@ ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_2D_TRANSFER 0 ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_SG_TRANSFER 1 ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_DATA_WIDTH_SRC 64 ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_DATA_WIDTH_SG 64 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY ad_connect util_ad9361_divclk/clk_out axi_ad9361_adc_dma/fifo_wr_clk ad_connect util_ad9361_adc_pack/packed_fifo_wr axi_ad9361_adc_dma/fifo_wr @@ -207,6 +212,7 @@ ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_2D_TRANSFER 0 ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_SG_TRANSFER 1 ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_DATA_WIDTH_DEST 64 ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_DATA_WIDTH_SG 64 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY ad_connect util_ad9361_divclk/clk_out axi_ad9361_dac_dma/m_axis_aclk ad_connect axi_ad9361_dac_dma/m_axis util_ad9361_dac_upack/s_axis @@ -219,13 +225,13 @@ ad_connect $sys_cpu_resetn axi_ad9361_dac_dma/m_sg_axi_aresetn ad_cpu_interconnect 0x79020000 axi_ad9361 ad_cpu_interconnect 0x7C400000 axi_ad9361_adc_dma ad_cpu_interconnect 0x7C420000 axi_ad9361_dac_dma -ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1 -ad_mem_hp1_interconnect $sys_cpu_clk axi_ad9361_adc_dma/m_dest_axi -ad_mem_hp2_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP2 -ad_mem_hp2_interconnect $sys_cpu_clk axi_ad9361_dac_dma/m_src_axi -ad_mem_hp2_interconnect $sys_cpu_clk axi_ad9361_dac_dma/m_sg_axi -ad_mem_hp1_interconnect $sys_cpu_clk axi_ad9361_adc_dma/m_sg_axi +ad_mem_hp1_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP1 $CACHE_COHERENCY +ad_mem_hp1_interconnect $sys_cpu_clk axi_ad9361_adc_dma/m_dest_axi $CACHE_COHERENCY +ad_mem_hp1_interconnect $sys_cpu_clk axi_ad9361_adc_dma/m_sg_axi $CACHE_COHERENCY +ad_mem_hp2_interconnect $sys_cpu_clk sys_ps7/S_AXI_HP2 $CACHE_COHERENCY +ad_mem_hp2_interconnect $sys_cpu_clk axi_ad9361_dac_dma/m_src_axi $CACHE_COHERENCY +ad_mem_hp2_interconnect $sys_cpu_clk axi_ad9361_dac_dma/m_sg_axi $CACHE_COHERENCY # interrupts diff --git a/projects/fmcomms5/common/fmcomms5_bd.tcl b/projects/fmcomms5/common/fmcomms5_bd.tcl index bb0b5186f1..84421cc433 100644 --- a/projects/fmcomms5/common/fmcomms5_bd.tcl +++ b/projects/fmcomms5/common/fmcomms5_bd.tcl @@ -3,6 +3,10 @@ ### SPDX short identifier: ADIBSD ############################################################################### +if {![info exists CACHE_COHERENCY]} { + set CACHE_COHERENCY false +} + # fmcomms5 # master @@ -193,6 +197,8 @@ ad_ip_parameter axi_ad9361_adc_dma CONFIG.AXI_SLICE_DEST 0 ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_2D_TRANSFER 0 ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_DATA_WIDTH_SRC 128 ad_ip_parameter axi_ad9361_adc_dma CONFIG.DMA_DATA_WIDTH_DEST 64 +ad_ip_parameter axi_ad9361_adc_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY + ad_connect util_ad9361_divclk/clk_out axi_ad9361_adc_dma/fifo_wr_clk ad_connect util_ad9361_adc_pack/packed_fifo_wr axi_ad9361_adc_dma/fifo_wr ad_connect util_ad9361_adc_pack/packed_sync axi_ad9361_adc_dma/sync @@ -266,6 +272,7 @@ ad_ip_parameter axi_ad9361_dac_dma CONFIG.AXI_SLICE_DEST 0 ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_2D_TRANSFER 0 ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_DATA_WIDTH_DEST 128 ad_ip_parameter axi_ad9361_dac_dma CONFIG.DMA_DATA_WIDTH_SRC 64 +ad_ip_parameter axi_ad9361_dac_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY ad_connect $sys_dma_resetn axi_ad9361_dac_dma/m_src_axi_aresetn ad_connect util_ad9361_divclk/clk_out axi_ad9361_dac_dma/m_axis_aclk @@ -277,10 +284,10 @@ ad_cpu_interconnect 0x79020000 axi_ad9361_0 ad_cpu_interconnect 0x7C420000 axi_ad9361_dac_dma ad_cpu_interconnect 0x7C400000 axi_ad9361_adc_dma ad_cpu_interconnect 0x79040000 axi_ad9361_1 -ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2 -ad_mem_hp2_interconnect $sys_dma_clk axi_ad9361_adc_dma/m_dest_axi -ad_mem_hp3_interconnect $sys_dma_clk sys_ps7/S_AXI_HP3 -ad_mem_hp3_interconnect $sys_dma_clk axi_ad9361_dac_dma/m_src_axi +ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2 $CACHE_COHERENCY +ad_mem_hp2_interconnect $sys_dma_clk axi_ad9361_adc_dma/m_dest_axi $CACHE_COHERENCY +ad_mem_hp3_interconnect $sys_dma_clk sys_ps7/S_AXI_HP3 $CACHE_COHERENCY +ad_mem_hp3_interconnect $sys_dma_clk axi_ad9361_dac_dma/m_src_axi $CACHE_COHERENCY # interrupts diff --git a/projects/fmcomms8/common/fmcomms8_bd.tcl b/projects/fmcomms8/common/fmcomms8_bd.tcl index 41217f2206..a9e1ef0893 100644 --- a/projects/fmcomms8/common/fmcomms8_bd.tcl +++ b/projects/fmcomms8/common/fmcomms8_bd.tcl @@ -19,6 +19,10 @@ create_bd_port -dir I dac_fifo_bypass # [TX/RX/RX_OS]_JESD_NP : Number of bits per sample # +if {![info exists CACHE_COHERENCY]} { + set CACHE_COHERENCY false +} + set MAX_TX_NUM_OF_LANES 8 set MAX_RX_NUM_OF_LANES 4 set MAX_RX_OS_NUM_OF_LANES 4 @@ -97,6 +101,7 @@ ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.DMA_DATA_WIDTH_DEST $dac_data_wid ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.DMA_DATA_WIDTH_SRC 128 ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.FIFO_SIZE 32 ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.MAX_BYTES_PER_BURST 512 +ad_ip_parameter axi_adrv9009_fmc_tx_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY ad_ip_instance axi_adxcvr axi_adrv9009_fmc_rx_xcvr ad_ip_parameter axi_adrv9009_fmc_rx_xcvr CONFIG.NUM_OF_LANES $MAX_RX_NUM_OF_LANES @@ -128,6 +133,7 @@ ad_ip_parameter axi_adrv9009_fmc_rx_dma CONFIG.AXI_SLICE_DEST 1 ad_ip_parameter axi_adrv9009_fmc_rx_dma CONFIG.DMA_2D_TRANSFER 0 ad_ip_parameter axi_adrv9009_fmc_rx_dma CONFIG.DMA_DATA_WIDTH_SRC $adc_dma_data_width ad_ip_parameter axi_adrv9009_fmc_rx_dma CONFIG.DMA_DATA_WIDTH_DEST 128 +ad_ip_parameter axi_adrv9009_fmc_rx_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY ad_ip_instance axi_adxcvr axi_adrv9009_fmc_obs_xcvr ad_ip_parameter axi_adrv9009_fmc_obs_xcvr CONFIG.NUM_OF_LANES $MAX_RX_OS_NUM_OF_LANES @@ -157,6 +163,7 @@ ad_ip_parameter axi_adrv9009_fmc_obs_dma CONFIG.AXI_SLICE_DEST 1 ad_ip_parameter axi_adrv9009_fmc_obs_dma CONFIG.DMA_2D_TRANSFER 0 ad_ip_parameter axi_adrv9009_fmc_obs_dma CONFIG.DMA_DATA_WIDTH_SRC [expr 32*$RX_OS_NUM_OF_LANES] ad_ip_parameter axi_adrv9009_fmc_obs_dma CONFIG.DMA_DATA_WIDTH_DEST 128 +ad_ip_parameter axi_adrv9009_fmc_obs_dma CONFIG.CACHE_COHERENT $CACHE_COHERENCY ad_ip_instance util_adxcvr util_adrv9009_fmc_xcvr ad_ip_parameter util_adrv9009_fmc_xcvr CONFIG.RX_NUM_OF_LANES [expr $MAX_RX_NUM_OF_LANES+$MAX_RX_OS_NUM_OF_LANES] @@ -371,12 +378,12 @@ ad_mem_hp0_interconnect $sys_cpu_clk axi_adrv9009_fmc_obs_xcvr/m_axi # interconnect (mem/dac) -ad_mem_hp1_interconnect $sys_dma_clk sys_ps7/S_AXI_HP1 -ad_mem_hp1_interconnect $sys_dma_clk axi_adrv9009_fmc_tx_dma/m_src_axi -ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2 -ad_mem_hp2_interconnect $sys_dma_clk axi_adrv9009_fmc_rx_dma/m_dest_axi -ad_mem_hp3_interconnect $sys_dma_clk sys_ps7/S_AXI_HP3 -ad_mem_hp3_interconnect $sys_dma_clk axi_adrv9009_fmc_obs_dma/m_dest_axi +ad_mem_hp1_interconnect $sys_dma_clk sys_ps7/S_AXI_HP1 $CACHE_COHERENCY +ad_mem_hp1_interconnect $sys_dma_clk axi_adrv9009_fmc_tx_dma/m_src_axi $CACHE_COHERENCY +ad_mem_hp2_interconnect $sys_dma_clk sys_ps7/S_AXI_HP2 $CACHE_COHERENCY +ad_mem_hp2_interconnect $sys_dma_clk axi_adrv9009_fmc_rx_dma/m_dest_axi $CACHE_COHERENCY +ad_mem_hp3_interconnect $sys_dma_clk sys_ps7/S_AXI_HP3 $CACHE_COHERENCY +ad_mem_hp3_interconnect $sys_dma_clk axi_adrv9009_fmc_obs_dma/m_dest_axi $CACHE_COHERENCY ad_connect $sys_dma_resetn axi_adrv9009_fmc_rx_dma/m_dest_axi_aresetn ad_connect $sys_dma_resetn axi_adrv9009_fmc_tx_dma/m_src_axi_aresetn ad_connect $sys_dma_resetn axi_adrv9009_fmc_obs_dma/m_dest_axi_aresetn diff --git a/projects/scripts/adi_board.tcl b/projects/scripts/adi_board.tcl index cb26587735..70c2518d1b 100644 --- a/projects/scripts/adi_board.tcl +++ b/projects/scripts/adi_board.tcl @@ -1,5 +1,5 @@ ############################################################################### -## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved. +## Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved. ### SPDX short identifier: ADIBSD ############################################################################### @@ -591,7 +591,7 @@ proc ad_xcvrpll {m_src m_dst} { ################################################################################################### ################################################################################################### -## Create an memory mapped interface connection to PS8 IP, using a +## Create a memory mapped interface connection to PS8 IP, using an # HPC0 high speed interface. # # \param[p_clk] - name of the clock or reset source @@ -604,7 +604,7 @@ proc ad_mem_hpc0_interconnect {p_clk p_name} { if {$sys_zynq == 2} {ad_mem_hpx_interconnect "HPC0" $p_clk $p_name} } -## Create an memory mapped interface connection to PS8 IP, using a +## Create a memory mapped interface connection to PS8 IP, using an # HPC1 high speed interface. # # \param[p_clk] - name of the clock or reset source @@ -617,79 +617,91 @@ proc ad_mem_hpc1_interconnect {p_clk p_name} { if {$sys_zynq == 2} {ad_mem_hpx_interconnect "HPC1" $p_clk $p_name} } -## Create an memory mapped interface connection to a MIG or PS7/8 IP, using a -# HP0 high speed interface in case of PSx. +## Create a memory mapped interface connection to a MIG or PS7/8 IP, using an +# HP0 high speed interface in case of PSx. On UltraScale, if cache coherency +# is enabled, an HPC0 high performance coherent interface will be used instead. # # \param[p_clk] - name of the clock or reset source # \param[p_name] - name or list of names of the clock or reset sink +# \param[p_cc] - cache coherency support # -proc ad_mem_hp0_interconnect {p_clk p_name} { +proc ad_mem_hp0_interconnect {p_clk p_name {p_cc false}} { global sys_zynq + global sys_hpc0_interconnect_index - if {($sys_zynq != 1 && $sys_zynq != 2) && ($p_name eq "sys_ps7/S_AXI_HP0")} {return} + if {(($sys_zynq != 1 && $sys_zynq != 2) || ($p_cc && $sys_hpc0_interconnect_index != -1)) && ($p_name eq "sys_ps7/S_AXI_HP0")} {return} if {$sys_zynq == -1} {ad_mem_hpx_interconnect "SIM" $p_clk $p_name} if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name} if {$sys_zynq == 1} {ad_mem_hpx_interconnect "HP0" $p_clk $p_name} - if {$sys_zynq == 2} {ad_mem_hpx_interconnect "HP0" $p_clk $p_name} + if {$sys_zynq == 2} {ad_mem_hpx_interconnect [expr {$p_cc ? "HPC0" : "HP0"}] $p_clk $p_name} if {$sys_zynq == 3} {ad_mem_hpx_interconnect "NOC" $p_clk $p_name} } -## Create an memory mapped interface connection to a MIG or PS7/8 IP, using a -# HP1 high speed interface in case of PSx. +## Create a memory mapped interface connection to a MIG or PS7/8 IP, using an +# HP1 high speed interface in case of PSx. On UltraScale, if cache coherency +# is enabled, an HPC0 high performance coherent interface will be used instead. # # \param[p_clk] - name of the clock or reset source # \param[p_name] - name or list of names of the clock or reset sink +# \param[p_cc] - cache coherency support # -proc ad_mem_hp1_interconnect {p_clk p_name} { +proc ad_mem_hp1_interconnect {p_clk p_name {p_cc false}} { global sys_zynq + global sys_hpc0_interconnect_index - if {($sys_zynq != 1 && $sys_zynq != 2) && ($p_name eq "sys_ps7/S_AXI_HP1")} {return} + if {(($sys_zynq != 1 && $sys_zynq != 2) || ($p_cc && $sys_hpc0_interconnect_index != -1)) && ($p_name eq "sys_ps7/S_AXI_HP1")} {return} if {$sys_zynq == -1} {ad_mem_hpx_interconnect "SIM" $p_clk $p_name} if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name} if {$sys_zynq == 1} {ad_mem_hpx_interconnect "HP1" $p_clk $p_name} - if {$sys_zynq == 2} {ad_mem_hpx_interconnect "HP1" $p_clk $p_name} + if {$sys_zynq == 2} {ad_mem_hpx_interconnect [expr {$p_cc ? "HPC0" : "HP1"}] $p_clk $p_name} if {$sys_zynq == 3} {ad_mem_hpx_interconnect "NOC" $p_clk $p_name} } -## Create an memory mapped interface connection to a MIG or PS7/8 IP, using a -# HP2 high speed interface in case of PSx. +## Create a memory mapped interface connection to a MIG or PS7/8 IP, using an +# HP2 high speed interface in case of PSx. On UltraScale, if cache coherency +# is enabled, an HPC1 high performance coherent interface will be used instead. # # \param[p_clk] - name of the clock or reset source # \param[p_name] - name or list of names of the clock or reset sink +# \param[p_cc] - cache coherency support # -proc ad_mem_hp2_interconnect {p_clk p_name} { +proc ad_mem_hp2_interconnect {p_clk p_name {p_cc false}} { global sys_zynq + global sys_hpc1_interconnect_index - if {($sys_zynq != 1 && $sys_zynq != 2) && ($p_name eq "sys_ps7/S_AXI_HP2")} {return} + if {(($sys_zynq != 1 && $sys_zynq != 2) || ($p_cc && $sys_hpc1_interconnect_index != -1)) && ($p_name eq "sys_ps7/S_AXI_HP2")} {return} if {$sys_zynq == -1} {ad_mem_hpx_interconnect "SIM" $p_clk $p_name} if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name} if {$sys_zynq == 1} {ad_mem_hpx_interconnect "HP2" $p_clk $p_name} - if {$sys_zynq == 2} {ad_mem_hpx_interconnect "HP2" $p_clk $p_name} + if {$sys_zynq == 2} {ad_mem_hpx_interconnect [expr {$p_cc ? "HPC1" : "HP2"}] $p_clk $p_name} if {$sys_zynq == 3} {ad_mem_hpx_interconnect "NOC" $p_clk $p_name} } -## Create an memory mapped interface connection to a MIG or PS7/8 IP, using a -# HP3 high speed interface in case of PSx. +## Create a memory mapped interface connection to a MIG or PS7/8 IP, using an +# HP3 high speed interface in case of PSx. On UltraScale, if cache coherency +# is enabled, an HPC1 high performance coherent interface will be used instead. # # \param[p_clk] - name of the clock or reset source # \param[p_name] - name or list of names of the clock or reset sink +# \param[p_cc] - cache coherency support # -proc ad_mem_hp3_interconnect {p_clk p_name} { +proc ad_mem_hp3_interconnect {p_clk p_name {p_cc false}} { global sys_zynq + global sys_hpc1_interconnect_index - if {($sys_zynq != 1 && $sys_zynq != 2) && ($p_name eq "sys_ps7/S_AXI_HP3")} {return} + if {(($sys_zynq != 1 && $sys_zynq != 2) || ($p_cc && $sys_hpc1_interconnect_index != -1)) && ($p_name eq "sys_ps7/S_AXI_HP3")} {return} if {$sys_zynq == -1} {ad_mem_hpx_interconnect "SIM" $p_clk $p_name} if {$sys_zynq == 0} {ad_mem_hpx_interconnect "MEM" $p_clk $p_name} if {$sys_zynq == 1} {ad_mem_hpx_interconnect "HP3" $p_clk $p_name} - if {$sys_zynq == 2} {ad_mem_hpx_interconnect "HP3" $p_clk $p_name} + if {$sys_zynq == 2} {ad_mem_hpx_interconnect [expr {$p_cc ? "HPC1" : "HP3"}] $p_clk $p_name} if {$sys_zynq == 3} {ad_mem_hpx_interconnect "NOC" $p_clk $p_name} } -## Create an memory mapped interface connection to a MIG or PS7/8 IP, proc is +## Create a memory mapped interface connection to a MIG or PS7/8 IP, proc is # called in the ad_mem_hp[0|1|2|3]_interconnect processes, should never be # directly called in block designs. #