From 05d553b3aa8dc7726842459c71aa4a4305769101 Mon Sep 17 00:00:00 2001 From: Ioan-daniel Pop Date: Tue, 19 Sep 2023 15:16:14 +0300 Subject: [PATCH] add spi engine ad738x I changed the ad738x_bd.tcl, system_bd.tcl, system_top.v for ad738x Signed-off-by: Ioan-daniel Pop --- projects/ad738x_fmc/common/ad738x_bd.tcl | 141 ++++++++--------------- projects/ad738x_fmc/zed/system_bd.tcl | 12 -- projects/ad738x_fmc/zed/system_top.v | 10 +- 3 files changed, 50 insertions(+), 113 deletions(-) diff --git a/projects/ad738x_fmc/common/ad738x_bd.tcl b/projects/ad738x_fmc/common/ad738x_bd.tcl index 099cb2c47a3..d8578e4aa81 100644 --- a/projects/ad738x_fmc/common/ad738x_bd.tcl +++ b/projects/ad738x_fmc/common/ad738x_bd.tcl @@ -3,92 +3,26 @@ ### SPDX short identifier: ADIBSD ############################################################################### -create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 spi - -# create a SPI Engine architecture - -create_bd_cell -type hier spi -current_bd_instance /spi - - create_bd_pin -dir I -type clk clk - create_bd_pin -dir I -type rst resetn - create_bd_pin -dir O irq - create_bd_intf_pin -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 m_spi - create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_SAMPLE - - ad_ip_instance spi_engine_execution execution - ad_ip_parameter execution CONFIG.DATA_WIDTH $adc_resolution - ad_ip_parameter execution CONFIG.NUM_OF_CS 1 - ad_ip_parameter execution CONFIG.NUM_OF_SDI $adc_num_of_channels - - ad_ip_instance axi_spi_engine axi - ad_ip_parameter axi CONFIG.DATA_WIDTH $adc_resolution - ad_ip_parameter axi CONFIG.NUM_OF_SDI $adc_num_of_channels - ad_ip_parameter axi CONFIG.NUM_OFFLOAD 1 - - ad_ip_instance spi_engine_offload offload - ad_ip_parameter offload CONFIG.DATA_WIDTH $adc_resolution - ad_ip_parameter offload CONFIG.NUM_OF_SDI $adc_num_of_channels - - ad_ip_instance spi_engine_interconnect interconnect - ad_ip_parameter interconnect CONFIG.DATA_WIDTH $adc_resolution - ad_ip_parameter interconnect CONFIG.NUM_OF_SDI $adc_num_of_channels - - ad_ip_instance util_pulse_gen trigger_gen - - ## to setup the sample rate of the system change the PULSE_PERIOD value - ## the acutal sample rate will be PULSE_PERIOD * (1/sys_cpu_clk) - ## fsys_cpu_clk is defined to 100 MHZ - set cycle_per_sec_100mhz 100000000 - set sampling_cycle [expr int(ceil(double($cycle_per_sec_100mhz) / $adc_sampling_rate))] - ad_ip_parameter trigger_gen CONFIG.PULSE_PERIOD $sampling_cycle - ad_ip_parameter trigger_gen CONFIG.PULSE_WIDTH 1 - - if {$adc_resolution < 16} { - ad_ip_instance util_axis_upscale axis_upscaler - ad_ip_parameter axis_upscaler CONFIG.NUM_OF_CHANNELS $adc_num_of_channels - ad_ip_parameter axis_upscaler CONFIG.DATA_WIDTH $adc_resolution - ad_ip_parameter axis_upscaler CONFIG.UDATA_WIDTH 16 - ad_connect clk axis_upscaler/clk - ad_connect axi/spi_resetn axis_upscaler/resetn - ad_connect offload/offload_sdi axis_upscaler/s_axis - ad_connect axis_upscaler/m_axis M_AXIS_SAMPLE - ad_connect axis_upscaler/dfmt_enable GND - ad_connect axis_upscaler/dfmt_type GND - ad_connect axis_upscaler/dfmt_se GND - } else { - ad_connect offload/offload_sdi M_AXIS_SAMPLE - } - - ad_connect axi/spi_engine_offload_ctrl0 offload/spi_engine_offload_ctrl - ad_connect offload/spi_engine_ctrl interconnect/s0_ctrl - ad_connect axi/spi_engine_ctrl interconnect/s1_ctrl - ad_connect interconnect/m_ctrl execution/ctrl - - ad_connect execution/spi m_spi - - ad_connect clk offload/spi_clk - ad_connect clk offload/ctrl_clk - ad_connect clk execution/clk - ad_connect clk axi/s_axi_aclk - ad_connect clk axi/spi_clk - ad_connect clk interconnect/clk - ad_connect clk trigger_gen/clk - - ad_connect axi/spi_resetn offload/spi_resetn - ad_connect axi/spi_resetn execution/resetn - ad_connect axi/spi_resetn interconnect/resetn - ad_connect axi/spi_resetn trigger_gen/rstn - ad_connect trigger_gen/load_config GND - ad_connect trigger_gen/pulse_width GND - ad_connect trigger_gen/pulse_period GND - - ad_connect trigger_gen/pulse offload/trigger - - ad_connect resetn axi/s_axi_aresetn - ad_connect irq axi/irq - -current_bd_instance / +create_bd_intf_port -mode Master -vlnv analog.com:interface:spi_master_rtl:1.0 ad738x_spi + +source $ad_hdl_dir/library/spi_engine/scripts/spi_engine.tcl + +set data_width 16 +set async_spi_clk 1 +set num_cs 1 +set num_sdi 2 +set num_sdo 1 +set sdi_delay 1 +set echo_sclk 0 + +set hier_spi_engine spi_ad738x_adc + +spi_engine_create $hier_spi_engine $data_width $async_spi_clk $num_cs $num_sdi $num_sdo $sdi_delay $echo_sclk + +ad_ip_instance axi_pwm_gen spi_trigger_gen +# 300ns pwm period +ad_ip_parameter spi_trigger_gen CONFIG.PULSE_0_PERIOD 48 +ad_ip_parameter spi_trigger_gen CONFIG.PULSE_0_WIDTH 1 ad_ip_instance axi_dmac axi_ad738x_dma ad_ip_parameter axi_ad738x_dma CONFIG.DMA_TYPE_SRC 1 @@ -98,23 +32,38 @@ ad_ip_parameter axi_ad738x_dma CONFIG.SYNC_TRANSFER_START 0 ad_ip_parameter axi_ad738x_dma CONFIG.AXI_SLICE_SRC 0 ad_ip_parameter axi_ad738x_dma CONFIG.AXI_SLICE_DEST 1 ad_ip_parameter axi_ad738x_dma CONFIG.DMA_2D_TRANSFER 0 -ad_ip_parameter axi_ad738x_dma CONFIG.DMA_DATA_WIDTH_SRC [expr $adc_num_of_channels * 16] +ad_ip_parameter axi_ad738x_dma CONFIG.DMA_DATA_WIDTH_SRC 32 ad_ip_parameter axi_ad738x_dma CONFIG.DMA_DATA_WIDTH_DEST 64 -ad_connect sys_cpu_clk spi/clk -ad_connect sys_cpu_resetn spi/resetn -ad_connect sys_cpu_resetn axi_ad738x_dma/m_dest_axi_aresetn +ad_ip_instance axi_clkgen spi_clkgen +ad_ip_parameter spi_clkgen CONFIG.CLK0_DIV 5 +ad_ip_parameter spi_clkgen CONFIG.VCO_DIV 1 +ad_ip_parameter spi_clkgen CONFIG.VCO_MUL 8 -ad_connect spi/m_spi spi -ad_connect axi_ad738x_dma/s_axis spi/M_AXIS_SAMPLE +ad_connect $sys_cpu_clk spi_clkgen/clk +ad_connect spi_clk spi_clkgen/clk_0 -ad_cpu_interconnect 0x44a00000 spi/axi -ad_cpu_interconnect 0x44a30000 axi_ad738x_dma +ad_connect spi_clk spi_trigger_gen/ext_clk +ad_connect $sys_cpu_clk spi_trigger_gen/s_axi_aclk +ad_connect sys_cpu_resetn spi_trigger_gen/s_axi_aresetn +ad_connect spi_trigger_gen/pwm_0 $hier_spi_engine/trigger + +ad_connect axi_ad738x_dma/s_axis $hier_spi_engine/M_AXIS_SAMPLE +ad_connect $hier_spi_engine/m_spi ad738x_spi -ad_connect sys_cpu_clk axi_ad738x_dma/s_axis_aclk +ad_connect $sys_cpu_clk $hier_spi_engine/clk +ad_connect spi_clk $hier_spi_engine/spi_clk +ad_connect spi_clk axi_ad738x_dma/s_axis_aclk +ad_connect sys_cpu_resetn $hier_spi_engine/resetn +ad_connect sys_cpu_resetn axi_ad738x_dma/m_dest_axi_aresetn + +ad_cpu_interconnect 0x44a00000 $hier_spi_engine/${hier_spi_engine}_axi_regmap +ad_cpu_interconnect 0x44a30000 axi_ad738x_dma +ad_cpu_interconnect 0x44a70000 spi_clkgen +ad_cpu_interconnect 0x44b00000 spi_trigger_gen ad_cpu_interrupt "ps-13" "mb-13" axi_ad738x_dma/irq -ad_cpu_interrupt "ps-12" "mb-12" spi/irq +ad_cpu_interrupt "ps-12" "mb-12" $hier_spi_engine/irq ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2 ad_mem_hp2_interconnect sys_cpu_clk axi_ad738x_dma/m_dest_axi diff --git a/projects/ad738x_fmc/zed/system_bd.tcl b/projects/ad738x_fmc/zed/system_bd.tcl index 69fdb467974..fc7582103bf 100644 --- a/projects/ad738x_fmc/zed/system_bd.tcl +++ b/projects/ad738x_fmc/zed/system_bd.tcl @@ -15,17 +15,5 @@ ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 sysid_gen_sys_init_file -# specify ADC resolution -- the design supports 16/14/12 bit resolutions - -set adc_resolution 16 - -# specify the number of active channel -- 1 or 2 or 4 - -set adc_num_of_channels 2 - -# specify ADC sampling rate in sample/seconds -- default is 3 MSPS - -set adc_sampling_rate 3000000 - source ../common/ad738x_bd.tcl diff --git a/projects/ad738x_fmc/zed/system_top.v b/projects/ad738x_fmc/zed/system_top.v index 72de92fe9c5..cffb09b7144 100644 --- a/projects/ad738x_fmc/zed/system_top.v +++ b/projects/ad738x_fmc/zed/system_top.v @@ -172,11 +172,11 @@ module system_top ( .iic_mux_sda_i (iic_mux_sda_i_s), .iic_mux_sda_o (iic_mux_sda_o_s), .iic_mux_sda_t (iic_mux_sda_t_s), - .spi_sdo (spi_sdo), - .spi_sdo_t (), - .spi_sdi ({spi_sdib, spi_sdia}), - .spi_cs (spi_cs), - .spi_sclk (spi_sclk), + .ad738x_spi_sdo (spi_sdo), + .ad738x_spi_sdo_t (), + .ad738x_spi_sdi ({spi_sdib, spi_sdia}), + .ad738x_spi_cs (spi_cs), + .ad738x_spi_sclk (spi_sclk) .otg_vbusoc (otg_vbusoc), .spdif (spdif));