diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Include/gcr_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Include/gcr_regs.h index 318bef56..38e9f2e2 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Include/gcr_regs.h +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Include/gcr_regs.h @@ -681,75 +681,63 @@ typedef struct { * @brief BTLE LDO Control Register * @{ */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXEN_POS 0 /**< BTLELDOCTRL_LDOTXEN Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXEN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXEN_POS)) /**< BTLELDOCTRL_LDOTXEN Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBEN_POS 0 /**< BTLELDOCTRL_LDOBBEN Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBEN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOBBEN_POS)) /**< BTLELDOCTRL_LDOBBEN Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXPULLD_POS 1 /**< BTLELDOCTRL_LDOTXPULLD Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXPULLD_POS)) /**< BTLELDOCTRL_LDOTXPULLD Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBPULLD_POS 1 /**< BTLELDOCTRL_LDOBBPULLD Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOBBPULLD_POS)) /**< BTLELDOCTRL_LDOBBPULLD Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS 2 /**< BTLELDOCTRL_LDOTXVSEL Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS)) /**< BTLELDOCTRL_LDOTXVSEL Mask */ -#define MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_0_7 ((uint32_t)0x0UL) /**< BTLELDOCTRL_LDOTXVSEL_0_7 Value */ -#define MXC_S_GCR_BTLELDOCTRL_LDOTXVSEL_0_7 (MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_0_7 << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS) /**< BTLELDOCTRL_LDOTXVSEL_0_7 Setting */ -#define MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_0_85 ((uint32_t)0x1UL) /**< BTLELDOCTRL_LDOTXVSEL_0_85 Value */ -#define MXC_S_GCR_BTLELDOCTRL_LDOTXVSEL_0_85 (MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_0_85 << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS) /**< BTLELDOCTRL_LDOTXVSEL_0_85 Setting */ -#define MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_0_9 ((uint32_t)0x2UL) /**< BTLELDOCTRL_LDOTXVSEL_0_9 Value */ -#define MXC_S_GCR_BTLELDOCTRL_LDOTXVSEL_0_9 (MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_0_9 << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS) /**< BTLELDOCTRL_LDOTXVSEL_0_9 Setting */ -#define MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_1_1 ((uint32_t)0x3UL) /**< BTLELDOCTRL_LDOTXVSEL_1_1 Value */ -#define MXC_S_GCR_BTLELDOCTRL_LDOTXVSEL_1_1 (MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_1_1 << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS) /**< BTLELDOCTRL_LDOTXVSEL_1_1 Setting */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL_POS 2 /**< BTLELDOCTRL_LDOBBVSEL Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL_POS)) /**< BTLELDOCTRL_LDOBBVSEL Mask */ +#define MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_0_85 ((uint32_t)0x0UL) /**< BTLELDOCTRL_LDOBBVSEL_0_85 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDOBBVSEL_0_85 (MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_0_85 << MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL_POS) /**< BTLELDOCTRL_LDOBBVSEL_0_85 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_0_9 ((uint32_t)0x1UL) /**< BTLELDOCTRL_LDOBBVSEL_0_9 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDOBBVSEL_0_9 (MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_0_9 << MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL_POS) /**< BTLELDOCTRL_LDOBBVSEL_0_9 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_1_0 ((uint32_t)0x2UL) /**< BTLELDOCTRL_LDOBBVSEL_1_0 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDOBBVSEL_1_0 (MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_1_0 << MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL_POS) /**< BTLELDOCTRL_LDOBBVSEL_1_0 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_1_1 ((uint32_t)0x3UL) /**< BTLELDOCTRL_LDOBBVSEL_1_1 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDOBBVSEL_1_1 (MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_1_1 << MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL_POS) /**< BTLELDOCTRL_LDOBBVSEL_1_1 Setting */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL0_POS 2 /**< BTLELDOCTRL_LDOTXVSEL0 Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL0 ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL0_POS)) /**< BTLELDOCTRL_LDOTXVSEL0 Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFEN_POS 4 /**< BTLELDOCTRL_LDORFEN Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFEN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORFEN_POS)) /**< BTLELDOCTRL_LDORFEN Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL1_POS 3 /**< BTLELDOCTRL_LDOTXVSEL1 Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL1 ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL1_POS)) /**< BTLELDOCTRL_LDOTXVSEL1 Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFPULLD_POS 5 /**< BTLELDOCTRL_LDORFPULLD Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORFPULLD_POS)) /**< BTLELDOCTRL_LDORFPULLD Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXEN_POS 4 /**< BTLELDOCTRL_LDORXEN Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXEN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXEN_POS)) /**< BTLELDOCTRL_LDORXEN Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFVSEL_POS 6 /**< BTLELDOCTRL_LDORFVSEL Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFVSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_LDORFVSEL_POS)) /**< BTLELDOCTRL_LDORFVSEL Mask */ +#define MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_0_85 ((uint32_t)0x0UL) /**< BTLELDOCTRL_LDORFVSEL_0_85 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDORFVSEL_0_85 (MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_0_85 << MXC_F_GCR_BTLELDOCTRL_LDORFVSEL_POS) /**< BTLELDOCTRL_LDORFVSEL_0_85 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_0_9 ((uint32_t)0x1UL) /**< BTLELDOCTRL_LDORFVSEL_0_9 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDORFVSEL_0_9 (MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_0_9 << MXC_F_GCR_BTLELDOCTRL_LDORFVSEL_POS) /**< BTLELDOCTRL_LDORFVSEL_0_9 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_1_0 ((uint32_t)0x2UL) /**< BTLELDOCTRL_LDORFVSEL_1_0 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDORFVSEL_1_0 (MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_1_0 << MXC_F_GCR_BTLELDOCTRL_LDORFVSEL_POS) /**< BTLELDOCTRL_LDORFVSEL_1_0 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_1_1 ((uint32_t)0x3UL) /**< BTLELDOCTRL_LDORFVSEL_1_1 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDORFVSEL_1_1 (MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_1_1 << MXC_F_GCR_BTLELDOCTRL_LDORFVSEL_POS) /**< BTLELDOCTRL_LDORFVSEL_1_1 Setting */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXPULLD_POS 5 /**< BTLELDOCTRL_LDORXPULLD Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXPULLD_POS)) /**< BTLELDOCTRL_LDORXPULLD Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFBYP_POS 8 /**< BTLELDOCTRL_LDORFBYP Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFBYP ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORFBYP_POS)) /**< BTLELDOCTRL_LDORFBYP Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS 6 /**< BTLELDOCTRL_LDORXVSEL Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS)) /**< BTLELDOCTRL_LDORXVSEL Mask */ -#define MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_0_7 ((uint32_t)0x0UL) /**< BTLELDOCTRL_LDORXVSEL_0_7 Value */ -#define MXC_S_GCR_BTLELDOCTRL_LDORXVSEL_0_7 (MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_0_7 << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS) /**< BTLELDOCTRL_LDORXVSEL_0_7 Setting */ -#define MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_0_85 ((uint32_t)0x1UL) /**< BTLELDOCTRL_LDORXVSEL_0_85 Value */ -#define MXC_S_GCR_BTLELDOCTRL_LDORXVSEL_0_85 (MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_0_85 << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS) /**< BTLELDOCTRL_LDORXVSEL_0_85 Setting */ -#define MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_0_9 ((uint32_t)0x2UL) /**< BTLELDOCTRL_LDORXVSEL_0_9 Value */ -#define MXC_S_GCR_BTLELDOCTRL_LDORXVSEL_0_9 (MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_0_9 << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS) /**< BTLELDOCTRL_LDORXVSEL_0_9 Setting */ -#define MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_1_1 ((uint32_t)0x3UL) /**< BTLELDOCTRL_LDORXVSEL_1_1 Value */ -#define MXC_S_GCR_BTLELDOCTRL_LDORXVSEL_1_1 (MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_1_1 << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS) /**< BTLELDOCTRL_LDORXVSEL_1_1 Setting */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFDISCH_POS 9 /**< BTLELDOCTRL_LDORFDISCH Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFDISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORFDISCH_POS)) /**< BTLELDOCTRL_LDORFDISCH Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL0_POS 6 /**< BTLELDOCTRL_LDORXVSEL0 Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL0 ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL0_POS)) /**< BTLELDOCTRL_LDORXVSEL0 Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBBYP_POS 10 /**< BTLELDOCTRL_LDOBBBYP Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBBYP ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOBBBYP_POS)) /**< BTLELDOCTRL_LDOBBBYP Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL1_POS 7 /**< BTLELDOCTRL_LDORXVSEL1 Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL1 ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL1_POS)) /**< BTLELDOCTRL_LDORXVSEL1 Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBDISCH_POS 11 /**< BTLELDOCTRL_LDOBBDISCH Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBDISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOBBDISCH_POS)) /**< BTLELDOCTRL_LDOBBDISCH Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXBYP_POS 8 /**< BTLELDOCTRL_LDORXBYP Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXBYP ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXBYP_POS)) /**< BTLELDOCTRL_LDORXBYP Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBENDLY_POS 12 /**< BTLELDOCTRL_LDOBBENDLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOBBENDLY_POS)) /**< BTLELDOCTRL_LDOBBENDLY Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXDISCH_POS 9 /**< BTLELDOCTRL_LDORXDISCH Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXDISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXDISCH_POS)) /**< BTLELDOCTRL_LDORXDISCH Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFENDLY_POS 13 /**< BTLELDOCTRL_LDORFENDLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORFENDLY_POS)) /**< BTLELDOCTRL_LDORFENDLY Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXBYP_POS 10 /**< BTLELDOCTRL_LDOTXBYP Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXBYP ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXBYP_POS)) /**< BTLELDOCTRL_LDOTXBYP Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFBYPENENDLY_POS 14 /**< BTLELDOCTRL_LDORFBYPENENDLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFBYPENENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORFBYPENENDLY_POS)) /**< BTLELDOCTRL_LDORFBYPENENDLY Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXDISCH_POS 11 /**< BTLELDOCTRL_LDOTXDISCH Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXDISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXDISCH_POS)) /**< BTLELDOCTRL_LDOTXDISCH Mask */ - -#define MXC_F_GCR_BTLELDOCTRL_LDOTXENDLY_POS 12 /**< BTLELDOCTRL_LDOTXENDLY Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXENDLY_POS)) /**< BTLELDOCTRL_LDOTXENDLY Mask */ - -#define MXC_F_GCR_BTLELDOCTRL_LDORXENDLY_POS 13 /**< BTLELDOCTRL_LDORXENDLY Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXENDLY_POS)) /**< BTLELDOCTRL_LDORXENDLY Mask */ - -#define MXC_F_GCR_BTLELDOCTRL_LDORXBYPENENDLY_POS 14 /**< BTLELDOCTRL_LDORXBYPENENDLY Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXBYPENENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXBYPENENDLY_POS)) /**< BTLELDOCTRL_LDORXBYPENENDLY Mask */ - -#define MXC_F_GCR_BTLELDOCTRL_LDOTXBYPENENDLY_POS 15 /**< BTLELDOCTRL_LDOTXBYPENENDLY Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXBYPENENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXBYPENENDLY_POS)) /**< BTLELDOCTRL_LDOTXBYPENENDLY Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBBYPENENDLY_POS 15 /**< BTLELDOCTRL_LDOBBBYPENENDLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBBYPENENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOBBBYPENENDLY_POS)) /**< BTLELDOCTRL_LDOBBBYPENENDLY Mask */ /**@} end of group GCR_BTLELDOCTRL_Register */ @@ -762,11 +750,11 @@ typedef struct { #define MXC_F_GCR_BTLELDODLY_BYPDLYCNT_POS 0 /**< BTLELDODLY_BYPDLYCNT Position */ #define MXC_F_GCR_BTLELDODLY_BYPDLYCNT ((uint32_t)(0xFFUL << MXC_F_GCR_BTLELDODLY_BYPDLYCNT_POS)) /**< BTLELDODLY_BYPDLYCNT Mask */ -#define MXC_F_GCR_BTLELDODLY_LDORXDLYCNT_POS 8 /**< BTLELDODLY_LDORXDLYCNT Position */ -#define MXC_F_GCR_BTLELDODLY_LDORXDLYCNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLELDODLY_LDORXDLYCNT_POS)) /**< BTLELDODLY_LDORXDLYCNT Mask */ +#define MXC_F_GCR_BTLELDODLY_LDOBBDLYCNT_POS 8 /**< BTLELDODLY_LDOBBDLYCNT Position */ +#define MXC_F_GCR_BTLELDODLY_LDOBBDLYCNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLELDODLY_LDOBBDLYCNT_POS)) /**< BTLELDODLY_LDOBBDLYCNT Mask */ -#define MXC_F_GCR_BTLELDODLY_LDOTXDLYCNT_POS 20 /**< BTLELDODLY_LDOTXDLYCNT Position */ -#define MXC_F_GCR_BTLELDODLY_LDOTXDLYCNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLELDODLY_LDOTXDLYCNT_POS)) /**< BTLELDODLY_LDOTXDLYCNT Mask */ +#define MXC_F_GCR_BTLELDODLY_LDORFDLYCNT_POS 20 /**< BTLELDODLY_LDORFDLYCNT Position */ +#define MXC_F_GCR_BTLELDODLY_LDORFDLYCNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLELDODLY_LDORFDLYCNT_POS)) /**< BTLELDODLY_LDORFDLYCNT Mask */ /**@} end of group GCR_BTLELDODLY_Register */ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Include/max32655.svd b/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Include/max32655.svd index 7e1cd74e..e371f160 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Include/max32655.svd +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Include/max32655.svd @@ -3822,36 +3822,36 @@ 0x74 - LDOTXEN - LDOTX Enable. + LDOBBEN + LDOBB Enable. 0 1 - LDOTXPULLD - LDOTX Pull Down. + LDOBBPULLD + LDOBB Pull Down. 1 1 - LDOTXVSEL - LDOTX Voltage Setting. + LDOBBVSEL + LDOBB Voltage Setting. 2 2 - - 0_7 - 0.7V - 0 - 0_85 0.85V - 1 + 0 0_9 0.9V + 1 + + + 1_0 + 1.0V 2 @@ -3862,36 +3862,36 @@ - LDORXEN - LDORX Enable. + LDORFEN + LDORF Enable. 4 1 - LDORXPULLD - LDOrX Pull Down. + LDORFPULLD + LDORF Pull Down. 5 1 - LDORXVSEL - LDORX Voltage Setting. + LDORFVSEL + LDORF Voltage Setting. 6 2 - - 0_7 - 0.7V - 0 - 0_85 0.85V - 1 + 0 0_9 0.9V + 1 + + + 1_0 + 1.0V 2 @@ -3902,50 +3902,50 @@ - LDORXBYP - LDORX Bypass Enable. + LDORFBYP + LDORF Bypass Enable. 8 1 - LDORXDISCH - LDORX Discharge. + LDORFDISCH + LDORF Discharge. 9 1 - LDOTXBYP - LDOTX Bypass Enable. + LDOBBBYP + LDOBB Bypass Enable. 10 1 - LDOTXDISCH - LDOTX Discharge. + LDOBBDISCH + LDOBB Discharge. 11 1 - LDOTXENDLY - LDOTX Enable Delay. + LDOBBENDLY + LDOBB Enable Delay. 12 1 - LDORXENDLY - LDORX Enable Delay. + LDORFENDLY + LDORF Enable Delay. 13 1 - LDORXBYPENENDLY - LDORX Bypass Enable Delay. + LDORFBYPENENDLY + LDORF Bypass Enable Delay. 14 1 - LDOTXBYPENENDLY - LDOTX Bypass Enable Delay. + LDOBBBYPENENDLY + LDOBB Bypass Enable Delay. 15 1 @@ -3963,14 +3963,14 @@ 8 - LDORXDLYCNT - LDORX Delay Count. + LDOBBDLYCNT + LDOBB Delay Count. 8 9 - LDOTXDLYCNT - LDOTX Delay Count. + LDORFDLYCNT + LDOBB Delay Count. 20 9 @@ -9257,16 +9257,16 @@ read-write - TX - TX LDO trim value. - 0 + RF + RF LDO trim value. + 16 5 read-write - RX - RX LDO trim value. - 8 + BB + BB LDO trim value. + 24 5 read-write diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Include/sir_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Include/sir_regs.h index 9d58a97e..42173bc2 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Include/sir_regs.h +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Include/sir_regs.h @@ -130,11 +130,11 @@ typedef struct { * @brief BTLE LDO Trim register. * @{ */ -#define MXC_F_SIR_BTLE_LDO_TRIM_TX_POS 0 /**< BTLE_LDO_TRIM_TX Position */ -#define MXC_F_SIR_BTLE_LDO_TRIM_TX ((uint32_t)(0x1FUL << MXC_F_SIR_BTLE_LDO_TRIM_TX_POS)) /**< BTLE_LDO_TRIM_TX Mask */ +#define MXC_F_SIR_BTLE_LDO_TRIM_RF_POS 16 /**< BTLE_LDO_TRIM_RF Position */ +#define MXC_F_SIR_BTLE_LDO_TRIM_RF ((uint32_t)(0x1FUL << MXC_F_SIR_BTLE_LDO_TRIM_RF_POS)) /**< BTLE_LDO_TRIM_RF Mask */ -#define MXC_F_SIR_BTLE_LDO_TRIM_RX_POS 8 /**< BTLE_LDO_TRIM_RX Position */ -#define MXC_F_SIR_BTLE_LDO_TRIM_RX ((uint32_t)(0x1FUL << MXC_F_SIR_BTLE_LDO_TRIM_RX_POS)) /**< BTLE_LDO_TRIM_RX Mask */ +#define MXC_F_SIR_BTLE_LDO_TRIM_BB_POS 24 /**< BTLE_LDO_TRIM_BB Position */ +#define MXC_F_SIR_BTLE_LDO_TRIM_BB ((uint32_t)(0x1FUL << MXC_F_SIR_BTLE_LDO_TRIM_BB_POS)) /**< BTLE_LDO_TRIM_BB Mask */ /**@} end of group SIR_BTLE_LDO_TRIM_Register */ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/gcr_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/gcr_regs.h index a91ec534..a79038e7 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/gcr_regs.h +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/gcr_regs.h @@ -953,64 +953,64 @@ typedef struct { * @brief BTLE LDO Control Register * @{ */ -#define MXC_F_GCR_BTLE_LDOCR_LDOTXEN_POS 0 /**< BTLE_LDOCR_LDOTXEN Position */ -#define MXC_F_GCR_BTLE_LDOCR_LDOTXEN ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDOTXEN_POS)) /**< BTLE_LDOCR_LDOTXEN Mask */ - -#define MXC_F_GCR_BTLE_LDOCR_LDOTXOPULLD_POS 1 /**< BTLE_LDOCR_LDOTXOPULLD Position */ -#define MXC_F_GCR_BTLE_LDOCR_LDOTXOPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDOTXOPULLD_POS)) /**< BTLE_LDOCR_LDOTXOPULLD Mask */ - -#define MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS 2 /**< BTLE_LDOCR_LDOTXVSEL Position */ -#define MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS)) /**< BTLE_LDOCR_LDOTXVSEL Mask */ -#define MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_0_7 ((uint32_t)0x0UL) /**< BTLE_LDOCR_LDOTXVSEL_0_7 Value */ -#define MXC_S_GCR_BTLE_LDOCR_LDOTXVSEL_0_7 (MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_0_7 << MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS) /**< BTLE_LDOCR_LDOTXVSEL_0_7 Setting */ -#define MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_0_85 ((uint32_t)0x1UL) /**< BTLE_LDOCR_LDOTXVSEL_0_85 Value */ -#define MXC_S_GCR_BTLE_LDOCR_LDOTXVSEL_0_85 (MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_0_85 << MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS) /**< BTLE_LDOCR_LDOTXVSEL_0_85 Setting */ -#define MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_0_9 ((uint32_t)0x2UL) /**< BTLE_LDOCR_LDOTXVSEL_0_9 Value */ -#define MXC_S_GCR_BTLE_LDOCR_LDOTXVSEL_0_9 (MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_0_9 << MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS) /**< BTLE_LDOCR_LDOTXVSEL_0_9 Setting */ -#define MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_1_1 ((uint32_t)0x3UL) /**< BTLE_LDOCR_LDOTXVSEL_1_1 Value */ -#define MXC_S_GCR_BTLE_LDOCR_LDOTXVSEL_1_1 (MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_1_1 << MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS) /**< BTLE_LDOCR_LDOTXVSEL_1_1 Setting */ - -#define MXC_F_GCR_BTLE_LDOCR_LDORXEN_POS 4 /**< BTLE_LDOCR_LDORXEN Position */ +#define MXC_F_GCR_BTLE_LDOCR_LDORXEN_POS 0 /**< BTLE_LDOCR_LDORXEN Position */ #define MXC_F_GCR_BTLE_LDOCR_LDORXEN ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDORXEN_POS)) /**< BTLE_LDOCR_LDORXEN Mask */ -#define MXC_F_GCR_BTLE_LDOCR_LDORXPULLD_POS 5 /**< BTLE_LDOCR_LDORXPULLD Position */ -#define MXC_F_GCR_BTLE_LDOCR_LDORXPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDORXPULLD_POS)) /**< BTLE_LDOCR_LDORXPULLD Mask */ +#define MXC_F_GCR_BTLE_LDOCR_LDORXOPULLD_POS 1 /**< BTLE_LDOCR_LDORXOPULLD Position */ +#define MXC_F_GCR_BTLE_LDOCR_LDORXOPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDORXOPULLD_POS)) /**< BTLE_LDOCR_LDORXOPULLD Mask */ -#define MXC_F_GCR_BTLE_LDOCR_LDORXVSEL_POS 6 /**< BTLE_LDOCR_LDORXVSEL Position */ +#define MXC_F_GCR_BTLE_LDOCR_LDORXVSEL_POS 2 /**< BTLE_LDOCR_LDORXVSEL Position */ #define MXC_F_GCR_BTLE_LDOCR_LDORXVSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLE_LDOCR_LDORXVSEL_POS)) /**< BTLE_LDOCR_LDORXVSEL Mask */ -#define MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_0_7 ((uint32_t)0x0UL) /**< BTLE_LDOCR_LDORXVSEL_0_7 Value */ -#define MXC_S_GCR_BTLE_LDOCR_LDORXVSEL_0_7 (MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_0_7 << MXC_F_GCR_BTLE_LDOCR_LDORXVSEL_POS) /**< BTLE_LDOCR_LDORXVSEL_0_7 Setting */ -#define MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_0_85 ((uint32_t)0x1UL) /**< BTLE_LDOCR_LDORXVSEL_0_85 Value */ +#define MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_0_85 ((uint32_t)0x0UL) /**< BTLE_LDOCR_LDORXVSEL_0_85 Value */ #define MXC_S_GCR_BTLE_LDOCR_LDORXVSEL_0_85 (MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_0_85 << MXC_F_GCR_BTLE_LDOCR_LDORXVSEL_POS) /**< BTLE_LDOCR_LDORXVSEL_0_85 Setting */ -#define MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_0_9 ((uint32_t)0x2UL) /**< BTLE_LDOCR_LDORXVSEL_0_9 Value */ +#define MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_0_9 ((uint32_t)0x1UL) /**< BTLE_LDOCR_LDORXVSEL_0_9 Value */ #define MXC_S_GCR_BTLE_LDOCR_LDORXVSEL_0_9 (MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_0_9 << MXC_F_GCR_BTLE_LDOCR_LDORXVSEL_POS) /**< BTLE_LDOCR_LDORXVSEL_0_9 Setting */ +#define MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_1_0 ((uint32_t)0x2UL) /**< BTLE_LDOCR_LDORXVSEL_1_0 Value */ +#define MXC_S_GCR_BTLE_LDOCR_LDORXVSEL_1_0 (MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_1_0 << MXC_F_GCR_BTLE_LDOCR_LDORXVSEL_POS) /**< BTLE_LDOCR_LDORXVSEL_1_0 Setting */ #define MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_1_1 ((uint32_t)0x3UL) /**< BTLE_LDOCR_LDORXVSEL_1_1 Value */ #define MXC_S_GCR_BTLE_LDOCR_LDORXVSEL_1_1 (MXC_V_GCR_BTLE_LDOCR_LDORXVSEL_1_1 << MXC_F_GCR_BTLE_LDOCR_LDORXVSEL_POS) /**< BTLE_LDOCR_LDORXVSEL_1_1 Setting */ -#define MXC_F_GCR_BTLE_LDOCR_LDORXBYP_POS 8 /**< BTLE_LDOCR_LDORXBYP Position */ -#define MXC_F_GCR_BTLE_LDOCR_LDORXBYP ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDORXBYP_POS)) /**< BTLE_LDOCR_LDORXBYP Mask */ +#define MXC_F_GCR_BTLE_LDOCR_LDOTXEN_POS 4 /**< BTLE_LDOCR_LDOTXEN Position */ +#define MXC_F_GCR_BTLE_LDOCR_LDOTXEN ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDOTXEN_POS)) /**< BTLE_LDOCR_LDOTXEN Mask */ -#define MXC_F_GCR_BTLE_LDOCR_LDORXDISCH_POS 9 /**< BTLE_LDOCR_LDORXDISCH Position */ -#define MXC_F_GCR_BTLE_LDOCR_LDORXDISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDORXDISCH_POS)) /**< BTLE_LDOCR_LDORXDISCH Mask */ +#define MXC_F_GCR_BTLE_LDOCR_LDOTXPULLD_POS 5 /**< BTLE_LDOCR_LDOTXPULLD Position */ +#define MXC_F_GCR_BTLE_LDOCR_LDOTXPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDOTXPULLD_POS)) /**< BTLE_LDOCR_LDOTXPULLD Mask */ + +#define MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS 6 /**< BTLE_LDOCR_LDOTXVSEL Position */ +#define MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS)) /**< BTLE_LDOCR_LDOTXVSEL Mask */ +#define MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_0_85 ((uint32_t)0x0UL) /**< BTLE_LDOCR_LDOTXVSEL_0_85 Value */ +#define MXC_S_GCR_BTLE_LDOCR_LDOTXVSEL_0_85 (MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_0_85 << MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS) /**< BTLE_LDOCR_LDOTXVSEL_0_85 Setting */ +#define MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_0_9 ((uint32_t)0x1UL) /**< BTLE_LDOCR_LDOTXVSEL_0_9 Value */ +#define MXC_S_GCR_BTLE_LDOCR_LDOTXVSEL_0_9 (MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_0_9 << MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS) /**< BTLE_LDOCR_LDOTXVSEL_0_9 Setting */ +#define MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_1_0 ((uint32_t)0x2UL) /**< BTLE_LDOCR_LDOTXVSEL_1_0 Value */ +#define MXC_S_GCR_BTLE_LDOCR_LDOTXVSEL_1_0 (MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_1_0 << MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS) /**< BTLE_LDOCR_LDOTXVSEL_1_0 Setting */ +#define MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_1_1 ((uint32_t)0x3UL) /**< BTLE_LDOCR_LDOTXVSEL_1_1 Value */ +#define MXC_S_GCR_BTLE_LDOCR_LDOTXVSEL_1_1 (MXC_V_GCR_BTLE_LDOCR_LDOTXVSEL_1_1 << MXC_F_GCR_BTLE_LDOCR_LDOTXVSEL_POS) /**< BTLE_LDOCR_LDOTXVSEL_1_1 Setting */ -#define MXC_F_GCR_BTLE_LDOCR_LDOTXBYP_POS 10 /**< BTLE_LDOCR_LDOTXBYP Position */ +#define MXC_F_GCR_BTLE_LDOCR_LDOTXBYP_POS 8 /**< BTLE_LDOCR_LDOTXBYP Position */ #define MXC_F_GCR_BTLE_LDOCR_LDOTXBYP ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDOTXBYP_POS)) /**< BTLE_LDOCR_LDOTXBYP Mask */ -#define MXC_F_GCR_BTLE_LDOCR_LDOTXDISCH_POS 11 /**< BTLE_LDOCR_LDOTXDISCH Position */ +#define MXC_F_GCR_BTLE_LDOCR_LDOTXDISCH_POS 9 /**< BTLE_LDOCR_LDOTXDISCH Position */ #define MXC_F_GCR_BTLE_LDOCR_LDOTXDISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDOTXDISCH_POS)) /**< BTLE_LDOCR_LDOTXDISCH Mask */ -#define MXC_F_GCR_BTLE_LDOCR_LDOTXENDLY_POS 12 /**< BTLE_LDOCR_LDOTXENDLY Position */ -#define MXC_F_GCR_BTLE_LDOCR_LDOTXENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDOTXENDLY_POS)) /**< BTLE_LDOCR_LDOTXENDLY Mask */ +#define MXC_F_GCR_BTLE_LDOCR_LDORXBYP_POS 10 /**< BTLE_LDOCR_LDORXBYP Position */ +#define MXC_F_GCR_BTLE_LDOCR_LDORXBYP ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDORXBYP_POS)) /**< BTLE_LDOCR_LDORXBYP Mask */ + +#define MXC_F_GCR_BTLE_LDOCR_LDORXDISCH_POS 11 /**< BTLE_LDOCR_LDORXDISCH Position */ +#define MXC_F_GCR_BTLE_LDOCR_LDORXDISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDORXDISCH_POS)) /**< BTLE_LDOCR_LDORXDISCH Mask */ -#define MXC_F_GCR_BTLE_LDOCR_LDORXENDLY_POS 13 /**< BTLE_LDOCR_LDORXENDLY Position */ +#define MXC_F_GCR_BTLE_LDOCR_LDORXENDLY_POS 12 /**< BTLE_LDOCR_LDORXENDLY Position */ #define MXC_F_GCR_BTLE_LDOCR_LDORXENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDORXENDLY_POS)) /**< BTLE_LDOCR_LDORXENDLY Mask */ -#define MXC_F_GCR_BTLE_LDOCR_LDORXBYPENENDLY_POS 14 /**< BTLE_LDOCR_LDORXBYPENENDLY Position */ -#define MXC_F_GCR_BTLE_LDOCR_LDORXBYPENENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDORXBYPENENDLY_POS)) /**< BTLE_LDOCR_LDORXBYPENENDLY Mask */ +#define MXC_F_GCR_BTLE_LDOCR_LDOTXENDLY_POS 13 /**< BTLE_LDOCR_LDOTXENDLY Position */ +#define MXC_F_GCR_BTLE_LDOCR_LDOTXENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDOTXENDLY_POS)) /**< BTLE_LDOCR_LDOTXENDLY Mask */ -#define MXC_F_GCR_BTLE_LDOCR_LDOTXBYPENENDLY_POS 15 /**< BTLE_LDOCR_LDOTXBYPENENDLY Position */ +#define MXC_F_GCR_BTLE_LDOCR_LDOTXBYPENENDLY_POS 14 /**< BTLE_LDOCR_LDOTXBYPENENDLY Position */ #define MXC_F_GCR_BTLE_LDOCR_LDOTXBYPENENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDOTXBYPENENDLY_POS)) /**< BTLE_LDOCR_LDOTXBYPENENDLY Mask */ +#define MXC_F_GCR_BTLE_LDOCR_LDORXBYPENENDLY_POS 15 /**< BTLE_LDOCR_LDORXBYPENENDLY Position */ +#define MXC_F_GCR_BTLE_LDOCR_LDORXBYPENENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLE_LDOCR_LDORXBYPENENDLY_POS)) /**< BTLE_LDOCR_LDORXBYPENENDLY Mask */ + /**@} end of group GCR_BTLE_LDOCR_Register */ /** @@ -1022,12 +1022,12 @@ typedef struct { #define MXC_F_GCR_BTLE_LDODCR_BYPDLYCNT_POS 0 /**< BTLE_LDODCR_BYPDLYCNT Position */ #define MXC_F_GCR_BTLE_LDODCR_BYPDLYCNT ((uint32_t)(0xFFUL << MXC_F_GCR_BTLE_LDODCR_BYPDLYCNT_POS)) /**< BTLE_LDODCR_BYPDLYCNT Mask */ -#define MXC_F_GCR_BTLE_LDODCR_LDORXDLYCNT_POS 8 /**< BTLE_LDODCR_LDORXDLYCNT Position */ -#define MXC_F_GCR_BTLE_LDODCR_LDORXDLYCNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLE_LDODCR_LDORXDLYCNT_POS)) /**< BTLE_LDODCR_LDORXDLYCNT Mask */ - -#define MXC_F_GCR_BTLE_LDODCR_LDOTXDLYCNT_POS 20 /**< BTLE_LDODCR_LDOTXDLYCNT Position */ +#define MXC_F_GCR_BTLE_LDODCR_LDOTXDLYCNT_POS 8 /**< BTLE_LDODCR_LDOTXDLYCNT Position */ #define MXC_F_GCR_BTLE_LDODCR_LDOTXDLYCNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLE_LDODCR_LDOTXDLYCNT_POS)) /**< BTLE_LDODCR_LDOTXDLYCNT Mask */ +#define MXC_F_GCR_BTLE_LDODCR_LDORXDLYCNT_POS 20 /**< BTLE_LDODCR_LDORXDLYCNT Position */ +#define MXC_F_GCR_BTLE_LDODCR_LDORXDLYCNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLE_LDODCR_LDORXDLYCNT_POS)) /**< BTLE_LDODCR_LDORXDLYCNT Mask */ + /**@} end of group GCR_BTLE_LDODCR_Register */ /** diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/max32665.svd b/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/max32665.svd index ff0bf637..095e976e 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/max32665.svd +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/max32665.svd @@ -4099,8 +4099,8 @@ 0x74 - LDOTXEN - LDOTX Enable + LDORXEN + LDORX Enable 0 1 @@ -4117,8 +4117,8 @@ - LDOTXOPULLD - LDOTX PULL Disable + LDORXOPULLD + LDORX PULL Disable 1 1 @@ -4135,24 +4135,24 @@ - LDOTXVSEL - LDOTX Voltage Setting + LDORXVSEL + LDORX Voltage Setting 2 2 - - 0_7 - 0.7V - 0 - 0_85 0.85V - 1 + 0 0_9 0.9V + 1 + + + 1_0 + 1.0V 2 @@ -4163,8 +4163,8 @@ - LDORXEN - LDORX Enable + LDOTXEN + LDOTX Enable 4 1 @@ -4181,8 +4181,8 @@ - LDORXPULLD - LDORX Pulldown + LDOTXPULLD + LDOTX Pulldown 5 1 @@ -4199,24 +4199,24 @@ - LDORXVSEL - LDORX Output Voltage Setting + LDOTXVSEL + LDOTX Output Voltage Setting 6 2 - - 0_7 - 0.7V - 0 - 0_85 0.85V - 1 + 0 0_9 0.9V + 1 + + + 1_0 + 1.0V 2 @@ -4227,8 +4227,8 @@ - LDORXBYP - LDORX Bypass Enable + LDOTXBYP + LDOTX Bypass Enable 8 1 @@ -4245,8 +4245,8 @@ - LDORXDISCH - LDORX Discharge + LDOTXDISCH + LDOTX Discharge 9 1 @@ -4263,8 +4263,8 @@ - LDOTXBYP - LDOTX Bypass Enable + LDORXBYP + LDORX Bypass Enable 10 1 @@ -4281,8 +4281,8 @@ - LDOTXDISCH - LDOTX Discharge + LDORXDISCH + LDORX Discharge 11 1 @@ -4299,8 +4299,8 @@ - LDOTXENDLY - LDOTX Enable Delay + LDORXENDLY + LDORX Enable Delay 12 1 @@ -4317,8 +4317,8 @@ - LDORXENDLY - LDORX Enable Delay + LDOTXENDLY + LDOTX Enable Delay 13 1 @@ -4335,14 +4335,14 @@ - LDORXBYPENENDLY - LDOTX Bypass Enable Delay + LDOTXBYPENENDLY + LDORX Bypass Enable Delay 14 1 - LDOTXBYPENENDLY - LDORX Bypass Enable Delay + LDORXBYPENENDLY + LDOTX Bypass Enable Delay 15 1 @@ -4360,14 +4360,14 @@ 8 - LDORXDLYCNT - LDORX Delay Count. Count delay base on PCLK/128. + LDOTXDLYCNT + LDOTX Delay Count. Count delay base on PCLK/128. 8 9 - LDOTXDLYCNT - LDOTX Delay Count. Count delay base on PCLK/128. + LDORXDLYCNT + LDORX Delay Count. Count delay base on PCLK/128. 20 9 @@ -13121,7 +13121,8 @@ MAGIC - Magic Word Validation. This bit is set by the system initialization block following power-up. + Magic Word Validation. This bit is set by the system initialization block + following power-up. 0 1 read-only @@ -13141,7 +13142,8 @@ CRCERR - CRC Error Status. This bit is set by the system initialization block following power-up. + CRC Error Status. This bit is set by the system initialization block + following power-up. 1 1 read-only @@ -13154,7 +13156,8 @@ error - A CRC error occurred while reading the OTP. The address of the failure location in the OTP memory is stored in the ERRADDR register. + A CRC error occurred while reading the OTP. The address of the failure + location in the OTP memory is stored in the ERRADDR register. 1 @@ -13163,7 +13166,8 @@ ERRADDR - Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1). + Read-only field set by the SIB block if a CRC error occurs during the read of + the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1). 0x04 read-only @@ -13174,6 +13178,36 @@ + + BTLE_LDO_TRIM_TX + BTLE LDO TX Trim register. + 0x54 + read-write + + + TX + TX LDO trim value. + 0 + 5 + read-write + + + + + BTLE_LDO_TRIM_RX + BTLE LDO RX Trim register. + 0x5C + read-write + + + RX + RX LDO trim value. + 0 + 5 + read-write + + + FSTAT funcstat register. diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/sir_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/sir_regs.h index b9749da3..70db2add 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/sir_regs.h +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Include/sir_regs.h @@ -76,7 +76,11 @@ extern "C" { typedef struct { __I uint32_t sistat; /**< \b 0x00: SIR SISTAT Register */ __I uint32_t erraddr; /**< \b 0x04: SIR ERRADDR Register */ - __R uint32_t rsv_0x8_0xff[62]; + __R uint32_t rsv_0x8_0x53[19]; + __IO uint32_t btle_ldo_trim_tx; /**< \b 0x54: SIR BTLE_LDO_TRIM_TX Register */ + __R uint32_t rsv_0x58; + __IO uint32_t btle_ldo_trim_rx; /**< \b 0x5C: SIR BTLE_LDO_TRIM_RX Register */ + __R uint32_t rsv_0x60_0xff[40]; __I uint32_t fstat; /**< \b 0x100: SIR FSTAT Register */ __I uint32_t sfstat; /**< \b 0x104: SIR SFSTAT Register */ } mxc_sir_regs_t; @@ -90,6 +94,8 @@ typedef struct { */ #define MXC_R_SIR_SISTAT ((uint32_t)0x00000000UL) /**< Offset from SIR Base Address: 0x0000 */ #define MXC_R_SIR_ERRADDR ((uint32_t)0x00000004UL) /**< Offset from SIR Base Address: 0x0004 */ +#define MXC_R_SIR_BTLE_LDO_TRIM_TX ((uint32_t)0x00000054UL) /**< Offset from SIR Base Address: 0x0054 */ +#define MXC_R_SIR_BTLE_LDO_TRIM_RX ((uint32_t)0x0000005CUL) /**< Offset from SIR Base Address: 0x005C */ #define MXC_R_SIR_FSTAT ((uint32_t)0x00000100UL) /**< Offset from SIR Base Address: 0x0100 */ #define MXC_R_SIR_SFSTAT ((uint32_t)0x00000104UL) /**< Offset from SIR Base Address: 0x0104 */ /**@} end of group sir_registers */ @@ -121,6 +127,28 @@ typedef struct { /**@} end of group SIR_ERRADDR_Register */ +/** + * @ingroup sir_registers + * @defgroup SIR_BTLE_LDO_TRIM_TX SIR_BTLE_LDO_TRIM_TX + * @brief BTLE LDO TX Trim register. + * @{ + */ +#define MXC_F_SIR_BTLE_LDO_TRIM_TX_TX_POS 0 /**< BTLE_LDO_TRIM_TX_TX Position */ +#define MXC_F_SIR_BTLE_LDO_TRIM_TX_TX ((uint32_t)(0x1FUL << MXC_F_SIR_BTLE_LDO_TRIM_TX_TX_POS)) /**< BTLE_LDO_TRIM_TX_TX Mask */ + +/**@} end of group SIR_BTLE_LDO_TRIM_TX_Register */ + +/** + * @ingroup sir_registers + * @defgroup SIR_BTLE_LDO_TRIM_RX SIR_BTLE_LDO_TRIM_RX + * @brief BTLE LDO RX Trim register. + * @{ + */ +#define MXC_F_SIR_BTLE_LDO_TRIM_RX_RX_POS 0 /**< BTLE_LDO_TRIM_RX_RX Position */ +#define MXC_F_SIR_BTLE_LDO_TRIM_RX_RX ((uint32_t)(0x1FUL << MXC_F_SIR_BTLE_LDO_TRIM_RX_RX_POS)) /**< BTLE_LDO_TRIM_RX_RX Mask */ + +/**@} end of group SIR_BTLE_LDO_TRIM_RX_Register */ + /** * @ingroup sir_registers * @defgroup SIR_FSTAT SIR_FSTAT diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32680/Include/gcr_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32680/Include/gcr_regs.h index 5a329868..ff049258 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32680/Include/gcr_regs.h +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32680/Include/gcr_regs.h @@ -681,75 +681,63 @@ typedef struct { * @brief BTLE LDO Control Register * @{ */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXEN_POS 0 /**< BTLELDOCTRL_LDOTXEN Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXEN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXEN_POS)) /**< BTLELDOCTRL_LDOTXEN Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBEN_POS 0 /**< BTLELDOCTRL_LDOBBEN Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBEN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOBBEN_POS)) /**< BTLELDOCTRL_LDOBBEN Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXPULLD_POS 1 /**< BTLELDOCTRL_LDOTXPULLD Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXPULLD_POS)) /**< BTLELDOCTRL_LDOTXPULLD Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBPULLD_POS 1 /**< BTLELDOCTRL_LDOBBPULLD Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOBBPULLD_POS)) /**< BTLELDOCTRL_LDOBBPULLD Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS 2 /**< BTLELDOCTRL_LDOTXVSEL Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS)) /**< BTLELDOCTRL_LDOTXVSEL Mask */ -#define MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_0_7 ((uint32_t)0x0UL) /**< BTLELDOCTRL_LDOTXVSEL_0_7 Value */ -#define MXC_S_GCR_BTLELDOCTRL_LDOTXVSEL_0_7 (MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_0_7 << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS) /**< BTLELDOCTRL_LDOTXVSEL_0_7 Setting */ -#define MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_0_85 ((uint32_t)0x1UL) /**< BTLELDOCTRL_LDOTXVSEL_0_85 Value */ -#define MXC_S_GCR_BTLELDOCTRL_LDOTXVSEL_0_85 (MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_0_85 << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS) /**< BTLELDOCTRL_LDOTXVSEL_0_85 Setting */ -#define MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_0_9 ((uint32_t)0x2UL) /**< BTLELDOCTRL_LDOTXVSEL_0_9 Value */ -#define MXC_S_GCR_BTLELDOCTRL_LDOTXVSEL_0_9 (MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_0_9 << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS) /**< BTLELDOCTRL_LDOTXVSEL_0_9 Setting */ -#define MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_1_1 ((uint32_t)0x3UL) /**< BTLELDOCTRL_LDOTXVSEL_1_1 Value */ -#define MXC_S_GCR_BTLELDOCTRL_LDOTXVSEL_1_1 (MXC_V_GCR_BTLELDOCTRL_LDOTXVSEL_1_1 << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS) /**< BTLELDOCTRL_LDOTXVSEL_1_1 Setting */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL_POS 2 /**< BTLELDOCTRL_LDOBBVSEL Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL_POS)) /**< BTLELDOCTRL_LDOBBVSEL Mask */ +#define MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_0_85 ((uint32_t)0x0UL) /**< BTLELDOCTRL_LDOBBVSEL_0_85 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDOBBVSEL_0_85 (MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_0_85 << MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL_POS) /**< BTLELDOCTRL_LDOBBVSEL_0_85 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_0_9 ((uint32_t)0x1UL) /**< BTLELDOCTRL_LDOBBVSEL_0_9 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDOBBVSEL_0_9 (MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_0_9 << MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL_POS) /**< BTLELDOCTRL_LDOBBVSEL_0_9 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_1_0 ((uint32_t)0x2UL) /**< BTLELDOCTRL_LDOBBVSEL_1_0 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDOBBVSEL_1_0 (MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_1_0 << MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL_POS) /**< BTLELDOCTRL_LDOBBVSEL_1_0 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_1_1 ((uint32_t)0x3UL) /**< BTLELDOCTRL_LDOBBVSEL_1_1 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDOBBVSEL_1_1 (MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_1_1 << MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL_POS) /**< BTLELDOCTRL_LDOBBVSEL_1_1 Setting */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL0_POS 2 /**< BTLELDOCTRL_LDOTXVSEL0 Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL0 ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL0_POS)) /**< BTLELDOCTRL_LDOTXVSEL0 Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFEN_POS 4 /**< BTLELDOCTRL_LDORFEN Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFEN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORFEN_POS)) /**< BTLELDOCTRL_LDORFEN Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL1_POS 3 /**< BTLELDOCTRL_LDOTXVSEL1 Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL1 ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL1_POS)) /**< BTLELDOCTRL_LDOTXVSEL1 Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFPULLD_POS 5 /**< BTLELDOCTRL_LDORFPULLD Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORFPULLD_POS)) /**< BTLELDOCTRL_LDORFPULLD Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXEN_POS 4 /**< BTLELDOCTRL_LDORXEN Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXEN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXEN_POS)) /**< BTLELDOCTRL_LDORXEN Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFVSEL_POS 6 /**< BTLELDOCTRL_LDORFVSEL Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFVSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_LDORFVSEL_POS)) /**< BTLELDOCTRL_LDORFVSEL Mask */ +#define MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_0_85 ((uint32_t)0x0UL) /**< BTLELDOCTRL_LDORFVSEL_0_85 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDORFVSEL_0_85 (MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_0_85 << MXC_F_GCR_BTLELDOCTRL_LDORFVSEL_POS) /**< BTLELDOCTRL_LDORFVSEL_0_85 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_0_9 ((uint32_t)0x1UL) /**< BTLELDOCTRL_LDORFVSEL_0_9 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDORFVSEL_0_9 (MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_0_9 << MXC_F_GCR_BTLELDOCTRL_LDORFVSEL_POS) /**< BTLELDOCTRL_LDORFVSEL_0_9 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_1_0 ((uint32_t)0x2UL) /**< BTLELDOCTRL_LDORFVSEL_1_0 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDORFVSEL_1_0 (MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_1_0 << MXC_F_GCR_BTLELDOCTRL_LDORFVSEL_POS) /**< BTLELDOCTRL_LDORFVSEL_1_0 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_1_1 ((uint32_t)0x3UL) /**< BTLELDOCTRL_LDORFVSEL_1_1 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDORFVSEL_1_1 (MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_1_1 << MXC_F_GCR_BTLELDOCTRL_LDORFVSEL_POS) /**< BTLELDOCTRL_LDORFVSEL_1_1 Setting */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXPULLD_POS 5 /**< BTLELDOCTRL_LDORXPULLD Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXPULLD_POS)) /**< BTLELDOCTRL_LDORXPULLD Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFBYP_POS 8 /**< BTLELDOCTRL_LDORFBYP Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFBYP ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORFBYP_POS)) /**< BTLELDOCTRL_LDORFBYP Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS 6 /**< BTLELDOCTRL_LDORXVSEL Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS)) /**< BTLELDOCTRL_LDORXVSEL Mask */ -#define MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_0_7 ((uint32_t)0x0UL) /**< BTLELDOCTRL_LDORXVSEL_0_7 Value */ -#define MXC_S_GCR_BTLELDOCTRL_LDORXVSEL_0_7 (MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_0_7 << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS) /**< BTLELDOCTRL_LDORXVSEL_0_7 Setting */ -#define MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_0_85 ((uint32_t)0x1UL) /**< BTLELDOCTRL_LDORXVSEL_0_85 Value */ -#define MXC_S_GCR_BTLELDOCTRL_LDORXVSEL_0_85 (MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_0_85 << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS) /**< BTLELDOCTRL_LDORXVSEL_0_85 Setting */ -#define MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_0_9 ((uint32_t)0x2UL) /**< BTLELDOCTRL_LDORXVSEL_0_9 Value */ -#define MXC_S_GCR_BTLELDOCTRL_LDORXVSEL_0_9 (MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_0_9 << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS) /**< BTLELDOCTRL_LDORXVSEL_0_9 Setting */ -#define MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_1_1 ((uint32_t)0x3UL) /**< BTLELDOCTRL_LDORXVSEL_1_1 Value */ -#define MXC_S_GCR_BTLELDOCTRL_LDORXVSEL_1_1 (MXC_V_GCR_BTLELDOCTRL_LDORXVSEL_1_1 << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS) /**< BTLELDOCTRL_LDORXVSEL_1_1 Setting */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFDISCH_POS 9 /**< BTLELDOCTRL_LDORFDISCH Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFDISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORFDISCH_POS)) /**< BTLELDOCTRL_LDORFDISCH Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL0_POS 6 /**< BTLELDOCTRL_LDORXVSEL0 Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL0 ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL0_POS)) /**< BTLELDOCTRL_LDORXVSEL0 Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBBYP_POS 10 /**< BTLELDOCTRL_LDOBBBYP Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBBYP ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOBBBYP_POS)) /**< BTLELDOCTRL_LDOBBBYP Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL1_POS 7 /**< BTLELDOCTRL_LDORXVSEL1 Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL1 ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL1_POS)) /**< BTLELDOCTRL_LDORXVSEL1 Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBDISCH_POS 11 /**< BTLELDOCTRL_LDOBBDISCH Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBDISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOBBDISCH_POS)) /**< BTLELDOCTRL_LDOBBDISCH Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXBYP_POS 8 /**< BTLELDOCTRL_LDORXBYP Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXBYP ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXBYP_POS)) /**< BTLELDOCTRL_LDORXBYP Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBENDLY_POS 12 /**< BTLELDOCTRL_LDOBBENDLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOBBENDLY_POS)) /**< BTLELDOCTRL_LDOBBENDLY Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXDISCH_POS 9 /**< BTLELDOCTRL_LDORXDISCH Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXDISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXDISCH_POS)) /**< BTLELDOCTRL_LDORXDISCH Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFENDLY_POS 13 /**< BTLELDOCTRL_LDORFENDLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORFENDLY_POS)) /**< BTLELDOCTRL_LDORFENDLY Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXBYP_POS 10 /**< BTLELDOCTRL_LDOTXBYP Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXBYP ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXBYP_POS)) /**< BTLELDOCTRL_LDOTXBYP Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFBYPENENDLY_POS 14 /**< BTLELDOCTRL_LDORFBYPENENDLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFBYPENENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORFBYPENENDLY_POS)) /**< BTLELDOCTRL_LDORFBYPENENDLY Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXDISCH_POS 11 /**< BTLELDOCTRL_LDOTXDISCH Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXDISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXDISCH_POS)) /**< BTLELDOCTRL_LDOTXDISCH Mask */ - -#define MXC_F_GCR_BTLELDOCTRL_LDOTXENDLY_POS 12 /**< BTLELDOCTRL_LDOTXENDLY Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXENDLY_POS)) /**< BTLELDOCTRL_LDOTXENDLY Mask */ - -#define MXC_F_GCR_BTLELDOCTRL_LDORXENDLY_POS 13 /**< BTLELDOCTRL_LDORXENDLY Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXENDLY_POS)) /**< BTLELDOCTRL_LDORXENDLY Mask */ - -#define MXC_F_GCR_BTLELDOCTRL_LDORXBYPENENDLY_POS 14 /**< BTLELDOCTRL_LDORXBYPENENDLY Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXBYPENENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXBYPENENDLY_POS)) /**< BTLELDOCTRL_LDORXBYPENENDLY Mask */ - -#define MXC_F_GCR_BTLELDOCTRL_LDOTXBYPENENDLY_POS 15 /**< BTLELDOCTRL_LDOTXBYPENENDLY Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXBYPENENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXBYPENENDLY_POS)) /**< BTLELDOCTRL_LDOTXBYPENENDLY Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBBYPENENDLY_POS 15 /**< BTLELDOCTRL_LDOBBBYPENENDLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBBYPENENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOBBBYPENENDLY_POS)) /**< BTLELDOCTRL_LDOBBBYPENENDLY Mask */ /**@} end of group GCR_BTLELDOCTRL_Register */ @@ -762,11 +750,11 @@ typedef struct { #define MXC_F_GCR_BTLELDODLY_BYPDLYCNT_POS 0 /**< BTLELDODLY_BYPDLYCNT Position */ #define MXC_F_GCR_BTLELDODLY_BYPDLYCNT ((uint32_t)(0xFFUL << MXC_F_GCR_BTLELDODLY_BYPDLYCNT_POS)) /**< BTLELDODLY_BYPDLYCNT Mask */ -#define MXC_F_GCR_BTLELDODLY_LDORXDLYCNT_POS 8 /**< BTLELDODLY_LDORXDLYCNT Position */ -#define MXC_F_GCR_BTLELDODLY_LDORXDLYCNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLELDODLY_LDORXDLYCNT_POS)) /**< BTLELDODLY_LDORXDLYCNT Mask */ +#define MXC_F_GCR_BTLELDODLY_LDOBBDLYCNT_POS 8 /**< BTLELDODLY_LDOBBDLYCNT Position */ +#define MXC_F_GCR_BTLELDODLY_LDOBBDLYCNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLELDODLY_LDOBBDLYCNT_POS)) /**< BTLELDODLY_LDOBBDLYCNT Mask */ -#define MXC_F_GCR_BTLELDODLY_LDOTXDLYCNT_POS 20 /**< BTLELDODLY_LDOTXDLYCNT Position */ -#define MXC_F_GCR_BTLELDODLY_LDOTXDLYCNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLELDODLY_LDOTXDLYCNT_POS)) /**< BTLELDODLY_LDOTXDLYCNT Mask */ +#define MXC_F_GCR_BTLELDODLY_LDORFDLYCNT_POS 20 /**< BTLELDODLY_LDORFDLYCNT Position */ +#define MXC_F_GCR_BTLELDODLY_LDORFDLYCNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLELDODLY_LDORFDLYCNT_POS)) /**< BTLELDODLY_LDORFDLYCNT Mask */ /**@} end of group GCR_BTLELDODLY_Register */ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32680/Include/max32680.svd b/MAX/Libraries/CMSIS/Device/Maxim/MAX32680/Include/max32680.svd index af2ae925..9ee59137 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32680/Include/max32680.svd +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32680/Include/max32680.svd @@ -3794,36 +3794,36 @@ 0x74 - LDOTXEN - LDOTX Enable. + LDOBBEN + LDOBB Enable. 0 1 - LDOTXPULLD - LDOTX Pull Down. + LDOBBPULLD + LDOBB Pull Down. 1 1 - LDOTXVSEL - LDOTX Voltage Setting. + LDOBBVSEL + LDOBB Voltage Setting. 2 2 - - 0_7 - 0.7V - 0 - 0_85 0.85V - 1 + 0 0_9 0.9V + 1 + + + 1_0 + 1.0V 2 @@ -3834,36 +3834,36 @@ - LDORXEN - LDORX Enable. + LDORFEN + LDORF Enable. 4 1 - LDORXPULLD - LDOrX Pull Down. + LDORFPULLD + LDORF Pull Down. 5 1 - LDORXVSEL - LDORX Voltage Setting. + LDORFVSEL + LDORF Voltage Setting. 6 2 - - 0_7 - 0.7V - 0 - 0_85 0.85V - 1 + 0 0_9 0.9V + 1 + + + 1_0 + 1.0V 2 @@ -3874,50 +3874,50 @@ - LDORXBYP - LDORX Bypass Enable. + LDORFBYP + LDORF Bypass Enable. 8 1 - LDORXDISCH - LDORX Discharge. + LDORFDISCH + LDORF Discharge. 9 1 - LDOTXBYP - LDOTX Bypass Enable. + LDOBBBYP + LDOBB Bypass Enable. 10 1 - LDOTXDISCH - LDOTX Discharge. + LDOBBDISCH + LDOBB Discharge. 11 1 - LDOTXENDLY - LDOTX Enable Delay. + LDOBBENDLY + LDOBB Enable Delay. 12 1 - LDORXENDLY - LDORX Enable Delay. + LDORFENDLY + LDORF Enable Delay. 13 1 - LDORXBYPENENDLY - LDORX Bypass Enable Delay. + LDORFBYPENENDLY + LDORF Bypass Enable Delay. 14 1 - LDOTXBYPENENDLY - LDOTX Bypass Enable Delay. + LDOBBBYPENENDLY + LDOBB Bypass Enable Delay. 15 1 @@ -3935,14 +3935,14 @@ 8 - LDORXDLYCNT - LDORX Delay Count. + LDOBBDLYCNT + LDOBB Delay Count. 8 9 - LDOTXDLYCNT - LDOTX Delay Count. + LDORFDLYCNT + LDOBB Delay Count. 20 9 @@ -9121,16 +9121,16 @@ read-write - TX - TX LDO trim value. - 0 + RF + RF LDO trim value. + 16 5 read-write - RX - RX LDO trim value. - 8 + BB + BB LDO trim value. + 24 5 read-write diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32680/Include/sir_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32680/Include/sir_regs.h index 5f9e6734..4f8c04c2 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32680/Include/sir_regs.h +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32680/Include/sir_regs.h @@ -130,11 +130,11 @@ typedef struct { * @brief BTLE LDO Trim register. * @{ */ -#define MXC_F_SIR_BTLE_LDO_TRIM_TX_POS 0 /**< BTLE_LDO_TRIM_TX Position */ -#define MXC_F_SIR_BTLE_LDO_TRIM_TX ((uint32_t)(0x1FUL << MXC_F_SIR_BTLE_LDO_TRIM_TX_POS)) /**< BTLE_LDO_TRIM_TX Mask */ +#define MXC_F_SIR_BTLE_LDO_TRIM_RF_POS 16 /**< BTLE_LDO_TRIM_RF Position */ +#define MXC_F_SIR_BTLE_LDO_TRIM_RF ((uint32_t)(0x1FUL << MXC_F_SIR_BTLE_LDO_TRIM_RF_POS)) /**< BTLE_LDO_TRIM_RF Mask */ -#define MXC_F_SIR_BTLE_LDO_TRIM_RX_POS 8 /**< BTLE_LDO_TRIM_RX Position */ -#define MXC_F_SIR_BTLE_LDO_TRIM_RX ((uint32_t)(0x1FUL << MXC_F_SIR_BTLE_LDO_TRIM_RX_POS)) /**< BTLE_LDO_TRIM_RX Mask */ +#define MXC_F_SIR_BTLE_LDO_TRIM_BB_POS 24 /**< BTLE_LDO_TRIM_BB Position */ +#define MXC_F_SIR_BTLE_LDO_TRIM_BB ((uint32_t)(0x1FUL << MXC_F_SIR_BTLE_LDO_TRIM_BB_POS)) /**< BTLE_LDO_TRIM_BB Mask */ /**@} end of group SIR_BTLE_LDO_TRIM_Register */ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Include/gcr_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Include/gcr_regs.h index 62aed4af..1ab61adf 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Include/gcr_regs.h +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Include/gcr_regs.h @@ -878,47 +878,63 @@ typedef struct { * @brief BTLE LDO Control Register * @{ */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXEN_POS 0 /**< BTLELDOCTRL_LDOTXEN Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXEN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXEN_POS)) /**< BTLELDOCTRL_LDOTXEN Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBEN_POS 0 /**< BTLELDOCTRL_LDOBBEN Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBEN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOBBEN_POS)) /**< BTLELDOCTRL_LDOBBEN Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXPULLD_POS 1 /**< BTLELDOCTRL_LDOTXPULLD Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXPULLD_POS)) /**< BTLELDOCTRL_LDOTXPULLD Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBPULLD_POS 1 /**< BTLELDOCTRL_LDOBBPULLD Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOBBPULLD_POS)) /**< BTLELDOCTRL_LDOBBPULLD Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS 2 /**< BTLELDOCTRL_LDOTXVSEL Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL_POS)) /**< BTLELDOCTRL_LDOTXVSEL Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL_POS 2 /**< BTLELDOCTRL_LDOBBVSEL Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL_POS)) /**< BTLELDOCTRL_LDOBBVSEL Mask */ +#define MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_0_85 ((uint32_t)0x0UL) /**< BTLELDOCTRL_LDOBBVSEL_0_85 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDOBBVSEL_0_85 (MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_0_85 << MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL_POS) /**< BTLELDOCTRL_LDOBBVSEL_0_85 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_0_9 ((uint32_t)0x1UL) /**< BTLELDOCTRL_LDOBBVSEL_0_9 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDOBBVSEL_0_9 (MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_0_9 << MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL_POS) /**< BTLELDOCTRL_LDOBBVSEL_0_9 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_1_0 ((uint32_t)0x2UL) /**< BTLELDOCTRL_LDOBBVSEL_1_0 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDOBBVSEL_1_0 (MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_1_0 << MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL_POS) /**< BTLELDOCTRL_LDOBBVSEL_1_0 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_1_1 ((uint32_t)0x3UL) /**< BTLELDOCTRL_LDOBBVSEL_1_1 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDOBBVSEL_1_1 (MXC_V_GCR_BTLELDOCTRL_LDOBBVSEL_1_1 << MXC_F_GCR_BTLELDOCTRL_LDOBBVSEL_POS) /**< BTLELDOCTRL_LDOBBVSEL_1_1 Setting */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXEN_POS 4 /**< BTLELDOCTRL_LDORXEN Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXEN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXEN_POS)) /**< BTLELDOCTRL_LDORXEN Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFEN_POS 4 /**< BTLELDOCTRL_LDORFEN Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFEN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORFEN_POS)) /**< BTLELDOCTRL_LDORFEN Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXPULLD_POS 5 /**< BTLELDOCTRL_LDORXPULLD Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXPULLD_POS)) /**< BTLELDOCTRL_LDORXPULLD Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFPULLD_POS 5 /**< BTLELDOCTRL_LDORFPULLD Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFPULLD ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORFPULLD_POS)) /**< BTLELDOCTRL_LDORFPULLD Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS 6 /**< BTLELDOCTRL_LDORXVSEL Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXVSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_LDORXVSEL_POS)) /**< BTLELDOCTRL_LDORXVSEL Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFVSEL_POS 6 /**< BTLELDOCTRL_LDORFVSEL Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFVSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_LDORFVSEL_POS)) /**< BTLELDOCTRL_LDORFVSEL Mask */ +#define MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_0_85 ((uint32_t)0x0UL) /**< BTLELDOCTRL_LDORFVSEL_0_85 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDORFVSEL_0_85 (MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_0_85 << MXC_F_GCR_BTLELDOCTRL_LDORFVSEL_POS) /**< BTLELDOCTRL_LDORFVSEL_0_85 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_0_9 ((uint32_t)0x1UL) /**< BTLELDOCTRL_LDORFVSEL_0_9 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDORFVSEL_0_9 (MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_0_9 << MXC_F_GCR_BTLELDOCTRL_LDORFVSEL_POS) /**< BTLELDOCTRL_LDORFVSEL_0_9 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_1_0 ((uint32_t)0x2UL) /**< BTLELDOCTRL_LDORFVSEL_1_0 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDORFVSEL_1_0 (MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_1_0 << MXC_F_GCR_BTLELDOCTRL_LDORFVSEL_POS) /**< BTLELDOCTRL_LDORFVSEL_1_0 Setting */ +#define MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_1_1 ((uint32_t)0x3UL) /**< BTLELDOCTRL_LDORFVSEL_1_1 Value */ +#define MXC_S_GCR_BTLELDOCTRL_LDORFVSEL_1_1 (MXC_V_GCR_BTLELDOCTRL_LDORFVSEL_1_1 << MXC_F_GCR_BTLELDOCTRL_LDORFVSEL_POS) /**< BTLELDOCTRL_LDORFVSEL_1_1 Setting */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXBYP_POS 8 /**< BTLELDOCTRL_LDORXBYP Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXBYP ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXBYP_POS)) /**< BTLELDOCTRL_LDORXBYP Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFBYP_POS 8 /**< BTLELDOCTRL_LDORFBYP Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFBYP ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORFBYP_POS)) /**< BTLELDOCTRL_LDORFBYP Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXDISCH_POS 9 /**< BTLELDOCTRL_LDORXDISCH Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXDISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXDISCH_POS)) /**< BTLELDOCTRL_LDORXDISCH Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFDISCH_POS 9 /**< BTLELDOCTRL_LDORFDISCH Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFDISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORFDISCH_POS)) /**< BTLELDOCTRL_LDORFDISCH Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXBYP_POS 10 /**< BTLELDOCTRL_LDOTXBYP Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXBYP ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXBYP_POS)) /**< BTLELDOCTRL_LDOTXBYP Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBBYP_POS 10 /**< BTLELDOCTRL_LDOBBBYP Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBBYP ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOBBBYP_POS)) /**< BTLELDOCTRL_LDOBBBYP Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXDISCH_POS 11 /**< BTLELDOCTRL_LDOTXDISCH Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXDISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXDISCH_POS)) /**< BTLELDOCTRL_LDOTXDISCH Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBDISCH_POS 11 /**< BTLELDOCTRL_LDOBBDISCH Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBDISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOBBDISCH_POS)) /**< BTLELDOCTRL_LDOBBDISCH Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXENDLY_POS 12 /**< BTLELDOCTRL_LDOTXENDLY Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXENDLY_POS)) /**< BTLELDOCTRL_LDOTXENDLY Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBENDLY_POS 12 /**< BTLELDOCTRL_LDOBBENDLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOBBENDLY_POS)) /**< BTLELDOCTRL_LDOBBENDLY Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXENDLY_POS 13 /**< BTLELDOCTRL_LDORXENDLY Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXENDLY_POS)) /**< BTLELDOCTRL_LDORXENDLY Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFENDLY_POS 13 /**< BTLELDOCTRL_LDORFENDLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORFENDLY_POS)) /**< BTLELDOCTRL_LDORFENDLY Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXBYPENENDLY_POS 14 /**< BTLELDOCTRL_LDORXBYPENENDLY Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDORXBYPENENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORXBYPENENDLY_POS)) /**< BTLELDOCTRL_LDORXBYPENENDLY Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFBYPENENDLY_POS 14 /**< BTLELDOCTRL_LDORFBYPENENDLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDORFBYPENENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDORFBYPENENDLY_POS)) /**< BTLELDOCTRL_LDORFBYPENENDLY Mask */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXBYPENENDLY_POS 15 /**< BTLELDOCTRL_LDOTXBYPENENDLY Position */ -#define MXC_F_GCR_BTLELDOCTRL_LDOTXBYPENENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOTXBYPENENDLY_POS)) /**< BTLELDOCTRL_LDOTXBYPENENDLY Mask */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBBYPENENDLY_POS 15 /**< BTLELDOCTRL_LDOBBBYPENENDLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_LDOBBBYPENENDLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_LDOBBBYPENENDLY_POS)) /**< BTLELDOCTRL_LDOBBBYPENENDLY Mask */ /**@} end of group GCR_BTLELDOCTRL_Register */ @@ -931,11 +947,11 @@ typedef struct { #define MXC_F_GCR_BTLELDODLY_BYPDLYCNT_POS 0 /**< BTLELDODLY_BYPDLYCNT Position */ #define MXC_F_GCR_BTLELDODLY_BYPDLYCNT ((uint32_t)(0xFFUL << MXC_F_GCR_BTLELDODLY_BYPDLYCNT_POS)) /**< BTLELDODLY_BYPDLYCNT Mask */ -#define MXC_F_GCR_BTLELDODLY_LDOTXDLYCNT_POS 8 /**< BTLELDODLY_LDOTXDLYCNT Position */ -#define MXC_F_GCR_BTLELDODLY_LDOTXDLYCNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLELDODLY_LDOTXDLYCNT_POS)) /**< BTLELDODLY_LDOTXDLYCNT Mask */ +#define MXC_F_GCR_BTLELDODLY_LDORFDLYCNT_POS 8 /**< BTLELDODLY_LDORFDLYCNT Position */ +#define MXC_F_GCR_BTLELDODLY_LDORFDLYCNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLELDODLY_LDORFDLYCNT_POS)) /**< BTLELDODLY_LDORFDLYCNT Mask */ -#define MXC_F_GCR_BTLELDODLY_LDORXDLYCNT_POS 20 /**< BTLELDODLY_LDORXDLYCNT Position */ -#define MXC_F_GCR_BTLELDODLY_LDORXDLYCNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLELDODLY_LDORXDLYCNT_POS)) /**< BTLELDODLY_LDORXDLYCNT Mask */ +#define MXC_F_GCR_BTLELDODLY_LDOBBDLYCNT_POS 20 /**< BTLELDODLY_LDOBBDLYCNT Position */ +#define MXC_F_GCR_BTLELDODLY_LDOBBDLYCNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLELDODLY_LDOBBDLYCNT_POS)) /**< BTLELDODLY_LDOBBDLYCNT Mask */ /**@} end of group GCR_BTLELDODLY_Register */ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Include/max32690.svd b/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Include/max32690.svd index 0846a01a..56af430f 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Include/max32690.svd +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Include/max32690.svd @@ -7334,86 +7334,130 @@ memory. 0x74 - LDOTXEN - LDOTX Enable. + LDOBBEN + LDOBB Enable. 0 1 - LDOTXPULLD - LDOTX Pull Down. + LDOBBPULLD + LDOBB Pull Down. 1 1 - LDOTXVSEL - LDOTX Voltage Setting. + LDOBBVSEL + LDOBB Voltage Setting. 2 2 + + + 0_85 + 0.85V + 0 + + + 0_9 + 0.9V + 1 + + + 1_0 + 1.0V + 2 + + + 1_1 + 1.1V + 3 + + - LDORXEN - LDORX Enable. + LDORFEN + LDORF Enable. 4 1 - LDORXPULLD - LDOrX Pull Down. + LDORFPULLD + LDORF Pull Down. 5 1 - LDORXVSEL - LDORX Voltage Setting. + LDORFVSEL + LDORF Voltage Setting. 6 2 + + + 0_85 + 0.85V + 0 + + + 0_9 + 0.9V + 1 + + + 1_0 + 1.0V + 2 + + + 1_1 + 1.1V + 3 + + - LDORXBYP - LDORX Bypass Enable. + LDORFBYP + LDORF Bypass Enable. 8 1 - LDORXDISCH - LDORX Discharge. + LDORFDISCH + LDORF Discharge. 9 1 - LDOTXBYP - LDOTX Bypass Enable. + LDOBBBYP + LDOBB Bypass Enable. 10 1 - LDOTXDISCH - LDOTX Discharge. + LDOBBDISCH + LDOBB Discharge. 11 1 - LDOTXENDLY - LDOTX Enable Delay. + LDOBBENDLY + LDOBB Enable Delay. 12 1 - LDORXENDLY - LDORX Enable Delay. + LDORFENDLY + LDORF Enable Delay. 13 1 - LDORXBYPENENDLY - LDORX Bypass Enable Delay. + LDORFBYPENENDLY + LDORF Bypass Enable Delay. 14 1 - LDOTXBYPENENDLY - LDOTX Bypass Enable Delay. + LDOBBBYPENENDLY + LDOBB Bypass Enable Delay. 15 1 @@ -7431,14 +7475,14 @@ memory. 8 - LDOTXDLYCNT - LDOTX Delay Count. + LDORFDLYCNT + LDORF Delay Count. 8 9 - LDORXDLYCNT - LDORX Delay Count. + LDOBBDLYCNT + LDOBB Delay Count. 20 9 @@ -13438,7 +13482,8 @@ signal(s) on transition(s) from low to high or high to low when PM.USBWKEN is se MAGIC - Magic Word Validation. This bit is set by the system initialization block following power-up. + Magic Word Validation. This bit is set by the system initialization block + following power-up. 0 1 read-only @@ -13458,7 +13503,8 @@ signal(s) on transition(s) from low to high or high to low when PM.USBWKEN is se CRCERR - CRC Error Status. This bit is set by the system initialization block following power-up. + CRC Error Status. This bit is set by the system initialization block + following power-up. 1 1 read-only @@ -13471,7 +13517,8 @@ signal(s) on transition(s) from low to high or high to low when PM.USBWKEN is se error - A CRC error occurred while reading the OTP. The address of the failure location in the OTP memory is stored in the ERRADDR register. + A CRC error occurred while reading the OTP. The address of the failure + location in the OTP memory is stored in the ERRADDR register. 1 @@ -13480,7 +13527,8 @@ signal(s) on transition(s) from low to high or high to low when PM.USBWKEN is se SIADDR - Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1). + Read-only field set by the SIB block if a CRC error occurs during the read of + the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1). 0x04 read-only @@ -13498,15 +13546,15 @@ signal(s) on transition(s) from low to high or high to low when PM.USBWKEN is se read-write - TX - TX LDO trim value. + RF + RF LDO trim value. 0 5 read-write - RX - RX LDO trim value. + BB + BB LDO trim value. 5 5 read-write diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Include/sir_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Include/sir_regs.h index cb5b357b..d1b5f527 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Include/sir_regs.h +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Include/sir_regs.h @@ -130,11 +130,11 @@ typedef struct { * @brief BTLE LDO Trim register. * @{ */ -#define MXC_F_SIR_BTLE_LDO_TRIM_TX_POS 0 /**< BTLE_LDO_TRIM_TX Position */ -#define MXC_F_SIR_BTLE_LDO_TRIM_TX ((uint32_t)(0x1FUL << MXC_F_SIR_BTLE_LDO_TRIM_TX_POS)) /**< BTLE_LDO_TRIM_TX Mask */ +#define MXC_F_SIR_BTLE_LDO_TRIM_RF_POS 0 /**< BTLE_LDO_TRIM_RF Position */ +#define MXC_F_SIR_BTLE_LDO_TRIM_RF ((uint32_t)(0x1FUL << MXC_F_SIR_BTLE_LDO_TRIM_RF_POS)) /**< BTLE_LDO_TRIM_RF Mask */ -#define MXC_F_SIR_BTLE_LDO_TRIM_RX_POS 5 /**< BTLE_LDO_TRIM_RX Position */ -#define MXC_F_SIR_BTLE_LDO_TRIM_RX ((uint32_t)(0x1FUL << MXC_F_SIR_BTLE_LDO_TRIM_RX_POS)) /**< BTLE_LDO_TRIM_RX Mask */ +#define MXC_F_SIR_BTLE_LDO_TRIM_BB_POS 5 /**< BTLE_LDO_TRIM_BB Position */ +#define MXC_F_SIR_BTLE_LDO_TRIM_BB ((uint32_t)(0x1FUL << MXC_F_SIR_BTLE_LDO_TRIM_BB_POS)) /**< BTLE_LDO_TRIM_BB Mask */ /**@} end of group SIR_BTLE_LDO_TRIM_Register */ diff --git a/MAX/Libraries/PeriphDrivers/Source/AFE/hart_uart.c b/MAX/Libraries/PeriphDrivers/Source/AFE/hart_uart.c index c3ab27eb..b167ab88 100644 --- a/MAX/Libraries/PeriphDrivers/Source/AFE/hart_uart.c +++ b/MAX/Libraries/PeriphDrivers/Source/AFE/hart_uart.c @@ -643,9 +643,9 @@ int hart_clock_enable(void) pPTG->intfl = 0x01; //enable ISO before enabling ERFO - MXC_GCR->btleldoctrl |= (MXC_F_GCR_BTLELDOCTRL_LDOTXEN | MXC_F_GCR_BTLELDOCTRL_LDORXEN | - MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL0 | MXC_F_GCR_BTLELDOCTRL_LDOTXVSEL1 | - MXC_F_GCR_BTLELDOCTRL_LDORXVSEL0 | MXC_F_GCR_BTLELDOCTRL_LDORXVSEL1); + MXC_GCR->btleldoctrl |= + (MXC_F_GCR_BTLELDOCTRL_LDORFEN | MXC_F_GCR_BTLELDOCTRL_LDOBBEN | + MXC_S_GCR_BTLELDOCTRL_LDORFVSEL_0_9 | MXC_S_GCR_BTLELDOCTRL_LDOBBVSEL_0_9); MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_ISO_EN; diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me14.svd b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me14.svd index 018778fd..52a915dc 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me14.svd +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me14.svd @@ -1864,281 +1864,281 @@ BTLE LDO Control Register 0x74 - - LDOTXEN - LDOTX Enable - 0 - 1 - - - dis - disabled. - 0 - - - en - enabled. - 1 - - - - - LDOTXOPULLD - LDOTX PULL Disable - 1 - 1 - - - en - enabled. - 0 - - - dis - disabled. - 1 - - - - - LDOTXVSEL - LDOTX Voltage Setting - 2 - 2 - - - 0_7 - 0.7V - 0 - - - 0_85 - 0.85V - 1 - - - 0_9 - 0.9V - 2 - - - 1_1 - 1.1V - 3 - - - - - LDORXEN - LDORX Enable - 4 - 1 - - - dis - disabled. - 0 - - - en - enabled. - 1 - - - - - LDORXPULLD - LDORX Pulldown - 5 - 1 - - - en - enabled. - 0 - - - dis - disabled. - 1 - - - - - LDORXVSEL - LDORX Output Voltage Setting - 6 - 2 - - - 0_7 - 0.7V - 0 - - - 0_85 - 0.85V - 1 - - - 0_9 - 0.9V - 2 - - - 1_1 - 1.1V - 3 - - - - - LDORXBYP - LDORX Bypass Enable - 8 - 1 - - - dis - disabled. - 0 - - - en - enabled. - 1 - - - - - LDORXDISCH - LDORX Discharge - 9 - 1 - - - dis - disabled. - 0 - - - en - enabled. - 1 - - - - - LDOTXBYP - LDOTX Bypass Enable - 10 - 1 - - - dis - disabled. - 0 - - - en - enabled. - 1 - - - - - LDOTXDISCH - LDOTX Discharge - 11 - 1 - - - dis - disabled. - 0 - - - en - enabled. - 1 - - - - - LDOTXENDLY - LDOTX Enable Delay - 12 - 1 - - - dis - disabled. - 0 - - - en - enabled. - 1 - - - - - LDORXENDLY - LDORX Enable Delay - 13 - 1 - - - dis - disabled. - 0 - - - en - enabled. - 1 - - - - - LDORXBYPENENDLY - LDOTX Bypass Enable Delay - 14 - 1 - - - LDOTXBYPENENDLY - LDORX Bypass Enable Delay - 15 - 1 - + + LDORXEN + LDORX Enable + 0 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + LDORXOPULLD + LDORX PULL Disable + 1 + 1 + + + en + enabled. + 0 + + + dis + disabled. + 1 + + + + + LDORXVSEL + LDORX Voltage Setting + 2 + 2 + + + 0_85 + 0.85V + 0 + + + 0_9 + 0.9V + 1 + + + 1_0 + 1.0V + 2 + + + 1_1 + 1.1V + 3 + + + + + LDOTXEN + LDOTX Enable + 4 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + LDOTXPULLD + LDOTX Pulldown + 5 + 1 + + + en + enabled. + 0 + + + dis + disabled. + 1 + + + + + LDOTXVSEL + LDOTX Output Voltage Setting + 6 + 2 + + + 0_85 + 0.85V + 0 + + + 0_9 + 0.9V + 1 + + + 1_0 + 1.0V + 2 + + + 1_1 + 1.1V + 3 + + + + + LDOTXBYP + LDOTX Bypass Enable + 8 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + LDOTXDISCH + LDOTX Discharge + 9 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + LDORXBYP + LDORX Bypass Enable + 10 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + LDORXDISCH + LDORX Discharge + 11 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + LDORXENDLY + LDORX Enable Delay + 12 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + LDOTXENDLY + LDOTX Enable Delay + 13 + 1 + + + dis + disabled. + 0 + + + en + enabled. + 1 + + + + + LDOTXBYPENENDLY + LDORX Bypass Enable Delay + 14 + 1 + + + LDORXBYPENENDLY + LDOTX Bypass Enable Delay + 15 + 1 + - - + + BTLE_LDODCR BTLE LDO Delay Register 0x78 - - BYPDLYCNT - Bypass Delay Count. Count delay base on PCLK. - 0 - 8 - - - LDORXDLYCNT - LDORX Delay Count. Count delay base on PCLK/128. - 8 - 9 - - - LDOTXDLYCNT - LDOTX Delay Count. Count delay base on PCLK/128. - 20 - 9 - + + BYPDLYCNT + Bypass Delay Count. Count delay base on PCLK. + 0 + 8 + + + LDOTXDLYCNT + LDOTX Delay Count. Count delay base on PCLK/128. + 8 + 9 + + + LDORXDLYCNT + LDORX Delay Count. Count delay base on PCLK/128. + 20 + 9 + - + GP0 General Purpose Register 0 diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me17.svd b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me17.svd index dce8af63..06cc96ff 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me17.svd +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me17.svd @@ -1213,165 +1213,141 @@ - - BTLELDOCTRL - BTLE LDO Control Register - 0x74 - - - LDOTXEN - LDOTX Enable. - 0 - 1 - - - LDOTXPULLD - LDOTX Pull Down. - 1 - 1 - - - LDOTXVSEL - LDOTX Voltage Setting. - 2 - 2 - - - 0_7 - 0.7V - 0 - - - 0_85 - 0.85V - 1 - - - 0_9 - 0.9V - 2 - - - 1_1 - 1.1V - 3 - - - - - LDOTXVSEL0 - LDOTX Voltage Setting. - 2 - 1 - - - LDOTXVSEL1 - LDOTX Voltage Setting. - 3 - 1 - - - LDORXEN - LDORX Enable. - 4 - 1 - - - LDORXPULLD - LDOrX Pull Down. - 5 - 1 - - - LDORXVSEL - LDORX Voltage Setting. - 6 - 2 - - - 0_7 - 0.7V - 0 - - - 0_85 - 0.85V - 1 - - - 0_9 - 0.9V - 2 - - - 1_1 - 1.1V - 3 - - - - - LDORXVSEL0 - LDORX Voltage Setting. - 6 - 1 - - - LDORXVSEL1 - LDORX Voltage Setting. - 7 - 1 - - - LDORXBYP - LDORX Bypass Enable. - 8 - 1 - - - LDORXDISCH - LDORX Discharge. - 9 - 1 - - - LDOTXBYP - LDOTX Bypass Enable. - 10 - 1 - - - LDOTXDISCH - LDOTX Discharge. - 11 - 1 - - - LDOTXENDLY - LDOTX Enable Delay. - 12 - 1 - - - LDORXENDLY - LDORX Enable Delay. - 13 - 1 - - - LDORXBYPENENDLY - LDORX Bypass Enable Delay. - 14 - 1 - - - LDOTXBYPENENDLY - LDOTX Bypass Enable Delay. - 15 - 1 - - - + + BTLELDOCTRL + BTLE LDO Control Register + 0x74 + + + LDOBBEN + LDOBB Enable. + 0 + 1 + + + LDOBBPULLD + LDOBB Pull Down. + 1 + 1 + + + LDOBBVSEL + LDOBB Voltage Setting. + 2 + 2 + + + 0_85 + 0.85V + 0 + + + 0_9 + 0.9V + 1 + + + 1_0 + 1.0V + 2 + + + 1_1 + 1.1V + 3 + + + + + LDORFEN + LDORF Enable. + 4 + 1 + + + LDORFPULLD + LDORF Pull Down. + 5 + 1 + + + LDORFVSEL + LDORF Voltage Setting. + 6 + 2 + + + 0_85 + 0.85V + 0 + + + 0_9 + 0.9V + 1 + + + 1_0 + 1.0V + 2 + + + 1_1 + 1.1V + 3 + + + + + LDORFBYP + LDORF Bypass Enable. + 8 + 1 + + + LDORFDISCH + LDORF Discharge. + 9 + 1 + + + LDOBBBYP + LDOBB Bypass Enable. + 10 + 1 + + + LDOBBDISCH + LDOBB Discharge. + 11 + 1 + + + LDOBBENDLY + LDOBB Enable Delay. + 12 + 1 + + + LDORFENDLY + LDORF Enable Delay. + 13 + 1 + + + LDORFBYPENENDLY + LDORF Bypass Enable Delay. + 14 + 1 + + + LDOBBBYPENENDLY + LDOBB Bypass Enable Delay. + 15 + 1 + + + BTLELDODLY BTLE LDO Delay Register @@ -1384,14 +1360,14 @@ 8 - LDORXDLYCNT - LDORX Delay Count. + LDOBBDLYCNT + LDOBB Delay Count. 8 9 - LDOTXDLYCNT - LDOTX Delay Count. + LDORFDLYCNT + LDOBB Delay Count. 20 9 diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me18.svd b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me18.svd index f0389422..9d79a039 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me18.svd +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me18.svd @@ -1596,117 +1596,161 @@ BTLE LDO Control Register 0x74 - - LDOTXEN - LDOTX Enable. - 0 - 1 - - - LDOTXPULLD - LDOTX Pull Down. - 1 - 1 - - - LDOTXVSEL - LDOTX Voltage Setting. - 2 - 2 - - - LDORXEN - LDORX Enable. - 4 - 1 - - - LDORXPULLD - LDOrX Pull Down. - 5 - 1 - - - LDORXVSEL - LDORX Voltage Setting. - 6 - 2 - - - LDORXBYP - LDORX Bypass Enable. - 8 - 1 - - - LDORXDISCH - LDORX Discharge. - 9 - 1 - - - LDOTXBYP - LDOTX Bypass Enable. - 10 - 1 - - - LDOTXDISCH - LDOTX Discharge. - 11 - 1 - - - LDOTXENDLY - LDOTX Enable Delay. - 12 - 1 - - - LDORXENDLY - LDORX Enable Delay. - 13 - 1 - - - LDORXBYPENENDLY - LDORX Bypass Enable Delay. - 14 - 1 - - - LDOTXBYPENENDLY - LDOTX Bypass Enable Delay. - 15 - 1 - + + LDOBBEN + LDOBB Enable. + 0 + 1 + + + LDOBBPULLD + LDOBB Pull Down. + 1 + 1 + + + LDOBBVSEL + LDOBB Voltage Setting. + 2 + 2 + + + 0_85 + 0.85V + 0 + + + 0_9 + 0.9V + 1 + + + 1_0 + 1.0V + 2 + + + 1_1 + 1.1V + 3 + + + + + LDORFEN + LDORF Enable. + 4 + 1 + + + LDORFPULLD + LDORF Pull Down. + 5 + 1 + + + LDORFVSEL + LDORF Voltage Setting. + 6 + 2 + + + 0_85 + 0.85V + 0 + + + 0_9 + 0.9V + 1 + + + 1_0 + 1.0V + 2 + + + 1_1 + 1.1V + 3 + + + + + LDORFBYP + LDORF Bypass Enable. + 8 + 1 + + + LDORFDISCH + LDORF Discharge. + 9 + 1 + + + LDOBBBYP + LDOBB Bypass Enable. + 10 + 1 + + + LDOBBDISCH + LDOBB Discharge. + 11 + 1 + + + LDOBBENDLY + LDOBB Enable Delay. + 12 + 1 + + + LDORFENDLY + LDORF Enable Delay. + 13 + 1 + + + LDORFBYPENENDLY + LDORF Bypass Enable Delay. + 14 + 1 + + + LDOBBBYPENENDLY + LDOBB Bypass Enable Delay. + 15 + 1 + - - + + BTLELDODLY BTLE LDO Delay Register 0x78 - - BYPDLYCNT - Bypass Delay Count. - 0 - 8 - - - LDOTXDLYCNT - LDOTX Delay Count. - 8 - 9 - - - LDORXDLYCNT - LDORX Delay Count. - 20 - 9 - + + BYPDLYCNT + Bypass Delay Count. + 0 + 8 + + + LDORFDLYCNT + LDORF Delay Count. + 8 + 9 + + + LDOBBDLYCNT + LDOBB Delay Count. + 20 + 9 + - + GPR0 General Purpose Register 0 diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me14.svd b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me14.svd index 33037b35..ee57622c 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me14.svd +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me14.svd @@ -1,5 +1,6 @@ - + SIR System Initialization Registers. @@ -19,7 +20,8 @@ MAGIC - Magic Word Validation. This bit is set by the system initialization block following power-up. + Magic Word Validation. This bit is set by the system initialization block + following power-up. 0 1 read-only @@ -39,7 +41,8 @@ CRCERR - CRC Error Status. This bit is set by the system initialization block following power-up. + CRC Error Status. This bit is set by the system initialization block + following power-up. 1 1 read-only @@ -52,7 +55,8 @@ error - A CRC error occurred while reading the OTP. The address of the failure location in the OTP memory is stored in the ERRADDR register. + A CRC error occurred while reading the OTP. The address of the failure + location in the OTP memory is stored in the ERRADDR register. 1 @@ -61,7 +65,8 @@ ERRADDR - Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1). + Read-only field set by the SIB block if a CRC error occurs during the read of + the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1). 0x04 read-only @@ -72,6 +77,40 @@ + + + + BTLE_LDO_TRIM_TX + BTLE LDO TX Trim register. + 0x54 + read-write + + + TX + TX LDO trim value. + 0 + 5 + read-write + + + + + + BTLE_LDO_TRIM_RX + BTLE LDO RX Trim register. + 0x5C + read-write + + + RX + RX LDO trim value. + 0 + 5 + read-write + + + + FSTAT funcstat register. diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me17.svd b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me17.svd index a3b401cd..e84b7101 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me17.svd +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me17.svd @@ -72,28 +72,28 @@ - - BTLE_LDO_TRIM - BTLE LDO Trim register. - 0x48 - read-write - - - TX - TX LDO trim value. - 0 - 5 - read-write - - - RX - RX LDO trim value. - 8 - 5 - read-write - - - + + BTLE_LDO_TRIM + BTLE LDO Trim register. + 0x48 + read-write + + + RF + RF LDO trim value. + 16 + 5 + read-write + + + BB + BB LDO trim value. + 24 + 5 + read-write + + + FSTAT funcstat register. diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me18.svd b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me18.svd index 6174cb8c..da911131 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me18.svd +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me18.svd @@ -1,5 +1,6 @@  - + SIR System Initialization Registers. @@ -19,7 +20,8 @@ MAGIC - Magic Word Validation. This bit is set by the system initialization block following power-up. + Magic Word Validation. This bit is set by the system initialization block + following power-up. 0 1 read-only @@ -39,7 +41,8 @@ CRCERR - CRC Error Status. This bit is set by the system initialization block following power-up. + CRC Error Status. This bit is set by the system initialization block + following power-up. 1 1 read-only @@ -52,7 +55,8 @@ error - A CRC error occurred while reading the OTP. The address of the failure location in the OTP memory is stored in the ERRADDR register. + A CRC error occurred while reading the OTP. The address of the failure + location in the OTP memory is stored in the ERRADDR register. 1 @@ -61,7 +65,8 @@ SIADDR - Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1). + Read-only field set by the SIB block if a CRC error occurs during the read of + the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1). 0x04 read-only @@ -79,15 +84,15 @@ read-write - TX - TX LDO trim value. + RF + RF LDO trim value. 0 5 read-write - RX - RX LDO trim value. + BB + BB LDO trim value. 5 5 read-write diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me17.c b/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me17.c index cb9ad432..ff2d5c92 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me17.c +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me17.c @@ -248,7 +248,7 @@ int MXC_SYS_ClockSourceEnable(mxc_sys_system_clock_t clock) break; case MXC_SYS_CLOCK_ERFO: - MXC_GCR->btleldoctrl |= MXC_F_GCR_BTLELDOCTRL_LDOTXEN | MXC_F_GCR_BTLELDOCTRL_LDORXEN; + MXC_GCR->btleldoctrl |= MXC_F_GCR_BTLELDOCTRL_LDORFEN | MXC_F_GCR_BTLELDOCTRL_LDOBBEN; /* Initialize kickstart circuit Select Kick start circuit clock source- IPO/ISO diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me18.c b/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me18.c index 40a48497..79aa5c17 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me18.c +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me18.c @@ -255,7 +255,7 @@ int MXC_SYS_ClockSourceEnable(mxc_sys_system_clock_t clock) break; case MXC_SYS_CLOCK_ERFO: - MXC_GCR->btleldoctrl |= MXC_F_GCR_BTLELDOCTRL_LDOTXEN | MXC_F_GCR_BTLELDOCTRL_LDORXEN; + MXC_GCR->btleldoctrl |= MXC_F_GCR_BTLELDOCTRL_LDORFEN | MXC_F_GCR_BTLELDOCTRL_LDOBBEN; MXC_GCR->clkctrl |= MXC_F_GCR_CLKCTRL_ERFO_EN; return MXC_SYS_Clock_Timeout(MXC_F_GCR_CLKCTRL_ERFO_RDY); diff --git a/MAX/msdk_sha b/MAX/msdk_sha index 8e70396a..cb10793f 100644 --- a/MAX/msdk_sha +++ b/MAX/msdk_sha @@ -1 +1 @@ -fb3ae96e021ca2bd195408e1ee0e88f1057e2119 +51ec9ada64735befc5cdc4dac00bbc2f32baf031