diff --git a/MAX/Include/wrap_max32_dma.h b/MAX/Include/wrap_max32_dma.h index fe228dc3..23830507 100644 --- a/MAX/Include/wrap_max32_dma.h +++ b/MAX/Include/wrap_max32_dma.h @@ -26,7 +26,11 @@ extern "C" { #endif +/* + * MAX32665, MAX32666 related mapping + */ #if defined(CONFIG_SOC_MAX32665) || (CONFIG_SOC_MAX32666) + #define ADI_MAX32_DMA_CTRL_DIS_IE MXC_F_DMA_CFG_CHDIEN #define ADI_MAX32_DMA_CTRL_CTZIEN MXC_F_DMA_CFG_CTZIEN @@ -36,7 +40,52 @@ extern "C" { #define ADI_MAX32_DMA_STATUS_ST MXC_F_DMA_ST_CH_ST #define ADI_MAX32_DMA_CFG_REQ_POS MXC_F_DMA_CFG_REQSEL_POS -#else + +static inline int MXC_DMA_GetIntFlags(mxc_dma_regs_t *dma) +{ + return dma->intr; +} + +static inline int Wrap_MXC_DMA_Init(mxc_dma_regs_t *dma) +{ + return MXC_DMA_Init(dma); +} + +static inline void Wrap_MXC_DMA_DeInit(mxc_dma_regs_t *dma) +{ + MXC_DMA_DeInit(dma); +} + +static inline int Wrap_MXC_DMA_AcquireChannel(mxc_dma_regs_t *dma) +{ + return MXC_DMA_AcquireChannel(dma); +} + +static inline void Wrap_MXC_DMA_Handler(mxc_dma_regs_t *dma) +{ + MXC_DMA_Handler(dma); +} + +static inline int Wrap_MXC_DMA_MemCpy(mxc_dma_regs_t *dma, void *dest, void *src, int len, + mxc_dma_complete_cb_t callback) +{ + return MXC_DMA_MemCpy(dma, dest, src, len, callback); +} + +static inline int Wrap_MXC_DMA_DoTransfer(mxc_dma_regs_t *dma, mxc_dma_config_t config, + mxc_dma_srcdst_t firstSrcDst, + mxc_dma_trans_chain_t callback) +{ + return MXC_DMA_DoTransfer(dma, config, firstSrcDst, callback); +} + +/* + * MAX32690, MAX32655 related mapping + */ +#elif defined(CONFIG_SOC_MAX32690) || (CONFIG_SOC_MAX32655) || (CONFIG_SOC_MAX32670) || \ + (CONFIG_SOC_MAX32672) || (CONFIG_SOC_MAX32662) || (CONFIG_SOC_MAX32675) || \ + (CONFIG_SOC_MAX32680) || (CONFIG_SOC_MAX32657) + #define ADI_MAX32_DMA_CTRL_DIS_IE MXC_F_DMA_CTRL_DIS_IE #define ADI_MAX32_DMA_CTRL_CTZIEN MXC_F_DMA_CTRL_CTZ_IE @@ -46,89 +95,52 @@ extern "C" { #define ADI_MAX32_DMA_STATUS_ST MXC_F_DMA_STATUS_STATUS #define ADI_MAX32_DMA_CFG_REQ_POS MXC_F_DMA_CTRL_REQUEST_POS -#endif static inline int MXC_DMA_GetIntFlags(mxc_dma_regs_t *dma) { -#if defined(CONFIG_SOC_MAX32665) || (CONFIG_SOC_MAX32666) - return dma->intr; -#else return dma->intfl; -#endif } static inline int Wrap_MXC_DMA_Init(mxc_dma_regs_t *dma) { -#if defined(CONFIG_SOC_MAX32657) || (CONFIG_SOC_MAX32665) || (CONFIG_SOC_MAX32666) - return MXC_DMA_Init(dma); -#else (void)dma; return MXC_DMA_Init(); -#endif } static inline void Wrap_MXC_DMA_DeInit(mxc_dma_regs_t *dma) { -#if defined(CONFIG_SOC_MAX32657) || (CONFIG_SOC_MAX32665) || (CONFIG_SOC_MAX32666) - MXC_DMA_DeInit(dma); -#else (void)dma; MXC_DMA_DeInit(); -#endif } static inline int Wrap_MXC_DMA_AcquireChannel(mxc_dma_regs_t *dma) { -#if defined(CONFIG_SOC_MAX32657) || (CONFIG_SOC_MAX32665) || (CONFIG_SOC_MAX32666) - return MXC_DMA_AcquireChannel(dma); -#else (void)dma; return MXC_DMA_AcquireChannel(); -#endif } static inline void Wrap_MXC_DMA_Handler(mxc_dma_regs_t *dma) { -#if defined(CONFIG_SOC_MAX32657) || (CONFIG_SOC_MAX32665) || (CONFIG_SOC_MAX32666) - MXC_DMA_Handler(dma); -#else (void)dma; MXC_DMA_Handler(); -#endif } static inline int Wrap_MXC_DMA_MemCpy(mxc_dma_regs_t *dma, void *dest, void *src, int len, mxc_dma_complete_cb_t callback) { -#if defined(CONFIG_SOC_MAX32657) || (CONFIG_SOC_MAX32665) || (CONFIG_SOC_MAX32666) - return MXC_DMA_MemCpy(dma, dest, src, len, callback); -#else (void)dma; return MXC_DMA_MemCpy(dest, src, len, callback); -#endif } static inline int Wrap_MXC_DMA_DoTransfer(mxc_dma_regs_t *dma, mxc_dma_config_t config, mxc_dma_srcdst_t firstSrcDst, mxc_dma_trans_chain_t callback) { -#if defined(CONFIG_SOC_MAX32657) || (CONFIG_SOC_MAX32665) || (CONFIG_SOC_MAX32666) - return MXC_DMA_DoTransfer(dma, config, firstSrcDst, callback); -#else (void)dma; return MXC_DMA_DoTransfer(config, firstSrcDst, callback); -#endif } -static inline int Wrap_MXC_DMA_EnableInt(mxc_dma_regs_t *dma, int ch) -{ -#if defined(CONFIG_SOC_MAX32657) - return MXC_DMA_EnableInt(dma, ch); -#else - (void)dma; - return MXC_DMA_EnableInt(ch); -#endif -} +#endif // part number #ifdef __cplusplus } diff --git a/MAX/Include/wrap_max32_uart.h b/MAX/Include/wrap_max32_uart.h index dd690756..24882a61 100644 --- a/MAX/Include/wrap_max32_uart.h +++ b/MAX/Include/wrap_max32_uart.h @@ -133,7 +133,11 @@ static inline void Wrap_MXC_UART_DisableRxDMA(mxc_uart_regs_t *uart) #define ADI_MAX32_UART_INT_OE MXC_F_UART_INTEN_RX_OV // Overrun Error Interrupt #define ADI_MAX32_UART_INT_PE MXC_F_UART_INTEN_RX_PAR // Parity Error Interrupt #define ADI_MAX32_UART_INT_FE MXC_F_UART_INTEN_RX_FERR // Framing Error Interrupt +#if defined(CONFIG_SOC_MAX32657) +#define ADI_MAX32_UART_INT_TX MXC_F_UART_INTEN_TX_THD // Transmit Interrupt +#else #define ADI_MAX32_UART_INT_TX MXC_F_UART_INTEN_TX_HE // Transmit Interrupt +#endif #define ADI_MAX32_UART_INT_RX MXC_F_UART_INTEN_RX_THD // Receive Interrupt #define ADI_MAX32_UART_INT_CTS MXC_F_UART_INTEN_CTS_EV // CTS Modem Interrupt #define ADI_MAX32_UART_INT_TX_OEM MXC_F_UART_INTEN_TX_OB // TX FIFO Almost Empty Interrupt @@ -213,15 +217,6 @@ static inline void Wrap_MXC_UART_DisableRxDMA(mxc_uart_regs_t *uart) #endif // defined(CONFIG_SOC_MAX32690) || (CONFIG_SOC_MAX32655) -static inline unsigned int Wrap_MXC_UART_GetRegINTEN(mxc_uart_regs_t *uart) -{ -#if defined(CONFIG_SOC_MAX32662) - return uart->inten; -#else - return uart->int_en; -#endif -} - #ifdef __cplusplus } #endif diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32520/Source/sla_header_MAX32520.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32520/Source/header_MAX32520.c similarity index 100% rename from MAX/Libraries/CMSIS/Device/Maxim/MAX32520/Source/sla_header_MAX32520.c rename to MAX/Libraries/CMSIS/Device/Maxim/MAX32520/Source/header_MAX32520.c diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32520/Source/system_max32520.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32520/Source/system_max32520.c index 4f98ee0c..4fdbbe9b 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32520/Source/system_max32520.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32520/Source/system_max32520.c @@ -39,12 +39,12 @@ The libc implementation from GCC 11+ depends on _getpid and _kill in some places There is no concept of processes/PIDs in the baremetal PeriphDrivers, therefore we implement stub functions that return an error code to resolve linker warnings. */ -__weak int _getpid(void) +int _getpid(void) { return E_NOT_SUPPORTED; } -__weak int _kill(void) +int _kill(void) { return E_NOT_SUPPORTED; } diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32570/Source/sla_header_MAX32570.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32570/Source/header_MAX32570.c similarity index 100% rename from MAX/Libraries/CMSIS/Device/Maxim/MAX32570/Source/sla_header_MAX32570.c rename to MAX/Libraries/CMSIS/Device/Maxim/MAX32570/Source/header_MAX32570.c diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32570/Source/system_max32570.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32570/Source/system_max32570.c index d437a2f9..8c0fc6d1 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32570/Source/system_max32570.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32570/Source/system_max32570.c @@ -36,12 +36,12 @@ The libc implementation from GCC 11+ depends on _getpid and _kill in some places There is no concept of processes/PIDs in the baremetal PeriphDrivers, therefore we implement stub functions that return an error code to resolve linker warnings. */ -__weak int _getpid(void) +int _getpid(void) { return E_NOT_SUPPORTED; } -__weak int _kill(void) +int _kill(void) { return E_NOT_SUPPORTED; } diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32572/Source/sla_header_MAX32572.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32572/Source/header_MAX32572.c similarity index 100% rename from MAX/Libraries/CMSIS/Device/Maxim/MAX32572/Source/sla_header_MAX32572.c rename to MAX/Libraries/CMSIS/Device/Maxim/MAX32572/Source/header_MAX32572.c diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32572/Source/system_max32572.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32572/Source/system_max32572.c index c14d69d1..13d09951 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32572/Source/system_max32572.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32572/Source/system_max32572.c @@ -36,12 +36,12 @@ The libc implementation from GCC 11+ depends on _getpid and _kill in some places There is no concept of processes/PIDs in the baremetal PeriphDrivers, therefore we implement stub functions that return an error code to resolve linker warnings. */ -__weak int _getpid(void) +int _getpid(void) { return E_NOT_SUPPORTED; } -__weak int _kill(void) +int _kill(void) { return E_NOT_SUPPORTED; } diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32572/Source/system_riscv_max32572.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32572/Source/system_riscv_max32572.c index 6d51ac0a..b922ac0d 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32572/Source/system_riscv_max32572.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32572/Source/system_riscv_max32572.c @@ -33,12 +33,12 @@ The libc implementation from GCC 11+ depends on _getpid and _kill in some places There is no concept of processes/PIDs in the baremetal PeriphDrivers, therefore we implement stub functions that return an error code to resolve linker warnings. */ -__weak int _getpid(void) +int _getpid(void) { return E_NOT_SUPPORTED; } -__weak int _kill(void) +int _kill(void) { return E_NOT_SUPPORTED; } diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32650/Source/sla_header_MAX32650.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32650/Source/header_MAX32650.c similarity index 100% rename from MAX/Libraries/CMSIS/Device/Maxim/MAX32650/Source/sla_header_MAX32650.c rename to MAX/Libraries/CMSIS/Device/Maxim/MAX32650/Source/header_MAX32650.c diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32650/Source/system_max32650.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32650/Source/system_max32650.c index 0cb9e419..567c6ca1 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32650/Source/system_max32650.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32650/Source/system_max32650.c @@ -38,12 +38,12 @@ The libc implementation from GCC 11+ depends on _getpid and _kill in some places There is no concept of processes/PIDs in the baremetal PeriphDrivers, therefore we implement stub functions that return an error code to resolve linker warnings. */ -__weak int _getpid(void) +int _getpid(void) { return E_NOT_SUPPORTED; } -__weak int _kill(void) +int _kill(void) { return E_NOT_SUPPORTED; } diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Source/system_max32655.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Source/system_max32655.c index c735e55d..d269e39c 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Source/system_max32655.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Source/system_max32655.c @@ -37,12 +37,12 @@ The libc implementation from GCC 11+ depends on _getpid and _kill in some places There is no concept of processes/PIDs in the baremetal PeriphDrivers, therefore we implement stub functions that return an error code to resolve linker warnings. */ -__weak int _getpid(void) +int _getpid(void) { return E_NOT_SUPPORTED; } -__weak int _kill(void) +int _kill(void) { return E_NOT_SUPPORTED; } diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Source/system_riscv_max32655.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Source/system_riscv_max32655.c index c9d37353..58f4f77d 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Source/system_riscv_max32655.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32655/Source/system_riscv_max32655.c @@ -38,12 +38,12 @@ The libc implementation from GCC 11+ depends on _getpid and _kill in some places There is no concept of processes/PIDs in the baremetal PeriphDrivers, therefore we implement stub functions that return an error code to resolve linker warnings. */ -__weak int _getpid(void) +int _getpid(void) { return E_NOT_SUPPORTED; } -__weak int _kill(void) +int _kill(void) { return E_NOT_SUPPORTED; } diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/crc_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/crc_regs.h index 1cbe04b2..8f2430af 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/crc_regs.h +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/crc_regs.h @@ -78,7 +78,6 @@ typedef struct { __IO uint16_t datain16; /**< \b 0x0004: CRC DATAIN16 Register */ __IO uint8_t datain8; /**< \b 0x0004: CRC DATAIN8 Register */ }; - __R uint8_t rsv_0x5_0x7[3]; __IO uint32_t poly; /**< \b 0x0008: CRC POLY Register */ __IO uint32_t val; /**< \b 0x000C: CRC VAL Register */ } mxc_crc_regs_t; diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h index 01f4cd18..c0217beb 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/fcr_regs.h @@ -100,11 +100,11 @@ typedef struct { * @brief Register 0. * @{ */ -#define MXC_F_FCR_FCTRL0_BTLELDO_TX_POS 0 /**< FCTRL0_BTLELDO_TX Position */ -#define MXC_F_FCR_FCTRL0_BTLELDO_TX ((uint32_t)(0x1FUL << MXC_F_FCR_FCTRL0_BTLELDO_TX_POS)) /**< FCTRL0_BTLELDO_TX Mask */ +#define MXC_F_FCR_FCTRL0_BTLELDO_RF_POS 0 /**< FCTRL0_BTLELDO_RF Position */ +#define MXC_F_FCR_FCTRL0_BTLELDO_RF ((uint32_t)(0x1FUL << MXC_F_FCR_FCTRL0_BTLELDO_RF_POS)) /**< FCTRL0_BTLELDO_RF Mask */ -#define MXC_F_FCR_FCTRL0_BTLELDO_RX_POS 8 /**< FCTRL0_BTLELDO_RX Position */ -#define MXC_F_FCR_FCTRL0_BTLELDO_RX ((uint32_t)(0x1FUL << MXC_F_FCR_FCTRL0_BTLELDO_RX_POS)) /**< FCTRL0_BTLELDO_RX Mask */ +#define MXC_F_FCR_FCTRL0_BTLELDO_BB_POS 8 /**< FCTRL0_BTLELDO_BB Position */ +#define MXC_F_FCR_FCTRL0_BTLELDO_BB ((uint32_t)(0x1FUL << MXC_F_FCR_FCTRL0_BTLELDO_BB_POS)) /**< FCTRL0_BTLELDO_BB Mask */ #define MXC_F_FCR_FCTRL0_I3CDGEN0_POS 20 /**< FCTRL0_I3CDGEN0 Position */ #define MXC_F_FCR_FCTRL0_I3CDGEN0 ((uint32_t)(0x1UL << MXC_F_FCR_FCTRL0_I3CDGEN0_POS)) /**< FCTRL0_I3CDGEN0 Mask */ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h index 817963f7..ffa74940 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/gcr_regs.h @@ -91,7 +91,7 @@ typedef struct { __IO uint32_t sysinten; /**< \b 0x54: GCR SYSINTEN Register */ __R uint32_t rsv_0x58_0x63[3]; __IO uint32_t eccerr; /**< \b 0x64: GCR ECCERR Register */ - __R uint32_t rsv_0x68; + __IO uint32_t eccced; /**< \b 0x68: GCR ECCCED Register */ __IO uint32_t eccinten; /**< \b 0x6C: GCR ECCINTEN Register */ __IO uint32_t eccaddr; /**< \b 0x70: GCR ECCADDR Register */ __IO uint32_t btleldoctrl; /**< \b 0x74: GCR BTLELDOCTRL Register */ @@ -120,6 +120,7 @@ typedef struct { #define MXC_R_GCR_REVISION ((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: 0x0050 */ #define MXC_R_GCR_SYSINTEN ((uint32_t)0x00000054UL) /**< Offset from GCR Base Address: 0x0054 */ #define MXC_R_GCR_ECCERR ((uint32_t)0x00000064UL) /**< Offset from GCR Base Address: 0x0064 */ +#define MXC_R_GCR_ECCCED ((uint32_t)0x00000068UL) /**< Offset from GCR Base Address: 0x0068 */ #define MXC_R_GCR_ECCINTEN ((uint32_t)0x0000006CUL) /**< Offset from GCR Base Address: 0x006C */ #define MXC_R_GCR_ECCADDR ((uint32_t)0x00000070UL) /**< Offset from GCR Base Address: 0x0070 */ #define MXC_R_GCR_BTLELDOCTRL ((uint32_t)0x00000074UL) /**< Offset from GCR Base Address: 0x0074 */ @@ -427,6 +428,9 @@ typedef struct { #define MXC_F_GCR_RST1_AES_POS 10 /**< RST1_AES Position */ #define MXC_F_GCR_RST1_AES ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AES_POS)) /**< RST1_AES Mask */ +#define MXC_F_GCR_RST1_AUTOCAL_POS 12 /**< RST1_AUTOCAL Position */ +#define MXC_F_GCR_RST1_AUTOCAL ((uint32_t)(0x1UL << MXC_F_GCR_RST1_AUTOCAL_POS)) /**< RST1_AUTOCAL Mask */ + /**@} end of group GCR_RST1_Register */ /** @@ -444,9 +448,6 @@ typedef struct { #define MXC_F_GCR_PCLKDIS1_AES_POS 15 /**< PCLKDIS1_AES Position */ #define MXC_F_GCR_PCLKDIS1_AES ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_AES_POS)) /**< PCLKDIS1_AES Mask */ -#define MXC_F_GCR_PCLKDIS1_SPI_POS 16 /**< PCLKDIS1_SPI Position */ -#define MXC_F_GCR_PCLKDIS1_SPI ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_SPI_POS)) /**< PCLKDIS1_SPI Mask */ - #define MXC_F_GCR_PCLKDIS1_DMA1_POS 21 /**< PCLKDIS1_DMA1 Position */ #define MXC_F_GCR_PCLKDIS1_DMA1 ((uint32_t)(0x1UL << MXC_F_GCR_PCLKDIS1_DMA1_POS)) /**< PCLKDIS1_DMA1 Mask */ @@ -505,13 +506,24 @@ typedef struct { /**@} end of group GCR_ECCERR_Register */ +/** + * @ingroup gcr_registers + * @defgroup GCR_ECCCED GCR_ECCCED + * @brief ECC Correctable Error Detect Register. + * @{ + */ +#define MXC_F_GCR_ECCCED_FLASH_POS 0 /**< ECCCED_FLASH Position */ +#define MXC_F_GCR_ECCCED_FLASH ((uint32_t)(0x1UL << MXC_F_GCR_ECCCED_FLASH_POS)) /**< ECCCED_FLASH Mask */ + +/**@} end of group GCR_ECCCED_Register */ + /** * @ingroup gcr_registers * @defgroup GCR_ECCINTEN GCR_ECCINTEN * @brief ECC Interrupt Enable Register * @{ */ -#define MXC_F_GCR_ECCINTEN_FLASH_POS 11 /**< ECCINTEN_FLASH Position */ +#define MXC_F_GCR_ECCINTEN_FLASH_POS 0 /**< ECCINTEN_FLASH Position */ #define MXC_F_GCR_ECCINTEN_FLASH ((uint32_t)(0x1UL << MXC_F_GCR_ECCINTEN_FLASH_POS)) /**< ECCINTEN_FLASH Mask */ /**@} end of group GCR_ECCINTEN_Register */ @@ -548,47 +560,47 @@ typedef struct { * @brief BTLE LDO Control Register * @{ */ -#define MXC_F_GCR_BTLELDOCTRL_TX_EN_POS 0 /**< BTLELDOCTRL_TX_EN Position */ -#define MXC_F_GCR_BTLELDOCTRL_TX_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_TX_EN_POS)) /**< BTLELDOCTRL_TX_EN Mask */ +#define MXC_F_GCR_BTLELDOCTRL_RF_EN_POS 0 /**< BTLELDOCTRL_RF_EN Position */ +#define MXC_F_GCR_BTLELDOCTRL_RF_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_EN_POS)) /**< BTLELDOCTRL_RF_EN Mask */ -#define MXC_F_GCR_BTLELDOCTRL_TX_PD_EN_POS 1 /**< BTLELDOCTRL_TX_PD_EN Position */ -#define MXC_F_GCR_BTLELDOCTRL_TX_PD_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_TX_PD_EN_POS)) /**< BTLELDOCTRL_TX_PD_EN Mask */ +#define MXC_F_GCR_BTLELDOCTRL_RF_PD_EN_POS 1 /**< BTLELDOCTRL_RF_PD_EN Position */ +#define MXC_F_GCR_BTLELDOCTRL_RF_PD_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_PD_EN_POS)) /**< BTLELDOCTRL_RF_PD_EN Mask */ -#define MXC_F_GCR_BTLELDOCTRL_TX_VSEL_POS 2 /**< BTLELDOCTRL_TX_VSEL Position */ -#define MXC_F_GCR_BTLELDOCTRL_TX_VSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_TX_VSEL_POS)) /**< BTLELDOCTRL_TX_VSEL Mask */ +#define MXC_F_GCR_BTLELDOCTRL_RF_VSEL_POS 2 /**< BTLELDOCTRL_RF_VSEL Position */ +#define MXC_F_GCR_BTLELDOCTRL_RF_VSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_RF_VSEL_POS)) /**< BTLELDOCTRL_RF_VSEL Mask */ -#define MXC_F_GCR_BTLELDOCTRL_RX_EN_POS 4 /**< BTLELDOCTRL_RX_EN Position */ -#define MXC_F_GCR_BTLELDOCTRL_RX_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RX_EN_POS)) /**< BTLELDOCTRL_RX_EN Mask */ +#define MXC_F_GCR_BTLELDOCTRL_BB_EN_POS 4 /**< BTLELDOCTRL_BB_EN Position */ +#define MXC_F_GCR_BTLELDOCTRL_BB_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_EN_POS)) /**< BTLELDOCTRL_BB_EN Mask */ -#define MXC_F_GCR_BTLELDOCTRL_RX_PD_EN_POS 5 /**< BTLELDOCTRL_RX_PD_EN Position */ -#define MXC_F_GCR_BTLELDOCTRL_RX_PD_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RX_PD_EN_POS)) /**< BTLELDOCTRL_RX_PD_EN Mask */ +#define MXC_F_GCR_BTLELDOCTRL_BB_PD_EN_POS 5 /**< BTLELDOCTRL_BB_PD_EN Position */ +#define MXC_F_GCR_BTLELDOCTRL_BB_PD_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_PD_EN_POS)) /**< BTLELDOCTRL_BB_PD_EN Mask */ -#define MXC_F_GCR_BTLELDOCTRL_RX_VSEL_POS 6 /**< BTLELDOCTRL_RX_VSEL Position */ -#define MXC_F_GCR_BTLELDOCTRL_RX_VSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_RX_VSEL_POS)) /**< BTLELDOCTRL_RX_VSEL Mask */ +#define MXC_F_GCR_BTLELDOCTRL_BB_VSEL_POS 6 /**< BTLELDOCTRL_BB_VSEL Position */ +#define MXC_F_GCR_BTLELDOCTRL_BB_VSEL ((uint32_t)(0x3UL << MXC_F_GCR_BTLELDOCTRL_BB_VSEL_POS)) /**< BTLELDOCTRL_BB_VSEL Mask */ -#define MXC_F_GCR_BTLELDOCTRL_RX_BP_EN_POS 8 /**< BTLELDOCTRL_RX_BP_EN Position */ -#define MXC_F_GCR_BTLELDOCTRL_RX_BP_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RX_BP_EN_POS)) /**< BTLELDOCTRL_RX_BP_EN Mask */ +#define MXC_F_GCR_BTLELDOCTRL_BB_BP_EN_POS 8 /**< BTLELDOCTRL_BB_BP_EN Position */ +#define MXC_F_GCR_BTLELDOCTRL_BB_BP_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_BP_EN_POS)) /**< BTLELDOCTRL_BB_BP_EN Mask */ -#define MXC_F_GCR_BTLELDOCTRL_RX_DISCH_POS 9 /**< BTLELDOCTRL_RX_DISCH Position */ -#define MXC_F_GCR_BTLELDOCTRL_RX_DISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RX_DISCH_POS)) /**< BTLELDOCTRL_RX_DISCH Mask */ +#define MXC_F_GCR_BTLELDOCTRL_BB_DISCH_POS 9 /**< BTLELDOCTRL_BB_DISCH Position */ +#define MXC_F_GCR_BTLELDOCTRL_BB_DISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_DISCH_POS)) /**< BTLELDOCTRL_BB_DISCH Mask */ -#define MXC_F_GCR_BTLELDOCTRL_TX_BP_EN_POS 10 /**< BTLELDOCTRL_TX_BP_EN Position */ -#define MXC_F_GCR_BTLELDOCTRL_TX_BP_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_TX_BP_EN_POS)) /**< BTLELDOCTRL_TX_BP_EN Mask */ +#define MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_POS 10 /**< BTLELDOCTRL_RF_BP_EN Position */ +#define MXC_F_GCR_BTLELDOCTRL_RF_BP_EN ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_POS)) /**< BTLELDOCTRL_RF_BP_EN Mask */ -#define MXC_F_GCR_BTLELDOCTRL_TX_DISCH_POS 11 /**< BTLELDOCTRL_TX_DISCH Position */ -#define MXC_F_GCR_BTLELDOCTRL_TX_DISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_TX_DISCH_POS)) /**< BTLELDOCTRL_TX_DISCH Mask */ +#define MXC_F_GCR_BTLELDOCTRL_RF_DISCH_POS 11 /**< BTLELDOCTRL_RF_DISCH Position */ +#define MXC_F_GCR_BTLELDOCTRL_RF_DISCH ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_DISCH_POS)) /**< BTLELDOCTRL_RF_DISCH Mask */ -#define MXC_F_GCR_BTLELDOCTRL_TX_EN_DLY_POS 12 /**< BTLELDOCTRL_TX_EN_DLY Position */ -#define MXC_F_GCR_BTLELDOCTRL_TX_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_TX_EN_DLY_POS)) /**< BTLELDOCTRL_TX_EN_DLY Mask */ +#define MXC_F_GCR_BTLELDOCTRL_RF_EN_DLY_POS 12 /**< BTLELDOCTRL_RF_EN_DLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_RF_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_EN_DLY_POS)) /**< BTLELDOCTRL_RF_EN_DLY Mask */ -#define MXC_F_GCR_BTLELDOCTRL_RX_EN_DLY_POS 13 /**< BTLELDOCTRL_RX_EN_DLY Position */ -#define MXC_F_GCR_BTLELDOCTRL_RX_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RX_EN_DLY_POS)) /**< BTLELDOCTRL_RX_EN_DLY Mask */ +#define MXC_F_GCR_BTLELDOCTRL_BB_EN_DLY_POS 13 /**< BTLELDOCTRL_BB_EN_DLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_BB_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_EN_DLY_POS)) /**< BTLELDOCTRL_BB_EN_DLY Mask */ -#define MXC_F_GCR_BTLELDOCTRL_RX_BP_EN_DLY_POS 14 /**< BTLELDOCTRL_RX_BP_EN_DLY Position */ -#define MXC_F_GCR_BTLELDOCTRL_RX_BP_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RX_BP_EN_DLY_POS)) /**< BTLELDOCTRL_RX_BP_EN_DLY Mask */ +#define MXC_F_GCR_BTLELDOCTRL_BB_BP_EN_DLY_POS 14 /**< BTLELDOCTRL_BB_BP_EN_DLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_BB_BP_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_BB_BP_EN_DLY_POS)) /**< BTLELDOCTRL_BB_BP_EN_DLY Mask */ -#define MXC_F_GCR_BTLELDOCTRL_TX_BP_EN_DLY_POS 15 /**< BTLELDOCTRL_TX_BP_EN_DLY Position */ -#define MXC_F_GCR_BTLELDOCTRL_TX_BP_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_TX_BP_EN_DLY_POS)) /**< BTLELDOCTRL_TX_BP_EN_DLY Mask */ +#define MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_DLY_POS 15 /**< BTLELDOCTRL_RF_BP_EN_DLY Position */ +#define MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_DLY ((uint32_t)(0x1UL << MXC_F_GCR_BTLELDOCTRL_RF_BP_EN_DLY_POS)) /**< BTLELDOCTRL_RF_BP_EN_DLY Mask */ /**@} end of group GCR_BTLELDOCTRL_Register */ @@ -601,11 +613,11 @@ typedef struct { #define MXC_F_GCR_BTLELDODLY_BP_CNT_POS 0 /**< BTLELDODLY_BP_CNT Position */ #define MXC_F_GCR_BTLELDODLY_BP_CNT ((uint32_t)(0xFFUL << MXC_F_GCR_BTLELDODLY_BP_CNT_POS)) /**< BTLELDODLY_BP_CNT Mask */ -#define MXC_F_GCR_BTLELDODLY_RX_CNT_POS 8 /**< BTLELDODLY_RX_CNT Position */ -#define MXC_F_GCR_BTLELDODLY_RX_CNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLELDODLY_RX_CNT_POS)) /**< BTLELDODLY_RX_CNT Mask */ +#define MXC_F_GCR_BTLELDODLY_BB_CNT_POS 8 /**< BTLELDODLY_BB_CNT Position */ +#define MXC_F_GCR_BTLELDODLY_BB_CNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLELDODLY_BB_CNT_POS)) /**< BTLELDODLY_BB_CNT Mask */ -#define MXC_F_GCR_BTLELDODLY_TX_CNT_POS 20 /**< BTLELDODLY_TX_CNT Position */ -#define MXC_F_GCR_BTLELDODLY_TX_CNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLELDODLY_TX_CNT_POS)) /**< BTLELDODLY_TX_CNT Mask */ +#define MXC_F_GCR_BTLELDODLY_RF_CNT_POS 20 /**< BTLELDODLY_RF_CNT Position */ +#define MXC_F_GCR_BTLELDODLY_RF_CNT ((uint32_t)(0x1FFUL << MXC_F_GCR_BTLELDODLY_RF_CNT_POS)) /**< BTLELDODLY_RF_CNT Mask */ /**@} end of group GCR_BTLELDODLY_Register */ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/i3c_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/i3c_regs.h new file mode 100644 index 00000000..04f5a560 --- /dev/null +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/i3c_regs.h @@ -0,0 +1,1601 @@ +/** + * @file i3c_regs.h + * @brief Registers, Bit Masks and Bit Positions for the I3C Peripheral Module. + * @note This file is @generated. + * @ingroup i3c_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_I3C_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_I3C_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup i3c + * @defgroup i3c_registers I3C_Registers + * @brief Registers, Bit Masks and Bit Positions for the I3C Peripheral Module. + * @details Improved Inter-Integrated Circuit. + */ + +/** + * @ingroup i3c_registers + * Structure type to access the I3C Registers. + */ +typedef struct { + __IO uint32_t cont_ctrl0; /**< \b 0x000: I3C CONT_CTRL0 Register */ + __IO uint32_t targ_ctrl0; /**< \b 0x004: I3C TARG_CTRL0 Register */ + __IO uint32_t targ_status; /**< \b 0x008: I3C TARG_STATUS Register */ + __IO uint32_t targ_ctrl1; /**< \b 0x00C: I3C TARG_CTRL1 Register */ + __IO uint32_t targ_inten; /**< \b 0x010: I3C TARG_INTEN Register */ + __O uint32_t targ_intclr; /**< \b 0x014: I3C TARG_INTCLR Register */ + __I uint32_t targ_intfl; /**< \b 0x018: I3C TARG_INTFL Register */ + __IO uint32_t targ_errwarn; /**< \b 0x01C: I3C TARG_ERRWARN Register */ + __IO uint32_t targ_dmactrl; /**< \b 0x020: I3C TARG_DMACTRL Register */ + __R uint32_t rsv_0x24_0x2b[2]; + __IO uint32_t targ_fifoctrl; /**< \b 0x02C: I3C TARG_FIFOCTRL Register */ + __O uint32_t targ_txfifo8; /**< \b 0x030: I3C TARG_TXFIFO8 Register */ + __O uint32_t targ_txfifo8e; /**< \b 0x034: I3C TARG_TXFIFO8E Register */ + __O uint32_t targ_txfifo16; /**< \b 0x038: I3C TARG_TXFIFO16 Register */ + __O uint32_t targ_txfifo16e; /**< \b 0x03C: I3C TARG_TXFIFO16E Register */ + __I uint32_t targ_rxfifo8; /**< \b 0x040: I3C TARG_RXFIFO8 Register */ + __R uint32_t rsv_0x44; + __I uint32_t targ_rxfifo16; /**< \b 0x048: I3C TARG_RXFIFO16 Register */ + __R uint32_t rsv_0x4c_0x53[2]; + __O uint32_t targ_txfifo8o; /**< \b 0x054: I3C TARG_TXFIFO8O Register */ + __R uint32_t rsv_0x58; + __I uint32_t targ_cap0; /**< \b 0x05C: I3C TARG_CAP0 Register */ + __I uint32_t targ_cap1; /**< \b 0x060: I3C TARG_CAP1 Register */ + __IO uint32_t targ_dynaddr; /**< \b 0x064: I3C TARG_DYNADDR Register */ + __IO uint32_t targ_maxlimits; /**< \b 0x068: I3C TARG_MAXLIMITS Register */ + __R uint32_t rsv_0x6c; + __IO uint32_t targ_idext; /**< \b 0x070: I3C TARG_IDEXT Register */ + __R uint32_t rsv_0x74_0x7b[2]; + __I uint32_t targ_msglast; /**< \b 0x07C: I3C TARG_MSGLAST Register */ + __R uint32_t rsv_0x80; + __IO uint32_t cont_ctrl1; /**< \b 0x084: I3C CONT_CTRL1 Register */ + __IO uint32_t cont_status; /**< \b 0x088: I3C CONT_STATUS Register */ + __IO uint32_t cont_ibirules; /**< \b 0x08C: I3C CONT_IBIRULES Register */ + __IO uint32_t cont_inten; /**< \b 0x090: I3C CONT_INTEN Register */ + __O uint32_t cont_intclr; /**< \b 0x094: I3C CONT_INTCLR Register */ + __I uint32_t cont_intfl; /**< \b 0x098: I3C CONT_INTFL Register */ + __IO uint32_t cont_errwarn; /**< \b 0x09C: I3C CONT_ERRWARN Register */ + __IO uint32_t cont_dmactrl; /**< \b 0x0A0: I3C CONT_DMACTRL Register */ + __R uint32_t rsv_0xa4_0xab[2]; + __IO uint32_t cont_fifoctrl; /**< \b 0x0AC: I3C CONT_FIFOCTRL Register */ + __O uint32_t cont_txfifo8; /**< \b 0x0B0: I3C CONT_TXFIFO8 Register */ + __O uint32_t cont_txfifo8e; /**< \b 0x0B4: I3C CONT_TXFIFO8E Register */ + __O uint32_t cont_txfifo16; /**< \b 0x0B8: I3C CONT_TXFIFO16 Register */ + __O uint32_t cont_txfifo16e; /**< \b 0x0BC: I3C CONT_TXFIFO16E Register */ + __I uint32_t cont_rxfifo8; /**< \b 0x0C0: I3C CONT_RXFIFO8 Register */ + __R uint32_t rsv_0xc4; + __I uint32_t cont_rxfifo16; /**< \b 0x0C8: I3C CONT_RXFIFO16 Register */ + __O uint32_t cont_txfifo8o; /**< \b 0x0CC: I3C CONT_TXFIFO8O Register */ + union { + __IO uint32_t cont_txsdrmsg_ctrl; /**< \b 0x0D0: I3C CONT_TXSDRMSG_CTRL Register */ + __O uint32_t cont_txsdrmsg_fifo; /**< \b 0x0D0: I3C CONT_TXSDRMSG_FIFO Register */ + }; + __I uint32_t cont_rxsdrmsg; /**< \b 0x0D4: I3C CONT_RXSDRMSG Register */ + __O uint32_t cont_txddrmsg; /**< \b 0x0D8: I3C CONT_TXDDRMSG Register */ + __I uint32_t cont_rxddr16; /**< \b 0x0DC: I3C CONT_RXDDR16 Register */ + __R uint32_t rsv_0xe0; + __IO uint32_t cont_dynaddr; /**< \b 0x0E4: I3C CONT_DYNADDR Register */ + __R uint32_t rsv_0xe8_0x113[11]; + __I uint32_t targ_groupdef; /**< \b 0x114: I3C TARG_GROUPDEF Register */ + __R uint32_t rsv_0x118; + __IO uint32_t targ_mapctrl0; /**< \b 0x11C: I3C TARG_MAPCTRL0 Register */ + __IO uint32_t targ_mapctrl1; /**< \b 0x120: I3C TARG_MAPCTRL1 Register */ + __IO uint32_t targ_mapctrl2; /**< \b 0x124: I3C TARG_MAPCTRL2 Register */ +} mxc_i3c_regs_t; + +/* Register offsets for module I3C */ +/** + * @ingroup i3c_registers + * @defgroup I3C_Register_Offsets Register Offsets + * @brief I3C Peripheral Register Offsets from the I3C Base Peripheral Address. + * @{ + */ +#define MXC_R_I3C_CONT_CTRL0 ((uint32_t)0x00000000UL) /**< Offset from I3C Base Address: 0x0000 */ +#define MXC_R_I3C_TARG_CTRL0 ((uint32_t)0x00000004UL) /**< Offset from I3C Base Address: 0x0004 */ +#define MXC_R_I3C_TARG_STATUS ((uint32_t)0x00000008UL) /**< Offset from I3C Base Address: 0x0008 */ +#define MXC_R_I3C_TARG_CTRL1 ((uint32_t)0x0000000CUL) /**< Offset from I3C Base Address: 0x000C */ +#define MXC_R_I3C_TARG_INTEN ((uint32_t)0x00000010UL) /**< Offset from I3C Base Address: 0x0010 */ +#define MXC_R_I3C_TARG_INTCLR ((uint32_t)0x00000014UL) /**< Offset from I3C Base Address: 0x0014 */ +#define MXC_R_I3C_TARG_INTFL ((uint32_t)0x00000018UL) /**< Offset from I3C Base Address: 0x0018 */ +#define MXC_R_I3C_TARG_ERRWARN ((uint32_t)0x0000001CUL) /**< Offset from I3C Base Address: 0x001C */ +#define MXC_R_I3C_TARG_DMACTRL ((uint32_t)0x00000020UL) /**< Offset from I3C Base Address: 0x0020 */ +#define MXC_R_I3C_TARG_FIFOCTRL ((uint32_t)0x0000002CUL) /**< Offset from I3C Base Address: 0x002C */ +#define MXC_R_I3C_TARG_TXFIFO8 ((uint32_t)0x00000030UL) /**< Offset from I3C Base Address: 0x0030 */ +#define MXC_R_I3C_TARG_TXFIFO8E ((uint32_t)0x00000034UL) /**< Offset from I3C Base Address: 0x0034 */ +#define MXC_R_I3C_TARG_TXFIFO16 ((uint32_t)0x00000038UL) /**< Offset from I3C Base Address: 0x0038 */ +#define MXC_R_I3C_TARG_TXFIFO16E ((uint32_t)0x0000003CUL) /**< Offset from I3C Base Address: 0x003C */ +#define MXC_R_I3C_TARG_RXFIFO8 ((uint32_t)0x00000040UL) /**< Offset from I3C Base Address: 0x0040 */ +#define MXC_R_I3C_TARG_RXFIFO16 ((uint32_t)0x00000048UL) /**< Offset from I3C Base Address: 0x0048 */ +#define MXC_R_I3C_TARG_TXFIFO8O ((uint32_t)0x00000054UL) /**< Offset from I3C Base Address: 0x0054 */ +#define MXC_R_I3C_TARG_CAP0 ((uint32_t)0x0000005CUL) /**< Offset from I3C Base Address: 0x005C */ +#define MXC_R_I3C_TARG_CAP1 ((uint32_t)0x00000060UL) /**< Offset from I3C Base Address: 0x0060 */ +#define MXC_R_I3C_TARG_DYNADDR ((uint32_t)0x00000064UL) /**< Offset from I3C Base Address: 0x0064 */ +#define MXC_R_I3C_TARG_MAXLIMITS ((uint32_t)0x00000068UL) /**< Offset from I3C Base Address: 0x0068 */ +#define MXC_R_I3C_TARG_IDEXT ((uint32_t)0x00000070UL) /**< Offset from I3C Base Address: 0x0070 */ +#define MXC_R_I3C_TARG_MSGLAST ((uint32_t)0x0000007CUL) /**< Offset from I3C Base Address: 0x007C */ +#define MXC_R_I3C_CONT_CTRL1 ((uint32_t)0x00000084UL) /**< Offset from I3C Base Address: 0x0084 */ +#define MXC_R_I3C_CONT_STATUS ((uint32_t)0x00000088UL) /**< Offset from I3C Base Address: 0x0088 */ +#define MXC_R_I3C_CONT_IBIRULES ((uint32_t)0x0000008CUL) /**< Offset from I3C Base Address: 0x008C */ +#define MXC_R_I3C_CONT_INTEN ((uint32_t)0x00000090UL) /**< Offset from I3C Base Address: 0x0090 */ +#define MXC_R_I3C_CONT_INTCLR ((uint32_t)0x00000094UL) /**< Offset from I3C Base Address: 0x0094 */ +#define MXC_R_I3C_CONT_INTFL ((uint32_t)0x00000098UL) /**< Offset from I3C Base Address: 0x0098 */ +#define MXC_R_I3C_CONT_ERRWARN ((uint32_t)0x0000009CUL) /**< Offset from I3C Base Address: 0x009C */ +#define MXC_R_I3C_CONT_DMACTRL ((uint32_t)0x000000A0UL) /**< Offset from I3C Base Address: 0x00A0 */ +#define MXC_R_I3C_CONT_FIFOCTRL ((uint32_t)0x000000ACUL) /**< Offset from I3C Base Address: 0x00AC */ +#define MXC_R_I3C_CONT_TXFIFO8 ((uint32_t)0x000000B0UL) /**< Offset from I3C Base Address: 0x00B0 */ +#define MXC_R_I3C_CONT_TXFIFO8E ((uint32_t)0x000000B4UL) /**< Offset from I3C Base Address: 0x00B4 */ +#define MXC_R_I3C_CONT_TXFIFO16 ((uint32_t)0x000000B8UL) /**< Offset from I3C Base Address: 0x00B8 */ +#define MXC_R_I3C_CONT_TXFIFO16E ((uint32_t)0x000000BCUL) /**< Offset from I3C Base Address: 0x00BC */ +#define MXC_R_I3C_CONT_RXFIFO8 ((uint32_t)0x000000C0UL) /**< Offset from I3C Base Address: 0x00C0 */ +#define MXC_R_I3C_CONT_RXFIFO16 ((uint32_t)0x000000C8UL) /**< Offset from I3C Base Address: 0x00C8 */ +#define MXC_R_I3C_CONT_TXFIFO8O ((uint32_t)0x000000CCUL) /**< Offset from I3C Base Address: 0x00CC */ +#define MXC_R_I3C_CONT_TXSDRMSG_CTRL ((uint32_t)0x000000D0UL) /**< Offset from I3C Base Address: 0x00D0 */ +#define MXC_R_I3C_CONT_TXSDRMSG_FIFO ((uint32_t)0x000000D0UL) /**< Offset from I3C Base Address: 0x00D0 */ +#define MXC_R_I3C_CONT_RXSDRMSG ((uint32_t)0x000000D4UL) /**< Offset from I3C Base Address: 0x00D4 */ +#define MXC_R_I3C_CONT_TXDDRMSG ((uint32_t)0x000000D8UL) /**< Offset from I3C Base Address: 0x00D8 */ +#define MXC_R_I3C_CONT_RXDDR16 ((uint32_t)0x000000DCUL) /**< Offset from I3C Base Address: 0x00DC */ +#define MXC_R_I3C_CONT_DYNADDR ((uint32_t)0x000000E4UL) /**< Offset from I3C Base Address: 0x00E4 */ +#define MXC_R_I3C_TARG_GROUPDEF ((uint32_t)0x00000114UL) /**< Offset from I3C Base Address: 0x0114 */ +#define MXC_R_I3C_TARG_MAPCTRL0 ((uint32_t)0x0000011CUL) /**< Offset from I3C Base Address: 0x011C */ +#define MXC_R_I3C_TARG_MAPCTRL1 ((uint32_t)0x00000120UL) /**< Offset from I3C Base Address: 0x0120 */ +#define MXC_R_I3C_TARG_MAPCTRL2 ((uint32_t)0x00000124UL) /**< Offset from I3C Base Address: 0x0124 */ +/**@} end of group i3c_registers */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_CTRL0 I3C_CONT_CTRL0 + * @brief Controller Control 0 (Configuration) Register. + * @{ + */ +#define MXC_F_I3C_CONT_CTRL0_EN_POS 0 /**< CONT_CTRL0_EN Position */ +#define MXC_F_I3C_CONT_CTRL0_EN ((uint32_t)(0x3UL << MXC_F_I3C_CONT_CTRL0_EN_POS)) /**< CONT_CTRL0_EN Mask */ +#define MXC_V_I3C_CONT_CTRL0_EN_OFF ((uint32_t)0x0UL) /**< CONT_CTRL0_EN_OFF Value */ +#define MXC_S_I3C_CONT_CTRL0_EN_OFF (MXC_V_I3C_CONT_CTRL0_EN_OFF << MXC_F_I3C_CONT_CTRL0_EN_POS) /**< CONT_CTRL0_EN_OFF Setting */ +#define MXC_V_I3C_CONT_CTRL0_EN_ON ((uint32_t)0x1UL) /**< CONT_CTRL0_EN_ON Value */ +#define MXC_S_I3C_CONT_CTRL0_EN_ON (MXC_V_I3C_CONT_CTRL0_EN_ON << MXC_F_I3C_CONT_CTRL0_EN_POS) /**< CONT_CTRL0_EN_ON Setting */ +#define MXC_V_I3C_CONT_CTRL0_EN_CAP ((uint32_t)0x2UL) /**< CONT_CTRL0_EN_CAP Value */ +#define MXC_S_I3C_CONT_CTRL0_EN_CAP (MXC_V_I3C_CONT_CTRL0_EN_CAP << MXC_F_I3C_CONT_CTRL0_EN_POS) /**< CONT_CTRL0_EN_CAP Setting */ + +#define MXC_F_I3C_CONT_CTRL0_TO_DIS_POS 3 /**< CONT_CTRL0_TO_DIS Position */ +#define MXC_F_I3C_CONT_CTRL0_TO_DIS ((uint32_t)(0x1UL << MXC_F_I3C_CONT_CTRL0_TO_DIS_POS)) /**< CONT_CTRL0_TO_DIS Mask */ + +#define MXC_F_I3C_CONT_CTRL0_HKEEP_POS 4 /**< CONT_CTRL0_HKEEP Position */ +#define MXC_F_I3C_CONT_CTRL0_HKEEP ((uint32_t)(0x3UL << MXC_F_I3C_CONT_CTRL0_HKEEP_POS)) /**< CONT_CTRL0_HKEEP Mask */ +#define MXC_V_I3C_CONT_CTRL0_HKEEP_OFF ((uint32_t)0x0UL) /**< CONT_CTRL0_HKEEP_OFF Value */ +#define MXC_S_I3C_CONT_CTRL0_HKEEP_OFF (MXC_V_I3C_CONT_CTRL0_HKEEP_OFF << MXC_F_I3C_CONT_CTRL0_HKEEP_POS) /**< CONT_CTRL0_HKEEP_OFF Setting */ +#define MXC_V_I3C_CONT_CTRL0_HKEEP_ON_CHIP ((uint32_t)0x1UL) /**< CONT_CTRL0_HKEEP_ON_CHIP Value */ +#define MXC_S_I3C_CONT_CTRL0_HKEEP_ON_CHIP (MXC_V_I3C_CONT_CTRL0_HKEEP_ON_CHIP << MXC_F_I3C_CONT_CTRL0_HKEEP_POS) /**< CONT_CTRL0_HKEEP_ON_CHIP Setting */ +#define MXC_V_I3C_CONT_CTRL0_HKEEP_EXT_SDA ((uint32_t)0x2UL) /**< CONT_CTRL0_HKEEP_EXT_SDA Value */ +#define MXC_S_I3C_CONT_CTRL0_HKEEP_EXT_SDA (MXC_V_I3C_CONT_CTRL0_HKEEP_EXT_SDA << MXC_F_I3C_CONT_CTRL0_HKEEP_POS) /**< CONT_CTRL0_HKEEP_EXT_SDA Setting */ +#define MXC_V_I3C_CONT_CTRL0_HKEEP_EXT_SCL_SDA ((uint32_t)0x3UL) /**< CONT_CTRL0_HKEEP_EXT_SCL_SDA Value */ +#define MXC_S_I3C_CONT_CTRL0_HKEEP_EXT_SCL_SDA (MXC_V_I3C_CONT_CTRL0_HKEEP_EXT_SCL_SDA << MXC_F_I3C_CONT_CTRL0_HKEEP_POS) /**< CONT_CTRL0_HKEEP_EXT_SCL_SDA Setting */ + +#define MXC_F_I3C_CONT_CTRL0_OD_STOP_POS 6 /**< CONT_CTRL0_OD_STOP Position */ +#define MXC_F_I3C_CONT_CTRL0_OD_STOP ((uint32_t)(0x1UL << MXC_F_I3C_CONT_CTRL0_OD_STOP_POS)) /**< CONT_CTRL0_OD_STOP Mask */ + +#define MXC_F_I3C_CONT_CTRL0_PP_BAUD_POS 8 /**< CONT_CTRL0_PP_BAUD Position */ +#define MXC_F_I3C_CONT_CTRL0_PP_BAUD ((uint32_t)(0xFUL << MXC_F_I3C_CONT_CTRL0_PP_BAUD_POS)) /**< CONT_CTRL0_PP_BAUD Mask */ +#define MXC_V_I3C_CONT_CTRL0_PP_BAUD_1_FCLK ((uint32_t)0x0UL) /**< CONT_CTRL0_PP_BAUD_1_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_BAUD_1_FCLK (MXC_V_I3C_CONT_CTRL0_PP_BAUD_1_FCLK << MXC_F_I3C_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_1_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_BAUD_2_FCLK ((uint32_t)0x1UL) /**< CONT_CTRL0_PP_BAUD_2_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_BAUD_2_FCLK (MXC_V_I3C_CONT_CTRL0_PP_BAUD_2_FCLK << MXC_F_I3C_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_2_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_BAUD_3_FCLK ((uint32_t)0x2UL) /**< CONT_CTRL0_PP_BAUD_3_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_BAUD_3_FCLK (MXC_V_I3C_CONT_CTRL0_PP_BAUD_3_FCLK << MXC_F_I3C_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_3_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_BAUD_4_FCLK ((uint32_t)0x3UL) /**< CONT_CTRL0_PP_BAUD_4_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_BAUD_4_FCLK (MXC_V_I3C_CONT_CTRL0_PP_BAUD_4_FCLK << MXC_F_I3C_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_4_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_BAUD_5_FCLK ((uint32_t)0x4UL) /**< CONT_CTRL0_PP_BAUD_5_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_BAUD_5_FCLK (MXC_V_I3C_CONT_CTRL0_PP_BAUD_5_FCLK << MXC_F_I3C_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_5_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_BAUD_6_FCLK ((uint32_t)0x5UL) /**< CONT_CTRL0_PP_BAUD_6_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_BAUD_6_FCLK (MXC_V_I3C_CONT_CTRL0_PP_BAUD_6_FCLK << MXC_F_I3C_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_6_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_BAUD_7_FCLK ((uint32_t)0x6UL) /**< CONT_CTRL0_PP_BAUD_7_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_BAUD_7_FCLK (MXC_V_I3C_CONT_CTRL0_PP_BAUD_7_FCLK << MXC_F_I3C_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_7_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_BAUD_8_FCLK ((uint32_t)0x7UL) /**< CONT_CTRL0_PP_BAUD_8_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_BAUD_8_FCLK (MXC_V_I3C_CONT_CTRL0_PP_BAUD_8_FCLK << MXC_F_I3C_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_8_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_BAUD_9_FCLK ((uint32_t)0x8UL) /**< CONT_CTRL0_PP_BAUD_9_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_BAUD_9_FCLK (MXC_V_I3C_CONT_CTRL0_PP_BAUD_9_FCLK << MXC_F_I3C_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_9_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_BAUD_10_FCLK ((uint32_t)0x9UL) /**< CONT_CTRL0_PP_BAUD_10_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_BAUD_10_FCLK (MXC_V_I3C_CONT_CTRL0_PP_BAUD_10_FCLK << MXC_F_I3C_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_10_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_BAUD_11_FCLK ((uint32_t)0xAUL) /**< CONT_CTRL0_PP_BAUD_11_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_BAUD_11_FCLK (MXC_V_I3C_CONT_CTRL0_PP_BAUD_11_FCLK << MXC_F_I3C_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_11_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_BAUD_12_FCLK ((uint32_t)0xBUL) /**< CONT_CTRL0_PP_BAUD_12_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_BAUD_12_FCLK (MXC_V_I3C_CONT_CTRL0_PP_BAUD_12_FCLK << MXC_F_I3C_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_12_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_BAUD_13_FCLK ((uint32_t)0xCUL) /**< CONT_CTRL0_PP_BAUD_13_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_BAUD_13_FCLK (MXC_V_I3C_CONT_CTRL0_PP_BAUD_13_FCLK << MXC_F_I3C_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_13_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_BAUD_14_FCLK ((uint32_t)0xDUL) /**< CONT_CTRL0_PP_BAUD_14_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_BAUD_14_FCLK (MXC_V_I3C_CONT_CTRL0_PP_BAUD_14_FCLK << MXC_F_I3C_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_14_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_BAUD_15_FCLK ((uint32_t)0xEUL) /**< CONT_CTRL0_PP_BAUD_15_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_BAUD_15_FCLK (MXC_V_I3C_CONT_CTRL0_PP_BAUD_15_FCLK << MXC_F_I3C_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_15_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_BAUD_16_FCLK ((uint32_t)0xFUL) /**< CONT_CTRL0_PP_BAUD_16_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_BAUD_16_FCLK (MXC_V_I3C_CONT_CTRL0_PP_BAUD_16_FCLK << MXC_F_I3C_CONT_CTRL0_PP_BAUD_POS) /**< CONT_CTRL0_PP_BAUD_16_FCLK Setting */ + +#define MXC_F_I3C_CONT_CTRL0_PP_ADD_LBAUD_POS 12 /**< CONT_CTRL0_PP_ADD_LBAUD Position */ +#define MXC_F_I3C_CONT_CTRL0_PP_ADD_LBAUD ((uint32_t)(0xFUL << MXC_F_I3C_CONT_CTRL0_PP_ADD_LBAUD_POS)) /**< CONT_CTRL0_PP_ADD_LBAUD Mask */ +#define MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_0_FCLK ((uint32_t)0x0UL) /**< CONT_CTRL0_PP_ADD_LBAUD_0_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_ADD_LBAUD_0_FCLK (MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_0_FCLK << MXC_F_I3C_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_0_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_1_FCLK ((uint32_t)0x1UL) /**< CONT_CTRL0_PP_ADD_LBAUD_1_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_ADD_LBAUD_1_FCLK (MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_1_FCLK << MXC_F_I3C_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_1_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_2_FCLK ((uint32_t)0x2UL) /**< CONT_CTRL0_PP_ADD_LBAUD_2_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_ADD_LBAUD_2_FCLK (MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_2_FCLK << MXC_F_I3C_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_2_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_3_FCLK ((uint32_t)0x3UL) /**< CONT_CTRL0_PP_ADD_LBAUD_3_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_ADD_LBAUD_3_FCLK (MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_3_FCLK << MXC_F_I3C_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_3_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_4_FCLK ((uint32_t)0x4UL) /**< CONT_CTRL0_PP_ADD_LBAUD_4_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_ADD_LBAUD_4_FCLK (MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_4_FCLK << MXC_F_I3C_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_4_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_5_FCLK ((uint32_t)0x5UL) /**< CONT_CTRL0_PP_ADD_LBAUD_5_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_ADD_LBAUD_5_FCLK (MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_5_FCLK << MXC_F_I3C_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_5_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_6_FCLK ((uint32_t)0x6UL) /**< CONT_CTRL0_PP_ADD_LBAUD_6_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_ADD_LBAUD_6_FCLK (MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_6_FCLK << MXC_F_I3C_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_6_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_7_FCLK ((uint32_t)0x7UL) /**< CONT_CTRL0_PP_ADD_LBAUD_7_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_ADD_LBAUD_7_FCLK (MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_7_FCLK << MXC_F_I3C_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_7_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_8_FCLK ((uint32_t)0x8UL) /**< CONT_CTRL0_PP_ADD_LBAUD_8_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_ADD_LBAUD_8_FCLK (MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_8_FCLK << MXC_F_I3C_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_8_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_9_FCLK ((uint32_t)0x9UL) /**< CONT_CTRL0_PP_ADD_LBAUD_9_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_ADD_LBAUD_9_FCLK (MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_9_FCLK << MXC_F_I3C_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_9_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_10_FCLK ((uint32_t)0xAUL) /**< CONT_CTRL0_PP_ADD_LBAUD_10_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_ADD_LBAUD_10_FCLK (MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_10_FCLK << MXC_F_I3C_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_10_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_11_FCLK ((uint32_t)0xBUL) /**< CONT_CTRL0_PP_ADD_LBAUD_11_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_ADD_LBAUD_11_FCLK (MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_11_FCLK << MXC_F_I3C_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_11_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_12_FCLK ((uint32_t)0xCUL) /**< CONT_CTRL0_PP_ADD_LBAUD_12_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_ADD_LBAUD_12_FCLK (MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_12_FCLK << MXC_F_I3C_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_12_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_13_FCLK ((uint32_t)0xDUL) /**< CONT_CTRL0_PP_ADD_LBAUD_13_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_ADD_LBAUD_13_FCLK (MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_13_FCLK << MXC_F_I3C_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_13_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_14_FCLK ((uint32_t)0xEUL) /**< CONT_CTRL0_PP_ADD_LBAUD_14_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_ADD_LBAUD_14_FCLK (MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_14_FCLK << MXC_F_I3C_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_14_FCLK Setting */ +#define MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_15_FCLK ((uint32_t)0xFUL) /**< CONT_CTRL0_PP_ADD_LBAUD_15_FCLK Value */ +#define MXC_S_I3C_CONT_CTRL0_PP_ADD_LBAUD_15_FCLK (MXC_V_I3C_CONT_CTRL0_PP_ADD_LBAUD_15_FCLK << MXC_F_I3C_CONT_CTRL0_PP_ADD_LBAUD_POS) /**< CONT_CTRL0_PP_ADD_LBAUD_15_FCLK Setting */ + +#define MXC_F_I3C_CONT_CTRL0_OD_LBAUD_POS 16 /**< CONT_CTRL0_OD_LBAUD Position */ +#define MXC_F_I3C_CONT_CTRL0_OD_LBAUD ((uint32_t)(0xFFUL << MXC_F_I3C_CONT_CTRL0_OD_LBAUD_POS)) /**< CONT_CTRL0_OD_LBAUD Mask */ + +#define MXC_F_I3C_CONT_CTRL0_OD_HP_POS 24 /**< CONT_CTRL0_OD_HP Position */ +#define MXC_F_I3C_CONT_CTRL0_OD_HP ((uint32_t)(0x1UL << MXC_F_I3C_CONT_CTRL0_OD_HP_POS)) /**< CONT_CTRL0_OD_HP Mask */ + +#define MXC_F_I3C_CONT_CTRL0_PP_SKEW_POS 25 /**< CONT_CTRL0_PP_SKEW Position */ +#define MXC_F_I3C_CONT_CTRL0_PP_SKEW ((uint32_t)(0x7UL << MXC_F_I3C_CONT_CTRL0_PP_SKEW_POS)) /**< CONT_CTRL0_PP_SKEW Mask */ + +#define MXC_F_I3C_CONT_CTRL0_I2C_BAUD_POS 28 /**< CONT_CTRL0_I2C_BAUD Position */ +#define MXC_F_I3C_CONT_CTRL0_I2C_BAUD ((uint32_t)(0xFUL << MXC_F_I3C_CONT_CTRL0_I2C_BAUD_POS)) /**< CONT_CTRL0_I2C_BAUD Mask */ + +/**@} end of group I3C_CONT_CTRL0_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_CTRL0 I3C_TARG_CTRL0 + * @brief Target Control 0 (Configuration) Register. + * @{ + */ +#define MXC_F_I3C_TARG_CTRL0_EN_POS 0 /**< TARG_CTRL0_EN Position */ +#define MXC_F_I3C_TARG_CTRL0_EN ((uint32_t)(0x1UL << MXC_F_I3C_TARG_CTRL0_EN_POS)) /**< TARG_CTRL0_EN Mask */ + +#define MXC_F_I3C_TARG_CTRL0_MATCHSS_POS 2 /**< TARG_CTRL0_MATCHSS Position */ +#define MXC_F_I3C_TARG_CTRL0_MATCHSS ((uint32_t)(0x1UL << MXC_F_I3C_TARG_CTRL0_MATCHSS_POS)) /**< TARG_CTRL0_MATCHSS Mask */ + +#define MXC_F_I3C_TARG_CTRL0_TO_IGN_POS 3 /**< TARG_CTRL0_TO_IGN Position */ +#define MXC_F_I3C_TARG_CTRL0_TO_IGN ((uint32_t)(0x1UL << MXC_F_I3C_TARG_CTRL0_TO_IGN_POS)) /**< TARG_CTRL0_TO_IGN Mask */ + +#define MXC_F_I3C_TARG_CTRL0_OFFLINE_POS 9 /**< TARG_CTRL0_OFFLINE Position */ +#define MXC_F_I3C_TARG_CTRL0_OFFLINE ((uint32_t)(0x1UL << MXC_F_I3C_TARG_CTRL0_OFFLINE_POS)) /**< TARG_CTRL0_OFFLINE Mask */ + +/**@} end of group I3C_TARG_CTRL0_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_STATUS I3C_TARG_STATUS + * @brief Target Status Register. + * @{ + */ +#define MXC_F_I3C_TARG_STATUS_BUSY_POS 0 /**< TARG_STATUS_BUSY Position */ +#define MXC_F_I3C_TARG_STATUS_BUSY ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_BUSY_POS)) /**< TARG_STATUS_BUSY Mask */ + +#define MXC_F_I3C_TARG_STATUS_LIST_RESP_POS 1 /**< TARG_STATUS_LIST_RESP Position */ +#define MXC_F_I3C_TARG_STATUS_LIST_RESP ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_LIST_RESP_POS)) /**< TARG_STATUS_LIST_RESP Mask */ + +#define MXC_F_I3C_TARG_STATUS_CCCH_POS 2 /**< TARG_STATUS_CCCH Position */ +#define MXC_F_I3C_TARG_STATUS_CCCH ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_CCCH_POS)) /**< TARG_STATUS_CCCH Mask */ + +#define MXC_F_I3C_TARG_STATUS_RX_SDR_POS 3 /**< TARG_STATUS_RX_SDR Position */ +#define MXC_F_I3C_TARG_STATUS_RX_SDR ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_RX_SDR_POS)) /**< TARG_STATUS_RX_SDR Mask */ + +#define MXC_F_I3C_TARG_STATUS_TX_SDR_POS 4 /**< TARG_STATUS_TX_SDR Position */ +#define MXC_F_I3C_TARG_STATUS_TX_SDR ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_TX_SDR_POS)) /**< TARG_STATUS_TX_SDR Mask */ + +#define MXC_F_I3C_TARG_STATUS_DAA_POS 5 /**< TARG_STATUS_DAA Position */ +#define MXC_F_I3C_TARG_STATUS_DAA ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_DAA_POS)) /**< TARG_STATUS_DAA Mask */ + +#define MXC_F_I3C_TARG_STATUS_HDR_POS 6 /**< TARG_STATUS_HDR Position */ +#define MXC_F_I3C_TARG_STATUS_HDR ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_HDR_POS)) /**< TARG_STATUS_HDR Mask */ + +#define MXC_F_I3C_TARG_STATUS_START_POS 8 /**< TARG_STATUS_START Position */ +#define MXC_F_I3C_TARG_STATUS_START ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_START_POS)) /**< TARG_STATUS_START Mask */ + +#define MXC_F_I3C_TARG_STATUS_ADDRMATCH_POS 9 /**< TARG_STATUS_ADDRMATCH Position */ +#define MXC_F_I3C_TARG_STATUS_ADDRMATCH ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_ADDRMATCH_POS)) /**< TARG_STATUS_ADDRMATCH Mask */ + +#define MXC_F_I3C_TARG_STATUS_STOP_POS 10 /**< TARG_STATUS_STOP Position */ +#define MXC_F_I3C_TARG_STATUS_STOP ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_STOP_POS)) /**< TARG_STATUS_STOP Mask */ + +#define MXC_F_I3C_TARG_STATUS_RX_RDY_POS 11 /**< TARG_STATUS_RX_RDY Position */ +#define MXC_F_I3C_TARG_STATUS_RX_RDY ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_RX_RDY_POS)) /**< TARG_STATUS_RX_RDY Mask */ + +#define MXC_F_I3C_TARG_STATUS_TX_NFULL_POS 12 /**< TARG_STATUS_TX_NFULL Position */ +#define MXC_F_I3C_TARG_STATUS_TX_NFULL ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_TX_NFULL_POS)) /**< TARG_STATUS_TX_NFULL Mask */ + +#define MXC_F_I3C_TARG_STATUS_DYNADDR_CHG_POS 13 /**< TARG_STATUS_DYNADDR_CHG Position */ +#define MXC_F_I3C_TARG_STATUS_DYNADDR_CHG ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_DYNADDR_CHG_POS)) /**< TARG_STATUS_DYNADDR_CHG Mask */ + +#define MXC_F_I3C_TARG_STATUS_CCC_POS 14 /**< TARG_STATUS_CCC Position */ +#define MXC_F_I3C_TARG_STATUS_CCC ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_CCC_POS)) /**< TARG_STATUS_CCC Mask */ + +#define MXC_F_I3C_TARG_STATUS_ERRWARN_POS 15 /**< TARG_STATUS_ERRWARN Position */ +#define MXC_F_I3C_TARG_STATUS_ERRWARN ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_ERRWARN_POS)) /**< TARG_STATUS_ERRWARN Mask */ + +#define MXC_F_I3C_TARG_STATUS_CCCH_DONE_POS 17 /**< TARG_STATUS_CCCH_DONE Position */ +#define MXC_F_I3C_TARG_STATUS_CCCH_DONE ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_CCCH_DONE_POS)) /**< TARG_STATUS_CCCH_DONE Mask */ + +#define MXC_F_I3C_TARG_STATUS_EVENT_REQ_POS 18 /**< TARG_STATUS_EVENT_REQ Position */ +#define MXC_F_I3C_TARG_STATUS_EVENT_REQ ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_EVENT_REQ_POS)) /**< TARG_STATUS_EVENT_REQ Mask */ + +#define MXC_F_I3C_TARG_STATUS_TARG_RST_POS 19 /**< TARG_STATUS_TARG_RST Position */ +#define MXC_F_I3C_TARG_STATUS_TARG_RST ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_TARG_RST_POS)) /**< TARG_STATUS_TARG_RST Mask */ + +#define MXC_F_I3C_TARG_STATUS_EVENT_POS 20 /**< TARG_STATUS_EVENT Position */ +#define MXC_F_I3C_TARG_STATUS_EVENT ((uint32_t)(0x3UL << MXC_F_I3C_TARG_STATUS_EVENT_POS)) /**< TARG_STATUS_EVENT Mask */ +#define MXC_V_I3C_TARG_STATUS_EVENT_NONE ((uint32_t)0x0UL) /**< TARG_STATUS_EVENT_NONE Value */ +#define MXC_S_I3C_TARG_STATUS_EVENT_NONE (MXC_V_I3C_TARG_STATUS_EVENT_NONE << MXC_F_I3C_TARG_STATUS_EVENT_POS) /**< TARG_STATUS_EVENT_NONE Setting */ +#define MXC_V_I3C_TARG_STATUS_EVENT_REQ_PEND ((uint32_t)0x1UL) /**< TARG_STATUS_EVENT_REQ_PEND Value */ +#define MXC_S_I3C_TARG_STATUS_EVENT_REQ_PEND (MXC_V_I3C_TARG_STATUS_EVENT_REQ_PEND << MXC_F_I3C_TARG_STATUS_EVENT_POS) /**< TARG_STATUS_EVENT_REQ_PEND Setting */ +#define MXC_V_I3C_TARG_STATUS_EVENT_REQ_NACK ((uint32_t)0x2UL) /**< TARG_STATUS_EVENT_REQ_NACK Value */ +#define MXC_S_I3C_TARG_STATUS_EVENT_REQ_NACK (MXC_V_I3C_TARG_STATUS_EVENT_REQ_NACK << MXC_F_I3C_TARG_STATUS_EVENT_POS) /**< TARG_STATUS_EVENT_REQ_NACK Setting */ +#define MXC_V_I3C_TARG_STATUS_EVENT_REQ_ACK ((uint32_t)0x3UL) /**< TARG_STATUS_EVENT_REQ_ACK Value */ +#define MXC_S_I3C_TARG_STATUS_EVENT_REQ_ACK (MXC_V_I3C_TARG_STATUS_EVENT_REQ_ACK << MXC_F_I3C_TARG_STATUS_EVENT_POS) /**< TARG_STATUS_EVENT_REQ_ACK Setting */ + +#define MXC_F_I3C_TARG_STATUS_IBI_DIS_POS 24 /**< TARG_STATUS_IBI_DIS Position */ +#define MXC_F_I3C_TARG_STATUS_IBI_DIS ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_IBI_DIS_POS)) /**< TARG_STATUS_IBI_DIS Mask */ + +#define MXC_F_I3C_TARG_STATUS_CONTREQ_DIS_POS 25 /**< TARG_STATUS_CONTREQ_DIS Position */ +#define MXC_F_I3C_TARG_STATUS_CONTREQ_DIS ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_CONTREQ_DIS_POS)) /**< TARG_STATUS_CONTREQ_DIS Mask */ + +#define MXC_F_I3C_TARG_STATUS_HJ_DIS_POS 27 /**< TARG_STATUS_HJ_DIS Position */ +#define MXC_F_I3C_TARG_STATUS_HJ_DIS ((uint32_t)(0x1UL << MXC_F_I3C_TARG_STATUS_HJ_DIS_POS)) /**< TARG_STATUS_HJ_DIS Mask */ + +#define MXC_F_I3C_TARG_STATUS_ACTSTATE_POS 28 /**< TARG_STATUS_ACTSTATE Position */ +#define MXC_F_I3C_TARG_STATUS_ACTSTATE ((uint32_t)(0x3UL << MXC_F_I3C_TARG_STATUS_ACTSTATE_POS)) /**< TARG_STATUS_ACTSTATE Mask */ +#define MXC_V_I3C_TARG_STATUS_ACTSTATE_NORMAL ((uint32_t)0x0UL) /**< TARG_STATUS_ACTSTATE_NORMAL Value */ +#define MXC_S_I3C_TARG_STATUS_ACTSTATE_NORMAL (MXC_V_I3C_TARG_STATUS_ACTSTATE_NORMAL << MXC_F_I3C_TARG_STATUS_ACTSTATE_POS) /**< TARG_STATUS_ACTSTATE_NORMAL Setting */ +#define MXC_V_I3C_TARG_STATUS_ACTSTATE_1MS_LAT ((uint32_t)0x1UL) /**< TARG_STATUS_ACTSTATE_1MS_LAT Value */ +#define MXC_S_I3C_TARG_STATUS_ACTSTATE_1MS_LAT (MXC_V_I3C_TARG_STATUS_ACTSTATE_1MS_LAT << MXC_F_I3C_TARG_STATUS_ACTSTATE_POS) /**< TARG_STATUS_ACTSTATE_1MS_LAT Setting */ +#define MXC_V_I3C_TARG_STATUS_ACTSTATE_100MS_LAT ((uint32_t)0x2UL) /**< TARG_STATUS_ACTSTATE_100MS_LAT Value */ +#define MXC_S_I3C_TARG_STATUS_ACTSTATE_100MS_LAT (MXC_V_I3C_TARG_STATUS_ACTSTATE_100MS_LAT << MXC_F_I3C_TARG_STATUS_ACTSTATE_POS) /**< TARG_STATUS_ACTSTATE_100MS_LAT Setting */ +#define MXC_V_I3C_TARG_STATUS_ACTSTATE_10S_LAT ((uint32_t)0x3UL) /**< TARG_STATUS_ACTSTATE_10S_LAT Value */ +#define MXC_S_I3C_TARG_STATUS_ACTSTATE_10S_LAT (MXC_V_I3C_TARG_STATUS_ACTSTATE_10S_LAT << MXC_F_I3C_TARG_STATUS_ACTSTATE_POS) /**< TARG_STATUS_ACTSTATE_10S_LAT Setting */ + +#define MXC_F_I3C_TARG_STATUS_TIMECTRL_POS 30 /**< TARG_STATUS_TIMECTRL Position */ +#define MXC_F_I3C_TARG_STATUS_TIMECTRL ((uint32_t)(0x3UL << MXC_F_I3C_TARG_STATUS_TIMECTRL_POS)) /**< TARG_STATUS_TIMECTRL Mask */ +#define MXC_V_I3C_TARG_STATUS_TIMECTRL_DIS ((uint32_t)0x0UL) /**< TARG_STATUS_TIMECTRL_DIS Value */ +#define MXC_S_I3C_TARG_STATUS_TIMECTRL_DIS (MXC_V_I3C_TARG_STATUS_TIMECTRL_DIS << MXC_F_I3C_TARG_STATUS_TIMECTRL_POS) /**< TARG_STATUS_TIMECTRL_DIS Setting */ +#define MXC_V_I3C_TARG_STATUS_TIMECTRL_SYNC ((uint32_t)0x1UL) /**< TARG_STATUS_TIMECTRL_SYNC Value */ +#define MXC_S_I3C_TARG_STATUS_TIMECTRL_SYNC (MXC_V_I3C_TARG_STATUS_TIMECTRL_SYNC << MXC_F_I3C_TARG_STATUS_TIMECTRL_POS) /**< TARG_STATUS_TIMECTRL_SYNC Setting */ +#define MXC_V_I3C_TARG_STATUS_TIMECTRL_ASYNC ((uint32_t)0x2UL) /**< TARG_STATUS_TIMECTRL_ASYNC Value */ +#define MXC_S_I3C_TARG_STATUS_TIMECTRL_ASYNC (MXC_V_I3C_TARG_STATUS_TIMECTRL_ASYNC << MXC_F_I3C_TARG_STATUS_TIMECTRL_POS) /**< TARG_STATUS_TIMECTRL_ASYNC Setting */ +#define MXC_V_I3C_TARG_STATUS_TIMECTRL_BOTH ((uint32_t)0x3UL) /**< TARG_STATUS_TIMECTRL_BOTH Value */ +#define MXC_S_I3C_TARG_STATUS_TIMECTRL_BOTH (MXC_V_I3C_TARG_STATUS_TIMECTRL_BOTH << MXC_F_I3C_TARG_STATUS_TIMECTRL_POS) /**< TARG_STATUS_TIMECTRL_BOTH Setting */ + +/**@} end of group I3C_TARG_STATUS_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_CTRL1 I3C_TARG_CTRL1 + * @brief Target Control 1 Register. + * @{ + */ +#define MXC_F_I3C_TARG_CTRL1_EVENT_POS 0 /**< TARG_CTRL1_EVENT Position */ +#define MXC_F_I3C_TARG_CTRL1_EVENT ((uint32_t)(0x3UL << MXC_F_I3C_TARG_CTRL1_EVENT_POS)) /**< TARG_CTRL1_EVENT Mask */ +#define MXC_V_I3C_TARG_CTRL1_EVENT_NORMAL ((uint32_t)0x0UL) /**< TARG_CTRL1_EVENT_NORMAL Value */ +#define MXC_S_I3C_TARG_CTRL1_EVENT_NORMAL (MXC_V_I3C_TARG_CTRL1_EVENT_NORMAL << MXC_F_I3C_TARG_CTRL1_EVENT_POS) /**< TARG_CTRL1_EVENT_NORMAL Setting */ +#define MXC_V_I3C_TARG_CTRL1_EVENT_IBI ((uint32_t)0x1UL) /**< TARG_CTRL1_EVENT_IBI Value */ +#define MXC_S_I3C_TARG_CTRL1_EVENT_IBI (MXC_V_I3C_TARG_CTRL1_EVENT_IBI << MXC_F_I3C_TARG_CTRL1_EVENT_POS) /**< TARG_CTRL1_EVENT_IBI Setting */ +#define MXC_V_I3C_TARG_CTRL1_EVENT_CONTREQ ((uint32_t)0x2UL) /**< TARG_CTRL1_EVENT_CONTREQ Value */ +#define MXC_S_I3C_TARG_CTRL1_EVENT_CONTREQ (MXC_V_I3C_TARG_CTRL1_EVENT_CONTREQ << MXC_F_I3C_TARG_CTRL1_EVENT_POS) /**< TARG_CTRL1_EVENT_CONTREQ Setting */ +#define MXC_V_I3C_TARG_CTRL1_EVENT_HJ ((uint32_t)0x3UL) /**< TARG_CTRL1_EVENT_HJ Value */ +#define MXC_S_I3C_TARG_CTRL1_EVENT_HJ (MXC_V_I3C_TARG_CTRL1_EVENT_HJ << MXC_F_I3C_TARG_CTRL1_EVENT_POS) /**< TARG_CTRL1_EVENT_HJ Setting */ + +#define MXC_F_I3C_TARG_CTRL1_EXTIBI_POS 3 /**< TARG_CTRL1_EXTIBI Position */ +#define MXC_F_I3C_TARG_CTRL1_EXTIBI ((uint32_t)(0x1UL << MXC_F_I3C_TARG_CTRL1_EXTIBI_POS)) /**< TARG_CTRL1_EXTIBI Mask */ + +#define MXC_F_I3C_TARG_CTRL1_DYNADDR_IDX_POS 4 /**< TARG_CTRL1_DYNADDR_IDX Position */ +#define MXC_F_I3C_TARG_CTRL1_DYNADDR_IDX ((uint32_t)(0xFUL << MXC_F_I3C_TARG_CTRL1_DYNADDR_IDX_POS)) /**< TARG_CTRL1_DYNADDR_IDX Mask */ + +#define MXC_F_I3C_TARG_CTRL1_IBIDATA_POS 8 /**< TARG_CTRL1_IBIDATA Position */ +#define MXC_F_I3C_TARG_CTRL1_IBIDATA ((uint32_t)(0xFFUL << MXC_F_I3C_TARG_CTRL1_IBIDATA_POS)) /**< TARG_CTRL1_IBIDATA Mask */ + +/**@} end of group I3C_TARG_CTRL1_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_INTEN I3C_TARG_INTEN + * @brief Target Interrupt Enable Register. + * @{ + */ +#define MXC_F_I3C_TARG_INTEN_START_POS 8 /**< TARG_INTEN_START Position */ +#define MXC_F_I3C_TARG_INTEN_START ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTEN_START_POS)) /**< TARG_INTEN_START Mask */ + +#define MXC_F_I3C_TARG_INTEN_ADDRMATCH_POS 9 /**< TARG_INTEN_ADDRMATCH Position */ +#define MXC_F_I3C_TARG_INTEN_ADDRMATCH ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTEN_ADDRMATCH_POS)) /**< TARG_INTEN_ADDRMATCH Mask */ + +#define MXC_F_I3C_TARG_INTEN_STOP_POS 10 /**< TARG_INTEN_STOP Position */ +#define MXC_F_I3C_TARG_INTEN_STOP ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTEN_STOP_POS)) /**< TARG_INTEN_STOP Mask */ + +#define MXC_F_I3C_TARG_INTEN_RX_RDY_POS 11 /**< TARG_INTEN_RX_RDY Position */ +#define MXC_F_I3C_TARG_INTEN_RX_RDY ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTEN_RX_RDY_POS)) /**< TARG_INTEN_RX_RDY Mask */ + +#define MXC_F_I3C_TARG_INTEN_TX_NFULL_POS 12 /**< TARG_INTEN_TX_NFULL Position */ +#define MXC_F_I3C_TARG_INTEN_TX_NFULL ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTEN_TX_NFULL_POS)) /**< TARG_INTEN_TX_NFULL Mask */ + +#define MXC_F_I3C_TARG_INTEN_DYNADDR_CHG_POS 13 /**< TARG_INTEN_DYNADDR_CHG Position */ +#define MXC_F_I3C_TARG_INTEN_DYNADDR_CHG ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTEN_DYNADDR_CHG_POS)) /**< TARG_INTEN_DYNADDR_CHG Mask */ + +#define MXC_F_I3C_TARG_INTEN_CCC_POS 14 /**< TARG_INTEN_CCC Position */ +#define MXC_F_I3C_TARG_INTEN_CCC ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTEN_CCC_POS)) /**< TARG_INTEN_CCC Mask */ + +#define MXC_F_I3C_TARG_INTEN_ERRWARN_POS 15 /**< TARG_INTEN_ERRWARN Position */ +#define MXC_F_I3C_TARG_INTEN_ERRWARN ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTEN_ERRWARN_POS)) /**< TARG_INTEN_ERRWARN Mask */ + +#define MXC_F_I3C_TARG_INTEN_CCCH_DONE_POS 17 /**< TARG_INTEN_CCCH_DONE Position */ +#define MXC_F_I3C_TARG_INTEN_CCCH_DONE ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTEN_CCCH_DONE_POS)) /**< TARG_INTEN_CCCH_DONE Mask */ + +#define MXC_F_I3C_TARG_INTEN_EVENT_REQ_POS 18 /**< TARG_INTEN_EVENT_REQ Position */ +#define MXC_F_I3C_TARG_INTEN_EVENT_REQ ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTEN_EVENT_REQ_POS)) /**< TARG_INTEN_EVENT_REQ Mask */ + +#define MXC_F_I3C_TARG_INTEN_TARG_RST_POS 19 /**< TARG_INTEN_TARG_RST Position */ +#define MXC_F_I3C_TARG_INTEN_TARG_RST ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTEN_TARG_RST_POS)) /**< TARG_INTEN_TARG_RST Mask */ + +/**@} end of group I3C_TARG_INTEN_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_INTCLR I3C_TARG_INTCLR + * @brief Target Interrupt Clear Register. + * @{ + */ +#define MXC_F_I3C_TARG_INTCLR_START_POS 8 /**< TARG_INTCLR_START Position */ +#define MXC_F_I3C_TARG_INTCLR_START ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTCLR_START_POS)) /**< TARG_INTCLR_START Mask */ + +#define MXC_F_I3C_TARG_INTCLR_ADDRMATCH_POS 9 /**< TARG_INTCLR_ADDRMATCH Position */ +#define MXC_F_I3C_TARG_INTCLR_ADDRMATCH ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTCLR_ADDRMATCH_POS)) /**< TARG_INTCLR_ADDRMATCH Mask */ + +#define MXC_F_I3C_TARG_INTCLR_STOP_POS 10 /**< TARG_INTCLR_STOP Position */ +#define MXC_F_I3C_TARG_INTCLR_STOP ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTCLR_STOP_POS)) /**< TARG_INTCLR_STOP Mask */ + +#define MXC_F_I3C_TARG_INTCLR_RX_RDY_POS 11 /**< TARG_INTCLR_RX_RDY Position */ +#define MXC_F_I3C_TARG_INTCLR_RX_RDY ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTCLR_RX_RDY_POS)) /**< TARG_INTCLR_RX_RDY Mask */ + +#define MXC_F_I3C_TARG_INTCLR_TX_NFULL_POS 12 /**< TARG_INTCLR_TX_NFULL Position */ +#define MXC_F_I3C_TARG_INTCLR_TX_NFULL ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTCLR_TX_NFULL_POS)) /**< TARG_INTCLR_TX_NFULL Mask */ + +#define MXC_F_I3C_TARG_INTCLR_DYNADDR_CHG_POS 13 /**< TARG_INTCLR_DYNADDR_CHG Position */ +#define MXC_F_I3C_TARG_INTCLR_DYNADDR_CHG ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTCLR_DYNADDR_CHG_POS)) /**< TARG_INTCLR_DYNADDR_CHG Mask */ + +#define MXC_F_I3C_TARG_INTCLR_CCC_POS 14 /**< TARG_INTCLR_CCC Position */ +#define MXC_F_I3C_TARG_INTCLR_CCC ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTCLR_CCC_POS)) /**< TARG_INTCLR_CCC Mask */ + +#define MXC_F_I3C_TARG_INTCLR_ERRWARN_POS 15 /**< TARG_INTCLR_ERRWARN Position */ +#define MXC_F_I3C_TARG_INTCLR_ERRWARN ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTCLR_ERRWARN_POS)) /**< TARG_INTCLR_ERRWARN Mask */ + +#define MXC_F_I3C_TARG_INTCLR_CCCH_DONE_POS 17 /**< TARG_INTCLR_CCCH_DONE Position */ +#define MXC_F_I3C_TARG_INTCLR_CCCH_DONE ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTCLR_CCCH_DONE_POS)) /**< TARG_INTCLR_CCCH_DONE Mask */ + +#define MXC_F_I3C_TARG_INTCLR_EVENT_REQ_POS 18 /**< TARG_INTCLR_EVENT_REQ Position */ +#define MXC_F_I3C_TARG_INTCLR_EVENT_REQ ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTCLR_EVENT_REQ_POS)) /**< TARG_INTCLR_EVENT_REQ Mask */ + +#define MXC_F_I3C_TARG_INTCLR_TARG_RST_POS 19 /**< TARG_INTCLR_TARG_RST Position */ +#define MXC_F_I3C_TARG_INTCLR_TARG_RST ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTCLR_TARG_RST_POS)) /**< TARG_INTCLR_TARG_RST Mask */ + +/**@} end of group I3C_TARG_INTCLR_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_INTFL I3C_TARG_INTFL + * @brief Target Interrupt Flag Register. + * @{ + */ +#define MXC_F_I3C_TARG_INTFL_START_POS 8 /**< TARG_INTFL_START Position */ +#define MXC_F_I3C_TARG_INTFL_START ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTFL_START_POS)) /**< TARG_INTFL_START Mask */ + +#define MXC_F_I3C_TARG_INTFL_ADDRMATCH_POS 9 /**< TARG_INTFL_ADDRMATCH Position */ +#define MXC_F_I3C_TARG_INTFL_ADDRMATCH ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTFL_ADDRMATCH_POS)) /**< TARG_INTFL_ADDRMATCH Mask */ + +#define MXC_F_I3C_TARG_INTFL_STOP_POS 10 /**< TARG_INTFL_STOP Position */ +#define MXC_F_I3C_TARG_INTFL_STOP ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTFL_STOP_POS)) /**< TARG_INTFL_STOP Mask */ + +#define MXC_F_I3C_TARG_INTFL_RX_RDY_POS 11 /**< TARG_INTFL_RX_RDY Position */ +#define MXC_F_I3C_TARG_INTFL_RX_RDY ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTFL_RX_RDY_POS)) /**< TARG_INTFL_RX_RDY Mask */ + +#define MXC_F_I3C_TARG_INTFL_TX_NFULL_POS 12 /**< TARG_INTFL_TX_NFULL Position */ +#define MXC_F_I3C_TARG_INTFL_TX_NFULL ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTFL_TX_NFULL_POS)) /**< TARG_INTFL_TX_NFULL Mask */ + +#define MXC_F_I3C_TARG_INTFL_DYNADDR_CHG_POS 13 /**< TARG_INTFL_DYNADDR_CHG Position */ +#define MXC_F_I3C_TARG_INTFL_DYNADDR_CHG ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTFL_DYNADDR_CHG_POS)) /**< TARG_INTFL_DYNADDR_CHG Mask */ + +#define MXC_F_I3C_TARG_INTFL_CCC_POS 14 /**< TARG_INTFL_CCC Position */ +#define MXC_F_I3C_TARG_INTFL_CCC ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTFL_CCC_POS)) /**< TARG_INTFL_CCC Mask */ + +#define MXC_F_I3C_TARG_INTFL_ERRWARN_POS 15 /**< TARG_INTFL_ERRWARN Position */ +#define MXC_F_I3C_TARG_INTFL_ERRWARN ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTFL_ERRWARN_POS)) /**< TARG_INTFL_ERRWARN Mask */ + +#define MXC_F_I3C_TARG_INTFL_CCCH_DONE_POS 17 /**< TARG_INTFL_CCCH_DONE Position */ +#define MXC_F_I3C_TARG_INTFL_CCCH_DONE ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTFL_CCCH_DONE_POS)) /**< TARG_INTFL_CCCH_DONE Mask */ + +#define MXC_F_I3C_TARG_INTFL_EVENT_REQ_POS 18 /**< TARG_INTFL_EVENT_REQ Position */ +#define MXC_F_I3C_TARG_INTFL_EVENT_REQ ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTFL_EVENT_REQ_POS)) /**< TARG_INTFL_EVENT_REQ Mask */ + +#define MXC_F_I3C_TARG_INTFL_TARG_RST_POS 19 /**< TARG_INTFL_TARG_RST Position */ +#define MXC_F_I3C_TARG_INTFL_TARG_RST ((uint32_t)(0x1UL << MXC_F_I3C_TARG_INTFL_TARG_RST_POS)) /**< TARG_INTFL_TARG_RST Mask */ + +/**@} end of group I3C_TARG_INTFL_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_ERRWARN I3C_TARG_ERRWARN + * @brief Target Error and Warning Register. + * @{ + */ +#define MXC_F_I3C_TARG_ERRWARN_OVR_POS 0 /**< TARG_ERRWARN_OVR Position */ +#define MXC_F_I3C_TARG_ERRWARN_OVR ((uint32_t)(0x1UL << MXC_F_I3C_TARG_ERRWARN_OVR_POS)) /**< TARG_ERRWARN_OVR Mask */ + +#define MXC_F_I3C_TARG_ERRWARN_UNR_POS 1 /**< TARG_ERRWARN_UNR Position */ +#define MXC_F_I3C_TARG_ERRWARN_UNR ((uint32_t)(0x1UL << MXC_F_I3C_TARG_ERRWARN_UNR_POS)) /**< TARG_ERRWARN_UNR Mask */ + +#define MXC_F_I3C_TARG_ERRWARN_UNR_NACK_POS 2 /**< TARG_ERRWARN_UNR_NACK Position */ +#define MXC_F_I3C_TARG_ERRWARN_UNR_NACK ((uint32_t)(0x1UL << MXC_F_I3C_TARG_ERRWARN_UNR_NACK_POS)) /**< TARG_ERRWARN_UNR_NACK Mask */ + +#define MXC_F_I3C_TARG_ERRWARN_CONT_RX_TERM_POS 3 /**< TARG_ERRWARN_CONT_RX_TERM Position */ +#define MXC_F_I3C_TARG_ERRWARN_CONT_RX_TERM ((uint32_t)(0x1UL << MXC_F_I3C_TARG_ERRWARN_CONT_RX_TERM_POS)) /**< TARG_ERRWARN_CONT_RX_TERM Mask */ + +#define MXC_F_I3C_TARG_ERRWARN_INVSTART_POS 4 /**< TARG_ERRWARN_INVSTART Position */ +#define MXC_F_I3C_TARG_ERRWARN_INVSTART ((uint32_t)(0x1UL << MXC_F_I3C_TARG_ERRWARN_INVSTART_POS)) /**< TARG_ERRWARN_INVSTART Mask */ + +#define MXC_F_I3C_TARG_ERRWARN_SDR_PAR_POS 8 /**< TARG_ERRWARN_SDR_PAR Position */ +#define MXC_F_I3C_TARG_ERRWARN_SDR_PAR ((uint32_t)(0x1UL << MXC_F_I3C_TARG_ERRWARN_SDR_PAR_POS)) /**< TARG_ERRWARN_SDR_PAR Mask */ + +#define MXC_F_I3C_TARG_ERRWARN_TO_POS 11 /**< TARG_ERRWARN_TO Position */ +#define MXC_F_I3C_TARG_ERRWARN_TO ((uint32_t)(0x1UL << MXC_F_I3C_TARG_ERRWARN_TO_POS)) /**< TARG_ERRWARN_TO Mask */ + +#define MXC_F_I3C_TARG_ERRWARN_RX_UNR_POS 16 /**< TARG_ERRWARN_RX_UNR Position */ +#define MXC_F_I3C_TARG_ERRWARN_RX_UNR ((uint32_t)(0x1UL << MXC_F_I3C_TARG_ERRWARN_RX_UNR_POS)) /**< TARG_ERRWARN_RX_UNR Mask */ + +#define MXC_F_I3C_TARG_ERRWARN_TX_OVR_POS 17 /**< TARG_ERRWARN_TX_OVR Position */ +#define MXC_F_I3C_TARG_ERRWARN_TX_OVR ((uint32_t)(0x1UL << MXC_F_I3C_TARG_ERRWARN_TX_OVR_POS)) /**< TARG_ERRWARN_TX_OVR Mask */ + +/**@} end of group I3C_TARG_ERRWARN_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_DMACTRL I3C_TARG_DMACTRL + * @brief Target DMA Control Register. + * @{ + */ +#define MXC_F_I3C_TARG_DMACTRL_RX_EN_POS 0 /**< TARG_DMACTRL_RX_EN Position */ +#define MXC_F_I3C_TARG_DMACTRL_RX_EN ((uint32_t)(0x3UL << MXC_F_I3C_TARG_DMACTRL_RX_EN_POS)) /**< TARG_DMACTRL_RX_EN Mask */ +#define MXC_V_I3C_TARG_DMACTRL_RX_EN_DIS ((uint32_t)0x0UL) /**< TARG_DMACTRL_RX_EN_DIS Value */ +#define MXC_S_I3C_TARG_DMACTRL_RX_EN_DIS (MXC_V_I3C_TARG_DMACTRL_RX_EN_DIS << MXC_F_I3C_TARG_DMACTRL_RX_EN_POS) /**< TARG_DMACTRL_RX_EN_DIS Setting */ +#define MXC_V_I3C_TARG_DMACTRL_RX_EN_ONE_FR ((uint32_t)0x1UL) /**< TARG_DMACTRL_RX_EN_ONE_FR Value */ +#define MXC_S_I3C_TARG_DMACTRL_RX_EN_ONE_FR (MXC_V_I3C_TARG_DMACTRL_RX_EN_ONE_FR << MXC_F_I3C_TARG_DMACTRL_RX_EN_POS) /**< TARG_DMACTRL_RX_EN_ONE_FR Setting */ +#define MXC_V_I3C_TARG_DMACTRL_RX_EN_EN ((uint32_t)0x2UL) /**< TARG_DMACTRL_RX_EN_EN Value */ +#define MXC_S_I3C_TARG_DMACTRL_RX_EN_EN (MXC_V_I3C_TARG_DMACTRL_RX_EN_EN << MXC_F_I3C_TARG_DMACTRL_RX_EN_POS) /**< TARG_DMACTRL_RX_EN_EN Setting */ + +#define MXC_F_I3C_TARG_DMACTRL_TX_EN_POS 2 /**< TARG_DMACTRL_TX_EN Position */ +#define MXC_F_I3C_TARG_DMACTRL_TX_EN ((uint32_t)(0x3UL << MXC_F_I3C_TARG_DMACTRL_TX_EN_POS)) /**< TARG_DMACTRL_TX_EN Mask */ +#define MXC_V_I3C_TARG_DMACTRL_TX_EN_DIS ((uint32_t)0x0UL) /**< TARG_DMACTRL_TX_EN_DIS Value */ +#define MXC_S_I3C_TARG_DMACTRL_TX_EN_DIS (MXC_V_I3C_TARG_DMACTRL_TX_EN_DIS << MXC_F_I3C_TARG_DMACTRL_TX_EN_POS) /**< TARG_DMACTRL_TX_EN_DIS Setting */ +#define MXC_V_I3C_TARG_DMACTRL_TX_EN_ONE_FR ((uint32_t)0x1UL) /**< TARG_DMACTRL_TX_EN_ONE_FR Value */ +#define MXC_S_I3C_TARG_DMACTRL_TX_EN_ONE_FR (MXC_V_I3C_TARG_DMACTRL_TX_EN_ONE_FR << MXC_F_I3C_TARG_DMACTRL_TX_EN_POS) /**< TARG_DMACTRL_TX_EN_ONE_FR Setting */ +#define MXC_V_I3C_TARG_DMACTRL_TX_EN_EN ((uint32_t)0x2UL) /**< TARG_DMACTRL_TX_EN_EN Value */ +#define MXC_S_I3C_TARG_DMACTRL_TX_EN_EN (MXC_V_I3C_TARG_DMACTRL_TX_EN_EN << MXC_F_I3C_TARG_DMACTRL_TX_EN_POS) /**< TARG_DMACTRL_TX_EN_EN Setting */ + +#define MXC_F_I3C_TARG_DMACTRL_WIDTH_POS 4 /**< TARG_DMACTRL_WIDTH Position */ +#define MXC_F_I3C_TARG_DMACTRL_WIDTH ((uint32_t)(0x3UL << MXC_F_I3C_TARG_DMACTRL_WIDTH_POS)) /**< TARG_DMACTRL_WIDTH Mask */ +#define MXC_V_I3C_TARG_DMACTRL_WIDTH_BYTE ((uint32_t)0x0UL) /**< TARG_DMACTRL_WIDTH_BYTE Value */ +#define MXC_S_I3C_TARG_DMACTRL_WIDTH_BYTE (MXC_V_I3C_TARG_DMACTRL_WIDTH_BYTE << MXC_F_I3C_TARG_DMACTRL_WIDTH_POS) /**< TARG_DMACTRL_WIDTH_BYTE Setting */ +#define MXC_V_I3C_TARG_DMACTRL_WIDTH_HALFWORD ((uint32_t)0x2UL) /**< TARG_DMACTRL_WIDTH_HALFWORD Value */ +#define MXC_S_I3C_TARG_DMACTRL_WIDTH_HALFWORD (MXC_V_I3C_TARG_DMACTRL_WIDTH_HALFWORD << MXC_F_I3C_TARG_DMACTRL_WIDTH_POS) /**< TARG_DMACTRL_WIDTH_HALFWORD Setting */ + +/**@} end of group I3C_TARG_DMACTRL_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_FIFOCTRL I3C_TARG_FIFOCTRL + * @brief Target FIFO Control Register. + * @{ + */ +#define MXC_F_I3C_TARG_FIFOCTRL_TX_FLUSH_POS 0 /**< TARG_FIFOCTRL_TX_FLUSH Position */ +#define MXC_F_I3C_TARG_FIFOCTRL_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_I3C_TARG_FIFOCTRL_TX_FLUSH_POS)) /**< TARG_FIFOCTRL_TX_FLUSH Mask */ + +#define MXC_F_I3C_TARG_FIFOCTRL_RX_FLUSH_POS 1 /**< TARG_FIFOCTRL_RX_FLUSH Position */ +#define MXC_F_I3C_TARG_FIFOCTRL_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_I3C_TARG_FIFOCTRL_RX_FLUSH_POS)) /**< TARG_FIFOCTRL_RX_FLUSH Mask */ + +#define MXC_F_I3C_TARG_FIFOCTRL_UNLOCK_POS 3 /**< TARG_FIFOCTRL_UNLOCK Position */ +#define MXC_F_I3C_TARG_FIFOCTRL_UNLOCK ((uint32_t)(0x1UL << MXC_F_I3C_TARG_FIFOCTRL_UNLOCK_POS)) /**< TARG_FIFOCTRL_UNLOCK Mask */ + +#define MXC_F_I3C_TARG_FIFOCTRL_TX_THD_LVL_POS 4 /**< TARG_FIFOCTRL_TX_THD_LVL Position */ +#define MXC_F_I3C_TARG_FIFOCTRL_TX_THD_LVL ((uint32_t)(0x3UL << MXC_F_I3C_TARG_FIFOCTRL_TX_THD_LVL_POS)) /**< TARG_FIFOCTRL_TX_THD_LVL Mask */ +#define MXC_V_I3C_TARG_FIFOCTRL_TX_THD_LVL_EMPTY ((uint32_t)0x0UL) /**< TARG_FIFOCTRL_TX_THD_LVL_EMPTY Value */ +#define MXC_S_I3C_TARG_FIFOCTRL_TX_THD_LVL_EMPTY (MXC_V_I3C_TARG_FIFOCTRL_TX_THD_LVL_EMPTY << MXC_F_I3C_TARG_FIFOCTRL_TX_THD_LVL_POS) /**< TARG_FIFOCTRL_TX_THD_LVL_EMPTY Setting */ +#define MXC_V_I3C_TARG_FIFOCTRL_TX_THD_LVL_QUARTER_FULL ((uint32_t)0x1UL) /**< TARG_FIFOCTRL_TX_THD_LVL_QUARTER_FULL Value */ +#define MXC_S_I3C_TARG_FIFOCTRL_TX_THD_LVL_QUARTER_FULL (MXC_V_I3C_TARG_FIFOCTRL_TX_THD_LVL_QUARTER_FULL << MXC_F_I3C_TARG_FIFOCTRL_TX_THD_LVL_POS) /**< TARG_FIFOCTRL_TX_THD_LVL_QUARTER_FULL Setting */ +#define MXC_V_I3C_TARG_FIFOCTRL_TX_THD_LVL_HALF_FULL ((uint32_t)0x2UL) /**< TARG_FIFOCTRL_TX_THD_LVL_HALF_FULL Value */ +#define MXC_S_I3C_TARG_FIFOCTRL_TX_THD_LVL_HALF_FULL (MXC_V_I3C_TARG_FIFOCTRL_TX_THD_LVL_HALF_FULL << MXC_F_I3C_TARG_FIFOCTRL_TX_THD_LVL_POS) /**< TARG_FIFOCTRL_TX_THD_LVL_HALF_FULL Setting */ +#define MXC_V_I3C_TARG_FIFOCTRL_TX_THD_LVL_ALMOST_FULL ((uint32_t)0x3UL) /**< TARG_FIFOCTRL_TX_THD_LVL_ALMOST_FULL Value */ +#define MXC_S_I3C_TARG_FIFOCTRL_TX_THD_LVL_ALMOST_FULL (MXC_V_I3C_TARG_FIFOCTRL_TX_THD_LVL_ALMOST_FULL << MXC_F_I3C_TARG_FIFOCTRL_TX_THD_LVL_POS) /**< TARG_FIFOCTRL_TX_THD_LVL_ALMOST_FULL Setting */ + +#define MXC_F_I3C_TARG_FIFOCTRL_RX_THD_LVL_POS 6 /**< TARG_FIFOCTRL_RX_THD_LVL Position */ +#define MXC_F_I3C_TARG_FIFOCTRL_RX_THD_LVL ((uint32_t)(0x3UL << MXC_F_I3C_TARG_FIFOCTRL_RX_THD_LVL_POS)) /**< TARG_FIFOCTRL_RX_THD_LVL Mask */ +#define MXC_V_I3C_TARG_FIFOCTRL_RX_THD_LVL_NOT_EMPTY ((uint32_t)0x0UL) /**< TARG_FIFOCTRL_RX_THD_LVL_NOT_EMPTY Value */ +#define MXC_S_I3C_TARG_FIFOCTRL_RX_THD_LVL_NOT_EMPTY (MXC_V_I3C_TARG_FIFOCTRL_RX_THD_LVL_NOT_EMPTY << MXC_F_I3C_TARG_FIFOCTRL_RX_THD_LVL_POS) /**< TARG_FIFOCTRL_RX_THD_LVL_NOT_EMPTY Setting */ +#define MXC_V_I3C_TARG_FIFOCTRL_RX_THD_LVL_QUARTER_FULL ((uint32_t)0x1UL) /**< TARG_FIFOCTRL_RX_THD_LVL_QUARTER_FULL Value */ +#define MXC_S_I3C_TARG_FIFOCTRL_RX_THD_LVL_QUARTER_FULL (MXC_V_I3C_TARG_FIFOCTRL_RX_THD_LVL_QUARTER_FULL << MXC_F_I3C_TARG_FIFOCTRL_RX_THD_LVL_POS) /**< TARG_FIFOCTRL_RX_THD_LVL_QUARTER_FULL Setting */ +#define MXC_V_I3C_TARG_FIFOCTRL_RX_THD_LVL_HALF_FULL ((uint32_t)0x2UL) /**< TARG_FIFOCTRL_RX_THD_LVL_HALF_FULL Value */ +#define MXC_S_I3C_TARG_FIFOCTRL_RX_THD_LVL_HALF_FULL (MXC_V_I3C_TARG_FIFOCTRL_RX_THD_LVL_HALF_FULL << MXC_F_I3C_TARG_FIFOCTRL_RX_THD_LVL_POS) /**< TARG_FIFOCTRL_RX_THD_LVL_HALF_FULL Setting */ +#define MXC_V_I3C_TARG_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL ((uint32_t)0x3UL) /**< TARG_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL Value */ +#define MXC_S_I3C_TARG_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL (MXC_V_I3C_TARG_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL << MXC_F_I3C_TARG_FIFOCTRL_RX_THD_LVL_POS) /**< TARG_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL Setting */ + +#define MXC_F_I3C_TARG_FIFOCTRL_TX_LVL_POS 16 /**< TARG_FIFOCTRL_TX_LVL Position */ +#define MXC_F_I3C_TARG_FIFOCTRL_TX_LVL ((uint32_t)(0x3FUL << MXC_F_I3C_TARG_FIFOCTRL_TX_LVL_POS)) /**< TARG_FIFOCTRL_TX_LVL Mask */ + +#define MXC_F_I3C_TARG_FIFOCTRL_RX_LVL_POS 24 /**< TARG_FIFOCTRL_RX_LVL Position */ +#define MXC_F_I3C_TARG_FIFOCTRL_RX_LVL ((uint32_t)(0x3FUL << MXC_F_I3C_TARG_FIFOCTRL_RX_LVL_POS)) /**< TARG_FIFOCTRL_RX_LVL Mask */ + +#define MXC_F_I3C_TARG_FIFOCTRL_TX_FULL_POS 30 /**< TARG_FIFOCTRL_TX_FULL Position */ +#define MXC_F_I3C_TARG_FIFOCTRL_TX_FULL ((uint32_t)(0x1UL << MXC_F_I3C_TARG_FIFOCTRL_TX_FULL_POS)) /**< TARG_FIFOCTRL_TX_FULL Mask */ + +#define MXC_F_I3C_TARG_FIFOCTRL_RX_EM_POS 31 /**< TARG_FIFOCTRL_RX_EM Position */ +#define MXC_F_I3C_TARG_FIFOCTRL_RX_EM ((uint32_t)(0x1UL << MXC_F_I3C_TARG_FIFOCTRL_RX_EM_POS)) /**< TARG_FIFOCTRL_RX_EM Mask */ + +/**@} end of group I3C_TARG_FIFOCTRL_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_TXFIFO8 I3C_TARG_TXFIFO8 + * @brief Target Write Byte Data Register. + * @{ + */ +#define MXC_F_I3C_TARG_TXFIFO8_DATA_POS 0 /**< TARG_TXFIFO8_DATA Position */ +#define MXC_F_I3C_TARG_TXFIFO8_DATA ((uint32_t)(0xFFUL << MXC_F_I3C_TARG_TXFIFO8_DATA_POS)) /**< TARG_TXFIFO8_DATA Mask */ + +#define MXC_F_I3C_TARG_TXFIFO8_END_POS 8 /**< TARG_TXFIFO8_END Position */ +#define MXC_F_I3C_TARG_TXFIFO8_END ((uint32_t)(0x1UL << MXC_F_I3C_TARG_TXFIFO8_END_POS)) /**< TARG_TXFIFO8_END Mask */ + +#define MXC_F_I3C_TARG_TXFIFO8_END2_POS 16 /**< TARG_TXFIFO8_END2 Position */ +#define MXC_F_I3C_TARG_TXFIFO8_END2 ((uint32_t)(0x1UL << MXC_F_I3C_TARG_TXFIFO8_END2_POS)) /**< TARG_TXFIFO8_END2 Mask */ + +/**@} end of group I3C_TARG_TXFIFO8_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_TXFIFO8E I3C_TARG_TXFIFO8E + * @brief Target Write Byte Data as End Register. + * @{ + */ +#define MXC_F_I3C_TARG_TXFIFO8E_DATA_POS 0 /**< TARG_TXFIFO8E_DATA Position */ +#define MXC_F_I3C_TARG_TXFIFO8E_DATA ((uint32_t)(0xFFUL << MXC_F_I3C_TARG_TXFIFO8E_DATA_POS)) /**< TARG_TXFIFO8E_DATA Mask */ + +/**@} end of group I3C_TARG_TXFIFO8E_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_TXFIFO16 I3C_TARG_TXFIFO16 + * @brief Target Write Half-Word Data Register. + * @{ + */ +#define MXC_F_I3C_TARG_TXFIFO16_DATA_POS 0 /**< TARG_TXFIFO16_DATA Position */ +#define MXC_F_I3C_TARG_TXFIFO16_DATA ((uint32_t)(0xFFFFUL << MXC_F_I3C_TARG_TXFIFO16_DATA_POS)) /**< TARG_TXFIFO16_DATA Mask */ + +#define MXC_F_I3C_TARG_TXFIFO16_END_POS 16 /**< TARG_TXFIFO16_END Position */ +#define MXC_F_I3C_TARG_TXFIFO16_END ((uint32_t)(0x1UL << MXC_F_I3C_TARG_TXFIFO16_END_POS)) /**< TARG_TXFIFO16_END Mask */ + +/**@} end of group I3C_TARG_TXFIFO16_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_TXFIFO16E I3C_TARG_TXFIFO16E + * @brief Target Write Half-Word Data as End Register. + * @{ + */ +#define MXC_F_I3C_TARG_TXFIFO16E_DATA_POS 0 /**< TARG_TXFIFO16E_DATA Position */ +#define MXC_F_I3C_TARG_TXFIFO16E_DATA ((uint32_t)(0xFFFFUL << MXC_F_I3C_TARG_TXFIFO16E_DATA_POS)) /**< TARG_TXFIFO16E_DATA Mask */ + +/**@} end of group I3C_TARG_TXFIFO16E_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_RXFIFO8 I3C_TARG_RXFIFO8 + * @brief Target Read Byte Data Register. + * @{ + */ +#define MXC_F_I3C_TARG_RXFIFO8_DATA_POS 0 /**< TARG_RXFIFO8_DATA Position */ +#define MXC_F_I3C_TARG_RXFIFO8_DATA ((uint32_t)(0xFFUL << MXC_F_I3C_TARG_RXFIFO8_DATA_POS)) /**< TARG_RXFIFO8_DATA Mask */ + +/**@} end of group I3C_TARG_RXFIFO8_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_RXFIFO16 I3C_TARG_RXFIFO16 + * @brief Target Read Half-Word Data Register. + * @{ + */ +#define MXC_F_I3C_TARG_RXFIFO16_DATA_POS 0 /**< TARG_RXFIFO16_DATA Position */ +#define MXC_F_I3C_TARG_RXFIFO16_DATA ((uint32_t)(0xFFFFUL << MXC_F_I3C_TARG_RXFIFO16_DATA_POS)) /**< TARG_RXFIFO16_DATA Mask */ + +/**@} end of group I3C_TARG_RXFIFO16_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_TXFIFO8O I3C_TARG_TXFIFO8O + * @brief Target Byte-Only Write Byte Data Register. + * @{ + */ +#define MXC_F_I3C_TARG_TXFIFO8O_DATA_POS 0 /**< TARG_TXFIFO8O_DATA Position */ +#define MXC_F_I3C_TARG_TXFIFO8O_DATA ((uint32_t)(0xFFUL << MXC_F_I3C_TARG_TXFIFO8O_DATA_POS)) /**< TARG_TXFIFO8O_DATA Mask */ + +/**@} end of group I3C_TARG_TXFIFO8O_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_CAP0 I3C_TARG_CAP0 + * @brief Target Capabilities 0 Register. + * @{ + */ +#define MXC_F_I3C_TARG_CAP0_MAPCNT_POS 0 /**< TARG_CAP0_MAPCNT Position */ +#define MXC_F_I3C_TARG_CAP0_MAPCNT ((uint32_t)(0xFUL << MXC_F_I3C_TARG_CAP0_MAPCNT_POS)) /**< TARG_CAP0_MAPCNT Mask */ + +#define MXC_F_I3C_TARG_CAP0_I2C_10BADDR_POS 4 /**< TARG_CAP0_I2C_10BADDR Position */ +#define MXC_F_I3C_TARG_CAP0_I2C_10BADDR ((uint32_t)(0x1UL << MXC_F_I3C_TARG_CAP0_I2C_10BADDR_POS)) /**< TARG_CAP0_I2C_10BADDR Mask */ + +#define MXC_F_I3C_TARG_CAP0_I2C_SWRST_POS 5 /**< TARG_CAP0_I2C_SWRST Position */ +#define MXC_F_I3C_TARG_CAP0_I2C_SWRST ((uint32_t)(0x1UL << MXC_F_I3C_TARG_CAP0_I2C_SWRST_POS)) /**< TARG_CAP0_I2C_SWRST Mask */ + +#define MXC_F_I3C_TARG_CAP0_I2C_DEVID_POS 6 /**< TARG_CAP0_I2C_DEVID Position */ +#define MXC_F_I3C_TARG_CAP0_I2C_DEVID ((uint32_t)(0x1UL << MXC_F_I3C_TARG_CAP0_I2C_DEVID_POS)) /**< TARG_CAP0_I2C_DEVID Mask */ + +#define MXC_F_I3C_TARG_CAP0_FIFO32_REG_POS 7 /**< TARG_CAP0_FIFO32_REG Position */ +#define MXC_F_I3C_TARG_CAP0_FIFO32_REG ((uint32_t)(0x1UL << MXC_F_I3C_TARG_CAP0_FIFO32_REG_POS)) /**< TARG_CAP0_FIFO32_REG Mask */ + +#define MXC_F_I3C_TARG_CAP0_EXTIBI_POS 8 /**< TARG_CAP0_EXTIBI Position */ +#define MXC_F_I3C_TARG_CAP0_EXTIBI ((uint32_t)(0x1UL << MXC_F_I3C_TARG_CAP0_EXTIBI_POS)) /**< TARG_CAP0_EXTIBI Mask */ + +#define MXC_F_I3C_TARG_CAP0_EXTIBI_REG_POS 9 /**< TARG_CAP0_EXTIBI_REG Position */ +#define MXC_F_I3C_TARG_CAP0_EXTIBI_REG ((uint32_t)(0x1UL << MXC_F_I3C_TARG_CAP0_EXTIBI_REG_POS)) /**< TARG_CAP0_EXTIBI_REG Mask */ + +#define MXC_F_I3C_TARG_CAP0_HDRBT_LANES_POS 12 /**< TARG_CAP0_HDRBT_LANES Position */ +#define MXC_F_I3C_TARG_CAP0_HDRBT_LANES ((uint32_t)(0x3UL << MXC_F_I3C_TARG_CAP0_HDRBT_LANES_POS)) /**< TARG_CAP0_HDRBT_LANES Mask */ + +#define MXC_F_I3C_TARG_CAP0_CCC_V1_1_POS 16 /**< TARG_CAP0_CCC_V1_1 Position */ +#define MXC_F_I3C_TARG_CAP0_CCC_V1_1 ((uint32_t)(0x1UL << MXC_F_I3C_TARG_CAP0_CCC_V1_1_POS)) /**< TARG_CAP0_CCC_V1_1 Mask */ + +#define MXC_F_I3C_TARG_CAP0_TARG_RST_POS 17 /**< TARG_CAP0_TARG_RST Position */ +#define MXC_F_I3C_TARG_CAP0_TARG_RST ((uint32_t)(0x1UL << MXC_F_I3C_TARG_CAP0_TARG_RST_POS)) /**< TARG_CAP0_TARG_RST Mask */ + +#define MXC_F_I3C_TARG_CAP0_GROUPADDR_POS 18 /**< TARG_CAP0_GROUPADDR Position */ +#define MXC_F_I3C_TARG_CAP0_GROUPADDR ((uint32_t)(0x3UL << MXC_F_I3C_TARG_CAP0_GROUPADDR_POS)) /**< TARG_CAP0_GROUPADDR Mask */ + +#define MXC_F_I3C_TARG_CAP0_AASA_CCC_POS 21 /**< TARG_CAP0_AASA_CCC Position */ +#define MXC_F_I3C_TARG_CAP0_AASA_CCC ((uint32_t)(0x1UL << MXC_F_I3C_TARG_CAP0_AASA_CCC_POS)) /**< TARG_CAP0_AASA_CCC Mask */ + +#define MXC_F_I3C_TARG_CAP0_T2T_SUBSC_POS 22 /**< TARG_CAP0_T2T_SUBSC Position */ +#define MXC_F_I3C_TARG_CAP0_T2T_SUBSC ((uint32_t)(0x1UL << MXC_F_I3C_TARG_CAP0_T2T_SUBSC_POS)) /**< TARG_CAP0_T2T_SUBSC Mask */ + +#define MXC_F_I3C_TARG_CAP0_T2T_WR_POS 23 /**< TARG_CAP0_T2T_WR Position */ +#define MXC_F_I3C_TARG_CAP0_T2T_WR ((uint32_t)(0x1UL << MXC_F_I3C_TARG_CAP0_T2T_WR_POS)) /**< TARG_CAP0_T2T_WR Mask */ + +/**@} end of group I3C_TARG_CAP0_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_CAP1 I3C_TARG_CAP1 + * @brief TARG_Capabilities 1 Register. + * @{ + */ +#define MXC_F_I3C_TARG_CAP1_PROVID_POS 0 /**< TARG_CAP1_PROVID Position */ +#define MXC_F_I3C_TARG_CAP1_PROVID ((uint32_t)(0x3UL << MXC_F_I3C_TARG_CAP1_PROVID_POS)) /**< TARG_CAP1_PROVID Mask */ + +#define MXC_F_I3C_TARG_CAP1_PROVID_REG_POS 2 /**< TARG_CAP1_PROVID_REG Position */ +#define MXC_F_I3C_TARG_CAP1_PROVID_REG ((uint32_t)(0xFUL << MXC_F_I3C_TARG_CAP1_PROVID_REG_POS)) /**< TARG_CAP1_PROVID_REG Mask */ + +#define MXC_F_I3C_TARG_CAP1_HDR_MODES_POS 6 /**< TARG_CAP1_HDR_MODES Position */ +#define MXC_F_I3C_TARG_CAP1_HDR_MODES ((uint32_t)(0x7UL << MXC_F_I3C_TARG_CAP1_HDR_MODES_POS)) /**< TARG_CAP1_HDR_MODES Mask */ + +#define MXC_F_I3C_TARG_CAP1_CONT_POS 9 /**< TARG_CAP1_CONT Position */ +#define MXC_F_I3C_TARG_CAP1_CONT ((uint32_t)(0x1UL << MXC_F_I3C_TARG_CAP1_CONT_POS)) /**< TARG_CAP1_CONT Mask */ + +#define MXC_F_I3C_TARG_CAP1_STATADDR_POS 10 /**< TARG_CAP1_STATADDR Position */ +#define MXC_F_I3C_TARG_CAP1_STATADDR ((uint32_t)(0x3UL << MXC_F_I3C_TARG_CAP1_STATADDR_POS)) /**< TARG_CAP1_STATADDR Mask */ + +#define MXC_F_I3C_TARG_CAP1_CCCH_POS 12 /**< TARG_CAP1_CCCH Position */ +#define MXC_F_I3C_TARG_CAP1_CCCH ((uint32_t)(0xFUL << MXC_F_I3C_TARG_CAP1_CCCH_POS)) /**< TARG_CAP1_CCCH Mask */ + +#define MXC_F_I3C_TARG_CAP1_IBI_EVENTS_POS 16 /**< TARG_CAP1_IBI_EVENTS Position */ +#define MXC_F_I3C_TARG_CAP1_IBI_EVENTS ((uint32_t)(0x1FUL << MXC_F_I3C_TARG_CAP1_IBI_EVENTS_POS)) /**< TARG_CAP1_IBI_EVENTS Mask */ + +#define MXC_F_I3C_TARG_CAP1_TIMECTRL_POS 21 /**< TARG_CAP1_TIMECTRL Position */ +#define MXC_F_I3C_TARG_CAP1_TIMECTRL ((uint32_t)(0x1UL << MXC_F_I3C_TARG_CAP1_TIMECTRL_POS)) /**< TARG_CAP1_TIMECTRL Mask */ + +#define MXC_F_I3C_TARG_CAP1_EXTFIFO_POS 23 /**< TARG_CAP1_EXTFIFO Position */ +#define MXC_F_I3C_TARG_CAP1_EXTFIFO ((uint32_t)(0x7UL << MXC_F_I3C_TARG_CAP1_EXTFIFO_POS)) /**< TARG_CAP1_EXTFIFO Mask */ + +#define MXC_F_I3C_TARG_CAP1_TXFIFO_CFG_POS 26 /**< TARG_CAP1_TXFIFO_CFG Position */ +#define MXC_F_I3C_TARG_CAP1_TXFIFO_CFG ((uint32_t)(0x3UL << MXC_F_I3C_TARG_CAP1_TXFIFO_CFG_POS)) /**< TARG_CAP1_TXFIFO_CFG Mask */ + +#define MXC_F_I3C_TARG_CAP1_RXFIFO_CFG_POS 28 /**< TARG_CAP1_RXFIFO_CFG Position */ +#define MXC_F_I3C_TARG_CAP1_RXFIFO_CFG ((uint32_t)(0x3UL << MXC_F_I3C_TARG_CAP1_RXFIFO_CFG_POS)) /**< TARG_CAP1_RXFIFO_CFG Mask */ + +#define MXC_F_I3C_TARG_CAP1_INTR_POS 30 /**< TARG_CAP1_INTR Position */ +#define MXC_F_I3C_TARG_CAP1_INTR ((uint32_t)(0x1UL << MXC_F_I3C_TARG_CAP1_INTR_POS)) /**< TARG_CAP1_INTR Mask */ + +#define MXC_F_I3C_TARG_CAP1_DMA_POS 31 /**< TARG_CAP1_DMA Position */ +#define MXC_F_I3C_TARG_CAP1_DMA ((uint32_t)(0x1UL << MXC_F_I3C_TARG_CAP1_DMA_POS)) /**< TARG_CAP1_DMA Mask */ + +/**@} end of group I3C_TARG_CAP1_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_DYNADDR I3C_TARG_DYNADDR + * @brief Target Dynamic Address Register. + * @{ + */ +#define MXC_F_I3C_TARG_DYNADDR_VALID_POS 0 /**< TARG_DYNADDR_VALID Position */ +#define MXC_F_I3C_TARG_DYNADDR_VALID ((uint32_t)(0x1UL << MXC_F_I3C_TARG_DYNADDR_VALID_POS)) /**< TARG_DYNADDR_VALID Mask */ + +#define MXC_F_I3C_TARG_DYNADDR_ADDR_POS 1 /**< TARG_DYNADDR_ADDR Position */ +#define MXC_F_I3C_TARG_DYNADDR_ADDR ((uint32_t)(0x7FUL << MXC_F_I3C_TARG_DYNADDR_ADDR_POS)) /**< TARG_DYNADDR_ADDR Mask */ + +#define MXC_F_I3C_TARG_DYNADDR_CAUSE_POS 8 /**< TARG_DYNADDR_CAUSE Position */ +#define MXC_F_I3C_TARG_DYNADDR_CAUSE ((uint32_t)(0x7UL << MXC_F_I3C_TARG_DYNADDR_CAUSE_POS)) /**< TARG_DYNADDR_CAUSE Mask */ + +/**@} end of group I3C_TARG_DYNADDR_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_MAXLIMITS I3C_TARG_MAXLIMITS + * @brief Maximum Limits Register. + * @{ + */ +#define MXC_F_I3C_TARG_MAXLIMITS_RX_POS 0 /**< TARG_MAXLIMITS_RX Position */ +#define MXC_F_I3C_TARG_MAXLIMITS_RX ((uint32_t)(0xFFFUL << MXC_F_I3C_TARG_MAXLIMITS_RX_POS)) /**< TARG_MAXLIMITS_RX Mask */ + +#define MXC_F_I3C_TARG_MAXLIMITS_TX_POS 16 /**< TARG_MAXLIMITS_TX Position */ +#define MXC_F_I3C_TARG_MAXLIMITS_TX ((uint32_t)(0xFFFUL << MXC_F_I3C_TARG_MAXLIMITS_TX_POS)) /**< TARG_MAXLIMITS_TX Mask */ + +/**@} end of group I3C_TARG_MAXLIMITS_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_IDEXT I3C_TARG_IDEXT + * @brief ID Extension Register. + * @{ + */ +#define MXC_F_I3C_TARG_IDEXT_DEVCHAR_POS 8 /**< TARG_IDEXT_DEVCHAR Position */ +#define MXC_F_I3C_TARG_IDEXT_DEVCHAR ((uint32_t)(0xFFUL << MXC_F_I3C_TARG_IDEXT_DEVCHAR_POS)) /**< TARG_IDEXT_DEVCHAR Mask */ + +#define MXC_F_I3C_TARG_IDEXT_BUSCHAR_POS 16 /**< TARG_IDEXT_BUSCHAR Position */ +#define MXC_F_I3C_TARG_IDEXT_BUSCHAR ((uint32_t)(0xFFUL << MXC_F_I3C_TARG_IDEXT_BUSCHAR_POS)) /**< TARG_IDEXT_BUSCHAR Mask */ + +/**@} end of group I3C_TARG_IDEXT_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_MSGLAST I3C_TARG_MSGLAST + * @brief Target Matching Address Index Register. + * @{ + */ +#define MXC_F_I3C_TARG_MSGLAST_IDX_POS 0 /**< TARG_MSGLAST_IDX Position */ +#define MXC_F_I3C_TARG_MSGLAST_IDX ((uint32_t)(0xFUL << MXC_F_I3C_TARG_MSGLAST_IDX_POS)) /**< TARG_MSGLAST_IDX Mask */ + +#define MXC_F_I3C_TARG_MSGLAST_STATADDR_POS 4 /**< TARG_MSGLAST_STATADDR Position */ +#define MXC_F_I3C_TARG_MSGLAST_STATADDR ((uint32_t)(0x1UL << MXC_F_I3C_TARG_MSGLAST_STATADDR_POS)) /**< TARG_MSGLAST_STATADDR Mask */ + +#define MXC_F_I3C_TARG_MSGLAST_GROUP_POS 5 /**< TARG_MSGLAST_GROUP Position */ +#define MXC_F_I3C_TARG_MSGLAST_GROUP ((uint32_t)(0x1UL << MXC_F_I3C_TARG_MSGLAST_GROUP_POS)) /**< TARG_MSGLAST_GROUP Mask */ + +#define MXC_F_I3C_TARG_MSGLAST_MODE_POS 6 /**< TARG_MSGLAST_MODE Position */ +#define MXC_F_I3C_TARG_MSGLAST_MODE ((uint32_t)(0x3UL << MXC_F_I3C_TARG_MSGLAST_MODE_POS)) /**< TARG_MSGLAST_MODE Mask */ +#define MXC_V_I3C_TARG_MSGLAST_MODE_DYN_STAT_ADDR ((uint32_t)0x0UL) /**< TARG_MSGLAST_MODE_DYN_STAT_ADDR Value */ +#define MXC_S_I3C_TARG_MSGLAST_MODE_DYN_STAT_ADDR (MXC_V_I3C_TARG_MSGLAST_MODE_DYN_STAT_ADDR << MXC_F_I3C_TARG_MSGLAST_MODE_POS) /**< TARG_MSGLAST_MODE_DYN_STAT_ADDR Setting */ +#define MXC_V_I3C_TARG_MSGLAST_MODE_HDR_DDR ((uint32_t)0x1UL) /**< TARG_MSGLAST_MODE_HDR_DDR Value */ +#define MXC_S_I3C_TARG_MSGLAST_MODE_HDR_DDR (MXC_V_I3C_TARG_MSGLAST_MODE_HDR_DDR << MXC_F_I3C_TARG_MSGLAST_MODE_POS) /**< TARG_MSGLAST_MODE_HDR_DDR Setting */ +#define MXC_V_I3C_TARG_MSGLAST_MODE_HDR_BT ((uint32_t)0x2UL) /**< TARG_MSGLAST_MODE_HDR_BT Value */ +#define MXC_S_I3C_TARG_MSGLAST_MODE_HDR_BT (MXC_V_I3C_TARG_MSGLAST_MODE_HDR_BT << MXC_F_I3C_TARG_MSGLAST_MODE_POS) /**< TARG_MSGLAST_MODE_HDR_BT Setting */ + +#define MXC_F_I3C_TARG_MSGLAST_PREV_IDX_POS 8 /**< TARG_MSGLAST_PREV_IDX Position */ +#define MXC_F_I3C_TARG_MSGLAST_PREV_IDX ((uint32_t)(0xFUL << MXC_F_I3C_TARG_MSGLAST_PREV_IDX_POS)) /**< TARG_MSGLAST_PREV_IDX Mask */ + +#define MXC_F_I3C_TARG_MSGLAST_PREV_GROUP_POS 13 /**< TARG_MSGLAST_PREV_GROUP Position */ +#define MXC_F_I3C_TARG_MSGLAST_PREV_GROUP ((uint32_t)(0x1UL << MXC_F_I3C_TARG_MSGLAST_PREV_GROUP_POS)) /**< TARG_MSGLAST_PREV_GROUP Mask */ + +#define MXC_F_I3C_TARG_MSGLAST_PREV_MODE_POS 14 /**< TARG_MSGLAST_PREV_MODE Position */ +#define MXC_F_I3C_TARG_MSGLAST_PREV_MODE ((uint32_t)(0x3UL << MXC_F_I3C_TARG_MSGLAST_PREV_MODE_POS)) /**< TARG_MSGLAST_PREV_MODE Mask */ +#define MXC_V_I3C_TARG_MSGLAST_PREV_MODE_DYN_STAT_ADDR ((uint32_t)0x0UL) /**< TARG_MSGLAST_PREV_MODE_DYN_STAT_ADDR Value */ +#define MXC_S_I3C_TARG_MSGLAST_PREV_MODE_DYN_STAT_ADDR (MXC_V_I3C_TARG_MSGLAST_PREV_MODE_DYN_STAT_ADDR << MXC_F_I3C_TARG_MSGLAST_PREV_MODE_POS) /**< TARG_MSGLAST_PREV_MODE_DYN_STAT_ADDR Setting */ +#define MXC_V_I3C_TARG_MSGLAST_PREV_MODE_HDR_DDR ((uint32_t)0x1UL) /**< TARG_MSGLAST_PREV_MODE_HDR_DDR Value */ +#define MXC_S_I3C_TARG_MSGLAST_PREV_MODE_HDR_DDR (MXC_V_I3C_TARG_MSGLAST_PREV_MODE_HDR_DDR << MXC_F_I3C_TARG_MSGLAST_PREV_MODE_POS) /**< TARG_MSGLAST_PREV_MODE_HDR_DDR Setting */ +#define MXC_V_I3C_TARG_MSGLAST_PREV_MODE_HDR_BT ((uint32_t)0x2UL) /**< TARG_MSGLAST_PREV_MODE_HDR_BT Value */ +#define MXC_S_I3C_TARG_MSGLAST_PREV_MODE_HDR_BT (MXC_V_I3C_TARG_MSGLAST_PREV_MODE_HDR_BT << MXC_F_I3C_TARG_MSGLAST_PREV_MODE_POS) /**< TARG_MSGLAST_PREV_MODE_HDR_BT Setting */ + +#define MXC_F_I3C_TARG_MSGLAST_SECPREV_IDX_POS 16 /**< TARG_MSGLAST_SECPREV_IDX Position */ +#define MXC_F_I3C_TARG_MSGLAST_SECPREV_IDX ((uint32_t)(0xFUL << MXC_F_I3C_TARG_MSGLAST_SECPREV_IDX_POS)) /**< TARG_MSGLAST_SECPREV_IDX Mask */ + +#define MXC_F_I3C_TARG_MSGLAST_SECPREV_GROUP_POS 21 /**< TARG_MSGLAST_SECPREV_GROUP Position */ +#define MXC_F_I3C_TARG_MSGLAST_SECPREV_GROUP ((uint32_t)(0x1UL << MXC_F_I3C_TARG_MSGLAST_SECPREV_GROUP_POS)) /**< TARG_MSGLAST_SECPREV_GROUP Mask */ + +#define MXC_F_I3C_TARG_MSGLAST_SECPREV_MODE_POS 22 /**< TARG_MSGLAST_SECPREV_MODE Position */ +#define MXC_F_I3C_TARG_MSGLAST_SECPREV_MODE ((uint32_t)(0x3UL << MXC_F_I3C_TARG_MSGLAST_SECPREV_MODE_POS)) /**< TARG_MSGLAST_SECPREV_MODE Mask */ +#define MXC_V_I3C_TARG_MSGLAST_SECPREV_MODE_DYN_STAT_ADDR ((uint32_t)0x0UL) /**< TARG_MSGLAST_SECPREV_MODE_DYN_STAT_ADDR Value */ +#define MXC_S_I3C_TARG_MSGLAST_SECPREV_MODE_DYN_STAT_ADDR (MXC_V_I3C_TARG_MSGLAST_SECPREV_MODE_DYN_STAT_ADDR << MXC_F_I3C_TARG_MSGLAST_SECPREV_MODE_POS) /**< TARG_MSGLAST_SECPREV_MODE_DYN_STAT_ADDR Setting */ +#define MXC_V_I3C_TARG_MSGLAST_SECPREV_MODE_HDR_DDR ((uint32_t)0x1UL) /**< TARG_MSGLAST_SECPREV_MODE_HDR_DDR Value */ +#define MXC_S_I3C_TARG_MSGLAST_SECPREV_MODE_HDR_DDR (MXC_V_I3C_TARG_MSGLAST_SECPREV_MODE_HDR_DDR << MXC_F_I3C_TARG_MSGLAST_SECPREV_MODE_POS) /**< TARG_MSGLAST_SECPREV_MODE_HDR_DDR Setting */ +#define MXC_V_I3C_TARG_MSGLAST_SECPREV_MODE_HDR_BT ((uint32_t)0x2UL) /**< TARG_MSGLAST_SECPREV_MODE_HDR_BT Value */ +#define MXC_S_I3C_TARG_MSGLAST_SECPREV_MODE_HDR_BT (MXC_V_I3C_TARG_MSGLAST_SECPREV_MODE_HDR_BT << MXC_F_I3C_TARG_MSGLAST_SECPREV_MODE_POS) /**< TARG_MSGLAST_SECPREV_MODE_HDR_BT Setting */ + +/**@} end of group I3C_TARG_MSGLAST_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_CTRL1 I3C_CONT_CTRL1 + * @brief Controller Control 1 Register. + * @{ + */ +#define MXC_F_I3C_CONT_CTRL1_REQ_POS 0 /**< CONT_CTRL1_REQ Position */ +#define MXC_F_I3C_CONT_CTRL1_REQ ((uint32_t)(0x7UL << MXC_F_I3C_CONT_CTRL1_REQ_POS)) /**< CONT_CTRL1_REQ Mask */ +#define MXC_V_I3C_CONT_CTRL1_REQ_NONE ((uint32_t)0x0UL) /**< CONT_CTRL1_REQ_NONE Value */ +#define MXC_S_I3C_CONT_CTRL1_REQ_NONE (MXC_V_I3C_CONT_CTRL1_REQ_NONE << MXC_F_I3C_CONT_CTRL1_REQ_POS) /**< CONT_CTRL1_REQ_NONE Setting */ +#define MXC_V_I3C_CONT_CTRL1_REQ_EMIT_START ((uint32_t)0x1UL) /**< CONT_CTRL1_REQ_EMIT_START Value */ +#define MXC_S_I3C_CONT_CTRL1_REQ_EMIT_START (MXC_V_I3C_CONT_CTRL1_REQ_EMIT_START << MXC_F_I3C_CONT_CTRL1_REQ_POS) /**< CONT_CTRL1_REQ_EMIT_START Setting */ +#define MXC_V_I3C_CONT_CTRL1_REQ_EMIT_STOP ((uint32_t)0x2UL) /**< CONT_CTRL1_REQ_EMIT_STOP Value */ +#define MXC_S_I3C_CONT_CTRL1_REQ_EMIT_STOP (MXC_V_I3C_CONT_CTRL1_REQ_EMIT_STOP << MXC_F_I3C_CONT_CTRL1_REQ_POS) /**< CONT_CTRL1_REQ_EMIT_STOP Setting */ +#define MXC_V_I3C_CONT_CTRL1_REQ_IBI_ACKNACK ((uint32_t)0x3UL) /**< CONT_CTRL1_REQ_IBI_ACKNACK Value */ +#define MXC_S_I3C_CONT_CTRL1_REQ_IBI_ACKNACK (MXC_V_I3C_CONT_CTRL1_REQ_IBI_ACKNACK << MXC_F_I3C_CONT_CTRL1_REQ_POS) /**< CONT_CTRL1_REQ_IBI_ACKNACK Setting */ +#define MXC_V_I3C_CONT_CTRL1_REQ_PROCESS_DAA ((uint32_t)0x4UL) /**< CONT_CTRL1_REQ_PROCESS_DAA Value */ +#define MXC_S_I3C_CONT_CTRL1_REQ_PROCESS_DAA (MXC_V_I3C_CONT_CTRL1_REQ_PROCESS_DAA << MXC_F_I3C_CONT_CTRL1_REQ_POS) /**< CONT_CTRL1_REQ_PROCESS_DAA Setting */ +#define MXC_V_I3C_CONT_CTRL1_REQ_EXIT_RST ((uint32_t)0x6UL) /**< CONT_CTRL1_REQ_EXIT_RST Value */ +#define MXC_S_I3C_CONT_CTRL1_REQ_EXIT_RST (MXC_V_I3C_CONT_CTRL1_REQ_EXIT_RST << MXC_F_I3C_CONT_CTRL1_REQ_POS) /**< CONT_CTRL1_REQ_EXIT_RST Setting */ +#define MXC_V_I3C_CONT_CTRL1_REQ_AUTO_IBI ((uint32_t)0x7UL) /**< CONT_CTRL1_REQ_AUTO_IBI Value */ +#define MXC_S_I3C_CONT_CTRL1_REQ_AUTO_IBI (MXC_V_I3C_CONT_CTRL1_REQ_AUTO_IBI << MXC_F_I3C_CONT_CTRL1_REQ_POS) /**< CONT_CTRL1_REQ_AUTO_IBI Setting */ + +#define MXC_F_I3C_CONT_CTRL1_TYPE_POS 4 /**< CONT_CTRL1_TYPE Position */ +#define MXC_F_I3C_CONT_CTRL1_TYPE ((uint32_t)(0x3UL << MXC_F_I3C_CONT_CTRL1_TYPE_POS)) /**< CONT_CTRL1_TYPE Mask */ + +#define MXC_F_I3C_CONT_CTRL1_IBIRESP_POS 6 /**< CONT_CTRL1_IBIRESP Position */ +#define MXC_F_I3C_CONT_CTRL1_IBIRESP ((uint32_t)(0x3UL << MXC_F_I3C_CONT_CTRL1_IBIRESP_POS)) /**< CONT_CTRL1_IBIRESP Mask */ + +#define MXC_F_I3C_CONT_CTRL1_RDWR_DIR_POS 8 /**< CONT_CTRL1_RDWR_DIR Position */ +#define MXC_F_I3C_CONT_CTRL1_RDWR_DIR ((uint32_t)(0x1UL << MXC_F_I3C_CONT_CTRL1_RDWR_DIR_POS)) /**< CONT_CTRL1_RDWR_DIR Mask */ + +#define MXC_F_I3C_CONT_CTRL1_ADDR_POS 9 /**< CONT_CTRL1_ADDR Position */ +#define MXC_F_I3C_CONT_CTRL1_ADDR ((uint32_t)(0x7FUL << MXC_F_I3C_CONT_CTRL1_ADDR_POS)) /**< CONT_CTRL1_ADDR Mask */ + +#define MXC_F_I3C_CONT_CTRL1_TERM_RD_POS 16 /**< CONT_CTRL1_TERM_RD Position */ +#define MXC_F_I3C_CONT_CTRL1_TERM_RD ((uint32_t)(0xFFUL << MXC_F_I3C_CONT_CTRL1_TERM_RD_POS)) /**< CONT_CTRL1_TERM_RD Mask */ + +/**@} end of group I3C_CONT_CTRL1_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_STATUS I3C_CONT_STATUS + * @brief Controller Status Register. + * @{ + */ +#define MXC_F_I3C_CONT_STATUS_STATE_POS 0 /**< CONT_STATUS_STATE Position */ +#define MXC_F_I3C_CONT_STATUS_STATE ((uint32_t)(0x7UL << MXC_F_I3C_CONT_STATUS_STATE_POS)) /**< CONT_STATUS_STATE Mask */ +#define MXC_V_I3C_CONT_STATUS_STATE_IDLE ((uint32_t)0x0UL) /**< CONT_STATUS_STATE_IDLE Value */ +#define MXC_S_I3C_CONT_STATUS_STATE_IDLE (MXC_V_I3C_CONT_STATUS_STATE_IDLE << MXC_F_I3C_CONT_STATUS_STATE_POS) /**< CONT_STATUS_STATE_IDLE Setting */ +#define MXC_V_I3C_CONT_STATUS_STATE_TARG_REQ ((uint32_t)0x1UL) /**< CONT_STATUS_STATE_TARG_REQ Value */ +#define MXC_S_I3C_CONT_STATUS_STATE_TARG_REQ (MXC_V_I3C_CONT_STATUS_STATE_TARG_REQ << MXC_F_I3C_CONT_STATUS_STATE_POS) /**< CONT_STATUS_STATE_TARG_REQ Setting */ +#define MXC_V_I3C_CONT_STATUS_STATE_SDR_TXSDRMSG ((uint32_t)0x2UL) /**< CONT_STATUS_STATE_SDR_TXSDRMSG Value */ +#define MXC_S_I3C_CONT_STATUS_STATE_SDR_TXSDRMSG (MXC_V_I3C_CONT_STATUS_STATE_SDR_TXSDRMSG << MXC_F_I3C_CONT_STATUS_STATE_POS) /**< CONT_STATUS_STATE_SDR_TXSDRMSG Setting */ +#define MXC_V_I3C_CONT_STATUS_STATE_SDR_NORM ((uint32_t)0x3UL) /**< CONT_STATUS_STATE_SDR_NORM Value */ +#define MXC_S_I3C_CONT_STATUS_STATE_SDR_NORM (MXC_V_I3C_CONT_STATUS_STATE_SDR_NORM << MXC_F_I3C_CONT_STATUS_STATE_POS) /**< CONT_STATUS_STATE_SDR_NORM Setting */ +#define MXC_V_I3C_CONT_STATUS_STATE_DDR ((uint32_t)0x4UL) /**< CONT_STATUS_STATE_DDR Value */ +#define MXC_S_I3C_CONT_STATUS_STATE_DDR (MXC_V_I3C_CONT_STATUS_STATE_DDR << MXC_F_I3C_CONT_STATUS_STATE_POS) /**< CONT_STATUS_STATE_DDR Setting */ +#define MXC_V_I3C_CONT_STATUS_STATE_DAA ((uint32_t)0x5UL) /**< CONT_STATUS_STATE_DAA Value */ +#define MXC_S_I3C_CONT_STATUS_STATE_DAA (MXC_V_I3C_CONT_STATUS_STATE_DAA << MXC_F_I3C_CONT_STATUS_STATE_POS) /**< CONT_STATUS_STATE_DAA Setting */ +#define MXC_V_I3C_CONT_STATUS_STATE_IBI_ACKNACK ((uint32_t)0x6UL) /**< CONT_STATUS_STATE_IBI_ACKNACK Value */ +#define MXC_S_I3C_CONT_STATUS_STATE_IBI_ACKNACK (MXC_V_I3C_CONT_STATUS_STATE_IBI_ACKNACK << MXC_F_I3C_CONT_STATUS_STATE_POS) /**< CONT_STATUS_STATE_IBI_ACKNACK Setting */ +#define MXC_V_I3C_CONT_STATUS_STATE_IBI_RX ((uint32_t)0x7UL) /**< CONT_STATUS_STATE_IBI_RX Value */ +#define MXC_S_I3C_CONT_STATUS_STATE_IBI_RX (MXC_V_I3C_CONT_STATUS_STATE_IBI_RX << MXC_F_I3C_CONT_STATUS_STATE_POS) /**< CONT_STATUS_STATE_IBI_RX Setting */ + +#define MXC_F_I3C_CONT_STATUS_WAIT_POS 4 /**< CONT_STATUS_WAIT Position */ +#define MXC_F_I3C_CONT_STATUS_WAIT ((uint32_t)(0x1UL << MXC_F_I3C_CONT_STATUS_WAIT_POS)) /**< CONT_STATUS_WAIT Mask */ + +#define MXC_F_I3C_CONT_STATUS_NACK_POS 5 /**< CONT_STATUS_NACK Position */ +#define MXC_F_I3C_CONT_STATUS_NACK ((uint32_t)(0x1UL << MXC_F_I3C_CONT_STATUS_NACK_POS)) /**< CONT_STATUS_NACK Mask */ + +#define MXC_F_I3C_CONT_STATUS_IBITYPE_POS 6 /**< CONT_STATUS_IBITYPE Position */ +#define MXC_F_I3C_CONT_STATUS_IBITYPE ((uint32_t)(0x3UL << MXC_F_I3C_CONT_STATUS_IBITYPE_POS)) /**< CONT_STATUS_IBITYPE Mask */ +#define MXC_V_I3C_CONT_STATUS_IBITYPE_NONE ((uint32_t)0x0UL) /**< CONT_STATUS_IBITYPE_NONE Value */ +#define MXC_S_I3C_CONT_STATUS_IBITYPE_NONE (MXC_V_I3C_CONT_STATUS_IBITYPE_NONE << MXC_F_I3C_CONT_STATUS_IBITYPE_POS) /**< CONT_STATUS_IBITYPE_NONE Setting */ +#define MXC_V_I3C_CONT_STATUS_IBITYPE_IBI ((uint32_t)0x1UL) /**< CONT_STATUS_IBITYPE_IBI Value */ +#define MXC_S_I3C_CONT_STATUS_IBITYPE_IBI (MXC_V_I3C_CONT_STATUS_IBITYPE_IBI << MXC_F_I3C_CONT_STATUS_IBITYPE_POS) /**< CONT_STATUS_IBITYPE_IBI Setting */ +#define MXC_V_I3C_CONT_STATUS_IBITYPE_CONT_REQ ((uint32_t)0x1UL) /**< CONT_STATUS_IBITYPE_CONT_REQ Value */ +#define MXC_S_I3C_CONT_STATUS_IBITYPE_CONT_REQ (MXC_V_I3C_CONT_STATUS_IBITYPE_CONT_REQ << MXC_F_I3C_CONT_STATUS_IBITYPE_POS) /**< CONT_STATUS_IBITYPE_CONT_REQ Setting */ +#define MXC_V_I3C_CONT_STATUS_IBITYPE_HOTJOIN_REQ ((uint32_t)0x1UL) /**< CONT_STATUS_IBITYPE_HOTJOIN_REQ Value */ +#define MXC_S_I3C_CONT_STATUS_IBITYPE_HOTJOIN_REQ (MXC_V_I3C_CONT_STATUS_IBITYPE_HOTJOIN_REQ << MXC_F_I3C_CONT_STATUS_IBITYPE_POS) /**< CONT_STATUS_IBITYPE_HOTJOIN_REQ Setting */ + +#define MXC_F_I3C_CONT_STATUS_TARG_START_POS 8 /**< CONT_STATUS_TARG_START Position */ +#define MXC_F_I3C_CONT_STATUS_TARG_START ((uint32_t)(0x1UL << MXC_F_I3C_CONT_STATUS_TARG_START_POS)) /**< CONT_STATUS_TARG_START Mask */ + +#define MXC_F_I3C_CONT_STATUS_REQ_DONE_POS 9 /**< CONT_STATUS_REQ_DONE Position */ +#define MXC_F_I3C_CONT_STATUS_REQ_DONE ((uint32_t)(0x1UL << MXC_F_I3C_CONT_STATUS_REQ_DONE_POS)) /**< CONT_STATUS_REQ_DONE Mask */ + +#define MXC_F_I3C_CONT_STATUS_DONE_POS 10 /**< CONT_STATUS_DONE Position */ +#define MXC_F_I3C_CONT_STATUS_DONE ((uint32_t)(0x1UL << MXC_F_I3C_CONT_STATUS_DONE_POS)) /**< CONT_STATUS_DONE Mask */ + +#define MXC_F_I3C_CONT_STATUS_RX_RDY_POS 11 /**< CONT_STATUS_RX_RDY Position */ +#define MXC_F_I3C_CONT_STATUS_RX_RDY ((uint32_t)(0x1UL << MXC_F_I3C_CONT_STATUS_RX_RDY_POS)) /**< CONT_STATUS_RX_RDY Mask */ + +#define MXC_F_I3C_CONT_STATUS_TX_NFULL_POS 12 /**< CONT_STATUS_TX_NFULL Position */ +#define MXC_F_I3C_CONT_STATUS_TX_NFULL ((uint32_t)(0x1UL << MXC_F_I3C_CONT_STATUS_TX_NFULL_POS)) /**< CONT_STATUS_TX_NFULL Mask */ + +#define MXC_F_I3C_CONT_STATUS_IBI_WON_POS 13 /**< CONT_STATUS_IBI_WON Position */ +#define MXC_F_I3C_CONT_STATUS_IBI_WON ((uint32_t)(0x1UL << MXC_F_I3C_CONT_STATUS_IBI_WON_POS)) /**< CONT_STATUS_IBI_WON Mask */ + +#define MXC_F_I3C_CONT_STATUS_ERRWARN_POS 15 /**< CONT_STATUS_ERRWARN Position */ +#define MXC_F_I3C_CONT_STATUS_ERRWARN ((uint32_t)(0x1UL << MXC_F_I3C_CONT_STATUS_ERRWARN_POS)) /**< CONT_STATUS_ERRWARN Mask */ + +#define MXC_F_I3C_CONT_STATUS_CONT_TRANS_POS 19 /**< CONT_STATUS_CONT_TRANS Position */ +#define MXC_F_I3C_CONT_STATUS_CONT_TRANS ((uint32_t)(0x1UL << MXC_F_I3C_CONT_STATUS_CONT_TRANS_POS)) /**< CONT_STATUS_CONT_TRANS Mask */ + +#define MXC_F_I3C_CONT_STATUS_IBI_ADDR_POS 24 /**< CONT_STATUS_IBI_ADDR Position */ +#define MXC_F_I3C_CONT_STATUS_IBI_ADDR ((uint32_t)(0x7FUL << MXC_F_I3C_CONT_STATUS_IBI_ADDR_POS)) /**< CONT_STATUS_IBI_ADDR Mask */ + +/**@} end of group I3C_CONT_STATUS_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_IBIRULES I3C_CONT_IBIRULES + * @brief Controller IBI Registry and Rules Register. + * @{ + */ +#define MXC_F_I3C_CONT_IBIRULES_ADDR0_POS 0 /**< CONT_IBIRULES_ADDR0 Position */ +#define MXC_F_I3C_CONT_IBIRULES_ADDR0 ((uint32_t)(0x3FUL << MXC_F_I3C_CONT_IBIRULES_ADDR0_POS)) /**< CONT_IBIRULES_ADDR0 Mask */ + +#define MXC_F_I3C_CONT_IBIRULES_ADDR1_POS 6 /**< CONT_IBIRULES_ADDR1 Position */ +#define MXC_F_I3C_CONT_IBIRULES_ADDR1 ((uint32_t)(0x3FUL << MXC_F_I3C_CONT_IBIRULES_ADDR1_POS)) /**< CONT_IBIRULES_ADDR1 Mask */ + +#define MXC_F_I3C_CONT_IBIRULES_ADDR2_POS 12 /**< CONT_IBIRULES_ADDR2 Position */ +#define MXC_F_I3C_CONT_IBIRULES_ADDR2 ((uint32_t)(0x3FUL << MXC_F_I3C_CONT_IBIRULES_ADDR2_POS)) /**< CONT_IBIRULES_ADDR2 Mask */ + +#define MXC_F_I3C_CONT_IBIRULES_ADDR3_POS 18 /**< CONT_IBIRULES_ADDR3 Position */ +#define MXC_F_I3C_CONT_IBIRULES_ADDR3 ((uint32_t)(0x3FUL << MXC_F_I3C_CONT_IBIRULES_ADDR3_POS)) /**< CONT_IBIRULES_ADDR3 Mask */ + +#define MXC_F_I3C_CONT_IBIRULES_ADDR4_POS 24 /**< CONT_IBIRULES_ADDR4 Position */ +#define MXC_F_I3C_CONT_IBIRULES_ADDR4 ((uint32_t)(0x3FUL << MXC_F_I3C_CONT_IBIRULES_ADDR4_POS)) /**< CONT_IBIRULES_ADDR4 Mask */ + +#define MXC_F_I3C_CONT_IBIRULES_MSB0_POS 30 /**< CONT_IBIRULES_MSB0 Position */ +#define MXC_F_I3C_CONT_IBIRULES_MSB0 ((uint32_t)(0x1UL << MXC_F_I3C_CONT_IBIRULES_MSB0_POS)) /**< CONT_IBIRULES_MSB0 Mask */ + +#define MXC_F_I3C_CONT_IBIRULES_NOBYTE_POS 31 /**< CONT_IBIRULES_NOBYTE Position */ +#define MXC_F_I3C_CONT_IBIRULES_NOBYTE ((uint32_t)(0x1UL << MXC_F_I3C_CONT_IBIRULES_NOBYTE_POS)) /**< CONT_IBIRULES_NOBYTE Mask */ + +/**@} end of group I3C_CONT_IBIRULES_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_INTEN I3C_CONT_INTEN + * @brief Controller Interrupt Enable Register. + * @{ + */ +#define MXC_F_I3C_CONT_INTEN_TARG_START_POS 8 /**< CONT_INTEN_TARG_START Position */ +#define MXC_F_I3C_CONT_INTEN_TARG_START ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTEN_TARG_START_POS)) /**< CONT_INTEN_TARG_START Mask */ + +#define MXC_F_I3C_CONT_INTEN_REQ_DONE_POS 9 /**< CONT_INTEN_REQ_DONE Position */ +#define MXC_F_I3C_CONT_INTEN_REQ_DONE ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTEN_REQ_DONE_POS)) /**< CONT_INTEN_REQ_DONE Mask */ + +#define MXC_F_I3C_CONT_INTEN_DONE_POS 10 /**< CONT_INTEN_DONE Position */ +#define MXC_F_I3C_CONT_INTEN_DONE ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTEN_DONE_POS)) /**< CONT_INTEN_DONE Mask */ + +#define MXC_F_I3C_CONT_INTEN_RX_RDY_POS 11 /**< CONT_INTEN_RX_RDY Position */ +#define MXC_F_I3C_CONT_INTEN_RX_RDY ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTEN_RX_RDY_POS)) /**< CONT_INTEN_RX_RDY Mask */ + +#define MXC_F_I3C_CONT_INTEN_TX_NFULL_POS 12 /**< CONT_INTEN_TX_NFULL Position */ +#define MXC_F_I3C_CONT_INTEN_TX_NFULL ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTEN_TX_NFULL_POS)) /**< CONT_INTEN_TX_NFULL Mask */ + +#define MXC_F_I3C_CONT_INTEN_IBI_WON_POS 13 /**< CONT_INTEN_IBI_WON Position */ +#define MXC_F_I3C_CONT_INTEN_IBI_WON ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTEN_IBI_WON_POS)) /**< CONT_INTEN_IBI_WON Mask */ + +#define MXC_F_I3C_CONT_INTEN_ERRWARN_POS 15 /**< CONT_INTEN_ERRWARN Position */ +#define MXC_F_I3C_CONT_INTEN_ERRWARN ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTEN_ERRWARN_POS)) /**< CONT_INTEN_ERRWARN Mask */ + +#define MXC_F_I3C_CONT_INTEN_NOW_CONT_POS 19 /**< CONT_INTEN_NOW_CONT Position */ +#define MXC_F_I3C_CONT_INTEN_NOW_CONT ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTEN_NOW_CONT_POS)) /**< CONT_INTEN_NOW_CONT Mask */ + +/**@} end of group I3C_CONT_INTEN_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_INTCLR I3C_CONT_INTCLR + * @brief Controller Interrupt Clear Register. + * @{ + */ +#define MXC_F_I3C_CONT_INTCLR_TARG_START_POS 8 /**< CONT_INTCLR_TARG_START Position */ +#define MXC_F_I3C_CONT_INTCLR_TARG_START ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTCLR_TARG_START_POS)) /**< CONT_INTCLR_TARG_START Mask */ + +#define MXC_F_I3C_CONT_INTCLR_REQ_DONE_POS 9 /**< CONT_INTCLR_REQ_DONE Position */ +#define MXC_F_I3C_CONT_INTCLR_REQ_DONE ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTCLR_REQ_DONE_POS)) /**< CONT_INTCLR_REQ_DONE Mask */ + +#define MXC_F_I3C_CONT_INTCLR_DONE_POS 10 /**< CONT_INTCLR_DONE Position */ +#define MXC_F_I3C_CONT_INTCLR_DONE ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTCLR_DONE_POS)) /**< CONT_INTCLR_DONE Mask */ + +#define MXC_F_I3C_CONT_INTCLR_RX_RDY_POS 11 /**< CONT_INTCLR_RX_RDY Position */ +#define MXC_F_I3C_CONT_INTCLR_RX_RDY ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTCLR_RX_RDY_POS)) /**< CONT_INTCLR_RX_RDY Mask */ + +#define MXC_F_I3C_CONT_INTCLR_TX_NFULL_POS 12 /**< CONT_INTCLR_TX_NFULL Position */ +#define MXC_F_I3C_CONT_INTCLR_TX_NFULL ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTCLR_TX_NFULL_POS)) /**< CONT_INTCLR_TX_NFULL Mask */ + +#define MXC_F_I3C_CONT_INTCLR_IBI_WON_POS 13 /**< CONT_INTCLR_IBI_WON Position */ +#define MXC_F_I3C_CONT_INTCLR_IBI_WON ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTCLR_IBI_WON_POS)) /**< CONT_INTCLR_IBI_WON Mask */ + +#define MXC_F_I3C_CONT_INTCLR_ERRWARN_POS 15 /**< CONT_INTCLR_ERRWARN Position */ +#define MXC_F_I3C_CONT_INTCLR_ERRWARN ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTCLR_ERRWARN_POS)) /**< CONT_INTCLR_ERRWARN Mask */ + +#define MXC_F_I3C_CONT_INTCLR_NOW_CONT_POS 19 /**< CONT_INTCLR_NOW_CONT Position */ +#define MXC_F_I3C_CONT_INTCLR_NOW_CONT ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTCLR_NOW_CONT_POS)) /**< CONT_INTCLR_NOW_CONT Mask */ + +/**@} end of group I3C_CONT_INTCLR_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_INTFL I3C_CONT_INTFL + * @brief Controller Interrupt Flag Register. + * @{ + */ +#define MXC_F_I3C_CONT_INTFL_TARG_START_POS 8 /**< CONT_INTFL_TARG_START Position */ +#define MXC_F_I3C_CONT_INTFL_TARG_START ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTFL_TARG_START_POS)) /**< CONT_INTFL_TARG_START Mask */ + +#define MXC_F_I3C_CONT_INTFL_REQ_DONE_POS 9 /**< CONT_INTFL_REQ_DONE Position */ +#define MXC_F_I3C_CONT_INTFL_REQ_DONE ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTFL_REQ_DONE_POS)) /**< CONT_INTFL_REQ_DONE Mask */ + +#define MXC_F_I3C_CONT_INTFL_DONE_POS 10 /**< CONT_INTFL_DONE Position */ +#define MXC_F_I3C_CONT_INTFL_DONE ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTFL_DONE_POS)) /**< CONT_INTFL_DONE Mask */ + +#define MXC_F_I3C_CONT_INTFL_RX_RDY_POS 11 /**< CONT_INTFL_RX_RDY Position */ +#define MXC_F_I3C_CONT_INTFL_RX_RDY ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTFL_RX_RDY_POS)) /**< CONT_INTFL_RX_RDY Mask */ + +#define MXC_F_I3C_CONT_INTFL_TX_NFULL_POS 12 /**< CONT_INTFL_TX_NFULL Position */ +#define MXC_F_I3C_CONT_INTFL_TX_NFULL ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTFL_TX_NFULL_POS)) /**< CONT_INTFL_TX_NFULL Mask */ + +#define MXC_F_I3C_CONT_INTFL_IBI_WON_POS 13 /**< CONT_INTFL_IBI_WON Position */ +#define MXC_F_I3C_CONT_INTFL_IBI_WON ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTFL_IBI_WON_POS)) /**< CONT_INTFL_IBI_WON Mask */ + +#define MXC_F_I3C_CONT_INTFL_ERRWARN_POS 15 /**< CONT_INTFL_ERRWARN Position */ +#define MXC_F_I3C_CONT_INTFL_ERRWARN ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTFL_ERRWARN_POS)) /**< CONT_INTFL_ERRWARN Mask */ + +#define MXC_F_I3C_CONT_INTFL_NOW_CONT_POS 19 /**< CONT_INTFL_NOW_CONT Position */ +#define MXC_F_I3C_CONT_INTFL_NOW_CONT ((uint32_t)(0x1UL << MXC_F_I3C_CONT_INTFL_NOW_CONT_POS)) /**< CONT_INTFL_NOW_CONT Mask */ + +/**@} end of group I3C_CONT_INTFL_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_ERRWARN I3C_CONT_ERRWARN + * @brief Controller Error and Warning Register. + * @{ + */ +#define MXC_F_I3C_CONT_ERRWARN_NACK_POS 2 /**< CONT_ERRWARN_NACK Position */ +#define MXC_F_I3C_CONT_ERRWARN_NACK ((uint32_t)(0x1UL << MXC_F_I3C_CONT_ERRWARN_NACK_POS)) /**< CONT_ERRWARN_NACK Mask */ + +#define MXC_F_I3C_CONT_ERRWARN_TX_ABT_POS 3 /**< CONT_ERRWARN_TX_ABT Position */ +#define MXC_F_I3C_CONT_ERRWARN_TX_ABT ((uint32_t)(0x1UL << MXC_F_I3C_CONT_ERRWARN_TX_ABT_POS)) /**< CONT_ERRWARN_TX_ABT Mask */ + +#define MXC_F_I3C_CONT_ERRWARN_RX_TERM_POS 4 /**< CONT_ERRWARN_RX_TERM Position */ +#define MXC_F_I3C_CONT_ERRWARN_RX_TERM ((uint32_t)(0x1UL << MXC_F_I3C_CONT_ERRWARN_RX_TERM_POS)) /**< CONT_ERRWARN_RX_TERM Mask */ + +#define MXC_F_I3C_CONT_ERRWARN_HDR_PAR_POS 9 /**< CONT_ERRWARN_HDR_PAR Position */ +#define MXC_F_I3C_CONT_ERRWARN_HDR_PAR ((uint32_t)(0x1UL << MXC_F_I3C_CONT_ERRWARN_HDR_PAR_POS)) /**< CONT_ERRWARN_HDR_PAR Mask */ + +#define MXC_F_I3C_CONT_ERRWARN_HDR_CRC_POS 10 /**< CONT_ERRWARN_HDR_CRC Position */ +#define MXC_F_I3C_CONT_ERRWARN_HDR_CRC ((uint32_t)(0x1UL << MXC_F_I3C_CONT_ERRWARN_HDR_CRC_POS)) /**< CONT_ERRWARN_HDR_CRC Mask */ + +#define MXC_F_I3C_CONT_ERRWARN_RX_UNR_POS 16 /**< CONT_ERRWARN_RX_UNR Position */ +#define MXC_F_I3C_CONT_ERRWARN_RX_UNR ((uint32_t)(0x1UL << MXC_F_I3C_CONT_ERRWARN_RX_UNR_POS)) /**< CONT_ERRWARN_RX_UNR Mask */ + +#define MXC_F_I3C_CONT_ERRWARN_TX_OVR_POS 17 /**< CONT_ERRWARN_TX_OVR Position */ +#define MXC_F_I3C_CONT_ERRWARN_TX_OVR ((uint32_t)(0x1UL << MXC_F_I3C_CONT_ERRWARN_TX_OVR_POS)) /**< CONT_ERRWARN_TX_OVR Mask */ + +#define MXC_F_I3C_CONT_ERRWARN_MSG_POS 18 /**< CONT_ERRWARN_MSG Position */ +#define MXC_F_I3C_CONT_ERRWARN_MSG ((uint32_t)(0x1UL << MXC_F_I3C_CONT_ERRWARN_MSG_POS)) /**< CONT_ERRWARN_MSG Mask */ + +#define MXC_F_I3C_CONT_ERRWARN_INV_REQ_POS 19 /**< CONT_ERRWARN_INV_REQ Position */ +#define MXC_F_I3C_CONT_ERRWARN_INV_REQ ((uint32_t)(0x1UL << MXC_F_I3C_CONT_ERRWARN_INV_REQ_POS)) /**< CONT_ERRWARN_INV_REQ Mask */ + +#define MXC_F_I3C_CONT_ERRWARN_TO_POS 20 /**< CONT_ERRWARN_TO Position */ +#define MXC_F_I3C_CONT_ERRWARN_TO ((uint32_t)(0x1UL << MXC_F_I3C_CONT_ERRWARN_TO_POS)) /**< CONT_ERRWARN_TO Mask */ + +/**@} end of group I3C_CONT_ERRWARN_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_DMACTRL I3C_CONT_DMACTRL + * @brief Controller DMA Control Register. + * @{ + */ +#define MXC_F_I3C_CONT_DMACTRL_RX_EN_POS 0 /**< CONT_DMACTRL_RX_EN Position */ +#define MXC_F_I3C_CONT_DMACTRL_RX_EN ((uint32_t)(0x3UL << MXC_F_I3C_CONT_DMACTRL_RX_EN_POS)) /**< CONT_DMACTRL_RX_EN Mask */ +#define MXC_V_I3C_CONT_DMACTRL_RX_EN_DIS ((uint32_t)0x0UL) /**< CONT_DMACTRL_RX_EN_DIS Value */ +#define MXC_S_I3C_CONT_DMACTRL_RX_EN_DIS (MXC_V_I3C_CONT_DMACTRL_RX_EN_DIS << MXC_F_I3C_CONT_DMACTRL_RX_EN_POS) /**< CONT_DMACTRL_RX_EN_DIS Setting */ +#define MXC_V_I3C_CONT_DMACTRL_RX_EN_ONE_FR ((uint32_t)0x1UL) /**< CONT_DMACTRL_RX_EN_ONE_FR Value */ +#define MXC_S_I3C_CONT_DMACTRL_RX_EN_ONE_FR (MXC_V_I3C_CONT_DMACTRL_RX_EN_ONE_FR << MXC_F_I3C_CONT_DMACTRL_RX_EN_POS) /**< CONT_DMACTRL_RX_EN_ONE_FR Setting */ +#define MXC_V_I3C_CONT_DMACTRL_RX_EN_EN ((uint32_t)0x2UL) /**< CONT_DMACTRL_RX_EN_EN Value */ +#define MXC_S_I3C_CONT_DMACTRL_RX_EN_EN (MXC_V_I3C_CONT_DMACTRL_RX_EN_EN << MXC_F_I3C_CONT_DMACTRL_RX_EN_POS) /**< CONT_DMACTRL_RX_EN_EN Setting */ + +#define MXC_F_I3C_CONT_DMACTRL_TX_EN_POS 2 /**< CONT_DMACTRL_TX_EN Position */ +#define MXC_F_I3C_CONT_DMACTRL_TX_EN ((uint32_t)(0x3UL << MXC_F_I3C_CONT_DMACTRL_TX_EN_POS)) /**< CONT_DMACTRL_TX_EN Mask */ +#define MXC_V_I3C_CONT_DMACTRL_TX_EN_DIS ((uint32_t)0x0UL) /**< CONT_DMACTRL_TX_EN_DIS Value */ +#define MXC_S_I3C_CONT_DMACTRL_TX_EN_DIS (MXC_V_I3C_CONT_DMACTRL_TX_EN_DIS << MXC_F_I3C_CONT_DMACTRL_TX_EN_POS) /**< CONT_DMACTRL_TX_EN_DIS Setting */ +#define MXC_V_I3C_CONT_DMACTRL_TX_EN_ONE_FR ((uint32_t)0x1UL) /**< CONT_DMACTRL_TX_EN_ONE_FR Value */ +#define MXC_S_I3C_CONT_DMACTRL_TX_EN_ONE_FR (MXC_V_I3C_CONT_DMACTRL_TX_EN_ONE_FR << MXC_F_I3C_CONT_DMACTRL_TX_EN_POS) /**< CONT_DMACTRL_TX_EN_ONE_FR Setting */ +#define MXC_V_I3C_CONT_DMACTRL_TX_EN_EN ((uint32_t)0x2UL) /**< CONT_DMACTRL_TX_EN_EN Value */ +#define MXC_S_I3C_CONT_DMACTRL_TX_EN_EN (MXC_V_I3C_CONT_DMACTRL_TX_EN_EN << MXC_F_I3C_CONT_DMACTRL_TX_EN_POS) /**< CONT_DMACTRL_TX_EN_EN Setting */ + +#define MXC_F_I3C_CONT_DMACTRL_WIDTH_POS 4 /**< CONT_DMACTRL_WIDTH Position */ +#define MXC_F_I3C_CONT_DMACTRL_WIDTH ((uint32_t)(0x3UL << MXC_F_I3C_CONT_DMACTRL_WIDTH_POS)) /**< CONT_DMACTRL_WIDTH Mask */ +#define MXC_V_I3C_CONT_DMACTRL_WIDTH_BYTE ((uint32_t)0x0UL) /**< CONT_DMACTRL_WIDTH_BYTE Value */ +#define MXC_S_I3C_CONT_DMACTRL_WIDTH_BYTE (MXC_V_I3C_CONT_DMACTRL_WIDTH_BYTE << MXC_F_I3C_CONT_DMACTRL_WIDTH_POS) /**< CONT_DMACTRL_WIDTH_BYTE Setting */ +#define MXC_V_I3C_CONT_DMACTRL_WIDTH_HALFWORD ((uint32_t)0x2UL) /**< CONT_DMACTRL_WIDTH_HALFWORD Value */ +#define MXC_S_I3C_CONT_DMACTRL_WIDTH_HALFWORD (MXC_V_I3C_CONT_DMACTRL_WIDTH_HALFWORD << MXC_F_I3C_CONT_DMACTRL_WIDTH_POS) /**< CONT_DMACTRL_WIDTH_HALFWORD Setting */ + +/**@} end of group I3C_CONT_DMACTRL_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_FIFOCTRL I3C_CONT_FIFOCTRL + * @brief Controller FIFO Control Register. + * @{ + */ +#define MXC_F_I3C_CONT_FIFOCTRL_TX_FLUSH_POS 0 /**< CONT_FIFOCTRL_TX_FLUSH Position */ +#define MXC_F_I3C_CONT_FIFOCTRL_TX_FLUSH ((uint32_t)(0x1UL << MXC_F_I3C_CONT_FIFOCTRL_TX_FLUSH_POS)) /**< CONT_FIFOCTRL_TX_FLUSH Mask */ + +#define MXC_F_I3C_CONT_FIFOCTRL_RX_FLUSH_POS 1 /**< CONT_FIFOCTRL_RX_FLUSH Position */ +#define MXC_F_I3C_CONT_FIFOCTRL_RX_FLUSH ((uint32_t)(0x1UL << MXC_F_I3C_CONT_FIFOCTRL_RX_FLUSH_POS)) /**< CONT_FIFOCTRL_RX_FLUSH Mask */ + +#define MXC_F_I3C_CONT_FIFOCTRL_UNLOCK_POS 3 /**< CONT_FIFOCTRL_UNLOCK Position */ +#define MXC_F_I3C_CONT_FIFOCTRL_UNLOCK ((uint32_t)(0x1UL << MXC_F_I3C_CONT_FIFOCTRL_UNLOCK_POS)) /**< CONT_FIFOCTRL_UNLOCK Mask */ + +#define MXC_F_I3C_CONT_FIFOCTRL_TX_THD_LVL_POS 4 /**< CONT_FIFOCTRL_TX_THD_LVL Position */ +#define MXC_F_I3C_CONT_FIFOCTRL_TX_THD_LVL ((uint32_t)(0x3UL << MXC_F_I3C_CONT_FIFOCTRL_TX_THD_LVL_POS)) /**< CONT_FIFOCTRL_TX_THD_LVL Mask */ +#define MXC_V_I3C_CONT_FIFOCTRL_TX_THD_LVL_EMPTY ((uint32_t)0x0UL) /**< CONT_FIFOCTRL_TX_THD_LVL_EMPTY Value */ +#define MXC_S_I3C_CONT_FIFOCTRL_TX_THD_LVL_EMPTY (MXC_V_I3C_CONT_FIFOCTRL_TX_THD_LVL_EMPTY << MXC_F_I3C_CONT_FIFOCTRL_TX_THD_LVL_POS) /**< CONT_FIFOCTRL_TX_THD_LVL_EMPTY Setting */ +#define MXC_V_I3C_CONT_FIFOCTRL_TX_THD_LVL_QUARTER_FULL ((uint32_t)0x1UL) /**< CONT_FIFOCTRL_TX_THD_LVL_QUARTER_FULL Value */ +#define MXC_S_I3C_CONT_FIFOCTRL_TX_THD_LVL_QUARTER_FULL (MXC_V_I3C_CONT_FIFOCTRL_TX_THD_LVL_QUARTER_FULL << MXC_F_I3C_CONT_FIFOCTRL_TX_THD_LVL_POS) /**< CONT_FIFOCTRL_TX_THD_LVL_QUARTER_FULL Setting */ +#define MXC_V_I3C_CONT_FIFOCTRL_TX_THD_LVL_HALF_FULL ((uint32_t)0x2UL) /**< CONT_FIFOCTRL_TX_THD_LVL_HALF_FULL Value */ +#define MXC_S_I3C_CONT_FIFOCTRL_TX_THD_LVL_HALF_FULL (MXC_V_I3C_CONT_FIFOCTRL_TX_THD_LVL_HALF_FULL << MXC_F_I3C_CONT_FIFOCTRL_TX_THD_LVL_POS) /**< CONT_FIFOCTRL_TX_THD_LVL_HALF_FULL Setting */ +#define MXC_V_I3C_CONT_FIFOCTRL_TX_THD_LVL_ALMOST_FULL ((uint32_t)0x3UL) /**< CONT_FIFOCTRL_TX_THD_LVL_ALMOST_FULL Value */ +#define MXC_S_I3C_CONT_FIFOCTRL_TX_THD_LVL_ALMOST_FULL (MXC_V_I3C_CONT_FIFOCTRL_TX_THD_LVL_ALMOST_FULL << MXC_F_I3C_CONT_FIFOCTRL_TX_THD_LVL_POS) /**< CONT_FIFOCTRL_TX_THD_LVL_ALMOST_FULL Setting */ + +#define MXC_F_I3C_CONT_FIFOCTRL_RX_THD_LVL_POS 6 /**< CONT_FIFOCTRL_RX_THD_LVL Position */ +#define MXC_F_I3C_CONT_FIFOCTRL_RX_THD_LVL ((uint32_t)(0x3UL << MXC_F_I3C_CONT_FIFOCTRL_RX_THD_LVL_POS)) /**< CONT_FIFOCTRL_RX_THD_LVL Mask */ +#define MXC_V_I3C_CONT_FIFOCTRL_RX_THD_LVL_NOT_EMPTY ((uint32_t)0x0UL) /**< CONT_FIFOCTRL_RX_THD_LVL_NOT_EMPTY Value */ +#define MXC_S_I3C_CONT_FIFOCTRL_RX_THD_LVL_NOT_EMPTY (MXC_V_I3C_CONT_FIFOCTRL_RX_THD_LVL_NOT_EMPTY << MXC_F_I3C_CONT_FIFOCTRL_RX_THD_LVL_POS) /**< CONT_FIFOCTRL_RX_THD_LVL_NOT_EMPTY Setting */ +#define MXC_V_I3C_CONT_FIFOCTRL_RX_THD_LVL_QUARTER_FULL ((uint32_t)0x1UL) /**< CONT_FIFOCTRL_RX_THD_LVL_QUARTER_FULL Value */ +#define MXC_S_I3C_CONT_FIFOCTRL_RX_THD_LVL_QUARTER_FULL (MXC_V_I3C_CONT_FIFOCTRL_RX_THD_LVL_QUARTER_FULL << MXC_F_I3C_CONT_FIFOCTRL_RX_THD_LVL_POS) /**< CONT_FIFOCTRL_RX_THD_LVL_QUARTER_FULL Setting */ +#define MXC_V_I3C_CONT_FIFOCTRL_RX_THD_LVL_HALF_FULL ((uint32_t)0x2UL) /**< CONT_FIFOCTRL_RX_THD_LVL_HALF_FULL Value */ +#define MXC_S_I3C_CONT_FIFOCTRL_RX_THD_LVL_HALF_FULL (MXC_V_I3C_CONT_FIFOCTRL_RX_THD_LVL_HALF_FULL << MXC_F_I3C_CONT_FIFOCTRL_RX_THD_LVL_POS) /**< CONT_FIFOCTRL_RX_THD_LVL_HALF_FULL Setting */ +#define MXC_V_I3C_CONT_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL ((uint32_t)0x3UL) /**< CONT_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL Value */ +#define MXC_S_I3C_CONT_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL (MXC_V_I3C_CONT_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL << MXC_F_I3C_CONT_FIFOCTRL_RX_THD_LVL_POS) /**< CONT_FIFOCTRL_RX_THD_LVL_3_QUARTER_FULL Setting */ + +#define MXC_F_I3C_CONT_FIFOCTRL_TX_LVL_POS 16 /**< CONT_FIFOCTRL_TX_LVL Position */ +#define MXC_F_I3C_CONT_FIFOCTRL_TX_LVL ((uint32_t)(0x3FUL << MXC_F_I3C_CONT_FIFOCTRL_TX_LVL_POS)) /**< CONT_FIFOCTRL_TX_LVL Mask */ + +#define MXC_F_I3C_CONT_FIFOCTRL_RX_LVL_POS 24 /**< CONT_FIFOCTRL_RX_LVL Position */ +#define MXC_F_I3C_CONT_FIFOCTRL_RX_LVL ((uint32_t)(0x3FUL << MXC_F_I3C_CONT_FIFOCTRL_RX_LVL_POS)) /**< CONT_FIFOCTRL_RX_LVL Mask */ + +#define MXC_F_I3C_CONT_FIFOCTRL_TX_FULL_POS 30 /**< CONT_FIFOCTRL_TX_FULL Position */ +#define MXC_F_I3C_CONT_FIFOCTRL_TX_FULL ((uint32_t)(0x1UL << MXC_F_I3C_CONT_FIFOCTRL_TX_FULL_POS)) /**< CONT_FIFOCTRL_TX_FULL Mask */ + +#define MXC_F_I3C_CONT_FIFOCTRL_RX_EM_POS 31 /**< CONT_FIFOCTRL_RX_EM Position */ +#define MXC_F_I3C_CONT_FIFOCTRL_RX_EM ((uint32_t)(0x1UL << MXC_F_I3C_CONT_FIFOCTRL_RX_EM_POS)) /**< CONT_FIFOCTRL_RX_EM Mask */ + +/**@} end of group I3C_CONT_FIFOCTRL_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_TXFIFO8 I3C_CONT_TXFIFO8 + * @brief Controller Write Byte Data Register. + * @{ + */ +#define MXC_F_I3C_CONT_TXFIFO8_DATA_POS 0 /**< CONT_TXFIFO8_DATA Position */ +#define MXC_F_I3C_CONT_TXFIFO8_DATA ((uint32_t)(0xFFUL << MXC_F_I3C_CONT_TXFIFO8_DATA_POS)) /**< CONT_TXFIFO8_DATA Mask */ + +#define MXC_F_I3C_CONT_TXFIFO8_END_POS 8 /**< CONT_TXFIFO8_END Position */ +#define MXC_F_I3C_CONT_TXFIFO8_END ((uint32_t)(0x1UL << MXC_F_I3C_CONT_TXFIFO8_END_POS)) /**< CONT_TXFIFO8_END Mask */ + +#define MXC_F_I3C_CONT_TXFIFO8_END2_POS 16 /**< CONT_TXFIFO8_END2 Position */ +#define MXC_F_I3C_CONT_TXFIFO8_END2 ((uint32_t)(0x1UL << MXC_F_I3C_CONT_TXFIFO8_END2_POS)) /**< CONT_TXFIFO8_END2 Mask */ + +/**@} end of group I3C_CONT_TXFIFO8_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_TXFIFO8E I3C_CONT_TXFIFO8E + * @brief Controller Write Byte Data as End Register. + * @{ + */ +#define MXC_F_I3C_CONT_TXFIFO8E_DATA_POS 0 /**< CONT_TXFIFO8E_DATA Position */ +#define MXC_F_I3C_CONT_TXFIFO8E_DATA ((uint32_t)(0xFFUL << MXC_F_I3C_CONT_TXFIFO8E_DATA_POS)) /**< CONT_TXFIFO8E_DATA Mask */ + +/**@} end of group I3C_CONT_TXFIFO8E_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_TXFIFO16 I3C_CONT_TXFIFO16 + * @brief Controller Write Half-Word Data Register. + * @{ + */ +#define MXC_F_I3C_CONT_TXFIFO16_DATA_POS 0 /**< CONT_TXFIFO16_DATA Position */ +#define MXC_F_I3C_CONT_TXFIFO16_DATA ((uint32_t)(0xFFFFUL << MXC_F_I3C_CONT_TXFIFO16_DATA_POS)) /**< CONT_TXFIFO16_DATA Mask */ + +#define MXC_F_I3C_CONT_TXFIFO16_END_POS 16 /**< CONT_TXFIFO16_END Position */ +#define MXC_F_I3C_CONT_TXFIFO16_END ((uint32_t)(0x1UL << MXC_F_I3C_CONT_TXFIFO16_END_POS)) /**< CONT_TXFIFO16_END Mask */ + +/**@} end of group I3C_CONT_TXFIFO16_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_TXFIFO16E I3C_CONT_TXFIFO16E + * @brief Controller Write Half-Word Data as End Register. + * @{ + */ +#define MXC_F_I3C_CONT_TXFIFO16E_DATA_POS 0 /**< CONT_TXFIFO16E_DATA Position */ +#define MXC_F_I3C_CONT_TXFIFO16E_DATA ((uint32_t)(0xFFFFUL << MXC_F_I3C_CONT_TXFIFO16E_DATA_POS)) /**< CONT_TXFIFO16E_DATA Mask */ + +/**@} end of group I3C_CONT_TXFIFO16E_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_RXFIFO8 I3C_CONT_RXFIFO8 + * @brief Controller Read Byte Data Register. + * @{ + */ +#define MXC_F_I3C_CONT_RXFIFO8_DATA_POS 0 /**< CONT_RXFIFO8_DATA Position */ +#define MXC_F_I3C_CONT_RXFIFO8_DATA ((uint32_t)(0xFFUL << MXC_F_I3C_CONT_RXFIFO8_DATA_POS)) /**< CONT_RXFIFO8_DATA Mask */ + +/**@} end of group I3C_CONT_RXFIFO8_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_RXFIFO16 I3C_CONT_RXFIFO16 + * @brief Controller Read Half-Word Data Register. + * @{ + */ +#define MXC_F_I3C_CONT_RXFIFO16_DATA_POS 0 /**< CONT_RXFIFO16_DATA Position */ +#define MXC_F_I3C_CONT_RXFIFO16_DATA ((uint32_t)(0xFFFFUL << MXC_F_I3C_CONT_RXFIFO16_DATA_POS)) /**< CONT_RXFIFO16_DATA Mask */ + +/**@} end of group I3C_CONT_RXFIFO16_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_TXFIFO8O I3C_CONT_TXFIFO8O + * @brief Controller Byte-Only Write Byte Data Register. + * @{ + */ +#define MXC_F_I3C_CONT_TXFIFO8O_DATA_POS 0 /**< CONT_TXFIFO8O_DATA Position */ +#define MXC_F_I3C_CONT_TXFIFO8O_DATA ((uint32_t)(0xFFUL << MXC_F_I3C_CONT_TXFIFO8O_DATA_POS)) /**< CONT_TXFIFO8O_DATA Mask */ + +/**@} end of group I3C_CONT_TXFIFO8O_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_TXSDRMSG_CTRL I3C_CONT_TXSDRMSG_CTRL + * @brief Controller Start or Continue SDR Message Register. + * @{ + */ +#define MXC_F_I3C_CONT_TXSDRMSG_CTRL_RDWR_DIR_POS 0 /**< CONT_TXSDRMSG_CTRL_RDWR_DIR Position */ +#define MXC_F_I3C_CONT_TXSDRMSG_CTRL_RDWR_DIR ((uint32_t)(0x1UL << MXC_F_I3C_CONT_TXSDRMSG_CTRL_RDWR_DIR_POS)) /**< CONT_TXSDRMSG_CTRL_RDWR_DIR Mask */ + +#define MXC_F_I3C_CONT_TXSDRMSG_CTRL_ADDR_POS 1 /**< CONT_TXSDRMSG_CTRL_ADDR Position */ +#define MXC_F_I3C_CONT_TXSDRMSG_CTRL_ADDR ((uint32_t)(0x7FUL << MXC_F_I3C_CONT_TXSDRMSG_CTRL_ADDR_POS)) /**< CONT_TXSDRMSG_CTRL_ADDR Mask */ + +#define MXC_F_I3C_CONT_TXSDRMSG_CTRL_END_POS 8 /**< CONT_TXSDRMSG_CTRL_END Position */ +#define MXC_F_I3C_CONT_TXSDRMSG_CTRL_END ((uint32_t)(0x1UL << MXC_F_I3C_CONT_TXSDRMSG_CTRL_END_POS)) /**< CONT_TXSDRMSG_CTRL_END Mask */ + +#define MXC_F_I3C_CONT_TXSDRMSG_CTRL_I2C_EN_POS 10 /**< CONT_TXSDRMSG_CTRL_I2C_EN Position */ +#define MXC_F_I3C_CONT_TXSDRMSG_CTRL_I2C_EN ((uint32_t)(0x1UL << MXC_F_I3C_CONT_TXSDRMSG_CTRL_I2C_EN_POS)) /**< CONT_TXSDRMSG_CTRL_I2C_EN Mask */ + +#define MXC_F_I3C_CONT_TXSDRMSG_CTRL_LEN_POS 11 /**< CONT_TXSDRMSG_CTRL_LEN Position */ +#define MXC_F_I3C_CONT_TXSDRMSG_CTRL_LEN ((uint32_t)(0x1FUL << MXC_F_I3C_CONT_TXSDRMSG_CTRL_LEN_POS)) /**< CONT_TXSDRMSG_CTRL_LEN Mask */ + +/**@} end of group I3C_CONT_TXSDRMSG_CTRL_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_TXSDRMSG_FIFO I3C_CONT_TXSDRMSG_FIFO + * @brief Controller Start or Continue SDR Message Register. + * @{ + */ +#define MXC_F_I3C_CONT_TXSDRMSG_FIFO_DATA_POS 0 /**< CONT_TXSDRMSG_FIFO_DATA Position */ +#define MXC_F_I3C_CONT_TXSDRMSG_FIFO_DATA ((uint32_t)(0xFFFFUL << MXC_F_I3C_CONT_TXSDRMSG_FIFO_DATA_POS)) /**< CONT_TXSDRMSG_FIFO_DATA Mask */ + +/**@} end of group I3C_CONT_TXSDRMSG_FIFO_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_RXSDRMSG I3C_CONT_RXSDRMSG + * @brief Controller Read SDR Message Data Register. + * @{ + */ +#define MXC_F_I3C_CONT_RXSDRMSG_DATA_POS 0 /**< CONT_RXSDRMSG_DATA Position */ +#define MXC_F_I3C_CONT_RXSDRMSG_DATA ((uint32_t)(0xFFFFUL << MXC_F_I3C_CONT_RXSDRMSG_DATA_POS)) /**< CONT_RXSDRMSG_DATA Mask */ + +/**@} end of group I3C_CONT_RXSDRMSG_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_TXDDRMSG I3C_CONT_TXDDRMSG + * @brief Controller Start or Continue DDR Message Register. + * @{ + */ +#define MXC_F_I3C_CONT_TXDDRMSG_MSG_POS 0 /**< CONT_TXDDRMSG_MSG Position */ +#define MXC_F_I3C_CONT_TXDDRMSG_MSG ((uint32_t)(0xFFFFUL << MXC_F_I3C_CONT_TXDDRMSG_MSG_POS)) /**< CONT_TXDDRMSG_MSG Mask */ + +/**@} end of group I3C_CONT_TXDDRMSG_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_RXDDR16 I3C_CONT_RXDDR16 + * @brief Controller Read DDR Message Data Register. + * @{ + */ +#define MXC_F_I3C_CONT_RXDDR16_DATA_POS 0 /**< CONT_RXDDR16_DATA Position */ +#define MXC_F_I3C_CONT_RXDDR16_DATA ((uint32_t)(0xFFFFUL << MXC_F_I3C_CONT_RXDDR16_DATA_POS)) /**< CONT_RXDDR16_DATA Mask */ + +/**@} end of group I3C_CONT_RXDDR16_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_CONT_DYNADDR I3C_CONT_DYNADDR + * @brief Controller Dynamic Address Register. + * @{ + */ +#define MXC_F_I3C_CONT_DYNADDR_ADDR_POS 1 /**< CONT_DYNADDR_ADDR Position */ +#define MXC_F_I3C_CONT_DYNADDR_ADDR ((uint32_t)(0x7FUL << MXC_F_I3C_CONT_DYNADDR_ADDR_POS)) /**< CONT_DYNADDR_ADDR Mask */ + +#define MXC_F_I3C_CONT_DYNADDR_VALID_POS 8 /**< CONT_DYNADDR_VALID Position */ +#define MXC_F_I3C_CONT_DYNADDR_VALID ((uint32_t)(0x1UL << MXC_F_I3C_CONT_DYNADDR_VALID_POS)) /**< CONT_DYNADDR_VALID Mask */ + +/**@} end of group I3C_CONT_DYNADDR_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_GROUPDEF I3C_TARG_GROUPDEF + * @brief Target Group Definition Register. + * @{ + */ +#define MXC_F_I3C_TARG_GROUPDEF_ADDR_EN_POS 0 /**< TARG_GROUPDEF_ADDR_EN Position */ +#define MXC_F_I3C_TARG_GROUPDEF_ADDR_EN ((uint32_t)(0x1UL << MXC_F_I3C_TARG_GROUPDEF_ADDR_EN_POS)) /**< TARG_GROUPDEF_ADDR_EN Mask */ + +#define MXC_F_I3C_TARG_GROUPDEF_ADDR_POS 1 /**< TARG_GROUPDEF_ADDR Position */ +#define MXC_F_I3C_TARG_GROUPDEF_ADDR ((uint32_t)(0x7FUL << MXC_F_I3C_TARG_GROUPDEF_ADDR_POS)) /**< TARG_GROUPDEF_ADDR Mask */ + +/**@} end of group I3C_TARG_GROUPDEF_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_MAPCTRL0 I3C_TARG_MAPCTRL0 + * @brief Target Primary Map Control Register. + * @{ + */ +#define MXC_F_I3C_TARG_MAPCTRL0_DYNADDR_EN_POS 0 /**< TARG_MAPCTRL0_DYNADDR_EN Position */ +#define MXC_F_I3C_TARG_MAPCTRL0_DYNADDR_EN ((uint32_t)(0x1UL << MXC_F_I3C_TARG_MAPCTRL0_DYNADDR_EN_POS)) /**< TARG_MAPCTRL0_DYNADDR_EN Mask */ + +#define MXC_F_I3C_TARG_MAPCTRL0_DYNADDR_POS 1 /**< TARG_MAPCTRL0_DYNADDR Position */ +#define MXC_F_I3C_TARG_MAPCTRL0_DYNADDR ((uint32_t)(0x7FUL << MXC_F_I3C_TARG_MAPCTRL0_DYNADDR_POS)) /**< TARG_MAPCTRL0_DYNADDR Mask */ + +#define MXC_F_I3C_TARG_MAPCTRL0_CAUSE_POS 8 /**< TARG_MAPCTRL0_CAUSE Position */ +#define MXC_F_I3C_TARG_MAPCTRL0_CAUSE ((uint32_t)(0x7UL << MXC_F_I3C_TARG_MAPCTRL0_CAUSE_POS)) /**< TARG_MAPCTRL0_CAUSE Mask */ + +/**@} end of group I3C_TARG_MAPCTRL0_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_MAPCTRL1 I3C_TARG_MAPCTRL1 + * @brief Target Map Control 1 Register. + * @{ + */ +#define MXC_F_I3C_TARG_MAPCTRL1_EN_POS 0 /**< TARG_MAPCTRL1_EN Position */ +#define MXC_F_I3C_TARG_MAPCTRL1_EN ((uint32_t)(0x1UL << MXC_F_I3C_TARG_MAPCTRL1_EN_POS)) /**< TARG_MAPCTRL1_EN Mask */ + +#define MXC_F_I3C_TARG_MAPCTRL1_ADDR_POS 1 /**< TARG_MAPCTRL1_ADDR Position */ +#define MXC_F_I3C_TARG_MAPCTRL1_ADDR ((uint32_t)(0x7FUL << MXC_F_I3C_TARG_MAPCTRL1_ADDR_POS)) /**< TARG_MAPCTRL1_ADDR Mask */ + +#define MXC_F_I3C_TARG_MAPCTRL1_STATADDR_EN_POS 8 /**< TARG_MAPCTRL1_STATADDR_EN Position */ +#define MXC_F_I3C_TARG_MAPCTRL1_STATADDR_EN ((uint32_t)(0x1UL << MXC_F_I3C_TARG_MAPCTRL1_STATADDR_EN_POS)) /**< TARG_MAPCTRL1_STATADDR_EN Mask */ + +#define MXC_F_I3C_TARG_MAPCTRL1_STATADDR_10B_POS 9 /**< TARG_MAPCTRL1_STATADDR_10B Position */ +#define MXC_F_I3C_TARG_MAPCTRL1_STATADDR_10B ((uint32_t)(0x7UL << MXC_F_I3C_TARG_MAPCTRL1_STATADDR_10B_POS)) /**< TARG_MAPCTRL1_STATADDR_10B Mask */ + +#define MXC_F_I3C_TARG_MAPCTRL1_NACK_POS 12 /**< TARG_MAPCTRL1_NACK Position */ +#define MXC_F_I3C_TARG_MAPCTRL1_NACK ((uint32_t)(0x1UL << MXC_F_I3C_TARG_MAPCTRL1_NACK_POS)) /**< TARG_MAPCTRL1_NACK Mask */ + +/**@} end of group I3C_TARG_MAPCTRL1_Register */ + +/** + * @ingroup i3c_registers + * @defgroup I3C_TARG_MAPCTRL2 I3C_TARG_MAPCTRL2 + * @brief Target Map Control 2 Register. + * @{ + */ +#define MXC_F_I3C_TARG_MAPCTRL2_EN_POS 0 /**< TARG_MAPCTRL2_EN Position */ +#define MXC_F_I3C_TARG_MAPCTRL2_EN ((uint32_t)(0x1UL << MXC_F_I3C_TARG_MAPCTRL2_EN_POS)) /**< TARG_MAPCTRL2_EN Mask */ + +#define MXC_F_I3C_TARG_MAPCTRL2_ADDR_POS 1 /**< TARG_MAPCTRL2_ADDR Position */ +#define MXC_F_I3C_TARG_MAPCTRL2_ADDR ((uint32_t)(0x7FUL << MXC_F_I3C_TARG_MAPCTRL2_ADDR_POS)) /**< TARG_MAPCTRL2_ADDR Mask */ + +#define MXC_F_I3C_TARG_MAPCTRL2_STATADDR_EN_POS 8 /**< TARG_MAPCTRL2_STATADDR_EN Position */ +#define MXC_F_I3C_TARG_MAPCTRL2_STATADDR_EN ((uint32_t)(0x1UL << MXC_F_I3C_TARG_MAPCTRL2_STATADDR_EN_POS)) /**< TARG_MAPCTRL2_STATADDR_EN Mask */ + +#define MXC_F_I3C_TARG_MAPCTRL2_NACK_POS 12 /**< TARG_MAPCTRL2_NACK Position */ +#define MXC_F_I3C_TARG_MAPCTRL2_NACK ((uint32_t)(0x1UL << MXC_F_I3C_TARG_MAPCTRL2_NACK_POS)) /**< TARG_MAPCTRL2_NACK Mask */ + +#define MXC_F_I3C_TARG_MAPCTRL2_AUTO_EN_POS 13 /**< TARG_MAPCTRL2_AUTO_EN Position */ +#define MXC_F_I3C_TARG_MAPCTRL2_AUTO_EN ((uint32_t)(0x1UL << MXC_F_I3C_TARG_MAPCTRL2_AUTO_EN_POS)) /**< TARG_MAPCTRL2_AUTO_EN Mask */ + +#define MXC_F_I3C_TARG_MAPCTRL2_PID_POS 14 /**< TARG_MAPCTRL2_PID Position */ +#define MXC_F_I3C_TARG_MAPCTRL2_PID ((uint32_t)(0x3FFFFUL << MXC_F_I3C_TARG_MAPCTRL2_PID_POS)) /**< TARG_MAPCTRL2_PID Mask */ + +/**@} end of group I3C_TARG_MAPCTRL2_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_I3C_REGS_H_ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/icc_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/icc_regs.h index 4a64475e..e7691d55 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/icc_regs.h +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/icc_regs.h @@ -84,8 +84,8 @@ typedef struct { __R uint32_t rsv_0x104_0x1ff[63]; __IO uint32_t way; /**< \b 0x0200: ICC WAY Register */ __IO uint32_t regctrl; /**< \b 0x0204: ICC REGCTRL Register */ - __IO mxc_icc_reg_regs_t region[15]; /**< \b 0x0208: ICC REGION Register */ - __R uint32_t rsv_0x244_0x2ff[47]; + __IO mxc_icc_reg_regs_t region[4]; /**< \b 0x0208: ICC REGION Register */ + __R uint32_t rsv_0x228_0x2ff[54]; __IO uint32_t pfmctrl; /**< \b 0x0300: ICC PFMCTRL Register */ __IO uint32_t pfmcnt; /**< \b 0x0304: ICC PFMCNT Register */ __R uint32_t rsv_0x308_0x6ff[254]; @@ -164,7 +164,13 @@ typedef struct { * @{ */ #define MXC_F_ICC_WAY_WAY_POS 0 /**< WAY_WAY Position */ -#define MXC_F_ICC_WAY_WAY ((uint32_t)(0x1UL << MXC_F_ICC_WAY_WAY_POS)) /**< WAY_WAY Mask */ +#define MXC_F_ICC_WAY_WAY ((uint32_t)(0x7UL << MXC_F_ICC_WAY_WAY_POS)) /**< WAY_WAY Mask */ +#define MXC_V_ICC_WAY_WAY_1 ((uint32_t)0x1UL) /**< WAY_WAY_1 Value */ +#define MXC_S_ICC_WAY_WAY_1 (MXC_V_ICC_WAY_WAY_1 << MXC_F_ICC_WAY_WAY_POS) /**< WAY_WAY_1 Setting */ +#define MXC_V_ICC_WAY_WAY_2 ((uint32_t)0x2UL) /**< WAY_WAY_2 Value */ +#define MXC_S_ICC_WAY_WAY_2 (MXC_V_ICC_WAY_WAY_2 << MXC_F_ICC_WAY_WAY_POS) /**< WAY_WAY_2 Setting */ +#define MXC_V_ICC_WAY_WAY_4 ((uint32_t)0x4UL) /**< WAY_WAY_4 Value */ +#define MXC_S_ICC_WAY_WAY_4 (MXC_V_ICC_WAY_WAY_4 << MXC_F_ICC_WAY_WAY_POS) /**< WAY_WAY_4 Setting */ /**@} end of group ICC_WAY_Register */ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h index 44e81073..f3ea5759 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.h @@ -123,7 +123,7 @@ typedef enum { BTLE_RX_AES_IRQn, /* 0x3B 0x00EC 59: BTLE RX AES Done */ BTLE_INV_APB_ADDR_IRQn, /* 0x3C 0x00F0 60: BTLE Invalid APB Address */ BTLE_IQ_DATA_VALID_IRQn, /* 0x3D 0x00F4 61:BTLE IQ Data Valid */ - BTLE_XXXX_IRQn, /* 0x3E 0x00F8 62: BTLE XXXX TODO(ME30): Verify BTLE IRQs */ + BTLE_RX_CRC_IRQn, /* 0x3E 0x00F8 62: BTLE RX CRC */ RSV47_IRQn, /* 0x3F 0x00FC 63: Reserved */ MPC_IRQn, /* 0x40 0x0100 64: MPC Combined (Secure) */ PPC_IRQn, /* 0x41 0x0104 65: PPC Combined (Secure) */ @@ -152,11 +152,17 @@ typedef enum { #define __Vendor_SysTickConfig 0U /**< Is 1 if different SysTick counter is used */ #include +#include #include + +#if defined(__GNUC__) #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define IS_SECURE_ENVIRONMENT 1 -#else -#define IS_SECURE_ENVIRONMENT 0 +// Type used for secure code to call non-secure code. +#define __ns_call __attribute((cmse_nonsecure_call)) +typedef void __ns_call (*mxc_ns_call_t) (void); +// Type used for non-secure code to call secure code. +#define __ns_entry __attribute((cmse_nonsecure_entry)) +#endif #endif /* ================================================================================ */ @@ -607,15 +613,15 @@ We may want to handle GET_IRQ better... /******************************************************************************/ /* I3C */ -#define MXC_I3C_FIFO_DEPTH (8) // TODO(ME30): Confirm this is correct. +#define MXC_I3C_FIFO_DEPTH (8) /* Non-secure Mapping */ -#define MXC_BASE_I3C_NS ((uint32_t)0x4001D000UL) -#define MXC_I3C_NS ((mxc_i2c_regs_t *)MXC_BASE_I3C_NS) +#define MXC_BASE_I3C_NS ((uint32_t)0x40018000UL) +#define MXC_I3C_NS ((mxc_i3c_regs_t *)MXC_BASE_I3C_NS) /* Secure Mapping */ -#define MXC_BASE_I3C_S ((uint32_t)0x5001D000UL) -#define MXC_I3C_S ((mxc_i2c_regs_t *)MXC_BASE_I3C_S) +#define MXC_BASE_I3C_S ((uint32_t)0x50018000UL) +#define MXC_I3C_S ((mxc_i3c_regs_t *)MXC_BASE_I3C_S) #if IS_SECURE_ENVIRONMENT #define MXC_BASE_I3C MXC_BASE_I3C_S @@ -819,39 +825,39 @@ We may want to handle GET_IRQ better... /* Secure Mapping Only */ #define MXC_BASE_SPC ((uint32_t)0x50090000UL) -#define MXC_SPC // TODO(ME30): Does this have registers? -#define MXC_SPC_S // TODO(ME30): Does this have registers? +#define MXC_SPC ((mxc_spc_regs_t *)MXC_BASE_SPC) +#define MXC_SPC_S MXC_SPC /******************************************************************************/ /* MPC */ /* Secure Mapping Only */ #define MXC_BASE_MPC_SRAM0 ((uint32_t)0x50091000UL) -#define MXC_MPC_SRAM0 // TODO(ME30): Does this have registers? +#define MXC_MPC_SRAM0 ((mxc_mpc_regs_t *)MXC_BASE_MPC_SRAM0) #define MXC_BASE_MPC_SRAM1 ((uint32_t)0x50092000UL) -#define MXC_MPC_SRAM1 // TODO(ME30): Does this have registers? +#define MXC_MPC_SRAM1 ((mxc_mpc_regs_t *)MXC_BASE_MPC_SRAM1) #define MXC_BASE_MPC_SRAM2 ((uint32_t)0x50093000UL) -#define MXC_MPC_SRAM2 // TODO(ME30): Does this have registers? +#define MXC_MPC_SRAM2 ((mxc_mpc_regs_t *)MXC_BASE_MPC_SRAM2) #define MXC_BASE_MPC_SRAM3 ((uint32_t)0x50094000UL) -#define MXC_MPC_SRAM3 // TODO(ME30): Does this have registers? +#define MXC_MPC_SRAM3 ((mxc_mpc_regs_t *)MXC_BASE_MPC_SRAM3) #define MXC_BASE_MPC_SRAM4 ((uint32_t)0x50095000UL) -#define MXC_MPC_SRAM4 // TODO(ME30): Does this have registers? +#define MXC_MPC_SRAM4 ((mxc_mpc_regs_t *)MXC_BASE_MPC_SRAM4) #define MXC_BASE_MPC_FLASH ((uint32_t)0x50096000UL) -#define MXC_MPC_FLASH // TODO(ME30): Does this have registers? +#define MXC_MPC_FLASH ((mxc_mpc_regs_t *)MXC_BASE_MPC_FLASH) /* Added for consistency and explicitness */ #define MXC_BASE_MPC_SRAM0_S MXC_BASE_MPC_SRAM0 -#define MXC_MPC_SRAM0_S // TODO(ME30): Does this have registers? +#define MXC_MPC_SRAM0_S MXC_MPC_SRAM0 #define MXC_BASE_MPC_SRAM1_S MXC_BASE_MPC_SRAM1 -#define MXC_MPC_SRAM1_S // TODO(ME30): Does this have registers? +#define MXC_MPC_SRAM1_S MXC_MPC_SRAM1 #define MXC_BASE_MPC_SRAM2_S MXC_BASE_MPC_SRAM2 -#define MXC_MPC_SRAM2_S // TODO(ME30): Does this have registers? +#define MXC_MPC_SRAM2_S MXC_MPC_SRAM2 #define MXC_BASE_MPC_SRAM3_S MXC_BASE_MPC_SRAM3 -#define MXC_MPC_SRAM3_S // TODO(ME30): Does this have registers? +#define MXC_MPC_SRAM3_S MXC_MPC_SRAM3 #define MXC_BASE_MPC_SRAM4_S MXC_BASE_MPC_SRAM4 -#define MXC_MPC_SRAM4_S // TODO(ME30): Does this have registers? +#define MXC_MPC_SRAM4_S MXC_MPC_SRAM4 #define MXC_BASE_MPC_FLASH_S MXC_BASE_MPC_FLASH -#define MXC_MPC_FLASH_S // TODO(ME30): Does this have registers? +#define MXC_MPC_FLASH_S MXC_MPC_FLASH /******************************************************************************/ /* Bit Shifting */ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd index a3b75cce..8849da30 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/max32657.svd @@ -25,7 +25,7 @@ AESKEYS AES Key Registers. - 0x40007800 + 0x50007800 0x00 0x400 @@ -86,7 +86,7 @@ AES AES Keys. - 0x40007400 + 0x50007400 0x00 0x400 @@ -296,7 +296,7 @@ CRC CRC Registers. - 0x4000F000 + 0x5000F000 0x00 0x1000 @@ -424,7 +424,7 @@ DMA DMA Controller Fully programmable, chaining capable DMA channels. - 0x40028000 + 0x50028000 32 0x00 @@ -432,20 +432,20 @@ registers - DMA0 - 28 + DMA0_CH0 + 32 - DMA1 - 29 + DMA0_CH1 + 33 - DMA2 - 30 + DMA0_CH2 + 34 - DMA3 - 31 + DMA0_CH4 + 35 @@ -1058,10 +1058,36 @@ + + DMA1 + DMA Controller Fully programmable, chaining capable DMA channels. 1 + 0x50035000 + + DMA1_CH0 + DMA1_CH0 + 36 + + + DMA1_CH1 + DMA1_CH1 + 37 + + + DMA1_CH2 + DMA1_CH2 + 38 + + + DMA1_CH3 + DMA1_CH3 + 39 + + + FCR Function Control Register. - 0x40000800 + 0x50000800 0x00 0x400 @@ -1075,14 +1101,14 @@ read-write - BTLELDO_TX - BTLE LDO TX Trim. + BTLELDO_RF + BTLE LDO RF Trim. 0 5 - BTLELDO_RX - BTLE LDO RX Trim. + BTLELDO_BB + BTLE LDO BB Trim. 8 5 @@ -1313,7 +1339,7 @@ FLC Flash Memory Control. FLSH_ - 0x40029000 + 0x50029000 0x00 0x400 @@ -1630,7 +1656,7 @@ GCR Global Control Registers. - 0x40000000 + 0x50000000 0 0x400 @@ -2298,6 +2324,12 @@ 10 1 + + AUTOCAL + Auto calibration Reset. + 12 + 1 + @@ -2335,12 +2367,6 @@ 15 1 - - SPI - SPI Clock Disable - 16 - 1 - DMA1 DMA1 Clock Disable @@ -2432,6 +2458,19 @@ + + ECCCED + ECC Correctable Error Detect Register. + 0x68 + + + FLASH + ECC Correctable Error Detect Flag for Flash. Write 1 to clear. + 0 + 1 + + + ECCINTEN ECC Interrupt Enable Register @@ -2440,7 +2479,7 @@ FLASH ECC Flash0 Interrupt Enable. - 11 + 0 1 @@ -2494,86 +2533,86 @@ 0x74 - TX_EN - LDOTX enable. + RF_EN + LDO RF enable. 0 1 - TX_PD_EN - LDOTX Pull Down. + RF_PD_EN + LDO RF Pull Down. 1 1 - TX_VSEL - Voltage Selection for NFC LDO + RF_VSEL + Voltage Selection for RF LDO 2 2 - RX_EN - LDORX enable. + BB_EN + LDOBB enable. 4 1 - RX_PD_EN - LDORX Pull DOwn. + BB_PD_EN + LDO BB Pull DOwn. 5 1 - RX_VSEL - LDORX Voltage Setting. + BB_VSEL + LDO BB Voltage Setting. 6 2 - RX_BP_EN - LDORX Bypass Enable. + BB_BP_EN + LDO BB Bypass Enable. 8 1 - RX_DISCH - LDORX Discharge. + BB_DISCH + LDO BB Discharge. 9 1 - TX_BP_EN - LDOTX Bypass Enable. + RF_BP_EN + LDO RF Bypass Enable. 10 1 - TX_DISCH - LDOTX Discharge. + RF_DISCH + LDO RF Discharge. 11 1 - TX_EN_DLY - LDOTX Enable Delay. + RF_EN_DLY + LDO RF Enable Delay. 12 1 - RX_EN_DLY - LDORX Enable Delay. + BB_EN_DLY + LDO BB Enable Delay. 13 1 - RX_BP_EN_DLY - LDORX Bypass Enable Delay. + BB_BP_EN_DLY + LDO BB Bypass Enable Delay. 14 1 - TX_BP_EN_DLY - LDOTX Bypass Enable Delay. + RF_BP_EN_DLY + LDO RF Bypass Enable Delay. 15 1 @@ -2591,14 +2630,14 @@ 8 - RX_CNT - RX delay count. + BB_CNT + BB delay count. 8 9 - TX_CNT - TX delay count. + RF_CNT + RF delay count. 20 9 @@ -2611,7 +2650,7 @@ GPIO0 Individual I/O for each GPIO GPIO - 0x40008000 + 0x50008000 0x00 0x1000 @@ -3317,167 +3356,2577 @@ - ICC - Instruction Cache Controller Registers - 0x4002A000 + I3C0 + Improved Inter-Integrated Circuit. + I3C + 0x50018000 + 32 0x00 - 0x800 + 0x1000 registers + + I3C0 + I3C0 IRQ + 26 + - INFO - Cache ID Register. - 0x0000 - read-only - - - RELNUM - Release Number. Identifies the RTL release version. - 0 - 6 - - - PARTNUM - Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter. - 6 - 4 - - - ID - Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter. - 10 - 6 - - - - - SZ - Memory Configuration Register. - 0x0004 - read-only - 0x00080008 + CONT_CTRL0 + Controller Control 0 (Configuration) Register. + 0x000 - CCH - Cache Size. Indicates total size in Kbytes of cache. - 0 - 16 + EN + I3C Device Enable. + [1:0] + read-write + + + OFF + Off. + 0 + + + ON + On. + 1 + + + CAP + I23 Bug Target with secondary controller capability. + 2 + + - MEM - Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller. - 16 - 16 + TO_DIS + Disable Timeout error. + [3:3] + read-write - - - - CTRL - Cache Control and Status Register. - 0x0100 - - EN - Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated. - 0 - 1 + HKEEP + High-keepr implementation. + [5:4] + read-write - dis - Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array. + OFF + No high-keeper support. 0 - en - Cache Enabled. + ON_CHIP + On-chip high-keeper support. 1 + + EXT_SDA + External high-keeper support for SDA. + 2 + + + EXT_SCL_SDA + External high-keeper support for SCL and SDA. + 3 + - RDY - Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready. - 16 - 1 - read-only + OD_STOP + Use open-drain speed for STOP. + [6:6] + read-write + + + PP_BAUD + SCL Frequency for push-pull drive. + [11:8] + read-write - notReady - Not Ready. + 1_FCLK + SCL High Period is one FCLK Period. 0 - ready - Ready. + 2_FCLK + SCL High Period is two FLCK Periods. 1 + + 3_FCLK + SCL High Period is three FCLK Period. + 2 + + + 4_FCLK + SCL High Period is four FCLK Period. + 3 + + + 5_FCLK + SCL High Period is five FCLK Period. + 4 + + + 6_FCLK + SCL High Period is six FCLK Period. + 5 + + + 7_FCLK + SCL High Period is seven FCLK Period. + 6 + + + 8_FCLK + SCL High Period is eight FCLK Period. + 7 + + + 9_FCLK + SCL High Period is nine FCLK Period. + 8 + + + 10_FCLK + SCL High Period is ten FCLK Period. + 9 + + + 11_FCLK + SCL High Period is eleven FCLK Period. + 10 + + + 12_FCLK + SCL High Period is twelve FCLK Period. + 11 + + + 13_FCLK + SCL High Period is thirteen FCLK Period. + 12 + + + 14_FCLK + SCL High Period is fourteen FCLK Period. + 13 + + + 15_FCLK + SCL High Period is fifthteen FCLK Period. + 14 + + + 16_FCLK + SCL High Period is sixteen FCLK Period. + 15 + - - - - WAY - Cache Way Control Register. - 0x0200 - - WAY - Number of cache way, default is always 2. Allowed values are 1,2,4. - 0 - 1 + PP_ADD_LBAUD + Number of FCLK periods to add to the base of SCL low period. + [15:12] + read-write - 1 - 1 + 0_FCLK + Adds zero FCLK periods to the SCL low period. 0 - 2 - 2 + 1_FCLK + Adds one FCLK period to the SCL low period. 1 - 4 - 4 + 2_FCLK + Adds two FCLK periods to the SCL low period. 2 + + 3_FCLK + Adds three FCLK periods to the SCL low period. + 3 + + + 4_FCLK + Adds four FCLK periods to the SCL low period. + 4 + + + 5_FCLK + Adds five FCLK periods to the SCL low period. + 5 + + + 6_FCLK + Adds six FCLK periods to the SCL low period. + 6 + + + 7_FCLK + Adds seven FCLK periods to the SCL low period. + 7 + + + 8_FCLK + Adds eight FCLK periods to the SCL low period. + 8 + + + 9_FCLK + Adds nine FCLK periods to the SCL low period. + 9 + + + 10_FCLK + Adds ten FCLK periods to the SCL low period. + 10 + + + 11_FCLK + Adds eleven FCLK periods to the SCL low period. + 11 + + + 12_FCLK + Adds twelve FCLK periods to the SCL low period. + 12 + + + 13_FCLK + Adds thirteen FCLK periods to the SCL low period. + 13 + + + 14_FCLK + Adds fourteen FCLK periods to the SCL low period. + 14 + + + 15_FCLK + Adds fifthteen FCLK periods to the SCL low period. + 15 + + + OD_LBAUD + Number of PP_BAUD periods minus 1 to make one SCL low period for I3C open-dran periods. + [23:16] + read-write + + + OD_HP + Controls SCL high period for I3C oepn-drain operation. + [24:24] + read-write + + + PP_SKEW + Number of FCLK periods to delay the SDA value change from the SCL edge for I3C push-pull operation. + [27:25] + read-write + + + I2C_BAUD + Detyermines SCL high and low pweriods for I2C mode, in units of OD_BAUD period. + [31:28] + read-write + - REGCTRL - Regional Control Register. - 0x0204 + TARG_CTRL0 + Target Control 0 (Configuration) Register. + 0x004 EN - Enable the regional high andlow bound compare, cache the data only if the TAG content between the high and low bound. - 0 - 8 + Target device enable. + [0:0] + read-write - EXC - Cache the data only if the TAG content is excluded in the high and low bound. - 8 - 8 + MATCHSS + Match STOP and START. + [2:2] + read-write - + + TO_IGN + Ignore Timeout Errors. + [3:3] + read-write + + + OFFLINE + Rejoin I3C bus with existing dynamic address. + [9:9] + read-write + + + + + TARG_STATUS + Target Status Register. + 0x008 + + + BUSY + Not stopped. + [0:0] + read-only + + + LIST_RESP + Message status - listening/responding or not. + [1:1] + read-only + + + CCCH + CCC is being handled. + [2:2] + read-only + + + RX_SDR + SDR Read. + [3:3] + + + TX_SDR + SDR Write. + [4:4] + + + DAA + Dynamic Address Assignment Mode. + [5:5] + read-only + + + HDR + HDR Mode. + [6:6] + read-only + + + START + START Detected. + [8:8] + read-write + + + ADDRMATCH + Address Matched. + [9:9] + read-write + + + STOP + STOP Detected. + [10:10] + read-write + + + RX_RDY + Receive data ready. + [11:11] + read-only + + + TX_NFULL + TX FIFO is not full, ready to accept more data. + [12:12] + read-write + + + DYNADDR_CHG + Dynamic address changed. + [13:13] + read-write + + + CCC + CCC received. + [14:14] + read-write + + + ERRWARN + An error or warning has occurred. + [15:15] + read-only + + + CCCH_DONE + CCC Handled. + [17:17] + read-write + + + EVENT_REQ + Event Requested. + [18:18] + read-write + + + TARG_RST + Target Reset. + [19:19] + read-write + + + EVENT + Event Status. + [21:20] + read-only + + + NONE + No event. + 0 + + + REQ_PEND + Request not yet sent. + 1 + + + REQ_NACK + Request was sent and NACKed and will be tried again. + 2 + + + REQ_ACK + Request was sent and ACKed. + 3 + + + + + IBI_DIS + Indicates whether IBI events are disabled. + [24:24] + read-only + + + CONTREQ_DIS + Indicates whether bus controller request events are disabled. + [25:25] + read-only + + + HJ_DIS + Indicates whether Hot-Joinevents are disabled. + [27:27] + read-only + + + ACTSTATE + Holds the current activity state. + [29:28] + read-only + + + NORMAL + No latency, normal bus operation. + 0 + + + 1MS_LAT + 1 ms latency. + 1 + + + 100MS_LAT + 100 ms latency. + 2 + + + 10S_LAT + 10 s latency. + 3 + + + + + TIMECTRL + Time Control mode. + [31:30] + read-only + + + DIS + No timing control mode is enabled. + 0 + + + SYNC + Synchronous Mode is enabled. + 1 + + + ASYNC + Asynchronous Mode is enabled. + 2 + + + BOTH + Both synchronous and asynchronous modes are enabled. + 3 + + + + + + + TARG_CTRL1 + Target Control 1 Register. + 0x00C + + + EVENT + Sets respecive I3C target event request. + [1:0] + read-write + + + NORMAL + Normal mode. + 0 + + + IBI + Generate an IBI on the I3C bus. + 1 + + + CONTREQ + Request control of the I3C bus. + 2 + + + HJ + Generate a Hot-Join request. + 3 + + + + + EXTIBI + Indicates there are extended IBI data bytes. + [3:3] + read-write + + + DYNADDR_IDX + Index of dynamic address for the current IBI request. + [7:4] + read-write + + + IBIDATA + Contains the mandatory data byte to be sent when generating an IBI. + [15:8] + read-write + + + + + TARG_INTEN + Target Interrupt Enable Register. + 0x010 + read-write + + + START + START detected. + [8:8] + + + ADDRMATCH + Address matched interrupt. + [9:9] + + + STOP + STOP detected. + [10:10] + + + RX_RDY + Receive data ready. + [11:11] + + + TX_NFULL + Ready for transmit data, + [12:12] + + + DYNADDR_CHG + Dynamic Address Changed interrupt enable. + [13:13] + + + CCC + CCC Reveived Interrupt. + [14:14] + + + ERRWARN + Error or warning interrupt. + [15:15] + + + CCCH_DONE + CCC Handled Interrupt. + [17:17] + + + EVENT_REQ + Event Reqeusted Interrupt. + [18:18] + + + TARG_RST + I3C Target Reset Interrupt. + [19:19] + + + + + TARG_INTCLR + Target Interrupt Clear Register. + 0x014 + write-only + + + START + START detected. + [8:8] + + + ADDRMATCH + Address matched interrupt. + [9:9] + + + STOP + STOP detected. + [10:10] + + + RX_RDY + Receive data ready. + [11:11] + + + TX_NFULL + Ready for transmit data, + [12:12] + + + DYNADDR_CHG + Dynamic Address Changed interrupt enable. + [13:13] + + + CCC + CCC Reveived Interrupt. + [14:14] + + + ERRWARN + Error or warning interrupt. + [15:15] + + + CCCH_DONE + CCC Handled Interrupt. + [17:17] + + + EVENT_REQ + Event Reqeusted Interrupt. + [18:18] + + + TARG_RST + I3C Target Reset Interrupt. + [19:19] + + + + + TARG_INTFL + Target Interrupt Flag Register. + 0x018 + read-only + + + START + START detected. + [8:8] + + + ADDRMATCH + Address matched interrupt. + [9:9] + + + STOP + STOP detected. + [10:10] + + + RX_RDY + Receive data ready. + [11:11] + + + TX_NFULL + Ready for transmit data, + [12:12] + + + DYNADDR_CHG + Dynamic Address Changed interrupt enable. + [13:13] + + + CCC + CCC Reveived Interrupt. + [14:14] + + + ERRWARN + Error or warning interrupt. + [15:15] + + + CCCH_DONE + CCC Handled Interrupt. + [17:17] + + + EVENT_REQ + Event Reqeusted Interrupt. + [18:18] + + + TARG_RST + I3C Target Reset Interrupt. + [19:19] + + + + + TARG_ERRWARN + Target Error and Warning Register. + 0x01C + read-write + + + OVR + Internal FIFO overrun flag. + [0:0] + + + UNR + Internal FIFO underrun flag. + [1:1] + + + UNR_NACK + I3C or I2C mode address emitted by the IP was NACKed by the targets. + [2:2] + + + CONT_RX_TERM + Controller terminated read in message mode. + [3:3] + + + INVSTART + Invalid START. + [4:4] + + + SDR_PAR + SDR Parity Error. + [8:8] + + + TO + Timeout Error. + [11:11] + + + RX_UNR + Read data underrun. + [16:16] + + + TX_OVR + Write data overrun. + [17:17] + + + + + TARG_DMACTRL + Target DMA Control Register. + 0x020 + read-write + + + RX_EN + DMA read enable. + [1:0] + + + DIS + Disable DMA. + 0 + + + ONE_FR + Enable DMA for one frame. + 1 + + + EN + Enable DMA until disabled by setting this field to 0b00. + 2 + + + + + TX_EN + DMA write enable. + [3:2] + + + DIS + Disable DMA. + 0 + + + ONE_FR + Enable DMA for one frame. + 1 + + + EN + Enable DMA until disabled by setting this field to 0b00. + 2 + + + + + WIDTH + Selects the data width for DMA transfers. + [5:4] + + + BYTE + Byte size. + 0 + + + HALFWORD + Halfword size. + 2 + + + + + + + TARG_FIFOCTRL + Target FIFO Control Register. + 0x02C + + + TX_FLUSH + Flush TX FIFO. + [0:0] + write-only + + + RX_FLUSH + Flush RX FIFO. + [1:1] + write-only + + + UNLOCK + Unlock FIFO Triggers. + [3:3] + write-only + + + TX_THD_LVL + TX FIFO trigger level. + [5:4] + read-write + + + EMPTY + Trigger when empty. + 0 + + + QUARTER_FULL + Trigger when quarter full or less. + 1 + + + HALF_FULL + Trigger when half full or less. + 2 + + + ALMOST_FULL + Trigger when almost full or less. + 3 + + + + + RX_THD_LVL + RX FIFO trigger level. + [7:6] + read-write + + + NOT_EMPTY + Trigger when empty. + 0 + + + QUARTER_FULL + Trigger when quarter full or less. + 1 + + + HALF_FULL + Trigger when half full or less. + 2 + + + 3_QUARTER_FULL + Trigger when 3 quarters full or less. + 3 + + + + + TX_LVL + Number of messages in TX FIFO. + [21:16] + read-only + + + RX_LVL + Number of messages in RX FIFO. + [29:24] + read-only + + + TX_FULL + TX FIFO Full flag. + [30:30] + read-only + + + RX_EM + RX FIFO Empty Flag. + [31:31] + read-only + + + + + TARG_TXFIFO8 + Target Write Byte Data Register. + 0x030 + write-only + + + DATA + Data byte to send. + [7:0] + + + END + End of data. + [8:8] + + + END2 + End of data. + [16:16] + + + + + TARG_TXFIFO8E + Target Write Byte Data as End Register. + 0x034 + write-only + + + DATA + Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location. + [7:0] + + + + + TARG_TXFIFO16 + Target Write Half-Word Data Register. + 0x038 + write-only + + + DATA + Data halfword to send. + [15:0] + + + END + End of data. + [16:16] + + + + + TARG_TXFIFO16E + Target Write Half-Word Data as End Register. + 0x03C + write-only + + + DATA + Data halfword to send. + [15:0] + + + + + TARG_RXFIFO8 + Target Read Byte Data Register. + 0x040 + read-only + + + DATA + Read data byte from RX FIFO. + [7:0] + + + + + TARG_RXFIFO16 + Target Read Half-Word Data Register. + 0x048 + read-only + + + DATA + Read data hyalfword from RX FIFO. + [15:0] + + + + + TARG_TXFIFO8O + Target Byte-Only Write Byte Data Register. + 0x054 + write-only + + + DATA + Data byte to send. + [7:0] + + + + + TARG_CAP0 + Target Capabilities 0 Register. + 0x05C + read-only + + + MAPCNT + Number of mapped target addresses supported. + [3:0] + + + I2C_10BADDR + I2C 10-bit address support. + [4:4] + + + I2C_SWRST + I2C Software Reset Support. + [5:5] + + + I2C_DEVID + I2C Device ID Support. + [6:6] + + + FIFO32_REG + FIFO 32 registers available. + [7:7] + + + EXTIBI + Extended IBI data support. + [8:8] + + + EXTIBI_REG + Extended IBI data register support. + [9:9] + + + HDRBT_LANES + Multi-lane support for HDR-BT mode. + [13:12] + + + CCC_V1_1 + CCC V1.1 Support. + [16:16] + + + TARG_RST + Target Reset Support. + [17:17] + + + GROUPADDR + Group address support. + [19:18] + + + AASA_CCC + SETAASA CCC Support. + [21:21] + + + T2T_SUBSC + Target-to-target subscriber support. + [22:22] + + + T2T_WR + Target-to-target write support. + [23:23] + + + + + TARG_CAP1 + TARG_Capabilities 1 Register. + 0x060 + read-only + + + PROVID + Provisioned ID implementation. + [1:0] + + + PROVID_REG + Provision ID, Bus Characteristics, Device Characteristics implementation. + [5:2] + + + HDR_MODES + Supported HDR modes. + [8:6] + + + CONT + Controller mode capable. + [9:9] + + + STATADDR + I2C-style static address implementation. + [11:10] + + + CCCH + CCC Handled by IP. + [15:12] + + + IBI_EVENTS + Supported IBI events. + [20:16] + + + TIMECTRL + Timing Control Support. + [21:21] + + + EXTFIFO + External FIFO configuration. + [25:23] + + + TXFIFO_CFG + TX FIFO configuration. + [27:26] + + + RXFIFO_CFG + RX FIFO configuration. + [29:28] + + + INTR + Interrupt support. + [30:30] + + + DMA + DMA support. + [31:31] + + + + + TARG_DYNADDR + Target Dynamic Address Register. + 0x064 + read-write + + + VALID + Address valid check. + [0:0] + + + ADDR + The assigned dynamic address. + [7:1] + + + CAUSE + Indicates how the last primary dynnamic address value change occurred. + [10:8] + + + + + TARG_MAXLIMITS + Maximum Limits Register. + 0x068 + read-write + + + RX + The maximum number of bytes that the I3C controller may read from this I3C target device per message. + [11:0] + + + TX + The maximum number of bytes that the I3C controller may write from this I3C target device per message. + [27:16] + + + + + TARG_IDEXT + ID Extension Register. + 0x070 + read-write + + + DEVCHAR + Device Characteristics Register. + [15:8] + + + BUSCHAR + Bus Characteristics Register. + [23:16] + + + + + TARG_MSGLAST + Target Matching Address Index Register. + 0x07C + read-only + + + IDX + Index or group number of last matched address. + [3:0] + + + STATADDR + Last matched address was a I2C static address. + [4:4] + + + GROUP + Last matched address was a group address. + [5:5] + + + MODE + Indicates the mode of the last access. + [7:6] + + + DYN_STAT_ADDR + I3C SDR or I2C + 0 + + + HDR_DDR + HDR-DDR. + 1 + + + HDR_BT + HDR-BT. + 2 + + + + + PREV_IDX + Index or group number of previous matched address. + [11:8] + + + PREV_GROUP + Last matched address was a previous group address. + [13:13] + + + PREV_MODE + Indicates the mode of the previous access. + [15:14] + + + DYN_STAT_ADDR + I3C SDR or I2C + 0 + + + HDR_DDR + HDR-DDR. + 1 + + + HDR_BT + HDR-BT. + 2 + + + + + SECPREV_IDX + Index or group number of secondary previous matched address. + [19:16] + + + SECPREV_GROUP + Last matched address was a secondary previous group address. + [21:21] + + + SECPREV_MODE + Indicates the mode of the secondary previous access. + [23:22] + + + DYN_STAT_ADDR + I3C SDR or I2C + 0 + + + HDR_DDR + HDR-DDR. + 1 + + + HDR_BT + HDR-BT. + 2 + + + + + + + CONT_CTRL1 + Controller Control 1 Register. + 0x084 + + + REQ + Requests an I3C or I2C bus operation. + [2:0] + read-write + + + NONE + None operation. + 0 + + + EMIT_START + Emit a START with address and read-write bit from stopped state or in the middle of an SDR message. + 1 + + + EMIT_STOP + Emit a STOP. + 2 + + + IBI_ACKNACK + Manually ACK or NACK an IBI. + 3 + + + PROCESS_DAA + Process Dynamic Address Assignment. + 4 + + + EXIT_RST + Emit HDR Exit Pattern or Target Reset pattern. + 6 + + + AUTO_IBI + Automatic IBI response. + 7 + + + + + TYPE + Controls type of operation for REQ field. + [5:4] + read-write + + + IBIRESP + Response to use when an IBI occurs. + [7:6] + read-write + + + RDWR_DIR + Direction of the transfer. + [8:8] + read-write + + + ADDR + Address to send with START. + [15:9] + read-write + + + TERM_RD + Termination count for read. + [23:16] + read-write + + + + + CONT_STATUS + Controller Status Register. + 0x088 + + + STATE + Current working state. + [2:0] + read-only + + + IDLE + Bus Idle. + 0 + + + TARG_REQ + I3C Bus i stopped and a target is holding SDA low. + 1 + + + SDR_TXSDRMSG + SDR Message Mode using SDRMSG registers. + 2 + + + SDR_NORM + Normal SDR message mode. + 3 + + + DDR + DDR Message mode + 4 + + + DAA + Dynamic Address Assignment mode. + 5 + + + IBI_ACKNACK + IP is waiting for the application to provide an ACK or NACK decision. + 6 + + + IBI_RX + IP is receiving an IBI. + 7 + + + + + WAIT + Depending on STATE, WAIT is 1 when it's waiting in an intermediary state. + [4:4] + read-only + + + NACK + Address was NACKed. + [5:5] + read-only + + + IBITYPE + The type of event for which arbitration was last won. + [7:6] + + + NONE + None. + 0 + + + IBI + In-band Interrupt. + 1 + + + CONT_REQ + Controller request. + 1 + + + HOTJOIN_REQ + Hot-Join request. + 1 + + + + + TARG_START + Target START detected. + [8:8] + + + REQ_DONE + CTRL1 Request completed. + [9:9] + read-only + + + DONE + Message completed. + [10:10] + read-write + + + RX_RDY + Receive data ready. + [11:11] + read-only + + + TX_NFULL + TX FIFO Not Full flag. + [12:12] + read-only + + + IBI_WON + IBI Arbitration won. + [13:13] + read-write + + + ERRWARN + Error or warning status. + [15:15] + read-only + + + CONT_TRANS + IP transitioned from I3C target to controller. + [19:19] + read-write + + + IBI_ADDR + The address of a received IBI or dcontroller request. + [30:24] + read-only + + + + + CONT_IBIRULES + Controller IBI Registry and Rules Register. + 0x08C + + + ADDR0 + Target 0 dynamic address. + [5:0] + read-write + + + ADDR1 + Target 1 dynamic address. + [11:6] + read-write + + + ADDR2 + Target 2 dynamic address. + [17:12] + read-write + + + ADDR3 + Target 3 dynamic address. + [23:18] + read-write + + + ADDR4 + Target 4 dynamic address. + [29:24] + read-write + + + MSB0 + Implementation of MSb for I3C dynamic addresses. + [30:30] + read-write + + + NOBYTE + Specifies the function of ADDR0 to ADDR4 + [31:31] + read-write + + + + + CONT_INTEN + Controller Interrupt Enable Register. + 0x090 + read-write + + + TARG_START + Target Start Detected. + [8:8] + + + REQ_DONE + CTRL request completed. + [9:9] + + + DONE + Message complete. + [10:10] + + + RX_RDY + Receive data ready. + [11:11] + + + TX_NFULL + Ready for transmit data, + [12:12] + + + IBI_WON + IBI arbitration won. + [13:13] + + + ERRWARN + Error or warning interrupt. + [15:15] + + + NOW_CONT + The IP transitioned from I3C bus target to I3C bus controller. + [19:19] + + + + + CONT_INTCLR + Controller Interrupt Clear Register. + 0x094 + write-only + + + TARG_START + Target Start Detected. + [8:8] + + + REQ_DONE + CTRL request completed. + [9:9] + + + DONE + Message complete. + [10:10] + + + RX_RDY + Receive data ready. + [11:11] + + + TX_NFULL + Ready for transmit data, + [12:12] + + + IBI_WON + IBI arbitration won. + [13:13] + + + ERRWARN + Error or warning interrupt. + [15:15] + + + NOW_CONT + The IP transitioned from I3C bus target to I3C bus controller. + [19:19] + + + + + CONT_INTFL + Controller Interrupt Flag Register. + 0x098 + read-only + + + TARG_START + Target Start Detected. + [8:8] + + + REQ_DONE + CTRL request completed. + [9:9] + + + DONE + Message complete. + [10:10] + + + RX_RDY + Receive data ready. + [11:11] + + + TX_NFULL + Ready for transmit data, + [12:12] + + + IBI_WON + IBI arbitration won. + [13:13] + + + ERRWARN + Error or warning interrupt. + [15:15] + + + NOW_CONT + The IP transitioned from I3C bus target to I3C bus controller. + [19:19] + + + + + CONT_ERRWARN + Controller Error and Warning Register. + 0x09C + read-write + + + NACK + I3C or I2C mode address emitted by the IP was NACKed by the targets. + [2:2] + + + TX_ABT + Write aborted due to data NACK. + [3:3] + + + RX_TERM + Controller terminated read in messaage mode. + [4:4] + + + HDR_PAR + HDR Parity Error. + [9:9] + + + HDR_CRC + HDR-DDR CRC Error. + [10:10] + + + RX_UNR + Read data underrun. + [16:16] + + + TX_OVR + Write data overrun. + [17:17] + + + MSG + Message mode error. + [18:18] + + + INV_REQ + Invalid use of request from CTRL register. + [19:19] + + + TO + Timeout error. + [20:20] + + + + + CONT_DMACTRL + Controller DMA Control Register. + 0x0A0 + read-write + + + RX_EN + DMA read enable. + [1:0] + + + DIS + Disable DMA. + 0 + + + ONE_FR + Enable DMA for one frame. + 1 + + + EN + Enable DMA until disabled by setting this field to 0b00. + 2 + + + + + TX_EN + DMA write enable. + [3:2] + + + DIS + Disable DMA. + 0 + + + ONE_FR + Enable DMA for one frame. + 1 + + + EN + Enable DMA until disabled by setting this field to 0b00. + 2 + + + + + WIDTH + Selects the data width for DMA transfers. + [5:4] + + + BYTE + Byte size. + 0 + + + HALFWORD + Halfword size. + 2 + + + + + + + CONT_FIFOCTRL + Controller FIFO Control Register. + 0x0AC + + + TX_FLUSH + Flush TX FIFO. + [0:0] + write-only + + + RX_FLUSH + Flush RX FIFO. + [1:1] + write-only + + + UNLOCK + Unlock FIFO Triggers. + [3:3] + write-only + + + TX_THD_LVL + TX FIFO trigger level. + [5:4] + read-write + + + EMPTY + Trigger when empty. + 0 + + + QUARTER_FULL + Trigger when quarter full or less. + 1 + + + HALF_FULL + Trigger when half full or less. + 2 + + + ALMOST_FULL + Trigger when almost full or less. + 3 + + + + + RX_THD_LVL + RX FIFO trigger level. + [7:6] + read-write + + + NOT_EMPTY + Trigger when empty. + 0 + + + QUARTER_FULL + Trigger when quarter full or less. + 1 + + + HALF_FULL + Trigger when half full or less. + 2 + + + 3_QUARTER_FULL + Trigger when 3 quarters full or less. + 3 + + + + + TX_LVL + Number of messages in TX FIFO. + [21:16] + read-only + + + RX_LVL + Number of messages in RX FIFO. + [29:24] + read-only + + + TX_FULL + TX FIFO Full flag. + [30:30] + read-only + + + RX_EM + RX FIFO Empty Flag. + [31:31] + read-only + + + + + CONT_TXFIFO8 + Controller Write Byte Data Register. + 0x0B0 + write-only + + + DATA + Data byte to send. + [7:0] + + + END + End of data. + [8:8] + + + END2 + End of data. + [16:16] + + + + + CONT_TXFIFO8E + Controller Write Byte Data as End Register. + 0x0B4 + write-only + + + DATA + Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location. + [7:0] + + + + + CONT_TXFIFO16 + Controller Write Half-Word Data Register. + 0x0B8 + write-only + + + DATA + Data halfword to send. + [15:0] + + + END + End of data. + [16:16] + + + + + CONT_TXFIFO16E + Controller Write Half-Word Data as End Register. + 0x0BC + write-only + + + DATA + Data halfword to send. + [15:0] + + + + + CONT_RXFIFO8 + Controller Read Byte Data Register. + 0x0C0 + read-only + + + DATA + Read data byte from RX FIFO. + [7:0] + + + + + CONT_RXFIFO16 + Controller Read Half-Word Data Register. + 0x0C8 + read-only + + + DATA + Read data hyalfword from RX FIFO. + [15:0] + + + + + CONT_TXFIFO8O + Controller Byte-Only Write Byte Data Register. + 0x0CC + write-only + + + DATA + Data byte to send. + [7:0] + + + + + CONT_TXSDRMSG_CTRL + Controller Start or Continue SDR Message Register. + 0x0D0 + read-write + + + RDWR_DIR + Direction of the transfer. + [0:0] + + + ADDR + Destination address of message. + [7:1] + + + END + Select how to end message. + [8:8] + + + I2C_EN + I2C Mode Enable. + [10:10] + + + LEN + Message length in bytes. + [15:11] + + + + + CONT_TXSDRMSG_FIFO + Controller Start or Continue SDR Message Register. + 0x0D0 + write-only + + + DATA + Data for SDR write message after control information has been written. + [15:0] + + + + + CONT_RXSDRMSG + Controller Read SDR Message Data Register. + 0x0D4 + read-only + + + DATA + Data for SDR write message after control information has been written. + [15:0] + + + + + CONT_TXDDRMSG + Controller Start or Continue DDR Message Register. + 0x0D8 + write-only + + + MSG + Data, address/command, and control information. + [15:0] + + + + + CONT_RXDDR16 + Controller Read DDR Message Data Register. + 0x0DC + read-only + + + DATA + Read data (16bits). + [15:0] + + + + + CONT_DYNADDR + Controller Dynamic Address Register. + 0x0E4 + read-write + + + ADDR + The assigned dynamic address. + [7:1] + + + VALID + Address valid check. + [8:8] + + + + + TARG_GROUPDEF + Target Group Definition Register. + 0x114 + read-only + + + ADDR_EN + Group Address enable. + [0:0] + + + ADDR + Group Address . + [7:1] + + + + + TARG_MAPCTRL0 + Target Primary Map Control Register. + 0x11C + read-write + + + DYNADDR_EN + Dynamic address is enabled. + [0:0] + + + DYNADDR + Dynamic address. + [7:1] + + + CAUSE + Indicates how the last primary dynamic address value change occurred. + [10:8] + + + + + TARG_MAPCTRL1 + Target Map Control 1 Register. + 0x120 + read-write + + + EN + Mapped address slot is enabled. + [0:0] + + + ADDR + Static or Dynamic address. + [7:1] + + + STATADDR_EN + ADDR field contains the I2C static address if enabled. + [8:8] + + + STATADDR_10B + Contains the upper 3 bits of a 10-bit I2C Static Address. + [11:9] + + + NACK + Indicates how the last primary dynamic address value change occurred. + [12:12] + + + + + TARG_MAPCTRL2 + Target Map Control 2 Register. + 0x124 + read-write + + + EN + Mapped address slot is enabled. + [0:0] + + + ADDR + Static or Dynamic address. + [7:1] + + + STATADDR_EN + ADDR field contains the I2C static address if enabled. + [8:8] + + + NACK + Indicates how the last primary dynamic address value change occurred. + [12:12] + + + AUTO_EN + Enable slot for automatic dynamic address assignment. + [13:13] + + + PID + Indicates how the last primary dynamic address value change occurred. + [31:14] + + + + + + + + ICC + Instruction Cache Controller Registers + 0x5002A000 + + 0x00 + 0x1000 + registers + + + + INFO + Cache ID Register. + 0x0000 + read-only + 32 + + + RELNUM + Release Number. Identifies the RTL release version. + 0 + 6 + + + PARTNUM + Part Number. This field reflects the value of C_ID_PART_NUMBER configuration parameter. + 6 + 4 + + + ID + Cache ID. This field reflects the value of the C_ID_CACHEID configuration parameter. + 10 + 6 + + + + + SZ + Memory Configuration Register. + 0x0004 + read-only + 0x00080008 + 32 + + + CCH + Cache Size. Indicates total size in Kbytes of cache. + 0 + 16 + + + MEM + Main Memory Size. Indicates the total size, in units of 128 Kbytes, of code memory accessible to the cache controller. + 16 + 16 + + + + + CTRL + Cache Control and Status Register. + 0x0100 + 32 + + + EN + Cache Enable. Controls whether the cache is bypassed or is in use. Changing the state of this bit will cause the instruction cache to be flushed and its contents invalidated. + 0 + 1 + + + dis + Cache Bypassed. Instruction data is stored in the line fill buffer but is not written to main cache memory array. + 0 + + + en + Cache Enabled. + 1 + + + + + RDY + Cache Ready flag. Cleared by hardware when at any time the cache as a whole is invalidated (including a system reset). When this bit is 0, the cache is effectively in bypass mode (instruction fetches will come from main memory or from the line fill buffer). Set by hardware when the invalidate operation is complete and the cache is ready. + 16 + 1 + read-only + + + notReady + Not Ready. + 0 + + + ready + Ready. + 1 + + + + + + + WAY + Cache Way Control Register. + 0x0200 + 32 + + + WAY + Number of cache way, default is always 2. Allowed values are 1,2,4. + 0 + 3 + + + 1 + 1 + 1 + + + 2 + 2 + 2 + + + 4 + 4 + 4 + + + + + + + REGCTRL + Regional Control Register. + 0x0204 + 32 + + + EN + Enable the regional high andlow bound compare, cache the data only if the TAG content between the high and low bound. + 0 + 8 + + + EXC + Cache the data only if the TAG content is excluded in the high and low bound. + 8 + 8 + + - 15 - 0x20 + 4 + 8 REGION[%s] Regional Low and High Bound Registers. icc_reg 0x0208 + 64 read-write LBOUND Regional Low Bound Register. 0x0000 + 32 BOUND @@ -3491,6 +5940,7 @@ HBOUND DMA Channel Status Register. 0x004 + 32 BOUND @@ -3505,6 +5955,7 @@ PFMCTRL Performance Control Register. 0x0300 + 32 EN @@ -3518,6 +5969,7 @@ PFMCNT Performance Counter Register. 0x0304 + 32 CNT @@ -3532,6 +5984,7 @@ Invalidate All Registers. 0x0700 read-write + 32 INVALID @@ -3547,7 +6000,7 @@ MCR Misc Control. - 0x40006C00 + 0x50006C00 0x00 0x400 @@ -3685,7 +6138,7 @@ PWRSEQ Power Sequencer / Low Power Control Register. - 0x40006800 + 0x50006800 0x00 0x400 @@ -3831,10 +6284,286 @@ + + MPC + Memory Protection Controller. + 0x50091000 + + 0x00 + 0x1000 + registers + + + + CTRL + Control Register. + 0x0000 + 32 + + + SEC_ERR + Security Error Response COnfiguration. + 4 + 1 + + + DATAIF_REQ + Data interface gating request. + 6 + 1 + + + DATAIF_ACK + Data interface gating acknowledged. + 7 + 1 + + + AUTO_INC + Auto-increment. + 8 + 1 + + + SEC_LOCKDOWN + Security Lockdown. + 31 + 1 + + + + + BLK_MAX + Maximum value of block-based index register. + 0x0010 + 32 + read-only + + + VAL + Maximum value of block-based index register. + 0 + 32 + + + + + BLK_CFG + Block Control Register. + 0x0014 + 32 + read-only + + + SIZE + Block Size. + 0 + 4 + + + INIT_ST + Initialization in progress. + 31 + 1 + + + + + BLK_IDX + Block Index Register. + 0x0018 + + + IDX + Index value for accessing block-based lookup table. + 0 + 32 + + + + + BLK_LUT + Block-based gating Look Up Table Register. + 0x001C + + + ACCESS + Each bit indicates one block, based on the index pointed by the BLKIDX register. + 0 + 32 + + + + + INT_STAT + Interrupt Flag Register. + 0x0020 + read-only + + + MPC_IRQ + MPC IRQ triggered. + 0 + 1 + + + + + INT_CLEAR + Interrupt Clear Register. + 0x0024 + write-only + + + MPC_IRQ + MPC IRQ Clear. + 0 + 1 + + + + + INT_EN + Interrupt Enable Register. + 0x0028 + + + MPC_IRQ + MPC IRQ Enable. + 0 + 1 + + + + + INT_INFO1 + Interrupt Info 1 Register. + 0x002C + read-only + + + HADDR + AHB bus signals: Address bus. + 0 + 32 + + + + + INT_INFO2 + Interrupt Info 2 Register. + 0x0030 + read-only + + + HMASTER + AHB bus signals: Master Select. + 0 + 16 + + + HNONSEC + AHB bus signals: Indicates the current transfer is either a Non-Secure or Secure transfer. + 16 + 1 + + + CFG_NS + Security state. + 17 + 1 + + + + + INT_SET + Interrupt Set Debug Register. + 0x0034 + write-only + + + MPC_IRQ + MPC IRQ Set. + 0 + 1 + + + + + PIDR4 + Peripheral ID 4 Register. + 0x0FD0 + read-only + + + PIDR0 + Peripheral ID 0 Register. + 0x0FE0 + read-only + + + PIDR1 + Peripheral ID 1 Register. + 0x0FE4 + read-only + + + PIDR2 + Peripheral ID 2 Register. + 0x0FE8 + read-only + + + PIDR3 + Peripheral ID 3 Register. + 0x0FEC + read-only + + + 4 + 4 + CIDR[%s] + Component ID register. + 0x0FF0 + read-only + + + + + + MPC1 + Memory Protection Controller. 1 + 0x50092000 + + + + MPC2 + Memory Protection Controller. 2 + 0x50093000 + + + + MPC3 + Memory Protection Controller. 3 + 0x50094000 + + + + MPC4 + Memory Protection Controller. 4 + 0x50095000 + + + + MPC5 + Memory Protection Controller. 5 + 0x50096000 + + RTC Real Time Clock and Alarm. - 0x40006000 + 0x50006000 0x00 0x400 @@ -4245,7 +6974,7 @@ architect to decide how and when the semaphores are used and how they are allocated. Existing hardware does not have to be modified for this type of cooperative sharing, and the use of semaphores is exclusively within the software domain. - 0x4003E000 + 0x5003E000 0x00 0x1000 @@ -4383,7 +7112,7 @@ SIMO Single Inductor Multiple Output Switching Converter - 0x40004400 + 0x50004400 0x00 0x400 @@ -4790,7 +7519,7 @@ SIR System Initialization Registers. - 0x40000400 + 0x50000400 read-only 0x00 @@ -4801,7 +7530,7 @@ SISTAT System Initialization Status Register. - 0x00 + 0x000 read-only @@ -4849,7 +7578,7 @@ ADDR Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1). - 0x04 + 0x004 read-only @@ -4859,6 +7588,32 @@ + + BTLELDO_BB + BTLE LDO TRIM BB Register. + 0x01C + + + TRIM + Target 0.9V. VDDA BB Voltage Trim. + 0 + 5 + + + + + BTLELDO_RF + BTLE LDO TRIM RF Register. + 0x002C + + + TRIM + Target 0.9V. VDDA RF Voltage Trim. + 0 + 5 + + + SFSTAT Security function status register. @@ -5018,7 +7773,7 @@ APBPPC Interrupt Status of APB PPC for targets on APB bus. Each bit ties to an individual PPC in the system. 0 - 2 + 4 @@ -5032,7 +7787,7 @@ APBPPC Interrupt Clear of APB PPC for targets on the APB bus. Each bit ties to an individual PPC in the system. 0 - 2 + 4 @@ -5045,7 +7800,7 @@ APBPPC Interrupt Enable for APB PPC for targets on the APB bus. Each bit ties to an individual PPC in the system. 0 - 2 + 4 @@ -5144,28 +7899,28 @@ - GPIO0 - Secure GPIO0 Configuration Register. - 0x0180 + AHBMPRIV + AHB Privileged/Non-privileged Secure DMA Access. + 0x0170 - PINS - Each bit configures a GPIO pin as secore or non-secure on GPIO Port 0. Secure GPIO pins prevent software from reading GPIO Data In pin states. + DMA + Controls access of transactions coming from the Secure DMA. 0 - 12 + 1 - GPIO1 - Secure GPIO1 Configuration Register. - 0x0184 + GPIO0 + Secure GPIO0 Configuration Register. + 0x0180 PINS Each bit configures a GPIO pin as secore or non-secure on GPIO Port 0. Secure GPIO pins prevent software from reading GPIO Data In pin states. 0 - 2 + 14 @@ -5195,13 +7950,26 @@ + + AHBMPRIV + AHB Privileged/Non-Privileged Non-Secure DMA Access Register. + 0x0170 + + + DMA + Control access for transactions coming from the Non-Secure DMA. + 1 + 1 + + + SPI SPI peripheral. - 0x400BE000 + 0x500BE000 0x00 0x1000 @@ -5288,7 +8056,7 @@ - CTRLR_MODE + CONT_MODE Controller Mode Enable. 1 1 @@ -5955,7 +8723,7 @@ - CTRLR_DONE + CONT_DONE Controller Done, set when SPI Controller has completed any transactions. 11 1 @@ -6172,7 +8940,7 @@ - CTRLR_DONE + CONT_DONE Controller Done interrupt enable. 11 1 @@ -6435,7 +9203,7 @@ TMR Low-Power Configurable Timer - 0x40010000 + 0x50010000 0x00 0x1000 @@ -7092,7 +9860,7 @@ TMR1 Low-Power Configurable Timer 1 - 0x40011000 + 0x50011000 TMR1 TMR1 IRQ @@ -7103,7 +9871,7 @@ TMR2 Low-Power Configurable Timer 2 - 0x40012000 + 0x50012000 TMR2 TMR2 IRQ @@ -7114,7 +9882,7 @@ TMR3 Low-Power Configurable Timer 3 - 0x40013000 + 0x50013000 TMR3 TMR3 IRQ @@ -7125,7 +9893,7 @@ TMR4 Low-Power Configurable Timer 4 - 0x40080C00 + 0x50080C00 TMR4 TMR4 IRQ @@ -7136,7 +9904,7 @@ TMR5 Low-Power Configurable Timer 5 - 0x40081000 + 0x50081000 TMR5 TMR5 IRQ @@ -7147,7 +9915,7 @@ TRIMSIR Trim System Initilazation Registers - 0x40005400 + 0x50005400 0x00 0x400 @@ -7325,7 +10093,7 @@ TRNG Random Number Generator. - 0x4004D000 + 0x5004D000 0x00 0x1000 @@ -7671,7 +10439,7 @@ UART UART Low Power Registers - 0x40042000 + 0x50042000 0x00 0x1000 @@ -8150,7 +10918,7 @@ WDT Windowed Watchdog Timer - 0x40003000 + 0x50003000 0x00 0x0400 @@ -8741,7 +11509,7 @@ WUT 32-bit reloadable timer that can be used for timing and wakeup. - 0x40006400 + 0x50006400 0x00 0x400 diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mpc_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mpc_regs.h new file mode 100644 index 00000000..e1d10ec0 --- /dev/null +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/mpc_regs.h @@ -0,0 +1,269 @@ +/** + * @file mpc_regs.h + * @brief Registers, Bit Masks and Bit Positions for the MPC Peripheral Module. + * @note This file is @generated. + * @ingroup mpc_registers + */ + +/****************************************************************************** + * + * Copyright (C) 2024 Analog Devices, Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + ******************************************************************************/ + +#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_MPC_REGS_H_ +#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_MPC_REGS_H_ + +/* **** Includes **** */ +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined (__ICCARM__) + #pragma system_include +#endif + +#if defined (__CC_ARM) + #pragma anon_unions +#endif +/// @cond +/* + If types are not defined elsewhere (CMSIS) define them here +*/ +#ifndef __IO +#define __IO volatile +#endif +#ifndef __I +#define __I volatile const +#endif +#ifndef __O +#define __O volatile +#endif +#ifndef __R +#define __R volatile const +#endif +/// @endcond + +/* **** Definitions **** */ + +/** + * @ingroup mpc + * @defgroup mpc_registers MPC_Registers + * @brief Registers, Bit Masks and Bit Positions for the MPC Peripheral Module. + * @details Memory Protection Controller. + */ + +/** + * @ingroup mpc_registers + * Structure type to access the MPC Registers. + */ +typedef struct { + __IO uint32_t ctrl; /**< \b 0x0000: MPC CTRL Register */ + __R uint32_t rsv_0x4_0xf[3]; + __I uint32_t blk_max; /**< \b 0x0010: MPC BLK_MAX Register */ + __I uint32_t blk_cfg; /**< \b 0x0014: MPC BLK_CFG Register */ + __IO uint32_t blk_idx; /**< \b 0x0018: MPC BLK_IDX Register */ + __IO uint32_t blk_lut; /**< \b 0x001C: MPC BLK_LUT Register */ + __I uint32_t int_stat; /**< \b 0x0020: MPC INT_STAT Register */ + __O uint32_t int_clear; /**< \b 0x0024: MPC INT_CLEAR Register */ + __IO uint32_t int_en; /**< \b 0x0028: MPC INT_EN Register */ + __I uint32_t int_info1; /**< \b 0x002C: MPC INT_INFO1 Register */ + __I uint32_t int_info2; /**< \b 0x0030: MPC INT_INFO2 Register */ + __O uint32_t int_set; /**< \b 0x0034: MPC INT_SET Register */ + __R uint32_t rsv_0x38_0xfcf[998]; + __I uint32_t pidr4; /**< \b 0x0FD0: MPC PIDR4 Register */ + __R uint32_t rsv_0xfd4_0xfdf[3]; + __I uint32_t pidr0; /**< \b 0x0FE0: MPC PIDR0 Register */ + __I uint32_t pidr1; /**< \b 0x0FE4: MPC PIDR1 Register */ + __I uint32_t pidr2; /**< \b 0x0FE8: MPC PIDR2 Register */ + __I uint32_t pidr3; /**< \b 0x0FEC: MPC PIDR3 Register */ + __I uint32_t cidr[4]; /**< \b 0x0FF0: MPC CIDR Register */ +} mxc_mpc_regs_t; + +/* Register offsets for module MPC */ +/** + * @ingroup mpc_registers + * @defgroup MPC_Register_Offsets Register Offsets + * @brief MPC Peripheral Register Offsets from the MPC Base Peripheral Address. + * @{ + */ +#define MXC_R_MPC_CTRL ((uint32_t)0x00000000UL) /**< Offset from MPC Base Address: 0x0000 */ +#define MXC_R_MPC_BLK_MAX ((uint32_t)0x00000010UL) /**< Offset from MPC Base Address: 0x0010 */ +#define MXC_R_MPC_BLK_CFG ((uint32_t)0x00000014UL) /**< Offset from MPC Base Address: 0x0014 */ +#define MXC_R_MPC_BLK_IDX ((uint32_t)0x00000018UL) /**< Offset from MPC Base Address: 0x0018 */ +#define MXC_R_MPC_BLK_LUT ((uint32_t)0x0000001CUL) /**< Offset from MPC Base Address: 0x001C */ +#define MXC_R_MPC_INT_STAT ((uint32_t)0x00000020UL) /**< Offset from MPC Base Address: 0x0020 */ +#define MXC_R_MPC_INT_CLEAR ((uint32_t)0x00000024UL) /**< Offset from MPC Base Address: 0x0024 */ +#define MXC_R_MPC_INT_EN ((uint32_t)0x00000028UL) /**< Offset from MPC Base Address: 0x0028 */ +#define MXC_R_MPC_INT_INFO1 ((uint32_t)0x0000002CUL) /**< Offset from MPC Base Address: 0x002C */ +#define MXC_R_MPC_INT_INFO2 ((uint32_t)0x00000030UL) /**< Offset from MPC Base Address: 0x0030 */ +#define MXC_R_MPC_INT_SET ((uint32_t)0x00000034UL) /**< Offset from MPC Base Address: 0x0034 */ +#define MXC_R_MPC_PIDR4 ((uint32_t)0x00000FD0UL) /**< Offset from MPC Base Address: 0x0FD0 */ +#define MXC_R_MPC_PIDR0 ((uint32_t)0x00000FE0UL) /**< Offset from MPC Base Address: 0x0FE0 */ +#define MXC_R_MPC_PIDR1 ((uint32_t)0x00000FE4UL) /**< Offset from MPC Base Address: 0x0FE4 */ +#define MXC_R_MPC_PIDR2 ((uint32_t)0x00000FE8UL) /**< Offset from MPC Base Address: 0x0FE8 */ +#define MXC_R_MPC_PIDR3 ((uint32_t)0x00000FECUL) /**< Offset from MPC Base Address: 0x0FEC */ +#define MXC_R_MPC_CIDR ((uint32_t)0x00000FF0UL) /**< Offset from MPC Base Address: 0x0FF0 */ +/**@} end of group mpc_registers */ + +/** + * @ingroup mpc_registers + * @defgroup MPC_CTRL MPC_CTRL + * @brief Control Register. + * @{ + */ +#define MXC_F_MPC_CTRL_SEC_ERR_POS 4 /**< CTRL_SEC_ERR Position */ +#define MXC_F_MPC_CTRL_SEC_ERR ((uint32_t)(0x1UL << MXC_F_MPC_CTRL_SEC_ERR_POS)) /**< CTRL_SEC_ERR Mask */ + +#define MXC_F_MPC_CTRL_DATAIF_REQ_POS 6 /**< CTRL_DATAIF_REQ Position */ +#define MXC_F_MPC_CTRL_DATAIF_REQ ((uint32_t)(0x1UL << MXC_F_MPC_CTRL_DATAIF_REQ_POS)) /**< CTRL_DATAIF_REQ Mask */ + +#define MXC_F_MPC_CTRL_DATAIF_ACK_POS 7 /**< CTRL_DATAIF_ACK Position */ +#define MXC_F_MPC_CTRL_DATAIF_ACK ((uint32_t)(0x1UL << MXC_F_MPC_CTRL_DATAIF_ACK_POS)) /**< CTRL_DATAIF_ACK Mask */ + +#define MXC_F_MPC_CTRL_AUTO_INC_POS 8 /**< CTRL_AUTO_INC Position */ +#define MXC_F_MPC_CTRL_AUTO_INC ((uint32_t)(0x1UL << MXC_F_MPC_CTRL_AUTO_INC_POS)) /**< CTRL_AUTO_INC Mask */ + +#define MXC_F_MPC_CTRL_SEC_LOCKDOWN_POS 31 /**< CTRL_SEC_LOCKDOWN Position */ +#define MXC_F_MPC_CTRL_SEC_LOCKDOWN ((uint32_t)(0x1UL << MXC_F_MPC_CTRL_SEC_LOCKDOWN_POS)) /**< CTRL_SEC_LOCKDOWN Mask */ + +/**@} end of group MPC_CTRL_Register */ + +/** + * @ingroup mpc_registers + * @defgroup MPC_BLK_MAX MPC_BLK_MAX + * @brief Maximum value of block-based index register. + * @{ + */ +#define MXC_F_MPC_BLK_MAX_VAL_POS 0 /**< BLK_MAX_VAL Position */ +#define MXC_F_MPC_BLK_MAX_VAL ((uint32_t)(0xFFFFFFFFUL << MXC_F_MPC_BLK_MAX_VAL_POS)) /**< BLK_MAX_VAL Mask */ + +/**@} end of group MPC_BLK_MAX_Register */ + +/** + * @ingroup mpc_registers + * @defgroup MPC_BLK_CFG MPC_BLK_CFG + * @brief Block Control Register. + * @{ + */ +#define MXC_F_MPC_BLK_CFG_SIZE_POS 0 /**< BLK_CFG_SIZE Position */ +#define MXC_F_MPC_BLK_CFG_SIZE ((uint32_t)(0xFUL << MXC_F_MPC_BLK_CFG_SIZE_POS)) /**< BLK_CFG_SIZE Mask */ + +#define MXC_F_MPC_BLK_CFG_INIT_ST_POS 31 /**< BLK_CFG_INIT_ST Position */ +#define MXC_F_MPC_BLK_CFG_INIT_ST ((uint32_t)(0x1UL << MXC_F_MPC_BLK_CFG_INIT_ST_POS)) /**< BLK_CFG_INIT_ST Mask */ + +/**@} end of group MPC_BLK_CFG_Register */ + +/** + * @ingroup mpc_registers + * @defgroup MPC_BLK_IDX MPC_BLK_IDX + * @brief Block Index Register. + * @{ + */ +#define MXC_F_MPC_BLK_IDX_IDX_POS 0 /**< BLK_IDX_IDX Position */ +#define MXC_F_MPC_BLK_IDX_IDX ((uint32_t)(0xFFFFFFFFUL << MXC_F_MPC_BLK_IDX_IDX_POS)) /**< BLK_IDX_IDX Mask */ + +/**@} end of group MPC_BLK_IDX_Register */ + +/** + * @ingroup mpc_registers + * @defgroup MPC_BLK_LUT MPC_BLK_LUT + * @brief Block-based gating Look Up Table Register. + * @{ + */ +#define MXC_F_MPC_BLK_LUT_ACCESS_POS 0 /**< BLK_LUT_ACCESS Position */ +#define MXC_F_MPC_BLK_LUT_ACCESS ((uint32_t)(0xFFFFFFFFUL << MXC_F_MPC_BLK_LUT_ACCESS_POS)) /**< BLK_LUT_ACCESS Mask */ + +/**@} end of group MPC_BLK_LUT_Register */ + +/** + * @ingroup mpc_registers + * @defgroup MPC_INT_STAT MPC_INT_STAT + * @brief Interrupt Flag Register. + * @{ + */ +#define MXC_F_MPC_INT_STAT_MPC_IRQ_POS 0 /**< INT_STAT_MPC_IRQ Position */ +#define MXC_F_MPC_INT_STAT_MPC_IRQ ((uint32_t)(0x1UL << MXC_F_MPC_INT_STAT_MPC_IRQ_POS)) /**< INT_STAT_MPC_IRQ Mask */ + +/**@} end of group MPC_INT_STAT_Register */ + +/** + * @ingroup mpc_registers + * @defgroup MPC_INT_CLEAR MPC_INT_CLEAR + * @brief Interrupt Clear Register. + * @{ + */ +#define MXC_F_MPC_INT_CLEAR_MPC_IRQ_POS 0 /**< INT_CLEAR_MPC_IRQ Position */ +#define MXC_F_MPC_INT_CLEAR_MPC_IRQ ((uint32_t)(0x1UL << MXC_F_MPC_INT_CLEAR_MPC_IRQ_POS)) /**< INT_CLEAR_MPC_IRQ Mask */ + +/**@} end of group MPC_INT_CLEAR_Register */ + +/** + * @ingroup mpc_registers + * @defgroup MPC_INT_EN MPC_INT_EN + * @brief Interrupt Enable Register. + * @{ + */ +#define MXC_F_MPC_INT_EN_MPC_IRQ_POS 0 /**< INT_EN_MPC_IRQ Position */ +#define MXC_F_MPC_INT_EN_MPC_IRQ ((uint32_t)(0x1UL << MXC_F_MPC_INT_EN_MPC_IRQ_POS)) /**< INT_EN_MPC_IRQ Mask */ + +/**@} end of group MPC_INT_EN_Register */ + +/** + * @ingroup mpc_registers + * @defgroup MPC_INT_INFO1 MPC_INT_INFO1 + * @brief Interrupt Info 1 Register. + * @{ + */ +#define MXC_F_MPC_INT_INFO1_HADDR_POS 0 /**< INT_INFO1_HADDR Position */ +#define MXC_F_MPC_INT_INFO1_HADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_MPC_INT_INFO1_HADDR_POS)) /**< INT_INFO1_HADDR Mask */ + +/**@} end of group MPC_INT_INFO1_Register */ + +/** + * @ingroup mpc_registers + * @defgroup MPC_INT_INFO2 MPC_INT_INFO2 + * @brief Interrupt Info 2 Register. + * @{ + */ +#define MXC_F_MPC_INT_INFO2_HMASTER_POS 0 /**< INT_INFO2_HMASTER Position */ +#define MXC_F_MPC_INT_INFO2_HMASTER ((uint32_t)(0xFFFFUL << MXC_F_MPC_INT_INFO2_HMASTER_POS)) /**< INT_INFO2_HMASTER Mask */ + +#define MXC_F_MPC_INT_INFO2_HNONSEC_POS 16 /**< INT_INFO2_HNONSEC Position */ +#define MXC_F_MPC_INT_INFO2_HNONSEC ((uint32_t)(0x1UL << MXC_F_MPC_INT_INFO2_HNONSEC_POS)) /**< INT_INFO2_HNONSEC Mask */ + +#define MXC_F_MPC_INT_INFO2_CFG_NS_POS 17 /**< INT_INFO2_CFG_NS Position */ +#define MXC_F_MPC_INT_INFO2_CFG_NS ((uint32_t)(0x1UL << MXC_F_MPC_INT_INFO2_CFG_NS_POS)) /**< INT_INFO2_CFG_NS Mask */ + +/**@} end of group MPC_INT_INFO2_Register */ + +/** + * @ingroup mpc_registers + * @defgroup MPC_INT_SET MPC_INT_SET + * @brief Interrupt Set Debug Register. + * @{ + */ +#define MXC_F_MPC_INT_SET_MPC_IRQ_POS 0 /**< INT_SET_MPC_IRQ Position */ +#define MXC_F_MPC_INT_SET_MPC_IRQ ((uint32_t)(0x1UL << MXC_F_MPC_INT_SET_MPC_IRQ_POS)) /**< INT_SET_MPC_IRQ Mask */ + +/**@} end of group MPC_INT_SET_Register */ + +#ifdef __cplusplus +} +#endif + +#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_MPC_REGS_H_ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/nspc_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/nspc_regs.h index b5505f3d..263fdbf6 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/nspc_regs.h +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/nspc_regs.h @@ -74,6 +74,8 @@ extern "C" { typedef struct { __R uint32_t rsv_0x0_0x15f[88]; __IO uint32_t apbpriv; /**< \b 0x0160: NSPC APBPRIV Register */ + __R uint32_t rsv_0x164_0x16f[3]; + __IO uint32_t ahbmpriv; /**< \b 0x0170: NSPC AHBMPRIV Register */ } mxc_nspc_regs_t; /* Register offsets for module NSPC */ @@ -84,6 +86,7 @@ typedef struct { * @{ */ #define MXC_R_NSPC_APBPRIV ((uint32_t)0x00000160UL) /**< Offset from NSPC Base Address: 0x0160 */ +#define MXC_R_NSPC_AHBMPRIV ((uint32_t)0x00000170UL) /**< Offset from NSPC Base Address: 0x0170 */ /**@} end of group nspc_registers */ /** @@ -97,6 +100,17 @@ typedef struct { /**@} end of group NSPC_APBPRIV_Register */ +/** + * @ingroup nspc_registers + * @defgroup NSPC_AHBMPRIV NSPC_AHBMPRIV + * @brief AHB Privileged/Non-Privileged Non-Secure DMA Access Register. + * @{ + */ +#define MXC_F_NSPC_AHBMPRIV_DMA_POS 1 /**< AHBMPRIV_DMA Position */ +#define MXC_F_NSPC_AHBMPRIV_DMA ((uint32_t)(0x1UL << MXC_F_NSPC_AHBMPRIV_DMA_POS)) /**< AHBMPRIV_DMA Mask */ + +/**@} end of group NSPC_AHBMPRIV_Register */ + #ifdef __cplusplus } #endif diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/partition_max32657.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/partition_max32657.h deleted file mode 100644 index a948716c..00000000 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/partition_max32657.h +++ /dev/null @@ -1,1286 +0,0 @@ -/***************************************************************************** - * @file partition_max32657.h - * @brief CMSIS-Core(M) Device Initial Setup for Secure/Non-Secure Zones for - * MAX32657 - * @version V1.0.0 - * @date 20. January 2021 - *****************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * Portions Copyright (C) 2024 Analog Devices, Inc. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_PARTITION_MAX32657_H_ -#define LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_PARTITION_MAX32657_H_ - -#include "max32657.h" - -// clang-format off -#if IS_SECURE_ENVIRONMENT - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ----------------- -*/ - -/* -// Enable SAU -// Value for SAU->CTRL register bit ENABLE -*/ -#define SAU_INIT_CTRL_ENABLE 1 - -/* -// When SAU is disabled -// <0=> All Memory is Secure -// <1=> All Memory is Non-Secure -// Value for SAU->CTRL register bit ALLNS -// When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration. -*/ -#define SAU_INIT_CTRL_ALLNS 0 - -/* -// -*/ - -/* -// Initialize Security Attribution Unit (SAU) Address Regions -// SAU configuration specifies regions to be one of: -// - Secure and Non-Secure Callable -// - Non-Secure -// Note: All memory regions not configured by SAU are Secure -*/ -/** - * Analog Devices, Inc. - * 4 Regions in the MAX32657. - * 1. Non-Secure Flash - * 2. Secure Flash - * 3. Non-Secure SRAM - * 4. Secure SRAM - * - * Finer grain control can be achieved depending on the application - * requirements by updating the regions of this file. - * - * Non-Secure Flash (1MB) 0x0100.0000 - 0x010F.FFFF - * Non-Secure SRAM0 (32kB) 0x2000.0000 - 0x2000.7FFF - * Non-Secure SRAM1 (32kB) 0x2000.8000 - 0x2000.FFFF - * Non-Secure SRAM2 (64kB) 0x2001.0000 - 0x2001.FFFF - * Non-Secure SRAM3 (64kB) 0x2002.0000 - 0x2002.FFFF - * Non-Secure SRAM4 (64kB) 0x2003.0000 - 0x2003.FFFF - * - * Secure Flash (1MB) 0x1100.0000 - 0x110F.FFFF - * Secure SRAM0 (32kB) 0x3000.0000 - 0x3000.7FFF - * Secure SRAM1 (32kB) 0x3000.8000 - 0x3000.FFFF - * Secure SRAM2 (64kB) 0x3001.0000 - 0x3001.FFFF - * Secure SRAM3 (64kB) 0x3002.0000 - 0x3002.FFFF - * Secure SRAM4 (64kB) 0x3003.0000 - 0x3003.FFFF - */ -#define SAU_REGIONS_MAX 4 /* Max. number of SAU regions */ - -/* -// Initialize SAU Region 0 (Secure Flash) -// Setup SAU Region 0 memory attributes -*/ -#define SAU_INIT_REGION0 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START0 0x11000000 /* start address of SAU region 0 (ROM) */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END0 0x110FFFFF /* end address of SAU region 0 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC0 1 -/* -// -*/ - -/* -// Initialize SAU Region 1 (Non-Secure Flash) -// Setup SAU Region 1 memory attributes -*/ -#define SAU_INIT_REGION1 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START1 0x01000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END1 0x010FFFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC1 0 -/* -// -*/ - -/* -// Initialize SAU Region 2 (Secure SRAM) -// Setup SAU Region 2 memory attributes -*/ -#define SAU_INIT_REGION2 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START2 0x30000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END2 0x3003FFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC2 1 -/* -// -*/ - -/* -// Initialize SAU Region 3 (Non-Secure SRAM) -// Setup SAU Region 3 memory attributes -*/ -#define SAU_INIT_REGION3 1 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START3 0x20000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END3 0x2003FFFF - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC3 0 -/* -// -*/ - -/* -// Initialize SAU Region 4 -// Setup SAU Region 4 memory attributes -*/ -#define SAU_INIT_REGION4 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START4 0x00000000 /* start address of SAU region 4 */ - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END4 0x00000000 /* end address of SAU region 4 */ - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC4 0 -/* -// -*/ - -/* -// Initialize SAU Region 5 -// Setup SAU Region 5 memory attributes -*/ -#define SAU_INIT_REGION5 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START5 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END5 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC5 0 -/* -// -*/ - -/* -// Initialize SAU Region 6 -// Setup SAU Region 6 memory attributes -*/ -#define SAU_INIT_REGION6 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START6 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END6 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC6 0 -/* -// -*/ - -/* -// Initialize SAU Region 7 -// Setup SAU Region 7 memory attributes -*/ -#define SAU_INIT_REGION7 0 - -/* -// Start Address <0-0xFFFFFFE0> -*/ -#define SAU_INIT_START7 0x00000000 - -/* -// End Address <0x1F-0xFFFFFFFF> -*/ -#define SAU_INIT_END7 0x00000000 - -/* -// Region is -// <0=>Non-Secure -// <1=>Secure, Non-Secure Callable -*/ -#define SAU_INIT_NSC7 0 -/* -// -*/ - -/* -// -*/ - -/* -// Setup behaviour of Sleep and Exception Handling -*/ -#define SCB_CSR_AIRCR_INIT 1 - -/* -// Deep Sleep can be enabled by -// <0=>Secure and Non-Secure state -// <1=>Secure state only -// Value for SCB->CSR register bit DEEPSLEEPS -*/ -#define SCB_CSR_DEEPSLEEPS_VAL 1 - -/* -// System reset request accessible from -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for SCB->AIRCR register bit SYSRESETREQS -*/ -#define SCB_AIRCR_SYSRESETREQS_VAL 1 - -/* -// Priority of Non-Secure exceptions is -// <0=> Not altered -// <1=> Lowered to 0x80-0xFF -// Value for SCB->AIRCR register bit PRIS -*/ -#define SCB_AIRCR_PRIS_VAL 1 - -/* -// BusFault, HardFault, and NMI target -// <0=> Secure state -// <1=> Non-Secure state -// Value for SCB->AIRCR register bit BFHFNMINS -*/ -#define SCB_AIRCR_BFHFNMINS_VAL 0 - -/* -// -*/ - -/* -// Setup behaviour of Floating Point and Vector Unit (FPU/MVE) -*/ -#define TZ_FPU_NS_USAGE 1 - -/* -// Floating Point and Vector Unit usage -// <0=> Secure state only -// <3=> Secure and Non-Secure state -// Value for SCB->NSACR register bits CP10, CP11 -*/ -#define SCB_NSACR_CP10_11_VAL 3 - -/* -// Treat floating-point registers as Secure -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit TS -*/ -#define FPU_FPCCR_TS_VAL 0 - -/* -// Clear on return (CLRONRET) accessibility -// <0=> Secure and Non-Secure state -// <1=> Secure state only -// Value for FPU->FPCCR register bit CLRONRETS -*/ -#define FPU_FPCCR_CLRONRETS_VAL 0 - -/* -// Clear floating-point caller saved registers on exception return -// <0=> Disabled -// <1=> Enabled -// Value for FPU->FPCCR register bit CLRONRET -*/ -#define FPU_FPCCR_CLRONRET_VAL 1 - -/* -// -*/ - -/* -// Setup Interrupt Target -*/ - -/* -// Initialize ITNS 0 (Interrupts 0..31) -*/ -#define NVIC_INIT_ITNS0 1 - -/* -// Interrupts 0..31 -// ICE Unlock <0=> Secure state <1=> Non-Secure state -// Watchdog Timer <0=> Secure state <1=> Non-Secure state -// Real Time Clock <0=> Secure state <1=> Non-Secure state -// True Random Number Generator <0=> Secure state <1=> Non-Secure state -// Timer 0 <0=> Secure state <1=> Non-Secure state -// Timer 1 <0=> Secure state <1=> Non-Secure state -// Timer 2 <0=> Secure state <1=> Non-Secure state -// Timer 3 <0=> Secure state <1=> Non-Secure state -// Timer 4 <0=> Secure state <1=> Non-Secure state -// Timer 5 <0=> Secure state <1=> Non-Secure state -// I3C <0=> Secure state <1=> Non-Secure state -// UART <0=> Secure state <1=> Non-Secure state -// SPI <0=> Secure state <1=> Non-Secure state -// Flash Controller <0=> Secure state <1=> Non-Secure state -// GPIO0 <0=> Secure state <1=> Non-Secure state -// Reserved (15) <0=> Secure state <1=> Non-Secure state -// DMA0 Channel 0 <0=> Secure state <1=> Non-Secure state -// DMA0 Channel 1 <0=> Secure state <1=> Non-Secure state -// DMA0 Channel 2 <0=> Secure state <1=> Non-Secure state -// DMA0 Channel 3 <0=> Secure state <1=> Non-Secure state -// DMA1 Channel 0 <0=> Secure state <1=> Non-Secure state -// DMA1 Channel 1 <0=> Secure state <1=> Non-Secure state -// DMA1 Channel 2 <0=> Secure state <1=> Non-Secure state -// DMA1 Channel 3 <0=> Secure state <1=> Non-Secure state -// Wakeup Timer 0 <0=> Secure state <1=> Non-Secure state -// Wakeup Timer 1 <0=> Secure state <1=> Non-Secure state -// GPIO Wake <0=> Secure state <1=> Non-Secure state -// CRC <0=> Secure state <1=> Non-Secure state -// AES <0=> Secure state <1=> Non-Secure state -// ERFO Ready <0=> Secure state <1=> Non-Secure state -// Boost Controller <0=> Secure state <1=> Non-Secure state -// ECC <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS0_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 1 (Interrupts 32..63) -*/ -#define NVIC_INIT_ITNS1 1 - -/* -// Interrupts 32..63 -// BTLE XXXX0 <0=> Secure state <1=> Non-Secure state -// BTLE XXXX1 <0=> Secure state <1=> Non-Secure state -// BTLE XXXX2 <0=> Secure state <1=> Non-Secure state -// BTLE XXXX3 <0=> Secure state <1=> Non-Secure state -// BTLE XXXX4 <0=> Secure state <1=> Non-Secure state -// BTLE XXXX5 <0=> Secure state <1=> Non-Secure state -// BTLE XXXX6 <0=> Secure state <1=> Non-Secure state -// BTLE XXXX7 <0=> Secure state <1=> Non-Secure state -// BTLE XXXX8 <0=> Secure state <1=> Non-Secure state -// BTLE XXXX9 <0=> Secure state <1=> Non-Secure state -// BTLE XXXXA <0=> Secure state <1=> Non-Secure state -// BTLE XXXXB <0=> Secure state <1=> Non-Secure state -// BTLE XXXXC <0=> Secure state <1=> Non-Secure state -// BTLE XXXXD <0=> Secure state <1=> Non-Secure state -// BTLE XXXXE <0=> Secure state <1=> Non-Secure state -// Reserved (47) <0=> Secure state <1=> Non-Secure state -// MPC Combined (Secure) <0=> Secure state <1=> Non-Secure state -// PPC Combined (Secure) <0=> Secure state <1=> Non-Secure state -// Reserved (50) <0=> Secure state <1=> Non-Secure state -// Reserved (51) <0=> Secure state <1=> Non-Secure state -// Reserved (52) <0=> Secure state <1=> Non-Secure state -// Reserved (53) <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS1_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 2 (Interrupts 64..95) -*/ -#define NVIC_INIT_ITNS2 0 - -/* -// Interrupts 64..95 -// Interrupt 64 <0=> Secure state <1=> Non-Secure state -// Interrupt 65 <0=> Secure state <1=> Non-Secure state -// Interrupt 66 <0=> Secure state <1=> Non-Secure state -// Interrupt 67 <0=> Secure state <1=> Non-Secure state -// Interrupt 68 <0=> Secure state <1=> Non-Secure state -// Interrupt 69 <0=> Secure state <1=> Non-Secure state -// Interrupt 70 <0=> Secure state <1=> Non-Secure state -// Interrupt 71 <0=> Secure state <1=> Non-Secure state -// Interrupt 72 <0=> Secure state <1=> Non-Secure state -// Interrupt 73 <0=> Secure state <1=> Non-Secure state -// Interrupt 74 <0=> Secure state <1=> Non-Secure state -// Interrupt 75 <0=> Secure state <1=> Non-Secure state -// Interrupt 76 <0=> Secure state <1=> Non-Secure state -// Interrupt 77 <0=> Secure state <1=> Non-Secure state -// Interrupt 78 <0=> Secure state <1=> Non-Secure state -// Interrupt 79 <0=> Secure state <1=> Non-Secure state -// Interrupt 80 <0=> Secure state <1=> Non-Secure state -// Interrupt 81 <0=> Secure state <1=> Non-Secure state -// Interrupt 82 <0=> Secure state <1=> Non-Secure state -// Interrupt 83 <0=> Secure state <1=> Non-Secure state -// Interrupt 84 <0=> Secure state <1=> Non-Secure state -// Interrupt 85 <0=> Secure state <1=> Non-Secure state -// Interrupt 86 <0=> Secure state <1=> Non-Secure state -// Interrupt 87 <0=> Secure state <1=> Non-Secure state -// Interrupt 88 <0=> Secure state <1=> Non-Secure state -// Interrupt 89 <0=> Secure state <1=> Non-Secure state -// Interrupt 90 <0=> Secure state <1=> Non-Secure state -// Interrupt 91 <0=> Secure state <1=> Non-Secure state -// Interrupt 92 <0=> Secure state <1=> Non-Secure state -// Interrupt 93 <0=> Secure state <1=> Non-Secure state -// Interrupt 94 <0=> Secure state <1=> Non-Secure state -// Interrupt 95 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS2_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 3 (Interrupts 96..127) -*/ -#define NVIC_INIT_ITNS3 0 - -/* -// Interrupts 96..127 -// Interrupt 96 <0=> Secure state <1=> Non-Secure state -// Interrupt 97 <0=> Secure state <1=> Non-Secure state -// Interrupt 98 <0=> Secure state <1=> Non-Secure state -// Interrupt 99 <0=> Secure state <1=> Non-Secure state -// Interrupt 100 <0=> Secure state <1=> Non-Secure state -// Interrupt 101 <0=> Secure state <1=> Non-Secure state -// Interrupt 102 <0=> Secure state <1=> Non-Secure state -// Interrupt 103 <0=> Secure state <1=> Non-Secure state -// Interrupt 104 <0=> Secure state <1=> Non-Secure state -// Interrupt 105 <0=> Secure state <1=> Non-Secure state -// Interrupt 106 <0=> Secure state <1=> Non-Secure state -// Interrupt 107 <0=> Secure state <1=> Non-Secure state -// Interrupt 108 <0=> Secure state <1=> Non-Secure state -// Interrupt 109 <0=> Secure state <1=> Non-Secure state -// Interrupt 110 <0=> Secure state <1=> Non-Secure state -// Interrupt 111 <0=> Secure state <1=> Non-Secure state -// Interrupt 112 <0=> Secure state <1=> Non-Secure state -// Interrupt 113 <0=> Secure state <1=> Non-Secure state -// Interrupt 114 <0=> Secure state <1=> Non-Secure state -// Interrupt 115 <0=> Secure state <1=> Non-Secure state -// Interrupt 116 <0=> Secure state <1=> Non-Secure state -// Interrupt 117 <0=> Secure state <1=> Non-Secure state -// Interrupt 118 <0=> Secure state <1=> Non-Secure state -// Interrupt 119 <0=> Secure state <1=> Non-Secure state -// Interrupt 120 <0=> Secure state <1=> Non-Secure state -// Interrupt 121 <0=> Secure state <1=> Non-Secure state -// Interrupt 122 <0=> Secure state <1=> Non-Secure state -// Interrupt 123 <0=> Secure state <1=> Non-Secure state -// Interrupt 124 <0=> Secure state <1=> Non-Secure state -// Interrupt 125 <0=> Secure state <1=> Non-Secure state -// Interrupt 126 <0=> Secure state <1=> Non-Secure state -// Interrupt 127 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS3_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 4 (Interrupts 128..159) -*/ -#define NVIC_INIT_ITNS4 0 - -/* -// Interrupts 128..159 -// Interrupt 128 <0=> Secure state <1=> Non-Secure state -// Interrupt 129 <0=> Secure state <1=> Non-Secure state -// Interrupt 130 <0=> Secure state <1=> Non-Secure state -// Interrupt 131 <0=> Secure state <1=> Non-Secure state -// Interrupt 132 <0=> Secure state <1=> Non-Secure state -// Interrupt 133 <0=> Secure state <1=> Non-Secure state -// Interrupt 134 <0=> Secure state <1=> Non-Secure state -// Interrupt 135 <0=> Secure state <1=> Non-Secure state -// Interrupt 136 <0=> Secure state <1=> Non-Secure state -// Interrupt 137 <0=> Secure state <1=> Non-Secure state -// Interrupt 138 <0=> Secure state <1=> Non-Secure state -// Interrupt 139 <0=> Secure state <1=> Non-Secure state -// Interrupt 140 <0=> Secure state <1=> Non-Secure state -// Interrupt 141 <0=> Secure state <1=> Non-Secure state -// Interrupt 142 <0=> Secure state <1=> Non-Secure state -// Interrupt 143 <0=> Secure state <1=> Non-Secure state -// Interrupt 144 <0=> Secure state <1=> Non-Secure state -// Interrupt 145 <0=> Secure state <1=> Non-Secure state -// Interrupt 146 <0=> Secure state <1=> Non-Secure state -// Interrupt 147 <0=> Secure state <1=> Non-Secure state -// Interrupt 148 <0=> Secure state <1=> Non-Secure state -// Interrupt 149 <0=> Secure state <1=> Non-Secure state -// Interrupt 150 <0=> Secure state <1=> Non-Secure state -// Interrupt 151 <0=> Secure state <1=> Non-Secure state -// Interrupt 152 <0=> Secure state <1=> Non-Secure state -// Interrupt 153 <0=> Secure state <1=> Non-Secure state -// Interrupt 154 <0=> Secure state <1=> Non-Secure state -// Interrupt 155 <0=> Secure state <1=> Non-Secure state -// Interrupt 156 <0=> Secure state <1=> Non-Secure state -// Interrupt 157 <0=> Secure state <1=> Non-Secure state -// Interrupt 158 <0=> Secure state <1=> Non-Secure state -// Interrupt 159 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS4_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 5 (Interrupts 160..191) -*/ -#define NVIC_INIT_ITNS5 0 - -/* -// Interrupts 160..191 -// Interrupt 160 <0=> Secure state <1=> Non-Secure state -// Interrupt 161 <0=> Secure state <1=> Non-Secure state -// Interrupt 162 <0=> Secure state <1=> Non-Secure state -// Interrupt 163 <0=> Secure state <1=> Non-Secure state -// Interrupt 164 <0=> Secure state <1=> Non-Secure state -// Interrupt 165 <0=> Secure state <1=> Non-Secure state -// Interrupt 166 <0=> Secure state <1=> Non-Secure state -// Interrupt 167 <0=> Secure state <1=> Non-Secure state -// Interrupt 168 <0=> Secure state <1=> Non-Secure state -// Interrupt 169 <0=> Secure state <1=> Non-Secure state -// Interrupt 170 <0=> Secure state <1=> Non-Secure state -// Interrupt 171 <0=> Secure state <1=> Non-Secure state -// Interrupt 172 <0=> Secure state <1=> Non-Secure state -// Interrupt 173 <0=> Secure state <1=> Non-Secure state -// Interrupt 174 <0=> Secure state <1=> Non-Secure state -// Interrupt 175 <0=> Secure state <1=> Non-Secure state -// Interrupt 176 <0=> Secure state <1=> Non-Secure state -// Interrupt 177 <0=> Secure state <1=> Non-Secure state -// Interrupt 178 <0=> Secure state <1=> Non-Secure state -// Interrupt 179 <0=> Secure state <1=> Non-Secure state -// Interrupt 180 <0=> Secure state <1=> Non-Secure state -// Interrupt 181 <0=> Secure state <1=> Non-Secure state -// Interrupt 182 <0=> Secure state <1=> Non-Secure state -// Interrupt 183 <0=> Secure state <1=> Non-Secure state -// Interrupt 184 <0=> Secure state <1=> Non-Secure state -// Interrupt 185 <0=> Secure state <1=> Non-Secure state -// Interrupt 186 <0=> Secure state <1=> Non-Secure state -// Interrupt 187 <0=> Secure state <1=> Non-Secure state -// Interrupt 188 <0=> Secure state <1=> Non-Secure state -// Interrupt 189 <0=> Secure state <1=> Non-Secure state -// Interrupt 190 <0=> Secure state <1=> Non-Secure state -// Interrupt 191 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS5_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 6 (Interrupts 192..223) -*/ -#define NVIC_INIT_ITNS6 0 - -/* -// Interrupts 192..223 -// Interrupt 192 <0=> Secure state <1=> Non-Secure state -// Interrupt 193 <0=> Secure state <1=> Non-Secure state -// Interrupt 194 <0=> Secure state <1=> Non-Secure state -// Interrupt 195 <0=> Secure state <1=> Non-Secure state -// Interrupt 196 <0=> Secure state <1=> Non-Secure state -// Interrupt 197 <0=> Secure state <1=> Non-Secure state -// Interrupt 198 <0=> Secure state <1=> Non-Secure state -// Interrupt 199 <0=> Secure state <1=> Non-Secure state -// Interrupt 200 <0=> Secure state <1=> Non-Secure state -// Interrupt 201 <0=> Secure state <1=> Non-Secure state -// Interrupt 202 <0=> Secure state <1=> Non-Secure state -// Interrupt 203 <0=> Secure state <1=> Non-Secure state -// Interrupt 204 <0=> Secure state <1=> Non-Secure state -// Interrupt 205 <0=> Secure state <1=> Non-Secure state -// Interrupt 206 <0=> Secure state <1=> Non-Secure state -// Interrupt 207 <0=> Secure state <1=> Non-Secure state -// Interrupt 208 <0=> Secure state <1=> Non-Secure state -// Interrupt 209 <0=> Secure state <1=> Non-Secure state -// Interrupt 210 <0=> Secure state <1=> Non-Secure state -// Interrupt 211 <0=> Secure state <1=> Non-Secure state -// Interrupt 212 <0=> Secure state <1=> Non-Secure state -// Interrupt 213 <0=> Secure state <1=> Non-Secure state -// Interrupt 214 <0=> Secure state <1=> Non-Secure state -// Interrupt 215 <0=> Secure state <1=> Non-Secure state -// Interrupt 216 <0=> Secure state <1=> Non-Secure state -// Interrupt 217 <0=> Secure state <1=> Non-Secure state -// Interrupt 218 <0=> Secure state <1=> Non-Secure state -// Interrupt 219 <0=> Secure state <1=> Non-Secure state -// Interrupt 220 <0=> Secure state <1=> Non-Secure state -// Interrupt 221 <0=> Secure state <1=> Non-Secure state -// Interrupt 222 <0=> Secure state <1=> Non-Secure state -// Interrupt 223 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS6_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 7 (Interrupts 224..255) -*/ -#define NVIC_INIT_ITNS7 0 - -/* -// Interrupts 224..255 -// Interrupt 224 <0=> Secure state <1=> Non-Secure state -// Interrupt 225 <0=> Secure state <1=> Non-Secure state -// Interrupt 226 <0=> Secure state <1=> Non-Secure state -// Interrupt 227 <0=> Secure state <1=> Non-Secure state -// Interrupt 228 <0=> Secure state <1=> Non-Secure state -// Interrupt 229 <0=> Secure state <1=> Non-Secure state -// Interrupt 230 <0=> Secure state <1=> Non-Secure state -// Interrupt 231 <0=> Secure state <1=> Non-Secure state -// Interrupt 232 <0=> Secure state <1=> Non-Secure state -// Interrupt 233 <0=> Secure state <1=> Non-Secure state -// Interrupt 234 <0=> Secure state <1=> Non-Secure state -// Interrupt 235 <0=> Secure state <1=> Non-Secure state -// Interrupt 236 <0=> Secure state <1=> Non-Secure state -// Interrupt 237 <0=> Secure state <1=> Non-Secure state -// Interrupt 238 <0=> Secure state <1=> Non-Secure state -// Interrupt 239 <0=> Secure state <1=> Non-Secure state -// Interrupt 240 <0=> Secure state <1=> Non-Secure state -// Interrupt 241 <0=> Secure state <1=> Non-Secure state -// Interrupt 242 <0=> Secure state <1=> Non-Secure state -// Interrupt 243 <0=> Secure state <1=> Non-Secure state -// Interrupt 244 <0=> Secure state <1=> Non-Secure state -// Interrupt 245 <0=> Secure state <1=> Non-Secure state -// Interrupt 246 <0=> Secure state <1=> Non-Secure state -// Interrupt 247 <0=> Secure state <1=> Non-Secure state -// Interrupt 248 <0=> Secure state <1=> Non-Secure state -// Interrupt 249 <0=> Secure state <1=> Non-Secure state -// Interrupt 250 <0=> Secure state <1=> Non-Secure state -// Interrupt 251 <0=> Secure state <1=> Non-Secure state -// Interrupt 252 <0=> Secure state <1=> Non-Secure state -// Interrupt 253 <0=> Secure state <1=> Non-Secure state -// Interrupt 254 <0=> Secure state <1=> Non-Secure state -// Interrupt 255 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS7_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 8 (Interrupts 256..287) -*/ -#define NVIC_INIT_ITNS8 0 - -/* -// Interrupts 256..287 -// Interrupt 256 <0=> Secure state <1=> Non-Secure state -// Interrupt 257 <0=> Secure state <1=> Non-Secure state -// Interrupt 258 <0=> Secure state <1=> Non-Secure state -// Interrupt 259 <0=> Secure state <1=> Non-Secure state -// Interrupt 260 <0=> Secure state <1=> Non-Secure state -// Interrupt 261 <0=> Secure state <1=> Non-Secure state -// Interrupt 262 <0=> Secure state <1=> Non-Secure state -// Interrupt 263 <0=> Secure state <1=> Non-Secure state -// Interrupt 264 <0=> Secure state <1=> Non-Secure state -// Interrupt 265 <0=> Secure state <1=> Non-Secure state -// Interrupt 266 <0=> Secure state <1=> Non-Secure state -// Interrupt 267 <0=> Secure state <1=> Non-Secure state -// Interrupt 268 <0=> Secure state <1=> Non-Secure state -// Interrupt 269 <0=> Secure state <1=> Non-Secure state -// Interrupt 270 <0=> Secure state <1=> Non-Secure state -// Interrupt 271 <0=> Secure state <1=> Non-Secure state -// Interrupt 272 <0=> Secure state <1=> Non-Secure state -// Interrupt 273 <0=> Secure state <1=> Non-Secure state -// Interrupt 274 <0=> Secure state <1=> Non-Secure state -// Interrupt 275 <0=> Secure state <1=> Non-Secure state -// Interrupt 276 <0=> Secure state <1=> Non-Secure state -// Interrupt 277 <0=> Secure state <1=> Non-Secure state -// Interrupt 278 <0=> Secure state <1=> Non-Secure state -// Interrupt 279 <0=> Secure state <1=> Non-Secure state -// Interrupt 280 <0=> Secure state <1=> Non-Secure state -// Interrupt 281 <0=> Secure state <1=> Non-Secure state -// Interrupt 282 <0=> Secure state <1=> Non-Secure state -// Interrupt 283 <0=> Secure state <1=> Non-Secure state -// Interrupt 284 <0=> Secure state <1=> Non-Secure state -// Interrupt 285 <0=> Secure state <1=> Non-Secure state -// Interrupt 286 <0=> Secure state <1=> Non-Secure state -// Interrupt 287 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS8_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 9 (Interrupts 288..319) -*/ -#define NVIC_INIT_ITNS9 0 - -/* -// Interrupts 288..319 -// Interrupt 288 <0=> Secure state <1=> Non-Secure state -// Interrupt 289 <0=> Secure state <1=> Non-Secure state -// Interrupt 290 <0=> Secure state <1=> Non-Secure state -// Interrupt 291 <0=> Secure state <1=> Non-Secure state -// Interrupt 292 <0=> Secure state <1=> Non-Secure state -// Interrupt 293 <0=> Secure state <1=> Non-Secure state -// Interrupt 294 <0=> Secure state <1=> Non-Secure state -// Interrupt 295 <0=> Secure state <1=> Non-Secure state -// Interrupt 296 <0=> Secure state <1=> Non-Secure state -// Interrupt 297 <0=> Secure state <1=> Non-Secure state -// Interrupt 298 <0=> Secure state <1=> Non-Secure state -// Interrupt 299 <0=> Secure state <1=> Non-Secure state -// Interrupt 300 <0=> Secure state <1=> Non-Secure state -// Interrupt 301 <0=> Secure state <1=> Non-Secure state -// Interrupt 302 <0=> Secure state <1=> Non-Secure state -// Interrupt 303 <0=> Secure state <1=> Non-Secure state -// Interrupt 304 <0=> Secure state <1=> Non-Secure state -// Interrupt 305 <0=> Secure state <1=> Non-Secure state -// Interrupt 306 <0=> Secure state <1=> Non-Secure state -// Interrupt 307 <0=> Secure state <1=> Non-Secure state -// Interrupt 308 <0=> Secure state <1=> Non-Secure state -// Interrupt 309 <0=> Secure state <1=> Non-Secure state -// Interrupt 310 <0=> Secure state <1=> Non-Secure state -// Interrupt 311 <0=> Secure state <1=> Non-Secure state -// Interrupt 312 <0=> Secure state <1=> Non-Secure state -// Interrupt 313 <0=> Secure state <1=> Non-Secure state -// Interrupt 314 <0=> Secure state <1=> Non-Secure state -// Interrupt 315 <0=> Secure state <1=> Non-Secure state -// Interrupt 316 <0=> Secure state <1=> Non-Secure state -// Interrupt 317 <0=> Secure state <1=> Non-Secure state -// Interrupt 318 <0=> Secure state <1=> Non-Secure state -// Interrupt 319 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS9_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 10 (Interrupts 320..351) -*/ -#define NVIC_INIT_ITNS10 0 - -/* -// Interrupts 320..351 -// Interrupt 320 <0=> Secure state <1=> Non-Secure state -// Interrupt 321 <0=> Secure state <1=> Non-Secure state -// Interrupt 322 <0=> Secure state <1=> Non-Secure state -// Interrupt 323 <0=> Secure state <1=> Non-Secure state -// Interrupt 324 <0=> Secure state <1=> Non-Secure state -// Interrupt 325 <0=> Secure state <1=> Non-Secure state -// Interrupt 326 <0=> Secure state <1=> Non-Secure state -// Interrupt 327 <0=> Secure state <1=> Non-Secure state -// Interrupt 328 <0=> Secure state <1=> Non-Secure state -// Interrupt 329 <0=> Secure state <1=> Non-Secure state -// Interrupt 330 <0=> Secure state <1=> Non-Secure state -// Interrupt 331 <0=> Secure state <1=> Non-Secure state -// Interrupt 332 <0=> Secure state <1=> Non-Secure state -// Interrupt 333 <0=> Secure state <1=> Non-Secure state -// Interrupt 334 <0=> Secure state <1=> Non-Secure state -// Interrupt 335 <0=> Secure state <1=> Non-Secure state -// Interrupt 336 <0=> Secure state <1=> Non-Secure state -// Interrupt 337 <0=> Secure state <1=> Non-Secure state -// Interrupt 338 <0=> Secure state <1=> Non-Secure state -// Interrupt 339 <0=> Secure state <1=> Non-Secure state -// Interrupt 340 <0=> Secure state <1=> Non-Secure state -// Interrupt 341 <0=> Secure state <1=> Non-Secure state -// Interrupt 342 <0=> Secure state <1=> Non-Secure state -// Interrupt 343 <0=> Secure state <1=> Non-Secure state -// Interrupt 344 <0=> Secure state <1=> Non-Secure state -// Interrupt 345 <0=> Secure state <1=> Non-Secure state -// Interrupt 346 <0=> Secure state <1=> Non-Secure state -// Interrupt 347 <0=> Secure state <1=> Non-Secure state -// Interrupt 348 <0=> Secure state <1=> Non-Secure state -// Interrupt 349 <0=> Secure state <1=> Non-Secure state -// Interrupt 350 <0=> Secure state <1=> Non-Secure state -// Interrupt 351 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS10_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 11 (Interrupts 352..383) -*/ -#define NVIC_INIT_ITNS11 0 - -/* -// Interrupts 352..383 -// Interrupt 352 <0=> Secure state <1=> Non-Secure state -// Interrupt 353 <0=> Secure state <1=> Non-Secure state -// Interrupt 354 <0=> Secure state <1=> Non-Secure state -// Interrupt 355 <0=> Secure state <1=> Non-Secure state -// Interrupt 356 <0=> Secure state <1=> Non-Secure state -// Interrupt 357 <0=> Secure state <1=> Non-Secure state -// Interrupt 358 <0=> Secure state <1=> Non-Secure state -// Interrupt 359 <0=> Secure state <1=> Non-Secure state -// Interrupt 360 <0=> Secure state <1=> Non-Secure state -// Interrupt 361 <0=> Secure state <1=> Non-Secure state -// Interrupt 362 <0=> Secure state <1=> Non-Secure state -// Interrupt 363 <0=> Secure state <1=> Non-Secure state -// Interrupt 364 <0=> Secure state <1=> Non-Secure state -// Interrupt 365 <0=> Secure state <1=> Non-Secure state -// Interrupt 366 <0=> Secure state <1=> Non-Secure state -// Interrupt 367 <0=> Secure state <1=> Non-Secure state -// Interrupt 368 <0=> Secure state <1=> Non-Secure state -// Interrupt 369 <0=> Secure state <1=> Non-Secure state -// Interrupt 370 <0=> Secure state <1=> Non-Secure state -// Interrupt 371 <0=> Secure state <1=> Non-Secure state -// Interrupt 372 <0=> Secure state <1=> Non-Secure state -// Interrupt 373 <0=> Secure state <1=> Non-Secure state -// Interrupt 374 <0=> Secure state <1=> Non-Secure state -// Interrupt 375 <0=> Secure state <1=> Non-Secure state -// Interrupt 376 <0=> Secure state <1=> Non-Secure state -// Interrupt 377 <0=> Secure state <1=> Non-Secure state -// Interrupt 378 <0=> Secure state <1=> Non-Secure state -// Interrupt 379 <0=> Secure state <1=> Non-Secure state -// Interrupt 380 <0=> Secure state <1=> Non-Secure state -// Interrupt 381 <0=> Secure state <1=> Non-Secure state -// Interrupt 382 <0=> Secure state <1=> Non-Secure state -// Interrupt 383 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS11_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 12 (Interrupts 384..415) -*/ -#define NVIC_INIT_ITNS12 0 - -/* -// Interrupts 384..415 -// Interrupt 384 <0=> Secure state <1=> Non-Secure state -// Interrupt 385 <0=> Secure state <1=> Non-Secure state -// Interrupt 386 <0=> Secure state <1=> Non-Secure state -// Interrupt 387 <0=> Secure state <1=> Non-Secure state -// Interrupt 388 <0=> Secure state <1=> Non-Secure state -// Interrupt 389 <0=> Secure state <1=> Non-Secure state -// Interrupt 390 <0=> Secure state <1=> Non-Secure state -// Interrupt 391 <0=> Secure state <1=> Non-Secure state -// Interrupt 392 <0=> Secure state <1=> Non-Secure state -// Interrupt 393 <0=> Secure state <1=> Non-Secure state -// Interrupt 394 <0=> Secure state <1=> Non-Secure state -// Interrupt 395 <0=> Secure state <1=> Non-Secure state -// Interrupt 396 <0=> Secure state <1=> Non-Secure state -// Interrupt 397 <0=> Secure state <1=> Non-Secure state -// Interrupt 398 <0=> Secure state <1=> Non-Secure state -// Interrupt 399 <0=> Secure state <1=> Non-Secure state -// Interrupt 400 <0=> Secure state <1=> Non-Secure state -// Interrupt 401 <0=> Secure state <1=> Non-Secure state -// Interrupt 402 <0=> Secure state <1=> Non-Secure state -// Interrupt 403 <0=> Secure state <1=> Non-Secure state -// Interrupt 404 <0=> Secure state <1=> Non-Secure state -// Interrupt 405 <0=> Secure state <1=> Non-Secure state -// Interrupt 406 <0=> Secure state <1=> Non-Secure state -// Interrupt 407 <0=> Secure state <1=> Non-Secure state -// Interrupt 408 <0=> Secure state <1=> Non-Secure state -// Interrupt 409 <0=> Secure state <1=> Non-Secure state -// Interrupt 410 <0=> Secure state <1=> Non-Secure state -// Interrupt 411 <0=> Secure state <1=> Non-Secure state -// Interrupt 412 <0=> Secure state <1=> Non-Secure state -// Interrupt 413 <0=> Secure state <1=> Non-Secure state -// Interrupt 414 <0=> Secure state <1=> Non-Secure state -// Interrupt 415 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS12_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 13 (Interrupts 416..447) -*/ -#define NVIC_INIT_ITNS13 0 - -/* -// Interrupts 416..447 -// Interrupt 416 <0=> Secure state <1=> Non-Secure state -// Interrupt 417 <0=> Secure state <1=> Non-Secure state -// Interrupt 418 <0=> Secure state <1=> Non-Secure state -// Interrupt 419 <0=> Secure state <1=> Non-Secure state -// Interrupt 420 <0=> Secure state <1=> Non-Secure state -// Interrupt 421 <0=> Secure state <1=> Non-Secure state -// Interrupt 422 <0=> Secure state <1=> Non-Secure state -// Interrupt 423 <0=> Secure state <1=> Non-Secure state -// Interrupt 424 <0=> Secure state <1=> Non-Secure state -// Interrupt 425 <0=> Secure state <1=> Non-Secure state -// Interrupt 426 <0=> Secure state <1=> Non-Secure state -// Interrupt 427 <0=> Secure state <1=> Non-Secure state -// Interrupt 428 <0=> Secure state <1=> Non-Secure state -// Interrupt 429 <0=> Secure state <1=> Non-Secure state -// Interrupt 430 <0=> Secure state <1=> Non-Secure state -// Interrupt 431 <0=> Secure state <1=> Non-Secure state -// Interrupt 432 <0=> Secure state <1=> Non-Secure state -// Interrupt 433 <0=> Secure state <1=> Non-Secure state -// Interrupt 434 <0=> Secure state <1=> Non-Secure state -// Interrupt 435 <0=> Secure state <1=> Non-Secure state -// Interrupt 436 <0=> Secure state <1=> Non-Secure state -// Interrupt 437 <0=> Secure state <1=> Non-Secure state -// Interrupt 438 <0=> Secure state <1=> Non-Secure state -// Interrupt 439 <0=> Secure state <1=> Non-Secure state -// Interrupt 440 <0=> Secure state <1=> Non-Secure state -// Interrupt 441 <0=> Secure state <1=> Non-Secure state -// Interrupt 442 <0=> Secure state <1=> Non-Secure state -// Interrupt 443 <0=> Secure state <1=> Non-Secure state -// Interrupt 444 <0=> Secure state <1=> Non-Secure state -// Interrupt 445 <0=> Secure state <1=> Non-Secure state -// Interrupt 446 <0=> Secure state <1=> Non-Secure state -// Interrupt 447 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS13_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 14 (Interrupts 448..479) -*/ -#define NVIC_INIT_ITNS14 0 - -/* -// Interrupts 448..479 -// Interrupt 448 <0=> Secure state <1=> Non-Secure state -// Interrupt 449 <0=> Secure state <1=> Non-Secure state -// Interrupt 450 <0=> Secure state <1=> Non-Secure state -// Interrupt 451 <0=> Secure state <1=> Non-Secure state -// Interrupt 452 <0=> Secure state <1=> Non-Secure state -// Interrupt 453 <0=> Secure state <1=> Non-Secure state -// Interrupt 454 <0=> Secure state <1=> Non-Secure state -// Interrupt 455 <0=> Secure state <1=> Non-Secure state -// Interrupt 456 <0=> Secure state <1=> Non-Secure state -// Interrupt 457 <0=> Secure state <1=> Non-Secure state -// Interrupt 458 <0=> Secure state <1=> Non-Secure state -// Interrupt 459 <0=> Secure state <1=> Non-Secure state -// Interrupt 460 <0=> Secure state <1=> Non-Secure state -// Interrupt 461 <0=> Secure state <1=> Non-Secure state -// Interrupt 462 <0=> Secure state <1=> Non-Secure state -// Interrupt 463 <0=> Secure state <1=> Non-Secure state -// Interrupt 464 <0=> Secure state <1=> Non-Secure state -// Interrupt 465 <0=> Secure state <1=> Non-Secure state -// Interrupt 466 <0=> Secure state <1=> Non-Secure state -// Interrupt 467 <0=> Secure state <1=> Non-Secure state -// Interrupt 468 <0=> Secure state <1=> Non-Secure state -// Interrupt 469 <0=> Secure state <1=> Non-Secure state -// Interrupt 470 <0=> Secure state <1=> Non-Secure state -// Interrupt 471 <0=> Secure state <1=> Non-Secure state -// Interrupt 472 <0=> Secure state <1=> Non-Secure state -// Interrupt 473 <0=> Secure state <1=> Non-Secure state -// Interrupt 474 <0=> Secure state <1=> Non-Secure state -// Interrupt 475 <0=> Secure state <1=> Non-Secure state -// Interrupt 476 <0=> Secure state <1=> Non-Secure state -// Interrupt 477 <0=> Secure state <1=> Non-Secure state -// Interrupt 478 <0=> Secure state <1=> Non-Secure state -// Interrupt 479 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS14_VAL 0x00000000 - -/* -// -*/ - -/* -// Initialize ITNS 15 (Interrupts 480..511) -*/ -#define NVIC_INIT_ITNS15 0 - -/* -// Interrupts 480..511 -// Interrupt 480 <0=> Secure state <1=> Non-Secure state -// Interrupt 481 <0=> Secure state <1=> Non-Secure state -// Interrupt 482 <0=> Secure state <1=> Non-Secure state -// Interrupt 483 <0=> Secure state <1=> Non-Secure state -// Interrupt 484 <0=> Secure state <1=> Non-Secure state -// Interrupt 485 <0=> Secure state <1=> Non-Secure state -// Interrupt 486 <0=> Secure state <1=> Non-Secure state -// Interrupt 487 <0=> Secure state <1=> Non-Secure state -// Interrupt 488 <0=> Secure state <1=> Non-Secure state -// Interrupt 489 <0=> Secure state <1=> Non-Secure state -// Interrupt 490 <0=> Secure state <1=> Non-Secure state -// Interrupt 491 <0=> Secure state <1=> Non-Secure state -// Interrupt 492 <0=> Secure state <1=> Non-Secure state -// Interrupt 493 <0=> Secure state <1=> Non-Secure state -// Interrupt 494 <0=> Secure state <1=> Non-Secure state -// Interrupt 495 <0=> Secure state <1=> Non-Secure state -// Interrupt 496 <0=> Secure state <1=> Non-Secure state -// Interrupt 497 <0=> Secure state <1=> Non-Secure state -// Interrupt 498 <0=> Secure state <1=> Non-Secure state -// Interrupt 499 <0=> Secure state <1=> Non-Secure state -// Interrupt 500 <0=> Secure state <1=> Non-Secure state -// Interrupt 501 <0=> Secure state <1=> Non-Secure state -// Interrupt 502 <0=> Secure state <1=> Non-Secure state -// Interrupt 503 <0=> Secure state <1=> Non-Secure state -// Interrupt 504 <0=> Secure state <1=> Non-Secure state -// Interrupt 505 <0=> Secure state <1=> Non-Secure state -// Interrupt 506 <0=> Secure state <1=> Non-Secure state -// Interrupt 507 <0=> Secure state <1=> Non-Secure state -// Interrupt 508 <0=> Secure state <1=> Non-Secure state -// Interrupt 509 <0=> Secure state <1=> Non-Secure state -// Interrupt 510 <0=> Secure state <1=> Non-Secure state -// Interrupt 511 <0=> Secure state <1=> Non-Secure state -*/ -#define NVIC_INIT_ITNS15_VAL 0x00000000 - -/* -// -*/ - -/* -// -*/ - - - -/* - max 128 SAU regions. - SAU regions are defined in partition.h - */ - -#define SAU_INIT_REGION(n) \ - SAU->RNR = (n & SAU_RNR_REGION_Msk); \ - SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \ - SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \ - ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U - -/** - \brief Setup a SAU Region - \details Writes the region information contained in SAU_Region to the - registers SAU_RNR, SAU_RBAR, and SAU_RLAR - */ -__STATIC_INLINE void TZ_SAU_Setup (void) -{ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - - #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U) - SAU_INIT_REGION(0); - #endif - - #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U) - SAU_INIT_REGION(1); - #endif - - #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U) - SAU_INIT_REGION(2); - #endif - - #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U) - SAU_INIT_REGION(3); - #endif - - #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U) - SAU_INIT_REGION(4); - #endif - - #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U) - SAU_INIT_REGION(5); - #endif - - #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U) - SAU_INIT_REGION(6); - #endif - - #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U) - SAU_INIT_REGION(7); - #endif - - /* repeat this for all possible SAU regions */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - - - #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U) - SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) | - ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ; - #endif - - #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) - SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk )) | - ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk); - - SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_SYSRESETREQS_Msk | - SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk )) | - ((0x05FAU << SCB_AIRCR_VECTKEY_Pos) & SCB_AIRCR_VECTKEY_Msk) | - ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) | - ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk) | - ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk); - #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */ - - #if (((defined (__FPU_USED) && (__FPU_USED == 1U)) || \ - (defined (__ARM_FEATURE_MVE) && (__ARM_FEATURE_MVE > 0))) && \ - (defined (TZ_FPU_NS_USAGE) && (TZ_FPU_NS_USAGE == 1U))) - - SCB->NSACR = (SCB->NSACR & ~(SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)) | - ((SCB_NSACR_CP10_11_VAL << SCB_NSACR_CP10_Pos) & (SCB_NSACR_CP10_Msk | SCB_NSACR_CP11_Msk)); - - FPU->FPCCR = (FPU->FPCCR & ~(FPU_FPCCR_TS_Msk | FPU_FPCCR_CLRONRETS_Msk | FPU_FPCCR_CLRONRET_Msk)) | - ((FPU_FPCCR_TS_VAL << FPU_FPCCR_TS_Pos ) & FPU_FPCCR_TS_Msk ) | - ((FPU_FPCCR_CLRONRETS_VAL << FPU_FPCCR_CLRONRETS_Pos) & FPU_FPCCR_CLRONRETS_Msk) | - ((FPU_FPCCR_CLRONRET_VAL << FPU_FPCCR_CLRONRET_Pos ) & FPU_FPCCR_CLRONRET_Msk ); - #endif - - #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U) - NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL; - #endif - - #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U) - NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL; - #endif - - #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U) - NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL; - #endif - - #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U) - NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL; - #endif - - #if defined (NVIC_INIT_ITNS4) && (NVIC_INIT_ITNS4 == 1U) - NVIC->ITNS[4] = NVIC_INIT_ITNS4_VAL; - #endif - - #if defined (NVIC_INIT_ITNS5) && (NVIC_INIT_ITNS5 == 1U) - NVIC->ITNS[5] = NVIC_INIT_ITNS5_VAL; - #endif - - #if defined (NVIC_INIT_ITNS6) && (NVIC_INIT_ITNS6 == 1U) - NVIC->ITNS[6] = NVIC_INIT_ITNS6_VAL; - #endif - - #if defined (NVIC_INIT_ITNS7) && (NVIC_INIT_ITNS7 == 1U) - NVIC->ITNS[7] = NVIC_INIT_ITNS7_VAL; - #endif - - #if defined (NVIC_INIT_ITNS8) && (NVIC_INIT_ITNS8 == 1U) - NVIC->ITNS[8] = NVIC_INIT_ITNS8_VAL; - #endif - - #if defined (NVIC_INIT_ITNS9) && (NVIC_INIT_ITNS9 == 1U) - NVIC->ITNS[9] = NVIC_INIT_ITNS9_VAL; - #endif - - #if defined (NVIC_INIT_ITNS10) && (NVIC_INIT_ITNS10 == 1U) - NVIC->ITNS[10] = NVIC_INIT_ITNS10_VAL; - #endif - - #if defined (NVIC_INIT_ITNS11) && (NVIC_INIT_ITNS11 == 1U) - NVIC->ITNS[11] = NVIC_INIT_ITNS11_VAL; - #endif - - #if defined (NVIC_INIT_ITNS12) && (NVIC_INIT_ITNS12 == 1U) - NVIC->ITNS[12] = NVIC_INIT_ITNS12_VAL; - #endif - - #if defined (NVIC_INIT_ITNS13) && (NVIC_INIT_ITNS13 == 1U) - NVIC->ITNS[13] = NVIC_INIT_ITNS13_VAL; - #endif - - #if defined (NVIC_INIT_ITNS14) && (NVIC_INIT_ITNS14 == 1U) - NVIC->ITNS[14] = NVIC_INIT_ITNS14_VAL; - #endif - - #if defined (NVIC_INIT_ITNS15) && (NVIC_INIT_ITNS15 == 1U) - NVIC->ITNS[15] = NVIC_INIT_ITNS15_VAL; - #endif - - /* repeat this for all possible ITNS elements */ - -} - -#endif // IS_SECURE_EVIRONMENT - -#endif // LIBRARIES_CMSIS_DEVICE_MAXIM_MAX32657_INCLUDE_PARTITION_MAX32657_H_ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sir_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sir_regs.h index 400ce986..8be7861a 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sir_regs.h +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/sir_regs.h @@ -72,9 +72,13 @@ extern "C" { * Structure type to access the SIR Registers. */ typedef struct { - __I uint32_t sistat; /**< \b 0x00: SIR SISTAT Register */ - __I uint32_t addr; /**< \b 0x04: SIR ADDR Register */ - __R uint32_t rsv_0x8_0x103[63]; + __I uint32_t sistat; /**< \b 0x000: SIR SISTAT Register */ + __I uint32_t addr; /**< \b 0x004: SIR ADDR Register */ + __R uint32_t rsv_0x8_0x1b[5]; + __IO uint32_t btleldo_bb; /**< \b 0x01C: SIR BTLELDO_BB Register */ + __R uint32_t rsv_0x20_0x2b[3]; + __IO uint32_t btleldo_rf; /**< \b 0x002C: SIR BTLELDO_RF Register */ + __R uint32_t rsv_0x30_0x103[53]; __I uint32_t sfstat; /**< \b 0x104: SIR SFSTAT Register */ } mxc_sir_regs_t; @@ -87,6 +91,8 @@ typedef struct { */ #define MXC_R_SIR_SISTAT ((uint32_t)0x00000000UL) /**< Offset from SIR Base Address: 0x0000 */ #define MXC_R_SIR_ADDR ((uint32_t)0x00000004UL) /**< Offset from SIR Base Address: 0x0004 */ +#define MXC_R_SIR_BTLELDO_BB ((uint32_t)0x0000001CUL) /**< Offset from SIR Base Address: 0x001C */ +#define MXC_R_SIR_BTLELDO_RF ((uint32_t)0x0000002CUL) /**< Offset from SIR Base Address: 0x002C */ #define MXC_R_SIR_SFSTAT ((uint32_t)0x00000104UL) /**< Offset from SIR Base Address: 0x0104 */ /**@} end of group sir_registers */ @@ -117,6 +123,28 @@ typedef struct { /**@} end of group SIR_ADDR_Register */ +/** + * @ingroup sir_registers + * @defgroup SIR_BTLELDO_BB SIR_BTLELDO_BB + * @brief BTLE LDO TRIM BB Register. + * @{ + */ +#define MXC_F_SIR_BTLELDO_BB_TRIM_POS 0 /**< BTLELDO_BB_TRIM Position */ +#define MXC_F_SIR_BTLELDO_BB_TRIM ((uint32_t)(0x1FUL << MXC_F_SIR_BTLELDO_BB_TRIM_POS)) /**< BTLELDO_BB_TRIM Mask */ + +/**@} end of group SIR_BTLELDO_BB_Register */ + +/** + * @ingroup sir_registers + * @defgroup SIR_BTLELDO_RF SIR_BTLELDO_RF + * @brief BTLE LDO TRIM RF Register. + * @{ + */ +#define MXC_F_SIR_BTLELDO_RF_TRIM_POS 0 /**< BTLELDO_RF_TRIM Position */ +#define MXC_F_SIR_BTLELDO_RF_TRIM ((uint32_t)(0x1FUL << MXC_F_SIR_BTLELDO_RF_TRIM_POS)) /**< BTLELDO_RF_TRIM Mask */ + +/**@} end of group SIR_BTLELDO_RF_Register */ + /** * @ingroup sir_registers * @defgroup SIR_SFSTAT SIR_SFSTAT diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spc_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spc_regs.h index 0ad6d991..76b0bedb 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spc_regs.h +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spc_regs.h @@ -91,9 +91,10 @@ typedef struct { __IO uint32_t apbsec; /**< \b 0x0120: SPC APBSEC Register */ __R uint32_t rsv_0x124_0x15f[15]; __IO uint32_t apbpriv; /**< \b 0x0160: SPC APBPRIV Register */ - __R uint32_t rsv_0x164_0x17f[7]; + __R uint32_t rsv_0x164_0x16f[3]; + __IO uint32_t ahbmpriv; /**< \b 0x0170: SPC AHBMPRIV Register */ + __R uint32_t rsv_0x174_0x17f[3]; __IO uint32_t gpio0; /**< \b 0x0180: SPC GPIO0 Register */ - __IO uint32_t gpio1; /**< \b 0x0184: SPC GPIO1 Register */ } mxc_spc_regs_t; /* Register offsets for module SPC */ @@ -114,8 +115,8 @@ typedef struct { #define MXC_R_SPC_M33LOCK ((uint32_t)0x00000090UL) /**< Offset from SPC Base Address: 0x0090 */ #define MXC_R_SPC_APBSEC ((uint32_t)0x00000120UL) /**< Offset from SPC Base Address: 0x0120 */ #define MXC_R_SPC_APBPRIV ((uint32_t)0x00000160UL) /**< Offset from SPC Base Address: 0x0160 */ +#define MXC_R_SPC_AHBMPRIV ((uint32_t)0x00000170UL) /**< Offset from SPC Base Address: 0x0170 */ #define MXC_R_SPC_GPIO0 ((uint32_t)0x00000180UL) /**< Offset from SPC Base Address: 0x0180 */ -#define MXC_R_SPC_GPIO1 ((uint32_t)0x00000184UL) /**< Offset from SPC Base Address: 0x0184 */ /**@} end of group spc_registers */ /** @@ -199,7 +200,7 @@ typedef struct { * @{ */ #define MXC_F_SPC_PPC_STATUS_APBPPC_POS 0 /**< PPC_STATUS_APBPPC Position */ -#define MXC_F_SPC_PPC_STATUS_APBPPC ((uint32_t)(0x3UL << MXC_F_SPC_PPC_STATUS_APBPPC_POS)) /**< PPC_STATUS_APBPPC Mask */ +#define MXC_F_SPC_PPC_STATUS_APBPPC ((uint32_t)(0xFUL << MXC_F_SPC_PPC_STATUS_APBPPC_POS)) /**< PPC_STATUS_APBPPC Mask */ /**@} end of group SPC_PPC_STATUS_Register */ @@ -210,7 +211,7 @@ typedef struct { * @{ */ #define MXC_F_SPC_PPC_INTCLR_APBPPC_POS 0 /**< PPC_INTCLR_APBPPC Position */ -#define MXC_F_SPC_PPC_INTCLR_APBPPC ((uint32_t)(0x3UL << MXC_F_SPC_PPC_INTCLR_APBPPC_POS)) /**< PPC_INTCLR_APBPPC Mask */ +#define MXC_F_SPC_PPC_INTCLR_APBPPC ((uint32_t)(0xFUL << MXC_F_SPC_PPC_INTCLR_APBPPC_POS)) /**< PPC_INTCLR_APBPPC Mask */ /**@} end of group SPC_PPC_INTCLR_Register */ @@ -221,7 +222,7 @@ typedef struct { * @{ */ #define MXC_F_SPC_PPC_INTEN_APBPPC_POS 0 /**< PPC_INTEN_APBPPC Position */ -#define MXC_F_SPC_PPC_INTEN_APBPPC ((uint32_t)(0x3UL << MXC_F_SPC_PPC_INTEN_APBPPC_POS)) /**< PPC_INTEN_APBPPC Mask */ +#define MXC_F_SPC_PPC_INTEN_APBPPC ((uint32_t)(0xFUL << MXC_F_SPC_PPC_INTEN_APBPPC_POS)) /**< PPC_INTEN_APBPPC Mask */ /**@} end of group SPC_PPC_INTEN_Register */ @@ -286,25 +287,25 @@ typedef struct { /** * @ingroup spc_registers - * @defgroup SPC_GPIO0 SPC_GPIO0 - * @brief Secure GPIO0 Configuration Register. + * @defgroup SPC_AHBMPRIV SPC_AHBMPRIV + * @brief AHB Privileged/Non-privileged Secure DMA Access. * @{ */ -#define MXC_F_SPC_GPIO0_PINS_POS 0 /**< GPIO0_PINS Position */ -#define MXC_F_SPC_GPIO0_PINS ((uint32_t)(0xFFFUL << MXC_F_SPC_GPIO0_PINS_POS)) /**< GPIO0_PINS Mask */ +#define MXC_F_SPC_AHBMPRIV_DMA_POS 0 /**< AHBMPRIV_DMA Position */ +#define MXC_F_SPC_AHBMPRIV_DMA ((uint32_t)(0x1UL << MXC_F_SPC_AHBMPRIV_DMA_POS)) /**< AHBMPRIV_DMA Mask */ -/**@} end of group SPC_GPIO0_Register */ +/**@} end of group SPC_AHBMPRIV_Register */ /** * @ingroup spc_registers - * @defgroup SPC_GPIO1 SPC_GPIO1 - * @brief Secure GPIO1 Configuration Register. + * @defgroup SPC_GPIO0 SPC_GPIO0 + * @brief Secure GPIO0 Configuration Register. * @{ */ -#define MXC_F_SPC_GPIO1_PINS_POS 0 /**< GPIO1_PINS Position */ -#define MXC_F_SPC_GPIO1_PINS ((uint32_t)(0x3UL << MXC_F_SPC_GPIO1_PINS_POS)) /**< GPIO1_PINS Mask */ +#define MXC_F_SPC_GPIO0_PINS_POS 0 /**< GPIO0_PINS Position */ +#define MXC_F_SPC_GPIO0_PINS ((uint32_t)(0x3FFFUL << MXC_F_SPC_GPIO0_PINS_POS)) /**< GPIO0_PINS Mask */ -/**@} end of group SPC_GPIO1_Register */ +/**@} end of group SPC_GPIO0_Register */ #ifdef __cplusplus } diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spi_regs.h b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spi_regs.h index e9651121..c9443d1d 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spi_regs.h +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Include/spi_regs.h @@ -156,8 +156,8 @@ typedef struct { #define MXC_F_SPI_CTRL0_EN_POS 0 /**< CTRL0_EN Position */ #define MXC_F_SPI_CTRL0_EN ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_EN_POS)) /**< CTRL0_EN Mask */ -#define MXC_F_SPI_CTRL0_CTRLR_MODE_POS 1 /**< CTRL0_CTRLR_MODE Position */ -#define MXC_F_SPI_CTRL0_CTRLR_MODE ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_CTRLR_MODE_POS)) /**< CTRL0_CTRLR_MODE Mask */ +#define MXC_F_SPI_CTRL0_CONT_MODE_POS 1 /**< CTRL0_CONT_MODE Position */ +#define MXC_F_SPI_CTRL0_CONT_MODE ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_CONT_MODE_POS)) /**< CTRL0_CONT_MODE Mask */ #define MXC_F_SPI_CTRL0_TS_IO_POS 4 /**< CTRL0_TS_IO Position */ #define MXC_F_SPI_CTRL0_TS_IO ((uint32_t)(0x1UL << MXC_F_SPI_CTRL0_TS_IO_POS)) /**< CTRL0_TS_IO Mask */ @@ -383,8 +383,8 @@ typedef struct { #define MXC_F_SPI_INTFL_ABORT_POS 9 /**< INTFL_ABORT Position */ #define MXC_F_SPI_INTFL_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_ABORT_POS)) /**< INTFL_ABORT Mask */ -#define MXC_F_SPI_INTFL_CTRLR_DONE_POS 11 /**< INTFL_CTRLR_DONE Position */ -#define MXC_F_SPI_INTFL_CTRLR_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_CTRLR_DONE_POS)) /**< INTFL_CTRLR_DONE Mask */ +#define MXC_F_SPI_INTFL_CONT_DONE_POS 11 /**< INTFL_CONT_DONE Position */ +#define MXC_F_SPI_INTFL_CONT_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_CONT_DONE_POS)) /**< INTFL_CONT_DONE Mask */ #define MXC_F_SPI_INTFL_TX_OV_POS 12 /**< INTFL_TX_OV Position */ #define MXC_F_SPI_INTFL_TX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTFL_TX_OV_POS)) /**< INTFL_TX_OV Mask */ @@ -430,8 +430,8 @@ typedef struct { #define MXC_F_SPI_INTEN_ABORT_POS 9 /**< INTEN_ABORT Position */ #define MXC_F_SPI_INTEN_ABORT ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_ABORT_POS)) /**< INTEN_ABORT Mask */ -#define MXC_F_SPI_INTEN_CTRLR_DONE_POS 11 /**< INTEN_CTRLR_DONE Position */ -#define MXC_F_SPI_INTEN_CTRLR_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_CTRLR_DONE_POS)) /**< INTEN_CTRLR_DONE Mask */ +#define MXC_F_SPI_INTEN_CONT_DONE_POS 11 /**< INTEN_CONT_DONE Position */ +#define MXC_F_SPI_INTEN_CONT_DONE ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_CONT_DONE_POS)) /**< INTEN_CONT_DONE Mask */ #define MXC_F_SPI_INTEN_TX_OV_POS 12 /**< INTEN_TX_OV Position */ #define MXC_F_SPI_INTEN_TX_OV ((uint32_t)(0x1UL << MXC_F_SPI_INTEN_TX_OV_POS)) /**< INTEN_TX_OV Mask */ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Source/sla_header_max32657.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Source/sla_header_max32657.c new file mode 100644 index 00000000..03672459 --- /dev/null +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Source/sla_header_max32657.c @@ -0,0 +1,37 @@ +/***** Includes *****/ +#include +#include + +extern uint32_t _application_end; + +#define SLA_HEADER_MAGIC0 0xBF1421E4 +#define SLA_HEADER_MAGIC1 0x461A8CF5 +#define SLA_HEADER_VERSION 0x00000001 +#define SLA_HEADER_ALGORITHM_ECDSA 0x516A0001 +#define SLA_HEADER_RESERVED 0x00000000 + +typedef struct +{ + uint32_t magic0; + uint32_t magic1; + uint32_t version; + uint32_t verifytype; + uint32_t sigaddress; + uint32_t reserved5; + uint32_t reserved6; + uint32_t reserved7; +} flash_app_header_t; + +__attribute__ ((section(".sla_header"))) __attribute__ ((__used__)) +const flash_app_header_t sla_header = +{ + .magic0 = SLA_HEADER_MAGIC0, + .magic1 = SLA_HEADER_MAGIC1, + .version = SLA_HEADER_VERSION, + .verifytype = SLA_HEADER_ALGORITHM_ECDSA, + .sigaddress = (uint32_t)&_application_end, + .reserved5 = SLA_HEADER_RESERVED, + .reserved6 = SLA_HEADER_RESERVED, + .reserved7 = SLA_HEADER_RESERVED +}; + diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c index ac9719da..ca1ac228 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32657/Source/system_max32657.c @@ -23,9 +23,13 @@ #include "mxc_sys.h" #include "max32657.h" #include "system_max32657.h" -#include "partition_max32657.h" #include "gcr_regs.h" + +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#include "partition_max32657.h" +#endif + extern void (*const __isr_vector[])(void); uint32_t SystemCoreClock = IPO_FREQ; // Part defaults to IPO on startup @@ -146,7 +150,7 @@ __weak void SystemInit(void) #endif /* Security Extension Features */ -#if IS_SECURE_ENVIRONMENT +#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) /* Settings for TrustZone SAU setup are defined in partitions_max32657.h */ TZ_SAU_Setup(); #endif /* TrustZone */ diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c index 024c30fe..bb818302 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32660/Source/system_max32660.c @@ -41,12 +41,12 @@ The libc implementation from GCC 11+ depends on _getpid and _kill in some places There is no concept of processes/PIDs in the baremetal PeriphDrivers, therefore we implement stub functions that return an error code to resolve linker warnings. */ -__weak int _getpid(void) +int _getpid(void) { return E_NOT_SUPPORTED; } -__weak int _kill(void) +int _kill(void) { return E_NOT_SUPPORTED; } diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32662/Source/sla_header_MAX32662.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32662/Source/header_MAX32662.c similarity index 100% rename from MAX/Libraries/CMSIS/Device/Maxim/MAX32662/Source/sla_header_MAX32662.c rename to MAX/Libraries/CMSIS/Device/Maxim/MAX32662/Source/header_MAX32662.c diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32662/Source/system_max32662.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32662/Source/system_max32662.c index 89c35233..1d0fcd03 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32662/Source/system_max32662.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32662/Source/system_max32662.c @@ -32,19 +32,20 @@ extern void (*const __isr_vector[])(void); -uint32_t SystemCoreClock = HIRC_FREQ; +uint32_t SystemCoreClock __attribute__((section(".shared"))); +volatile uint32_t mailbox __attribute__((section(".mailbox"))); /* The libc implementation from GCC 11+ depends on _getpid and _kill in some places. There is no concept of processes/PIDs in the baremetal PeriphDrivers, therefore we implement stub functions that return an error code to resolve linker warnings. */ -__weak int _getpid(void) +int _getpid(void) { return E_NOT_SUPPORTED; } -__weak int _kill(void) +int _kill(void) { return E_NOT_SUPPORTED; } diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Source/sla_header_MAX32665.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Source/header_MAX32665.c similarity index 100% rename from MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Source/sla_header_MAX32665.c rename to MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Source/header_MAX32665.c diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Source/system_max32665.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Source/system_max32665.c index 2729e992..a7e5bb14 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Source/system_max32665.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32665/Source/system_max32665.c @@ -43,12 +43,12 @@ The libc implementation from GCC 11+ depends on _getpid and _kill in some places There is no concept of processes/PIDs in the baremetal PeriphDrivers, therefore we implement stub functions that return an error code to resolve linker warnings. */ -__weak int _getpid(void) +int _getpid(void) { return E_NOT_SUPPORTED; } -__weak int _kill(void) +int _kill(void) { return E_NOT_SUPPORTED; } diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32670/Source/system_max32670.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32670/Source/system_max32670.c index b7951e51..7b8b644d 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32670/Source/system_max32670.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32670/Source/system_max32670.c @@ -37,12 +37,12 @@ The libc implementation from GCC 11+ depends on _getpid and _kill in some places There is no concept of processes/PIDs in the baremetal PeriphDrivers, therefore we implement stub functions that return an error code to resolve linker warnings. */ -__weak int _getpid(void) +int _getpid(void) { return E_NOT_SUPPORTED; } -__weak int _kill(void) +int _kill(void) { return E_NOT_SUPPORTED; } diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32672/Source/sla_header_MAX32672.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32672/Source/header_MAX32672.c similarity index 100% rename from MAX/Libraries/CMSIS/Device/Maxim/MAX32672/Source/sla_header_MAX32672.c rename to MAX/Libraries/CMSIS/Device/Maxim/MAX32672/Source/header_MAX32672.c diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32672/Source/system_max32672.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32672/Source/system_max32672.c index 67a1c371..fbe7fc3b 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32672/Source/system_max32672.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32672/Source/system_max32672.c @@ -35,12 +35,12 @@ The libc implementation from GCC 11+ depends on _getpid and _kill in some places There is no concept of processes/PIDs in the baremetal PeriphDrivers, therefore we implement stub functions that return an error code to resolve linker warnings. */ -__weak int _getpid(void) +int _getpid(void) { return E_NOT_SUPPORTED; } -__weak int _kill(void) +int _kill(void) { return E_NOT_SUPPORTED; } diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32675/Source/system_max32675.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32675/Source/system_max32675.c index ce9f218b..190e2b21 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32675/Source/system_max32675.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32675/Source/system_max32675.c @@ -37,12 +37,12 @@ The libc implementation from GCC 11+ depends on _getpid and _kill in some places There is no concept of processes/PIDs in the baremetal PeriphDrivers, therefore we implement stub functions that return an error code to resolve linker warnings. */ -__weak int _getpid(void) +int _getpid(void) { return E_NOT_SUPPORTED; } -__weak int _kill(void) +int _kill(void) { return E_NOT_SUPPORTED; } diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32680/Source/system_max32680.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32680/Source/system_max32680.c index b3395119..33191b59 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32680/Source/system_max32680.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32680/Source/system_max32680.c @@ -36,12 +36,12 @@ The libc implementation from GCC 11+ depends on _getpid and _kill in some places There is no concept of processes/PIDs in the baremetal PeriphDrivers, therefore we implement stub functions that return an error code to resolve linker warnings. */ -__weak int _getpid(void) +int _getpid(void) { return E_NOT_SUPPORTED; } -__weak int _kill(void) +int _kill(void) { return E_NOT_SUPPORTED; } diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32680/Source/system_riscv_max32680.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32680/Source/system_riscv_max32680.c index b0296209..b5528022 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32680/Source/system_riscv_max32680.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32680/Source/system_riscv_max32680.c @@ -38,12 +38,12 @@ The libc implementation from GCC 11+ depends on _getpid and _kill in some places There is no concept of processes/PIDs in the baremetal PeriphDrivers, therefore we implement stub functions that return an error code to resolve linker warnings. */ -__weak int _getpid(void) +int _getpid(void) { return E_NOT_SUPPORTED; } -__weak int _kill(void) +int _kill(void) { return E_NOT_SUPPORTED; } diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Source/sla_header_MAX32690.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Source/header_MAX32690.c similarity index 100% rename from MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Source/sla_header_MAX32690.c rename to MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Source/header_MAX32690.c diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Source/system_max32690.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Source/system_max32690.c index f51599c5..08c66bc3 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Source/system_max32690.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Source/system_max32690.c @@ -36,12 +36,12 @@ The libc implementation from GCC 11+ depends on _getpid and _kill in some places There is no concept of processes/PIDs in the baremetal PeriphDrivers, therefore we implement stub functions that return an error code to resolve linker warnings. */ -__weak int _getpid(void) +int _getpid(void) { return E_NOT_SUPPORTED; } -__weak int _kill(void) +int _kill(void) { return E_NOT_SUPPORTED; } diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Source/system_riscv_max32690.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Source/system_riscv_max32690.c index cf40e1d0..e4787f58 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Source/system_riscv_max32690.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX32690/Source/system_riscv_max32690.c @@ -33,12 +33,12 @@ The libc implementation from GCC 11+ depends on _getpid and _kill in some places There is no concept of processes/PIDs in the baremetal PeriphDrivers, therefore we implement stub functions that return an error code to resolve linker warnings. */ -__weak int _getpid(void) +int _getpid(void) { return E_NOT_SUPPORTED; } -__weak int _kill(void) +int _kill(void) { return E_NOT_SUPPORTED; } diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX78000/Source/system_max78000.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX78000/Source/system_max78000.c index 4c5c1dc5..2b05de21 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX78000/Source/system_max78000.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX78000/Source/system_max78000.c @@ -36,12 +36,12 @@ The libc implementation from GCC 11+ depends on _getpid and _kill in some places There is no concept of processes/PIDs in the baremetal PeriphDrivers, therefore we implement stub functions that return an error code to resolve linker warnings. */ -__weak int _getpid(void) +int _getpid(void) { return E_NOT_SUPPORTED; } -__weak int _kill(void) +int _kill(void) { return E_NOT_SUPPORTED; } diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX78000/Source/system_riscv_max78000.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX78000/Source/system_riscv_max78000.c index c54653cb..b706dafc 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX78000/Source/system_riscv_max78000.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX78000/Source/system_riscv_max78000.c @@ -33,12 +33,12 @@ The libc implementation from GCC 11+ depends on _getpid and _kill in some places There is no concept of processes/PIDs in the baremetal PeriphDrivers, therefore we implement stub functions that return an error code to resolve linker warnings. */ -__weak int _getpid(void) +int _getpid(void) { return E_NOT_SUPPORTED; } -__weak int _kill(void) +int _kill(void) { return E_NOT_SUPPORTED; } diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX78002/Source/system_max78002.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX78002/Source/system_max78002.c index d6cbd2fc..1f153a3b 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX78002/Source/system_max78002.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX78002/Source/system_max78002.c @@ -35,12 +35,12 @@ The libc implementation from GCC 11+ depends on _getpid and _kill in some places There is no concept of processes/PIDs in the baremetal PeriphDrivers, therefore we implement stub functions that return an error code to resolve linker warnings. */ -__weak int _getpid(void) +int _getpid(void) { return E_NOT_SUPPORTED; } -__weak int _kill(void) +int _kill(void) { return E_NOT_SUPPORTED; } diff --git a/MAX/Libraries/CMSIS/Device/Maxim/MAX78002/Source/system_riscv_max78002.c b/MAX/Libraries/CMSIS/Device/Maxim/MAX78002/Source/system_riscv_max78002.c index 14a8fdc3..ba04dec7 100644 --- a/MAX/Libraries/CMSIS/Device/Maxim/MAX78002/Source/system_riscv_max78002.c +++ b/MAX/Libraries/CMSIS/Device/Maxim/MAX78002/Source/system_riscv_max78002.c @@ -33,12 +33,12 @@ The libc implementation from GCC 11+ depends on _getpid and _kill in some places There is no concept of processes/PIDs in the baremetal PeriphDrivers, therefore we implement stub functions that return an error code to resolve linker warnings. */ -__weak int _getpid(void) +int _getpid(void) { return E_NOT_SUPPORTED; } -__weak int _kill(void) +int _kill(void) { return E_NOT_SUPPORTED; } diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32657/icc.h b/MAX/Libraries/PeriphDrivers/Include/MAX32657/icc.h index 962cf021..252bd958 100644 --- a/MAX/Libraries/PeriphDrivers/Include/MAX32657/icc.h +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32657/icc.h @@ -53,22 +53,22 @@ typedef enum { * @param cid Enumeration type for Cache Id Register. * @retval Returns the contents of Cache Id Register. */ -int MXC_ICC_ID(mxc_icc_regs_t *icc, mxc_icc_info_t cid); +int MXC_ICC_ID(mxc_icc_info_t cid); /** * @brief Enable the instruction cache controller. */ -void MXC_ICC_Enable(mxc_icc_regs_t *icc); +void MXC_ICC_Enable(void); /** * @brief Disable the instruction cache controller. */ -void MXC_ICC_Disable(mxc_icc_regs_t *icc); +void MXC_ICC_Disable(void); /** * @brief Flush the instruction cache controller. */ -void MXC_ICC_Flush(mxc_icc_regs_t *icc); +void MXC_ICC_Flush(void); /**@} end of group icc */ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32657/lp.h b/MAX/Libraries/PeriphDrivers/Include/MAX32657/lp.h index e4c53fce..0e4ea3bb 100644 --- a/MAX/Libraries/PeriphDrivers/Include/MAX32657/lp.h +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32657/lp.h @@ -49,15 +49,6 @@ extern "C" { */ typedef enum { MXC_LP_V0_9 = 0, MXC_LP_V1_0, MXC_LP_V1_1 } mxc_lp_ovr_t; -/** - * @brief Enumeration type for PM Mode - * - */ -typedef enum { - MXC_LP_IPO = MXC_F_GCR_PM_IPO_PD, - MXC_LP_IBRO = MXC_F_GCR_PM_IBRO_PD, -} mxc_lp_cfg_ds_pd_t; - /** * @brief Places the device into SLEEP mode. This function returns once an RTC or external interrupt occur. */ diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h b/MAX/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h index 840d2bf2..507e9ece 100644 --- a/MAX/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32657/mxc_sys.h @@ -62,6 +62,7 @@ typedef enum { /* RESET1 Below this line we add 32 to separate RESET0 and RESET1 */ MXC_SYS_RESET1_CRC = (MXC_F_GCR_RST1_CRC_POS + 32), /**< Reset CRC */ MXC_SYS_RESET1_AES = (MXC_F_GCR_RST1_AES_POS + 32), /**< Reset AES */ + MXC_SYS_RESET1_AUTOCAL = (MXC_F_GCR_RST1_AUTOCAL_POS + 32), /**< Reset AUTOCAL */ } mxc_sys_reset_t; /** @brief System clock disable enumeration. Used in MXC_SYS_ClockDisable and MXC_SYS_ClockEnable functions */ @@ -79,13 +80,9 @@ typedef enum { MXC_SYS_PERIPH_CLOCK_TMR5 = MXC_F_GCR_PCLKDIS0_TMR5_POS, /**< Disable TMR4 clock */ /* PCLKDIS1 Below this line we add 32 to separate PCLKDIS0 and PCLKDIS1 */ MXC_SYS_PERIPH_CLOCK_TRNG = (MXC_F_GCR_PCLKDIS1_TRNG_POS + 32), /**< Disable TRNG clock */ - // MXC_SYS_PERIPH_CLOCK_SMPHR = - // (MXC_F_GCR_PCLKDIS1_SMPHR_POS + 32), /**< Disable SMPHR clock */ MXC_SYS_PERIPH_CLOCK_CRC = (MXC_F_GCR_PCLKDIS1_CRC_POS + 32), /**< Disable CRC clock */ MXC_SYS_PERIPH_CLOCK_AES = (MXC_F_GCR_PCLKDIS1_AES_POS + 32), /**< Disable AES clock */ - // MXC_SYS_PERIPH_CLOCK_SPI = - // (MXC_F_GCR_PCLKDIS1_SPI_POS + 32), /**< Disable SPI clock */ - // TODO(JC): The SPI clock disable is defined in both PCLKDIS0 and PCLKDIS1 + MXC_SYS_PERIPH_CLOCK_DMA1 = (MXC_F_GCR_PCLKDIS1_DMA1_POS + 32), /**< Disable DMA1 clock */ MXC_SYS_PERIPH_CLOCK_WDT = (MXC_F_GCR_PCLKDIS1_WDT_POS), /**< Disable WDT clock */ } mxc_sys_periph_clock_t; diff --git a/MAX/Libraries/PeriphDrivers/Include/MAX32657/nvic_table.h b/MAX/Libraries/PeriphDrivers/Include/MAX32657/nvic_table.h index 0b96279a..6367d3ea 100644 --- a/MAX/Libraries/PeriphDrivers/Include/MAX32657/nvic_table.h +++ b/MAX/Libraries/PeriphDrivers/Include/MAX32657/nvic_table.h @@ -40,27 +40,6 @@ extern "C" { */ void MXC_NVIC_SetVector(IRQn_Type irqn, void (*irq_callback)(void)); -#if defined(__GNUC__) -#if __CM4_CMSIS_VERSION_MAIN == 0x03 -// NVIC_SetVector was custom-implemented in the PeriphDrivers library for -// CMSIS version 3. Newer versions of CMSIS provide an implementation of -// NVIC_SetVector with different functionality, so the Maxim implementation -// has been moved to MXC_NVIC_SetVector (above). - -// The MSDK will move to CMSIS version 5 in the future. - -// For CMSIS version 3, use MXC_NVIC_SetVector instead. -// For CMSIS version 5, you have the choice of using either. However, only -// MXC_NVIC_SetVector will work with legacy code. -inline __attribute__(( - deprecated("Use MXC_NVIC_SetVector instead. See nvic_table.h for more details."))) void -NVIC_SetVector(IRQn_Type irqn, void (*irq_callback)(void)) -{ - MXC_NVIC_SetVector(irqn, irq_callback); -} -#endif -#endif - /** * @brief Copy NVIC vector table to RAM and set NVIC to RAM based table. * @@ -77,27 +56,6 @@ void NVIC_SetRAM(void); */ uint32_t MXC_NVIC_GetVector(IRQn_Type IRQn); -#if defined(__GNUC__) -#if __CM4_CMSIS_VERSION_MAIN == 0x03 -// NVIC_GetVector was custom-implemented in the PeriphDrivers library for -// CMSIS version 3. Newer versions of CMSIS provide an implementation of -// NVIC_GetVector with different functionality, so the Maxim implementation -// has been moved to MXC_NVIC_GetVector (above). - -// The MSDK will move to CMSIS version 5 in the future. - -// For CMSIS version 3, use MXC_NVIC_SetVector instead. -// For CMSIS version 5, you have the choice of using either. However, only -// MXC_NVIC_GetVector will work with legacy code. -inline __attribute__(( - deprecated("Use MXC_NVIC_GetVector instead. See nvic_table.h for more details."))) void -NVIC_GetVector(IRQn_Type irqn) -{ - MXC_NVIC_GetVector(irqn); -} -#endif -#endif - #ifdef __cplusplus } #endif diff --git a/MAX/Libraries/PeriphDrivers/Source/DMA/dma_reva_me30.svd b/MAX/Libraries/PeriphDrivers/Source/DMA/dma_reva_me30.svd index 16ae2b95..fba4389d 100644 --- a/MAX/Libraries/PeriphDrivers/Source/DMA/dma_reva_me30.svd +++ b/MAX/Libraries/PeriphDrivers/Source/DMA/dma_reva_me30.svd @@ -11,20 +11,20 @@ registers - DMA0 - 28 + DMA0_CH0 + 32 - DMA1 - 29 + DMA0_CH1 + 33 - DMA2 - 30 + DMA0_CH2 + 34 - DMA3 - 31 + DMA0_CH4 + 35 diff --git a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me30.c b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me30.c index bddc113d..eaa9e279 100644 --- a/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me30.c +++ b/MAX/Libraries/PeriphDrivers/Source/GPIO/gpio_me30.c @@ -87,12 +87,6 @@ int MXC_GPIO_Config(const mxc_gpio_cfg_t *cfg) return E_NO_ERROR; } - // Configure the vssel - error = MXC_GPIO_SetVSSEL(gpio, cfg->vssel, cfg->mask); - if (error != E_NO_ERROR) { - return error; - } - // Configure alternate function error = MXC_GPIO_RevA_SetAF((mxc_gpio_reva_regs_t *)gpio, cfg->func, cfg->mask); if (error != E_NO_ERROR) { @@ -224,7 +218,7 @@ uint32_t MXC_GPIO_GetFlags(mxc_gpio_regs_t *port) /* ************************************************************************** */ int MXC_GPIO_SetVSSEL(mxc_gpio_regs_t *port, mxc_gpio_vssel_t vssel, uint32_t mask) { - return MXC_GPIO_RevA_SetVSSEL((mxc_gpio_reva_regs_t *)port, vssel, mask); + return E_NOT_SUPPORTED; } /* ************************************************************************** */ diff --git a/MAX/Libraries/PeriphDrivers/Source/I3C/i3c_reva.svd b/MAX/Libraries/PeriphDrivers/Source/I3C/i3c_reva.svd new file mode 100644 index 00000000..0135661c --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/I3C/i3c_reva.svd @@ -0,0 +1,2406 @@ + + + + I3C0 + Improved Inter-Integrated Circuit. + I3C + 0x40018000 + 32 + + 0x00 + 0x1000 + registers + + + I3C0 + I3C0 IRQ + 30 + + + + CONT_CTRL0 + Controller Control 0 (Configuration) Register. + 0x000 + + + EN + I3C Device Enable. + [1:0] + read-write + + + OFF + Off. + 0 + + + ON + On. + 1 + + + CAP + I23 Bug Target with secondary controller capability. + 2 + + + + + TO_DIS + Disable Timeout error. + [3:3] + read-write + + + HKEEP + High-keepr implementation. + [5:4] + read-write + + + OFF + No high-keeper support. + 0 + + + ON_CHIP + On-chip high-keeper support. + 1 + + + EXT_SDA + External high-keeper support for SDA. + 2 + + + EXT_SCL_SDA + External high-keeper support for SCL and SDA. + 3 + + + + + OD_STOP + Use open-drain speed for STOP. + [6:6] + read-write + + + PP_BAUD + SCL Frequency for push-pull drive. + [11:8] + read-write + + + 1_FCLK + SCL High Period is one FCLK Period. + 0 + + + 2_FCLK + SCL High Period is two FLCK Periods. + 1 + + + 3_FCLK + SCL High Period is three FCLK Period. + 2 + + + 4_FCLK + SCL High Period is four FCLK Period. + 3 + + + 5_FCLK + SCL High Period is five FCLK Period. + 4 + + + 6_FCLK + SCL High Period is six FCLK Period. + 5 + + + 7_FCLK + SCL High Period is seven FCLK Period. + 6 + + + 8_FCLK + SCL High Period is eight FCLK Period. + 7 + + + 9_FCLK + SCL High Period is nine FCLK Period. + 8 + + + 10_FCLK + SCL High Period is ten FCLK Period. + 9 + + + 11_FCLK + SCL High Period is eleven FCLK Period. + 10 + + + 12_FCLK + SCL High Period is twelve FCLK Period. + 11 + + + 13_FCLK + SCL High Period is thirteen FCLK Period. + 12 + + + 14_FCLK + SCL High Period is fourteen FCLK Period. + 13 + + + 15_FCLK + SCL High Period is fifthteen FCLK Period. + 14 + + + 16_FCLK + SCL High Period is sixteen FCLK Period. + 15 + + + + + PP_ADD_LBAUD + Number of FCLK periods to add to the base of SCL low period. + [15:12] + read-write + + + 0_FCLK + Adds zero FCLK periods to the SCL low period. + 0 + + + 1_FCLK + Adds one FCLK period to the SCL low period. + 1 + + + 2_FCLK + Adds two FCLK periods to the SCL low period. + 2 + + + 3_FCLK + Adds three FCLK periods to the SCL low period. + 3 + + + 4_FCLK + Adds four FCLK periods to the SCL low period. + 4 + + + 5_FCLK + Adds five FCLK periods to the SCL low period. + 5 + + + 6_FCLK + Adds six FCLK periods to the SCL low period. + 6 + + + 7_FCLK + Adds seven FCLK periods to the SCL low period. + 7 + + + 8_FCLK + Adds eight FCLK periods to the SCL low period. + 8 + + + 9_FCLK + Adds nine FCLK periods to the SCL low period. + 9 + + + 10_FCLK + Adds ten FCLK periods to the SCL low period. + 10 + + + 11_FCLK + Adds eleven FCLK periods to the SCL low period. + 11 + + + 12_FCLK + Adds twelve FCLK periods to the SCL low period. + 12 + + + 13_FCLK + Adds thirteen FCLK periods to the SCL low period. + 13 + + + 14_FCLK + Adds fourteen FCLK periods to the SCL low period. + 14 + + + 15_FCLK + Adds fifthteen FCLK periods to the SCL low period. + 15 + + + + + OD_LBAUD + Number of PP_BAUD periods minus 1 to make one SCL low period for I3C open-dran periods. + [23:16] + read-write + + + OD_HP + Controls SCL high period for I3C oepn-drain operation. + [24:24] + read-write + + + PP_SKEW + Number of FCLK periods to delay the SDA value change from the SCL edge for I3C push-pull operation. + [27:25] + read-write + + + I2C_BAUD + Detyermines SCL high and low pweriods for I2C mode, in units of OD_BAUD period. + [31:28] + read-write + + + + + TARG_CTRL0 + Target Control 0 (Configuration) Register. + 0x004 + + + EN + Target device enable. + [0:0] + read-write + + + MATCHSS + Match STOP and START. + [2:2] + read-write + + + TO_IGN + Ignore Timeout Errors. + [3:3] + read-write + + + OFFLINE + Rejoin I3C bus with existing dynamic address. + [9:9] + read-write + + + + + TARG_STATUS + Target Status Register. + 0x008 + + + BUSY + Not stopped. + [0:0] + read-only + + + LIST_RESP + Message status - listening/responding or not. + [1:1] + read-only + + + CCCH + CCC is being handled. + [2:2] + read-only + + + RX_SDR + SDR Read. + [3:3] + + + TX_SDR + SDR Write. + [4:4] + + + DAA + Dynamic Address Assignment Mode. + [5:5] + read-only + + + HDR + HDR Mode. + [6:6] + read-only + + + START + START Detected. + [8:8] + read-write + + + ADDRMATCH + Address Matched. + [9:9] + read-write + + + STOP + STOP Detected. + [10:10] + read-write + + + RX_RDY + Receive data ready. + [11:11] + read-only + + + TX_NFULL + TX FIFO is not full, ready to accept more data. + [12:12] + read-write + + + DYNADDR_CHG + Dynamic address changed. + [13:13] + read-write + + + CCC + CCC received. + [14:14] + read-write + + + ERRWARN + An error or warning has occurred. + [15:15] + read-only + + + CCCH_DONE + CCC Handled. + [17:17] + read-write + + + EVENT_REQ + Event Requested. + [18:18] + read-write + + + TARG_RST + Target Reset. + [19:19] + read-write + + + EVENT + Event Status. + [21:20] + read-only + + + NONE + No event. + 0 + + + REQ_PEND + Request not yet sent. + 1 + + + REQ_NACK + Request was sent and NACKed and will be tried again. + 2 + + + REQ_ACK + Request was sent and ACKed. + 3 + + + + + IBI_DIS + Indicates whether IBI events are disabled. + [24:24] + read-only + + + CONTREQ_DIS + Indicates whether bus controller request events are disabled. + [25:25] + read-only + + + HJ_DIS + Indicates whether Hot-Joinevents are disabled. + [27:27] + read-only + + + ACTSTATE + Holds the current activity state. + [29:28] + read-only + + + NORMAL + No latency, normal bus operation. + 0 + + + 1MS_LAT + 1 ms latency. + 1 + + + 100MS_LAT + 100 ms latency. + 2 + + + 10S_LAT + 10 s latency. + 3 + + + + + TIMECTRL + Time Control mode. + [31:30] + read-only + + + DIS + No timing control mode is enabled. + 0 + + + SYNC + Synchronous Mode is enabled. + 1 + + + ASYNC + Asynchronous Mode is enabled. + 2 + + + BOTH + Both synchronous and asynchronous modes are enabled. + 3 + + + + + + + TARG_CTRL1 + Target Control 1 Register. + 0x00C + + + EVENT + Sets respecive I3C target event request. + [1:0] + read-write + + + NORMAL + Normal mode. + 0 + + + IBI + Generate an IBI on the I3C bus. + 1 + + + CONTREQ + Request control of the I3C bus. + 2 + + + HJ + Generate a Hot-Join request. + 3 + + + + + EXTIBI + Indicates there are extended IBI data bytes. + [3:3] + read-write + + + DYNADDR_IDX + Index of dynamic address for the current IBI request. + [7:4] + read-write + + + IBIDATA + Contains the mandatory data byte to be sent when generating an IBI. + [15:8] + read-write + + + + + TARG_INTEN + Target Interrupt Enable Register. + 0x010 + read-write + + + START + START detected. + [8:8] + + + ADDRMATCH + Address matched interrupt. + [9:9] + + + STOP + STOP detected. + [10:10] + + + RX_RDY + Receive data ready. + [11:11] + + + TX_NFULL + Ready for transmit data, + [12:12] + + + DYNADDR_CHG + Dynamic Address Changed interrupt enable. + [13:13] + + + CCC + CCC Reveived Interrupt. + [14:14] + + + ERRWARN + Error or warning interrupt. + [15:15] + + + CCCH_DONE + CCC Handled Interrupt. + [17:17] + + + EVENT_REQ + Event Reqeusted Interrupt. + [18:18] + + + TARG_RST + I3C Target Reset Interrupt. + [19:19] + + + + + TARG_INTCLR + Target Interrupt Clear Register. + 0x014 + write-only + + + START + START detected. + [8:8] + + + ADDRMATCH + Address matched interrupt. + [9:9] + + + STOP + STOP detected. + [10:10] + + + RX_RDY + Receive data ready. + [11:11] + + + TX_NFULL + Ready for transmit data, + [12:12] + + + DYNADDR_CHG + Dynamic Address Changed interrupt enable. + [13:13] + + + CCC + CCC Reveived Interrupt. + [14:14] + + + ERRWARN + Error or warning interrupt. + [15:15] + + + CCCH_DONE + CCC Handled Interrupt. + [17:17] + + + EVENT_REQ + Event Reqeusted Interrupt. + [18:18] + + + TARG_RST + I3C Target Reset Interrupt. + [19:19] + + + + + TARG_INTFL + Target Interrupt Flag Register. + 0x018 + read-only + + + START + START detected. + [8:8] + + + ADDRMATCH + Address matched interrupt. + [9:9] + + + STOP + STOP detected. + [10:10] + + + RX_RDY + Receive data ready. + [11:11] + + + TX_NFULL + Ready for transmit data, + [12:12] + + + DYNADDR_CHG + Dynamic Address Changed interrupt enable. + [13:13] + + + CCC + CCC Reveived Interrupt. + [14:14] + + + ERRWARN + Error or warning interrupt. + [15:15] + + + CCCH_DONE + CCC Handled Interrupt. + [17:17] + + + EVENT_REQ + Event Reqeusted Interrupt. + [18:18] + + + TARG_RST + I3C Target Reset Interrupt. + [19:19] + + + + + TARG_ERRWARN + Target Error and Warning Register. + 0x01C + read-write + + + OVR + Internal FIFO overrun flag. + [0:0] + + + UNR + Internal FIFO underrun flag. + [1:1] + + + UNR_NACK + I3C or I2C mode address emitted by the IP was NACKed by the targets. + [2:2] + + + CONT_RX_TERM + Controller terminated read in message mode. + [3:3] + + + INVSTART + Invalid START. + [4:4] + + + SDR_PAR + SDR Parity Error. + [8:8] + + + TO + Timeout Error. + [11:11] + + + RX_UNR + Read data underrun. + [16:16] + + + TX_OVR + Write data overrun. + [17:17] + + + + + TARG_DMACTRL + Target DMA Control Register. + 0x020 + read-write + + + RX_EN + DMA read enable. + [1:0] + + + DIS + Disable DMA. + 0 + + + ONE_FR + Enable DMA for one frame. + 1 + + + EN + Enable DMA until disabled by setting this field to 0b00. + 2 + + + + + TX_EN + DMA write enable. + [3:2] + + + DIS + Disable DMA. + 0 + + + ONE_FR + Enable DMA for one frame. + 1 + + + EN + Enable DMA until disabled by setting this field to 0b00. + 2 + + + + + WIDTH + Selects the data width for DMA transfers. + [5:4] + + + BYTE + Byte size. + 0 + + + HALFWORD + Halfword size. + 2 + + + + + + + TARG_FIFOCTRL + Target FIFO Control Register. + 0x02C + + + TX_FLUSH + Flush TX FIFO. + [0:0] + write-only + + + RX_FLUSH + Flush RX FIFO. + [1:1] + write-only + + + UNLOCK + Unlock FIFO Triggers. + [3:3] + write-only + + + TX_THD_LVL + TX FIFO trigger level. + [5:4] + read-write + + + EMPTY + Trigger when empty. + 0 + + + QUARTER_FULL + Trigger when quarter full or less. + 1 + + + HALF_FULL + Trigger when half full or less. + 2 + + + ALMOST_FULL + Trigger when almost full or less. + 3 + + + + + RX_THD_LVL + RX FIFO trigger level. + [7:6] + read-write + + + NOT_EMPTY + Trigger when empty. + 0 + + + QUARTER_FULL + Trigger when quarter full or less. + 1 + + + HALF_FULL + Trigger when half full or less. + 2 + + + 3_QUARTER_FULL + Trigger when 3 quarters full or less. + 3 + + + + + TX_LVL + Number of messages in TX FIFO. + [21:16] + read-only + + + RX_LVL + Number of messages in RX FIFO. + [29:24] + read-only + + + TX_FULL + TX FIFO Full flag. + [30:30] + read-only + + + RX_EM + RX FIFO Empty Flag. + [31:31] + read-only + + + + + TARG_TXFIFO8 + Target Write Byte Data Register. + 0x030 + write-only + + + DATA + Data byte to send. + [7:0] + + + END + End of data. + [8:8] + + + END2 + End of data. + [16:16] + + + + + TARG_TXFIFO8E + Target Write Byte Data as End Register. + 0x034 + write-only + + + DATA + Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location. + [7:0] + + + + + TARG_TXFIFO16 + Target Write Half-Word Data Register. + 0x038 + write-only + + + DATA + Data halfword to send. + [15:0] + + + END + End of data. + [16:16] + + + + + TARG_TXFIFO16E + Target Write Half-Word Data as End Register. + 0x03C + write-only + + + DATA + Data halfword to send. + [15:0] + + + + + TARG_RXFIFO8 + Target Read Byte Data Register. + 0x040 + read-only + + + DATA + Read data byte from RX FIFO. + [7:0] + + + + + TARG_RXFIFO16 + Target Read Half-Word Data Register. + 0x048 + read-only + + + DATA + Read data hyalfword from RX FIFO. + [15:0] + + + + + TARG_TXFIFO8O + Target Byte-Only Write Byte Data Register. + 0x054 + write-only + + + DATA + Data byte to send. + [7:0] + + + + + TARG_CAP0 + Target Capabilities 0 Register. + 0x05C + read-only + + + MAPCNT + Number of mapped target addresses supported. + [3:0] + + + I2C_10BADDR + I2C 10-bit address support. + [4:4] + + + I2C_SWRST + I2C Software Reset Support. + [5:5] + + + I2C_DEVID + I2C Device ID Support. + [6:6] + + + FIFO32_REG + FIFO 32 registers available. + [7:7] + + + EXTIBI + Extended IBI data support. + [8:8] + + + EXTIBI_REG + Extended IBI data register support. + [9:9] + + + HDRBT_LANES + Multi-lane support for HDR-BT mode. + [13:12] + + + CCC_V1_1 + CCC V1.1 Support. + [16:16] + + + TARG_RST + Target Reset Support. + [17:17] + + + GROUPADDR + Group address support. + [19:18] + + + AASA_CCC + SETAASA CCC Support. + [21:21] + + + T2T_SUBSC + Target-to-target subscriber support. + [22:22] + + + T2T_WR + Target-to-target write support. + [23:23] + + + + + TARG_CAP1 + TARG_Capabilities 1 Register. + 0x060 + read-only + + + PROVID + Provisioned ID implementation. + [1:0] + + + PROVID_REG + Provision ID, Bus Characteristics, Device Characteristics implementation. + [5:2] + + + HDR_MODES + Supported HDR modes. + [8:6] + + + CONT + Controller mode capable. + [9:9] + + + STATADDR + I2C-style static address implementation. + [11:10] + + + CCCH + CCC Handled by IP. + [15:12] + + + IBI_EVENTS + Supported IBI events. + [20:16] + + + TIMECTRL + Timing Control Support. + [21:21] + + + EXTFIFO + External FIFO configuration. + [25:23] + + + TXFIFO_CFG + TX FIFO configuration. + [27:26] + + + RXFIFO_CFG + RX FIFO configuration. + [29:28] + + + INTR + Interrupt support. + [30:30] + + + DMA + DMA support. + [31:31] + + + + + TARG_DYNADDR + Target Dynamic Address Register. + 0x064 + read-write + + + VALID + Address valid check. + [0:0] + + + ADDR + The assigned dynamic address. + [7:1] + + + CAUSE + Indicates how the last primary dynnamic address value change occurred. + [10:8] + + + + + TARG_MAXLIMITS + Maximum Limits Register. + 0x068 + read-write + + + RX + The maximum number of bytes that the I3C controller may read from this I3C target device per message. + [11:0] + + + TX + The maximum number of bytes that the I3C controller may write from this I3C target device per message. + [27:16] + + + + + TARG_IDEXT + ID Extension Register. + 0x070 + read-write + + + DEVCHAR + Device Characteristics Register. + [15:8] + + + BUSCHAR + Bus Characteristics Register. + [23:16] + + + + + TARG_MSGLAST + Target Matching Address Index Register. + 0x07C + read-only + + + IDX + Index or group number of last matched address. + [3:0] + + + STATADDR + Last matched address was a I2C static address. + [4:4] + + + GROUP + Last matched address was a group address. + [5:5] + + + MODE + Indicates the mode of the last access. + [7:6] + + + DYN_STAT_ADDR + I3C SDR or I2C + 0 + + + HDR_DDR + HDR-DDR. + 1 + + + HDR_BT + HDR-BT. + 2 + + + + + PREV_IDX + Index or group number of previous matched address. + [11:8] + + + PREV_GROUP + Last matched address was a previous group address. + [13:13] + + + PREV_MODE + Indicates the mode of the previous access. + [15:14] + + + DYN_STAT_ADDR + I3C SDR or I2C + 0 + + + HDR_DDR + HDR-DDR. + 1 + + + HDR_BT + HDR-BT. + 2 + + + + + SECPREV_IDX + Index or group number of secondary previous matched address. + [19:16] + + + SECPREV_GROUP + Last matched address was a secondary previous group address. + [21:21] + + + SECPREV_MODE + Indicates the mode of the secondary previous access. + [23:22] + + + DYN_STAT_ADDR + I3C SDR or I2C + 0 + + + HDR_DDR + HDR-DDR. + 1 + + + HDR_BT + HDR-BT. + 2 + + + + + + + CONT_CTRL1 + Controller Control 1 Register. + 0x084 + + + REQ + Requests an I3C or I2C bus operation. + [2:0] + read-write + + + NONE + None operation. + 0 + + + EMIT_START + Emit a START with address and read-write bit from stopped state or in the middle of an SDR message. + 1 + + + EMIT_STOP + Emit a STOP. + 2 + + + IBI_ACKNACK + Manually ACK or NACK an IBI. + 3 + + + PROCESS_DAA + Process Dynamic Address Assignment. + 4 + + + EXIT_RST + Emit HDR Exit Pattern or Target Reset pattern. + 6 + + + AUTO_IBI + Automatic IBI response. + 7 + + + + + TYPE + Controls type of operation for REQ field. + [5:4] + read-write + + + IBIRESP + Response to use when an IBI occurs. + [7:6] + read-write + + + RDWR_DIR + Direction of the transfer. + [8:8] + read-write + + + ADDR + Address to send with START. + [15:9] + read-write + + + TERM_RD + Termination count for read. + [23:16] + read-write + + + + + CONT_STATUS + Controller Status Register. + 0x088 + + + STATE + Current working state. + [2:0] + read-only + + + IDLE + Bus Idle. + 0 + + + TARG_REQ + I3C Bus i stopped and a target is holding SDA low. + 1 + + + SDR_TXSDRMSG + SDR Message Mode using SDRMSG registers. + 2 + + + SDR_NORM + Normal SDR message mode. + 3 + + + DDR + DDR Message mode + 4 + + + DAA + Dynamic Address Assignment mode. + 5 + + + IBI_ACKNACK + IP is waiting for the application to provide an ACK or NACK decision. + 6 + + + IBI_RX + IP is receiving an IBI. + 7 + + + + + WAIT + Depending on STATE, WAIT is 1 when it's waiting in an intermediary state. + [4:4] + read-only + + + NACK + Address was NACKed. + [5:5] + read-only + + + IBITYPE + The type of event for which arbitration was last won. + [7:6] + + + NONE + None. + 0 + + + IBI + In-band Interrupt. + 1 + + + CONT_REQ + Controller request. + 1 + + + HOTJOIN_REQ + Hot-Join request. + 1 + + + + + TARG_START + Target START detected. + [8:8] + + + REQ_DONE + CTRL1 Request completed. + [9:9] + read-only + + + DONE + Message completed. + [10:10] + read-write + + + RX_RDY + Receive data ready. + [11:11] + read-only + + + TX_NFULL + TX FIFO Not Full flag. + [12:12] + read-only + + + IBI_WON + IBI Arbitration won. + [13:13] + read-write + + + ERRWARN + Error or warning status. + [15:15] + read-only + + + CONT_TRANS + IP transitioned from I3C target to controller. + [19:19] + read-write + + + IBI_ADDR + The address of a received IBI or dcontroller request. + [30:24] + read-only + + + + + CONT_IBIRULES + Controller IBI Registry and Rules Register. + 0x08C + + + ADDR0 + Target 0 dynamic address. + [5:0] + read-write + + + ADDR1 + Target 1 dynamic address. + [11:6] + read-write + + + ADDR2 + Target 2 dynamic address. + [17:12] + read-write + + + ADDR3 + Target 3 dynamic address. + [23:18] + read-write + + + ADDR4 + Target 4 dynamic address. + [29:24] + read-write + + + MSB0 + Implementation of MSb for I3C dynamic addresses. + [30:30] + read-write + + + NOBYTE + Specifies the function of ADDR0 to ADDR4 + [31:31] + read-write + + + + + CONT_INTEN + Controller Interrupt Enable Register. + 0x090 + read-write + + + TARG_START + Target Start Detected. + [8:8] + + + REQ_DONE + CTRL request completed. + [9:9] + + + DONE + Message complete. + [10:10] + + + RX_RDY + Receive data ready. + [11:11] + + + TX_NFULL + Ready for transmit data, + [12:12] + + + IBI_WON + IBI arbitration won. + [13:13] + + + ERRWARN + Error or warning interrupt. + [15:15] + + + NOW_CONT + The IP transitioned from I3C bus target to I3C bus controller. + [19:19] + + + + + CONT_INTCLR + Controller Interrupt Clear Register. + 0x094 + write-only + + + TARG_START + Target Start Detected. + [8:8] + + + REQ_DONE + CTRL request completed. + [9:9] + + + DONE + Message complete. + [10:10] + + + RX_RDY + Receive data ready. + [11:11] + + + TX_NFULL + Ready for transmit data, + [12:12] + + + IBI_WON + IBI arbitration won. + [13:13] + + + ERRWARN + Error or warning interrupt. + [15:15] + + + NOW_CONT + The IP transitioned from I3C bus target to I3C bus controller. + [19:19] + + + + + CONT_INTFL + Controller Interrupt Flag Register. + 0x098 + read-only + + + TARG_START + Target Start Detected. + [8:8] + + + REQ_DONE + CTRL request completed. + [9:9] + + + DONE + Message complete. + [10:10] + + + RX_RDY + Receive data ready. + [11:11] + + + TX_NFULL + Ready for transmit data, + [12:12] + + + IBI_WON + IBI arbitration won. + [13:13] + + + ERRWARN + Error or warning interrupt. + [15:15] + + + NOW_CONT + The IP transitioned from I3C bus target to I3C bus controller. + [19:19] + + + + + CONT_ERRWARN + Controller Error and Warning Register. + 0x09C + read-write + + + NACK + I3C or I2C mode address emitted by the IP was NACKed by the targets. + [2:2] + + + TX_ABT + Write aborted due to data NACK. + [3:3] + + + RX_TERM + Controller terminated read in messaage mode. + [4:4] + + + HDR_PAR + HDR Parity Error. + [9:9] + + + HDR_CRC + HDR-DDR CRC Error. + [10:10] + + + RX_UNR + Read data underrun. + [16:16] + + + TX_OVR + Write data overrun. + [17:17] + + + MSG + Message mode error. + [18:18] + + + INV_REQ + Invalid use of request from CTRL register. + [19:19] + + + TO + Timeout error. + [20:20] + + + + + CONT_DMACTRL + Controller DMA Control Register. + 0x0A0 + read-write + + + RX_EN + DMA read enable. + [1:0] + + + DIS + Disable DMA. + 0 + + + ONE_FR + Enable DMA for one frame. + 1 + + + EN + Enable DMA until disabled by setting this field to 0b00. + 2 + + + + + TX_EN + DMA write enable. + [3:2] + + + DIS + Disable DMA. + 0 + + + ONE_FR + Enable DMA for one frame. + 1 + + + EN + Enable DMA until disabled by setting this field to 0b00. + 2 + + + + + WIDTH + Selects the data width for DMA transfers. + [5:4] + + + BYTE + Byte size. + 0 + + + HALFWORD + Halfword size. + 2 + + + + + + + CONT_FIFOCTRL + Controller FIFO Control Register. + 0x0AC + + + TX_FLUSH + Flush TX FIFO. + [0:0] + write-only + + + RX_FLUSH + Flush RX FIFO. + [1:1] + write-only + + + UNLOCK + Unlock FIFO Triggers. + [3:3] + write-only + + + TX_THD_LVL + TX FIFO trigger level. + [5:4] + read-write + + + EMPTY + Trigger when empty. + 0 + + + QUARTER_FULL + Trigger when quarter full or less. + 1 + + + HALF_FULL + Trigger when half full or less. + 2 + + + ALMOST_FULL + Trigger when almost full or less. + 3 + + + + + RX_THD_LVL + RX FIFO trigger level. + [7:6] + read-write + + + NOT_EMPTY + Trigger when empty. + 0 + + + QUARTER_FULL + Trigger when quarter full or less. + 1 + + + HALF_FULL + Trigger when half full or less. + 2 + + + 3_QUARTER_FULL + Trigger when 3 quarters full or less. + 3 + + + + + TX_LVL + Number of messages in TX FIFO. + [21:16] + read-only + + + RX_LVL + Number of messages in RX FIFO. + [29:24] + read-only + + + TX_FULL + TX FIFO Full flag. + [30:30] + read-only + + + RX_EM + RX FIFO Empty Flag. + [31:31] + read-only + + + + + CONT_TXFIFO8 + Controller Write Byte Data Register. + 0x0B0 + write-only + + + DATA + Data byte to send. + [7:0] + + + END + End of data. + [8:8] + + + END2 + End of data. + [16:16] + + + + + CONT_TXFIFO8E + Controller Write Byte Data as End Register. + 0x0B4 + write-only + + + DATA + Data is read from or written to this location. Transmit and receive FIFO are separate but both are addressed at this location. + [7:0] + + + + + CONT_TXFIFO16 + Controller Write Half-Word Data Register. + 0x0B8 + write-only + + + DATA + Data halfword to send. + [15:0] + + + END + End of data. + [16:16] + + + + + CONT_TXFIFO16E + Controller Write Half-Word Data as End Register. + 0x0BC + write-only + + + DATA + Data halfword to send. + [15:0] + + + + + CONT_RXFIFO8 + Controller Read Byte Data Register. + 0x0C0 + read-only + + + DATA + Read data byte from RX FIFO. + [7:0] + + + + + CONT_RXFIFO16 + Controller Read Half-Word Data Register. + 0x0C8 + read-only + + + DATA + Read data hyalfword from RX FIFO. + [15:0] + + + + + CONT_TXFIFO8O + Controller Byte-Only Write Byte Data Register. + 0x0CC + write-only + + + DATA + Data byte to send. + [7:0] + + + + + CONT_TXSDRMSG_CTRL + Controller Start or Continue SDR Message Register. + 0x0D0 + read-write + + + RDWR_DIR + Direction of the transfer. + [0:0] + + + ADDR + Destination address of message. + [7:1] + + + END + Select how to end message. + [8:8] + + + I2C_EN + I2C Mode Enable. + [10:10] + + + LEN + Message length in bytes. + [15:11] + + + + + CONT_TXSDRMSG_FIFO + Controller Start or Continue SDR Message Register. + 0x0D0 + write-only + + + DATA + Data for SDR write message after control information has been written. + [15:0] + + + + + CONT_RXSDRMSG + Controller Read SDR Message Data Register. + 0x0D4 + read-only + + + DATA + Data for SDR write message after control information has been written. + [15:0] + + + + + CONT_TXDDRMSG + Controller Start or Continue DDR Message Register. + 0x0D8 + write-only + + + MSG + Data, address/command, and control information. + [15:0] + + + + + CONT_RXDDR16 + Controller Read DDR Message Data Register. + 0x0DC + read-only + + + DATA + Read data (16bits). + [15:0] + + + + + CONT_DYNADDR + Controller Dynamic Address Register. + 0x0E4 + read-write + + + ADDR + The assigned dynamic address. + [7:1] + + + VALID + Address valid check. + [8:8] + + + + + TARG_GROUPDEF + Target Group Definition Register. + 0x114 + read-only + + + ADDR_EN + Group Address enable. + [0:0] + + + ADDR + Group Address . + [7:1] + + + + + TARG_MAPCTRL0 + Target Primary Map Control Register. + 0x11C + read-write + + + DYNADDR_EN + Dynamic address is enabled. + [0:0] + + + DYNADDR + Dynamic address. + [7:1] + + + CAUSE + Indicates how the last primary dynamic address value change occurred. + [10:8] + + + + + TARG_MAPCTRL1 + Target Map Control 1 Register. + 0x120 + read-write + + + EN + Mapped address slot is enabled. + [0:0] + + + ADDR + Static or Dynamic address. + [7:1] + + + STATADDR_EN + ADDR field contains the I2C static address if enabled. + [8:8] + + + STATADDR_10B + Contains the upper 3 bits of a 10-bit I2C Static Address. + [11:9] + + + NACK + Indicates how the last primary dynamic address value change occurred. + [12:12] + + + + + TARG_MAPCTRL2 + Target Map Control 2 Register. + 0x124 + read-write + + + EN + Mapped address slot is enabled. + [0:0] + + + ADDR + Static or Dynamic address. + [7:1] + + + STATADDR_EN + ADDR field contains the I2C static address if enabled. + [8:8] + + + NACK + Indicates how the last primary dynamic address value change occurred. + [12:12] + + + AUTO_EN + Enable slot for automatic dynamic address assignment. + [13:13] + + + PID + Indicates how the last primary dynamic address value change occurred. + [31:14] + + + + + + + \ No newline at end of file diff --git a/MAX/Libraries/PeriphDrivers/Source/ICC/icc_me30.c b/MAX/Libraries/PeriphDrivers/Source/ICC/icc_me30.c index 1a9cc8cd..cace41e7 100644 --- a/MAX/Libraries/PeriphDrivers/Source/ICC/icc_me30.c +++ b/MAX/Libraries/PeriphDrivers/Source/ICC/icc_me30.c @@ -35,23 +35,22 @@ Maxim Internal Use * ****************************************************************************** */ -int MXC_ICC_ID(mxc_icc_regs_t *icc, mxc_icc_info_t cid) +int MXC_ICC_ID(mxc_icc_info_t cid) { - return MXC_ICC_RevA_ID((mxc_icc_reva_regs_t *)icc, cid); + return MXC_ICC_RevA_ID((mxc_icc_reva_regs_t *)MXC_ICC, cid); } -void MXC_ICC_Enable(mxc_icc_regs_t *icc) +void MXC_ICC_Enable(void) { - MXC_ICC_RevA_Enable((mxc_icc_reva_regs_t *)icc); + MXC_ICC_RevA_Enable((mxc_icc_reva_regs_t *)MXC_ICC); } -void MXC_ICC_Disable(mxc_icc_regs_t *icc) +void MXC_ICC_Disable(void) { - MXC_ICC_RevA_Disable((mxc_icc_reva_regs_t *)icc); + MXC_ICC_RevA_Disable((mxc_icc_reva_regs_t *)MXC_ICC); } -void MXC_ICC_Flush(mxc_icc_regs_t *icc) +void MXC_ICC_Flush(void) { - MXC_ICC_Disable(icc); - MXC_ICC_Enable(icc); + MXC_ICC_Com_Flush(); } diff --git a/MAX/Libraries/PeriphDrivers/Source/ICC/icc_reva_me30.svd b/MAX/Libraries/PeriphDrivers/Source/ICC/icc_reva_me30.svd index eba1471e..b2e331cf 100644 --- a/MAX/Libraries/PeriphDrivers/Source/ICC/icc_reva_me30.svd +++ b/MAX/Libraries/PeriphDrivers/Source/ICC/icc_reva_me30.svd @@ -6,7 +6,7 @@ 0x4002A000 0x00 - 0x800 + 0x1000 registers @@ -15,6 +15,7 @@ Cache ID Register. 0x0000 read-only + 32 RELNUM @@ -42,6 +43,7 @@ 0x0004 read-only 0x00080008 + 32 CCH @@ -61,6 +63,7 @@ CTRL Cache Control and Status Register. 0x0100 + 32 EN @@ -105,27 +108,28 @@ WAY Cache Way Control Register. 0x0200 + 32 WAY Number of cache way, default is always 2. Allowed values are 1,2,4. 0 - 1 + 3 1 1 - 0 + 1 2 2 - 1 + 2 4 4 - 2 + 4 @@ -135,6 +139,7 @@ REGCTRL Regional Control Register. 0x0204 + 32 EN @@ -151,18 +156,20 @@ - 15 - 0x20 + 4 + 8 REGION[%s] Regional Low and High Bound Registers. icc_reg 0x0208 + 64 read-write LBOUND Regional Low Bound Register. 0x0000 reg + 32 BOUND @@ -177,6 +184,7 @@ DMA Channel Status Register. 0x004 reg + 32 BOUND @@ -191,6 +199,7 @@ PFMCTRL Performance Control Register. 0x0300 + 32 EN @@ -204,6 +213,7 @@ PFMCNT Performance Counter Register. 0x0304 + 32 CNT @@ -218,6 +228,7 @@ Invalidate All Registers. 0x0700 read-write + 32 INVALID diff --git a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_reva_me30.svd b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_reva_me30.svd index fb1b9851..2f6efe41 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SPI/spi_reva_me30.svd +++ b/MAX/Libraries/PeriphDrivers/Source/SPI/spi_reva_me30.svd @@ -90,7 +90,7 @@ - CTRLR_MODE + CONT_MODE Controller Mode Enable. 1 1 @@ -757,7 +757,7 @@ - CTRLR_DONE + CONT_DONE Controller Done, set when SPI Controller has completed any transactions. 11 1 @@ -974,7 +974,7 @@ - CTRLR_DONE + CONT_DONE Controller Done interrupt enable. 11 1 diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/TZ/mpc_me30.svd b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/TZ/mpc_me30.svd new file mode 100644 index 00000000..1f36d7f8 --- /dev/null +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/TZ/mpc_me30.svd @@ -0,0 +1,249 @@ + + + + MPC + Memory Protection Controller. + 0x50091000 + + 0x00 + 0x1000 + registers + + + + CTRL + Control Register. + 0x0000 + 32 + + + SEC_ERR + Security Error Response COnfiguration. + 4 + 1 + + + DATAIF_REQ + Data interface gating request. + 6 + 1 + + + DATAIF_ACK + Data interface gating acknowledged. + 7 + 1 + + + AUTO_INC + Auto-increment. + 8 + 1 + + + SEC_LOCKDOWN + Security Lockdown. + 31 + 1 + + + + + BLK_MAX + Maximum value of block-based index register. + 0x0010 + 32 + read-only + + + VAL + Maximum value of block-based index register. + 0 + 32 + + + + + BLK_CFG + Block Control Register. + 0x0014 + 32 + read-only + + + SIZE + Block Size. + 0 + 4 + + + INIT_ST + Initialization in progress. + 31 + 1 + + + + + BLK_IDX + Block Index Register. + 0x0018 + + + IDX + Index value for accessing block-based lookup table. + 0 + 32 + + + + + BLK_LUT + Block-based gating Look Up Table Register. + 0x001C + + + ACCESS + Each bit indicates one block, based on the index pointed by the BLKIDX register. + 0 + 32 + + + + + INT_STAT + Interrupt Flag Register. + 0x0020 + read-only + + + MPC_IRQ + MPC IRQ triggered. + 0 + 1 + + + + + INT_CLEAR + Interrupt Clear Register. + 0x0024 + write-only + + + MPC_IRQ + MPC IRQ Clear. + 0 + 1 + + + + + INT_EN + Interrupt Enable Register. + 0x0028 + + + MPC_IRQ + MPC IRQ Enable. + 0 + 1 + + + + + INT_INFO1 + Interrupt Info 1 Register. + 0x002C + read-only + + + HADDR + AHB bus signals: Address bus. + 0 + 32 + + + + + INT_INFO2 + Interrupt Info 2 Register. + 0x0030 + read-only + + + HMASTER + AHB bus signals: Master Select. + 0 + 16 + + + HNONSEC + AHB bus signals: Indicates the current transfer is either a Non-Secure or Secure transfer. + 16 + 1 + + + CFG_NS + Security state. + 17 + 1 + + + + + INT_SET + Interrupt Set Debug Register. + 0x0034 + write-only + + + MPC_IRQ + MPC IRQ Set. + 0 + 1 + + + + + PIDR4 + Peripheral ID 4 Register. + 0x0FD0 + read-only + + + PIDR0 + Peripheral ID 0 Register. + 0x0FE0 + read-only + + + PIDR1 + Peripheral ID 1 Register. + 0x0FE4 + read-only + + + PIDR2 + Peripheral ID 2 Register. + 0x0FE8 + read-only + + + PIDR3 + Peripheral ID 3 Register. + 0x0FEC + read-only + + + 4 + 4 + CIDR[%s] + Component ID register. + 0x0FF0 + read-only + + + + + \ No newline at end of file diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/TZ/nspc_reva.svd b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/TZ/nspc_me30.svd similarity index 69% rename from MAX/Libraries/PeriphDrivers/Source/SYS/SVD/TZ/nspc_reva.svd rename to MAX/Libraries/PeriphDrivers/Source/SYS/SVD/TZ/nspc_me30.svd index 844c25a7..17e7f4a0 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/TZ/nspc_reva.svd +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/TZ/nspc_me30.svd @@ -23,6 +23,19 @@ + + AHBMPRIV + AHB Privileged/Non-Privileged Non-Secure DMA Access Register. + 0x0170 + + + DMA + Control access for transactions coming from the Non-Secure DMA. + 1 + 1 + + + diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/TZ/spc_reva.svd b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/TZ/spc_me30.svd similarity index 94% rename from MAX/Libraries/PeriphDrivers/Source/SYS/SVD/TZ/spc_reva.svd rename to MAX/Libraries/PeriphDrivers/Source/SYS/SVD/TZ/spc_me30.svd index a290bd93..9c511b5c 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/TZ/spc_reva.svd +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/TZ/spc_me30.svd @@ -136,7 +136,7 @@ APBPPC Interrupt Status of APB PPC for targets on APB bus. Each bit ties to an individual PPC in the system. 0 - 2 + 4 @@ -150,7 +150,7 @@ APBPPC Interrupt Clear of APB PPC for targets on the APB bus. Each bit ties to an individual PPC in the system. 0 - 2 + 4 @@ -163,7 +163,7 @@ APBPPC Interrupt Enable for APB PPC for targets on the APB bus. Each bit ties to an individual PPC in the system. 0 - 2 + 4 @@ -262,32 +262,32 @@ - GPIO0 - Secure GPIO0 Configuration Register. - 0x0180 + AHBMPRIV + AHB Privileged/Non-privileged Secure DMA Access. + 0x0170 - PINS - Each bit configures a GPIO pin as secore or non-secure on GPIO Port 0. Secure GPIO pins prevent software from reading GPIO Data In pin states. + DMA + Controls access of transactions coming from the Secure DMA. 0 - 12 + 1 - GPIO1 - Secure GPIO1 Configuration Register. - 0x0184 + GPIO0 + Secure GPIO0 Configuration Register. + 0x0180 PINS Each bit configures a GPIO pin as secore or non-secure on GPIO Port 0. Secure GPIO pins prevent software from reading GPIO Data In pin states. 0 - 2 + 14 - + \ No newline at end of file diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/fcr_me30.svd b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/fcr_me30.svd index 2a8d1e38..a83d5ee9 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/fcr_me30.svd +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/fcr_me30.svd @@ -17,14 +17,14 @@ read-write - BTLELDO_TX - BTLE LDO TX Trim. + BTLELDO_RF + BTLE LDO RF Trim. 0 5 - BTLELDO_RX - BTLE LDO RX Trim. + BTLELDO_BB + BTLE LDO BB Trim. 8 5 diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me30.svd b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me30.svd index 9485ad8c..48dd1abd 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me30.svd +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/gcr_me30.svd @@ -671,6 +671,12 @@ 10 1 + + AUTOCAL + Auto calibration Reset. + 12 + 1 + @@ -708,12 +714,6 @@ 15 1 - - SPI - SPI Clock Disable - 16 - 1 - DMA1 DMA1 Clock Disable @@ -805,6 +805,19 @@ + + ECCCED + ECC Correctable Error Detect Register. + 0x68 + + + FLASH + ECC Correctable Error Detect Flag for Flash. Write 1 to clear. + 0 + 1 + + + ECCINTEN ECC Interrupt Enable Register @@ -813,7 +826,7 @@ FLASH ECC Flash0 Interrupt Enable. - 11 + 0 1 @@ -867,86 +880,86 @@ 0x74 - TX_EN - LDOTX enable. + RF_EN + LDO RF enable. 0 1 - TX_PD_EN - LDOTX Pull Down. + RF_PD_EN + LDO RF Pull Down. 1 1 - TX_VSEL - Voltage Selection for NFC LDO + RF_VSEL + Voltage Selection for RF LDO 2 2 - RX_EN - LDORX enable. + BB_EN + LDOBB enable. 4 1 - RX_PD_EN - LDORX Pull DOwn. + BB_PD_EN + LDO BB Pull DOwn. 5 1 - RX_VSEL - LDORX Voltage Setting. + BB_VSEL + LDO BB Voltage Setting. 6 2 - RX_BP_EN - LDORX Bypass Enable. + BB_BP_EN + LDO BB Bypass Enable. 8 1 - RX_DISCH - LDORX Discharge. + BB_DISCH + LDO BB Discharge. 9 1 - TX_BP_EN - LDOTX Bypass Enable. + RF_BP_EN + LDO RF Bypass Enable. 10 1 - TX_DISCH - LDOTX Discharge. + RF_DISCH + LDO RF Discharge. 11 1 - TX_EN_DLY - LDOTX Enable Delay. + RF_EN_DLY + LDO RF Enable Delay. 12 1 - RX_EN_DLY - LDORX Enable Delay. + BB_EN_DLY + LDO BB Enable Delay. 13 1 - RX_BP_EN_DLY - LDORX Bypass Enable Delay. + BB_BP_EN_DLY + LDO BB Bypass Enable Delay. 14 1 - TX_BP_EN_DLY - LDOTX Bypass Enable Delay. + RF_BP_EN_DLY + LDO RF Bypass Enable Delay. 15 1 @@ -964,14 +977,14 @@ 8 - RX_CNT - RX delay count. + BB_CNT + BB delay count. 8 9 - TX_CNT - TX delay count. + RF_CNT + RF delay count. 20 9 diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me30.svd b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me30.svd index 84216c88..330f128c 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me30.svd +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/SVD/sir_me30.svd @@ -14,7 +14,7 @@ SISTAT System Initialization Status Register. - 0x00 + 0x000 read-only @@ -62,7 +62,7 @@ ADDR Read-only field set by the SIB block if a CRC error occurs during the read of the OTP memory. Contains the failing address in OTP memory (when CRCERR equals 1). - 0x04 + 0x004 read-only @@ -72,6 +72,32 @@ + + BTLELDO_BB + BTLE LDO TRIM BB Register. + 0x01C + + + TRIM + Target 0.9V. VDDA BB Voltage Trim. + 0 + 5 + + + + + BTLELDO_RF + BTLE LDO TRIM RF Register. + 0x002C + + + TRIM + Target 0.9V. VDDA RF Voltage Trim. + 0 + 5 + + + SFSTAT Security function status register. diff --git a/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me30.c b/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me30.c index c66b9bce..9366db55 100644 --- a/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me30.c +++ b/MAX/Libraries/PeriphDrivers/Source/SYS/sys_me30.c @@ -17,7 +17,7 @@ ******************************************************************************/ /** - * @file mxc_sys.c + * @file mxc_sys.c * @brief System layer driver. * @details This driver is used to control the system layer of the device. */ @@ -237,7 +237,7 @@ int MXC_SYS_ClockSourceEnable(mxc_sys_system_clock_t clock) break; case MXC_SYS_CLOCK_ERFO: - MXC_GCR->btleldoctrl |= MXC_F_GCR_BTLELDOCTRL_TX_EN | MXC_F_GCR_BTLELDOCTRL_RX_EN; + MXC_GCR->btleldoctrl |= MXC_F_GCR_BTLELDOCTRL_RF_EN | MXC_F_GCR_BTLELDOCTRL_BB_EN; /* Initialize kickstart circuit Select Kick start circuit clock source- IPO/ISO diff --git a/MAX/Libraries/PeriphDrivers/Source/TMR/tmr_me30.c b/MAX/Libraries/PeriphDrivers/Source/TMR/tmr_me30.c index 868caf34..6b1c80e0 100644 --- a/MAX/Libraries/PeriphDrivers/Source/TMR/tmr_me30.c +++ b/MAX/Libraries/PeriphDrivers/Source/TMR/tmr_me30.c @@ -119,8 +119,6 @@ int MXC_TMR_Init(mxc_tmr_regs_t *tmr, mxc_tmr_cfg_t *cfg, bool init_pins) if (init_pins) { if (cfg->bitMode != MXC_TMR_BIT_MODE_16B) { MXC_GPIO_Config(&gpio_cfg_tmr2); - } else { - MXC_GPIO_Config(&gpio_cfg_tmr2b); } } diff --git a/MAX/Libraries/PeriphDrivers/Source/TMR/tmr_revb.c b/MAX/Libraries/PeriphDrivers/Source/TMR/tmr_revb.c index 18a81332..fd6c46e0 100644 --- a/MAX/Libraries/PeriphDrivers/Source/TMR/tmr_revb.c +++ b/MAX/Libraries/PeriphDrivers/Source/TMR/tmr_revb.c @@ -192,7 +192,7 @@ void MXC_TMR_RevB_ConfigGeneric(mxc_tmr_revb_regs_t *tmr, mxc_tmr_cfg_t *cfg) while (!(tmr->intfl & (MXC_F_TMR_REVB_INTFL_WRDONE_A << timerOffset))) {} tmr->cmp = (cfg->cmp_cnt << timerOffset); -#if TARGET_NUM == 32655 || TARGET_NUM == 78000 || TARGET_NUM == 32690 || TARGET_NUM == 78002 +#if TARGET_NUM == 32655 || TARGET_NUM == 32657 || TARGET_NUM == 78000 || TARGET_NUM == 32690 || TARGET_NUM == 78002 tmr->ctrl1 &= ~(MXC_F_TMR_REVB_CTRL1_OUTEN_A << timerOffset); #else tmr->ctrl1 |= (MXC_F_TMR_REVB_CTRL1_OUTEN_A << timerOffset); diff --git a/MAX/msdk_sha b/MAX/msdk_sha index e60b26ec..bd67acb6 100644 --- a/MAX/msdk_sha +++ b/MAX/msdk_sha @@ -1 +1 @@ -1430a0c9fcddbd691bd7a26f8ea8ade7e3b678ba +d97b56559a58b52cba25e70560457542a5ea6dfd