diff --git a/pcx_examples/streaming/cn0585_fmcz/CN0585_streaming_axi4lite_read_write.m b/pcx_examples/streaming/cn0585_fmcz/cn0585_axi4_lite_rw_demo/CN0585_streaming_axi4lite_read_write.m
similarity index 100%
rename from pcx_examples/streaming/cn0585_fmcz/CN0585_streaming_axi4lite_read_write.m
rename to pcx_examples/streaming/cn0585_fmcz/cn0585_axi4_lite_rw_demo/CN0585_streaming_axi4lite_read_write.m
diff --git a/pcx_examples/streaming/cn0585_fmcz/cn0585_host_axi4_lite_read_write_example.slx b/pcx_examples/streaming/cn0585_fmcz/cn0585_axi4_lite_rw_demo/cn0585_host_axi4_lite_read_write_example.slx
similarity index 100%
rename from pcx_examples/streaming/cn0585_fmcz/cn0585_host_axi4_lite_read_write_example.slx
rename to pcx_examples/streaming/cn0585_fmcz/cn0585_axi4_lite_rw_demo/cn0585_host_axi4_lite_read_write_example.slx
diff --git a/pcx_examples/targeting/cn0585_fmcz/cn0585_axi4_lite_demo/zynq-zed-adv7511-cn0585.dts b/pcx_examples/targeting/cn0585_fmcz/cn0585_axi4_lite_demo/zynq-zed-adv7511-cn0585.dts
new file mode 100644
index 0000000..d2260bb
--- /dev/null
+++ b/pcx_examples/targeting/cn0585_fmcz/cn0585_axi4_lite_demo/zynq-zed-adv7511-cn0585.dts
@@ -0,0 +1,269 @@
+/dts-v1/;
+
+#include "zynq-zed.dtsi"
+#include "zynq-zed-adv7511.dtsi"
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pwm/pwm.h>
+
+/ {
+	clocks {
+		ext_clk: clock@0 {
+			#clock-cells = <0>;
+			compatible = "fixed-clock";
+			clock-frequency = <120000000>;
+		};
+	};
+
+	one-bit-adc-dac@0 {
+		compatible = "adi,one-bit-adc-dac";
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		in-gpios =  <&gpio_mux 4 GPIO_ACTIVE_HIGH>,
+				<&gpio_mux 5 GPIO_ACTIVE_HIGH>;
+		out-gpios = <&gpio_mux 3 GPIO_ACTIVE_HIGH>,
+				<&gpio_mux 2 GPIO_ACTIVE_HIGH>,
+				<&gpio_mux 1 GPIO_ACTIVE_HIGH>,
+				<&gpio_mux 0 GPIO_ACTIVE_HIGH>,
+				<&gpio_mux 6 GPIO_ACTIVE_HIGH>,
+				<&gpio_mux 7 GPIO_ACTIVE_HIGH>,
+				<&gpio_mux 11 GPIO_ACTIVE_HIGH>,
+				<&gpio_mux 12 GPIO_ACTIVE_HIGH>,
+				<&gpio_mux 13 GPIO_ACTIVE_HIGH>,
+				<&gpio_mux 14 GPIO_ACTIVE_HIGH>;
+
+		channel@0 {
+			reg = <0>;
+			label = "GPIO4_VIO";
+		};
+		channel@1 {
+			reg = <1>;
+			label = "GPIO5_VIO";
+		};
+		channel@2 {
+			reg = <2>;
+			label = "GPIO0_VIO";
+		};
+		channel@3 {
+			reg = <3>;
+			label = "GPIO1_VIO";
+		};
+		channel@4 {
+			reg = <4>;
+			label = "GPIO2_VIO";
+		};
+		channel@5 {
+			reg = <5>;
+			label = "GPIO3_VIO";
+		};
+		channel@6 {
+			reg = <6>;
+			label = "GPIO6_VIO";
+		};
+		channel@7 {
+			reg = <7>;
+			label = "GPIO7_VIO";
+		};
+		channel@8 {
+			reg = <8>;
+			label = "PAD_ADC0";
+		};
+		channel@9 {
+			reg = <9>;
+			label = "PAD_ADC1";
+		};
+		channel@10 {
+			reg = <10>;
+			label = "PAD_ADC2";
+		};
+		channel@11 {
+			reg = <11>;
+			label = "PAD_ADC3";
+		};
+	};
+};
+
+&fpga_axi {
+	axi_pwm_gen: pwm@44B10000 {
+		compatible = "adi,axi-pwmgen";
+		reg = <0x44B10000 0x1000>;
+		label = "ltc2387_if";
+		#pwm-cells = <2>;
+		clocks = <&ext_clk>;
+	};
+
+	ref_clk: clk@44B00000 {
+		compatible = "adi,axi-clkgen-2.00.a";
+		reg = <0x44B00000 0x10000>;
+		#clock-cells = <0>;
+		clocks = <&clkc 15>, <&clkc 15>;
+		clock-names = "s_axi_aclk", "clkin1";
+		clock-output-names = "ref_clk";
+	};
+
+	rx_dma: dmac@44A40000 {
+		compatible = "adi,axi-dmac-1.00.a";
+		reg = <0x44A40000 0x1000>;
+		#dma-cells = <1>;
+		interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clkc 15>;
+
+		adi,channels {
+			#size-cells = <0>;
+			#address-cells = <1>;
+
+			dma-channel@0 {
+				reg = <0>;
+				adi,source-bus-width = <64>;
+				adi,source-bus-type = <2>;
+				adi,destination-bus-width = <64>;
+				adi,destination-bus-type = <0>;
+			};
+		};
+	};
+
+	ltc2387@0{
+		compatible = "ltc2387-16-x4";
+		pwms = <&axi_pwm_gen 0 0
+			&axi_pwm_gen 1 0>;
+		pwm-names = "cnv", "clk_en";
+		clocks = <&ref_clk>;
+		dmas = <&rx_dma 0>;
+		dma-names = "rx";
+		adi,use-two-lanes;
+	};
+
+        qspi0: spi@0x44B20000 {
+                #address-cells = <1>;
+                #size-cells = <0>;
+                reg = <0x44B20000 0x1000>;
+                num-cs = <0x2>;
+                compatible = "xlnx,xps-spi-2.00.a";
+                bits-per-word = <16>;
+                fifo-size = <16>;
+                clock-names = "ext_spi_clk", "s_axi_aclk";
+                clocks = <&clkc 15>, <&clkc 15>;
+                interrupt-names = "ip2intc_irpt";
+                interrupt-parent = <&intc>;
+                interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
+
+                gpio_mux: max7301@0 {
+                        compatible = "max7301";
+                        reg = <0>;
+                        spi-max-frequency = <20000000>;
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                };
+        };
+
+	dac0_tx_dma: tx-dmac@0x44D30000 {
+		compatible = "adi,axi-dmac-1.00.a";
+		reg = <0x44D30000 0x10000>;
+		#dma-cells = <1>;
+		interrupt-parent = <&intc>;
+		interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clkc 15>;
+
+		adi,channels {
+			#size-cells = <0>;
+			#address-cells = <1>;
+
+			dma-channel@0 {
+				reg = <0>;
+				adi,source-bus-width = <32>;
+				adi,source-bus-type = <0>;
+				adi,destination-bus-width = <32>;
+				adi,destination-bus-type = <1>;
+			};
+		};
+	};
+
+	dac1_tx_dma: tx-dmac@0x44E30000 {
+		compatible = "adi,axi-dmac-1.00.a";
+		reg = <0x44E30000 0x10000>;
+		#dma-cells = <1>;
+		interrupt-parent = <&intc>;
+		interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clkc 15>;
+
+		adi,channels {
+			#size-cells = <0>;
+			#address-cells = <1>;
+
+			dma-channel@0 {
+				reg = <0>;
+				adi,source-bus-width = <32>;
+				adi,source-bus-type = <0>;
+				adi,destination-bus-width = <32>;
+				adi,destination-bus-type = <1>;
+			};
+		};
+	};
+
+	axi_ad3552r_0: axi-ad3552r-0@44d04000 {
+		compatible = "adi,axi-ad3552r";
+		reg = <0x44d04000 0x1000>;
+
+		reset-gpios = <&gpio0 90 GPIO_ACTIVE_LOW>;
+
+		clocks = <&ref_clk>;
+
+		dmas = <&dac0_tx_dma 0>;
+		dma-names = "tx";
+	};
+
+	axi_ad3552r_1: axi-ad3552r-1@44e04000 {
+		compatible = "adi,axi-ad3552r";
+		reg = <0x44e04000 0x1000>;
+
+		clocks = <&ref_clk>;
+
+		dmas = <&dac1_tx_dma 0>;
+		dma-names = "tx";
+	};
+	
+	mwipcore@43c00000 {
+		compatible = "mathworks,mwipcore-v3.00";
+		reg = <0x43C00000 0xfffff>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		mmwr-channel@0{
+				reg = <0x0>;
+				compatible = "mathworks,mm-write-channel-v1.00";
+		};
+		mmrd-channel@1{
+				reg = <0x1>;
+				compatible = "mathworks,mm-read-channel-v1.00";
+		};
+	
+		
+	};
+
+	i2c@41620000 {
+		compatible = "xlnx,axi-iic-1.01.b", "xlnx,xps-iic-2.00.a";
+		reg = <0x41620000 0x10000>;
+		interrupt-parent = <&intc>;
+		interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&clkc 15>;
+		clock-names = "pclk";
+
+		#size-cells = <0>;
+		#address-cells = <1>;
+
+		eeprom@50 {
+			compatible = "at24,24c02";
+			reg = <0x50>;
+		};
+		eeprom2@54 {
+			compatible = "at24,24c02";
+			reg = <0x54>;
+		};
+		ad7291_1@20 {
+			label = "ADC_I2C_1";
+			compatible = "adi,ad7291";
+			reg = <0x20>;
+		};
+
+	};
+};
diff --git a/pcx_examples/targeting/cn0585_fmcz/cn0585_led_sw_gpio_control_demo/matlab_processors.tcl b/pcx_examples/targeting/cn0585_fmcz/cn0585_led_sw_gpio_control_demo/matlab_processors.tcl
new file mode 100755
index 0000000..1a82443
--- /dev/null
+++ b/pcx_examples/targeting/cn0585_fmcz/cn0585_led_sw_gpio_control_demo/matlab_processors.tcl
@@ -0,0 +1,136 @@
+proc preprocess_bd {project carrier rxtx} {
+
+    puts "Preprocessing $project $carrier $rxtx"
+
+    switch $project {
+        cn0585_fmcz {
+            # Disconnect the ADC PACK pins
+            delete_bd_objs [get_bd_nets axi_ltc2387_0_adc_data]
+	    delete_bd_objs [get_bd_nets axi_ltc2387_1_adc_data]
+	    delete_bd_objs [get_bd_nets axi_ltc2387_2_adc_data]
+	    delete_bd_objs [get_bd_nets axi_ltc2387_3_adc_data]
+
+            set sys_cstring "matlab $rxtx"
+            sysid_gen_sys_init_file $sys_cstring
+
+            # Disconnect adc_valid
+            delete_bd_objs [get_bd_nets axi_ltc2387_0_adc_valid]
+            # Reconnect the adc_valid in the system
+            connect_bd_net [get_bd_pins axi_ltc2387_0/adc_valid] [get_bd_pins axi_ltc2387_dma/fifo_wr_en]
+
+           if {$rxtx == "rx"} {
+	     connect_bd_net [get_bd_pins axi_ltc2387_0/adc_data] [get_bd_pins axi_ad3552r_0/data_in_a]
+             connect_bd_net [get_bd_pins axi_ltc2387_1/adc_data] [get_bd_pins axi_ad3552r_0/data_in_b]
+             connect_bd_net [get_bd_pins axi_ltc2387_2/adc_data] [get_bd_pins axi_ad3552r_1/data_in_a]
+             connect_bd_net [get_bd_pins axi_ltc2387_3/adc_data] [get_bd_pins axi_ad3552r_1/data_in_b]
+           }
+
+           if {$rxtx == "tx"} {
+	     connect_bd_net [get_bd_pins axi_ltc2387_0/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_0]
+             connect_bd_net [get_bd_pins axi_ltc2387_1/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_1]
+             connect_bd_net [get_bd_pins axi_ltc2387_2/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_2]
+             connect_bd_net [get_bd_pins axi_ltc2387_3/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_3]
+             connect_bd_net [get_bd_pins axi_ltc2387_0/adc_valid] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_en]
+           }
+
+	   if {$rxtx == "tx" || $rxtx == "rxtx"} {
+
+            delete_bd_objs [get_bd_nets axi_ltc2387_0_adc_valid]
+            delete_bd_objs [get_bd_nets axi_ltc2387_1_adc_valid]
+            delete_bd_objs [get_bd_nets axi_ltc2387_2_adc_valid]
+            delete_bd_objs [get_bd_nets axi_ltc2387_3_adc_valid]
+
+            # Connect dac valids together
+            connect_bd_net [get_bd_pins axi_ad3552r_0/valid_in_a] [get_bd_pins axi_ad3552r_0/valid_in_b]
+            connect_bd_net [get_bd_pins axi_ad3552r_0/valid_in_a] [get_bd_pins axi_ad3552r_1/valid_in_a]
+            connect_bd_net [get_bd_pins axi_ad3552r_0/valid_in_a] [get_bd_pins axi_ad3552r_1/valid_in_b]
+
+            # Remove the gpio bd connections
+            delete_bd_objs [get_bd_nets gpio_i_1]
+            delete_bd_objs [get_bd_nets sys_ps7_GPIO_O]
+            # Split the input gpios into 3 to separate the switches
+            create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_0
+            set_property -dict [list \
+              CONFIG.DIN_FROM {63} \
+              CONFIG.DIN_TO {19} \
+              CONFIG.DIN_WIDTH {64} \
+              CONFIG.DOUT_WIDTH {45} \
+            ] [get_bd_cells xlslice_0]
+            create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_1
+            set_property -dict [list \
+              CONFIG.DIN_FROM {18} \
+              CONFIG.DIN_TO {11} \
+              CONFIG.DIN_WIDTH {64} \
+              CONFIG.DOUT_WIDTH {8} \
+            ] [get_bd_cells xlslice_1]
+            create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_2
+            set_property -dict [list \
+              CONFIG.DIN_FROM {10} \
+              CONFIG.DIN_TO {0} \
+              CONFIG.DIN_WIDTH {64} \
+              CONFIG.DOUT_WIDTH {11} \
+            ] [get_bd_cells xlslice_2]
+            # Reconnect the input gpios
+            connect_bd_net [get_bd_ports gpio_i] [get_bd_pins xlslice_0/Din]
+            connect_bd_net [get_bd_ports gpio_i] [get_bd_pins xlslice_1/Din]
+            connect_bd_net [get_bd_ports gpio_i] [get_bd_pins xlslice_2/Din]
+            create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0
+            set_property -dict [list CONFIG.IN2_WIDTH.VALUE_SRC USER CONFIG.IN1_WIDTH.VALUE_SRC USER CONFIG.IN0_WIDTH.VALUE_SRC USER] [get_bd_cells xlconcat_0]
+            set_property -dict [list \
+              CONFIG.IN0_WIDTH {45} \
+              CONFIG.IN1_WIDTH {8} \
+              CONFIG.IN2_WIDTH {11} \
+            ] [get_bd_cells xlconcat_0]
+            connect_bd_net [get_bd_pins xlslice_0/Dout] [get_bd_pins xlconcat_0/In0]
+            connect_bd_net [get_bd_pins xlslice_2/Dout] [get_bd_pins xlconcat_0/In2]
+            # Reconnect the input gpios to the ps7
+            connect_bd_net [get_bd_pins sys_ps7/GPIO_I] [get_bd_pins xlconcat_0/dout]
+            # Split the output gpios into 3 to separate the leds
+            create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_3
+            set_property -dict [list \
+              CONFIG.DIN_FROM {63} \
+              CONFIG.DIN_TO {27} \
+              CONFIG.DIN_WIDTH {64} \
+              CONFIG.DOUT_WIDTH {37} \
+            ] [get_bd_cells xlslice_3]
+            create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_4
+            set_property -dict [list \
+              CONFIG.DIN_FROM {26} \
+              CONFIG.DIN_TO {19} \
+              CONFIG.DIN_WIDTH {64} \
+              CONFIG.DOUT_WIDTH {8} \
+            ] [get_bd_cells xlslice_4]
+            create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 xlslice_5
+            set_property -dict [list \
+              CONFIG.DIN_FROM {18} \
+              CONFIG.DIN_TO {0} \
+              CONFIG.DIN_WIDTH {64} \
+              CONFIG.DOUT_WIDTH {19} \
+            ] [get_bd_cells xlslice_5]
+            # Reconnect the output gpios
+            connect_bd_net [get_bd_pins sys_ps7/GPIO_O] [get_bd_pins xlslice_3/Din]
+            connect_bd_net [get_bd_pins sys_ps7/GPIO_O] [get_bd_pins xlslice_4/Din]
+            connect_bd_net [get_bd_pins sys_ps7/GPIO_O] [get_bd_pins xlslice_5/Din]
+            create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_1
+            set_property -dict [list CONFIG.IN2_WIDTH.VALUE_SRC USER CONFIG.IN1_WIDTH.VALUE_SRC USER CONFIG.IN0_WIDTH.VALUE_SRC USER] [get_bd_cells xlconcat_1]
+            set_property -dict [list \
+              CONFIG.IN0_WIDTH {37} \
+              CONFIG.IN1_WIDTH {8} \
+              CONFIG.IN2_WIDTH {19} \
+            ] [get_bd_cells xlconcat_1]
+            connect_bd_net [get_bd_pins xlslice_3/Dout] [get_bd_pins xlconcat_1/In0]
+            connect_bd_net [get_bd_pins xlslice_5/Dout] [get_bd_pins xlconcat_1/In2]
+            # Reconnect the output gpios to the output port
+            connect_bd_net [get_bd_ports gpio_o] [get_bd_pins xlconcat_1/Dout]
+
+           }
+	    switch $carrier {
+              zed {
+                    set_property -dict [list CONFIG.NUM_MI {21}] [get_bd_cells axi_cpu_interconnect]
+                    connect_bd_net [get_bd_pins axi_cpu_interconnect/M20_ACLK]    [get_bd_pins axi_clkgen/clk_0]
+                    connect_bd_net [get_bd_pins axi_cpu_interconnect/M20_ARESETN] [get_bd_pins sampling_clk_rstgen/peripheral_aresetn]
+                  }
+             }
+        }
+    }
+}
diff --git a/pcx_examples/targeting/cn0585_fmcz/cn0585_led_sw_gpio_control_demo/ports.json b/pcx_examples/targeting/cn0585_fmcz/cn0585_led_sw_gpio_control_demo/ports.json
new file mode 100755
index 0000000..ca94808
--- /dev/null
+++ b/pcx_examples/targeting/cn0585_fmcz/cn0585_led_sw_gpio_control_demo/ports.json
@@ -0,0 +1,154 @@
+{
+    "cn0585": {
+        "chip": "CN0585",
+        "complex": "true",
+        "fpga": [
+            "zed"
+        ],
+        "supported_rd": [
+            "rx",
+            "tx",
+            "rx & tx"
+        ],
+        "ports": [
+            {
+                "rx": [
+                    {
+                        "input": "false",
+                        "width": 1,
+                        "name": "util_ltc2387_adc_pack/fifo_wr_en",
+                        "type": "valid"
+                    },
+                    {
+                        "input": "false",
+                        "width": 16,
+                        "name": "util_ltc2387_adc_pack/fifo_wr_data_0",
+                        "type": "data"
+                    },
+                    {
+                        "input": "false",
+                        "width": 16,
+                        "name": "util_ltc2387_adc_pack/fifo_wr_data_1",
+                        "type": "data"
+                    },
+                    {
+                        "input": "false",
+                        "width": 16,
+                        "name": "util_ltc2387_adc_pack/fifo_wr_data_2",
+                        "type": "data"
+                    },
+                    {
+                        "input": "false",
+                        "width": 16,
+                        "name": "util_ltc2387_adc_pack/fifo_wr_data_3",
+                        "type": "data"
+                    },
+                    {
+                        "input": "true",
+                        "width": 1,
+                        "name": "axi_ltc2387_0/adc_valid",
+                        "type": "valid"
+	            },
+                    {
+                        "input": "true",
+                        "width": 16,
+                        "name": "axi_ltc2387_0/adc_data",
+                        "type": "data"
+                    },
+                    {
+                        "input": "true",
+                        "width": 16,
+                        "name": "axi_ltc2387_1/adc_data",
+                        "type": "data"
+                    },
+                    {
+                        "input": "true",
+                        "width": 16,
+                        "name": "axi_ltc2387_2/adc_data",
+                        "type": "data"
+                    },
+                    {
+                        "input": "true",
+                        "width": 16,
+                        "name": "axi_ltc2387_3/adc_data",
+                        "type": "data"
+                    }
+                ],
+                "tx": [
+	            {
+                        "input": "true",
+                        "width": 16,
+                        "name": "axi_ltc2387_0/adc_data",
+                        "type": "data"
+                    },
+                    {
+                        "input": "true",
+                        "width": 16,
+                        "name": "axi_ltc2387_1/adc_data",
+                        "type": "data"
+                    },
+                    {
+                        "input": "true",
+                        "width": 16,
+                        "name": "axi_ltc2387_2/adc_data",
+                        "type": "data"
+                    },
+                    {
+                        "input": "true",
+                        "width": 16,
+                        "name": "axi_ltc2387_3/adc_data",
+                        "type": "data"
+                    },
+                    {
+                        "input": "true",
+                        "width": 1,
+                        "name": "axi_ltc2387_0/adc_valid",
+                        "type": "valid"
+                    },
+		    {
+                        "input": "false",
+                        "width": 16,
+                        "name": "axi_ad3552r_0/data_in_a",
+                        "type": "data"
+                    },
+		    {   
+                        "input": "false",
+                        "width": 16,
+                        "name": "axi_ad3552r_0/data_in_b",
+                        "type": "data"
+                    },
+                    {
+                        "input": "false",
+                        "width": 1,
+                        "name": "axi_ad3552r_0/valid_in_a",
+                        "type": "valid"
+                    },
+                    {
+                        "input": "false",
+                        "width": 16,
+                        "name": "axi_ad3552r_1/data_in_a",
+                        "type": "data"
+                    },
+                    {
+                        "input": "false",
+                        "width": 16,
+                        "name": "axi_ad3552r_1/data_in_b",
+                        "type": "data"
+                    },
+                    {
+                        "input": "true",
+                        "width": 8,
+                        "name": "xlsice_1/Dout",
+                        "type": "data"
+                   },
+                   {
+                       "input": "false",
+                       "width": 8,
+                       "name": "xlconcat_1/In1",
+                       "type": "data"
+                    }
+                ]
+            }
+        ]
+    }
+}
diff --git a/pcx_examples/targeting/cn0585_fmcz/cn0585_led_sw_gpio_control_demo/testModel_Tx16and8.slx b/pcx_examples/targeting/cn0585_fmcz/cn0585_led_sw_gpio_control_demo/testModel_Tx16and8.slx
new file mode 100644
index 0000000..55d8cf3
Binary files /dev/null and b/pcx_examples/targeting/cn0585_fmcz/cn0585_led_sw_gpio_control_demo/testModel_Tx16and8.slx differ