diff --git a/hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585_fmcz/+zed/hdlcoder_ref_design_customization.m b/hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585_fmcz/+zed/hdlcoder_ref_design_customization.m index 8e2c2c9..a7b638c 100755 --- a/hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585_fmcz/+zed/hdlcoder_ref_design_customization.m +++ b/hdl/vendor/AnalogDevices/+AnalogDevices/+cn0585_fmcz/+zed/hdlcoder_ref_design_customization.m @@ -12,9 +12,9 @@ % Copyright 2013-2014 The MathWorks, Inc. rd = {... - 'AnalogDevices.cn0585_fmcz.zed.plugin_rd_rx', ... - 'AnalogDevices.cn0585_fmcz.zed.plugin_rd_tx', ... - 'AnalogDevices.cn0585_fmcz.zed.plugin_rd_rxtx', ... + 'AnalogDevices.cn0585.zed.plugin_rd_rx', ... + 'AnalogDevices.cn0585.zed.plugin_rd_tx', ... + 'AnalogDevices.cn0585.zed.plugin_rd_rxtx', ... }; boardName = 'AnalogDevices CN0585 ZED'; diff --git a/hdl/vendor/AnalogDevices/hdlcoder_board_customization.m b/hdl/vendor/AnalogDevices/hdlcoder_board_customization.m index d553377..a83f72a 100755 --- a/hdl/vendor/AnalogDevices/hdlcoder_board_customization.m +++ b/hdl/vendor/AnalogDevices/hdlcoder_board_customization.m @@ -9,7 +9,7 @@ % Copyright 2012-2013 The MathWorks, Inc. r = { ... - 'AnalogDevices.cn0585_fmcz.zed.plugin_board' ..., + 'AnalogDevices.cn0585.zed.plugin_board' ..., }; end % LocalWords: Zynq ZC diff --git a/hdl/vendor/AnalogDevices/vivado/projects/scripts/matlab_processors.tcl b/hdl/vendor/AnalogDevices/vivado/projects/scripts/matlab_processors.tcl new file mode 100755 index 0000000..093650d --- /dev/null +++ b/hdl/vendor/AnalogDevices/vivado/projects/scripts/matlab_processors.tcl @@ -0,0 +1,58 @@ +proc preprocess_bd {project carrier rxtx} { + + puts "Preprocessing $project $carrier $rxtx" + + switch $project { + cn0585 { + # Disconnect the ADC PACK pins + delete_bd_objs [get_bd_nets axi_ltc2387_0_adc_data] + delete_bd_objs [get_bd_nets axi_ltc2387_1_adc_data] + delete_bd_objs [get_bd_nets axi_ltc2387_2_adc_data] + delete_bd_objs [get_bd_nets axi_ltc2387_3_adc_data] + + + set sys_cstring "matlab $rxtx" + sysid_gen_sys_init_file $sys_cstring + + #Disconnect adc_valid + delete_bd_objs [get_bd_nets axi_ltc2387_0_adc_valid] + # Reconnect the adc_valid in the system + connect_bd_net [get_bd_pins axi_ltc2387_0/adc_valid] [get_bd_pins axi_ltc2387_dma/fifo_wr_en] + + if {$rxtx == "rx"} { + connect_bd_net [get_bd_pins axi_ltc2387_0/adc_data] [get_bd_pins axi_ad3552r_0/data_in_a] + connect_bd_net [get_bd_pins axi_ltc2387_1/adc_data] [get_bd_pins axi_ad3552r_0/data_in_b] + connect_bd_net [get_bd_pins axi_ltc2387_2/adc_data] [get_bd_pins axi_ad3552r_1/data_in_a] + connect_bd_net [get_bd_pins axi_ltc2387_3/adc_data] [get_bd_pins axi_ad3552r_1/data_in_b] + } + + if {$rxtx == "tx"} { + connect_bd_net [get_bd_pins axi_ltc2387_0/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_0] + connect_bd_net [get_bd_pins axi_ltc2387_1/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_1] + connect_bd_net [get_bd_pins axi_ltc2387_2/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_2] + connect_bd_net [get_bd_pins axi_ltc2387_3/adc_data] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_data_3] + connect_bd_net [get_bd_pins axi_ltc2387_0/adc_valid] [get_bd_pins util_ltc2387_adc_pack/fifo_wr_en] + } + + if {$rxtx == "tx" || $rxtx == "rxtx"} { + + delete_bd_objs [get_bd_nets axi_ltc2387_0_adc_valid] + delete_bd_objs [get_bd_nets axi_ltc2387_1_adc_valid] + delete_bd_objs [get_bd_nets axi_ltc2387_2_adc_valid] + delete_bd_objs [get_bd_nets axi_ltc2387_3_adc_valid] + + # Connect dac valids together + connect_bd_net [get_bd_pins axi_ad3552r_0/valid_in_a] [get_bd_pins axi_ad3552r_0/valid_in_b] + connect_bd_net [get_bd_pins axi_ad3552r_0/valid_in_a] [get_bd_pins axi_ad3552r_1/valid_in_a] + connect_bd_net [get_bd_pins axi_ad3552r_0/valid_in_a] [get_bd_pins axi_ad3552r_1/valid_in_b] + } + switch $carrier { + zed { + set_property -dict [list CONFIG.NUM_MI {21}] [get_bd_cells axi_cpu_interconnect] + connect_bd_net [get_bd_pins axi_cpu_interconnect/M20_ACLK] [get_bd_pins axi_clkgen/clk_0] + connect_bd_net [get_bd_pins axi_cpu_interconnect/M20_ARESETN] [get_bd_pins sampling_clk_rstgen/peripheral_aresetn] + } + } + } + } +} diff --git a/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/plugin_rd.m b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/plugin_rd.m index 5bc799a..d277e32 100644 --- a/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/plugin_rd.m +++ b/pcx_examples/targeting/cn0585_fmcz/+AnalogDevicesDemo/+cn0585_led_sw_gpio_control_demo/+common/plugin_rd.m @@ -6,7 +6,7 @@ % pname = upper(project); % ppath = project; % if strcmpi(project, 'cn0585') -% ppath = 'cn0585_fmcz'; +% ppath = 'cn0585'; % end board = 'zed'; @@ -21,7 +21,7 @@ hRD.BoardName = sprintf('AnalogDevices CN0585 GPIO Control'); % Tool information -hRD.SupportedToolVersion = {'2022.2'}; +hRD.SupportedToolVersion = {'2023.2'}; % Get the root directories rootDirExample = fileparts(strtok(mfilename('fullpath'), '+')); @@ -42,7 +42,7 @@ hRD.addParameter( ... 'ParameterID', 'project', ... 'DisplayName', 'HDL Project Subfolder', ... - 'DefaultValue', 'cn0585_fmcz'); + 'DefaultValue', 'cn0585'); hRD.addParameter( ... 'ParameterID', 'carrier', ... @@ -51,7 +51,7 @@ %% Add custom design files hRD.addCustomVivadoDesign( ... - 'CustomBlockDesignTcl', fullfile('pcx_examples', 'targeting', 'cn0585_fmcz', 'cn0585_hdl', 'system_project_rxtx.tcl')); + 'CustomBlockDesignTcl', fullfile('pcx_examples', 'targeting', 'cn0585', 'cn0585_hdl', 'system_project_rxtx.tcl')); %% Standard reference design pieces hRD.BlockDesignName = 'system'; @@ -70,10 +70,10 @@ fullfile(rootDirBSP, 'library','xilinx')..., fullfile(rootDirBSP, 'projects','common')..., fullfile(rootDirBSP, 'projects','scripts')..., - fullfile(rootDirBSP, 'projects','cn0585_fmcz')..., - fullfile(rootDirBSP, 'projects','cn0585_fmcz', 'common')..., - fullfile(rootDirBSP, 'projects','cn0585_fmcz', 'zed')..., - fullfile('pcx_examples', 'targeting', 'cn0585_fmcz', 'cn0585_hdl')..., + fullfile(rootDirBSP, 'projects','cn0585')..., + fullfile(rootDirBSP, 'projects','cn0585', 'common')..., + fullfile(rootDirBSP, 'projects','cn0585', 'zed')..., + fullfile('pcx_examples', 'targeting', 'cn0585', 'cn0585_hdl')..., }; hRD.addParameter( ... @@ -93,7 +93,7 @@ hRD.addParameter( ... 'ParameterID', 'preprocess_script', ... 'DisplayName', 'Preprocess Script', ... - 'DefaultValue', fullfile('pcx_examples', 'targeting', 'cn0585_fmcz','cn0585_hdl','fh_preprocess.tcl')); + 'DefaultValue', fullfile('pcx_examples', 'targeting', 'cn0585','cn0585_hdl','fh_preprocess.tcl')); hRD.addParameter( ... 'ParameterID', 'postprocess', ... diff --git a/pcx_examples/targeting/cn0585_fmcz/cn0585_hdl/matlab_processors.tcl b/pcx_examples/targeting/cn0585_fmcz/cn0585_hdl/matlab_processors.tcl index 5376448..ece7ad2 100755 --- a/pcx_examples/targeting/cn0585_fmcz/cn0585_hdl/matlab_processors.tcl +++ b/pcx_examples/targeting/cn0585_fmcz/cn0585_hdl/matlab_processors.tcl @@ -3,12 +3,12 @@ proc preprocess_bd {project carrier rxtx} { puts "Preprocessing $project $carrier $rxtx" switch $project { - cn0585_fmcz { + cn0585 { # Disconnect the ADC PACK pins delete_bd_objs [get_bd_nets axi_ltc2387_0_adc_data] - delete_bd_objs [get_bd_nets axi_ltc2387_1_adc_data] - delete_bd_objs [get_bd_nets axi_ltc2387_2_adc_data] - delete_bd_objs [get_bd_nets axi_ltc2387_3_adc_data] + delete_bd_objs [get_bd_nets axi_ltc2387_1_adc_data] + delete_bd_objs [get_bd_nets axi_ltc2387_2_adc_data] + delete_bd_objs [get_bd_nets axi_ltc2387_3_adc_data] set sys_cstring "matlab $rxtx" sysid_gen_sys_init_file $sys_cstring diff --git a/test/board_variants.m b/test/board_variants.m index 441c4ab..dc6e70c 100755 --- a/test/board_variants.m +++ b/test/board_variants.m @@ -9,9 +9,9 @@ % Copyright 2023 The MathWorks, Inc. r = { ... - 'AnalogDevices.cn0585_fmcz.zed.plugin_rd_rx', ... - 'AnalogDevices.cn0585_fmcz.zed.plugin_rd_tx', ... - 'AnalogDevices.cn0585_fmcz.zed.plugin_rd_rxtx', ... + 'AnalogDevices.cn0585.zed.plugin_rd_rx', ... + 'AnalogDevices.cn0585.zed.plugin_rd_tx', ... + 'AnalogDevices.cn0585.zed.plugin_rd_rxtx', ... }; end % LocalWords: Zynq ZC