From 9d2fe3474e0765ae2a177619db7fcd9d272fce42 Mon Sep 17 00:00:00 2001 From: Pagadarai Date: Wed, 22 Mar 2023 13:59:17 -0400 Subject: [PATCH 1/4] Update to fix missing doc link in help Signed-off-by: Pagadarai --- Jenkinsfile | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Jenkinsfile b/Jenkinsfile index 32b1ce6a..33a918c7 100644 --- a/Jenkinsfile +++ b/Jenkinsfile @@ -15,6 +15,8 @@ stage("Build Toolbox") { withEnv(['HDLBRANCH='+branchName]) { checkout scm sh 'git submodule update --init' + sh 'pip3 install -r ./CI/gen_doc/requirements_doc.txt' + sh 'make -C ./CI/gen_doc doc_ml' sh 'make -C ./CI/scripts build' sh 'make -C ./CI/scripts gen_tlbx' } From 1079b51cdc5e9a033371ca8b741f838d54305ab1 Mon Sep 17 00:00:00 2001 From: Pagadarai Date: Wed, 22 Mar 2023 14:10:38 -0400 Subject: [PATCH 2/4] Minor fix to CI/gen_doc Makefile Signed-off-by: Pagadarai --- CI/gen_doc/Makefile | 1 - 1 file changed, 1 deletion(-) diff --git a/CI/gen_doc/Makefile b/CI/gen_doc/Makefile index 4a92a3c6..5b729cf4 100644 --- a/CI/gen_doc/Makefile +++ b/CI/gen_doc/Makefile @@ -42,7 +42,6 @@ GITTAG := $(shell git describe --tags HEAD) .ONESHELL: doc_ml: - cd ../.. ; \ cd docs ; \ cp ../../scripts/ports.json . ; \ cp ../../scripts/read_ports_json.py . ; \ From a2cbb8da972861b48e044696824beb92362513be Mon Sep 17 00:00:00 2001 From: Pagadarai Date: Wed, 22 Mar 2023 16:50:44 -0400 Subject: [PATCH 3/4] Minor fix to CI/gen_doc Makefile Signed-off-by: Pagadarai --- CI/gen_doc/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/CI/gen_doc/Makefile b/CI/gen_doc/Makefile index 5b729cf4..f1013b0a 100644 --- a/CI/gen_doc/Makefile +++ b/CI/gen_doc/Makefile @@ -49,6 +49,7 @@ doc_ml: MATLAB=ON python3 gen_all_doc.py ; \ cd .. ; \ mkdocs build -d doc + mv doc ../../ doc: cd docs ; \ From 421e41fbe3b5565f9ad76c251ef761221422c990 Mon Sep 17 00:00:00 2001 From: Pagadarai Date: Thu, 23 Mar 2023 15:00:53 -0400 Subject: [PATCH 4/4] MATLAB Doc toc fix Signed-off-by: Pagadarai --- CI/gen_doc/docs/_pages/targeting.md | 2 +- CI/gen_doc/docs/gen_md_pages.py | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/CI/gen_doc/docs/_pages/targeting.md b/CI/gen_doc/docs/_pages/targeting.md index a2535ad4..ca7812cf 100644 --- a/CI/gen_doc/docs/_pages/targeting.md +++ b/CI/gen_doc/docs/_pages/targeting.md @@ -1,4 +1,4 @@ - +{% include 'header.tmpl' %} # HDL Targeting with HDL-Coder High-Speed Converter Toolbox supports the IP Core generation flow from MathWorks which allows for automated integration of DSP into HDL reference designs from Analog Devices. This workflow will take Simulink subsystems, run HDL-Coder to generate source Verilog, and then integrate that into a larger reference design. The figure below is a simplified block diagram of a SoC (Fabric+ARM) device, where specialized IP are inserted into the receive and transmit datapaths. This is supported on specific FPGA families and high-speed based reference designs. This support is based on the Zynq HDL-Coder and support diff --git a/CI/gen_doc/docs/gen_md_pages.py b/CI/gen_doc/docs/gen_md_pages.py index fc3fa9f5..a8a289ee 100644 --- a/CI/gen_doc/docs/gen_md_pages.py +++ b/CI/gen_doc/docs/gen_md_pages.py @@ -33,6 +33,8 @@ def gen_toc(pages, devices, designs): template = env.get_template("toc.tmpl") + pages.remove('index') + pages.remove('ad9081') output = template.render(pages=pages, devices=devices, designs=designs) loc = os.path.dirname(__file__)