diff --git a/CI/gen_doc/docs/_pages/targeting.md b/CI/gen_doc/docs/_pages/targeting.md
index a2535ad4..ca7812cf 100644
--- a/CI/gen_doc/docs/_pages/targeting.md
+++ b/CI/gen_doc/docs/_pages/targeting.md
@@ -1,4 +1,4 @@
-
+{% include 'header.tmpl' %}
 # HDL Targeting with HDL-Coder
 
 High-Speed Converter Toolbox supports the IP Core generation flow from MathWorks which allows for automated integration of DSP into HDL reference designs from Analog Devices. This workflow will take Simulink subsystems, run HDL-Coder to generate source Verilog, and then integrate that into a larger reference design. The figure below is a simplified block diagram of a SoC (Fabric+ARM) device, where specialized IP are inserted into the receive and transmit datapaths. This is supported on specific FPGA families and high-speed based reference designs. This support is based on the Zynq HDL-Coder and support
diff --git a/CI/gen_doc/docs/gen_md_pages.py b/CI/gen_doc/docs/gen_md_pages.py
index fc3fa9f5..a8a289ee 100644
--- a/CI/gen_doc/docs/gen_md_pages.py
+++ b/CI/gen_doc/docs/gen_md_pages.py
@@ -33,6 +33,8 @@ def gen_toc(pages, devices, designs):
 
     template = env.get_template("toc.tmpl")
 
+    pages.remove('index')
+    pages.remove('ad9081')
     output = template.render(pages=pages, devices=devices, designs=designs)
 
     loc = os.path.dirname(__file__)