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CPU.qsf
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2013 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II 64-Bit
# Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
# Date created = 13:42:33 October 08, 2019
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# CPU_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name DEVICE EP4CE115F29C7
set_global_assignment -name TOP_LEVEL_ENTITY fpga
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:42:33 OCTOBER 08, 2019"
set_global_assignment -name LAST_QUARTUS_VERSION "13.0 SP1"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
set_global_assignment -name BDF_FILE ULA/mux.bdf
set_global_assignment -name BDF_FILE ULA/multi2.bdf
set_global_assignment -name BDF_FILE ULA/full_subtractor.bdf
set_global_assignment -name BDF_FILE ULA/full_adder.bdf
set_global_assignment -name BDF_FILE ULA/div2.bdf
set_global_assignment -name BDF_FILE ULA/adder_4bits.bdf
set_global_assignment -name BDF_FILE ULA/subtractor_4bits.bdf
set_global_assignment -name BDF_FILE ULA/ula.bdf
set_global_assignment -name BSF_FILE ULA/ula.bsf
set_global_assignment -name BDF_FILE 7seg.bdf
set_global_assignment -name BDF_FILE register.bdf
set_global_assignment -name QIP_FILE rom.qip
set_global_assignment -name QIP_FILE op_sel.qip
set_global_assignment -name BDF_FILE fpga.bdf
set_global_assignment -name BDF_FILE cpu.bdf
set_global_assignment -name BDF_FILE uc.bdf
set_global_assignment -name BDF_FILE counter.bdf
set_global_assignment -name QIP_FILE muxRg.qip
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_location_assignment PIN_Y2 -to fpga_clk
set_location_assignment PIN_AB25 -to clk
set_location_assignment PIN_AB28 -to reset
set_location_assignment PIN_G18 -to H0[0]
set_location_assignment PIN_F22 -to H0[1]
set_location_assignment PIN_E17 -to H0[2]
set_location_assignment PIN_L26 -to H0[3]
set_location_assignment PIN_L25 -to H0[4]
set_location_assignment PIN_J22 -to H0[5]
set_location_assignment PIN_H22 -to H0[6]
set_location_assignment PIN_M24 -to H1[0]
set_location_assignment PIN_Y22 -to H1[1]
set_location_assignment PIN_W21 -to H1[2]
set_location_assignment PIN_W22 -to H1[3]
set_location_assignment PIN_W25 -to H1[4]
set_location_assignment PIN_U23 -to H1[5]
set_location_assignment PIN_U24 -to H1[6]
set_location_assignment PIN_AA25 -to H2[0]
set_location_assignment PIN_AA26 -to H2[1]
set_location_assignment PIN_Y25 -to H2[2]
set_location_assignment PIN_W26 -to H2[3]
set_location_assignment PIN_Y26 -to H2[4]
set_location_assignment PIN_W27 -to H2[5]
set_location_assignment PIN_W28 -to H2[6]
set_location_assignment PIN_V21 -to H3[0]
set_location_assignment PIN_U21 -to H3[1]
set_location_assignment PIN_AB20 -to H3[2]
set_location_assignment PIN_AA21 -to H3[3]
set_location_assignment PIN_AD24 -to H3[4]
set_location_assignment PIN_AF23 -to H3[5]
set_location_assignment PIN_Y19 -to H3[6]
set_location_assignment PIN_AB19 -to H4[0]
set_location_assignment PIN_AA19 -to H4[1]
set_location_assignment PIN_AG21 -to H4[2]
set_location_assignment PIN_AH21 -to H4[3]
set_location_assignment PIN_AE19 -to H4[4]
set_location_assignment PIN_AF19 -to H4[5]
set_location_assignment PIN_AE18 -to H4[6]
set_location_assignment PIN_AA17 -to H6[0]
set_location_assignment PIN_AB16 -to H6[1]
set_location_assignment PIN_AA16 -to H6[2]
set_location_assignment PIN_AB17 -to H6[3]
set_location_assignment PIN_AB15 -to H6[4]
set_location_assignment PIN_AA15 -to H6[5]
set_location_assignment PIN_AC17 -to H6[6]
set_location_assignment PIN_G19 -to led[0]
set_location_assignment PIN_F19 -to led[1]
set_location_assignment PIN_E19 -to led[2]
set_location_assignment PIN_F21 -to led[3]
set_location_assignment PIN_F18 -to led[4]
set_location_assignment PIN_E18 -to led[5]
set_location_assignment PIN_J19 -to led[6]
set_location_assignment PIN_H19 -to led[7]
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top