From ab43a96a33a7bee2a1cda555f909d7c014d00a96 Mon Sep 17 00:00:00 2001
From: alaindargelas <63669492+alaindargelas@users.noreply.github.com>
Date: Wed, 24 Apr 2024 11:23:23 -0700
Subject: [PATCH] Revert "Update AST::process call arguments"

---
 frontends/systemverilog/compat_symbols.cc     | 19 +---------
 .../systemverilog/uhdm_common_frontend.cc     | 37 +++----------------
 2 files changed, 7 insertions(+), 49 deletions(-)

diff --git a/frontends/systemverilog/compat_symbols.cc b/frontends/systemverilog/compat_symbols.cc
index 25b08e0b8..874c8cebb 100644
--- a/frontends/systemverilog/compat_symbols.cc
+++ b/frontends/systemverilog/compat_symbols.cc
@@ -8,21 +8,4 @@ YOSYS_NAMESPACE_BEGIN
 #include "kernel/constids.inc"
 #undef X
 
-#ifdef __linux__
-namespace AST
-{
-extern void process(Design *, AstNode *, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool,
-                    bool, bool, bool);
-
-void __attribute__((weak))
-process(RTLIL::Design *design, AST::AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog1, bool dump_vlog2, bool dump_rtlil,
-        bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool noblackbox, bool lib, bool nowb, bool noopt, bool icells, bool pwires,
-        bool nooverwrite, bool overwrite, bool defer, bool autowire)
-{
-    process(design, ast, false, dump_ast1, dump_ast2, no_dump_ptr, dump_vlog1, dump_vlog2, dump_rtlil, nolatches, nomeminit, nomem2reg, mem2reg,
-            noblackbox, lib, nowb, noopt, icells, pwires, nooverwrite, overwrite, defer, autowire);
-}
-
-} // namespace AST
-#endif
-YOSYS_NAMESPACE_END
\ No newline at end of file
+YOSYS_NAMESPACE_END
diff --git a/frontends/systemverilog/uhdm_common_frontend.cc b/frontends/systemverilog/uhdm_common_frontend.cc
index a424d43bc..d242a7d48 100644
--- a/frontends/systemverilog/uhdm_common_frontend.cc
+++ b/frontends/systemverilog/uhdm_common_frontend.cc
@@ -20,20 +20,6 @@
 #include "uhdm_common_frontend.h"
 #include "synlig_edif.h"
 
-#ifdef __linux__
-namespace Yosys
-{
-using AST::AstNode;
-using RTLIL::Design;
-
-namespace AST
-{
-extern void process(Design *, AstNode *, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool, bool,
-                    bool, bool);
-} // namespace AST
-} // namespace Yosys
-#endif
-
 namespace systemverilog_plugin
 {
 
@@ -159,27 +145,16 @@ void UhdmCommonFrontend::execute(std::istream *&f, std::string filename, std::ve
     AST::set_line_num = &set_line_num;
     AST::get_line_num = &get_line_num;
 
+    bool dont_redefine = false;
+    bool default_nettype_wire = true;
+
     AST::AstNode *current_ast = parse(filename);
 
     if (current_ast) {
-        Yosys::AST::process(design, current_ast, dump_ast1, dump_ast2, no_dump_ptr, dump_vlog1, dump_vlog2, dump_rtlil,
-                            false, // nolatches
-                            false, // nomeminit
-                            false, // nomem2reg
-                            false, // mem2reg
-                            false, // noblackbox
-                            false, // lib
-                            false, // nowb
-                            false, // noopt
-                            false, // icells
-                            false, // pwires
-                            false, // nooverwrite
-                            false, // overwrite
-                            defer, // defer
-                            true   // autowire
-        );
+        AST::process(design, current_ast, dump_ast1, dump_ast2, no_dump_ptr, dump_vlog1, dump_vlog2, dump_rtlil, false, false, false, false, false,
+                     false, false, false, false, false, dont_redefine, false, defer, default_nettype_wire);
         delete current_ast;
     }
 }
 
-} // namespace systemverilog_plugin
\ No newline at end of file
+} // namespace systemverilog_plugin