fad.snk

# comment
Clr R0
Clr R1
Clr R2
Clr R3
Clr R4
Clr R5
Clr R6
Clr R7
Clr R8
Clr R9
Clr R10
Clr R11
Clr R12
Clr R13
Clr R14
Clr R15

# Load MSB's and LSB's of float into R2 and R3
Assign 127
Inc R1
Ld R2
Inc R1
Ld R3
Inc R1
Ld R4
Inc R1
Ld R5
Inc R1
Set R0

# get E of F1 and F2 into R7 and R8 respectively
Assign R2
Set R7
Assign R4
Set R8
Assign 1
Sl R7
Sl R8
Assign 3
Sr R7
Sr R8

# put sign and exp in 6 and 7 and 14 and 15
Assign R2
Set r6
set r7
Assign R4
Set r14
set r15
Assign 7
Sr R6
Sl r6
Sr R14
Sl r14
Assign 1
Sl R7
Sl R15
Assign 3
Sr R7
Sr R15

# clear Sign and E and restore Hidden bit of R2 and R4
Assign 6
Sl R2
Sr R2 
Sl R4
Sr R4
Assign 4
Or R2
Or R4


# get R9:(E1-E2) and R10:(E2-E1), if R9>R10: EXP(A) greater, etc
Assign R7
Set R9
Assign R15
Set R10
Assign R15
Sub R9
Assign R7
Sub R10
Assign R9
Set R12
Assign R10
Sub R12


# if sign = 0, R9 is positive meaning E1 > E2 
Assign 7
Sr R12
Assign 19
Bz R12

# switch registers and use E2-E1 shift value
Assign r14
Set r6
Assign r15
Set r7
Assign r10
Set r9

Assign r2
Set r10
Assign r3
Set r11
Assign r4
Set r2
Assign r5
Set r3
Assign r10
Set r4
Assign r11
Set r5

# if r9 > 8, do first shift to get it below 8
Assign r9
Set r10
Assign 9
Sub R10
Assign 7
Sr R10
Clr r12
Assign 24
BNZ R10

Clr R11
Assign r9
Set r10
Assign 8
Sub r10

#shift right by r10
Assign r4
Set r11
Assign r5
Set r12

Assign r10
Sr r4
Sr r5

Assign 8
Set r13
Assign r10
Sub r13

Assign r13
Sl r11
Sl r12

Assign r11
Or r5

Assign 8
Set R9

#shift right by R9
Assign 17
BZ R9

Assign r4
Set r11
Assign r5
Set r10

Assign r9
Sr r4
Sr r5

Assign 8
Set r13
Assign r9
Sub r13

Assign r13
Sl r11
Sl r10

Assign r11
Or r5

#### Step 3 - Add mantissas ###
Assign R5
Add R3
Adc R2
Assign R4
Add R2

#### Calculate U,R,S bit ####
# lsb of R5 is U bit -> R7 
Assign R3
Set R8
Assign 7
Sl R8
# R Bit(r9) is r10[7] and S Bit(r10) is or(r10[6:0]+r11)
Assign R10
Set R9
Assign 7
Sr R9
Assign 1
Sl R10
Assign r12
Or R10

# skip rounding if R bit is 0
Assign 8
BZ R9

# skip rounding if U(r7) or S(r10) bits are 0
Assign r8
Or r10
Assign 4
BZ R10

# rounding
Assign 1
Add R3
Adc R2

# overflow case
Assign R2
Set R4
Assign 8 
And R4
Assign 28
Bz R4

# right shift by 1
Assign R2
Set R5

Assign 1
Sr R2
Sr R3

Assign 7
Sl R5

Assign R5
Or R3

# increment exponent
Inc R7

Assign R7
Set R8
Assign 32
And R8
Assign 12
Bz R8

Assign 127
Set R9
Assign R6
Or r9
Clr R10
Dec r10
Assign r0
St r9
Inc r1
st r10
HALT

#### set up final float ####
# clear hidden bit from mantissa
Assign 6
Sl R2
Sr R2

# add exponent to mantissa
Assign 2
Sl r7
Assign r7
Or r2

# add sign bit to final
Assign r6
Or r2

## Return Code ## 
Assign R0
St r2
Inc R1
St r3
HALT