diff --git a/lab4/gA6_rules_dealer.bdf b/lab5/Block2.bdf similarity index 52% rename from lab4/gA6_rules_dealer.bdf rename to lab5/Block2.bdf index 8a377e0..38f77f2 100644 --- a/lab4/gA6_rules_dealer.bdf +++ b/lab5/Block2.bdf @@ -21,41 +21,9 @@ applicable agreement for further details. (header "graphic" (version "1.4")) (pin (input) - (rect 320 304 496 320) - (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) - (text "new_card[5..0]" (rect 9 0 80 12)(font "Arial" )) - (pt 176 8) - (drawing - (line (pt 92 12)(pt 117 12)) - (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) - (line (pt 92 12)(pt 92 4)) - (line (pt 117 4)(pt 121 8)) - (line (pt 117 12)(pt 121 8)) - ) - (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) -) -(pin - (input) - (rect 320 320 496 336) - (text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6))) - (text "hand_sum[5..0]" (rect 5 0 81 12)(font "Arial" )) - (pt 176 8) - (drawing - (line (pt 92 12)(pt 117 12)) - (line (pt 92 4)(pt 117 4)) - (line (pt 121 8)(pt 176 8)) - (line (pt 92 12)(pt 92 4)) - (line (pt 117 4)(pt 121 8)) - (line (pt 117 12)(pt 121 8)) - ) - (text "VCC" (rect 136 7 156 17)(font "Arial" (font_size 6))) -) -(pin - (input) - (rect 344 128 512 144) + (rect 728 104 896 120) (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) - (text "clk" (rect 5 0 20 12)(font "Arial" )) + (text "clk" (rect 5 0 19 12)(font "Arial" )) (pt 168 8) (drawing (line (pt 84 12)(pt 109 12)) @@ -69,9 +37,25 @@ applicable agreement for further details. ) (pin (input) - (rect 344 144 512 160) + (rect 392 336 576 352) + (text "INPUT" (rect 141 0 169 10)(font "Arial" (font_size 6))) + (text "player_sum[5..0]" (rect 5 0 88 12)(font "Arial" )) + (pt 184 8) + (drawing + (line (pt 100 12)(pt 125 12)) + (line (pt 100 4)(pt 125 4)) + (line (pt 129 8)(pt 184 8)) + (line (pt 100 12)(pt 100 4)) + (line (pt 125 4)(pt 129 8)) + (line (pt 125 12)(pt 129 8)) + ) + (text "VCC" (rect 144 7 164 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 544 200 712 216) (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) - (text "rst" (rect 5 0 18 12)(font "Arial" )) + (text "rst" (rect 5 0 17 12)(font "Arial" )) (pt 168 8) (drawing (line (pt 84 12)(pt 109 12)) @@ -85,9 +69,9 @@ applicable agreement for further details. ) (pin (input) - (rect 344 160 512 176) + (rect 544 216 712 232) (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) - (text "legal_num" (rect 5 0 55 12)(font "Arial" )) + (text "turn" (rect 5 0 23 12)(font "Arial" )) (pt 168 8) (drawing (line (pt 84 12)(pt 109 12)) @@ -101,9 +85,9 @@ applicable agreement for further details. ) (pin (input) - (rect 344 176 512 192) + (rect 544 232 712 248) (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) - (text "request_deal" (rect 5 0 68 12)(font "Arial" )) + (text "sum[5..0]" (rect 5 0 52 12)(font "Arial" )) (pt 168 8) (drawing (line (pt 84 12)(pt 109 12)) @@ -117,9 +101,25 @@ applicable agreement for further details. ) (pin (output) - (rect 784 304 960 320) + (rect 920 184 1096 200) + (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) + (text "hit" (rect 90 0 101 12)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) +) +(pin + (output) + (rect 920 200 1096 216) (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) - (text "legal_play" (rect 90 0 139 12)(font "Arial" )) + (text "done" (rect 90 0 113 12)(font "Arial" )) (pt 0 8) (drawing (line (pt 0 8)(pt 52 8)) @@ -133,9 +133,9 @@ applicable agreement for further details. ) (pin (output) - (rect 784 288 960 304) + (rect 944 216 1120 232) (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) - (text "ace_out" (rect 90 0 128 12)(font "Arial" )) + (text "sum_out[5..0]" (rect 90 0 158 12)(font "Arial" )) (pt 0 8) (drawing (line (pt 0 8)(pt 52 8)) @@ -149,9 +149,9 @@ applicable agreement for further details. ) (pin (output) - (rect 784 336 960 352) + (rect 944 320 1120 336) (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) - (text "out_2[5..0]" (rect 90 0 143 12)(font "Arial" )) + (text "player_wins" (rect 90 0 147 12)(font "Arial" )) (pt 0 8) (drawing (line (pt 0 8)(pt 52 8)) @@ -165,9 +165,9 @@ applicable agreement for further details. ) (pin (output) - (rect 784 352 960 368) + (rect 944 336 1120 352) (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) - (text "out_3[5..0]" (rect 90 0 143 12)(font "Arial" )) + (text "dealer_wins" (rect 90 0 146 12)(font "Arial" )) (pt 0 8) (drawing (line (pt 0 8)(pt 52 8)) @@ -181,9 +181,9 @@ applicable agreement for further details. ) (pin (output) - (rect 784 368 960 384) + (rect 944 352 1127 368) (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) - (text "out_4" (rect 90 0 117 12)(font "Arial" )) + (text "led_display1[6..0]" (rect 90 0 177 12)(font "Arial" )) (pt 0 8) (drawing (line (pt 0 8)(pt 52 8)) @@ -197,9 +197,9 @@ applicable agreement for further details. ) (pin (output) - (rect 784 320 960 336) + (rect 944 368 1127 384) (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) - (text "out_1[5..0]" (rect 90 0 143 12)(font "Arial" )) + (text "led_display2[6..0]" (rect 90 0 177 12)(font "Arial" )) (pt 0 8) (drawing (line (pt 0 8)(pt 52 8)) @@ -213,9 +213,9 @@ applicable agreement for further details. ) (pin (output) - (rect 784 384 960 400) + (rect 944 384 1127 400) (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) - (text "out_5" (rect 90 0 117 12)(font "Arial" )) + (text "led_display3[6..0]" (rect 90 0 177 12)(font "Arial" )) (pt 0 8) (drawing (line (pt 0 8)(pt 52 8)) @@ -229,9 +229,9 @@ applicable agreement for further details. ) (pin (output) - (rect 760 128 936 144) + (rect 944 400 1127 416) (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) - (text "rand_enable" (rect 90 0 149 12)(font "Arial" )) + (text "led_display4[6..0]" (rect 90 0 177 12)(font "Arial" )) (pt 0 8) (drawing (line (pt 0 8)(pt 52 8)) @@ -245,9 +245,9 @@ applicable agreement for further details. ) (pin (output) - (rect 760 144 936 160) + (rect 944 232 1120 248) (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) - (text "stack_enable" (rect 90 0 154 12)(font "Arial" )) + (text "state_out[1..0]" (rect 90 0 161 12)(font "Arial" )) (pt 0 8) (drawing (line (pt 0 8)(pt 52 8)) @@ -260,87 +260,80 @@ applicable agreement for further details. ) ) (symbol - (rect 536 264 744 440) - (text "gA6_rules" (rect 5 0 53 12)(font "Arial" )) - (text "inst" (rect 8 160 25 172)(font "Arial" )) + (rect 696 296 936 440) + (text "gA6_winner" (rect 5 0 60 12)(font "Arial" )) + (text "inst1" (rect 8 128 31 140)(font "Arial" )) (port (pt 0 32) (input) - (text "ace" (rect 0 0 17 12)(font "Arial" )) - (text "ace" (rect 21 27 38 39)(font "Arial" )) + (text "clk" (rect 0 0 14 12)(font "Arial" )) + (text "clk" (rect 21 27 35 39)(font "Arial" )) (line (pt 0 32)(pt 16 32)) ) (port (pt 0 48) (input) - (text "new_card[5..0]" (rect 0 0 71 12)(font "Arial" )) - (text "new_card[5..0]" (rect 21 43 92 55)(font "Arial" )) + (text "player_sum[5..0]" (rect 0 0 83 12)(font "Arial" )) + (text "player_sum[5..0]" (rect 21 43 104 55)(font "Arial" )) (line (pt 0 48)(pt 16 48)(line_width 3)) ) (port (pt 0 64) (input) - (text "hand_sum[5..0]" (rect 0 0 76 12)(font "Arial" )) - (text "hand_sum[5..0]" (rect 21 59 97 71)(font "Arial" )) + (text "dealer_sum[5..0]" (rect 0 0 82 12)(font "Arial" )) + (text "dealer_sum[5..0]" (rect 21 59 103 71)(font "Arial" )) (line (pt 0 64)(pt 16 64)(line_width 3)) ) (port - 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(line (pt 208 80)(pt 192 80)(line_width 3)) + (text "led_display1[6..0]" (rect 0 0 87 12)(font "Arial" )) + (text "led_display1[6..0]" (rect 146 59 233 71)(font "Arial" )) + (line (pt 240 64)(pt 224 64)(line_width 3)) ) (port - (pt 208 96) + (pt 240 80) (output) - (text "out_3[5..0]" (rect 0 0 53 12)(font "Arial" )) - (text "out_3[5..0]" (rect 143 91 196 103)(font "Arial" )) - (line (pt 208 96)(pt 192 96)(line_width 3)) + (text "led_display2[6..0]" (rect 0 0 87 12)(font "Arial" )) + (text "led_display2[6..0]" (rect 146 75 233 87)(font "Arial" )) + (line (pt 240 80)(pt 224 80)(line_width 3)) ) (port - (pt 208 112) + (pt 240 96) (output) - (text "out_4" (rect 0 0 27 12)(font "Arial" )) - (text "out_4" (rect 165 107 192 119)(font "Arial" )) - (line (pt 208 112)(pt 192 112)) + (text "led_display3[6..0]" (rect 0 0 87 12)(font "Arial" )) + (text "led_display3[6..0]" (rect 146 91 233 103)(font "Arial" )) + (line (pt 240 96)(pt 224 96)(line_width 3)) ) (port - (pt 208 128) + (pt 240 112) (output) - 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168) - (pt 536 168) + (pt 576 344) + (pt 696 344) + (bus) ) (connector - (pt 512 184) - (pt 536 184) + (pt 632 360) + (pt 632 288) + (bus) ) (connector - (pt 736 136) - (pt 760 136) + (pt 632 360) + (pt 696 360) + (bus) +) +(connector + (pt 912 240) + (pt 944 240) + (bus) ) (connector - (pt 736 152) - (pt 760 152) + (pt 912 224) + (pt 928 224) + (bus) ) (connector - (pt 512 240) - (pt 512 296) + (pt 928 224) + (pt 944 224) + (bus) ) -(junction (pt 760 296)) +(junction (pt 928 224)) diff --git a/lab5/db/gA6_lab5.(0).cnf.cdb b/lab5/db/gA6_lab5.(0).cnf.cdb new file mode 100644 index 0000000..fb7712c Binary files /dev/null and b/lab5/db/gA6_lab5.(0).cnf.cdb differ diff --git a/lab5/db/gA6_lab5.(0).cnf.hdb b/lab5/db/gA6_lab5.(0).cnf.hdb new file mode 100644 index 0000000..7239856 Binary files /dev/null and b/lab5/db/gA6_lab5.(0).cnf.hdb differ diff --git a/lab5/db/gA6_lab5.(1).cnf.cdb b/lab5/db/gA6_lab5.(1).cnf.cdb new file mode 100644 index 0000000..189940b Binary files /dev/null and b/lab5/db/gA6_lab5.(1).cnf.cdb differ diff --git a/lab5/db/gA6_lab5.(1).cnf.hdb b/lab5/db/gA6_lab5.(1).cnf.hdb new file mode 100644 index 0000000..20d50db Binary files /dev/null and b/lab5/db/gA6_lab5.(1).cnf.hdb differ diff --git a/lab5/db/gA6_lab5.(2).cnf.cdb b/lab5/db/gA6_lab5.(2).cnf.cdb new file mode 100644 index 0000000..e99abc5 Binary files /dev/null and b/lab5/db/gA6_lab5.(2).cnf.cdb differ diff --git a/lab5/db/gA6_lab5.(2).cnf.hdb b/lab5/db/gA6_lab5.(2).cnf.hdb new file mode 100644 index 0000000..23ebeef Binary files /dev/null and b/lab5/db/gA6_lab5.(2).cnf.hdb differ diff --git a/lab5/db/gA6_lab5.asm.qmsg b/lab5/db/gA6_lab5.asm.qmsg new file mode 100644 index 0000000..1b47979 --- /dev/null +++ b/lab5/db/gA6_lab5.asm.qmsg @@ -0,0 +1,6 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1511999677653 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II 64-Bit " "Running Quartus II 64-Bit Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Web Edition " "Version 13.0.0 Build 156 04/24/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1511999677654 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 29 18:54:37 2017 " "Processing started: Wed Nov 29 18:54:37 2017" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1511999677654 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Assembler" 0 -1 1511999677654 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off gA6_lab5 -c gA6_lab5 " "Command: quartus_asm --read_settings_files=off --write_settings_files=off gA6_lab5 -c gA6_lab5" { } { } 0 0 "Command: %1!s!" 0 0 "Assembler" 0 -1 1511999677654 ""} +{ "Info" "IASM_ASM_GENERATING_POWER_DATA" "" "Writing out detailed assembly data for power analysis" { } { } 0 115031 "Writing out detailed assembly data for power analysis" 0 0 "Assembler" 0 -1 1511999679168 ""} +{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Assembler is generating device programming files" { } { } 0 115030 "Assembler is generating device programming files" 0 0 "Assembler" 0 -1 1511999679235 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "499 " "Peak virtual memory: 499 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1511999680029 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 29 18:54:40 2017 " "Processing ended: Wed Nov 29 18:54:40 2017" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1511999680029 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1511999680029 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1511999680029 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Assembler" 0 -1 1511999680029 ""} diff --git a/lab5/db/gA6_lab5.asm.rdb b/lab5/db/gA6_lab5.asm.rdb new file mode 100644 index 0000000..81c018b Binary files /dev/null and b/lab5/db/gA6_lab5.asm.rdb differ diff --git a/lab5/db/gA6_lab5.asm_labs.ddb b/lab5/db/gA6_lab5.asm_labs.ddb new file mode 100644 index 0000000..7fdcefb Binary files /dev/null and b/lab5/db/gA6_lab5.asm_labs.ddb differ diff --git a/lab5/db/gA6_lab5.cbx.xml b/lab5/db/gA6_lab5.cbx.xml new file mode 100644 index 0000000..8d065f1 --- /dev/null +++ b/lab5/db/gA6_lab5.cbx.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/lab5/db/gA6_lab5.cmp.bpm b/lab5/db/gA6_lab5.cmp.bpm new file mode 100644 index 0000000..a49dfe6 Binary files /dev/null and b/lab5/db/gA6_lab5.cmp.bpm differ diff --git a/lab5/db/gA6_lab5.cmp.cdb b/lab5/db/gA6_lab5.cmp.cdb new file mode 100644 index 0000000..04b278d Binary files /dev/null and b/lab5/db/gA6_lab5.cmp.cdb differ diff --git a/lab5/db/gA6_lab5.cmp.hdb b/lab5/db/gA6_lab5.cmp.hdb new file mode 100644 index 0000000..0ef6f29 Binary files /dev/null and b/lab5/db/gA6_lab5.cmp.hdb differ diff --git a/lab5/db/gA6_lab5.cmp.idb b/lab5/db/gA6_lab5.cmp.idb new file mode 100644 index 0000000..df1c7e0 Binary files /dev/null and b/lab5/db/gA6_lab5.cmp.idb differ diff --git a/lab5/db/gA6_lab5.cmp.kpt b/lab5/db/gA6_lab5.cmp.kpt new file mode 100644 index 0000000..40cbdaa Binary files /dev/null and b/lab5/db/gA6_lab5.cmp.kpt differ diff --git a/lab5/db/gA6_lab5.cmp.logdb b/lab5/db/gA6_lab5.cmp.logdb new file mode 100644 index 0000000..d45424f --- /dev/null +++ b/lab5/db/gA6_lab5.cmp.logdb @@ -0,0 +1 @@ +v1 diff --git a/lab5/db/gA6_lab5.cmp.rdb b/lab5/db/gA6_lab5.cmp.rdb new file mode 100644 index 0000000..f4efcd1 Binary files /dev/null and b/lab5/db/gA6_lab5.cmp.rdb differ diff --git a/lab5/db/gA6_lab5.cmp0.ddb b/lab5/db/gA6_lab5.cmp0.ddb new file mode 100644 index 0000000..7ce6dcd Binary files /dev/null and b/lab5/db/gA6_lab5.cmp0.ddb differ diff --git a/lab5/db/gA6_lab5.cmp1.ddb b/lab5/db/gA6_lab5.cmp1.ddb new file mode 100644 index 0000000..7a5c5ba Binary files /dev/null and b/lab5/db/gA6_lab5.cmp1.ddb differ diff --git a/lab5/db/gA6_lab5.cmp2.ddb b/lab5/db/gA6_lab5.cmp2.ddb new file mode 100644 index 0000000..5c765a2 Binary files /dev/null and b/lab5/db/gA6_lab5.cmp2.ddb differ diff --git a/lab5/db/gA6_lab5.cmp_merge.kpt b/lab5/db/gA6_lab5.cmp_merge.kpt new file mode 100644 index 0000000..b378aa1 Binary files /dev/null and b/lab5/db/gA6_lab5.cmp_merge.kpt differ diff --git a/lab5/db/gA6_lab5.db_info b/lab5/db/gA6_lab5.db_info new file mode 100644 index 0000000..7442402 --- /dev/null +++ b/lab5/db/gA6_lab5.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 13.0.0 Build 156 04/24/2013 SJ Web Edition +Version_Index = 302029824 +Creation_Time = Thu Nov 30 11:17:41 2017 diff --git a/lab5/db/gA6_lab5.eda.qmsg b/lab5/db/gA6_lab5.eda.qmsg new file mode 100644 index 0000000..ae6c072 --- /dev/null +++ b/lab5/db/gA6_lab5.eda.qmsg @@ -0,0 +1,5 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1511999705103 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "EDA Netlist Writer Quartus II 64-Bit " "Running Quartus II 64-Bit EDA Netlist Writer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Web Edition " "Version 13.0.0 Build 156 04/24/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1511999705104 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 29 18:55:04 2017 " "Processing started: Wed Nov 29 18:55:04 2017" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1511999705104 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1511999705104 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_eda --functional=on --simulation=on --tool=modelsim_oem --format=verilog gA6_lab5 -c gA6_lab5 " "Command: quartus_eda --functional=on --simulation=on --tool=modelsim_oem --format=verilog gA6_lab5 -c gA6_lab5" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1511999705104 ""} +{ "Info" "IWSC_DONE_HDL_GENERATION" "gA6_lab5.vo C:/home/abbas/dsd_A6/lab5/simulation/modelsim/ simulation " "Generated file gA6_lab5.vo in folder \"C:/home/abbas/dsd_A6/lab5/simulation/modelsim/\" for EDA simulation tool" { } { } 0 204019 "Generated file %1!s! in folder \"%2!s!\" for EDA %3!s! tool" 0 0 "Quartus II" 0 -1 1511999705741 ""} +{ "Info" "IQEXE_ERROR_COUNT" "EDA Netlist Writer 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "459 " "Peak virtual memory: 459 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1511999705844 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 29 18:55:05 2017 " "Processing ended: Wed Nov 29 18:55:05 2017" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1511999705844 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1511999705844 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1511999705844 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1511999705844 ""} diff --git a/lab5/db/gA6_lab5.fit.qmsg b/lab5/db/gA6_lab5.fit.qmsg new file mode 100644 index 0000000..b0fb8d6 --- /dev/null +++ b/lab5/db/gA6_lab5.fit.qmsg @@ -0,0 +1,46 @@ +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "2 2 4 " "Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead." { } { } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Fitter" 0 -1 1511999669234 ""} +{ "Info" "IMPP_MPP_USER_DEVICE" "gA6_lab5 EP2C20F484C7 " "Selected device EP2C20F484C7 for design \"gA6_lab5\"" { } { } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1511999669244 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1511999669295 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Fitter" 0 -1 1511999669296 ""} +{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 171003 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1511999669389 ""} +{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." { } { } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1511999669403 ""} +{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C15AF484C7 " "Device EP2C15AF484C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1511999670047 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C35F484C7 " "Device EP2C35F484C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1511999670047 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F484C7 " "Device EP2C50F484C7 is compatible" { } { } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1511999670047 ""} } { } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1511999670047 ""} +{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ C4 " "Pin ~ASDO~ is reserved at location C4" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { ~ASDO~ } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 154 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1511999670049 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ C3 " "Pin ~nCSO~ is reserved at location C3" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { ~nCSO~ } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 155 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1511999670049 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS91p/nCEO~ W20 " "Pin ~LVDS91p/nCEO~ is reserved at location W20" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { ~LVDS91p/nCEO~ } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~LVDS91p/nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 156 9224 9983 0} } } } } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1511999670049 ""} } { } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1511999670049 ""} +{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "55 55 " "No exact pin location assignment(s) for 55 pins of 55 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "hit " "Pin hit not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { hit } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 160 384 560 176 "hit" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { hit } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 61 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "done " "Pin done not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { done } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 176 384 560 192 "done" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { done } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 65 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "player_wins " "Pin player_wins not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { player_wins } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 296 408 584 312 "player_wins" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { player_wins } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 66 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "dealer_wins " "Pin dealer_wins not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { dealer_wins } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 312 408 584 328 "dealer_wins" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { dealer_wins } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 67 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "led_display1\[6\] " "Pin led_display1\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { led_display1[6] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 328 408 591 344 "led_display1" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { led_display1[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 25 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "led_display1\[5\] " "Pin led_display1\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { led_display1[5] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 328 408 591 344 "led_display1" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { led_display1[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 26 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "led_display1\[4\] " "Pin led_display1\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { led_display1[4] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 328 408 591 344 "led_display1" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { led_display1[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 27 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "led_display1\[3\] " "Pin led_display1\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { led_display1[3] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 328 408 591 344 "led_display1" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { led_display1[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 28 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "led_display1\[2\] " "Pin led_display1\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { led_display1[2] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 328 408 591 344 "led_display1" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { led_display1[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 29 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "led_display1\[1\] " "Pin led_display1\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { led_display1[1] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 328 408 591 344 "led_display1" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { led_display1[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 30 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "led_display1\[0\] " "Pin led_display1\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { led_display1[0] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 328 408 591 344 "led_display1" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { led_display1[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 31 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "led_display2\[6\] " "Pin led_display2\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { led_display2[6] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 344 408 591 360 "led_display2" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { led_display2[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 32 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "led_display2\[5\] " "Pin led_display2\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { led_display2[5] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 344 408 591 360 "led_display2" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { led_display2[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 33 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "led_display2\[4\] " "Pin led_display2\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { led_display2[4] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 344 408 591 360 "led_display2" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { led_display2[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 34 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "led_display2\[3\] " "Pin led_display2\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { led_display2[3] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 344 408 591 360 "led_display2" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { led_display2[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 35 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "led_display2\[2\] " "Pin led_display2\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { led_display2[2] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 344 408 591 360 "led_display2" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { led_display2[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 36 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "led_display2\[1\] " "Pin led_display2\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { led_display2[1] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 344 408 591 360 "led_display2" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { led_display2[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 37 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "led_display2\[0\] " "Pin led_display2\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { led_display2[0] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 344 408 591 360 "led_display2" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { led_display2[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 38 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "led_display3\[6\] " "Pin led_display3\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { led_display3[6] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 360 408 591 376 "led_display3" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { led_display3[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 39 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "led_display3\[5\] " "Pin led_display3\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { led_display3[5] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 360 408 591 376 "led_display3" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { led_display3[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 40 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "led_display3\[4\] " "Pin led_display3\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { led_display3[4] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 360 408 591 376 "led_display3" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { led_display3[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 41 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "led_display3\[3\] " "Pin led_display3\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { led_display3[3] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 360 408 591 376 "led_display3" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { led_display3[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 42 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "led_display3\[2\] " "Pin led_display3\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { led_display3[2] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 360 408 591 376 "led_display3" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { led_display3[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 43 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "led_display3\[1\] " "Pin led_display3\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { led_display3[1] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 360 408 591 376 "led_display3" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { led_display3[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 44 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "led_display3\[0\] " "Pin led_display3\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { led_display3[0] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 360 408 591 376 "led_display3" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { led_display3[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 45 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "led_display4\[6\] " "Pin led_display4\[6\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { led_display4[6] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 376 408 591 392 "led_display4" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { led_display4[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 46 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "led_display4\[5\] " "Pin led_display4\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { led_display4[5] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 376 408 591 392 "led_display4" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { led_display4[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 47 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "led_display4\[4\] " "Pin led_display4\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { led_display4[4] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 376 408 591 392 "led_display4" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { led_display4[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 48 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "led_display4\[3\] " "Pin led_display4\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { led_display4[3] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 376 408 591 392 "led_display4" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { led_display4[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 49 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "led_display4\[2\] " "Pin led_display4\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { led_display4[2] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 376 408 591 392 "led_display4" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { led_display4[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 50 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "led_display4\[1\] " "Pin led_display4\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { led_display4[1] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 376 408 591 392 "led_display4" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { led_display4[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 51 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "led_display4\[0\] " "Pin led_display4\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { led_display4[0] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 376 408 591 392 "led_display4" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { led_display4[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 52 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "state_out\[1\] " "Pin state_out\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { state_out[1] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 208 408 584 224 "state_out" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { state_out[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 53 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "state_out\[0\] " "Pin state_out\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { state_out[0] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 208 408 584 224 "state_out" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { state_out[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 54 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "sum_out\[5\] " "Pin sum_out\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { sum_out[5] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 192 408 584 208 "sum_out" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sum_out[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 55 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "sum_out\[4\] " "Pin sum_out\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { sum_out[4] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 192 408 584 208 "sum_out" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sum_out[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 56 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "sum_out\[3\] " "Pin sum_out\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { sum_out[3] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 192 408 584 208 "sum_out" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sum_out[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 57 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "sum_out\[2\] " "Pin sum_out\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { sum_out[2] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 192 408 584 208 "sum_out" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sum_out[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 58 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "sum_out\[1\] " "Pin sum_out\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { sum_out[1] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 192 408 584 208 "sum_out" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sum_out[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 59 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "sum_out\[0\] " "Pin sum_out\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { sum_out[0] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 192 408 584 208 "sum_out" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sum_out[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 60 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "sum\[5\] " "Pin sum\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { sum[5] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 208 8 176 224 "sum" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sum[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 13 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "sum\[4\] " "Pin sum\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { sum[4] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 208 8 176 224 "sum" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sum[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 14 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "sum\[3\] " "Pin sum\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { sum[3] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 208 8 176 224 "sum" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sum[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 15 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "sum\[2\] " "Pin sum\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { sum[2] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 208 8 176 224 "sum" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sum[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 16 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "sum\[1\] " "Pin sum\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { sum[1] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 208 8 176 224 "sum" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sum[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 17 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "sum\[0\] " "Pin sum\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { sum[0] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 208 8 176 224 "sum" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { sum[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 18 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "clk " "Pin clk not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { clk } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 80 192 360 96 "clk" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 62 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "rst " "Pin rst not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { rst } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 176 8 176 192 "rst" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 63 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "player_sum\[5\] " "Pin player_sum\[5\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { player_sum[5] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 312 -144 40 328 "player_sum" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { player_sum[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 19 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "player_sum\[4\] " "Pin player_sum\[4\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { player_sum[4] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 312 -144 40 328 "player_sum" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { player_sum[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 20 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "player_sum\[3\] " "Pin player_sum\[3\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { player_sum[3] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 312 -144 40 328 "player_sum" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { player_sum[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 21 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "player_sum\[2\] " "Pin player_sum\[2\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { player_sum[2] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 312 -144 40 328 "player_sum" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { player_sum[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 22 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "player_sum\[1\] " "Pin player_sum\[1\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { player_sum[1] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 312 -144 40 328 "player_sum" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { player_sum[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 23 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "player_sum\[0\] " "Pin player_sum\[0\] not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { player_sum[0] } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 312 -144 40 328 "player_sum" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { player_sum[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 24 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "turn " "Pin turn not assigned to an exact location on the device" { } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { turn } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 192 8 176 208 "turn" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { turn } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 64 9224 9983 0} } } } } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1511999670158 ""} } { } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1511999670158 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "gA6_lab5.sdc " "Synopsys Design Constraints File file not found: 'gA6_lab5.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1511999670322 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" { } { } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1511999670323 ""} +{ "Info" "ISTA_TDC_NO_DEFAULT_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." { } { } 0 332130 "Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time." 0 0 "Fitter" 0 -1 1511999670326 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk (placed in PIN M1 (CLK2, LVDSCLK1p, Input)) " "Automatically promoted node clk (placed in PIN M1 (CLK2, LVDSCLK1p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G3 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1511999670346 ""} } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { clk } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 80 192 360 96 "clk" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 62 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1511999670346 ""} +{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "rst (placed in PIN M2 (CLK3, LVDSCLK1n, Input)) " "Automatically promoted node rst (placed in PIN M2 (CLK3, LVDSCLK1n, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G1 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1" { } { } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1511999670346 ""} } { { "c:/altera/13.0/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0/quartus/bin64/pin_planner.ppl" { rst } } } { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 176 8 176 192 "rst" "" } } } } { "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0/quartus/bin64/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 0 { 0 ""} 0 63 9224 9983 0} } } } } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1511999670346 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" { } { } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1511999670438 ""} +{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" { } { } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1511999670439 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" { } { } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1511999670439 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" { } { } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1511999670440 ""} +{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" { } { } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1511999670441 ""} +{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" { } { } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1511999670442 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" { } { } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1511999670442 ""} +{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" { } { } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1511999670442 ""} +{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" { } { } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1511999670461 ""} +{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" { } { } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1511999670462 ""} } { } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1511999670462 ""} +{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "53 unused 3.3V 13 40 0 " "Number of I/O pins in group: 53 (unused VREF, 3.3V VCCIO, 13 input, 40 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." { } { } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1511999670465 ""} } { } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1511999670465 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1511999670465 ""} +{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use undetermined 2 39 " "I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 39 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1511999670466 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use undetermined 2 31 " "I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 31 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1511999670466 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use undetermined 0 43 " "I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1511999670466 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use undetermined 0 40 " "I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1511999670466 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use undetermined 0 39 " "I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 39 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1511999670466 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use undetermined 1 35 " "I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 35 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1511999670466 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 40 " "I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1511999670466 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use undetermined 0 43 " "I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available" { } { } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "Quartus II" 0 -1 1511999670466 ""} } { } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1511999670466 ""} } { } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1511999670466 ""} +{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Fitter preparation operations ending: elapsed time is 00:00:00" { } { } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1511999670502 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" { } { } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1511999671704 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1511999671821 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" { } { } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1511999671834 ""} +{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" { } { } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1511999672662 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:01 " "Fitter placement operations ending: elapsed time is 00:00:01" { } { } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1511999672662 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" { } { } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1511999672748 ""} +{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Router estimated average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y0 X11_Y13 " "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X11_Y13" { } { { "loc" "" { Generic "C:/home/abbas/dsd_A6/lab5/" { { 1 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X11_Y13"} { { 11 { 0 "Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X11_Y13"} 0 0 12 14 } } } } } } } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1511999674897 ""} } { } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1511999674897 ""} +{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:02 " "Fitter routing operations ending: elapsed time is 00:00:02" { } { } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1511999675217 ""} +{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Optimizations that may affect the design's routability were skipped" { } { } 0 170201 "Optimizations that may affect the design's routability were skipped" 0 0 "Quartus II" 0 -1 1511999675220 ""} } { } 0 170199 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "Fitter" 0 -1 1511999675220 ""} +{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "0.28 " "Total time spent on timing analysis during the Fitter is 0.28 seconds." { } { } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1511999675229 ""} +{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1511999675232 ""} +{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "40 " "Found 40 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "hit 0 " "Pin \"hit\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1511999675237 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "done 0 " "Pin \"done\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1511999675237 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "player_wins 0 " "Pin \"player_wins\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1511999675237 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "dealer_wins 0 " "Pin \"dealer_wins\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1511999675237 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_display1\[6\] 0 " "Pin \"led_display1\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1511999675237 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_display1\[5\] 0 " "Pin \"led_display1\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1511999675237 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_display1\[4\] 0 " "Pin \"led_display1\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1511999675237 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_display1\[3\] 0 " "Pin \"led_display1\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1511999675237 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_display1\[2\] 0 " "Pin \"led_display1\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1511999675237 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_display1\[1\] 0 " "Pin \"led_display1\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1511999675237 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_display1\[0\] 0 " "Pin \"led_display1\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1511999675237 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_display2\[6\] 0 " "Pin \"led_display2\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1511999675237 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_display2\[5\] 0 " "Pin \"led_display2\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1511999675237 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_display2\[4\] 0 " "Pin \"led_display2\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1511999675237 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_display2\[3\] 0 " "Pin \"led_display2\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1511999675237 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_display2\[2\] 0 " "Pin \"led_display2\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1511999675237 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_display2\[1\] 0 " "Pin \"led_display2\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1511999675237 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_display2\[0\] 0 " "Pin \"led_display2\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1511999675237 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_display3\[6\] 0 " "Pin \"led_display3\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1511999675237 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_display3\[5\] 0 " "Pin \"led_display3\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1511999675237 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_display3\[4\] 0 " "Pin \"led_display3\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1511999675237 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_display3\[3\] 0 " "Pin \"led_display3\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1511999675237 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_display3\[2\] 0 " "Pin \"led_display3\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1511999675237 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_display3\[1\] 0 " "Pin \"led_display3\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1511999675237 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_display3\[0\] 0 " "Pin \"led_display3\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1511999675237 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_display4\[6\] 0 " "Pin \"led_display4\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1511999675237 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_display4\[5\] 0 " "Pin \"led_display4\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1511999675237 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_display4\[4\] 0 " "Pin \"led_display4\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1511999675237 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_display4\[3\] 0 " "Pin \"led_display4\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1511999675237 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_display4\[2\] 0 " "Pin \"led_display4\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1511999675237 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_display4\[1\] 0 " "Pin \"led_display4\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1511999675237 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "led_display4\[0\] 0 " "Pin \"led_display4\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1511999675237 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "state_out\[1\] 0 " "Pin \"state_out\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1511999675237 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "state_out\[0\] 0 " "Pin \"state_out\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1511999675237 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sum_out\[5\] 0 " "Pin \"sum_out\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1511999675237 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sum_out\[4\] 0 " "Pin \"sum_out\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1511999675237 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sum_out\[3\] 0 " "Pin \"sum_out\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1511999675237 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sum_out\[2\] 0 " "Pin \"sum_out\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1511999675237 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sum_out\[1\] 0 " "Pin \"sum_out\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1511999675237 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "sum_out\[0\] 0 " "Pin \"sum_out\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" { } { } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1511999675237 ""} } { } 0 306006 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "Fitter" 0 -1 1511999675237 ""} +{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1511999675373 ""} +{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" { } { } 0 306004 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1511999675391 ""} +{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" { } { } 0 306005 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1511999675503 ""} +{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:00 " "Fitter post-fit operations ending: elapsed time is 00:00:00" { } { } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1511999675838 ""} +{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 169174 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "Fitter" 0 -1 1511999675939 ""} +{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "C:/home/abbas/dsd_A6/lab5/output_files/gA6_lab5.fit.smsg " "Generated suppressed messages file C:/home/abbas/dsd_A6/lab5/output_files/gA6_lab5.fit.smsg" { } { } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1511999676079 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 5 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 5 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "944 " "Peak virtual memory: 944 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1511999676412 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 29 18:54:36 2017 " "Processing ended: Wed Nov 29 18:54:36 2017" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1511999676412 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:08 " "Elapsed time: 00:00:08" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1511999676412 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:09 " "Total CPU time (on all processors): 00:00:09" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1511999676412 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1511999676412 ""} diff --git a/lab5/db/gA6_lab5.hier_info b/lab5/db/gA6_lab5.hier_info new file mode 100644 index 0000000..356abaf --- /dev/null +++ b/lab5/db/gA6_lab5.hier_info @@ -0,0 +1,219 @@ +|gA6_lab5 +hit <= gA6_computer:inst.hit +clk => gA6_computer:inst.clk +clk => gA6_winner:inst1.clk +rst => gA6_computer:inst.rst +turn => gA6_computer:inst.turn +sum[0] => gA6_computer:inst.sum[0] +sum[1] => gA6_computer:inst.sum[1] +sum[2] => gA6_computer:inst.sum[2] +sum[3] => gA6_computer:inst.sum[3] +sum[4] => gA6_computer:inst.sum[4] +sum[5] => gA6_computer:inst.sum[5] +done <= gA6_computer:inst.done +player_wins <= gA6_winner:inst1.player_wins +player_sum[0] => gA6_winner:inst1.player_sum[0] +player_sum[1] => gA6_winner:inst1.player_sum[1] +player_sum[2] => gA6_winner:inst1.player_sum[2] +player_sum[3] => gA6_winner:inst1.player_sum[3] +player_sum[4] => gA6_winner:inst1.player_sum[4] +player_sum[5] => gA6_winner:inst1.player_sum[5] +dealer_wins <= gA6_winner:inst1.dealer_wins +led_display1[0] <= gA6_winner:inst1.led_display1[0] +led_display1[1] <= gA6_winner:inst1.led_display1[1] +led_display1[2] <= gA6_winner:inst1.led_display1[2] +led_display1[3] <= gA6_winner:inst1.led_display1[3] +led_display1[4] <= gA6_winner:inst1.led_display1[4] +led_display1[5] <= gA6_winner:inst1.led_display1[5] +led_display1[6] <= gA6_winner:inst1.led_display1[6] +led_display2[0] <= gA6_winner:inst1.led_display2[0] +led_display2[1] <= gA6_winner:inst1.led_display2[1] +led_display2[2] <= gA6_winner:inst1.led_display2[2] +led_display2[3] <= gA6_winner:inst1.led_display2[3] +led_display2[4] <= gA6_winner:inst1.led_display2[4] +led_display2[5] <= gA6_winner:inst1.led_display2[5] +led_display2[6] <= gA6_winner:inst1.led_display2[6] +led_display3[0] <= gA6_winner:inst1.led_display3[0] +led_display3[1] <= gA6_winner:inst1.led_display3[1] +led_display3[2] <= gA6_winner:inst1.led_display3[2] +led_display3[3] <= gA6_winner:inst1.led_display3[3] +led_display3[4] <= gA6_winner:inst1.led_display3[4] +led_display3[5] <= gA6_winner:inst1.led_display3[5] +led_display3[6] <= gA6_winner:inst1.led_display3[6] +led_display4[0] <= gA6_winner:inst1.led_display4[0] +led_display4[1] <= gA6_winner:inst1.led_display4[1] +led_display4[2] <= gA6_winner:inst1.led_display4[2] +led_display4[3] <= gA6_winner:inst1.led_display4[3] +led_display4[4] <= gA6_winner:inst1.led_display4[4] +led_display4[5] <= gA6_winner:inst1.led_display4[5] +led_display4[6] <= gA6_winner:inst1.led_display4[6] +state_out[0] <= gA6_computer:inst.state_out[0] +state_out[1] <= gA6_computer:inst.state_out[1] +sum_out[0] <= gA6_computer:inst.sum_out[0] +sum_out[1] <= gA6_computer:inst.sum_out[1] +sum_out[2] <= gA6_computer:inst.sum_out[2] +sum_out[3] <= gA6_computer:inst.sum_out[3] +sum_out[4] <= gA6_computer:inst.sum_out[4] +sum_out[5] <= gA6_computer:inst.sum_out[5] + + +|gA6_lab5|gA6_computer:inst +clk => sum_out[0]~reg0.CLK +clk => sum_out[1]~reg0.CLK +clk => sum_out[2]~reg0.CLK +clk => sum_out[3]~reg0.CLK +clk => sum_out[4]~reg0.CLK +clk => sum_out[5]~reg0.CLK +clk => done~reg0.CLK +clk => hit~reg0.CLK +clk => \computer:state[0].CLK +clk => \computer:state[1].CLK +rst => sum_out[0]~reg0.ACLR +rst => sum_out[1]~reg0.ACLR +rst => sum_out[2]~reg0.ACLR +rst => sum_out[3]~reg0.ACLR +rst => sum_out[4]~reg0.ACLR +rst => sum_out[5]~reg0.ACLR +rst => done~reg0.ACLR +rst => hit~reg0.ACLR +rst => \computer:state[0].ACLR +rst => \computer:state[1].ACLR +turn => state.OUTPUTSELECT +turn => state.OUTPUTSELECT +sum[0] => LessThan0.IN12 +sum[0] => sum_out[0]~reg0.DATAIN +sum[1] => LessThan0.IN11 +sum[1] => sum_out[1]~reg0.DATAIN +sum[2] => LessThan0.IN10 +sum[2] => sum_out[2]~reg0.DATAIN +sum[3] => LessThan0.IN9 +sum[3] => sum_out[3]~reg0.DATAIN +sum[4] => LessThan0.IN8 +sum[4] => sum_out[4]~reg0.DATAIN +sum[5] => LessThan0.IN7 +sum[5] => sum_out[5]~reg0.DATAIN +hit <= hit~reg0.DB_MAX_OUTPUT_PORT_TYPE +done <= done~reg0.DB_MAX_OUTPUT_PORT_TYPE +sum_out[0] <= sum_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sum_out[1] <= sum_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sum_out[2] <= sum_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sum_out[3] <= sum_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sum_out[4] <= sum_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +sum_out[5] <= sum_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +state_out[0] <= \computer:state[0].DB_MAX_OUTPUT_PORT_TYPE +state_out[1] <= \computer:state[1].DB_MAX_OUTPUT_PORT_TYPE + + +|gA6_lab5|gA6_winner:inst1 +clk => led_display4[0]~reg0.CLK +clk => led_display4[1]~reg0.CLK +clk => led_display4[2]~reg0.CLK +clk => led_display4[3]~reg0.CLK +clk => led_display4[4]~reg0.CLK +clk => led_display4[5]~reg0.CLK +clk => led_display4[6]~reg0.CLK +clk => led_display3[0]~reg0.CLK +clk => led_display3[1]~reg0.CLK +clk => led_display3[2]~reg0.CLK +clk => led_display3[3]~reg0.CLK +clk => led_display3[4]~reg0.CLK +clk => led_display3[5]~reg0.CLK +clk => led_display3[6]~reg0.CLK +clk => led_display2[0]~reg0.CLK +clk => led_display2[1]~reg0.CLK +clk => led_display2[2]~reg0.CLK +clk => led_display2[3]~reg0.CLK +clk => led_display2[4]~reg0.CLK +clk => led_display2[5]~reg0.CLK +clk => led_display2[6]~reg0.CLK +clk => led_display1[0]~reg0.CLK +clk => led_display1[1]~reg0.CLK +clk => led_display1[2]~reg0.CLK +clk => led_display1[3]~reg0.CLK +clk => led_display1[4]~reg0.CLK +clk => led_display1[5]~reg0.CLK +clk => led_display1[6]~reg0.CLK +clk => dealer_wins~reg0.CLK +clk => player_wins~reg0.CLK +clk => \dealer:d_win.CLK +clk => \dealer:p_win.CLK +player_sum[0] => LessThan0.IN12 +player_sum[0] => LessThan2.IN6 +player_sum[0] => LessThan3.IN6 +player_sum[0] => Equal0.IN5 +player_sum[1] => LessThan0.IN11 +player_sum[1] => LessThan2.IN5 +player_sum[1] => LessThan3.IN5 +player_sum[1] => Equal0.IN4 +player_sum[2] => LessThan0.IN10 +player_sum[2] => LessThan2.IN4 +player_sum[2] => LessThan3.IN4 +player_sum[2] => Equal0.IN3 +player_sum[3] => LessThan0.IN9 +player_sum[3] => LessThan2.IN3 +player_sum[3] => LessThan3.IN3 +player_sum[3] => Equal0.IN2 +player_sum[4] => LessThan0.IN8 +player_sum[4] => LessThan2.IN2 +player_sum[4] => LessThan3.IN2 +player_sum[4] => Equal0.IN1 +player_sum[5] => LessThan0.IN7 +player_sum[5] => LessThan2.IN1 +player_sum[5] => LessThan3.IN1 +player_sum[5] => Equal0.IN0 +dealer_sum[0] => LessThan1.IN12 +dealer_sum[0] => LessThan2.IN12 +dealer_sum[0] => LessThan3.IN12 +dealer_sum[0] => Equal0.IN11 +dealer_sum[1] => LessThan1.IN11 +dealer_sum[1] => LessThan2.IN11 +dealer_sum[1] => LessThan3.IN11 +dealer_sum[1] => Equal0.IN10 +dealer_sum[2] => LessThan1.IN10 +dealer_sum[2] => LessThan2.IN10 +dealer_sum[2] => LessThan3.IN10 +dealer_sum[2] => Equal0.IN9 +dealer_sum[3] => LessThan1.IN9 +dealer_sum[3] => LessThan2.IN9 +dealer_sum[3] => LessThan3.IN9 +dealer_sum[3] => Equal0.IN8 +dealer_sum[4] => LessThan1.IN8 +dealer_sum[4] => LessThan2.IN8 +dealer_sum[4] => LessThan3.IN8 +dealer_sum[4] => Equal0.IN7 +dealer_sum[5] => LessThan1.IN7 +dealer_sum[5] => LessThan2.IN7 +dealer_sum[5] => LessThan3.IN7 +dealer_sum[5] => Equal0.IN6 +player_wins <= player_wins~reg0.DB_MAX_OUTPUT_PORT_TYPE +dealer_wins <= dealer_wins~reg0.DB_MAX_OUTPUT_PORT_TYPE +led_display1[0] <= led_display1[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +led_display1[1] <= led_display1[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +led_display1[2] <= led_display1[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +led_display1[3] <= led_display1[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +led_display1[4] <= led_display1[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +led_display1[5] <= led_display1[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +led_display1[6] <= led_display1[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +led_display2[0] <= led_display2[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +led_display2[1] <= led_display2[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +led_display2[2] <= led_display2[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +led_display2[3] <= led_display2[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +led_display2[4] <= led_display2[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +led_display2[5] <= led_display2[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +led_display2[6] <= led_display2[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +led_display3[0] <= led_display3[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +led_display3[1] <= led_display3[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +led_display3[2] <= led_display3[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +led_display3[3] <= led_display3[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +led_display3[4] <= led_display3[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +led_display3[5] <= led_display3[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +led_display3[6] <= led_display3[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE +led_display4[0] <= led_display4[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE +led_display4[1] <= led_display4[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE +led_display4[2] <= led_display4[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE +led_display4[3] <= led_display4[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE +led_display4[4] <= led_display4[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE +led_display4[5] <= led_display4[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE +led_display4[6] <= led_display4[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE + + diff --git a/lab5/db/gA6_lab5.hif b/lab5/db/gA6_lab5.hif new file mode 100644 index 0000000..e6220c3 Binary files /dev/null and b/lab5/db/gA6_lab5.hif differ diff --git a/lab5/db/gA6_lab5.ipinfo b/lab5/db/gA6_lab5.ipinfo new file mode 100644 index 0000000..a02bb8b Binary files /dev/null and b/lab5/db/gA6_lab5.ipinfo differ diff --git a/lab5/db/gA6_lab5.lpc.html b/lab5/db/gA6_lab5.lpc.html new file mode 100644 index 0000000..0dac55b --- /dev/null +++ b/lab5/db/gA6_lab5.lpc.html @@ -0,0 +1,50 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
HierarchyInputConstant InputUnused InputFloating InputOutputConstant OutputUnused OutputFloating OutputBidirConstant BidirUnused BidirInput only BidirOutput only Bidir
inst1130003000000000
inst90001000000000
diff --git a/lab5/db/gA6_lab5.lpc.rdb b/lab5/db/gA6_lab5.lpc.rdb new file mode 100644 index 0000000..fbd6bab Binary files /dev/null and b/lab5/db/gA6_lab5.lpc.rdb differ diff --git a/lab5/db/gA6_lab5.lpc.txt b/lab5/db/gA6_lab5.lpc.txt new file mode 100644 index 0000000..4e9896f --- /dev/null +++ b/lab5/db/gA6_lab5.lpc.txt @@ -0,0 +1,8 @@ ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Legal Partition Candidates ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ +; inst1 ; 13 ; 0 ; 0 ; 0 ; 30 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; +; inst ; 9 ; 0 ; 0 ; 0 ; 10 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; ++-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+ diff --git a/lab5/db/gA6_lab5.map.ammdb b/lab5/db/gA6_lab5.map.ammdb new file mode 100644 index 0000000..7bf1c54 Binary files /dev/null and b/lab5/db/gA6_lab5.map.ammdb differ diff --git a/lab5/db/gA6_lab5.map.bpm b/lab5/db/gA6_lab5.map.bpm new file mode 100644 index 0000000..4875889 Binary files /dev/null and b/lab5/db/gA6_lab5.map.bpm differ diff --git a/lab5/db/gA6_lab5.map.cdb b/lab5/db/gA6_lab5.map.cdb new file mode 100644 index 0000000..661b06e Binary files /dev/null and b/lab5/db/gA6_lab5.map.cdb differ diff --git a/lab5/db/gA6_lab5.map.hdb b/lab5/db/gA6_lab5.map.hdb new file mode 100644 index 0000000..8748fd4 Binary files /dev/null and b/lab5/db/gA6_lab5.map.hdb differ diff --git a/lab5/db/gA6_lab5.map.kpt b/lab5/db/gA6_lab5.map.kpt new file mode 100644 index 0000000..b5b4e0a Binary files /dev/null and b/lab5/db/gA6_lab5.map.kpt differ diff --git a/lab5/db/gA6_lab5.map.logdb b/lab5/db/gA6_lab5.map.logdb new file mode 100644 index 0000000..d45424f --- /dev/null +++ b/lab5/db/gA6_lab5.map.logdb @@ -0,0 +1 @@ +v1 diff --git a/lab5/db/gA6_lab5.map.qmsg b/lab5/db/gA6_lab5.map.qmsg new file mode 100644 index 0000000..afb94c9 --- /dev/null +++ b/lab5/db/gA6_lab5.map.qmsg @@ -0,0 +1,14 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1511999664549 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II 64-Bit " "Running Quartus II 64-Bit Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Web Edition " "Version 13.0.0 Build 156 04/24/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1511999664550 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 29 18:54:24 2017 " "Processing started: Wed Nov 29 18:54:24 2017" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1511999664550 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1511999664550 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off gA6_lab5 -c gA6_lab5 " "Command: quartus_map --read_settings_files=on --write_settings_files=off gA6_lab5 -c gA6_lab5" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1511999664550 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "2 2 4 " "Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead." { } { } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1511999665216 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ga6_winner.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ga6_winner.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 gA6_winner-behavior " "Found design unit 1: gA6_winner-behavior" { } { { "gA6_winner.vhd" "" { Text "C:/home/abbas/dsd_A6/lab5/gA6_winner.vhd" 28 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1511999666026 ""} { "Info" "ISGN_ENTITY_NAME" "1 gA6_winner " "Found entity 1: gA6_winner" { } { { "gA6_winner.vhd" "" { Text "C:/home/abbas/dsd_A6/lab5/gA6_winner.vhd" 13 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1511999666026 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1511999666026 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ga6_computer.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ga6_computer.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 gA6_computer-behavior " "Found design unit 1: gA6_computer-behavior" { } { { "gA6_computer.vhd" "" { Text "C:/home/abbas/dsd_A6/lab5/gA6_computer.vhd" 27 -1 0 } } } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1511999666032 ""} { "Info" "ISGN_ENTITY_NAME" "1 gA6_computer " "Found entity 1: gA6_computer" { } { { "gA6_computer.vhd" "" { Text "C:/home/abbas/dsd_A6/lab5/gA6_computer.vhd" 13 -1 0 } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1511999666032 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1511999666032 ""} +{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ga6_lab5.bdf 1 1 " "Found 1 design units, including 1 entities, in source file ga6_lab5.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 gA6_lab5 " "Found entity 1: gA6_lab5" { } { { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { } } } } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Quartus II" 0 -1 1511999666036 ""} } { } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Quartus II" 0 -1 1511999666036 ""} +{ "Info" "ISGN_START_ELABORATION_TOP" "gA6_lab5 " "Elaborating entity \"gA6_lab5\" for the top level hierarchy" { } { } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Quartus II" 0 -1 1511999666094 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "gA6_computer gA6_computer:inst " "Elaborating entity \"gA6_computer\" for hierarchy \"gA6_computer:inst\"" { } { { "gA6_lab5.bdf" "inst" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 136 184 376 248 "inst" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1511999666099 ""} +{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "gA6_winner gA6_winner:inst1 " "Elaborating entity \"gA6_winner\" for hierarchy \"gA6_winner:inst1\"" { } { { "gA6_lab5.bdf" "inst1" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 272 160 400 416 "inst1" "" } } } } } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Quartus II" 0 -1 1511999666138 ""} +{ "Warning" "WMLS_MLS_STUCK_PIN_HDR" "" "Output pins are stuck at VCC or GND" { { "Warning" "WMLS_MLS_STUCK_PIN" "led_display1\[5\] GND " "Pin \"led_display1\[5\]\" is stuck at GND" { } { { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 328 408 591 344 "led_display1\[6..0\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1511999666770 "|gA6_lab5|led_display1[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "led_display1\[4\] GND " "Pin \"led_display1\[4\]\" is stuck at GND" { } { { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 328 408 591 344 "led_display1\[6..0\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1511999666770 "|gA6_lab5|led_display1[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "led_display2\[6\] VCC " "Pin \"led_display2\[6\]\" is stuck at VCC" { } { { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 344 408 591 360 "led_display2\[6..0\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1511999666770 "|gA6_lab5|led_display2[6]"} { "Warning" "WMLS_MLS_STUCK_PIN" "led_display2\[4\] GND " "Pin \"led_display2\[4\]\" is stuck at GND" { } { { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 344 408 591 360 "led_display2\[6..0\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1511999666770 "|gA6_lab5|led_display2[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "led_display2\[3\] GND " "Pin \"led_display2\[3\]\" is stuck at GND" { } { { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 344 408 591 360 "led_display2\[6..0\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1511999666770 "|gA6_lab5|led_display2[3]"} { "Warning" "WMLS_MLS_STUCK_PIN" "led_display2\[2\] GND " "Pin \"led_display2\[2\]\" is stuck at GND" { } { { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 344 408 591 360 "led_display2\[6..0\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1511999666770 "|gA6_lab5|led_display2[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "led_display2\[1\] GND " "Pin \"led_display2\[1\]\" is stuck at GND" { } { { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 344 408 591 360 "led_display2\[6..0\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1511999666770 "|gA6_lab5|led_display2[1]"} { "Warning" "WMLS_MLS_STUCK_PIN" "led_display3\[4\] VCC " "Pin \"led_display3\[4\]\" is stuck at VCC" { } { { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 360 408 591 376 "led_display3\[6..0\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1511999666770 "|gA6_lab5|led_display3[4]"} { "Warning" "WMLS_MLS_STUCK_PIN" "led_display3\[2\] GND " "Pin \"led_display3\[2\]\" is stuck at GND" { } { { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 360 408 591 376 "led_display3\[6..0\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1511999666770 "|gA6_lab5|led_display3[2]"} { "Warning" "WMLS_MLS_STUCK_PIN" "led_display4\[5\] GND " "Pin \"led_display4\[5\]\" is stuck at GND" { } { { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 376 408 591 392 "led_display4\[6..0\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1511999666770 "|gA6_lab5|led_display4[5]"} { "Warning" "WMLS_MLS_STUCK_PIN" "led_display4\[4\] GND " "Pin \"led_display4\[4\]\" is stuck at GND" { } { { "gA6_lab5.bdf" "" { Schematic "C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf" { { 376 408 591 392 "led_display4\[6..0\]" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "Quartus II" 0 -1 1511999666770 "|gA6_lab5|led_display4[4]"} } { } 0 13024 "Output pins are stuck at VCC or GND" 0 0 "Quartus II" 0 -1 1511999666770 ""} +{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "0 0 0 0 0 " "Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL" { } { } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Quartus II" 0 -1 1511999667196 ""} } { } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Quartus II" 0 -1 1511999667196 ""} +{ "Info" "ICUT_CUT_TM_SUMMARY" "102 " "Implemented 102 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "15 " "Implemented 15 input pins" { } { } 0 21058 "Implemented %1!d! input pins" 0 0 "Quartus II" 0 -1 1511999667301 ""} { "Info" "ICUT_CUT_TM_OPINS" "40 " "Implemented 40 output pins" { } { } 0 21059 "Implemented %1!d! output pins" 0 0 "Quartus II" 0 -1 1511999667301 ""} { "Info" "ICUT_CUT_TM_LCELLS" "47 " "Implemented 47 logic cells" { } { } 0 21061 "Implemented %1!d! logic cells" 0 0 "Quartus II" 0 -1 1511999667301 ""} } { } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Quartus II" 0 -1 1511999667301 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus II 64-Bit " "Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "582 " "Peak virtual memory: 582 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1511999667381 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 29 18:54:27 2017 " "Processing ended: Wed Nov 29 18:54:27 2017" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1511999667381 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1511999667381 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Total CPU time (on all processors): 00:00:03" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1511999667381 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1511999667381 ""} diff --git a/lab5/db/gA6_lab5.map.rdb b/lab5/db/gA6_lab5.map.rdb new file mode 100644 index 0000000..ca975c4 Binary files /dev/null and b/lab5/db/gA6_lab5.map.rdb differ diff --git a/lab5/db/gA6_lab5.map_bb.cdb b/lab5/db/gA6_lab5.map_bb.cdb new file mode 100644 index 0000000..f027702 Binary files /dev/null and b/lab5/db/gA6_lab5.map_bb.cdb differ diff --git a/lab5/db/gA6_lab5.map_bb.hdb b/lab5/db/gA6_lab5.map_bb.hdb new file mode 100644 index 0000000..58ce8b8 Binary files /dev/null and b/lab5/db/gA6_lab5.map_bb.hdb differ diff --git a/lab5/db/gA6_lab5.map_bb.logdb b/lab5/db/gA6_lab5.map_bb.logdb new file mode 100644 index 0000000..d45424f --- /dev/null +++ b/lab5/db/gA6_lab5.map_bb.logdb @@ -0,0 +1 @@ +v1 diff --git a/lab5/db/gA6_lab5.pre_map.hdb b/lab5/db/gA6_lab5.pre_map.hdb new file mode 100644 index 0000000..a32a008 Binary files /dev/null and b/lab5/db/gA6_lab5.pre_map.hdb differ diff --git a/lab5/db/gA6_lab5.pti_db_list.ddb b/lab5/db/gA6_lab5.pti_db_list.ddb new file mode 100644 index 0000000..a28fa07 Binary files /dev/null and b/lab5/db/gA6_lab5.pti_db_list.ddb differ diff --git a/lab5/db/gA6_lab5.root_partition.map.reg_db.cdb b/lab5/db/gA6_lab5.root_partition.map.reg_db.cdb new file mode 100644 index 0000000..21ee8ed Binary files /dev/null and b/lab5/db/gA6_lab5.root_partition.map.reg_db.cdb differ diff --git a/lab5/db/gA6_lab5.routing.rdb b/lab5/db/gA6_lab5.routing.rdb new file mode 100644 index 0000000..a48aa60 Binary files /dev/null and b/lab5/db/gA6_lab5.routing.rdb differ diff --git a/lab5/db/gA6_lab5.rtlv.hdb b/lab5/db/gA6_lab5.rtlv.hdb new file mode 100644 index 0000000..a934a48 Binary files /dev/null and b/lab5/db/gA6_lab5.rtlv.hdb differ diff --git a/lab5/db/gA6_lab5.rtlv_sg.cdb b/lab5/db/gA6_lab5.rtlv_sg.cdb new file mode 100644 index 0000000..3a45a55 Binary files /dev/null and b/lab5/db/gA6_lab5.rtlv_sg.cdb differ diff --git a/lab5/db/gA6_lab5.rtlv_sg_swap.cdb b/lab5/db/gA6_lab5.rtlv_sg_swap.cdb new file mode 100644 index 0000000..9d9081d Binary files /dev/null and b/lab5/db/gA6_lab5.rtlv_sg_swap.cdb differ diff --git a/lab5/db/gA6_lab5.sgdiff.cdb b/lab5/db/gA6_lab5.sgdiff.cdb new file mode 100644 index 0000000..8e2e0df Binary files /dev/null and b/lab5/db/gA6_lab5.sgdiff.cdb differ diff --git a/lab5/db/gA6_lab5.sgdiff.hdb b/lab5/db/gA6_lab5.sgdiff.hdb new file mode 100644 index 0000000..af82ec7 Binary files /dev/null and b/lab5/db/gA6_lab5.sgdiff.hdb differ diff --git a/lab5/db/gA6_lab5.sld_design_entry.sci b/lab5/db/gA6_lab5.sld_design_entry.sci new file mode 100644 index 0000000..2b1eb96 Binary files /dev/null and b/lab5/db/gA6_lab5.sld_design_entry.sci differ diff --git a/lab5/db/gA6_lab5.sld_design_entry_dsc.sci b/lab5/db/gA6_lab5.sld_design_entry_dsc.sci new file mode 100644 index 0000000..2b1eb96 Binary files /dev/null and b/lab5/db/gA6_lab5.sld_design_entry_dsc.sci differ diff --git a/lab5/db/gA6_lab5.smart_action.txt b/lab5/db/gA6_lab5.smart_action.txt new file mode 100644 index 0000000..f1e1649 --- /dev/null +++ b/lab5/db/gA6_lab5.smart_action.txt @@ -0,0 +1 @@ +SOURCE diff --git a/lab5/db/gA6_lab5.sta.qmsg b/lab5/db/gA6_lab5.sta.qmsg new file mode 100644 index 0000000..18311cc --- /dev/null +++ b/lab5/db/gA6_lab5.sta.qmsg @@ -0,0 +1,30 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1511999681531 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II 64-Bit " "Running Quartus II 64-Bit TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Web Edition " "Version 13.0.0 Build 156 04/24/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1511999681532 ""} { "Info" "IQEXE_START_BANNER_TIME" "Wed Nov 29 18:54:40 2017 " "Processing started: Wed Nov 29 18:54:40 2017" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1511999681532 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1511999681532 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta gA6_lab5 -c gA6_lab5 " "Command: quartus_sta gA6_lab5 -c gA6_lab5" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1511999681532 ""} +{ "Info" "0" "" "qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "Quartus II" 0 0 1511999681692 ""} +{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS_MORE_LOGICAL" "2 2 4 " "Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead." { } { } 0 11104 "Parallel Compilation has detected %3!i! hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use %1!i! of the %2!i! physical processors detected instead." 0 0 "Quartus II" 0 -1 1511999681948 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "Low junction temperature 0 degrees C " "Low junction temperature is 0 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1511999681998 ""} +{ "Info" "ICUT_CUT_USING_OPERATING_CONDITION" "High junction temperature 85 degrees C " "High junction temperature is 85 degrees C" { } { } 0 21077 "%1!s! is %2!s!" 0 0 "Quartus II" 0 -1 1511999681998 ""} +{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "gA6_lab5.sdc " "Synopsys Design Constraints File file not found: 'gA6_lab5.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." { } { } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Quartus II" 0 -1 1511999682173 ""} +{ "Info" "ISTA_NO_CLOCK_FOUND_DERIVING" "base clocks \"derive_clocks -period 1.0\" " "No user constrained base clocks found in the design. Calling \"derive_clocks -period 1.0\"" { } { } 0 332142 "No user constrained %1!s! found in the design. Calling %2!s!" 0 0 "Quartus II" 0 -1 1511999682174 ""} +{ "Info" "ISTA_DERIVE_CLOCKS_INFO" "Deriving Clocks " "Deriving Clocks" { { "Info" "ISTA_DERIVE_CLOCKS_INFO" "create_clock -period 1.000 -name clk clk " "create_clock -period 1.000 -name clk clk" { } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1511999682175 ""} } { } 0 332105 "%1!s!" 0 0 "Quartus II" 0 -1 1511999682175 ""} +{ "Info" "0" "" "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" { } { } 0 0 "Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON" 0 0 "Quartus II" 0 0 1511999682177 ""} +{ "Info" "0" "" "Analyzing Slow Model" { } { } 0 0 "Analyzing Slow Model" 0 0 "Quartus II" 0 0 1511999682192 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1511999682207 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -4.118 " "Worst-case setup slack is -4.118" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1511999682218 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1511999682218 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -4.118 -25.738 clk " " -4.118 -25.738 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1511999682218 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1511999682218 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.445 " "Worst-case hold slack is 0.445" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1511999682229 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1511999682229 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.445 0.000 clk " " 0.445 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1511999682229 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1511999682229 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1511999682240 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1511999682252 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.631 " "Worst-case minimum pulse width slack is -1.631" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1511999682263 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1511999682263 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.631 -22.405 clk " " -1.631 -22.405 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1511999682263 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1511999682263 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1511999682342 ""} +{ "Info" "0" "" "Analyzing Fast Model" { } { } 0 0 "Analyzing Fast Model" 0 0 "Quartus II" 0 0 1511999682344 ""} +{ "Critical Warning" "WSTA_TIMING_NOT_MET" "" "Timing requirements not met" { } { } 1 332148 "Timing requirements not met" 0 0 "Quartus II" 0 -1 1511999682361 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "setup -1.010 " "Worst-case setup slack is -1.010" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1511999682374 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1511999682374 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.010 -5.377 clk " " -1.010 -5.377 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1511999682374 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1511999682374 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "hold 0.215 " "Worst-case hold slack is 0.215" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1511999682441 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1511999682441 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " 0.215 0.000 clk " " 0.215 0.000 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1511999682441 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1511999682441 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Recovery " "No Recovery paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1511999682455 ""} +{ "Info" "ISTA_NO_PATHS_TO_REPORT" "Removal " "No Removal paths to report" { } { } 0 332140 "No %1!s! paths to report" 0 0 "Quartus II" 0 -1 1511999682468 ""} +{ "Info" "ISTA_WORST_CASE_SLACK" "minimum pulse width -1.380 " "Worst-case minimum pulse width slack is -1.380" { { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " Slack End Point TNS Clock " " Slack End Point TNS Clock " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1511999682481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" "========= ============= ===================== " "========= ============= =====================" { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1511999682481 ""} { "Info" "ISTA_CREATE_TIMING_SUMMARY_INFO" " -1.380 -18.380 clk " " -1.380 -18.380 clk " { } { } 0 332119 "%1!s!" 0 0 "Quartus II" 0 -1 1511999682481 ""} } { } 0 332146 "Worst-case %1!s! slack is %2!s!" 0 0 "Quartus II" 0 -1 1511999682481 ""} +{ "Info" "ISTA_METASTABILITY_REPORT_DISABLED" "" "The selected device family is not supported by the report_metastability command." { } { } 0 332001 "The selected device family is not supported by the report_metastability command." 0 0 "Quartus II" 0 -1 1511999682556 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "setup " "Design is not fully constrained for setup requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1511999683096 ""} +{ "Info" "ISTA_UCP_NOT_CONSTRAINED" "hold " "Design is not fully constrained for hold requirements" { } { } 0 332102 "Design is not fully constrained for %1!s! requirements" 0 0 "Quartus II" 0 -1 1511999683097 ""} +{ "Info" "IQEXE_ERROR_COUNT" "TimeQuest Timing Analyzer 0 s 3 s Quartus II 64-Bit " "Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "530 " "Peak virtual memory: 530 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1511999683273 ""} { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 29 18:54:43 2017 " "Processing ended: Wed Nov 29 18:54:43 2017" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1511999683273 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1511999683273 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1511999683273 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1511999683273 ""} diff --git a/lab5/db/gA6_lab5.sta.rdb b/lab5/db/gA6_lab5.sta.rdb new file mode 100644 index 0000000..cd23372 Binary files /dev/null and b/lab5/db/gA6_lab5.sta.rdb differ diff --git a/lab5/db/gA6_lab5.sta_cmp.7_slow.tdb b/lab5/db/gA6_lab5.sta_cmp.7_slow.tdb new file mode 100644 index 0000000..4812002 Binary files /dev/null and b/lab5/db/gA6_lab5.sta_cmp.7_slow.tdb differ diff --git a/lab5/db/gA6_lab5.syn_hier_info b/lab5/db/gA6_lab5.syn_hier_info new file mode 100644 index 0000000..e69de29 diff --git a/lab5/db/gA6_lab5.tis_db_list.ddb b/lab5/db/gA6_lab5.tis_db_list.ddb new file mode 100644 index 0000000..88b4d6d Binary files /dev/null and b/lab5/db/gA6_lab5.tis_db_list.ddb differ diff --git a/lab5/db/gA6_lab5.vpr.ammdb b/lab5/db/gA6_lab5.vpr.ammdb new file mode 100644 index 0000000..dea23a6 Binary files /dev/null and b/lab5/db/gA6_lab5.vpr.ammdb differ diff --git a/lab5/db/logic_util_heursitic.dat b/lab5/db/logic_util_heursitic.dat new file mode 100644 index 0000000..1df7706 Binary files /dev/null and b/lab5/db/logic_util_heursitic.dat differ diff --git a/lab5/db/prev_cmp_gA6_lab5.qmsg b/lab5/db/prev_cmp_gA6_lab5.qmsg new file mode 100644 index 0000000..9b85389 --- /dev/null +++ b/lab5/db/prev_cmp_gA6_lab5.qmsg @@ -0,0 +1,4 @@ +{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "Quartus II" 0 -1 1512068106518 ""} +{ "Info" "IQEXE_START_BANNER_PRODUCT" "Create Symbol File Quartus II 64-Bit " "Running Quartus II 64-Bit Create Symbol File" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 13.0.0 Build 156 04/24/2013 SJ Web Edition " "Version 13.0.0 Build 156 04/24/2013 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "Quartus II" 0 -1 1512068106518 ""} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 30 13:55:06 2017 " "Processing started: Thu Nov 30 13:55:06 2017" { } { } 0 0 "Processing started: %1!s!" 0 0 "Quartus II" 0 -1 1512068106518 ""} } { } 4 0 "Running %2!s! %1!s!" 0 0 "Quartus II" 0 -1 1512068106518 ""} +{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off gA6_lab5 -c gA6_lab5 --generate_symbol=C:\\home\\abbas\\dsd_A6\\lab5\\gA6_datapath.vhd " "Command: quartus_map --read_settings_files=on --write_settings_files=off gA6_lab5 -c gA6_lab5 --generate_symbol=C:\\home\\abbas\\dsd_A6\\lab5\\gA6_datapath.vhd" { } { } 0 0 "Command: %1!s!" 0 0 "Quartus II" 0 -1 1512068106518 ""} +{ "Info" "IQEXE_ERROR_COUNT" "Create Symbol File 0 s 0 s Quartus II 64-Bit " "Quartus II 64-Bit Create Symbol File was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "529 " "Peak virtual memory: 529 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1512068107429 ""} { "Info" "IQEXE_END_BANNER_TIME" "Thu Nov 30 13:55:07 2017 " "Processing ended: Thu Nov 30 13:55:07 2017" { } { } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1512068107429 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1512068107429 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1512068107429 ""} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Quartus II" 0 -1 1512068107429 ""} diff --git a/lab5/gA6_7_segment_decoder.bsf b/lab5/gA6_7_segment_decoder.bsf new file mode 100644 index 0000000..3e0ed3f --- /dev/null +++ b/lab5/gA6_7_segment_decoder.bsf @@ -0,0 +1,50 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 232 96) + (text "gA6_7_segment_decoder" (rect 5 0 111 12)(font "Arial" )) + (text "inst" (rect 8 64 20 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "code[3..0]" (rect 0 0 38 12)(font "Arial" )) + (text "code[3..0]" (rect 21 27 59 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "mode" (rect 0 0 22 12)(font "Arial" )) + (text "mode" (rect 21 43 43 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 216 32) + (output) + (text "segments_out[6..0]" (rect 0 0 76 12)(font "Arial" )) + (text "segments_out[6..0]" (rect 119 27 195 39)(font "Arial" )) + (line (pt 216 32)(pt 200 32)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 200 64)(line_width 1)) + ) +) diff --git a/lab5/gA6_7_segment_decoder.vhd b/lab5/gA6_7_segment_decoder.vhd new file mode 100644 index 0000000..83bf95a --- /dev/null +++ b/lab5/gA6_7_segment_decoder.vhd @@ -0,0 +1,64 @@ +-- entity name: gA6_7_segment_decoder +-- +-- Copyright (C) 2017 Abbas Yadollahi - He Qian Wang +-- Version 1.0 +-- Author: Abbas Yadollahi (abbas.yadollahi@mail.mcgill.ca) +-- He Qian Wang (he.q.wang@mail.mcgill.ca) +-- Date: Oct/18/2017 + +library ieee; -- Allows use of the std_logic_vector type +use ieee.std_logic_1164.all; + +entity gA6_7_segment_decoder is + port( + code : in std_logic_vector(3 downto 0); + mode : in std_logic; + segments_out : out std_logic_vector(6 downto 0) + ); +end gA6_7_segment_decoder; + +architecture behavior of gA6_7_segment_decoder is + signal xcode : std_logic_vector(4 downto 0); + + begin + + xcode(4 downto 1) <= code; + xcode(0) <= mode; + + with xcode select + + segments_out <= + "1000000" when "00000", --code=0, mode=0 x + "0001000" when "00001", --code=0, mode=1 x + "1111001" when "00010", --code=1, mode=0 x + "0100100" when "00011", --code=1, mode=1 x + "0100100" when "00100", --code=2, mode=0 x + "0110000" when "00101", --code=2, mode=1 x + "0110000" when "00110", --code=3, mode=0 x + "0011001" when "00111", --code=3, mode=1 x + "0011001" when "01000", --code=4, mode=0 x + "0010010" when "01001", --code=4, mode=1 x + "0010010" when "01010", --code=5, mode=0 x + "0000010" when "01011", --code=5, mode=1 x + "0000010" when "01100", --code=6, mode=0 x + "1111000" when "01101", --code=6, mode=1 x + "1111000" when "01110", --code=7, mode=0 x + "0000000" when "01111", --code=7, mode=1 x + "0000000" when "10000", --code=8, mode=0 x + "0010000" when "10001", --code=8, mode=1 x + "0010000" when "10010", --code=9, mode=0 x + "1000000" when "10011", --code=9, mode=1 x + "0001000" when "10100", --code=10, mode=0 x + "1100001" when "10101", --code=10, mode=1 x + "0000011" when "10110", --code=11, mode=0 x + "0100011" when "10111", --code=11, mode=1 x + "1000110" when "11000", --code=12, mode=0 x + "0001001" when "11001", --code=12, mode=1 x + "0100001" when "11010", --code=13, mode=0 x + "0111111" when "11011", --code=13, mode=1 x + "0000110" when "11100", --code=14, mode=0 x + "0111111" when "11101", --code=14, mode=1 x + "0001110" when "11110", --code=15, mode=0 x + "0111111" when "11111"; --code=15, mode=1 x + +end behavior; \ No newline at end of file diff --git a/lab5/gA6_7_segment_decoder.vhd.bak b/lab5/gA6_7_segment_decoder.vhd.bak new file mode 100644 index 0000000..0573068 --- /dev/null +++ b/lab5/gA6_7_segment_decoder.vhd.bak @@ -0,0 +1,64 @@ +-- entity name: gA6_7_segment_decoder +-- +-- Copyright (C) 2017 Abbas Yadollahi - He Qian Wang +-- Version 1.0 +-- Author: Abbas Yadollahi (abbas.yadollahi@mail.mcgill.ca) +-- He Qian Wang (he.q.wang@mail.mcgill.ca) +-- Date: Oct/18/2017 + +library ieee; -- Allows use of the std_logic_vector type +use ieee.std_logic_1164.all; + +entity gA6_7_segment_decoder is + port( + code : in std_logic_vector(3 downto 0); + mode : in std_logic; + segments_out : out std_logic_vector(6 downto 0) + ); +end gA6_7_segment_decoder; + +architecture behavior of gA6_7_segment_decoder is + signal xcode : std_logic_vector(4 downto 0); + + begin + + xcode(4 downto 1) <= code; + xcode(0) <= mode; + + with xcode select + + segments_out <= + "1000000" WHEN "00000", --code=0, mode=0 x + "0001000" WHEN "00001", --code=0, mode=1 x + "1111001" WHEN "00010", --code=1, mode=0 x + "0100100" WHEN "00011", --code=1, mode=1 x + "0100100" WHEN "00100", --code=2, mode=0 x + "0110000" WHEN "00101", --code=2, mode=1 x + "0110000" WHEN "00110", --code=3, mode=0 x + "0011001" WHEN "00111", --code=3, mode=1 x + "0011001" WHEN "01000", --code=4, mode=0 x + "0010010" WHEN "01001", --code=4, mode=1 x + "0010010" WHEN "01010", --code=5, mode=0 x + "0000010" WHEN "01011", --code=5, mode=1 x + "0000010" WHEN "01100", --code=6, mode=0 x + "1111000" WHEN "01101", --code=6, mode=1 x + "1111000" WHEN "01110", --code=7, mode=0 x + "0000000" WHEN "01111", --code=7, mode=1 x + "0000000" WHEN "10000", --code=8, mode=0 x + "0010000" WHEN "10001", --code=8, mode=1 x + "0010000" WHEN "10010", --code=9, mode=0 x + "1000000" WHEN "10011", --code=9, mode=1 x + "0001000" WHEN "10100", --code=10, mode=0 x + "1100001" WHEN "10101", --code=10, mode=1 x + "0000011" WHEN "10110", --code=11, mode=0 x + "0100001" WHEN "10111", --code=11, mode=1 x + "1000101" WHEN "11000", --code=12, mode=0 x + "0001001" WHEN "11001", --code=12, mode=1 x + "0100001" WHEN "11010", --code=13, mode=0 x + "1000000" WHEN "11011", --code=13, mode=1 x + "0000110" WHEN "11100", --code=14, mode=0 x + "1000000" WHEN "11101", --code=14, mode=1 x + "1001110" WHEN "11110", --code=15, mode=0 x + "1000000" WHEN "11111"; --code=15, mode=1 x + +end behavior; \ No newline at end of file diff --git a/lab5/gA6_RANDU.bsf b/lab5/gA6_RANDU.bsf new file mode 100644 index 0000000..8156a45 --- /dev/null +++ b/lab5/gA6_RANDU.bsf @@ -0,0 +1,43 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 200 96) + (text "gA6_RANDU" (rect 5 0 66 12)(font "Arial" )) + (text "inst" (rect 8 64 20 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "seed[31..0]" (rect 0 0 42 12)(font "Arial" )) + (text "seed[31..0]" (rect 21 27 63 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 184 32) + (output) + (text "rand[31..0]" (rect 0 0 41 12)(font "Arial" )) + (text "rand[31..0]" (rect 122 27 163 39)(font "Arial" )) + (line (pt 184 32)(pt 168 32)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 168 64)(line_width 1)) + ) +) diff --git a/lab5/gA6_RANDU.vhd b/lab5/gA6_RANDU.vhd new file mode 100644 index 0000000..10f8b12 --- /dev/null +++ b/lab5/gA6_RANDU.vhd @@ -0,0 +1,72 @@ +-- This circuit implements the IBM RANDU version of a linear congruential generator +-- +-- entity name: gA6_RANDU +-- +-- Copyright (C) 2017 Abbas Yadollahi - He Qian Wang +-- Version 1.0 +-- Author: Abbas Yadollahi (abbas.yadollahi@mail.mcgill.ca) +-- He Qian Wang (he.q.wang@mail.mcgill.ca) +-- Date: Oct/18/2017 + +library lpm; -- Allows use of 32-bit adder +library ieee; -- Allows use of the std_logic_vector type +use lpm.lpm_components.all; +use ieee.std_logic_1164.all; + +entity gA6_RANDU is + port( + seed : in std_logic_vector(31 downto 0); + rand : out std_logic_vector(31 downto 0) + ); +end gA6_RANDU; + + +architecture behavior of gA6_RANDU is + component gA6_adder32 + port( + cin : in std_logic; + dataa : in std_logic_vector(31 downto 0); + datab : in std_logic_vector(31 downto 0); + cout : out std_logic; + result : out std_logic_vector(31 downto 0) + ); + end component; + + signal cin_1, cin_2 : std_logic; + signal cout_1, cout_2 : std_logic; + signal dataa_1, dataa_2 : std_logic_vector(31 downto 0) := (others => '0'); + signal datab_1, datab_2 : std_logic_vector(31 downto 0) := (others => '0'); + signal result_1, result_2 : std_logic_vector(31 downto 0) := (others => '0'); + + begin + + -- Port mapping 1 + first_adder : gA6_adder32 + port map( + cin => cin_1, + dataa => dataa_1, + datab => datab_1, + cout => cout_1, + result => result_1 + ); + + cin_1 <= '0'; + dataa_1(31 downto 16) <= seed(15 downto 0); + datab_1(16 downto 1) <= seed(15 downto 0); + + -- Port mapping 2 + second_adder : gA6_adder32 + port map( + cin => cin_2, + dataa => dataa_2, + datab => datab_2, + cout => cout_2, + result => result_2 + ); + + cin_2 <= '0'; + dataa_2(31 downto 0) <= result_1; + datab_2(15 downto 0) <= seed(15 downto 0); + rand(30 downto 0) <= result_2(30 downto 0); + +end behavior; \ No newline at end of file diff --git a/lab5/gA6_adder.bdf b/lab5/gA6_adder.bdf new file mode 100644 index 0000000..44a7072 --- /dev/null +++ b/lab5/gA6_adder.bdf @@ -0,0 +1,376 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "graphic" (version "1.4")) +(pin + (input) + (rect 64 24 232 40) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "A" (rect 5 0 13 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 64 48 232 64) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "B" (rect 5 0 12 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 64 72 232 88) + (text "INPUT" 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+) +(connector + (pt 112 160) + (pt 144 160) +) +(connector + (pt 320 288) + (pt 336 288) +) +(connector + (pt 320 240) + (pt 336 240) +) +(connector + (pt 336 288) + (pt 336 272) +) +(connector + (pt 336 240) + (pt 336 256) +) +(connector + (pt 336 256) + (pt 352 256) +) +(connector + (pt 336 272) + (pt 352 272) +) +(connector + (text "Cout" (rect 453 256 476 268)(font "Arial" )) + (pt 416 264) + (pt 448 264) +) +(junction (pt 232 176)) +(junction (pt 216 192)) +(junction (pt 128 144)) +(junction (pt 112 160)) diff --git a/lab5/gA6_adder.bsf b/lab5/gA6_adder.bsf new file mode 100644 index 0000000..b38442e --- /dev/null +++ b/lab5/gA6_adder.bsf @@ -0,0 +1,64 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 16 16 112 112) + (text "gA6_adder" (rect 5 0 68 14)(font "Arial" (font_size 8))) + (text "inst" (rect 8 80 25 92)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "A" (rect 0 0 9 14)(font "Arial" (font_size 8))) + (text "A" (rect 21 27 30 41)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)) + ) + (port + (pt 0 48) + (input) + (text "B" (rect 0 0 8 14)(font "Arial" (font_size 8))) + (text "B" (rect 21 43 29 57)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)) + ) + (port + (pt 0 64) + (input) + (text "Cin" (rect 0 0 17 14)(font "Arial" (font_size 8))) + (text "Cin" (rect 21 59 38 73)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 16 64)) + ) + (port + (pt 96 32) + (output) + (text "S" (rect 0 0 8 14)(font "Arial" (font_size 8))) + (text "S" (rect 67 27 75 41)(font "Arial" (font_size 8))) + (line (pt 96 32)(pt 80 32)) + ) + (port + (pt 96 48) + (output) + (text "Cout" (rect 0 0 25 14)(font "Arial" (font_size 8))) + (text "Cout" (rect 50 43 75 57)(font "Arial" (font_size 8))) + (line (pt 96 48)(pt 80 48)) + ) + (drawing + (rectangle (rect 16 16 80 80)) + ) +) diff --git a/lab5/gA6_adder32.cmp b/lab5/gA6_adder32.cmp new file mode 100644 index 0000000..e6ce3d2 --- /dev/null +++ b/lab5/gA6_adder32.cmp @@ -0,0 +1,25 @@ +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +component gA6_adder32 + PORT + ( + cin : IN STD_LOGIC ; + dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + cout : OUT STD_LOGIC ; + result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +end component; diff --git a/lab5/gA6_adder32.qip b/lab5/gA6_adder32.qip new file mode 100644 index 0000000..4d3959e --- /dev/null +++ b/lab5/gA6_adder32.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_ADD_SUB" +set_global_assignment -name IP_TOOL_VERSION "13.0" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "gA6_adder32.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "gA6_adder32.cmp"] diff --git a/lab5/gA6_adder32.vhd b/lab5/gA6_adder32.vhd new file mode 100644 index 0000000..113fdad --- /dev/null +++ b/lab5/gA6_adder32.vhd @@ -0,0 +1,77 @@ +-- megafunction wizard: %LPM_ADD_SUB% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: LPM_ADD_SUB + +-- ============================================================ +-- File Name: gA6_adder32.vhd +-- Megafunction Name(s): +-- LPM_ADD_SUB +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY gA6_adder32 IS + PORT + ( + cin : IN STD_LOGIC; + dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + cout : OUT STD_LOGIC; + result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +END gA6_adder32; + + +ARCHITECTURE SYN OF gA6_adder32 IS + + SIGNAL sub_wire0 : STD_LOGIC; + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0); + + + + COMPONENT lpm_add_sub + GENERIC ( + lpm_hint : STRING; + lpm_type : STRING; + lpm_width : NATURAL; + lpm_direction : STRING; + lpm_representation : STRING + ); + PORT ( + cin : IN STD_LOGIC; + dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + cout : OUT STD_LOGIC; + result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + cout <= sub_wire0; + result <= sub_wire1(31 DOWNTO 0); + + LPM_ADD_SUB_component : LPM_ADD_SUB + GENERIC MAP ( + lpm_direction => "ADD", + lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=YES", + lpm_representation => "UNSIGNED", + lpm_type => "LPM_ADD_SUB", + lpm_width => 32 + ) + PORT MAP ( + cin => cin, + dataa => dataa, + datab => datab, + cout => sub_wire0, + result => sub_wire1 + ); + +END SYN; diff --git a/lab5/gA6_adder32.vhd.bak b/lab5/gA6_adder32.vhd.bak new file mode 100644 index 0000000..4a50974 --- /dev/null +++ b/lab5/gA6_adder32.vhd.bak @@ -0,0 +1,146 @@ +-- megafunction wizard: %LPM_ADD_SUB% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: LPM_ADD_SUB + +-- ============================================================ +-- File Name: gA6_adder32.vhd +-- Megafunction Name(s): +-- LPM_ADD_SUB +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.0.0 Build 156 04/24/2013 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.all; + +ENTITY gA6_adder32 IS + PORT + ( + cin : IN STD_LOGIC ; + dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + cout : OUT STD_LOGIC ; + result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); +END gA6_adder32; + + +ARCHITECTURE SYN OF ga6_adder32 IS + + SIGNAL sub_wire0 : STD_LOGIC ; + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0); + + + + COMPONENT lpm_add_sub + GENERIC ( + lpm_direction : STRING; + lpm_hint : STRING; + lpm_representation : STRING; + lpm_type : STRING; + lpm_width : NATURAL + ); + PORT ( + cin : IN STD_LOGIC ; + datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + cout : OUT STD_LOGIC ; + dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + cout <= sub_wire0; + result <= sub_wire1(31 DOWNTO 0); + + LPM_ADD_SUB_component : LPM_ADD_SUB + GENERIC MAP ( + lpm_direction => "ADD", + lpm_hint => "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=YES", + lpm_representation => "UNSIGNED", + lpm_type => "LPM_ADD_SUB", + lpm_width => 32 + ) + PORT MAP ( + cin => cin, + datab => datab, + dataa => dataa, + cout => sub_wire0, + result => sub_wire1 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: CarryIn NUMERIC "1" +-- Retrieval info: PRIVATE: CarryOut NUMERIC "1" +-- Retrieval info: PRIVATE: ConstantA NUMERIC "0" +-- Retrieval info: PRIVATE: ConstantB NUMERIC "0" +-- Retrieval info: PRIVATE: Function NUMERIC "0" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +-- Retrieval info: PRIVATE: LPM_PIPELINE NUMERIC "0" +-- Retrieval info: PRIVATE: Latency NUMERIC "0" +-- Retrieval info: PRIVATE: Overflow NUMERIC "0" +-- Retrieval info: PRIVATE: RadixA NUMERIC "10" +-- Retrieval info: PRIVATE: RadixB NUMERIC "10" +-- Retrieval info: PRIVATE: Representation NUMERIC "1" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: ValidCtA NUMERIC "0" +-- Retrieval info: PRIVATE: ValidCtB NUMERIC "0" +-- Retrieval info: PRIVATE: WhichConstant NUMERIC "0" +-- Retrieval info: PRIVATE: aclr NUMERIC "0" +-- Retrieval info: PRIVATE: clken NUMERIC "0" +-- Retrieval info: PRIVATE: nBit NUMERIC "32" +-- Retrieval info: PRIVATE: new_diagram STRING "1" +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "ADD" +-- Retrieval info: CONSTANT: LPM_HINT STRING "ONE_INPUT_IS_CONSTANT=NO,CIN_USED=YES" +-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_ADD_SUB" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32" +-- Retrieval info: USED_PORT: cin 0 0 0 0 INPUT NODEFVAL "cin" +-- Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL "cout" +-- Retrieval info: USED_PORT: dataa 0 0 32 0 INPUT NODEFVAL "dataa[31..0]" +-- Retrieval info: USED_PORT: datab 0 0 32 0 INPUT NODEFVAL "datab[31..0]" +-- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]" +-- Retrieval info: CONNECT: @cin 0 0 0 0 cin 0 0 0 0 +-- Retrieval info: CONNECT: @dataa 0 0 32 0 dataa 0 0 32 0 +-- Retrieval info: CONNECT: @datab 0 0 32 0 datab 0 0 32 0 +-- Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0 +-- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL gA6_adder32.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL gA6_adder32.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL gA6_adder32.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL gA6_adder32.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL gA6_adder32_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/lab5/gA6_adder6.bdf b/lab5/gA6_adder6.bdf new file mode 100644 index 0000000..32fc249 --- /dev/null +++ b/lab5/gA6_adder6.bdf @@ -0,0 +1,604 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "graphic" (version "1.4")) +(pin + (input) + (rect 47 32 215 48) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "A[5..0]" (rect 5 0 38 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 255 32 423 48) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "B[5..0]" (rect 5 0 38 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 463 32 631 48) + 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File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 16 16 144 112) + (text "gA6_adder6" (rect 5 0 75 14)(font "Arial" (font_size 8))) + (text "inst" (rect 8 80 25 92)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "A[5..0]" (rect 0 0 37 14)(font "Arial" (font_size 8))) + (text "A[5..0]" (rect 21 27 58 41)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "B[5..0]" (rect 0 0 36 14)(font "Arial" (font_size 8))) + (text "B[5..0]" (rect 21 43 57 57)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)(line_width 3)) + ) + (port + (pt 0 64) + (input) + (text "Cin" (rect 0 0 17 14)(font "Arial" (font_size 8))) + (text "Cin" (rect 21 59 38 73)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 16 64)) + ) + (port + (pt 128 32) + (output) + (text "Cout" (rect 0 0 25 14)(font "Arial" (font_size 8))) + (text "Cout" (rect 82 27 107 41)(font "Arial" (font_size 8))) + (line (pt 128 32)(pt 112 32)) + ) + (port + (pt 128 48) + (output) + (text "S[5..0]" (rect 0 0 36 14)(font "Arial" (font_size 8))) + (text "S[5..0]" (rect 71 43 107 57)(font "Arial" (font_size 8))) + (line (pt 128 48)(pt 112 48)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 112 80)) + ) +) diff --git a/lab5/gA6_adder8.bdf b/lab5/gA6_adder8.bdf new file mode 100644 index 0000000..1990ef4 --- /dev/null +++ b/lab5/gA6_adder8.bdf @@ -0,0 +1,763 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! 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(pt 640 96) +) diff --git a/lab5/gA6_adder8.bsf b/lab5/gA6_adder8.bsf new file mode 100644 index 0000000..8880be2 --- /dev/null +++ b/lab5/gA6_adder8.bsf @@ -0,0 +1,64 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 16 16 144 112) + (text "gA6_adder8" (rect 5 0 75 14)(font "Arial" (font_size 8))) + (text "inst" (rect 8 80 25 92)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "Cin" (rect 0 0 17 14)(font "Arial" (font_size 8))) + (text "Cin" (rect 21 27 38 41)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)) + ) + (port + (pt 0 48) + (input) + (text "A[7..0]" (rect 0 0 37 14)(font "Arial" (font_size 8))) + (text "A[7..0]" (rect 21 43 58 57)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)(line_width 3)) + ) + (port + (pt 0 64) + (input) + (text "B[7..0]" (rect 0 0 36 14)(font "Arial" (font_size 8))) + (text "B[7..0]" (rect 21 59 57 73)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 16 64)(line_width 3)) + ) + (port + (pt 128 32) + (output) + (text "Cout" (rect 0 0 25 14)(font "Arial" (font_size 8))) + (text "Cout" (rect 82 27 107 41)(font "Arial" (font_size 8))) + (line (pt 128 32)(pt 112 32)) + ) + (port + (pt 128 48) + (output) + (text "S[7..0]" (rect 0 0 36 14)(font "Arial" (font_size 8))) + (text "S[7..0]" (rect 71 43 107 57)(font "Arial" (font_size 8))) + (line (pt 128 48)(pt 112 48)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 112 80)) + ) +) diff --git a/lab5/gA6_computer.bsf b/lab5/gA6_computer.bsf new file mode 100644 index 0000000..6fdfcbc --- /dev/null +++ b/lab5/gA6_computer.bsf @@ -0,0 +1,85 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 208 160) + (text "gA6_computer" (rect 5 0 66 12)(font "Arial" )) + (text "inst" (rect 8 128 20 140)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clk" (rect 0 0 10 12)(font "Arial" )) + (text "clk" (rect 21 27 31 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "rst" (rect 0 0 10 12)(font "Arial" )) + (text "rst" (rect 21 43 31 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 0 64) + (input) + (text "turn" (rect 0 0 15 12)(font "Arial" )) + (text "turn" (rect 21 59 36 71)(font "Arial" )) + (line (pt 0 64)(pt 16 64)(line_width 1)) + ) + (port + (pt 0 80) + (input) + (text "setup" (rect 0 0 21 12)(font "Arial" )) + (text "setup" (rect 21 75 42 87)(font "Arial" )) + (line (pt 0 80)(pt 16 80)(line_width 1)) + ) + (port + (pt 0 96) + (input) + (text "sum[5..0]" (rect 0 0 37 12)(font "Arial" )) + (text "sum[5..0]" (rect 21 91 58 103)(font "Arial" )) + (line (pt 0 96)(pt 16 96)(line_width 3)) + ) + (port + (pt 192 32) + (output) + (text "hit" (rect 0 0 8 12)(font "Arial" )) + (text "hit" (rect 163 27 171 39)(font "Arial" )) + (line (pt 192 32)(pt 176 32)(line_width 1)) + ) + (port + (pt 192 48) + (output) + (text "done" (rect 0 0 18 12)(font "Arial" )) + (text "done" (rect 153 43 171 55)(font "Arial" )) + (line (pt 192 48)(pt 176 48)(line_width 1)) + ) + (port + (pt 192 64) + (output) + (text "sum_out[5..0]" (rect 0 0 55 12)(font "Arial" )) + (text "sum_out[5..0]" (rect 116 59 171 71)(font "Arial" )) + (line (pt 192 64)(pt 176 64)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 176 128)(line_width 1)) + ) +) diff --git a/lab5/gA6_computer.vhd b/lab5/gA6_computer.vhd new file mode 100644 index 0000000..9d3f7e7 --- /dev/null +++ b/lab5/gA6_computer.vhd @@ -0,0 +1,106 @@ +-- entity name: gA6_computer +-- +-- Copyright (C) 2017 Abbas Yadollahi - He Qian Wang +-- Version 1.0 +-- Author: Abbas Yadollahi (abbas.yadollahi@mail.mcgill.ca) +-- He Qian Wang (he.q.wang@mail.mcgill.ca) +-- Date: Nov/29/2017 + +library ieee; +use ieee.numeric_std.all; +use ieee.std_logic_1164.all; + +entity gA6_computer is + port( + clk : in std_logic; + rst : in std_logic; + turn : in std_logic; + setup : in std_logic; + sum : in std_logic_vector(5 downto 0); + + hit : out std_logic; + done : out std_logic; + sum_out : out std_logic_vector(5 downto 0) + ); +end gA6_computer; + +architecture behavior of gA6_computer is + begin + computer: process(clk, rst, turn, setup, sum) + + variable state : std_logic_vector(1 downto 0); + variable dealer_sum : std_logic_vector(5 downto 0); + + begin + -- Reset is on + if rst = '1' then + hit <= '0'; + done <= '0'; + sum_out <= "000000"; + + state := "00"; + elsif rising_edge(clk) then + case state is + -- State A/000 + -- Wait for setup + when "000" => + hit <= '0'; + done <= '0'; + sum_out <= "000000"; + + if setup = '1' then + state := "001"; + end if; + + -- State B/001 + -- Hit first card + when "001" => + hit <= '1'; + done <= '0'; + sum_out <= sum; + + state := "010"; + + -- State C/010 + -- Wait for turn + when "010" => + hit <= '0'; + done <= '0'; + sum_out <= sum; + + if turn = '1' then + state := "011"; + end if; + + -- State D/011 + -- Hit until 17/bust + when "011" => + hit <= '1'; + done <= '0'; + sum_out <= sum; + + if unsigned(sum) > 16 then + state := "100"; + hit <= '0'; + end if; + + -- State E/100 + -- Set done + when "100" => + hit <= '0'; + done <= '1'; + sum_out <= sum; + + state := "000"; + + -- Random State + when others => + hit <= '0'; + done <= '0'; + sum_out <= sum; + + state := "00"; + end case; + end if; + end process; +end behavior; \ No newline at end of file diff --git a/lab5/gA6_computer.vhd.bak b/lab5/gA6_computer.vhd.bak new file mode 100644 index 0000000..f143f94 --- /dev/null +++ b/lab5/gA6_computer.vhd.bak @@ -0,0 +1,73 @@ +-- entity name: gA6_computer +-- +-- Copyright (C) 2017 Abbas Yadollahi - He Qian Wang +-- Version 1.0 +-- Author: Abbas Yadollahi (abbas.yadollahi@mail.mcgill.ca) +-- He Qian Wang (he.q.wang@mail.mcgill.ca) +-- Date: Nov/29/2017 + +library ieee; +use ieee.numeric_std.all; +use ieee.std_logic_1164.all; + +entity gA6_computer is + port( + clk : in std_logic; + rst : in std_logic; + turn : in std_logic; + sum : in std_logic_vector(5 downto 0); + + hit : out std_logic; + done : out std_logic; + sum_out : out std_logic_vector(5 downto 0) + ); +end gA6_computer; + +architecture behavior of gA6_computer is + begin + computer: process(clk, rst, turn, sum) + + variable state : std_logic_vector(1 downto 0); + variable dealer_sum : std_logic_vector(5 downto 0) + + begin + -- Reset is on + if rst = '1' then + draw <= '0'; + finished <= '0'; + sum_out <= "000000"; + + state := "00"; + elsif rising_edge(clk) then + case state is + -- State A/00 + when "00" => + hit <= '0'; + done <= '0'; + sum_out <= sum; + + if turn = '1' then + state := "01"; + end if; + + -- State B/01 + when "01" => + hit <= '1'; + done <= '0'; + sum_out <= sum; + + if unsigned(sum) > 16 then + state := "10"; + end if; + + -- State C/10 + when "10" => + hit <= '0'; + done <= '1'; + sum_out <= sum; + + state := "00"; + end case; + end if; + end process; +end behavior; \ No newline at end of file diff --git a/lab5/gA6_datapath.bsf b/lab5/gA6_datapath.bsf new file mode 100644 index 0000000..a86ea3a --- /dev/null +++ b/lab5/gA6_datapath.bsf @@ -0,0 +1,127 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 240 192) + (text "gA6_datapath" (rect 5 0 61 12)(font "Arial" )) + (text "inst" (rect 8 160 20 172)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clk" (rect 0 0 10 12)(font "Arial" )) + (text "clk" (rect 21 27 31 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "rst" (rect 0 0 10 12)(font "Arial" )) + (text "rst" (rect 21 43 31 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 0 64) + (input) + (text "p_win" (rect 0 0 22 12)(font "Arial" )) + (text "p_win" (rect 21 59 43 71)(font "Arial" )) + (line (pt 0 64)(pt 16 64)(line_width 1)) + ) + (port + (pt 0 80) + (input) + (text "d_win" (rect 0 0 22 12)(font "Arial" )) + (text "d_win" (rect 21 75 43 87)(font "Arial" )) + (line (pt 0 80)(pt 16 80)(line_width 1)) + ) + (port + (pt 0 96) + (input) + (text "new_game" (rect 0 0 43 12)(font "Arial" )) + (text "new_game" (rect 21 91 64 103)(font "Arial" )) + (line (pt 0 96)(pt 16 96)(line_width 1)) + ) + (port + (pt 0 112) + (input) + (text "player_hit" (rect 0 0 38 12)(font "Arial" )) + (text "player_hit" (rect 21 107 59 119)(font "Arial" )) + (line (pt 0 112)(pt 16 112)(line_width 1)) + ) + (port + (pt 0 128) + (input) + (text "player_stay" (rect 0 0 48 12)(font "Arial" )) + (text "player_stay" (rect 21 123 69 135)(font "Arial" )) + (line (pt 0 128)(pt 16 128)(line_width 1)) + ) + (port + (pt 0 144) + (input) + (text "player_legal" (rect 0 0 47 12)(font "Arial" )) + (text "player_legal" (rect 21 139 68 151)(font "Arial" )) + (line (pt 0 144)(pt 16 144)(line_width 1)) + ) + (port + (pt 224 32) + (output) + (text "setup" (rect 0 0 21 12)(font "Arial" )) + (text "setup" (rect 182 27 203 39)(font "Arial" )) + (line (pt 224 32)(pt 208 32)(line_width 1)) + ) + (port + (pt 224 48) + (output) + (text "player_draw" (rect 0 0 49 12)(font "Arial" )) + (text "player_draw" (rect 154 43 203 55)(font "Arial" )) + (line (pt 224 48)(pt 208 48)(line_width 1)) + ) + (port + (pt 224 64) + (output) + (text "computer_turn" (rect 0 0 59 12)(font "Arial" )) + (text "computer_turn" (rect 144 59 203 71)(font "Arial" )) + (line (pt 224 64)(pt 208 64)(line_width 1)) + ) + (port + (pt 224 80) + (output) + (text "p_win_streak[1..0]" (rect 0 0 71 12)(font "Arial" )) + (text "p_win_streak[1..0]" (rect 132 75 203 87)(font "Arial" )) + (line (pt 224 80)(pt 208 80)(line_width 3)) + ) + (port + (pt 224 96) + (output) + (text "d_win_streak[1..0]" (rect 0 0 71 12)(font "Arial" )) + (text "d_win_streak[1..0]" (rect 132 91 203 103)(font "Arial" )) + (line (pt 224 96)(pt 208 96)(line_width 3)) + ) + (port + (pt 224 112) + (output) + (text "game_score[3..0]" (rect 0 0 70 12)(font "Arial" )) + (text "game_score[3..0]" (rect 133 107 203 119)(font "Arial" )) + (line (pt 224 112)(pt 208 112)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 208 160)(line_width 1)) + ) +) diff --git a/lab5/gA6_datapath.vhd b/lab5/gA6_datapath.vhd new file mode 100644 index 0000000..31c8d9d --- /dev/null +++ b/lab5/gA6_datapath.vhd @@ -0,0 +1,154 @@ +-- entity name: gA6_datapath +-- +-- Copyright (C) 2017 Abbas Yadollahi - He Qian Wang +-- Version 1.0 +-- Author: Abbas Yadollahi (abbas.yadollahi@mail.mcgill.ca) +-- He Qian Wang (he.q.wang@mail.mcgill.ca) +-- Date: Nov/29/2017 + +library ieee; +use ieee.numeric_std.all; +use ieee.std_logic_1164.all; + +entity gA6_datapath is + port( + clk : in std_logic; + rst : in std_logic; + p_win : in std_logic; + d_win : in std_logic; + new_game : in std_logic; + player_hit : in std_logic; + player_stay : in std_logic; + player_legal : in std_logic; + + setup : out std_logic; + player_draw : out std_logic; + computer_turn : out std_logic; + p_win_streak : out std_logic_vector(1 downto 0); + d_win_streak : out std_logic_vector(1 downto 0); + game_score : out std_logic_vector(3 downto 0) + ); +end gA6_datapath; + +architecture behavior of gA6_datapath is + begin + computer: process(clk, rst, p_win, d_win, new_game, player_hit, player_stay, player_legal) + + variable state : std_logic_vector(2 downto 0); + variable p_win_count : unsigned(1 downto 0); + variable d_win_count : unsigned(1 downto 0); + variable game_count : unsigned(3 downto 0); + + begin + -- Reset is on + if rst = '1' then + setup <= '0'; + player_draw <= '0'; + computer_turn <= '0'; + + state := "000"; + elsif rising_edge(clk) then + case state is + -- State A/000 + when "000" => + player_draw <= '0'; + computer_turn <= '0'; + + if new_game = '1' then + setup <= '1'; + + state := "001"; + end if; + + -- State B/001 + when "001" => + if player_legal = '1' or player_stay = '1' then + setup <= '0'; + player_draw <= '0'; + computer_turn <= '1'; + + state := "010"; + elsif player_hit = '1' then + setup <= '0'; + player_draw <= '1'; + computer_turn <= '0'; + end if; + + -- State C/010 + when "010" => + setup <= '0'; + player_draw <= '0'; + computer_turn <= '1'; + + state := "011"; + + -- State D/011 + when "011" => + setup <= '0'; + player_draw <= '0'; + computer_turn <= '0'; + + if p_win = '1' or d_win = '1' then + if p_win = '1' and d_win = '0' then + p_win_count := p_win_count + 1; + elsif p_win = '0' and d_win = '1' then + d_win_count := d_win_count + 1; + end if; + + state := "100"; + end if; + + -- State E/100 + when "100" => + setup <= '0'; + player_draw <= '0'; + computer_turn <= '0'; + + game_count := game_count + 1; + if p_win_count > 2 or d_win_count > 2 then + state := "101"; + else + state := "110"; + end if; + + -- State F/101 + when "101" => + setup <= '0'; + player_draw <= '0'; + computer_turn <= '0'; + + if rst = '1' then + state := "000"; + p_win_count := to_unsigned(0, 2); + d_win_count := to_unsigned(0, 2); + game_count := to_unsigned(0, 4); + end if; + + -- State G/110 + when "110" => + setup <= '0'; + player_draw <= '0'; + computer_turn <= '0'; + + if new_game = '1' then + state := "000"; + end if; + + -- Random State + when others => + setup <= '0'; + player_draw <= '0'; + computer_turn <= '0'; + + state := "000"; + p_win_count := to_unsigned(0, 2); + d_win_count := to_unsigned(0, 2); + game_count := to_unsigned(0, 4); + end case; + end if; + + p_win_streak <= std_logic_vector(p_win_count); + d_win_streak <= std_logic_vector(d_win_count); + game_score <= std_logic_vector(game_count); + end process; +end behavior; \ No newline at end of file diff --git a/lab5/gA6_datapath.vhd.bak b/lab5/gA6_datapath.vhd.bak new file mode 100644 index 0000000..6af0ccf --- /dev/null +++ b/lab5/gA6_datapath.vhd.bak @@ -0,0 +1,139 @@ +-- entity name: gA6_datapath +-- +-- Copyright (C) 2017 Abbas Yadollahi - He Qian Wang +-- Version 1.0 +-- Author: Abbas Yadollahi (abbas.yadollahi@mail.mcgill.ca) +-- He Qian Wang (he.q.wang@mail.mcgill.ca) +-- Date: Nov/29/2017 + +library ieee; +use ieee.numeric_std.all; +use ieee.std_logic_1164.all; + +entity gA6_datapath is + port( + clk : in std_logic; + rst : in std_logic; + d_win : in std_logic; + p_win : in std_logic; + new_game : in std_logic; + player_hit : in std_logic; + player_stay : in std_logic; + player_sum : in std_logic_vector(5 downto 0); + + setup : out std_logic; + player_draw : out std_logic; + computer_turn : out std_logic + ); +end gA6_datapath; + +architecture behavior of gA6_datapath is + begin + computer: process(clk, rst, p_win, d_win, new_game, player_hit, player_stay, player_sum) + + variable state : std_logic_vector(2 downto 0); + variable p_win_count : unsigned(1 downto 0); + variable d_win_count : unsigned(1 downto 0); + + begin + -- Reset is on + if rst = '1' then + setup <= '0'; + player_draw <= '0'; + computer_turn <= '0'; + + state := "000"; + elsif rising_edge(clk) then + case state is + -- State A/000 + when "000" => + player_draw <= '0'; + computer_turn <= '0'; + + if new_game = '1' then + setup <= '1'; + + state := "001"; + end if; + + -- State B/001 + when "001" => + if unsigned(player_sum) > 21 or player_stay = '1' then + setup <= '0'; + player_draw <= '0'; + computer_turn <= '1'; + + state := "010"; + elsif player_hit = '1' then + setup <= '0'; + player_draw <= '1'; + computer_turn <= '0'; + end if; + + -- State C/010 + when "010" => + setup <= '0'; + player_draw <= '0'; + computer_turn <= '1'; + + state := "011"; + + -- State D/011 + when "011" => + setup <= '0'; + player_draw <= '0'; + computer_turn <= '0'; + + if p_win = '1' or d_win = '1' then + if p_win = '1' and d_win = '0' then + p_win_count := p_win_count + 1; + elsif p_win = '0' and d_win = '1' then + d_win_count := d_win_count + 1; + end if; + + state := "100"; + end if; + + -- State E/100 + when "100" => + setup <= '0'; + player_draw <= '0'; + computer_turn <= '0'; + + if p_win_count > 2 or d_win_count > 2 then + state := "101"; + else + state := "110"; + end if; + + -- State F/101 + when "101" => + setup <= '0'; + player_draw <= '0'; + computer_turn <= '0'; + + if rst = '1' then + state := "000"; + end if; + + -- State G/110 + when "110" => + setup <= '0'; + player_draw <= '0'; + computer_turn <= '0'; + + if new_game = '1' then + state := "000"; + end if; + + -- Random State + when others => + setup <= '0'; + player_draw <= '0'; + computer_turn <= '0'; + + state := "000"; + end case; + end if; + end process; +end behavior; \ No newline at end of file diff --git a/lab5/gA6_dealer.bsf b/lab5/gA6_dealer.bsf new file mode 100644 index 0000000..2a178f4 --- /dev/null +++ b/lab5/gA6_dealer.bsf @@ -0,0 +1,71 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 216 128) + (text "gA6_dealer" (rect 5 0 52 12)(font "Arial" )) + (text "inst" (rect 8 96 20 108)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clk" (rect 0 0 10 12)(font "Arial" )) + (text "clk" (rect 21 27 31 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "rst" (rect 0 0 10 12)(font "Arial" )) + (text "rst" (rect 21 43 31 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 0 64) + (input) + (text "legal_num" (rect 0 0 40 12)(font "Arial" )) + (text "legal_num" (rect 21 59 61 71)(font "Arial" )) + (line (pt 0 64)(pt 16 64)(line_width 1)) + ) + (port + (pt 0 80) + (input) + (text "request_deal" (rect 0 0 50 12)(font "Arial" )) + (text "request_deal" (rect 21 75 71 87)(font "Arial" )) + (line (pt 0 80)(pt 16 80)(line_width 1)) + ) + (port + (pt 200 32) + (output) + (text "rand_enable" (rect 0 0 48 12)(font "Arial" )) + (text "rand_enable" (rect 131 27 179 39)(font "Arial" )) + (line (pt 200 32)(pt 184 32)(line_width 1)) + ) + (port + (pt 200 48) + (output) + (text "stack_enable" (rect 0 0 51 12)(font "Arial" )) + (text "stack_enable" (rect 128 43 179 55)(font "Arial" )) + (line (pt 200 48)(pt 184 48)(line_width 1)) + ) + (drawing + (rectangle (rect 16 16 184 96)(line_width 1)) + ) +) diff --git a/lab5/gA6_dealer.vhd b/lab5/gA6_dealer.vhd new file mode 100644 index 0000000..14e057c --- /dev/null +++ b/lab5/gA6_dealer.vhd @@ -0,0 +1,78 @@ +-- entity name: gA6_dealer +-- +-- Copyright (C) 2017 Abbas Yadollahi - He Qian Wang +-- Version 1.0 +-- Author: Abbas Yadollahi (abbas.yadollahi@mail.mcgill.ca) +-- He Qian Wang (he.q.wang@mail.mcgill.ca) +-- Date: Nov/17/2017 + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity gA6_dealer is + port( + clk : in std_logic; + rst : in std_logic; + legal_num : in std_logic; + request_deal : in std_logic; + + rand_enable : out std_logic; + stack_enable : out std_logic + ); +end gA6_dealer; + +architecture behavior of gA6_dealer is + begin + dealer: process(clk, rst, legal_num, request_deal) + + variable state : std_logic_vector(1 downto 0); + variable req_in : std_logic_vector(1 downto 0); + + begin + req_in := legal_num & request_deal; + + -- Reset is on + if rst = '1' then + rand_enable <= '0'; + stack_enable <= '0'; + state := "00"; + elsif rising_edge(clk) then + case state is + -- State A/00 + when "00" => + rand_enable <= '0'; + stack_enable <= '0'; + + if req_in(0) = '0' then + state := "01"; + end if; + + -- State B/01 + when "01" => + rand_enable <= '0'; + stack_enable <= '0'; + + if req_in(0) = '1' then + state := "10"; + end if; + + -- State C/10 + when "10" => + rand_enable <= '1'; + stack_enable <= '0'; + + if req_in(1) = '1' then + state := "11"; + end if; + + -- State D/11 + when "11" => + rand_enable <= '0'; + stack_enable <= '1'; + + state := "00"; + end case; + end if; + end process; +end behavior; \ No newline at end of file diff --git a/lab5/gA6_dealer.vhd.bak b/lab5/gA6_dealer.vhd.bak new file mode 100644 index 0000000..dbfeea0 --- /dev/null +++ b/lab5/gA6_dealer.vhd.bak @@ -0,0 +1,25 @@ +-- entity name: gA6_dealer +-- +-- Copyright (C) 2017 Abbas Yadollahi - He Qian Wang +-- Version 1.0 +-- Author: Abbas Yadollahi (abbas.yadollahi@mail.mcgill.ca) +-- He Qian Wang (he.q.wang@mail.mcgill.ca) +-- Date: Nov/17/2017 + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity gA6_dealer is + port( + new_card : in std_logic_vector(5 downto 0); + cards_in_hand : in std_logic_vector(5 downto 0); + ace_count : in std_logic_vector(2 downto 0); + legal_play : out std_logic; + new_ace_count : out std_logic_vector(2 downto 0); + out_1 : out unsigned(2 downto 0); + out_2 : out unsigned(5 downto 0); + out_3 : out unsigned(5 downto 0); + out_4 : out std_logic + ); +end gA6_dealer; diff --git a/lab5/gA6_debouncer.bdf b/lab5/gA6_debouncer.bdf new file mode 100644 index 0000000..73983ad --- /dev/null +++ b/lab5/gA6_debouncer.bdf @@ -0,0 +1,458 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "graphic" (version "1.4")) +(pin + (input) + (rect 240 112 408 128) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "button" (rect 5 0 35 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 240 136 408 152) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "clk" (rect 5 0 19 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 184 136 240 152)) +) +(pin + (output) + (rect 440 112 616 128) + (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) + (text "enable" (rect 90 0 121 12)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) +) +(symbol + (rect 226 200 274 232) + (text "NOT" (rect 1 0 21 10)(font "Arial" (font_size 6))) + (text "inst10" (rect 3 21 32 33)(font "Arial" )) + (port + (pt 0 16) + (input) + (text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible)) + (text "IN" (rect 2 7 13 19)(font "Courier New" (bold))(invisible)) + (line (pt 0 16)(pt 13 16)) + ) + (port + (pt 48 16) + (output) + (text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible)) + (text "OUT" (rect 32 7 49 19)(font "Courier New" (bold))(invisible)) + (line (pt 39 16)(pt 48 16)) + ) + (drawing + (line (pt 13 25)(pt 13 7)) + (line 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216) +) +(connector + (pt 282 216) + (pt 274 216) +) +(connector + (text "clk" (rect 194 240 208 252)(font "Arial" )) + (pt 282 248) + (pt 218 248) +) diff --git a/lab5/gA6_debouncer.bsf b/lab5/gA6_debouncer.bsf new file mode 100644 index 0000000..5270ed9 --- /dev/null +++ b/lab5/gA6_debouncer.bsf @@ -0,0 +1,50 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 16 16 144 112) + (text "gA6_debouncer" (rect 5 0 97 14)(font "Arial" (font_size 8))) + (text "inst" (rect 8 80 25 92)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "button" (rect 0 0 35 14)(font "Arial" (font_size 8))) + (text "button" (rect 21 27 56 41)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)) + ) + (port + (pt 0 48) + (input) + (text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8))) + (text "clk" (rect 21 43 36 57)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)) + ) + (port + (pt 128 32) + (output) + (text "enable" (rect 0 0 37 14)(font "Arial" (font_size 8))) + (text "enable" (rect 70 27 107 41)(font "Arial" (font_size 8))) + (line (pt 128 32)(pt 112 32)) + ) + (drawing + (rectangle (rect 16 16 112 80)) + ) +) diff --git a/lab5/gA6_ff_enable52.bdf b/lab5/gA6_ff_enable52.bdf new file mode 100644 index 0000000..3edc2df --- /dev/null +++ b/lab5/gA6_ff_enable52.bdf @@ -0,0 +1,6067 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. 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File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 16 16 208 144) + (text "gA6_ff_enable52" (rect 5 0 104 14)(font "Arial" (font_size 8))) + (text "inst" (rect 8 112 25 124)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "nop" (rect 0 0 21 14)(font "Arial" (font_size 8))) + (text "nop" (rect 21 27 42 41)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)) + ) + (port + (pt 0 48) + (input) + (text "push" (rect 0 0 28 14)(font "Arial" (font_size 8))) + (text "push" (rect 21 43 49 57)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)) + ) + (port + (pt 0 64) + (input) + (text "enable" (rect 0 0 37 14)(font "Arial" (font_size 8))) + (text "enable" (rect 21 59 58 73)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 16 64)) + ) + (port + (pt 0 80) + (input) + (text "en_in[51..0]" (rect 0 0 66 14)(font "Arial" (font_size 8))) + (text "en_in[51..0]" (rect 21 75 87 89)(font "Arial" (font_size 8))) + (line (pt 0 80)(pt 16 80)(line_width 3)) + ) + (port + (pt 192 32) + (output) + (text "en_out[51..0]" (rect 0 0 74 14)(font "Arial" (font_size 8))) + (text "en_out[51..0]" (rect 97 27 171 41)(font "Arial" (font_size 8))) + (line (pt 192 32)(pt 176 32)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 176 112)) + ) +) diff --git a/lab5/gA6_lab5.bdf b/lab5/gA6_lab5.bdf new file mode 100644 index 0000000..418db34 --- /dev/null +++ b/lab5/gA6_lab5.bdf @@ -0,0 +1,2082 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. 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(rect -136 440 -96 452)(font "Arial" )) + (pt -96 448) + (pt -72 448) +) +(connector + (text "player_legal" (rect -152 456 -93 468)(font "Arial" )) + (pt -72 464) + (pt -96 464) +) +(junction (pt -552 184)) +(junction (pt -552 280)) +(junction (pt -552 232)) diff --git a/lab5/gA6_lab5.qpf b/lab5/gA6_lab5.qpf new file mode 100644 index 0000000..af36ca2 --- /dev/null +++ b/lab5/gA6_lab5.qpf @@ -0,0 +1,30 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.0 Build 156 04/24/2013 SJ Web Edition +# Date created = 16:43:13 November 29, 2017 +# +# -------------------------------------------------------------------------- # + +QUARTUS_VERSION = "13.0" +DATE = "16:43:13 November 29, 2017" + +# Revisions + +PROJECT_REVISION = "gA6_lab5" diff --git a/lab5/gA6_lab5.qsf b/lab5/gA6_lab5.qsf new file mode 100644 index 0000000..47eeca5 --- /dev/null +++ b/lab5/gA6_lab5.qsf @@ -0,0 +1,84 @@ +# -------------------------------------------------------------------------- # +# +# Copyright (C) 1991-2013 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. +# +# -------------------------------------------------------------------------- # +# +# Quartus II 64-Bit +# Version 13.0.0 Build 156 04/24/2013 SJ Web Edition +# Date created = 16:43:13 November 29, 2017 +# +# -------------------------------------------------------------------------- # +# +# Notes: +# +# 1) The default values for assignments are stored in the file: +# gA6_lab5_assignment_defaults.qdf +# If this file doesn't exist, see file: +# assignment_defaults.qdf +# +# 2) Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. +# +# -------------------------------------------------------------------------- # + + +set_global_assignment -name FAMILY "Cyclone II" +set_global_assignment -name DEVICE EP2C20F484C7 +set_global_assignment -name TOP_LEVEL_ENTITY gA6_lab5 +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.0 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "16:43:13 NOVEMBER 29, 2017" +set_global_assignment -name LAST_QUARTUS_VERSION 13.0 +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 +set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name SIMULATION_MODE FUNCTIONAL +set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST ON -section_id eda_simulation +set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE "C:/home/abbas/dsd_A6/lab5/gA6_lab5_fsm.vwf" +set_global_assignment -name SOURCE_FILE lpm_mux0.cmp +set_global_assignment -name SOURCE_FILE gA6_adder32.cmp +set_global_assignment -name QIP_FILE lpm_mux0.qip +set_global_assignment -name QIP_FILE gA6_adder32.qip +set_global_assignment -name BDF_FILE gA6_stack52.bdf +set_global_assignment -name BDF_FILE gA6_not6.bdf +set_global_assignment -name BDF_FILE gA6_modulo_13.bdf +set_global_assignment -name BDF_FILE gA6_ff_enable52.bdf +set_global_assignment -name BDF_FILE gA6_debouncer.bdf +set_global_assignment -name BDF_FILE gA6_adder8.bdf +set_global_assignment -name BDF_FILE gA6_adder6.bdf +set_global_assignment -name BDF_FILE gA6_adder.bdf +set_global_assignment -name VHDL_FILE lpm_mux0.vhd +set_global_assignment -name VHDL_FILE gA6_rules.vhd +set_global_assignment -name VHDL_FILE gA6_RANDU.vhd +set_global_assignment -name VHDL_FILE gA6_pop_enable.vhd +set_global_assignment -name VHDL_FILE gA6_dealer.vhd +set_global_assignment -name VHDL_FILE gA6_adder32.vhd +set_global_assignment -name VHDL_FILE gA6_7_segment_decoder.vhd +set_global_assignment -name VHDL_FILE gA6_winner.vhd +set_global_assignment -name VHDL_FILE gA6_computer.vhd +set_global_assignment -name BDF_FILE gA6_lab5.bdf +set_global_assignment -name VECTOR_WAVEFORM_FILE gA6_lab5_fsm.vwf +set_global_assignment -name BDF_FILE Block2.bdf +set_global_assignment -name QIP_FILE lpm_mux1.qip +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/lab5/gA6_lab5.qws b/lab5/gA6_lab5.qws new file mode 100644 index 0000000..f5269dd Binary files /dev/null and b/lab5/gA6_lab5.qws differ diff --git a/lab5/gA6_lab5_fsm.vwf b/lab5/gA6_lab5_fsm.vwf new file mode 100644 index 0000000..f95cf67 --- /dev/null +++ b/lab5/gA6_lab5_fsm.vwf @@ -0,0 +1,973 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 10.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("clk") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("dealer_wins") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("done") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("hit") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("player_sum") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 6; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("player_sum[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "player_sum"; +} + +SIGNAL("player_sum[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "player_sum"; +} + +SIGNAL("player_sum[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "player_sum"; +} + +SIGNAL("player_sum[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "player_sum"; +} + +SIGNAL("player_sum[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "player_sum"; +} + +SIGNAL("player_sum[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "player_sum"; +} + +SIGNAL("player_wins") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("rst") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("sum") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 6; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("sum[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "sum"; +} + +SIGNAL("sum[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "sum"; +} + +SIGNAL("sum[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "sum"; +} + +SIGNAL("sum[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "sum"; +} + +SIGNAL("sum[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "sum"; +} + +SIGNAL("sum[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "sum"; +} + +SIGNAL("sum_out") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 6; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("sum_out[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "sum_out"; +} + +SIGNAL("sum_out[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "sum_out"; +} + +SIGNAL("sum_out[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "sum_out"; +} + +SIGNAL("sum_out[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "sum_out"; +} + +SIGNAL("sum_out[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "sum_out"; +} + +SIGNAL("sum_out[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "sum_out"; +} + +SIGNAL("turn") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("state_out") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 2; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("state_out[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "state_out"; +} + +SIGNAL("state_out[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "state_out"; +} + +TRANSITION_LIST("clk") +{ + NODE + { + REPEAT = 1; + NODE + { + REPEAT = 25; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + } + } +} + +TRANSITION_LIST("dealer_wins") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("done") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("hit") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("player_sum[5]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("player_sum[4]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 150.0; + LEVEL 0 FOR 70.0; + LEVEL 1 FOR 460.0; + LEVEL 0 FOR 210.0; + LEVEL 1 FOR 110.0; + } +} + +TRANSITION_LIST("player_sum[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 420.0; + LEVEL 1 FOR 170.0; + LEVEL 0 FOR 90.0; + LEVEL 1 FOR 210.0; + LEVEL 0 FOR 110.0; + } +} + +TRANSITION_LIST("player_sum[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 150.0; + LEVEL 0 FOR 180.0; + LEVEL 1 FOR 90.0; + LEVEL 0 FOR 170.0; + LEVEL 1 FOR 90.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 260.0; + } +} + +TRANSITION_LIST("player_sum[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 590.0; + LEVEL 1 FOR 90.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 150.0; + LEVEL 0 FOR 110.0; + } +} + +TRANSITION_LIST("player_sum[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 150.0; + LEVEL 0 FOR 530.0; + LEVEL 1 FOR 210.0; + LEVEL 0 FOR 110.0; + } +} + +TRANSITION_LIST("player_wins") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("rst") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 640.0; + LEVEL 1 FOR 130.0; + LEVEL 0 FOR 230.0; + } +} + +TRANSITION_LIST("sum[5]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("sum[4]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 210.0; + LEVEL 0 FOR 180.0; + LEVEL 1 FOR 90.0; + LEVEL 0 FOR 150.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 80.0; + } +} + +TRANSITION_LIST("sum[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 70.0; + LEVEL 0 FOR 210.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 270.0; + LEVEL 1 FOR 230.0; + } +} + +TRANSITION_LIST("sum[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 230.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 180.0; + LEVEL 1 FOR 240.0; + LEVEL 0 FOR 140.0; + } +} + +TRANSITION_LIST("sum[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 70.0; + LEVEL 1 FOR 90.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 90.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 90.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 50.0; + } +} + +TRANSITION_LIST("sum[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 210.0; + LEVEL 1 FOR 180.0; + LEVEL 0 FOR 90.0; + LEVEL 1 FOR 150.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 80.0; + } +} + +TRANSITION_LIST("sum_out[5]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("sum_out[4]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("sum_out[3]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("sum_out[2]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("sum_out[1]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("sum_out[0]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("turn") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 90.0; + LEVEL 1 FOR 340.0; + LEVEL 0 FOR 210.0; + LEVEL 1 FOR 90.0; + } +} + +TRANSITION_LIST("state_out[1]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("state_out[0]") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "clk"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "rst"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "turn"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "sum"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 3; + TREE_LEVEL = 0; + CHILDREN = 4, 5, 6, 7, 8, 9; +} + +DISPLAY_LINE +{ + CHANNEL = "sum[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "sum[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "sum[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 6; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "sum[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "sum[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "sum[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 9; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "sum_out"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 10; + TREE_LEVEL = 0; + CHILDREN = 11, 12, 13, 14, 15, 16; +} + +DISPLAY_LINE +{ + CHANNEL = "sum_out[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 11; + TREE_LEVEL = 1; + PARENT = 10; +} + +DISPLAY_LINE +{ + CHANNEL = "sum_out[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 12; + TREE_LEVEL = 1; + PARENT = 10; +} + +DISPLAY_LINE +{ + CHANNEL = "sum_out[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 13; + TREE_LEVEL = 1; + PARENT = 10; +} + +DISPLAY_LINE +{ + CHANNEL = "sum_out[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 14; + TREE_LEVEL = 1; + PARENT = 10; +} + +DISPLAY_LINE +{ + CHANNEL = "sum_out[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 15; + TREE_LEVEL = 1; + PARENT = 10; +} + +DISPLAY_LINE +{ + CHANNEL = "sum_out[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 16; + TREE_LEVEL = 1; + PARENT = 10; +} + +DISPLAY_LINE +{ + CHANNEL = "state_out"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 17; + TREE_LEVEL = 0; + CHILDREN = 18, 19; +} + +DISPLAY_LINE +{ + CHANNEL = "state_out[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 18; + TREE_LEVEL = 1; + PARENT = 17; +} + +DISPLAY_LINE +{ + CHANNEL = "state_out[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 19; + TREE_LEVEL = 1; + PARENT = 17; +} + +DISPLAY_LINE +{ + CHANNEL = "hit"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 20; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "done"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 21; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "player_sum"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 22; + TREE_LEVEL = 0; + CHILDREN = 23, 24, 25, 26, 27, 28; +} + +DISPLAY_LINE +{ + CHANNEL = "player_sum[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 23; + TREE_LEVEL = 1; + PARENT = 22; +} + +DISPLAY_LINE +{ + CHANNEL = "player_sum[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 24; + TREE_LEVEL = 1; + PARENT = 22; +} + +DISPLAY_LINE +{ + CHANNEL = "player_sum[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 25; + TREE_LEVEL = 1; + PARENT = 22; +} + +DISPLAY_LINE +{ + CHANNEL = "player_sum[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 26; + TREE_LEVEL = 1; + PARENT = 22; +} + +DISPLAY_LINE +{ + CHANNEL = "player_sum[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 27; + TREE_LEVEL = 1; + PARENT = 22; +} + +DISPLAY_LINE +{ + CHANNEL = "player_sum[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 28; + TREE_LEVEL = 1; + PARENT = 22; +} + +DISPLAY_LINE +{ + CHANNEL = "player_wins"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 29; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "dealer_wins"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 30; + TREE_LEVEL = 0; +} + +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/lab5/gA6_modulo_13.bdf b/lab5/gA6_modulo_13.bdf new file mode 100644 index 0000000..6b9d3ca --- /dev/null +++ b/lab5/gA6_modulo_13.bdf @@ -0,0 +1,444 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "graphic" (version "1.4")) +(pin + (input) + (rect 42 24 210 40) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "A[5..0]" (rect 5 0 38 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (output) + (rect 250 24 426 40) + (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) + (text "Amod13[3..0]" (rect 90 0 156 12)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) +) +(pin + (output) + (rect 248 56 424 72) + (text "OUTPUT" (rect 1 0 39 10)(font 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(pt 432 200) +) diff --git a/lab5/gA6_modulo_13.bsf b/lab5/gA6_modulo_13.bsf new file mode 100644 index 0000000..ed9f80e --- /dev/null +++ b/lab5/gA6_modulo_13.bsf @@ -0,0 +1,50 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 16 16 184 112) + (text "gA6_modulo_13" (rect 5 0 97 14)(font "Arial" (font_size 8))) + (text "inst" (rect 8 80 25 92)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "A[5..0]" (rect 0 0 37 14)(font "Arial" (font_size 8))) + (text "A[5..0]" (rect 21 27 58 41)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 168 32) + (output) + (text "Amod13[3..0]" (rect 0 0 75 14)(font "Arial" (font_size 8))) + (text "Amod13[3..0]" (rect 72 27 147 41)(font "Arial" (font_size 8))) + (line (pt 168 32)(pt 152 32)(line_width 3)) + ) + (port + (pt 168 48) + (output) + (text "Afloor13[3..0]" (rect 0 0 77 14)(font "Arial" (font_size 8))) + (text "Afloor13[3..0]" (rect 70 43 147 57)(font "Arial" (font_size 8))) + (line (pt 168 48)(pt 152 48)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 152 80)) + ) +) diff --git a/lab5/gA6_not6.bdf b/lab5/gA6_not6.bdf new file mode 100644 index 0000000..6117421 --- /dev/null +++ b/lab5/gA6_not6.bdf @@ -0,0 +1,263 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "graphic" (version "1.4")) +(pin + (input) + (rect 56 24 224 40) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "In[5..0]" (rect 5 0 40 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (output) + (rect 240 24 416 40) + (text "OUTPUT" (rect 1 0 39 10)(font "Arial" (font_size 6))) + (text "Out[5..0]" (rect 90 0 133 12)(font "Arial" )) + (pt 0 8) + (drawing + (line (pt 0 8)(pt 52 8)) + (line (pt 52 4)(pt 78 4)) + (line (pt 52 12)(pt 78 12)) + (line (pt 52 12)(pt 52 4)) + (line (pt 78 4)(pt 82 8)) + (line (pt 82 8)(pt 78 12)) + (line (pt 78 12)(pt 82 8)) + ) +) +(symbol + (rect 112 72 160 104) + (text "NOT" (rect 1 0 21 10)(font "Arial" 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13 25)(pt 31 16)) + (circle (rect 31 12 39 20)) + ) +) +(connector + (text "In[0]" (rect 56 80 78 92)(font "Arial" )) + (pt 112 88) + (pt 80 88) +) +(connector + (text "In[1]" (rect 53 120 75 132)(font "Arial" )) + (pt 80 128) + (pt 112 128) +) +(connector + (text "In[2]" (rect 53 160 75 172)(font "Arial" )) + (pt 112 168) + (pt 80 168) +) +(connector + (text "In[3]" (rect 246 80 268 92)(font "Arial" )) + (pt 304 88) + (pt 272 88) +) +(connector + (text "In[4]" (rect 248 120 270 132)(font "Arial" )) + (pt 304 128) + (pt 272 128) +) +(connector + (text "In[5]" (rect 243 160 265 172)(font "Arial" )) + (pt 304 168) + (pt 272 168) +) +(connector + (text "Out[0]" (rect 206 80 236 92)(font "Arial" )) + (pt 160 88) + (pt 200 88) +) +(connector + (text "Out[1]" (rect 205 120 235 132)(font "Arial" )) + (pt 160 128) + (pt 200 128) +) +(connector + (text "Out[2]" (rect 205 160 235 172)(font "Arial" )) + (pt 160 168) + (pt 200 168) +) +(connector + (text "Out[3]" (rect 398 80 428 92)(font "Arial" )) + (pt 352 88) + (pt 392 88) +) +(connector + (text "Out[4]" (rect 397 120 427 132)(font "Arial" )) + (pt 352 128) + (pt 392 128) +) +(connector + (text "Out[5]" (rect 403 160 433 172)(font "Arial" )) + (pt 352 168) + (pt 392 168) +) diff --git a/lab5/gA6_not6.bsf b/lab5/gA6_not6.bsf new file mode 100644 index 0000000..d7ec338 --- /dev/null +++ b/lab5/gA6_not6.bsf @@ -0,0 +1,43 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 64 64 192 136) + (text "gA6_not6" (rect 5 0 60 14)(font "Arial" (font_size 8))) + (text "inst" (rect 8 56 25 68)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "In[5..0]" (rect 0 0 37 14)(font "Arial" (font_size 8))) + (text "In[5..0]" (rect 21 27 58 41)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 128 32) + (output) + (text "Out[5..0]" (rect -8 0 40 14)(font "Arial" (font_size 8))) + (text "Out[5..0]" (rect 59 27 107 41)(font "Arial" (font_size 8))) + (line (pt 128 32)(pt 112 32)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 112 56)) + ) +) diff --git a/lab5/gA6_pop_enable.bsf b/lab5/gA6_pop_enable.bsf new file mode 100644 index 0000000..fc75447 --- /dev/null +++ b/lab5/gA6_pop_enable.bsf @@ -0,0 +1,50 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 192 96) + (text "gA6_pop_enable" (rect 5 0 73 12)(font "Arial" )) + (text "inst" (rect 8 64 20 76)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clk" (rect 0 0 10 12)(font "Arial" )) + (text "clk" (rect 21 27 31 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "N[5..0]" (rect 0 0 27 12)(font "Arial" )) + (text "N[5..0]" (rect 21 43 48 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 3)) + ) + (port + (pt 176 32) + (output) + (text "P_EN[51..0]" (rect 0 0 49 12)(font "Arial" )) + (text "P_EN[51..0]" (rect 106 27 155 39)(font "Arial" )) + (line (pt 176 32)(pt 160 32)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 160 64)(line_width 1)) + ) +) diff --git a/lab5/gA6_pop_enable.vhd b/lab5/gA6_pop_enable.vhd new file mode 100644 index 0000000..cc916bd --- /dev/null +++ b/lab5/gA6_pop_enable.vhd @@ -0,0 +1,41 @@ +-- entity name: gA6_pop_enable +-- +-- Copyright (C) 2017 Abbas Yadollahi - He Qian Wang +-- Version 1.0 +-- Author: Abbas Yadollahi (abbas.yadollahi@mail.mcgill.ca) +-- He Qian Wang (he.q.wang@mail.mcgill.ca) +-- Date: Oct/18/2017 + +library lpm; +library ieee; +use lpm.lpm_components.all; +use ieee.std_logic_1164.all; + +entity gA6_pop_enable is + port( + clk : std_logic; + N : in std_logic_vector(5 downto 0); + P_EN : out std_logic_vector(51 downto 0) + ); +end gA6_pop_enable; + +architecture lookup of gA6_pop_enable is + begin + + lookup_table : lpm_rom -- Use the altera rom library macrocell + generic map( + lpm_width => 52, -- The width of the word stored in each ROM location + lpm_widthad => 6, -- Sets the width of the ROM address bus + lpm_numwords => 64, -- Sets the number of words stored in the ROM + lpm_outdata => "UNREGISTERED", -- No register on the output + lpm_address_control => "REGISTERED", -- Register on the input + lpm_file => "gA6_popup_rom_data.mif" -- The ascii file containing the ROM data + ) + + port map( + inclock => clk, + address => N, + q => P_EN + ); + +end lookup; diff --git a/lab5/gA6_popup_rom_data.mif b/lab5/gA6_popup_rom_data.mif new file mode 100644 index 0000000..bff1ca1 --- /dev/null +++ b/lab5/gA6_popup_rom_data.mif @@ -0,0 +1,77 @@ +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- Quartus II generated Memory Initialization File (.mif) + +WIDTH=52; +DEPTH=64; + +ADDRESS_RADIX=UNS; +DATA_RADIX=BIN; + +CONTENT BEGIN + 0 : 1111111111111111111111111111111111111111111111111111; + 1 : 1111111111111111111111111111111111111111111111111110; + 2 : 1111111111111111111111111111111111111111111111111100; + 3 : 1111111111111111111111111111111111111111111111111000; + 4 : 1111111111111111111111111111111111111111111111110000; + 5 : 1111111111111111111111111111111111111111111111100000; + 6 : 1111111111111111111111111111111111111111111111000000; + 7 : 1111111111111111111111111111111111111111111110000000; + 8 : 1111111111111111111111111111111111111111111100000000; + 9 : 1111111111111111111111111111111111111111111000000000; + 10 : 1111111111111111111111111111111111111111110000000000; + 11 : 1111111111111111111111111111111111111111100000000000; + 12 : 1111111111111111111111111111111111111111000000000000; + 13 : 1111111111111111111111111111111111111110000000000000; + 14 : 1111111111111111111111111111111111111100000000000000; + 15 : 1111111111111111111111111111111111111000000000000000; + 16 : 1111111111111111111111111111111111110000000000000000; + 17 : 1111111111111111111111111111111111100000000000000000; + 18 : 1111111111111111111111111111111111000000000000000000; + 19 : 1111111111111111111111111111111110000000000000000000; + 20 : 1111111111111111111111111111111100000000000000000000; + 21 : 1111111111111111111111111111111000000000000000000000; + 22 : 1111111111111111111111111111110000000000000000000000; + 23 : 1111111111111111111111111111100000000000000000000000; + 24 : 1111111111111111111111111111000000000000000000000000; + 25 : 1111111111111111111111111110000000000000000000000000; + 26 : 1111111111111111111111111100000000000000000000000000; + 27 : 1111111111111111111111111000000000000000000000000000; + 28 : 1111111111111111111111110000000000000000000000000000; + 29 : 1111111111111111111111100000000000000000000000000000; + 30 : 1111111111111111111111000000000000000000000000000000; + 31 : 1111111111111111111110000000000000000000000000000000; + 32 : 1111111111111111111100000000000000000000000000000000; + 33 : 1111111111111111111000000000000000000000000000000000; + 34 : 1111111111111111110000000000000000000000000000000000; + 35 : 1111111111111111100000000000000000000000000000000000; + 36 : 1111111111111111000000000000000000000000000000000000; + 37 : 1111111111111110000000000000000000000000000000000000; + 38 : 1111111111111100000000000000000000000000000000000000; + 39 : 1111111111111000000000000000000000000000000000000000; + 40 : 1111111111110000000000000000000000000000000000000000; + 41 : 1111111111100000000000000000000000000000000000000000; + 42 : 1111111111000000000000000000000000000000000000000000; + 43 : 1111111110000000000000000000000000000000000000000000; + 44 : 1111111100000000000000000000000000000000000000000000; + 45 : 1111111000000000000000000000000000000000000000000000; + 46 : 1111110000000000000000000000000000000000000000000000; + 47 : 1111100000000000000000000000000000000000000000000000; + 48 : 1111000000000000000000000000000000000000000000000000; + 49 : 1110000000000000000000000000000000000000000000000000; + 50 : 1100000000000000000000000000000000000000000000000000; + 51 : 1000000000000000000000000000000000000000000000000000; + [52..63] : 0000000000000000000000000000000000000000000000000000; +END; diff --git a/lab5/gA6_rules.bsf b/lab5/gA6_rules.bsf new file mode 100644 index 0000000..d5d8f36 --- /dev/null +++ b/lab5/gA6_rules.bsf @@ -0,0 +1,78 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 240 160) + (text "gA6_rules" (rect 5 0 47 12)(font "Arial" )) + (text "inst" (rect 8 128 20 140)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clk" (rect 0 0 10 12)(font "Arial" )) + (text "clk" (rect 21 27 31 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "rst" (rect 0 0 10 12)(font "Arial" )) + (text "rst" (rect 21 43 31 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 0 64) + (input) + (text "enable" (rect 0 0 24 12)(font "Arial" )) + (text "enable" (rect 21 59 45 71)(font "Arial" )) + (line (pt 0 64)(pt 16 64)(line_width 1)) + ) + (port + (pt 0 80) + (input) + (text "new_card[5..0]" (rect 0 0 59 12)(font "Arial" )) + (text "new_card[5..0]" (rect 21 75 80 87)(font "Arial" )) + (line (pt 0 80)(pt 16 80)(line_width 3)) + ) + (port + (pt 0 96) + (input) + (text "hand_sum[5..0]" (rect 0 0 62 12)(font "Arial" )) + (text "hand_sum[5..0]" (rect 21 91 83 103)(font "Arial" )) + (line (pt 0 96)(pt 16 96)(line_width 3)) + ) + (port + (pt 224 32) + (output) + (text "legal_play" (rect 0 0 38 12)(font "Arial" )) + (text "legal_play" (rect 165 27 203 39)(font "Arial" )) + (line (pt 224 32)(pt 208 32)(line_width 1)) + ) + (port + (pt 224 48) + (output) + (text "new_total[5..0]" (rect 0 0 56 12)(font "Arial" )) + (text "new_total[5..0]" (rect 147 43 203 55)(font "Arial" )) + (line (pt 224 48)(pt 208 48)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 208 128)(line_width 1)) + ) +) diff --git a/lab5/gA6_rules.vhd b/lab5/gA6_rules.vhd new file mode 100644 index 0000000..b8fe6ea --- /dev/null +++ b/lab5/gA6_rules.vhd @@ -0,0 +1,85 @@ +-- entity name: gA6_rules +-- +-- Copyright (C) 2017 Abbas Yadollahi - He Qian Wang +-- Version 1.0 +-- Author: Abbas Yadollahi (abbas.yadollahi@mail.mcgill.ca) +-- He Qian Wang (he.q.wang@mail.mcgill.ca) +-- Date: Nov/17/2017 + +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity gA6_rules is + port( + --ace : in std_logic; + clk : in std_logic; + rst : in std_logic; + enable : in std_logic; + new_card : in std_logic_vector(5 downto 0); + hand_sum : in std_logic_vector(5 downto 0); + + --ace_out : out std_logic; + legal_play : out std_logic; + new_total : out std_logic_vector(5 downto 0) + ); +end gA6_rules; + +architecture behavior of gA6_rules is + begin + sum_cards: process(new_card, hand_sum) + + variable legal : std_logic; + variable new_ace : std_logic; + variable hand_ace : std_logic; + variable new_sum : unsigned(5 downto 0); + variable card_value : unsigned(5 downto 0); + + begin + if rst = '1' then + hand_ace := '0'; + elsif rising_edge(clk) then + new_ace := '0'; + if rst = '1' then + hand_ace := '0'; + --else + --hand_ace := ace; + end if; + + card_value := unsigned(new_card) mod 13 + 1; + + if card_value > 10 then + card_value := to_unsigned(10, 6); + elsif card_value = 1 then + new_ace := '1'; + card_value := to_unsigned(11, 6); + end if; + + new_sum := card_value + unsigned(hand_sum); + + if (new_sum > 21 and hand_ace = '1') then + hand_ace := '0'; + new_sum := new_sum - 10; + elsif (new_sum > 21 and new_ace = '1') then + new_ace := '0'; + new_sum := new_sum - 10; + end if; + + if new_ace = '1' then + hand_ace := '1'; + end if; + + if new_sum < 22 then + legal := '1'; + else + legal := '0'; + hand_ace := '0'; + end if; + + --ace_out <= hand_ace; + legal_play <= legal; + new_total <= std_logic_vector(new_sum); + end if; + end process; +end behavior; + diff --git a/lab5/gA6_rules.vhd.bak b/lab5/gA6_rules.vhd.bak new file mode 100644 index 0000000..9e5a6b7 --- /dev/null +++ b/lab5/gA6_rules.vhd.bak @@ -0,0 +1,10 @@ +-- entity name: gA6_rules +-- +-- Copyright (C) 2017 Abbas Yadollahi - He Qian Wang +-- Version 1.0 +-- Author: Abbas Yadollahi (abbas.yadollahi@mail.mcgill.ca) +-- He Qian Wang (he.q.wang@mail.mcgill.ca) +-- Date: Nov/17/2017 + +library ieee; +use ieee.std_logic_1164.all; diff --git a/lab5/gA6_stack52.bdf b/lab5/gA6_stack52.bdf new file mode 100644 index 0000000..caf40d3 --- /dev/null +++ b/lab5/gA6_stack52.bdf @@ -0,0 +1,15686 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "graphic" (version "1.4")) +(pin + (input) + (rect 400 64 568 80) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "data[5..0]" (rect 5 0 52 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) +) +(pin + (input) + (rect 400 88 568 104) + (text "INPUT" (rect 125 0 153 10)(font "Arial" (font_size 6))) + (text "mode[1..0]" (rect 5 0 58 12)(font "Arial" )) + (pt 168 8) + (drawing + (line (pt 84 12)(pt 109 12)) + (line (pt 84 4)(pt 109 4)) + (line (pt 113 8)(pt 168 8)) + (line (pt 84 12)(pt 84 4)) + (line (pt 109 4)(pt 113 8)) + (line (pt 109 12)(pt 113 8)) + ) + (text "VCC" (rect 128 7 148 17)(font "Arial" (font_size 6))) + (annotation_block (location)(rect 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+++ b/lab5/gA6_stack52.bsf @@ -0,0 +1,99 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 16 16 192 176) + (text "gA6_stack52" (rect 5 0 80 14)(font "Arial" (font_size 8))) + (text "inst" (rect 8 144 25 156)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "data[5..0]" (rect 0 0 53 14)(font "Arial" (font_size 8))) + (text "data[5..0]" (rect 21 27 74 41)(font "Arial" (font_size 8))) + (line (pt 0 32)(pt 16 32)(line_width 3)) + ) + (port + (pt 0 48) + (input) + (text "mode[1..0]" (rect 0 0 59 14)(font "Arial" (font_size 8))) + (text "mode[1..0]" (rect 21 43 80 57)(font "Arial" (font_size 8))) + (line (pt 0 48)(pt 16 48)(line_width 3)) + ) + (port + (pt 0 64) + (input) + (text "addr[5..0]" (rect 0 0 54 14)(font "Arial" (font_size 8))) + (text "addr[5..0]" (rect 21 59 75 73)(font "Arial" (font_size 8))) + (line (pt 0 64)(pt 16 64)(line_width 3)) + ) + (port + (pt 0 80) + (input) + (text "enable" (rect 0 0 37 14)(font "Arial" (font_size 8))) + (text "enable" (rect 21 75 58 89)(font "Arial" (font_size 8))) + (line (pt 0 80)(pt 16 80)) + ) + (port + (pt 0 96) + (input) + (text "rst" (rect 0 0 15 14)(font "Arial" (font_size 8))) + (text "rst" (rect 21 91 36 105)(font "Arial" (font_size 8))) + (line (pt 0 96)(pt 16 96)) + ) + (port + (pt 0 112) + (input) + (text "clk" (rect 0 0 15 14)(font "Arial" (font_size 8))) + (text "clk" (rect 21 107 36 121)(font "Arial" (font_size 8))) + (line (pt 0 112)(pt 16 112)) + ) + (port + (pt 176 32) + (output) + (text "value[5..0]" (rect 0 0 59 14)(font "Arial" (font_size 8))) + (text "value[5..0]" (rect 96 27 155 41)(font "Arial" (font_size 8))) + (line (pt 176 32)(pt 160 32)(line_width 3)) + ) + (port + (pt 176 48) + (output) + (text "num[5..0]" (rect 0 0 51 14)(font "Arial" (font_size 8))) + (text "num[5..0]" (rect 104 43 155 57)(font "Arial" (font_size 8))) + (line (pt 176 48)(pt 160 48)(line_width 3)) + ) + (port + (pt 176 64) + (output) + (text "empty" (rect 0 0 34 14)(font "Arial" (font_size 8))) + (text "empty" (rect 121 59 155 73)(font "Arial" (font_size 8))) + (line (pt 176 64)(pt 160 64)) + ) + (port + (pt 176 80) + (output) + (text "full" (rect 0 0 16 14)(font "Arial" (font_size 8))) + (text "full" (rect 139 75 155 89)(font "Arial" (font_size 8))) + (line (pt 176 80)(pt 160 80)) + ) + (drawing + (rectangle (rect 16 16 160 144)) + ) +) diff --git a/lab5/gA6_winner.bsf b/lab5/gA6_winner.bsf new file mode 100644 index 0000000..89f0fd8 --- /dev/null +++ b/lab5/gA6_winner.bsf @@ -0,0 +1,99 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.1")) +(symbol + (rect 16 16 256 160) + (text "gA6_winner" (rect 5 0 53 12)(font "Arial" )) + (text "inst" (rect 8 128 20 140)(font "Arial" )) + (port + (pt 0 32) + (input) + (text "clk" (rect 0 0 10 12)(font "Arial" )) + (text "clk" (rect 21 27 31 39)(font "Arial" )) + (line (pt 0 32)(pt 16 32)(line_width 1)) + ) + (port + (pt 0 48) + (input) + (text "enable" (rect 0 0 24 12)(font "Arial" )) + (text "enable" (rect 21 43 45 55)(font "Arial" )) + (line (pt 0 48)(pt 16 48)(line_width 1)) + ) + (port + (pt 0 64) + (input) + (text "player_sum[5..0]" (rect 0 0 68 12)(font "Arial" )) + (text "player_sum[5..0]" (rect 21 59 89 71)(font "Arial" )) + (line (pt 0 64)(pt 16 64)(line_width 3)) + ) + (port + (pt 0 80) + (input) + (text "dealer_sum[5..0]" (rect 0 0 67 12)(font "Arial" )) + (text "dealer_sum[5..0]" (rect 21 75 88 87)(font "Arial" )) + (line (pt 0 80)(pt 16 80)(line_width 3)) + ) + (port + (pt 240 32) + (output) + (text "player_wins" (rect 0 0 47 12)(font "Arial" )) + (text "player_wins" (rect 172 27 219 39)(font "Arial" )) + (line (pt 240 32)(pt 224 32)(line_width 1)) + ) + (port + (pt 240 48) + (output) + (text "dealer_wins" (rect 0 0 46 12)(font "Arial" )) + (text "dealer_wins" (rect 173 43 219 55)(font "Arial" )) + (line (pt 240 48)(pt 224 48)(line_width 1)) + ) + (port + (pt 240 64) + (output) + (text "led_display1[6..0]" (rect 0 0 67 12)(font "Arial" )) + (text "led_display1[6..0]" (rect 152 59 219 71)(font "Arial" )) + (line (pt 240 64)(pt 224 64)(line_width 3)) + ) + (port + (pt 240 80) + (output) + (text "led_display2[6..0]" (rect 0 0 68 12)(font "Arial" )) + (text "led_display2[6..0]" (rect 151 75 219 87)(font "Arial" )) + (line (pt 240 80)(pt 224 80)(line_width 3)) + ) + (port + (pt 240 96) + (output) + (text "led_display3[6..0]" (rect 0 0 68 12)(font "Arial" )) + (text "led_display3[6..0]" (rect 151 91 219 103)(font "Arial" )) + (line (pt 240 96)(pt 224 96)(line_width 3)) + ) + (port + (pt 240 112) + (output) + (text "led_display4[6..0]" (rect 0 0 69 12)(font "Arial" )) + (text "led_display4[6..0]" (rect 150 107 219 119)(font "Arial" )) + (line (pt 240 112)(pt 224 112)(line_width 3)) + ) + (drawing + (rectangle (rect 16 16 224 128)(line_width 1)) + ) +) diff --git a/lab5/gA6_winner.vhd b/lab5/gA6_winner.vhd new file mode 100644 index 0000000..fb1aa6a --- /dev/null +++ b/lab5/gA6_winner.vhd @@ -0,0 +1,76 @@ +-- entity name: gA6_winner +-- +-- Copyright (C) 2017 Abbas Yadollahi - He Qian Wang +-- Version 1.0 +-- Author: Abbas Yadollahi (abbas.yadollahi@mail.mcgill.ca) +-- He Qian Wang (he.q.wang@mail.mcgill.ca) +-- Date: Nov/29/2017 + +library ieee; +use ieee.numeric_std.all; +use ieee.std_logic_1164.all; + +entity gA6_winner is + port( + clk : in std_logic; + enable : in std_logic; + player_sum : in std_logic_vector(5 downto 0); + dealer_sum : in std_logic_vector(5 downto 0); + + player_wins : out std_logic; + dealer_wins : out std_logic; + led_display1 : out std_logic_vector(6 downto 0); + led_display2 : out std_logic_vector(6 downto 0); + led_display3 : out std_logic_vector(6 downto 0); + led_display4 : out std_logic_vector(6 downto 0) + ); +end gA6_winner; + +architecture behavior of gA6_winner is + begin + dealer: process(clk, player_sum, dealer_sum) + + variable p_win : std_logic; + variable d_win : std_logic; + + begin + if enable = '1' and rising_edge(clk) then + if unsigned(player_sum) > 21 then + p_win := '0'; + d_win := '1'; + elsif unsigned(dealer_sum) > 21 then + p_win := '1'; + d_win := '0'; + elsif unsigned(player_sum) > unsigned(dealer_sum) then + p_win := '1'; + d_win := '0'; + elsif unsigned(player_sum) < unsigned(dealer_sum) then + p_win := '0'; + d_win := '1'; + elsif unsigned(player_sum) = unsigned(dealer_sum) then + p_win := '1'; + d_win := '1'; + end if; + + player_wins <= p_win; + dealer_wins <= d_win; + + if p_win = '1' and d_win = '0' then + led_display1 <= "1000011"; + led_display2 <= "1100001"; + led_display3 <= "1111001"; + led_display4 <= "1001000"; + elsif p_win = '0' and d_win = '1' then + led_display1 <= "1000111"; + led_display2 <= "1000000"; + led_display3 <= "0010010"; + led_display4 <= "0000110"; + elsif p_win = '1' and d_win = '1' then + led_display1 <= "0001100"; + led_display2 <= "1000001"; + led_display3 <= "0010010"; + led_display4 <= "0001001"; + end if; + end if; + end process; +end behavior; \ No newline at end of file diff --git a/lab5/gA6_winner.vhd.bak b/lab5/gA6_winner.vhd.bak new file mode 100644 index 0000000..86f674f --- /dev/null +++ b/lab5/gA6_winner.vhd.bak @@ -0,0 +1,77 @@ +-- entity name: gA6_winner +-- +-- Copyright (C) 2017 Abbas Yadollahi - He Qian Wang +-- Version 1.0 +-- Author: Abbas Yadollahi (abbas.yadollahi@mail.mcgill.ca) +-- He Qian Wang (he.q.wang@mail.mcgill.ca) +-- Date: Nov/29/2017 + +library ieee; +use ieee.numeric_std.all; +use ieee.std_logic_1164.all; + +entity gA6_winner is + port( + clk : in std_logic; + player_sum : in std_logic_vector(5 downto 0); + dealer_sum : in std_logic_vector(5 downto 0); + + player_wins : out std_logic; + dealer_wins : out std_logic; + led_display1 : out std_logic_vector(6 downto 0); + led_display2 : out std_logic_vector(6 downto 0); + led_display3 : out std_logic_vector(6 downto 0); + led_display4 : out std_logic_vector(6 downto 0) + ); +end gA6_winner; + +architecture behavior of gA6_computer is + begin + dealer: process(clk, player_sum, dealer_sum) + + variable p_win : std_logic; + variable d_win : std_logic; + + begin + if rising_edge(clk) then + if unsigned(player_sum) > 21 then + p_win := '0'; + d_win := '1'; + elsif unsigned(dealer_sum) > 21 then + p_win := '1'; + d_win := '0'; + + + elsif unsigned(player_sum) > unsigned(dealer_sum) then + p_win := '1'; + d_win := '0'; + elsif unsigned(player_sum) < unsigned(dealer_sum) then + p_win := '0'; + d_win := '1'; + elsif unsigned(player_sum) = unsigned(dealer_sum) then + p_win := '1'; + d_win := '1'; + end if; + + player_wins <= p_win; + dealer_wins <= d_win; + + if p_win = '1' and d_win = '0' then + led_display1 <= "1000011"; + led_display2 <= "1100001"; + led_display3 <= "1111001"; + led_display4 <= "1001000"; + elsif p_win = '0' and d_win = '1' then + led_display1 <= "1000111"; + led_display2 <= "1000000"; + led_display3 <= "0010010"; + led_display4 <= "0000110"; + elsif p_win = '1' and d_win = '1' then + led_display1 <= "0001100"; + led_display2 <= "1000001"; + led_display3 <= "0010010"; + led_display4 <= "0001001"; + end if; + end if; + end process; +end behavior; \ No newline at end of file diff --git a/lab5/greybox_tmp/cbx_args.txt b/lab5/greybox_tmp/cbx_args.txt new file mode 100644 index 0000000..b76952d --- /dev/null +++ b/lab5/greybox_tmp/cbx_args.txt @@ -0,0 +1,11 @@ +LPM_SIZE=4 +LPM_TYPE=LPM_MUX +LPM_WIDTH=7 +LPM_WIDTHS=2 +DEVICE_FAMILY="Cyclone II" +data +data +data +data +sel +result diff --git a/lab5/incremental_db/README b/lab5/incremental_db/README new file mode 100644 index 0000000..6191fbe --- /dev/null +++ b/lab5/incremental_db/README @@ -0,0 +1,11 @@ +This folder contains data for incremental compilation. + +The compiled_partitions sub-folder contains previous compilation results for each partition. +As long as this folder is preserved, incremental compilation results from earlier compiles +can be re-used. To perform a clean compilation from source files for all partitions, both +the db and incremental_db folder should be removed. + +The imported_partitions sub-folder contains the last imported QXP for each imported partition. +As long as this folder is preserved, imported partitions will be automatically re-imported +when the db or incremental_db/compiled_partitions folders are removed. + diff --git a/lab5/incremental_db/compiled_partitions/gA6_lab5.db_info b/lab5/incremental_db/compiled_partitions/gA6_lab5.db_info new file mode 100644 index 0000000..fc77516 --- /dev/null +++ b/lab5/incremental_db/compiled_partitions/gA6_lab5.db_info @@ -0,0 +1,3 @@ +Quartus_Version = Version 13.0.0 Build 156 04/24/2013 SJ Web Edition +Version_Index = 302029824 +Creation_Time = Wed Nov 29 18:18:06 2017 diff --git a/lab5/incremental_db/compiled_partitions/gA6_lab5.root_partition.cmp.ammdb b/lab5/incremental_db/compiled_partitions/gA6_lab5.root_partition.cmp.ammdb new file mode 100644 index 0000000..f7455c4 Binary files /dev/null and b/lab5/incremental_db/compiled_partitions/gA6_lab5.root_partition.cmp.ammdb differ diff --git a/lab5/incremental_db/compiled_partitions/gA6_lab5.root_partition.cmp.cdb b/lab5/incremental_db/compiled_partitions/gA6_lab5.root_partition.cmp.cdb new file mode 100644 index 0000000..0e169e4 Binary files /dev/null and b/lab5/incremental_db/compiled_partitions/gA6_lab5.root_partition.cmp.cdb differ diff --git a/lab5/incremental_db/compiled_partitions/gA6_lab5.root_partition.cmp.dfp b/lab5/incremental_db/compiled_partitions/gA6_lab5.root_partition.cmp.dfp new file mode 100644 index 0000000..b1c67d6 Binary files /dev/null and b/lab5/incremental_db/compiled_partitions/gA6_lab5.root_partition.cmp.dfp differ diff --git a/lab5/incremental_db/compiled_partitions/gA6_lab5.root_partition.cmp.hdb b/lab5/incremental_db/compiled_partitions/gA6_lab5.root_partition.cmp.hdb new file mode 100644 index 0000000..cba82db Binary files /dev/null and b/lab5/incremental_db/compiled_partitions/gA6_lab5.root_partition.cmp.hdb differ diff --git a/lab5/incremental_db/compiled_partitions/gA6_lab5.root_partition.cmp.kpt b/lab5/incremental_db/compiled_partitions/gA6_lab5.root_partition.cmp.kpt new file mode 100644 index 0000000..96c4ab8 Binary files /dev/null and b/lab5/incremental_db/compiled_partitions/gA6_lab5.root_partition.cmp.kpt differ diff --git a/lab5/incremental_db/compiled_partitions/gA6_lab5.root_partition.cmp.logdb b/lab5/incremental_db/compiled_partitions/gA6_lab5.root_partition.cmp.logdb new file mode 100644 index 0000000..d45424f --- /dev/null +++ b/lab5/incremental_db/compiled_partitions/gA6_lab5.root_partition.cmp.logdb @@ -0,0 +1 @@ +v1 diff --git a/lab5/incremental_db/compiled_partitions/gA6_lab5.root_partition.cmp.rcfdb b/lab5/incremental_db/compiled_partitions/gA6_lab5.root_partition.cmp.rcfdb new file mode 100644 index 0000000..181a02a Binary files /dev/null and b/lab5/incremental_db/compiled_partitions/gA6_lab5.root_partition.cmp.rcfdb differ diff --git a/lab5/incremental_db/compiled_partitions/gA6_lab5.root_partition.map.cdb b/lab5/incremental_db/compiled_partitions/gA6_lab5.root_partition.map.cdb new file mode 100644 index 0000000..cbd73c3 Binary files /dev/null and b/lab5/incremental_db/compiled_partitions/gA6_lab5.root_partition.map.cdb differ diff --git a/lab5/incremental_db/compiled_partitions/gA6_lab5.root_partition.map.dpi b/lab5/incremental_db/compiled_partitions/gA6_lab5.root_partition.map.dpi new file mode 100644 index 0000000..c967294 Binary files /dev/null and b/lab5/incremental_db/compiled_partitions/gA6_lab5.root_partition.map.dpi differ diff --git a/lab5/incremental_db/compiled_partitions/gA6_lab5.root_partition.map.hbdb.cdb b/lab5/incremental_db/compiled_partitions/gA6_lab5.root_partition.map.hbdb.cdb new file mode 100644 index 0000000..dc2ead0 Binary files /dev/null and b/lab5/incremental_db/compiled_partitions/gA6_lab5.root_partition.map.hbdb.cdb differ diff --git a/lab5/incremental_db/compiled_partitions/gA6_lab5.root_partition.map.hbdb.hb_info b/lab5/incremental_db/compiled_partitions/gA6_lab5.root_partition.map.hbdb.hb_info new file mode 100644 index 0000000..8210c55 Binary files /dev/null and b/lab5/incremental_db/compiled_partitions/gA6_lab5.root_partition.map.hbdb.hb_info differ diff --git a/lab5/incremental_db/compiled_partitions/gA6_lab5.root_partition.map.hbdb.hdb b/lab5/incremental_db/compiled_partitions/gA6_lab5.root_partition.map.hbdb.hdb new file mode 100644 index 0000000..cc7c880 Binary files /dev/null and b/lab5/incremental_db/compiled_partitions/gA6_lab5.root_partition.map.hbdb.hdb differ diff --git a/lab5/incremental_db/compiled_partitions/gA6_lab5.root_partition.map.hbdb.sig b/lab5/incremental_db/compiled_partitions/gA6_lab5.root_partition.map.hbdb.sig new file mode 100644 index 0000000..7b7958d --- /dev/null +++ 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(font_size 8))) + (line (pt 0 728)(pt 64 728)(line_width 3)) + ) + (port + (pt 0 744) + (input) + (text "data7x[5..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data7x[5..0]" (rect 4 730 71 744)(font "Arial" (font_size 8))) + (line (pt 0 744)(pt 64 744)(line_width 3)) + ) + (port + (pt 0 760) + (input) + (text "data6x[5..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data6x[5..0]" (rect 4 746 71 760)(font "Arial" (font_size 8))) + (line (pt 0 760)(pt 64 760)(line_width 3)) + ) + (port + (pt 0 776) + (input) + (text "data5x[5..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data5x[5..0]" (rect 4 762 71 776)(font "Arial" (font_size 8))) + (line (pt 0 776)(pt 64 776)(line_width 3)) + ) + (port + (pt 0 792) + (input) + (text "data4x[5..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data4x[5..0]" (rect 4 778 71 792)(font "Arial" (font_size 8))) + (line (pt 0 792)(pt 64 792)(line_width 3)) + ) + (port + (pt 0 808) + (input) + (text "data3x[5..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data3x[5..0]" (rect 4 794 71 808)(font "Arial" (font_size 8))) + (line (pt 0 808)(pt 64 808)(line_width 3)) + ) + (port + (pt 0 824) + (input) + (text "data2x[5..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data2x[5..0]" (rect 4 810 71 824)(font "Arial" (font_size 8))) + (line (pt 0 824)(pt 64 824)(line_width 3)) + ) + (port + (pt 0 840) + (input) + (text "data1x[5..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data1x[5..0]" (rect 4 826 71 840)(font "Arial" (font_size 8))) + (line (pt 0 840)(pt 64 840)(line_width 3)) + ) + (port + (pt 0 856) + (input) + (text "data0x[5..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data0x[5..0]" (rect 4 842 71 856)(font "Arial" (font_size 8))) + (line (pt 0 856)(pt 64 856)(line_width 3)) + ) + (port + (pt 72 880) + (input) + (text "sel[5..0]" (rect 0 0 14 44)(font "Arial" (font_size 8))(vertical)) + (text "sel[5..0]" (rect 80 832 94 876)(font "Arial" (font_size 8))(vertical)) + (line (pt 72 880)(pt 72 872)(line_width 3)) + ) + (port + (pt 144 448) + (output) + (text "result[5..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "result[5..0]" (rect 90 434 150 448)(font "Arial" (font_size 8))) + (line (pt 144 448)(pt 80 448)(line_width 3)) + ) + (drawing + (line (pt 64 24)(pt 64 872)) + (line (pt 64 24)(pt 80 32)) + (line (pt 64 872)(pt 80 864)) + (line (pt 80 32)(pt 80 864)) + (line (pt 0 0)(pt 146 0)) + (line (pt 146 0)(pt 146 882)) + (line (pt 0 882)(pt 146 882)) + (line (pt 0 0)(pt 0 882)) + (line (pt 0 0)(pt 0 0)) + (line (pt 0 0)(pt 0 0)) + (line (pt 0 0)(pt 0 0)) + (line (pt 0 0)(pt 0 0)) + ) +) diff --git a/lab5/lpm_mux0.qip b/lab5/lpm_mux0.qip new file mode 100644 index 0000000..9a8f283 --- /dev/null +++ b/lab5/lpm_mux0.qip @@ -0,0 +1,5 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_MUX" +set_global_assignment -name IP_TOOL_VERSION "13.0" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux0.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.bsf"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux0.cmp"] diff --git a/lab5/lpm_mux0.vhd b/lab5/lpm_mux0.vhd new file mode 100644 index 0000000..ed23695 --- /dev/null +++ b/lab5/lpm_mux0.vhd @@ -0,0 +1,670 @@ +-- megafunction wizard: %LPM_MUX% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: LPM_MUX + +-- ============================================================ +-- File Name: lpm_mux0.vhd +-- Megafunction Name(s): +-- LPM_MUX +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.0.0 Build 156 04/24/2013 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.lpm_components.all; + +ENTITY lpm_mux0 IS + PORT + ( + data0x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data10x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data11x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data12x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data13x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data14x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data15x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data16x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data17x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data18x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data19x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data20x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data21x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data22x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data23x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data24x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data25x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data26x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data27x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data28x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data29x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data30x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data31x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data32x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data33x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data34x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data35x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data36x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data37x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data38x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data39x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data40x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data41x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data42x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data43x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data44x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data45x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data46x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data47x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data48x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data49x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data4x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data50x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data51x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data5x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data6x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data7x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data8x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + data9x : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR (5 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (5 DOWNTO 0) + ); +END lpm_mux0; + + +ARCHITECTURE SYN OF lpm_mux0 IS + +-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire2 : STD_LOGIC_2D (51 DOWNTO 0, 5 DOWNTO 0); + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire6 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire7 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire8 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire9 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire10 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire11 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire12 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire13 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire14 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire15 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire16 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire17 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire18 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire19 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire20 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire21 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire22 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire23 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire24 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire25 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire26 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire27 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire28 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire29 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire30 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire31 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire32 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire33 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire34 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire35 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire36 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire37 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire38 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire39 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire40 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire41 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire42 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire43 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire44 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire45 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire46 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire47 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire48 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire49 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire50 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire51 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire52 : STD_LOGIC_VECTOR (5 DOWNTO 0); + SIGNAL sub_wire53 : STD_LOGIC_VECTOR (5 DOWNTO 0); + +BEGIN + sub_wire53 <= data0x(5 DOWNTO 0); + sub_wire52 <= data1x(5 DOWNTO 0); + sub_wire51 <= data2x(5 DOWNTO 0); + sub_wire50 <= data3x(5 DOWNTO 0); + sub_wire49 <= data4x(5 DOWNTO 0); + sub_wire48 <= data5x(5 DOWNTO 0); + sub_wire47 <= data6x(5 DOWNTO 0); + sub_wire46 <= data7x(5 DOWNTO 0); + sub_wire45 <= data8x(5 DOWNTO 0); + sub_wire44 <= data9x(5 DOWNTO 0); + sub_wire43 <= data10x(5 DOWNTO 0); + sub_wire42 <= data11x(5 DOWNTO 0); + sub_wire41 <= data12x(5 DOWNTO 0); + sub_wire40 <= data13x(5 DOWNTO 0); + sub_wire39 <= data14x(5 DOWNTO 0); + sub_wire38 <= data15x(5 DOWNTO 0); + sub_wire37 <= data16x(5 DOWNTO 0); + sub_wire36 <= data17x(5 DOWNTO 0); + sub_wire35 <= data18x(5 DOWNTO 0); + sub_wire34 <= data19x(5 DOWNTO 0); + sub_wire33 <= data20x(5 DOWNTO 0); + sub_wire32 <= data21x(5 DOWNTO 0); + sub_wire31 <= data22x(5 DOWNTO 0); + sub_wire30 <= data23x(5 DOWNTO 0); + sub_wire29 <= data24x(5 DOWNTO 0); + sub_wire28 <= data25x(5 DOWNTO 0); + sub_wire27 <= data26x(5 DOWNTO 0); + sub_wire26 <= data27x(5 DOWNTO 0); + sub_wire25 <= data28x(5 DOWNTO 0); + sub_wire24 <= data29x(5 DOWNTO 0); + sub_wire23 <= data30x(5 DOWNTO 0); + sub_wire22 <= data31x(5 DOWNTO 0); + sub_wire21 <= data32x(5 DOWNTO 0); + sub_wire20 <= data33x(5 DOWNTO 0); + sub_wire19 <= data34x(5 DOWNTO 0); + sub_wire18 <= data35x(5 DOWNTO 0); + sub_wire17 <= data36x(5 DOWNTO 0); + sub_wire16 <= data37x(5 DOWNTO 0); + sub_wire15 <= data38x(5 DOWNTO 0); + sub_wire14 <= data39x(5 DOWNTO 0); + sub_wire13 <= data40x(5 DOWNTO 0); + sub_wire12 <= data41x(5 DOWNTO 0); + sub_wire11 <= data42x(5 DOWNTO 0); + sub_wire10 <= data43x(5 DOWNTO 0); + sub_wire9 <= data44x(5 DOWNTO 0); + sub_wire8 <= data45x(5 DOWNTO 0); + sub_wire7 <= data46x(5 DOWNTO 0); + sub_wire6 <= data47x(5 DOWNTO 0); + sub_wire5 <= data48x(5 DOWNTO 0); + sub_wire4 <= data49x(5 DOWNTO 0); + sub_wire3 <= data50x(5 DOWNTO 0); + result <= sub_wire0(5 DOWNTO 0); + sub_wire1 <= data51x(5 DOWNTO 0); + sub_wire2(51, 0) <= sub_wire1(0); + sub_wire2(51, 1) <= sub_wire1(1); + sub_wire2(51, 2) <= sub_wire1(2); + sub_wire2(51, 3) <= sub_wire1(3); + sub_wire2(51, 4) <= sub_wire1(4); + sub_wire2(51, 5) <= sub_wire1(5); + sub_wire2(50, 0) <= sub_wire3(0); + sub_wire2(50, 1) <= sub_wire3(1); + sub_wire2(50, 2) <= sub_wire3(2); + sub_wire2(50, 3) <= sub_wire3(3); + sub_wire2(50, 4) <= sub_wire3(4); + sub_wire2(50, 5) <= sub_wire3(5); + sub_wire2(49, 0) <= sub_wire4(0); + sub_wire2(49, 1) <= sub_wire4(1); + sub_wire2(49, 2) <= sub_wire4(2); + sub_wire2(49, 3) <= sub_wire4(3); + sub_wire2(49, 4) <= sub_wire4(4); + sub_wire2(49, 5) <= sub_wire4(5); + sub_wire2(48, 0) <= sub_wire5(0); + sub_wire2(48, 1) <= sub_wire5(1); + sub_wire2(48, 2) <= sub_wire5(2); + sub_wire2(48, 3) <= sub_wire5(3); + sub_wire2(48, 4) <= sub_wire5(4); + sub_wire2(48, 5) <= sub_wire5(5); + sub_wire2(47, 0) <= sub_wire6(0); + sub_wire2(47, 1) <= sub_wire6(1); + sub_wire2(47, 2) <= sub_wire6(2); + sub_wire2(47, 3) <= sub_wire6(3); + sub_wire2(47, 4) <= sub_wire6(4); + sub_wire2(47, 5) <= sub_wire6(5); + sub_wire2(46, 0) <= sub_wire7(0); + sub_wire2(46, 1) <= sub_wire7(1); + sub_wire2(46, 2) <= sub_wire7(2); + sub_wire2(46, 3) <= sub_wire7(3); + sub_wire2(46, 4) <= sub_wire7(4); + sub_wire2(46, 5) <= sub_wire7(5); + sub_wire2(45, 0) <= sub_wire8(0); + sub_wire2(45, 1) <= sub_wire8(1); + sub_wire2(45, 2) <= sub_wire8(2); + sub_wire2(45, 3) <= sub_wire8(3); + sub_wire2(45, 4) <= sub_wire8(4); + sub_wire2(45, 5) <= sub_wire8(5); + sub_wire2(44, 0) <= sub_wire9(0); + sub_wire2(44, 1) <= sub_wire9(1); + sub_wire2(44, 2) <= sub_wire9(2); + sub_wire2(44, 3) <= sub_wire9(3); + sub_wire2(44, 4) <= sub_wire9(4); + sub_wire2(44, 5) <= sub_wire9(5); + sub_wire2(43, 0) <= sub_wire10(0); + sub_wire2(43, 1) <= sub_wire10(1); + sub_wire2(43, 2) <= sub_wire10(2); + sub_wire2(43, 3) <= sub_wire10(3); + sub_wire2(43, 4) <= sub_wire10(4); + sub_wire2(43, 5) <= sub_wire10(5); + sub_wire2(42, 0) <= sub_wire11(0); + sub_wire2(42, 1) <= sub_wire11(1); + sub_wire2(42, 2) <= sub_wire11(2); + sub_wire2(42, 3) <= sub_wire11(3); + sub_wire2(42, 4) <= sub_wire11(4); + sub_wire2(42, 5) <= sub_wire11(5); + sub_wire2(41, 0) <= sub_wire12(0); + sub_wire2(41, 1) <= sub_wire12(1); + sub_wire2(41, 2) <= sub_wire12(2); + sub_wire2(41, 3) <= sub_wire12(3); + sub_wire2(41, 4) <= sub_wire12(4); + sub_wire2(41, 5) <= sub_wire12(5); + sub_wire2(40, 0) <= sub_wire13(0); + sub_wire2(40, 1) <= sub_wire13(1); + sub_wire2(40, 2) <= sub_wire13(2); + sub_wire2(40, 3) <= sub_wire13(3); + sub_wire2(40, 4) <= sub_wire13(4); + sub_wire2(40, 5) <= sub_wire13(5); + sub_wire2(39, 0) <= sub_wire14(0); + sub_wire2(39, 1) <= sub_wire14(1); + sub_wire2(39, 2) <= sub_wire14(2); + sub_wire2(39, 3) <= sub_wire14(3); + sub_wire2(39, 4) <= sub_wire14(4); + sub_wire2(39, 5) <= sub_wire14(5); + sub_wire2(38, 0) <= sub_wire15(0); + sub_wire2(38, 1) <= sub_wire15(1); + sub_wire2(38, 2) <= sub_wire15(2); + sub_wire2(38, 3) <= sub_wire15(3); + sub_wire2(38, 4) <= sub_wire15(4); + sub_wire2(38, 5) <= sub_wire15(5); + sub_wire2(37, 0) <= sub_wire16(0); + sub_wire2(37, 1) <= sub_wire16(1); + sub_wire2(37, 2) <= sub_wire16(2); + sub_wire2(37, 3) <= sub_wire16(3); + sub_wire2(37, 4) <= sub_wire16(4); + sub_wire2(37, 5) <= sub_wire16(5); + sub_wire2(36, 0) <= sub_wire17(0); + sub_wire2(36, 1) <= sub_wire17(1); + sub_wire2(36, 2) <= sub_wire17(2); + sub_wire2(36, 3) <= sub_wire17(3); + sub_wire2(36, 4) <= sub_wire17(4); + sub_wire2(36, 5) <= sub_wire17(5); + sub_wire2(35, 0) <= sub_wire18(0); + sub_wire2(35, 1) <= sub_wire18(1); + sub_wire2(35, 2) <= sub_wire18(2); + sub_wire2(35, 3) <= sub_wire18(3); + sub_wire2(35, 4) <= sub_wire18(4); + sub_wire2(35, 5) <= sub_wire18(5); + sub_wire2(34, 0) <= sub_wire19(0); + sub_wire2(34, 1) <= sub_wire19(1); + sub_wire2(34, 2) <= sub_wire19(2); + sub_wire2(34, 3) <= sub_wire19(3); + sub_wire2(34, 4) <= sub_wire19(4); + sub_wire2(34, 5) <= sub_wire19(5); + sub_wire2(33, 0) <= sub_wire20(0); + sub_wire2(33, 1) <= sub_wire20(1); + sub_wire2(33, 2) <= sub_wire20(2); + sub_wire2(33, 3) <= sub_wire20(3); + sub_wire2(33, 4) <= sub_wire20(4); + sub_wire2(33, 5) <= sub_wire20(5); + sub_wire2(32, 0) <= sub_wire21(0); + sub_wire2(32, 1) <= sub_wire21(1); + sub_wire2(32, 2) <= sub_wire21(2); + sub_wire2(32, 3) <= sub_wire21(3); + sub_wire2(32, 4) <= sub_wire21(4); + sub_wire2(32, 5) <= sub_wire21(5); + sub_wire2(31, 0) <= sub_wire22(0); + sub_wire2(31, 1) <= sub_wire22(1); + sub_wire2(31, 2) <= sub_wire22(2); + sub_wire2(31, 3) <= sub_wire22(3); + sub_wire2(31, 4) <= sub_wire22(4); + sub_wire2(31, 5) <= sub_wire22(5); + sub_wire2(30, 0) <= sub_wire23(0); + sub_wire2(30, 1) <= sub_wire23(1); + sub_wire2(30, 2) <= sub_wire23(2); + sub_wire2(30, 3) <= sub_wire23(3); + sub_wire2(30, 4) <= sub_wire23(4); + sub_wire2(30, 5) <= sub_wire23(5); + sub_wire2(29, 0) <= sub_wire24(0); + sub_wire2(29, 1) <= sub_wire24(1); + sub_wire2(29, 2) <= sub_wire24(2); + sub_wire2(29, 3) <= sub_wire24(3); + sub_wire2(29, 4) <= sub_wire24(4); + sub_wire2(29, 5) <= sub_wire24(5); + sub_wire2(28, 0) <= sub_wire25(0); + sub_wire2(28, 1) <= sub_wire25(1); + sub_wire2(28, 2) <= sub_wire25(2); + sub_wire2(28, 3) <= sub_wire25(3); + sub_wire2(28, 4) <= sub_wire25(4); + sub_wire2(28, 5) <= sub_wire25(5); + sub_wire2(27, 0) <= sub_wire26(0); + sub_wire2(27, 1) <= sub_wire26(1); + sub_wire2(27, 2) <= sub_wire26(2); + sub_wire2(27, 3) <= sub_wire26(3); + sub_wire2(27, 4) <= sub_wire26(4); + sub_wire2(27, 5) <= sub_wire26(5); + sub_wire2(26, 0) <= sub_wire27(0); + sub_wire2(26, 1) <= sub_wire27(1); + sub_wire2(26, 2) <= sub_wire27(2); + sub_wire2(26, 3) <= sub_wire27(3); + sub_wire2(26, 4) <= sub_wire27(4); + sub_wire2(26, 5) <= sub_wire27(5); + sub_wire2(25, 0) <= sub_wire28(0); + sub_wire2(25, 1) <= sub_wire28(1); + sub_wire2(25, 2) <= sub_wire28(2); + sub_wire2(25, 3) <= sub_wire28(3); + sub_wire2(25, 4) <= sub_wire28(4); + sub_wire2(25, 5) <= sub_wire28(5); + sub_wire2(24, 0) <= sub_wire29(0); + sub_wire2(24, 1) <= sub_wire29(1); + sub_wire2(24, 2) <= sub_wire29(2); + sub_wire2(24, 3) <= sub_wire29(3); + sub_wire2(24, 4) <= sub_wire29(4); + sub_wire2(24, 5) <= sub_wire29(5); + sub_wire2(23, 0) <= sub_wire30(0); + sub_wire2(23, 1) <= sub_wire30(1); + sub_wire2(23, 2) <= sub_wire30(2); + sub_wire2(23, 3) <= sub_wire30(3); + sub_wire2(23, 4) <= sub_wire30(4); + sub_wire2(23, 5) <= sub_wire30(5); + sub_wire2(22, 0) <= sub_wire31(0); + sub_wire2(22, 1) <= sub_wire31(1); + sub_wire2(22, 2) <= sub_wire31(2); + sub_wire2(22, 3) <= sub_wire31(3); + sub_wire2(22, 4) <= sub_wire31(4); + sub_wire2(22, 5) <= sub_wire31(5); + sub_wire2(21, 0) <= sub_wire32(0); + sub_wire2(21, 1) <= sub_wire32(1); + sub_wire2(21, 2) <= sub_wire32(2); + sub_wire2(21, 3) <= sub_wire32(3); + sub_wire2(21, 4) <= sub_wire32(4); + sub_wire2(21, 5) <= sub_wire32(5); + sub_wire2(20, 0) <= sub_wire33(0); + sub_wire2(20, 1) <= sub_wire33(1); + sub_wire2(20, 2) <= sub_wire33(2); + sub_wire2(20, 3) <= sub_wire33(3); + sub_wire2(20, 4) <= sub_wire33(4); + sub_wire2(20, 5) <= sub_wire33(5); + sub_wire2(19, 0) <= sub_wire34(0); + sub_wire2(19, 1) <= sub_wire34(1); + sub_wire2(19, 2) <= sub_wire34(2); + sub_wire2(19, 3) <= sub_wire34(3); + sub_wire2(19, 4) <= sub_wire34(4); + sub_wire2(19, 5) <= sub_wire34(5); + sub_wire2(18, 0) <= sub_wire35(0); + sub_wire2(18, 1) <= sub_wire35(1); + sub_wire2(18, 2) <= sub_wire35(2); + sub_wire2(18, 3) <= sub_wire35(3); + sub_wire2(18, 4) <= sub_wire35(4); + sub_wire2(18, 5) <= sub_wire35(5); + sub_wire2(17, 0) <= sub_wire36(0); + sub_wire2(17, 1) <= sub_wire36(1); + sub_wire2(17, 2) <= sub_wire36(2); + sub_wire2(17, 3) <= sub_wire36(3); + sub_wire2(17, 4) <= sub_wire36(4); + sub_wire2(17, 5) <= sub_wire36(5); + sub_wire2(16, 0) <= sub_wire37(0); + sub_wire2(16, 1) <= sub_wire37(1); + sub_wire2(16, 2) <= sub_wire37(2); + sub_wire2(16, 3) <= sub_wire37(3); + sub_wire2(16, 4) <= sub_wire37(4); + sub_wire2(16, 5) <= sub_wire37(5); + sub_wire2(15, 0) <= sub_wire38(0); + sub_wire2(15, 1) <= sub_wire38(1); + sub_wire2(15, 2) <= sub_wire38(2); + sub_wire2(15, 3) <= sub_wire38(3); + sub_wire2(15, 4) <= sub_wire38(4); + sub_wire2(15, 5) <= sub_wire38(5); + sub_wire2(14, 0) <= sub_wire39(0); + sub_wire2(14, 1) <= sub_wire39(1); + sub_wire2(14, 2) <= sub_wire39(2); + sub_wire2(14, 3) <= sub_wire39(3); + sub_wire2(14, 4) <= sub_wire39(4); + sub_wire2(14, 5) <= sub_wire39(5); + sub_wire2(13, 0) <= sub_wire40(0); + sub_wire2(13, 1) <= sub_wire40(1); + sub_wire2(13, 2) <= sub_wire40(2); + sub_wire2(13, 3) <= sub_wire40(3); + sub_wire2(13, 4) <= sub_wire40(4); + sub_wire2(13, 5) <= sub_wire40(5); + sub_wire2(12, 0) <= sub_wire41(0); + sub_wire2(12, 1) <= sub_wire41(1); + sub_wire2(12, 2) <= sub_wire41(2); + sub_wire2(12, 3) <= sub_wire41(3); + sub_wire2(12, 4) <= sub_wire41(4); + sub_wire2(12, 5) <= sub_wire41(5); + sub_wire2(11, 0) <= sub_wire42(0); + sub_wire2(11, 1) <= sub_wire42(1); + sub_wire2(11, 2) <= sub_wire42(2); + sub_wire2(11, 3) <= sub_wire42(3); + sub_wire2(11, 4) <= sub_wire42(4); + sub_wire2(11, 5) <= sub_wire42(5); + sub_wire2(10, 0) <= sub_wire43(0); + sub_wire2(10, 1) <= sub_wire43(1); + sub_wire2(10, 2) <= sub_wire43(2); + sub_wire2(10, 3) <= sub_wire43(3); + sub_wire2(10, 4) <= sub_wire43(4); + sub_wire2(10, 5) <= sub_wire43(5); + sub_wire2(9, 0) <= sub_wire44(0); + sub_wire2(9, 1) <= sub_wire44(1); + sub_wire2(9, 2) <= sub_wire44(2); + sub_wire2(9, 3) <= sub_wire44(3); + sub_wire2(9, 4) <= sub_wire44(4); + sub_wire2(9, 5) <= sub_wire44(5); + sub_wire2(8, 0) <= sub_wire45(0); + sub_wire2(8, 1) <= sub_wire45(1); + sub_wire2(8, 2) <= sub_wire45(2); + sub_wire2(8, 3) <= sub_wire45(3); + sub_wire2(8, 4) <= sub_wire45(4); + sub_wire2(8, 5) <= sub_wire45(5); + sub_wire2(7, 0) <= sub_wire46(0); + sub_wire2(7, 1) <= sub_wire46(1); + sub_wire2(7, 2) <= sub_wire46(2); + sub_wire2(7, 3) <= sub_wire46(3); + sub_wire2(7, 4) <= sub_wire46(4); + sub_wire2(7, 5) <= sub_wire46(5); + sub_wire2(6, 0) <= sub_wire47(0); + sub_wire2(6, 1) <= sub_wire47(1); + sub_wire2(6, 2) <= sub_wire47(2); + sub_wire2(6, 3) <= sub_wire47(3); + sub_wire2(6, 4) <= sub_wire47(4); + sub_wire2(6, 5) <= sub_wire47(5); + sub_wire2(5, 0) <= sub_wire48(0); + sub_wire2(5, 1) <= sub_wire48(1); + sub_wire2(5, 2) <= sub_wire48(2); + sub_wire2(5, 3) <= sub_wire48(3); + sub_wire2(5, 4) <= sub_wire48(4); + sub_wire2(5, 5) <= sub_wire48(5); + sub_wire2(4, 0) <= sub_wire49(0); + sub_wire2(4, 1) <= sub_wire49(1); + sub_wire2(4, 2) <= sub_wire49(2); + sub_wire2(4, 3) <= sub_wire49(3); + sub_wire2(4, 4) <= sub_wire49(4); + sub_wire2(4, 5) <= sub_wire49(5); + sub_wire2(3, 0) <= sub_wire50(0); + sub_wire2(3, 1) <= sub_wire50(1); + sub_wire2(3, 2) <= sub_wire50(2); + sub_wire2(3, 3) <= sub_wire50(3); + sub_wire2(3, 4) <= sub_wire50(4); + sub_wire2(3, 5) <= sub_wire50(5); + sub_wire2(2, 0) <= sub_wire51(0); + sub_wire2(2, 1) <= sub_wire51(1); + sub_wire2(2, 2) <= sub_wire51(2); + sub_wire2(2, 3) <= sub_wire51(3); + sub_wire2(2, 4) <= sub_wire51(4); + sub_wire2(2, 5) <= sub_wire51(5); + sub_wire2(1, 0) <= sub_wire52(0); + sub_wire2(1, 1) <= sub_wire52(1); + sub_wire2(1, 2) <= sub_wire52(2); + sub_wire2(1, 3) <= sub_wire52(3); + sub_wire2(1, 4) <= sub_wire52(4); + sub_wire2(1, 5) <= sub_wire52(5); + sub_wire2(0, 0) <= sub_wire53(0); + sub_wire2(0, 1) <= sub_wire53(1); + sub_wire2(0, 2) <= sub_wire53(2); + sub_wire2(0, 3) <= sub_wire53(3); + sub_wire2(0, 4) <= sub_wire53(4); + sub_wire2(0, 5) <= sub_wire53(5); + + LPM_MUX_component : LPM_MUX + GENERIC MAP ( + lpm_size => 52, + lpm_type => "LPM_MUX", + lpm_width => 6, + lpm_widths => 6 + ) + PORT MAP ( + data => sub_wire2, + sel => sel, + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: new_diagram STRING "1" +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "52" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "6" +-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "6" +-- Retrieval info: USED_PORT: data0x 0 0 6 0 INPUT NODEFVAL "data0x[5..0]" +-- Retrieval info: USED_PORT: data10x 0 0 6 0 INPUT NODEFVAL "data10x[5..0]" +-- Retrieval info: USED_PORT: data11x 0 0 6 0 INPUT NODEFVAL "data11x[5..0]" +-- Retrieval info: USED_PORT: data12x 0 0 6 0 INPUT NODEFVAL "data12x[5..0]" +-- Retrieval info: USED_PORT: data13x 0 0 6 0 INPUT NODEFVAL "data13x[5..0]" +-- Retrieval info: USED_PORT: data14x 0 0 6 0 INPUT NODEFVAL "data14x[5..0]" +-- Retrieval info: USED_PORT: data15x 0 0 6 0 INPUT NODEFVAL "data15x[5..0]" +-- Retrieval info: USED_PORT: data16x 0 0 6 0 INPUT NODEFVAL "data16x[5..0]" +-- Retrieval info: USED_PORT: data17x 0 0 6 0 INPUT NODEFVAL "data17x[5..0]" +-- Retrieval info: USED_PORT: data18x 0 0 6 0 INPUT NODEFVAL "data18x[5..0]" +-- Retrieval info: USED_PORT: data19x 0 0 6 0 INPUT NODEFVAL "data19x[5..0]" +-- Retrieval info: USED_PORT: data1x 0 0 6 0 INPUT NODEFVAL "data1x[5..0]" +-- Retrieval info: USED_PORT: data20x 0 0 6 0 INPUT NODEFVAL "data20x[5..0]" +-- Retrieval info: USED_PORT: data21x 0 0 6 0 INPUT NODEFVAL "data21x[5..0]" +-- Retrieval info: USED_PORT: data22x 0 0 6 0 INPUT NODEFVAL "data22x[5..0]" +-- Retrieval info: USED_PORT: data23x 0 0 6 0 INPUT NODEFVAL "data23x[5..0]" +-- Retrieval info: USED_PORT: data24x 0 0 6 0 INPUT NODEFVAL "data24x[5..0]" +-- Retrieval info: USED_PORT: data25x 0 0 6 0 INPUT NODEFVAL "data25x[5..0]" +-- Retrieval info: USED_PORT: data26x 0 0 6 0 INPUT NODEFVAL "data26x[5..0]" +-- Retrieval info: USED_PORT: data27x 0 0 6 0 INPUT NODEFVAL "data27x[5..0]" +-- Retrieval info: USED_PORT: data28x 0 0 6 0 INPUT NODEFVAL "data28x[5..0]" +-- Retrieval info: USED_PORT: data29x 0 0 6 0 INPUT NODEFVAL "data29x[5..0]" +-- Retrieval info: USED_PORT: data2x 0 0 6 0 INPUT NODEFVAL "data2x[5..0]" +-- Retrieval info: USED_PORT: data30x 0 0 6 0 INPUT NODEFVAL "data30x[5..0]" +-- Retrieval info: USED_PORT: data31x 0 0 6 0 INPUT NODEFVAL "data31x[5..0]" +-- Retrieval info: USED_PORT: data32x 0 0 6 0 INPUT NODEFVAL "data32x[5..0]" +-- Retrieval info: USED_PORT: data33x 0 0 6 0 INPUT NODEFVAL "data33x[5..0]" +-- Retrieval info: USED_PORT: data34x 0 0 6 0 INPUT NODEFVAL "data34x[5..0]" +-- Retrieval info: USED_PORT: data35x 0 0 6 0 INPUT NODEFVAL "data35x[5..0]" +-- Retrieval info: USED_PORT: data36x 0 0 6 0 INPUT NODEFVAL "data36x[5..0]" +-- Retrieval info: USED_PORT: data37x 0 0 6 0 INPUT NODEFVAL "data37x[5..0]" +-- Retrieval info: USED_PORT: data38x 0 0 6 0 INPUT NODEFVAL "data38x[5..0]" +-- Retrieval info: USED_PORT: data39x 0 0 6 0 INPUT NODEFVAL "data39x[5..0]" +-- Retrieval info: USED_PORT: data3x 0 0 6 0 INPUT NODEFVAL "data3x[5..0]" +-- Retrieval info: USED_PORT: data40x 0 0 6 0 INPUT NODEFVAL "data40x[5..0]" +-- Retrieval info: USED_PORT: data41x 0 0 6 0 INPUT NODEFVAL "data41x[5..0]" +-- Retrieval info: USED_PORT: data42x 0 0 6 0 INPUT NODEFVAL "data42x[5..0]" +-- Retrieval info: USED_PORT: data43x 0 0 6 0 INPUT NODEFVAL "data43x[5..0]" +-- Retrieval info: USED_PORT: data44x 0 0 6 0 INPUT NODEFVAL "data44x[5..0]" +-- Retrieval info: USED_PORT: data45x 0 0 6 0 INPUT NODEFVAL "data45x[5..0]" +-- Retrieval info: USED_PORT: data46x 0 0 6 0 INPUT NODEFVAL "data46x[5..0]" +-- Retrieval info: USED_PORT: data47x 0 0 6 0 INPUT NODEFVAL "data47x[5..0]" +-- Retrieval info: USED_PORT: data48x 0 0 6 0 INPUT NODEFVAL "data48x[5..0]" +-- Retrieval info: USED_PORT: data49x 0 0 6 0 INPUT NODEFVAL "data49x[5..0]" +-- Retrieval info: USED_PORT: data4x 0 0 6 0 INPUT NODEFVAL "data4x[5..0]" +-- Retrieval info: USED_PORT: data50x 0 0 6 0 INPUT NODEFVAL "data50x[5..0]" +-- Retrieval info: USED_PORT: data51x 0 0 6 0 INPUT NODEFVAL "data51x[5..0]" +-- Retrieval info: USED_PORT: data5x 0 0 6 0 INPUT NODEFVAL "data5x[5..0]" +-- Retrieval info: USED_PORT: data6x 0 0 6 0 INPUT NODEFVAL "data6x[5..0]" +-- Retrieval info: USED_PORT: data7x 0 0 6 0 INPUT NODEFVAL "data7x[5..0]" +-- Retrieval info: USED_PORT: data8x 0 0 6 0 INPUT NODEFVAL "data8x[5..0]" +-- Retrieval info: USED_PORT: data9x 0 0 6 0 INPUT NODEFVAL "data9x[5..0]" +-- Retrieval info: USED_PORT: result 0 0 6 0 OUTPUT NODEFVAL "result[5..0]" +-- Retrieval info: USED_PORT: sel 0 0 6 0 INPUT NODEFVAL "sel[5..0]" +-- Retrieval info: CONNECT: @data 1 0 6 0 data0x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 10 6 0 data10x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 11 6 0 data11x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 12 6 0 data12x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 13 6 0 data13x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 14 6 0 data14x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 15 6 0 data15x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 16 6 0 data16x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 17 6 0 data17x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 18 6 0 data18x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 19 6 0 data19x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 1 6 0 data1x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 20 6 0 data20x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 21 6 0 data21x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 22 6 0 data22x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 23 6 0 data23x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 24 6 0 data24x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 25 6 0 data25x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 26 6 0 data26x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 27 6 0 data27x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 28 6 0 data28x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 29 6 0 data29x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 2 6 0 data2x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 30 6 0 data30x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 31 6 0 data31x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 32 6 0 data32x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 33 6 0 data33x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 34 6 0 data34x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 35 6 0 data35x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 36 6 0 data36x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 37 6 0 data37x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 38 6 0 data38x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 39 6 0 data39x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 3 6 0 data3x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 40 6 0 data40x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 41 6 0 data41x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 42 6 0 data42x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 43 6 0 data43x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 44 6 0 data44x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 45 6 0 data45x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 46 6 0 data46x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 47 6 0 data47x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 48 6 0 data48x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 49 6 0 data49x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 4 6 0 data4x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 50 6 0 data50x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 51 6 0 data51x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 5 6 0 data5x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 6 6 0 data6x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 7 6 0 data7x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 8 6 0 data8x 0 0 6 0 +-- Retrieval info: CONNECT: @data 1 9 6 0 data9x 0 0 6 0 +-- Retrieval info: CONNECT: @sel 0 0 6 0 sel 0 0 6 0 +-- Retrieval info: CONNECT: result 0 0 6 0 @result 0 0 6 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux0_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/lab5/lpm_mux1.bsf b/lab5/lpm_mux1.bsf new file mode 100644 index 0000000..d7d4c8c --- /dev/null +++ b/lab5/lpm_mux1.bsf @@ -0,0 +1,82 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ +(header "symbol" (version "1.2")) +(symbol + (rect 0 0 144 112) + (text "lpm_mux1" (rect 43 0 113 16)(font "Arial" (font_size 10))) + (text "inst" (rect 8 96 25 108)(font "Arial" )) + (port + (pt 0 40) + (input) + (text "data3x[6..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data3x[6..0]" (rect 4 26 59 39)(font "Arial" (font_size 8))) + (line (pt 0 40)(pt 64 40)(line_width 3)) + ) + (port + (pt 0 56) + (input) + (text "data2x[6..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data2x[6..0]" (rect 4 42 59 55)(font "Arial" (font_size 8))) + (line (pt 0 56)(pt 64 56)(line_width 3)) + ) + (port + (pt 0 72) + (input) + (text "data1x[6..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data1x[6..0]" (rect 4 58 59 71)(font "Arial" (font_size 8))) + (line (pt 0 72)(pt 64 72)(line_width 3)) + ) + (port + (pt 0 88) + (input) + (text "data0x[6..0]" (rect 0 0 67 14)(font "Arial" (font_size 8))) + (text "data0x[6..0]" (rect 4 74 59 87)(font "Arial" (font_size 8))) + (line (pt 0 88)(pt 64 88)(line_width 3)) + ) + (port + (pt 72 112) + (input) + (text "sel[1..0]" (rect 0 0 14 44)(font "Arial" (font_size 8))(vertical)) + (text "sel[1..0]" (rect 65 59 78 95)(font "Arial" (font_size 8))(vertical)) + (line (pt 72 112)(pt 72 100)(line_width 3)) + ) + (port + (pt 144 64) + (output) + (text "result[6..0]" (rect 0 0 60 14)(font "Arial" (font_size 8))) + (text "result[6..0]" (rect 90 50 139 63)(font "Arial" (font_size 8))) + (line (pt 144 64)(pt 80 64)(line_width 3)) + ) + (drawing + (line (pt 64 24)(pt 64 104)) + (line (pt 64 24)(pt 80 32)) + (line (pt 64 104)(pt 80 96)) + (line (pt 80 32)(pt 80 96)) + (line (pt 0 0)(pt 146 0)) + (line (pt 146 0)(pt 146 114)) + (line (pt 0 114)(pt 146 114)) + (line (pt 0 0)(pt 0 114)) + (line (pt 0 0)(pt 0 0)) + (line (pt 0 0)(pt 0 0)) + (line (pt 0 0)(pt 0 0)) + (line (pt 0 0)(pt 0 0)) + ) +) diff --git a/lab5/lpm_mux1.qip b/lab5/lpm_mux1.qip new file mode 100644 index 0000000..1092800 --- /dev/null +++ b/lab5/lpm_mux1.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "LPM_MUX" +set_global_assignment -name IP_TOOL_VERSION "13.0" +set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "lpm_mux1.vhd"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_mux1.bsf"] diff --git a/lab5/lpm_mux1.vhd b/lab5/lpm_mux1.vhd new file mode 100644 index 0000000..4f626d7 --- /dev/null +++ b/lab5/lpm_mux1.vhd @@ -0,0 +1,146 @@ +-- megafunction wizard: %LPM_MUX% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: LPM_MUX + +-- ============================================================ +-- File Name: lpm_mux1.vhd +-- Megafunction Name(s): +-- LPM_MUX +-- +-- Simulation Library Files(s): +-- lpm +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.0.0 Build 156 04/24/2013 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2013 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY lpm; +USE lpm.lpm_components.all; + +ENTITY lpm_mux1 IS + PORT + ( + data0x : IN STD_LOGIC_VECTOR (6 DOWNTO 0); + data1x : IN STD_LOGIC_VECTOR (6 DOWNTO 0); + data2x : IN STD_LOGIC_VECTOR (6 DOWNTO 0); + data3x : IN STD_LOGIC_VECTOR (6 DOWNTO 0); + sel : IN STD_LOGIC_VECTOR (1 DOWNTO 0); + result : OUT STD_LOGIC_VECTOR (6 DOWNTO 0) + ); +END lpm_mux1; + + +ARCHITECTURE SYN OF lpm_mux1 IS + +-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC; + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL sub_wire2 : STD_LOGIC_2D (3 DOWNTO 0, 6 DOWNTO 0); + SIGNAL sub_wire3 : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL sub_wire4 : STD_LOGIC_VECTOR (6 DOWNTO 0); + SIGNAL sub_wire5 : STD_LOGIC_VECTOR (6 DOWNTO 0); + +BEGIN + sub_wire5 <= data0x(6 DOWNTO 0); + sub_wire4 <= data1x(6 DOWNTO 0); + sub_wire3 <= data2x(6 DOWNTO 0); + result <= sub_wire0(6 DOWNTO 0); + sub_wire1 <= data3x(6 DOWNTO 0); + sub_wire2(3, 0) <= sub_wire1(0); + sub_wire2(3, 1) <= sub_wire1(1); + sub_wire2(3, 2) <= sub_wire1(2); + sub_wire2(3, 3) <= sub_wire1(3); + sub_wire2(3, 4) <= sub_wire1(4); + sub_wire2(3, 5) <= sub_wire1(5); + sub_wire2(3, 6) <= sub_wire1(6); + sub_wire2(2, 0) <= sub_wire3(0); + sub_wire2(2, 1) <= sub_wire3(1); + sub_wire2(2, 2) <= sub_wire3(2); + sub_wire2(2, 3) <= sub_wire3(3); + sub_wire2(2, 4) <= sub_wire3(4); + sub_wire2(2, 5) <= sub_wire3(5); + sub_wire2(2, 6) <= sub_wire3(6); + sub_wire2(1, 0) <= sub_wire4(0); + sub_wire2(1, 1) <= sub_wire4(1); + sub_wire2(1, 2) <= sub_wire4(2); + sub_wire2(1, 3) <= sub_wire4(3); + sub_wire2(1, 4) <= sub_wire4(4); + sub_wire2(1, 5) <= sub_wire4(5); + sub_wire2(1, 6) <= sub_wire4(6); + sub_wire2(0, 0) <= sub_wire5(0); + sub_wire2(0, 1) <= sub_wire5(1); + sub_wire2(0, 2) <= sub_wire5(2); + sub_wire2(0, 3) <= sub_wire5(3); + sub_wire2(0, 4) <= sub_wire5(4); + sub_wire2(0, 5) <= sub_wire5(5); + sub_wire2(0, 6) <= sub_wire5(6); + + LPM_MUX_component : LPM_MUX + GENERIC MAP ( + lpm_size => 4, + lpm_type => "LPM_MUX", + lpm_width => 7, + lpm_widths => 2 + ) + PORT MAP ( + data => sub_wire2, + sel => sel, + result => sub_wire0 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: new_diagram STRING "1" +-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all +-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "4" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "7" +-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "2" +-- Retrieval info: USED_PORT: data0x 0 0 7 0 INPUT NODEFVAL "data0x[6..0]" +-- Retrieval info: USED_PORT: data1x 0 0 7 0 INPUT NODEFVAL "data1x[6..0]" +-- Retrieval info: USED_PORT: data2x 0 0 7 0 INPUT NODEFVAL "data2x[6..0]" +-- Retrieval info: USED_PORT: data3x 0 0 7 0 INPUT NODEFVAL "data3x[6..0]" +-- Retrieval info: USED_PORT: result 0 0 7 0 OUTPUT NODEFVAL "result[6..0]" +-- Retrieval info: USED_PORT: sel 0 0 2 0 INPUT NODEFVAL "sel[1..0]" +-- Retrieval info: CONNECT: @data 1 0 7 0 data0x 0 0 7 0 +-- Retrieval info: CONNECT: @data 1 1 7 0 data1x 0 0 7 0 +-- Retrieval info: CONNECT: @data 1 2 7 0 data2x 0 0 7 0 +-- Retrieval info: CONNECT: @data 1 3 7 0 data3x 0 0 7 0 +-- Retrieval info: CONNECT: @sel 0 0 2 0 sel 0 0 2 0 +-- Retrieval info: CONNECT: result 0 0 7 0 @result 0 0 7 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.bsf TRUE FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1_inst.vhd FALSE +-- Retrieval info: LIB_FILE: lpm diff --git a/lab5/output_files/gA6_lab5.asm.rpt b/lab5/output_files/gA6_lab5.asm.rpt new file mode 100644 index 0000000..8c86e05 --- /dev/null +++ b/lab5/output_files/gA6_lab5.asm.rpt @@ -0,0 +1,130 @@ +Assembler report for gA6_lab5 +Wed Nov 29 18:54:39 2017 +Quartus II 64-Bit Version 13.0.0 Build 156 04/24/2013 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Assembler Summary + 3. Assembler Settings + 4. Assembler Generated Files + 5. Assembler Device Options: C:/home/abbas/dsd_A6/lab5/output_files/gA6_lab5.sof + 6. Assembler Device Options: C:/home/abbas/dsd_A6/lab5/output_files/gA6_lab5.pof + 7. Assembler Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------+ +; Assembler Summary ; ++-----------------------+---------------------------------------+ +; Assembler Status ; Successful - Wed Nov 29 18:54:39 2017 ; +; Revision Name ; gA6_lab5 ; +; Top-level Entity Name ; gA6_lab5 ; +; Family ; Cyclone II ; +; Device ; EP2C20F484C7 ; ++-----------------------+---------------------------------------+ + + ++--------------------------------------------------------------------------------------------------------+ +; Assembler Settings ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Option ; Setting ; Default Value ; ++-----------------------------------------------------------------------------+----------+---------------+ +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Generate compressed bitstreams ; On ; On ; +; Compression mode ; Off ; Off ; +; Clock source for configuration device ; Internal ; Internal ; +; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; +; Divide clock frequency by ; 1 ; 1 ; +; Auto user code ; On ; On ; +; Use configuration device ; On ; On ; +; Configuration device ; Auto ; Auto ; +; Configuration device auto user code ; Off ; Off ; +; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; +; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ; +; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; +; Hexadecimal Output File start address ; 0 ; 0 ; +; Hexadecimal Output File count direction ; Up ; Up ; +; Release clears before tri-states ; Off ; Off ; +; Auto-restart configuration after error ; On ; On ; +; Maintain Compatibility with All Cyclone II M4K Versions ; On ; On ; +; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; +; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; +; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; ++-----------------------------------------------------------------------------+----------+---------------+ + + ++-----------------------------------------------------+ +; Assembler Generated Files ; ++-----------------------------------------------------+ +; File Name ; ++-----------------------------------------------------+ +; C:/home/abbas/dsd_A6/lab5/output_files/gA6_lab5.sof ; +; C:/home/abbas/dsd_A6/lab5/output_files/gA6_lab5.pof ; ++-----------------------------------------------------+ + + ++-------------------------------------------------------------------------------+ +; Assembler Device Options: C:/home/abbas/dsd_A6/lab5/output_files/gA6_lab5.sof ; ++----------------+--------------------------------------------------------------+ +; Option ; Setting ; ++----------------+--------------------------------------------------------------+ +; Device ; EP2C20F484C7 ; +; JTAG usercode ; 0x001B825A ; +; Checksum ; 0x001B825A ; ++----------------+--------------------------------------------------------------+ + + ++-------------------------------------------------------------------------------+ +; Assembler Device Options: C:/home/abbas/dsd_A6/lab5/output_files/gA6_lab5.pof ; ++--------------------+----------------------------------------------------------+ +; Option ; Setting ; ++--------------------+----------------------------------------------------------+ +; Device ; EPCS16 ; +; JTAG usercode ; 0x00000000 ; +; Checksum ; 0x1DD952BE ; +; Compression Ratio ; 3 ; ++--------------------+----------------------------------------------------------+ + + ++--------------------+ +; Assembler Messages ; ++--------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit Assembler + Info: Version 13.0.0 Build 156 04/24/2013 SJ Web Edition + Info: Processing started: Wed Nov 29 18:54:37 2017 +Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off gA6_lab5 -c gA6_lab5 +Info (115031): Writing out detailed assembly data for power analysis +Info (115030): Assembler is generating device programming files +Info: Quartus II 64-Bit Assembler was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 499 megabytes + Info: Processing ended: Wed Nov 29 18:54:40 2017 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:03 + + diff --git a/lab5/output_files/gA6_lab5.done b/lab5/output_files/gA6_lab5.done new file mode 100644 index 0000000..f2f97f9 --- /dev/null +++ b/lab5/output_files/gA6_lab5.done @@ -0,0 +1 @@ +Thu Nov 30 13:56:14 2017 diff --git a/lab5/output_files/gA6_lab5.eda.rpt b/lab5/output_files/gA6_lab5.eda.rpt new file mode 100644 index 0000000..cacec5d --- /dev/null +++ b/lab5/output_files/gA6_lab5.eda.rpt @@ -0,0 +1,92 @@ +EDA Netlist Writer report for gA6_lab5 +Wed Nov 29 18:55:05 2017 +Quartus II 64-Bit Version 13.0.0 Build 156 04/24/2013 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. EDA Netlist Writer Summary + 3. Simulation Settings + 4. Simulation Generated Files + 5. EDA Netlist Writer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-------------------------------------------------------------------+ +; EDA Netlist Writer Summary ; ++---------------------------+---------------------------------------+ +; EDA Netlist Writer Status ; Successful - Wed Nov 29 18:55:05 2017 ; +; Revision Name ; gA6_lab5 ; +; Top-level Entity Name ; gA6_lab5 ; +; Family ; Cyclone II ; +; Simulation Files Creation ; Successful ; ++---------------------------+---------------------------------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Simulation Settings ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Option ; Setting ; ++---------------------------------------------------------------------------------------------------+---------------------------+ +; Tool Name ; ModelSim-Altera (Verilog) ; +; Generate netlist for functional simulation only ; On ; +; Truncate long hierarchy paths ; Off ; +; Map illegal HDL characters ; Off ; +; Flatten buses into individual nodes ; Off ; +; Maintain hierarchy ; Off ; +; Bring out device-wide set/reset signals as ports ; Off ; +; Enable glitch filtering ; Off ; +; Do not write top level VHDL entity ; Off ; +; Disable detection of setup and hold time violations in the input registers of bi-directional pins ; Off ; +; Architecture name in VHDL output netlist ; structure ; +; Generate third-party EDA tool command script for RTL functional simulation ; Off ; +; Generate third-party EDA tool command script for gate-level simulation ; Off ; ++---------------------------------------------------------------------------------------------------+---------------------------+ + + ++-----------------------------------------------------------+ +; Simulation Generated Files ; ++-----------------------------------------------------------+ +; Generated Files ; ++-----------------------------------------------------------+ +; C:/home/abbas/dsd_A6/lab5/simulation/modelsim/gA6_lab5.vo ; ++-----------------------------------------------------------+ + + ++-----------------------------+ +; EDA Netlist Writer Messages ; ++-----------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit EDA Netlist Writer + Info: Version 13.0.0 Build 156 04/24/2013 SJ Web Edition + Info: Processing started: Wed Nov 29 18:55:04 2017 +Info: Command: quartus_eda --functional=on --simulation=on --tool=modelsim_oem --format=verilog gA6_lab5 -c gA6_lab5 +Info (204019): Generated file gA6_lab5.vo in folder "C:/home/abbas/dsd_A6/lab5/simulation/modelsim/" for EDA simulation tool +Info: Quartus II 64-Bit EDA Netlist Writer was successful. 0 errors, 0 warnings + Info: Peak virtual memory: 459 megabytes + Info: Processing ended: Wed Nov 29 18:55:05 2017 + Info: Elapsed time: 00:00:01 + Info: Total CPU time (on all processors): 00:00:01 + + diff --git a/lab5/output_files/gA6_lab5.fit.rpt b/lab5/output_files/gA6_lab5.fit.rpt new file mode 100644 index 0000000..fae7673 --- /dev/null +++ b/lab5/output_files/gA6_lab5.fit.rpt @@ -0,0 +1,1485 @@ +Fitter report for gA6_lab5 +Wed Nov 29 18:54:36 2017 +Quartus II 64-Bit Version 13.0.0 Build 156 04/24/2013 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Fitter Summary + 3. Fitter Settings + 4. Parallel Compilation + 5. Incremental Compilation Preservation Summary + 6. Incremental Compilation Partition Settings + 7. Incremental Compilation Placement Preservation + 8. Pin-Out File + 9. Fitter Resource Usage Summary + 10. Fitter Partition Statistics + 11. Input Pins + 12. Output Pins + 13. I/O Bank Usage + 14. All Package Pins + 15. Output Pin Default Load For Reported TCO + 16. Fitter Resource Utilization by Entity + 17. Delay Chain Summary + 18. Pad To Core Delay Chain Fanout + 19. Control Signals + 20. Global & Other Fast Signals + 21. Non-Global High Fan-Out Signals + 22. Other Routing Usage Summary + 23. LAB Logic Elements + 24. LAB-wide Signals + 25. LAB Signals Sourced + 26. LAB Signals Sourced Out + 27. LAB Distinct Inputs + 28. Fitter Device Options + 29. Operating Settings and Conditions + 30. Fitter Messages + 31. Fitter Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------------------------+ +; Fitter Summary ; ++------------------------------------+--------------------------------------------+ +; Fitter Status ; Successful - Wed Nov 29 18:54:36 2017 ; +; Quartus II 64-Bit Version ; 13.0.0 Build 156 04/24/2013 SJ Web Edition ; +; Revision Name ; gA6_lab5 ; +; Top-level Entity Name ; gA6_lab5 ; +; Family ; Cyclone II ; +; Device ; EP2C20F484C7 ; +; Timing Models ; Final ; +; Total logic elements ; 38 / 18,752 ( < 1 % ) ; +; Total combinational functions ; 36 / 18,752 ( < 1 % ) ; +; Dedicated logic registers ; 17 / 18,752 ( < 1 % ) ; +; Total registers ; 17 ; +; Total pins ; 55 / 315 ( 17 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 239,616 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; ++------------------------------------+--------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Settings ; ++----------------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+--------------------------------+--------------------------------+ +; Device ; EP2C20F484C7 ; ; +; Minimum Core Junction Temperature ; 0 ; ; +; Maximum Core Junction Temperature ; 85 ; ; +; Fit Attempts to Skip ; 0 ; 0.0 ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Auto Merge PLLs ; On ; On ; +; Ignore PLL Mode When Merging PLLs ; Off ; Off ; +; Router Timing Optimization Level ; Normal ; Normal ; +; Placement Effort Multiplier ; 1.0 ; 1.0 ; +; Router Effort Multiplier ; 1.0 ; 1.0 ; +; Always Enable Input Buffers ; Off ; Off ; +; Optimize Hold Timing ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ; +; Optimize Multi-Corner Timing ; On ; On ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; Optimize Timing ; Normal compilation ; Normal compilation ; +; Optimize Timing for ECOs ; Off ; Off ; +; Regenerate full fit report during ECO compiles ; Off ; Off ; +; Optimize IOC Register Placement for Timing ; Normal ; Normal ; +; Limit to One Fitting Attempt ; Off ; Off ; +; Final Placement Optimizations ; Automatically ; Automatically ; +; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ; +; Fitter Initial Placement Seed ; 1 ; 1 ; +; PCI I/O ; Off ; Off ; +; Weak Pull-Up Resistor ; Off ; Off ; +; Enable Bus-Hold Circuitry ; Off ; Off ; +; Auto Global Memory Control Signals ; Off ; Off ; +; Auto Packed Registers ; Auto ; Auto ; +; Auto Delay Chains ; On ; On ; +; Auto Delay Chains for High Fanout Input Pins ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Fitting ; Off ; Off ; +; Perform Physical Synthesis for Combinational Logic for Performance ; Off ; Off ; +; Perform Register Duplication for Performance ; Off ; Off ; +; Perform Logic to Memory Mapping for Fitting ; Off ; Off ; +; Perform Register Retiming for Performance ; Off ; Off ; +; Perform Asynchronous Signal Pipelining ; Off ; Off ; +; Fitter Effort ; Auto Fit ; Auto Fit ; +; Physical Synthesis Effort Level ; Normal ; Normal ; +; Auto Global Clock ; On ; On ; +; Auto Global Register Control Signals ; On ; On ; +; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ; ++----------------------------------------------------------------------------+--------------------------------+--------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 2 ; +; ; ; +; Average used ; 1.14 ; +; Maximum used ; 2 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processor 2 ; 14.3% ; +; Processors 3-4 ; 0.0% ; ++----------------------------+-------------+ + + ++----------------------------------------------+ +; Incremental Compilation Preservation Summary ; ++---------------------+------------------------+ +; Type ; Value ; ++---------------------+------------------------+ +; Placement (by node) ; ; +; -- Requested ; 0 / 114 ( 0.00 % ) ; +; -- Achieved ; 0 / 114 ( 0.00 % ) ; +; ; ; +; Routing (by net) ; ; +; -- Requested ; 0 / 0 ( 0.00 % ) ; +; -- Achieved ; 0 / 0 ( 0.00 % ) ; ++---------------------+------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Partition Settings ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ +; Top ; User-created ; Source File ; N/A ; Source File ; N/A ; ; +; hard_block:auto_generated_inst ; Auto-generated ; Source File ; N/A ; Source File ; N/A ; hard_block:auto_generated_inst ; ++--------------------------------+----------------+-------------------+-------------------------+------------------------+------------------------------+--------------------------------+ + + ++------------------------------------------------------------------------------------------------------------+ +; Incremental Compilation Placement Preservation ; ++--------------------------------+---------+-------------------+-------------------------+-------------------+ +; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ; ++--------------------------------+---------+-------------------+-------------------------+-------------------+ +; Top ; 111 ; 0 ; N/A ; Source File ; +; hard_block:auto_generated_inst ; 3 ; 0 ; N/A ; Source File ; ++--------------------------------+---------+-------------------+-------------------------+-------------------+ + + ++--------------+ +; Pin-Out File ; ++--------------+ +The pin-out file can be found in C:/home/abbas/dsd_A6/lab5/output_files/gA6_lab5.pin. + + ++---------------------------------------------------------------------+ +; Fitter Resource Usage Summary ; ++---------------------------------------------+-----------------------+ +; Resource ; Usage ; ++---------------------------------------------+-----------------------+ +; Total logic elements ; 38 / 18,752 ( < 1 % ) ; +; -- Combinational with no register ; 21 ; +; -- Register only ; 2 ; +; -- Combinational with a register ; 15 ; +; ; ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 17 ; +; -- 3 input functions ; 14 ; +; -- <=2 input functions ; 5 ; +; -- Register only ; 2 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 26 ; +; -- arithmetic mode ; 10 ; +; ; ; +; Total registers* ; 17 / 19,649 ( < 1 % ) ; +; -- Dedicated logic registers ; 17 / 18,752 ( < 1 % ) ; +; -- I/O registers ; 0 / 897 ( 0 % ) ; +; ; ; +; Total LABs: partially or completely used ; 4 / 1,172 ( < 1 % ) ; +; Virtual pins ; 0 ; +; I/O pins ; 55 / 315 ( 17 % ) ; +; -- Clock pins ; 1 / 8 ( 13 % ) ; +; ; ; +; Global signals ; 2 ; +; M4Ks ; 0 / 52 ( 0 % ) ; +; Total block memory bits ; 0 / 239,616 ( 0 % ) ; +; Total block memory implementation bits ; 0 / 239,616 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ; +; PLLs ; 0 / 4 ( 0 % ) ; +; Global clocks ; 2 / 16 ( 13 % ) ; +; JTAGs ; 0 / 1 ( 0 % ) ; +; ASMI blocks ; 0 / 1 ( 0 % ) ; +; CRC blocks ; 0 / 1 ( 0 % ) ; +; Average interconnect usage (total/H/V) ; 0% / 0% / 0% ; +; Peak interconnect usage (total/H/V) ; 0% / 0% / 0% ; +; Maximum fan-out ; 17 ; +; Highest non-global fan-out ; 8 ; +; Total fan-out ; 200 ; +; Average fan-out ; 1.74 ; ++---------------------------------------------+-----------------------+ +* Register count does not include registers inside RAM blocks or DSP blocks. + + + ++-----------------------------------------------------------------------------------------------------+ +; Fitter Partition Statistics ; ++---------------------------------------------+----------------------+--------------------------------+ +; Statistic ; Top ; hard_block:auto_generated_inst ; ++---------------------------------------------+----------------------+--------------------------------+ +; Difficulty Clustering Region ; Low ; Low ; +; ; ; ; +; Total logic elements ; 38 / 18752 ( < 1 % ) ; 0 / 18752 ( 0 % ) ; +; -- Combinational with no register ; 21 ; 0 ; +; -- Register only ; 2 ; 0 ; +; -- Combinational with a register ; 15 ; 0 ; +; ; ; ; +; Logic element usage by number of LUT inputs ; ; ; +; -- 4 input functions ; 17 ; 0 ; +; -- 3 input functions ; 14 ; 0 ; +; -- <=2 input functions ; 5 ; 0 ; +; -- Register only ; 2 ; 0 ; +; ; ; ; +; Logic elements by mode ; ; ; +; -- normal mode ; 26 ; 0 ; +; -- arithmetic mode ; 10 ; 0 ; +; ; ; ; +; Total registers ; 17 ; 0 ; +; -- Dedicated logic registers ; 17 / 18752 ( < 1 % ) ; 0 / 18752 ( 0 % ) ; +; ; ; ; +; Total LABs: partially or completely used ; 4 / 1172 ( < 1 % ) ; 0 / 1172 ( 0 % ) ; +; ; ; ; +; Virtual pins ; 0 ; 0 ; +; I/O pins ; 55 ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ; 0 / 52 ( 0 % ) ; +; Total memory bits ; 0 ; 0 ; +; Total RAM block bits ; 0 ; 0 ; +; Clock control block ; 2 / 20 ( 10 % ) ; 0 / 20 ( 0 % ) ; +; ; ; ; +; Connections ; ; ; +; -- Input Connections ; 0 ; 0 ; +; -- Registered Input Connections ; 0 ; 0 ; +; -- Output Connections ; 0 ; 0 ; +; -- Registered Output Connections ; 0 ; 0 ; +; ; ; ; +; Internal Connections ; ; ; +; -- Total Connections ; 200 ; 0 ; +; -- Registered Connections ; 68 ; 0 ; +; ; ; ; +; External Connections ; ; ; +; -- Top ; 0 ; 0 ; +; -- hard_block:auto_generated_inst ; 0 ; 0 ; +; ; ; ; +; Partition Interface ; ; ; +; -- Input Ports ; 15 ; 0 ; +; -- Output Ports ; 40 ; 0 ; +; -- Bidir Ports ; 0 ; 0 ; +; ; ; ; +; Registered Ports ; ; ; +; -- Registered Input Ports ; 0 ; 0 ; +; -- Registered Output Ports ; 0 ; 0 ; +; ; ; ; +; Port Connectivity ; ; ; +; -- Input Ports driven by GND ; 0 ; 0 ; +; -- Output Ports driven by GND ; 0 ; 0 ; +; -- Input Ports driven by VCC ; 0 ; 0 ; +; -- Output Ports driven by VCC ; 0 ; 0 ; +; -- Input Ports with no Source ; 0 ; 0 ; +; -- Output Ports with no Source ; 0 ; 0 ; +; -- Input Ports with no Fanout ; 0 ; 0 ; +; -- Output Ports with no Fanout ; 0 ; 0 ; ++---------------------------------------------+----------------------+--------------------------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Input Pins ; ++---------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Combinational Fan-Out ; Registered Fan-Out ; Global ; Input Register ; Power Up High ; PCI I/O Enabled ; Bus Hold ; Weak Pull Up ; I/O Standard ; Termination ; Location assigned by ; ++---------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ +; clk ; M1 ; 1 ; 0 ; 13 ; 2 ; 1 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; player_sum[0] ; Y4 ; 1 ; 0 ; 3 ; 3 ; 3 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; player_sum[1] ; AA6 ; 8 ; 7 ; 0 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; player_sum[2] ; AA3 ; 8 ; 1 ; 0 ; 3 ; 4 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; player_sum[3] ; Y7 ; 8 ; 5 ; 0 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; player_sum[4] ; V4 ; 1 ; 0 ; 2 ; 2 ; 4 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; player_sum[5] ; AB3 ; 8 ; 1 ; 0 ; 2 ; 7 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; rst ; M2 ; 1 ; 0 ; 13 ; 3 ; 1 ; 0 ; yes ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; sum[0] ; AA5 ; 8 ; 3 ; 0 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; sum[1] ; Y3 ; 1 ; 0 ; 3 ; 2 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; sum[2] ; AB5 ; 8 ; 3 ; 0 ; 1 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; sum[3] ; Y5 ; 8 ; 3 ; 0 ; 3 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; sum[4] ; Y6 ; 8 ; 3 ; 0 ; 2 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; sum[5] ; U8 ; 8 ; 5 ; 0 ; 1 ; 2 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; +; turn ; W8 ; 8 ; 9 ; 0 ; 1 ; 1 ; 0 ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; Off ; Fitter ; ++---------------+-------+----------+--------------+--------------+-------------+-----------------------+--------------------+--------+----------------+---------------+-----------------+----------+--------------+--------------+-------------+----------------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Output Pins ; ++-----------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+ +; Name ; Pin # ; I/O Bank ; X coordinate ; Y coordinate ; Cell number ; Output Register ; Output Enable Register ; Power Up High ; PCI I/O Enabled ; Open Drain ; TRI Primitive ; Bus Hold ; Weak Pull Up ; I/O Standard ; Current Strength ; Termination ; Location assigned by ; Load ; Output Enable Source ; Output Enable Group ; ++-----------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+ +; dealer_wins ; W3 ; 1 ; 0 ; 3 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; done ; V9 ; 8 ; 9 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; hit ; W7 ; 8 ; 9 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; led_display1[0] ; R5 ; 1 ; 0 ; 7 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; led_display1[1] ; U2 ; 1 ; 0 ; 7 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; led_display1[2] ; Y2 ; 1 ; 0 ; 4 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; led_display1[3] ; T3 ; 1 ; 0 ; 5 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; led_display1[4] ; T15 ; 7 ; 39 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; led_display1[5] ; B17 ; 4 ; 37 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; led_display1[6] ; R6 ; 1 ; 0 ; 7 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; led_display2[0] ; AB7 ; 8 ; 11 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; led_display2[1] ; AA16 ; 7 ; 35 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; led_display2[2] ; B11 ; 3 ; 22 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; led_display2[3] ; H15 ; 4 ; 44 ; 27 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; led_display2[4] ; W9 ; 8 ; 11 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; led_display2[5] ; T5 ; 1 ; 0 ; 6 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; led_display2[6] ; B14 ; 4 ; 29 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; led_display3[0] ; V2 ; 1 ; 0 ; 6 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; led_display3[1] ; Y1 ; 1 ; 0 ; 4 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; led_display3[2] ; C21 ; 5 ; 50 ; 24 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; led_display3[3] ; W1 ; 1 ; 0 ; 4 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; led_display3[4] ; C7 ; 3 ; 7 ; 27 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; led_display3[5] ; U3 ; 1 ; 0 ; 5 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; led_display3[6] ; T6 ; 1 ; 0 ; 5 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; led_display4[0] ; U1 ; 1 ; 0 ; 7 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; led_display4[1] ; AA7 ; 8 ; 11 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; led_display4[2] ; P8 ; 8 ; 7 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; led_display4[3] ; P9 ; 8 ; 7 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; led_display4[4] ; D2 ; 2 ; 0 ; 22 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; led_display4[5] ; G8 ; 3 ; 7 ; 27 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; led_display4[6] ; W2 ; 1 ; 0 ; 4 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; player_wins ; W4 ; 1 ; 0 ; 3 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; state_out[0] ; AB6 ; 8 ; 7 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; state_out[1] ; V8 ; 8 ; 9 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; sum_out[0] ; AB4 ; 8 ; 1 ; 0 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; sum_out[1] ; T7 ; 8 ; 5 ; 0 ; 2 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; sum_out[2] ; T8 ; 8 ; 5 ; 0 ; 3 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; sum_out[3] ; AA4 ; 8 ; 1 ; 0 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; sum_out[4] ; W5 ; 1 ; 0 ; 2 ; 0 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; +; sum_out[5] ; U4 ; 1 ; 0 ; 2 ; 1 ; no ; no ; no ; no ; no ; no ; no ; Off ; 3.3-V LVTTL ; 24mA ; Off ; Fitter ; 0 pF ; - ; - ; ++-----------------+-------+----------+--------------+--------------+-------------+-----------------+------------------------+---------------+-----------------+------------+---------------+----------+--------------+--------------+------------------+-------------+----------------------+------+----------------------+---------------------+ + + ++------------------------------------------------------------+ +; I/O Bank Usage ; ++----------+------------------+---------------+--------------+ +; I/O Bank ; Usage ; VCCIO Voltage ; VREF Voltage ; ++----------+------------------+---------------+--------------+ +; 1 ; 22 / 41 ( 54 % ) ; 3.3V ; -- ; +; 2 ; 3 / 33 ( 9 % ) ; 3.3V ; -- ; +; 3 ; 3 / 43 ( 7 % ) ; 3.3V ; -- ; +; 4 ; 3 / 40 ( 8 % ) ; 3.3V ; -- ; +; 5 ; 1 / 39 ( 3 % ) ; 3.3V ; -- ; +; 6 ; 1 / 36 ( 3 % ) ; 3.3V ; -- ; +; 7 ; 2 / 40 ( 5 % ) ; 3.3V ; -- ; +; 8 ; 23 / 43 ( 53 % ) ; 3.3V ; -- ; ++----------+------------------+---------------+--------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; All Package Pins ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; Location ; Pad Number ; I/O Bank ; Pin Name/Usage ; Dir. ; I/O Standard ; Voltage ; I/O Type ; User Assignment ; Bus Hold ; Weak Pull Up ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +; A1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; A2 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; A3 ; 325 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A4 ; 324 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A5 ; 322 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A6 ; 320 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A7 ; 306 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A8 ; 304 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A9 ; 298 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A10 ; 293 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A11 ; 287 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A12 ; 283 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; A13 ; 281 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A14 ; 279 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A15 ; 273 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A16 ; 271 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A17 ; 265 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A18 ; 251 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A19 ; 249 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A20 ; 247 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; A21 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; A22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA1 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AA2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA3 ; 82 ; 8 ; player_sum[2] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; AA4 ; 85 ; 8 ; sum_out[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; AA5 ; 89 ; 8 ; sum[0] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; AA6 ; 97 ; 8 ; player_sum[1] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; AA7 ; 103 ; 8 ; led_display4[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; AA8 ; 111 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA9 ; 114 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA10 ; 120 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA11 ; 122 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA12 ; 128 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA13 ; 130 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA14 ; 136 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA15 ; 138 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA16 ; 140 ; 7 ; led_display2[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; AA17 ; 144 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA18 ; 153 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA19 ; 162 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA20 ; 164 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AA21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AA22 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB1 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; AB2 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB3 ; 83 ; 8 ; player_sum[5] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; AB4 ; 84 ; 8 ; sum_out[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; AB5 ; 88 ; 8 ; sum[2] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; AB6 ; 96 ; 8 ; state_out[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; AB7 ; 102 ; 8 ; led_display2[0] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; AB8 ; 110 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB9 ; 113 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB10 ; 119 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB11 ; 121 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB12 ; 127 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB13 ; 129 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB14 ; 135 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB15 ; 137 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB16 ; 139 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB17 ; 143 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB18 ; 152 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB19 ; 161 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB20 ; 163 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; AB21 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; AB22 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B1 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; B2 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B3 ; 326 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B4 ; 323 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B5 ; 321 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B6 ; 319 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B7 ; 305 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B8 ; 303 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B9 ; 297 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B10 ; 292 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B11 ; 286 ; 3 ; led_display2[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; B12 ; 282 ; 4 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; B13 ; 280 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B14 ; 278 ; 4 ; led_display2[6] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; B15 ; 272 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B16 ; 270 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B17 ; 264 ; 4 ; led_display1[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; B18 ; 250 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B19 ; 248 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B20 ; 246 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; B21 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; B22 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; C1 ; 8 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; C2 ; 9 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; C3 ; 1 ; 2 ; ~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; +; C4 ; 0 ; 2 ; ~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; On ; +; C5 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C6 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; C7 ; 315 ; 3 ; led_display3[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; C8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C9 ; 310 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; C10 ; 296 ; 3 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; C11 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; C12 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; C13 ; 275 ; 4 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; C14 ; 260 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; C15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; C16 ; 254 ; 4 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; C17 ; 245 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; C18 ; 244 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; C19 ; 238 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; C20 ; 239 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; C21 ; 236 ; 5 ; led_display3[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; C22 ; 237 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D1 ; 14 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D2 ; 15 ; 2 ; led_display4[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; D3 ; 2 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D4 ; 3 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D5 ; 4 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D6 ; 5 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D7 ; 311 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D8 ; 309 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D9 ; 302 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D11 ; 289 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D12 ; 284 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; D13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D14 ; 267 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D15 ; 259 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D16 ; 255 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; D17 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; D18 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; D19 ; 240 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D20 ; 241 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D21 ; 229 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; D22 ; 230 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E1 ; 20 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E2 ; 21 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E3 ; 6 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E4 ; 7 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E5 ; ; ; VCCD_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; E6 ; ; ; VCCA_PLL3 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; E7 ; 316 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E8 ; 308 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E9 ; 301 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E10 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; E11 ; 288 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E12 ; 285 ; 3 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; E13 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; E14 ; 266 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E15 ; 256 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; E16 ; ; ; GNDA_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; E17 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; E18 ; 243 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E19 ; 242 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E20 ; 234 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E21 ; 227 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; E22 ; 228 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F1 ; 22 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F2 ; 23 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F3 ; 13 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F4 ; 10 ; 2 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; F5 ; ; ; GND_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ; +; F6 ; ; ; GND_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ; +; F7 ; ; ; GNDA_PLL3 ; gnd ; ; ; -- ; ; -- ; -- ; +; F8 ; 312 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F9 ; 307 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F10 ; 295 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F11 ; 294 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F12 ; 276 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F13 ; 269 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F14 ; 268 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F15 ; 262 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; F16 ; ; ; VCCA_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; F17 ; ; ; VCCD_PLL2 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; F18 ; ; ; GND_PLL2 ; gnd ; ; ; -- ; ; -- ; -- ; +; F19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; F20 ; 235 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F21 ; 223 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; F22 ; 224 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G1 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; G2 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; G3 ; 16 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G5 ; 12 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G6 ; 11 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G7 ; 317 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G8 ; 313 ; 3 ; led_display4[5] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; G9 ; ; 3 ; VCCIO3 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; G10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G11 ; 291 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G12 ; 277 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; G14 ; ; 4 ; VCCIO4 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; G15 ; 261 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G16 ; 252 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; G17 ; 231 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G18 ; 232 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G19 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; G20 ; 233 ; 5 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; G21 ; 221 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; G22 ; 222 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H1 ; 24 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H2 ; 25 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H3 ; 27 ; 2 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; H4 ; 17 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H5 ; 18 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H6 ; 19 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H7 ; 318 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H8 ; 314 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H9 ; 300 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H10 ; 299 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H11 ; 290 ; 3 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H12 ; 274 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H13 ; 263 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H14 ; 257 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; H15 ; 253 ; 4 ; led_display2[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; H16 ; 219 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H17 ; 226 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H18 ; 225 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H19 ; 214 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; H20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; H21 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; H22 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J1 ; 29 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J2 ; 30 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J3 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J4 ; 28 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J6 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J7 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; J8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J9 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; J10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; J14 ; 258 ; 4 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; J15 ; 220 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J16 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; J17 ; 218 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J18 ; 217 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J19 ; 216 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J20 ; 213 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J21 ; 211 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; J22 ; 212 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; K1 ; 37 ; 2 ; ^nCE ; ; ; ; -- ; ; -- ; -- ; +; K2 ; 32 ; 2 ; #TCK ; input ; ; ; -- ; ; -- ; -- ; +; K3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K4 ; 36 ; 2 ; ^DATA0 ; input ; ; ; -- ; ; -- ; -- ; +; K5 ; 31 ; 2 ; #TDI ; input ; ; ; -- ; ; -- ; -- ; +; K6 ; 33 ; 2 ; #TMS ; input ; ; ; -- ; ; -- ; -- ; +; K7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; K9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; K15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; K16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K17 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; K18 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; K19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; K20 ; 215 ; 5 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; K21 ; 209 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; K22 ; 210 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; L1 ; 38 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; L2 ; 39 ; 2 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; L3 ; ; 2 ; VCCIO2 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; L4 ; 40 ; 2 ; ^nCONFIG ; ; ; ; -- ; ; -- ; -- ; +; L5 ; 34 ; 2 ; #TDO ; output ; ; ; -- ; ; -- ; -- ; +; L6 ; 35 ; 2 ; ^DCLK ; ; ; ; -- ; ; -- ; -- ; +; L7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; L8 ; 26 ; 2 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; L9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; L14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; L15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; L16 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; L17 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; L18 ; 208 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; L19 ; 207 ; 5 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; L20 ; ; 5 ; VCCIO5 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; L21 ; 205 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; L22 ; 206 ; 5 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; M1 ; 41 ; 1 ; clk ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; M2 ; 42 ; 1 ; rst ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; M3 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; M4 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M5 ; 43 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; M6 ; 44 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; M7 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; M8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; M9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; M14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; M15 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; M16 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; M17 ; 198 ; 6 ; ^MSEL0 ; ; ; ; -- ; ; -- ; -- ; +; M18 ; 202 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; M19 ; 201 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; M20 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; M21 ; 203 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; M22 ; 204 ; 6 ; GND+ ; ; ; ; Row I/O ; ; -- ; -- ; +; N1 ; 45 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N2 ; 46 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N3 ; 51 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N4 ; 52 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N5 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; N6 ; 49 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N7 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N8 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; N9 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N11 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N12 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N14 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; N15 ; 194 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N16 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N17 ; 197 ; 6 ; ^MSEL1 ; ; ; ; -- ; ; -- ; -- ; +; N18 ; 196 ; 6 ; ^CONF_DONE ; ; ; ; -- ; ; -- ; -- ; +; N19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; N20 ; 195 ; 6 ; ^nSTATUS ; ; ; ; -- ; ; -- ; -- ; +; N21 ; 199 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; N22 ; 200 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P1 ; 47 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P2 ; 48 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P3 ; 50 ; 1 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; P4 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; P5 ; 55 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P6 ; 56 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P7 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; P8 ; 95 ; 8 ; led_display4[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; P9 ; 94 ; 8 ; led_display4[3] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; P10 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P11 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P12 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P13 ; ; ; VCCINT ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; P14 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; P15 ; 193 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P16 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; P17 ; 186 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P18 ; 187 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; P19 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; P20 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; P21 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; P22 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; R1 ; 57 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R2 ; 58 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; R4 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; R5 ; 63 ; 1 ; led_display1[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; R6 ; 64 ; 1 ; led_display1[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; R7 ; 54 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R8 ; 53 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R9 ; 109 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R10 ; 108 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R11 ; 116 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R12 ; 134 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R13 ; 145 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R14 ; 150 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R15 ; 151 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R16 ; 155 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; R17 ; 177 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R18 ; 184 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R19 ; 185 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R20 ; 192 ; 6 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; R21 ; 190 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; R22 ; 191 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T1 ; 59 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T2 ; 60 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T3 ; 69 ; 1 ; led_display1[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; T4 ; ; 1 ; VCCIO1 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; T5 ; 67 ; 1 ; led_display2[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; T6 ; 68 ; 1 ; led_display3[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; T7 ; 91 ; 8 ; sum_out[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; T8 ; 90 ; 8 ; sum_out[2] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; T9 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; T10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T11 ; 115 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T12 ; 131 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T14 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; T15 ; 147 ; 7 ; led_display1[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; T16 ; 156 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; T17 ; ; ; GND_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ; +; T18 ; 171 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T19 ; ; 6 ; VCCIO6 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; T20 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; T21 ; 188 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; T22 ; 189 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U1 ; 61 ; 1 ; led_display4[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; U2 ; 62 ; 1 ; led_display1[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; U3 ; 70 ; 1 ; led_display3[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; U4 ; 80 ; 1 ; sum_out[5] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; U5 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; U6 ; ; ; VCCD_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U7 ; ; ; VCCA_PLL1 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U8 ; 92 ; 8 ; sum[5] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; U9 ; 106 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U10 ; 107 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U11 ; 123 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; U12 ; 124 ; 8 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; U13 ; 132 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U14 ; 146 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U15 ; 157 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; U16 ; ; ; VCCA_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U17 ; ; ; VCCD_PLL4 ; power ; ; 1.2V ; -- ; ; -- ; -- ; +; U18 ; 170 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U19 ; 172 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U20 ; 176 ; 6 ; GND* ; ; ; ; Row I/O ; ; -- ; -- ; +; U21 ; 182 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; U22 ; 183 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V1 ; 65 ; 1 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V2 ; 66 ; 1 ; led_display3[0] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; V3 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V4 ; 81 ; 1 ; player_sum[4] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; V5 ; ; ; GND_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; V6 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V7 ; ; ; GNDA_PLL1 ; gnd ; ; ; -- ; ; -- ; -- ; +; V8 ; 98 ; 8 ; state_out[1] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; V9 ; 101 ; 8 ; done ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; V10 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; V11 ; 118 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; V12 ; 126 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; V13 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; V14 ; 142 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; V15 ; 158 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; V16 ; ; ; GNDA_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ; +; V17 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; V18 ; ; ; GND_PLL4 ; gnd ; ; ; -- ; ; -- ; -- ; +; V19 ; 166 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V20 ; 173 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V21 ; 180 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; V22 ; 181 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W1 ; 71 ; 1 ; led_display3[3] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; W2 ; 72 ; 1 ; led_display4[6] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; W3 ; 75 ; 1 ; dealer_wins ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; W4 ; 76 ; 1 ; player_wins ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; W5 ; 79 ; 1 ; sum_out[4] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; W6 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; W7 ; 99 ; 8 ; hit ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; W8 ; 100 ; 8 ; turn ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; W9 ; 105 ; 8 ; led_display2[4] ; output ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; W10 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W11 ; 117 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W12 ; 125 ; 7 ; GND+ ; ; ; ; Column I/O ; ; -- ; -- ; +; W13 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W14 ; 141 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W15 ; 149 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W16 ; 160 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; W17 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; W18 ; ; ; NC ; ; ; ; -- ; ; -- ; -- ; +; W19 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; W20 ; 167 ; 6 ; ~LVDS91p/nCEO~ ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; W21 ; 174 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; W22 ; 175 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y1 ; 73 ; 1 ; led_display3[1] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; Y2 ; 74 ; 1 ; led_display1[2] ; output ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; Y3 ; 77 ; 1 ; sum[1] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; Y4 ; 78 ; 1 ; player_sum[0] ; input ; 3.3-V LVTTL ; ; Row I/O ; N ; no ; Off ; +; Y5 ; 86 ; 8 ; sum[3] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; Y6 ; 87 ; 8 ; sum[4] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; Y7 ; 93 ; 8 ; player_sum[3] ; input ; 3.3-V LVTTL ; ; Column I/O ; N ; no ; Off ; +; Y8 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y9 ; 104 ; 8 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y10 ; 112 ; 8 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; Y11 ; ; 8 ; VCCIO8 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; Y12 ; ; 7 ; VCCIO7 ; power ; ; 3.3V ; -- ; ; -- ; -- ; +; Y13 ; 133 ; 7 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; Y14 ; 148 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y15 ; ; ; GND ; gnd ; ; ; -- ; ; -- ; -- ; +; Y16 ; 154 ; 7 ; GND* ; ; ; ; Column I/O ; ; -- ; -- ; +; Y17 ; 159 ; 7 ; GND* ; ; ; ; Column I/O ; ; no ; Off ; +; Y18 ; 165 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y19 ; 168 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y20 ; 169 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y21 ; 178 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; +; Y22 ; 179 ; 6 ; GND* ; ; ; ; Row I/O ; ; no ; Off ; ++----------+------------+----------+------------------------------------------+--------+--------------+---------+------------+-----------------+----------+--------------+ +Note: Pin directions (input, output or bidir) are based on device operating in user mode. + + ++-------------------------------------------------------------------------------+ +; Output Pin Default Load For Reported TCO ; ++----------------------------------+-------+------------------------------------+ +; I/O Standard ; Load ; Termination Resistance ; ++----------------------------------+-------+------------------------------------+ +; 3.3-V LVTTL ; 0 pF ; Not Available ; +; 3.3-V LVCMOS ; 0 pF ; Not Available ; +; 2.5 V ; 0 pF ; Not Available ; +; 1.8 V ; 0 pF ; Not Available ; +; 1.5 V ; 0 pF ; Not Available ; +; 3.3-V PCI ; 10 pF ; 25 Ohm (Parallel) ; +; 3.3-V PCI-X ; 10 pF ; 25 Ohm (Parallel) ; +; SSTL-2 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-2 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-18 Class I ; 0 pF ; 50 Ohm (Parallel), 25 Ohm (Serial) ; +; SSTL-18 Class II ; 0 pF ; 25 Ohm (Parallel), 25 Ohm (Serial) ; +; 1.5-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; +; 1.5-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; +; 1.8-V HSTL Class I ; 0 pF ; 50 Ohm (Parallel) ; +; 1.8-V HSTL Class II ; 0 pF ; 25 Ohm (Parallel) ; +; Differential SSTL-2 ; 0 pF ; (See SSTL-2) ; +; Differential 2.5-V SSTL Class II ; 0 pF ; (See SSTL-2 Class II) ; +; Differential 1.8-V SSTL Class I ; 0 pF ; (See 1.8-V SSTL Class I) ; +; Differential 1.8-V SSTL Class II ; 0 pF ; (See 1.8-V SSTL Class II) ; +; Differential 1.5-V HSTL Class I ; 0 pF ; (See 1.5-V HSTL Class I) ; +; Differential 1.5-V HSTL Class II ; 0 pF ; (See 1.5-V HSTL Class II) ; +; Differential 1.8-V HSTL Class I ; 0 pF ; (See 1.8-V HSTL Class I) ; +; Differential 1.8-V HSTL Class II ; 0 pF ; (See 1.8-V HSTL Class II) ; +; LVDS ; 0 pF ; 100 Ohm (Differential) ; +; mini-LVDS ; 0 pF ; 100 Ohm (Differential) ; +; RSDS ; 0 pF ; 100 Ohm (Differential) ; +; Simple RSDS ; 0 pF ; Not Available ; +; Differential LVPECL ; 0 pF ; 100 Ohm (Differential) ; ++----------------------------------+-------+------------------------------------+ +Note: User assignments will override these defaults. The user specified values are listed in the Output Pins and Bidir Pins tables. + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fitter Resource Utilization by Entity ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-----------------------------+--------------+ +; Compilation Hierarchy Node ; Logic Cells ; Dedicated Logic Registers ; I/O Registers ; Memory Bits ; M4Ks ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Full Hierarchy Name ; Library Name ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-----------------------------+--------------+ +; |gA6_lab5 ; 38 (0) ; 17 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 55 ; 0 ; 21 (0) ; 2 (0) ; 15 (0) ; |gA6_lab5 ; ; +; |gA6_computer:inst| ; 12 (12) ; 10 (10) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 10 (10) ; |gA6_lab5|gA6_computer:inst ; ; +; |gA6_winner:inst1| ; 32 (32) ; 7 (7) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 19 (19) ; 2 (2) ; 11 (11) ; |gA6_lab5|gA6_winner:inst1 ; ; ++----------------------------+-------------+---------------------------+---------------+-------------+------+--------------+---------+-----------+------+--------------+--------------+-------------------+------------------+-----------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++------------------------------------------------------------------------------------------+ +; Delay Chain Summary ; ++-----------------+----------+---------------+---------------+-----------------------+-----+ +; Name ; Pin Type ; Pad to Core 0 ; Pad to Core 1 ; Pad to Input Register ; TCO ; ++-----------------+----------+---------------+---------------+-----------------------+-----+ +; hit ; Output ; -- ; -- ; -- ; -- ; +; done ; Output ; -- ; -- ; -- ; -- ; +; player_wins ; Output ; -- ; -- ; -- ; -- ; +; dealer_wins ; Output ; -- ; -- ; -- ; -- ; +; led_display1[6] ; Output ; -- ; -- ; -- ; -- ; +; led_display1[5] ; Output ; -- ; -- ; -- ; -- ; +; led_display1[4] ; Output ; -- ; -- ; -- ; -- ; +; led_display1[3] ; Output ; -- ; -- ; -- ; -- ; +; led_display1[2] ; Output ; -- ; -- ; -- ; -- ; +; led_display1[1] ; Output ; -- ; -- ; -- ; -- ; +; led_display1[0] ; Output ; -- ; -- ; -- ; -- ; +; led_display2[6] ; Output ; -- ; -- ; -- ; -- ; +; led_display2[5] ; Output ; -- ; -- ; -- ; -- ; +; led_display2[4] ; Output ; -- ; -- ; -- ; -- ; +; led_display2[3] ; Output ; -- ; -- ; -- ; -- ; +; led_display2[2] ; Output ; -- ; -- ; -- ; -- ; +; led_display2[1] ; Output ; -- ; -- ; -- ; -- ; +; led_display2[0] ; Output ; -- ; -- ; -- ; -- ; +; led_display3[6] ; Output ; -- ; -- ; -- ; -- ; +; led_display3[5] ; Output ; -- ; -- ; -- ; -- ; +; led_display3[4] ; Output ; -- ; -- ; -- ; -- ; +; led_display3[3] ; Output ; -- ; -- ; -- ; -- ; +; led_display3[2] ; Output ; -- ; -- ; -- ; -- ; +; led_display3[1] ; Output ; -- ; -- ; -- ; -- ; +; led_display3[0] ; Output ; -- ; -- ; -- ; -- ; +; led_display4[6] ; Output ; -- ; -- ; -- ; -- ; +; led_display4[5] ; Output ; -- ; -- ; -- ; -- ; +; led_display4[4] ; Output ; -- ; -- ; -- ; -- ; +; led_display4[3] ; Output ; -- ; -- ; -- ; -- ; +; led_display4[2] ; Output ; -- ; -- ; -- ; -- ; +; led_display4[1] ; Output ; -- ; -- ; -- ; -- ; +; led_display4[0] ; Output ; -- ; -- ; -- ; -- ; +; state_out[1] ; Output ; -- ; -- ; -- ; -- ; +; state_out[0] ; Output ; -- ; -- ; -- ; -- ; +; sum_out[5] ; Output ; -- ; -- ; -- ; -- ; +; sum_out[4] ; Output ; -- ; -- ; -- ; -- ; +; sum_out[3] ; Output ; -- ; -- ; -- ; -- ; +; sum_out[2] ; Output ; -- ; -- ; -- ; -- ; +; sum_out[1] ; Output ; -- ; -- ; -- ; -- ; +; sum_out[0] ; Output ; -- ; -- ; -- ; -- ; +; sum[5] ; Input ; (6) 2514 ps ; (6) 2514 ps ; -- ; -- ; +; sum[4] ; Input ; (6) 2514 ps ; (6) 2514 ps ; -- ; -- ; +; sum[3] ; Input ; (6) 2514 ps ; (6) 2514 ps ; -- ; -- ; +; sum[2] ; Input ; (6) 2514 ps ; (6) 2514 ps ; -- ; -- ; +; sum[1] ; Input ; (6) 2523 ps ; (6) 2523 ps ; -- ; -- ; +; sum[0] ; Input ; (6) 2514 ps ; (6) 2514 ps ; -- ; -- ; +; clk ; Input ; (0) 171 ps ; (0) 171 ps ; -- ; -- ; +; rst ; Input ; (0) 171 ps ; (0) 171 ps ; -- ; -- ; +; player_sum[5] ; Input ; (6) 2514 ps ; (6) 2514 ps ; -- ; -- ; +; player_sum[4] ; Input ; (6) 2523 ps ; (6) 2523 ps ; -- ; -- ; +; player_sum[3] ; Input ; (6) 2514 ps ; (6) 2514 ps ; -- ; -- ; +; player_sum[2] ; Input ; (6) 2514 ps ; (6) 2514 ps ; -- ; -- ; +; player_sum[1] ; Input ; (6) 2514 ps ; (6) 2514 ps ; -- ; -- ; +; player_sum[0] ; Input ; (6) 2523 ps ; (6) 2523 ps ; -- ; -- ; +; turn ; Input ; (6) 2514 ps ; (6) 2514 ps ; -- ; -- ; ++-----------------+----------+---------------+---------------+-----------------------+-----+ + + ++-----------------------------------------------------------------------------+ +; Pad To Core Delay Chain Fanout ; ++-----------------------------------------------+-------------------+---------+ +; Source Pin / Fanout ; Pad To Core Index ; Setting ; ++-----------------------------------------------+-------------------+---------+ +; sum[5] ; ; ; +; - gA6_computer:inst|sum_out[5] ; 0 ; 6 ; +; - gA6_computer:inst|LessThan0~1 ; 0 ; 6 ; +; sum[4] ; ; ; +; - gA6_computer:inst|sum_out[4] ; 0 ; 6 ; +; - gA6_computer:inst|LessThan0~1 ; 0 ; 6 ; +; sum[3] ; ; ; +; - gA6_computer:inst|sum_out[3] ; 0 ; 6 ; +; - gA6_computer:inst|LessThan0~0 ; 0 ; 6 ; +; sum[2] ; ; ; +; - gA6_computer:inst|sum_out[2] ; 0 ; 6 ; +; - gA6_computer:inst|LessThan0~0 ; 0 ; 6 ; +; sum[1] ; ; ; +; - gA6_computer:inst|sum_out[1] ; 1 ; 6 ; +; - gA6_computer:inst|LessThan0~0 ; 1 ; 6 ; +; sum[0] ; ; ; +; - gA6_computer:inst|sum_out[0] ; 1 ; 6 ; +; - gA6_computer:inst|LessThan0~0 ; 1 ; 6 ; +; clk ; ; ; +; rst ; ; ; +; player_sum[5] ; ; ; +; - gA6_winner:inst1|LessThan2~10 ; 0 ; 6 ; +; - gA6_winner:inst1|LessThan3~10 ; 0 ; 6 ; +; - gA6_winner:inst1|p_win~3 ; 0 ; 6 ; +; - gA6_winner:inst1|p_win~6 ; 0 ; 6 ; +; - gA6_winner:inst1|led_display1~6 ; 0 ; 6 ; +; - gA6_winner:inst1|led_display1[0]~7 ; 0 ; 6 ; +; - gA6_winner:inst1|led_display3~3 ; 0 ; 6 ; +; player_sum[4] ; ; ; +; - gA6_winner:inst1|LessThan2~9 ; 1 ; 6 ; +; - gA6_winner:inst1|LessThan3~9 ; 1 ; 6 ; +; - gA6_winner:inst1|Equal0~2 ; 1 ; 6 ; +; - gA6_winner:inst1|p_win~2 ; 1 ; 6 ; +; player_sum[3] ; ; ; +; - gA6_winner:inst1|LessThan2~7 ; 0 ; 6 ; +; - gA6_winner:inst1|LessThan3~7 ; 0 ; 6 ; +; - gA6_winner:inst1|Equal0~1 ; 0 ; 6 ; +; - gA6_winner:inst1|p_win~2 ; 0 ; 6 ; +; player_sum[2] ; ; ; +; - gA6_winner:inst1|LessThan2~5 ; 0 ; 6 ; +; - gA6_winner:inst1|LessThan3~5 ; 0 ; 6 ; +; - gA6_winner:inst1|Equal0~1 ; 0 ; 6 ; +; - gA6_winner:inst1|p_win~2 ; 0 ; 6 ; +; player_sum[1] ; ; ; +; - gA6_winner:inst1|LessThan2~3 ; 1 ; 6 ; +; - gA6_winner:inst1|LessThan3~3 ; 1 ; 6 ; +; - gA6_winner:inst1|Equal0~0 ; 1 ; 6 ; +; - gA6_winner:inst1|p_win~2 ; 1 ; 6 ; +; player_sum[0] ; ; ; +; - gA6_winner:inst1|LessThan2~1 ; 1 ; 6 ; +; - gA6_winner:inst1|LessThan3~1 ; 1 ; 6 ; +; - gA6_winner:inst1|Equal0~0 ; 1 ; 6 ; +; turn ; ; ; +; - gA6_computer:inst|\computer:state[0]~0 ; 0 ; 6 ; ++-----------------------------------------------+-------------------+---------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Control Signals ; ++------------------------------------+-----------------+---------+--------------+--------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Usage ; Global ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++------------------------------------+-----------------+---------+--------------+--------+----------------------+------------------+---------------------------+ +; clk ; PIN_M1 ; 17 ; Clock ; yes ; Global Clock ; GCLK3 ; -- ; +; gA6_winner:inst1|led_display1[0]~5 ; LCCOMB_X1_Y1_N4 ; 3 ; Clock enable ; no ; -- ; -- ; -- ; +; rst ; PIN_M2 ; 10 ; Async. clear ; yes ; Global Clock ; GCLK1 ; -- ; ++------------------------------------+-----------------+---------+--------------+--------+----------------------+------------------+---------------------------+ + + ++-------------------------------------------------------------------------------------------------+ +; Global & Other Fast Signals ; ++------+----------+---------+----------------------+------------------+---------------------------+ +; Name ; Location ; Fan-Out ; Global Resource Used ; Global Line Name ; Enable Signal Source Name ; ++------+----------+---------+----------------------+------------------+---------------------------+ +; clk ; PIN_M1 ; 17 ; Global Clock ; GCLK3 ; -- ; +; rst ; PIN_M2 ; 10 ; Global Clock ; GCLK1 ; -- ; ++------+----------+---------+----------------------+------------------+---------------------------+ + + ++--------------------------------------------------+ +; Non-Global High Fan-Out Signals ; ++----------------------------------------+---------+ +; Name ; Fan-Out ; ++----------------------------------------+---------+ +; gA6_winner:inst1|led_display3[1] ; 8 ; +; player_sum[5] ; 7 ; +; gA6_winner:inst1|p_win~5 ; 5 ; +; gA6_winner:inst1|p_win~4 ; 5 ; +; gA6_winner:inst1|p_win~2 ; 5 ; +; gA6_computer:inst|sum_out[1] ; 5 ; +; gA6_computer:inst|sum_out[2] ; 5 ; +; gA6_computer:inst|sum_out[3] ; 5 ; +; gA6_computer:inst|sum_out[4] ; 5 ; +; gA6_computer:inst|sum_out[5] ; 5 ; +; gA6_computer:inst|\computer:state[0] ; 5 ; +; gA6_computer:inst|\computer:state[1] ; 5 ; +; gA6_winner:inst1|led_display1[0] ; 5 ; +; player_sum[1] ; 4 ; +; player_sum[2] ; 4 ; +; player_sum[3] ; 4 ; +; player_sum[4] ; 4 ; +; gA6_winner:inst1|\dealer:d_win ; 4 ; +; gA6_winner:inst1|p_win~1 ; 4 ; +; gA6_winner:inst1|\dealer:p_win ; 4 ; +; gA6_computer:inst|sum_out[0] ; 4 ; +; gA6_winner:inst1|led_display4[3] ; 4 ; +; player_sum[0] ; 3 ; +; gA6_winner:inst1|led_display1[0]~5 ; 3 ; +; gA6_winner:inst1|p_win~7 ; 3 ; +; gA6_computer:inst|LessThan0~1 ; 3 ; +; sum[0] ; 2 ; +; sum[1] ; 2 ; +; sum[2] ; 2 ; +; sum[3] ; 2 ; +; sum[4] ; 2 ; +; sum[5] ; 2 ; +; gA6_winner:inst1|d_win~0 ; 2 ; +; gA6_winner:inst1|p_win~6 ; 2 ; +; gA6_winner:inst1|p_win~0 ; 2 ; +; gA6_winner:inst1|LessThan3~10 ; 2 ; +; gA6_winner:inst1|LessThan2~10 ; 2 ; +; turn ; 1 ; +; gA6_winner:inst1|led_display3~3 ; 1 ; +; gA6_winner:inst1|led_display1[0]~7 ; 1 ; +; gA6_winner:inst1|led_display1~6 ; 1 ; +; gA6_computer:inst|\computer:state[0]~0 ; 1 ; +; gA6_computer:inst|\computer:state[1]~0 ; 1 ; +; gA6_winner:inst1|led_display3~2 ; 1 ; +; gA6_winner:inst1|led_display1~4 ; 1 ; +; gA6_winner:inst1|p_win~3 ; 1 ; +; gA6_winner:inst1|Equal0~2 ; 1 ; +; gA6_winner:inst1|Equal0~1 ; 1 ; +; gA6_winner:inst1|Equal0~0 ; 1 ; +; gA6_computer:inst|Mux1~0 ; 1 ; +; gA6_computer:inst|Mux0~0 ; 1 ; +; gA6_computer:inst|LessThan0~0 ; 1 ; +; gA6_winner:inst1|dealer_wins ; 1 ; +; gA6_winner:inst1|player_wins ; 1 ; +; gA6_computer:inst|done ; 1 ; +; gA6_computer:inst|hit ; 1 ; +; gA6_winner:inst1|LessThan3~9 ; 1 ; +; gA6_winner:inst1|LessThan3~7 ; 1 ; +; gA6_winner:inst1|LessThan3~5 ; 1 ; +; gA6_winner:inst1|LessThan3~3 ; 1 ; +; gA6_winner:inst1|LessThan3~1 ; 1 ; +; gA6_winner:inst1|LessThan2~9 ; 1 ; +; gA6_winner:inst1|LessThan2~7 ; 1 ; +; gA6_winner:inst1|LessThan2~5 ; 1 ; +; gA6_winner:inst1|LessThan2~3 ; 1 ; +; gA6_winner:inst1|LessThan2~1 ; 1 ; ++----------------------------------------+---------+ + + ++-----------------------------------------------------+ +; Other Routing Usage Summary ; ++-----------------------------+-----------------------+ +; Other Routing Resource Type ; Usage ; ++-----------------------------+-----------------------+ +; Block interconnects ; 58 / 54,004 ( < 1 % ) ; +; C16 interconnects ; 0 / 2,100 ( 0 % ) ; +; C4 interconnects ; 35 / 36,000 ( < 1 % ) ; +; Direct links ; 11 / 54,004 ( < 1 % ) ; +; Global clocks ; 2 / 16 ( 13 % ) ; +; Local interconnects ; 21 / 18,752 ( < 1 % ) ; +; R24 interconnects ; 0 / 1,900 ( 0 % ) ; +; R4 interconnects ; 20 / 46,920 ( < 1 % ) ; ++-----------------------------+-----------------------+ + + ++--------------------------------------------------------------------------+ +; LAB Logic Elements ; ++--------------------------------------------+-----------------------------+ +; Number of Logic Elements (Average = 9.50) ; Number of LABs (Total = 4) ; ++--------------------------------------------+-----------------------------+ +; 1 ; 0 ; +; 2 ; 1 ; +; 3 ; 0 ; +; 4 ; 1 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 2 ; ++--------------------------------------------+-----------------------------+ + + ++------------------------------------------------------------------+ +; LAB-wide Signals ; ++------------------------------------+-----------------------------+ +; LAB-wide Signals (Average = 1.25) ; Number of LABs (Total = 4) ; ++------------------------------------+-----------------------------+ +; 1 Async. clear ; 2 ; +; 1 Clock ; 3 ; ++------------------------------------+-----------------------------+ + + ++----------------------------------------------------------------------------+ +; LAB Signals Sourced ; ++----------------------------------------------+-----------------------------+ +; Number of Signals Sourced (Average = 11.25) ; Number of LABs (Total = 4) ; ++----------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 1 ; +; 3 ; 0 ; +; 4 ; 0 ; +; 5 ; 0 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 1 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 1 ; +; 13 ; 0 ; +; 14 ; 0 ; +; 15 ; 0 ; +; 16 ; 0 ; +; 17 ; 0 ; +; 18 ; 0 ; +; 19 ; 0 ; +; 20 ; 0 ; +; 21 ; 0 ; +; 22 ; 0 ; +; 23 ; 1 ; ++----------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------------+ +; LAB Signals Sourced Out ; ++-------------------------------------------------+-----------------------------+ +; Number of Signals Sourced Out (Average = 5.50) ; Number of LABs (Total = 4) ; ++-------------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 1 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 1 ; +; 5 ; 1 ; +; 6 ; 0 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 0 ; +; 12 ; 1 ; ++-------------------------------------------------+-----------------------------+ + + ++---------------------------------------------------------------------------+ +; LAB Distinct Inputs ; ++---------------------------------------------+-----------------------------+ +; Number of Distinct Inputs (Average = 8.75) ; Number of LABs (Total = 4) ; ++---------------------------------------------+-----------------------------+ +; 0 ; 0 ; +; 1 ; 0 ; +; 2 ; 0 ; +; 3 ; 0 ; +; 4 ; 1 ; +; 5 ; 0 ; +; 6 ; 1 ; +; 7 ; 0 ; +; 8 ; 0 ; +; 9 ; 0 ; +; 10 ; 0 ; +; 11 ; 1 ; +; 12 ; 0 ; +; 13 ; 0 ; +; 14 ; 1 ; ++---------------------------------------------+-----------------------------+ + + ++-------------------------------------------------------------------------+ +; Fitter Device Options ; ++----------------------------------------------+--------------------------+ +; Option ; Setting ; ++----------------------------------------------+--------------------------+ +; Enable user-supplied start-up clock (CLKUSR) ; Off ; +; Enable device-wide reset (DEV_CLRn) ; Off ; +; Enable device-wide output enable (DEV_OE) ; Off ; +; Enable INIT_DONE output ; Off ; +; Configuration scheme ; Active Serial ; +; Error detection CRC ; Off ; +; nCEO ; As output driving ground ; +; ASDO,nCSO ; As input tri-stated ; +; Reserve all unused pins ; As output driving ground ; +; Base pin-out file on sameframe device ; Off ; ++----------------------------------------------+--------------------------+ + + ++------------------------------------+ +; Operating Settings and Conditions ; ++---------------------------+--------+ +; Setting ; Value ; ++---------------------------+--------+ +; Nominal Core Voltage ; 1.20 V ; +; Low Junction Temperature ; 0 °C ; +; High Junction Temperature ; 85 °C ; ++---------------------------+--------+ + + ++-----------------+ +; Fitter Messages ; ++-----------------+ +Info (11104): Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead. +Info (119006): Selected device EP2C20F484C7 for design "gA6_lab5" +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Info (171003): Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time +Warning (292013): Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature. +Info (176444): Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices + Info (176445): Device EP2C15AF484C7 is compatible + Info (176445): Device EP2C35F484C7 is compatible + Info (176445): Device EP2C50F484C7 is compatible +Info (169124): Fitter converted 3 user pins into dedicated programming pins + Info (169125): Pin ~ASDO~ is reserved at location C4 + Info (169125): Pin ~nCSO~ is reserved at location C3 + Info (169125): Pin ~LVDS91p/nCEO~ is reserved at location W20 +Critical Warning (169085): No exact pin location assignment(s) for 55 pins of 55 total pins + Info (169086): Pin hit not assigned to an exact location on the device + Info (169086): Pin done not assigned to an exact location on the device + Info (169086): Pin player_wins not assigned to an exact location on the device + Info (169086): Pin dealer_wins not assigned to an exact location on the device + Info (169086): Pin led_display1[6] not assigned to an exact location on the device + Info (169086): Pin led_display1[5] not assigned to an exact location on the device + Info (169086): Pin led_display1[4] not assigned to an exact location on the device + Info (169086): Pin led_display1[3] not assigned to an exact location on the device + Info (169086): Pin led_display1[2] not assigned to an exact location on the device + Info (169086): Pin led_display1[1] not assigned to an exact location on the device + Info (169086): Pin led_display1[0] not assigned to an exact location on the device + Info (169086): Pin led_display2[6] not assigned to an exact location on the device + Info (169086): Pin led_display2[5] not assigned to an exact location on the device + Info (169086): Pin led_display2[4] not assigned to an exact location on the device + Info (169086): Pin led_display2[3] not assigned to an exact location on the device + Info (169086): Pin led_display2[2] not assigned to an exact location on the device + Info (169086): Pin led_display2[1] not assigned to an exact location on the device + Info (169086): Pin led_display2[0] not assigned to an exact location on the device + Info (169086): Pin led_display3[6] not assigned to an exact location on the device + Info (169086): Pin led_display3[5] not assigned to an exact location on the device + Info (169086): Pin led_display3[4] not assigned to an exact location on the device + Info (169086): Pin led_display3[3] not assigned to an exact location on the device + Info (169086): Pin led_display3[2] not assigned to an exact location on the device + Info (169086): Pin led_display3[1] not assigned to an exact location on the device + Info (169086): Pin led_display3[0] not assigned to an exact location on the device + Info (169086): Pin led_display4[6] not assigned to an exact location on the device + Info (169086): Pin led_display4[5] not assigned to an exact location on the device + Info (169086): Pin led_display4[4] not assigned to an exact location on the device + Info (169086): Pin led_display4[3] not assigned to an exact location on the device + Info (169086): Pin led_display4[2] not assigned to an exact location on the device + Info (169086): Pin led_display4[1] not assigned to an exact location on the device + Info (169086): Pin led_display4[0] not assigned to an exact location on the device + Info (169086): Pin state_out[1] not assigned to an exact location on the device + Info (169086): Pin state_out[0] not assigned to an exact location on the device + Info (169086): Pin sum_out[5] not assigned to an exact location on the device + Info (169086): Pin sum_out[4] not assigned to an exact location on the device + Info (169086): Pin sum_out[3] not assigned to an exact location on the device + Info (169086): Pin sum_out[2] not assigned to an exact location on the device + Info (169086): Pin sum_out[1] not assigned to an exact location on the device + Info (169086): Pin sum_out[0] not assigned to an exact location on the device + Info (169086): Pin sum[5] not assigned to an exact location on the device + Info (169086): Pin sum[4] not assigned to an exact location on the device + Info (169086): Pin sum[3] not assigned to an exact location on the device + Info (169086): Pin sum[2] not assigned to an exact location on the device + Info (169086): Pin sum[1] not assigned to an exact location on the device + Info (169086): Pin sum[0] not assigned to an exact location on the device + Info (169086): Pin clk not assigned to an exact location on the device + Info (169086): Pin rst not assigned to an exact location on the device + Info (169086): Pin player_sum[5] not assigned to an exact location on the device + Info (169086): Pin player_sum[4] not assigned to an exact location on the device + Info (169086): Pin player_sum[3] not assigned to an exact location on the device + Info (169086): Pin player_sum[2] not assigned to an exact location on the device + Info (169086): Pin player_sum[1] not assigned to an exact location on the device + Info (169086): Pin player_sum[0] not assigned to an exact location on the device + Info (169086): Pin turn not assigned to an exact location on the device +Critical Warning (332012): Synopsys Design Constraints File file not found: 'gA6_lab5.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332144): No user constrained base clocks found in the design +Info (332130): Timing requirements not specified -- quality metrics such as performance may be sacrificed to reduce compilation time. +Info (176353): Automatically promoted node clk (placed in PIN M1 (CLK2, LVDSCLK1p, Input)) + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G3 +Info (176353): Automatically promoted node rst (placed in PIN M2 (CLK3, LVDSCLK1n, Input)) + Info (176355): Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1 +Info (176233): Starting register packing +Info (176235): Finished register packing + Extra Info (176219): No registers were packed into other blocks +Info (176214): Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement + Info (176211): Number of I/O pins in group: 53 (unused VREF, 3.3V VCCIO, 13 input, 40 output, 0 bidirectional) + Info (176212): I/O standards used: 3.3-V LVTTL. +Info (176215): I/O bank details before I/O pin placement + Info (176214): Statistics of I/O banks + Info (176213): I/O bank number 1 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 39 pins available + Info (176213): I/O bank number 2 does not use VREF pins and has undetermined VCCIO pins. 2 total pin(s) used -- 31 pins available + Info (176213): I/O bank number 3 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available + Info (176213): I/O bank number 4 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available + Info (176213): I/O bank number 5 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 39 pins available + Info (176213): I/O bank number 6 does not use VREF pins and has undetermined VCCIO pins. 1 total pin(s) used -- 35 pins available + Info (176213): I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 40 pins available + Info (176213): I/O bank number 8 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 43 pins available +Info (171121): Fitter preparation operations ending: elapsed time is 00:00:00 +Info (170189): Fitter placement preparation operations beginning +Info (170190): Fitter placement preparation operations ending: elapsed time is 00:00:00 +Info (170191): Fitter placement operations beginning +Info (170137): Fitter placement was successful +Info (170192): Fitter placement operations ending: elapsed time is 00:00:01 +Info (170193): Fitter routing operations beginning +Info (170195): Router estimated average interconnect usage is 0% of the available device resources + Info (170196): Router estimated peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X11_Y13 +Info (170194): Fitter routing operations ending: elapsed time is 00:00:02 +Info (170199): The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time. + Info (170201): Optimizations that may affect the design's routability were skipped +Info (11888): Total time spent on timing analysis during the Fitter is 0.28 seconds. +Info (306004): Started post-fitting delay annotation +Warning (306006): Found 40 output pins without output pin load capacitance assignment + Info (306007): Pin "hit" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "done" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "player_wins" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "dealer_wins" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "led_display1[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "led_display1[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "led_display1[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "led_display1[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "led_display1[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "led_display1[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "led_display1[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "led_display2[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "led_display2[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "led_display2[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "led_display2[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "led_display2[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "led_display2[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "led_display2[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "led_display3[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "led_display3[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "led_display3[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "led_display3[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "led_display3[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "led_display3[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "led_display3[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "led_display4[6]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "led_display4[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "led_display4[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "led_display4[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "led_display4[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "led_display4[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "led_display4[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "state_out[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "state_out[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "sum_out[5]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "sum_out[4]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "sum_out[3]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "sum_out[2]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "sum_out[1]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis + Info (306007): Pin "sum_out[0]" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis +Info (306005): Delay annotation completed successfully +Info (306004): Started post-fitting delay annotation +Info (306005): Delay annotation completed successfully +Info (11218): Fitter post-fit operations ending: elapsed time is 00:00:00 +Warning (169174): The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'. +Info (144001): Generated suppressed messages file C:/home/abbas/dsd_A6/lab5/output_files/gA6_lab5.fit.smsg +Info: Quartus II 64-Bit Fitter was successful. 0 errors, 5 warnings + Info: Peak virtual memory: 944 megabytes + Info: Processing ended: Wed Nov 29 18:54:36 2017 + Info: Elapsed time: 00:00:08 + Info: Total CPU time (on all processors): 00:00:09 + + ++----------------------------+ +; Fitter Suppressed Messages ; ++----------------------------+ +The suppressed messages can be found in C:/home/abbas/dsd_A6/lab5/output_files/gA6_lab5.fit.smsg. + + diff --git a/lab5/output_files/gA6_lab5.fit.smsg b/lab5/output_files/gA6_lab5.fit.smsg new file mode 100644 index 0000000..558ea95 --- /dev/null +++ b/lab5/output_files/gA6_lab5.fit.smsg @@ -0,0 +1,8 @@ +Extra Info (176273): Performing register packing on registers with non-logic cell location assignments +Extra Info (176274): Completed register packing on registers with non-logic cell location assignments +Extra Info (176236): Started Fast Input/Output/OE register processing +Extra Info (176237): Finished Fast Input/Output/OE register processing +Extra Info (176238): Start inferring scan chains for DSP blocks +Extra Info (176239): Inferring scan chains for DSP blocks is complete +Extra Info (176248): Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density +Extra Info (176249): Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks diff --git a/lab5/output_files/gA6_lab5.fit.summary b/lab5/output_files/gA6_lab5.fit.summary new file mode 100644 index 0000000..66dbac2 --- /dev/null +++ b/lab5/output_files/gA6_lab5.fit.summary @@ -0,0 +1,16 @@ +Fitter Status : Successful - Wed Nov 29 18:54:36 2017 +Quartus II 64-Bit Version : 13.0.0 Build 156 04/24/2013 SJ Web Edition +Revision Name : gA6_lab5 +Top-level Entity Name : gA6_lab5 +Family : Cyclone II +Device : EP2C20F484C7 +Timing Models : Final +Total logic elements : 38 / 18,752 ( < 1 % ) + Total combinational functions : 36 / 18,752 ( < 1 % ) + Dedicated logic registers : 17 / 18,752 ( < 1 % ) +Total registers : 17 +Total pins : 55 / 315 ( 17 % ) +Total virtual pins : 0 +Total memory bits : 0 / 239,616 ( 0 % ) +Embedded Multiplier 9-bit elements : 0 / 52 ( 0 % ) +Total PLLs : 0 / 4 ( 0 % ) diff --git a/lab5/output_files/gA6_lab5.flow.rpt b/lab5/output_files/gA6_lab5.flow.rpt new file mode 100644 index 0000000..cff40b6 --- /dev/null +++ b/lab5/output_files/gA6_lab5.flow.rpt @@ -0,0 +1,136 @@ +Flow report for gA6_lab5 +Wed Nov 29 18:55:05 2017 +Quartus II 64-Bit Version 13.0.0 Build 156 04/24/2013 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Flow Summary + 3. Flow Settings + 4. Flow Non-Default Global Settings + 5. Flow Elapsed Time + 6. Flow OS Summary + 7. Flow Log + 8. Flow Messages + 9. Flow Suppressed Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------------------------+ +; Flow Summary ; ++------------------------------------+--------------------------------------------+ +; Flow Status ; Successful - Wed Nov 29 18:55:05 2017 ; +; Quartus II 64-Bit Version ; 13.0.0 Build 156 04/24/2013 SJ Web Edition ; +; Revision Name ; gA6_lab5 ; +; Top-level Entity Name ; gA6_lab5 ; +; Family ; Cyclone II ; +; Device ; EP2C20F484C7 ; +; Timing Models ; Final ; +; Total logic elements ; 38 / 18,752 ( < 1 % ) ; +; Total combinational functions ; 36 / 18,752 ( < 1 % ) ; +; Dedicated logic registers ; 17 / 18,752 ( < 1 % ) ; +; Total registers ; 17 ; +; Total pins ; 55 / 315 ( 17 % ) ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 / 239,616 ( 0 % ) ; +; Embedded Multiplier 9-bit elements ; 0 / 52 ( 0 % ) ; +; Total PLLs ; 0 / 4 ( 0 % ) ; ++------------------------------------+--------------------------------------------+ + + ++-----------------------------------------+ +; Flow Settings ; ++-------------------+---------------------+ +; Option ; Setting ; ++-------------------+---------------------+ +; Start date & time ; 11/29/2017 18:54:25 ; +; Main task ; Compilation ; +; Revision Name ; gA6_lab5 ; ++-------------------+---------------------+ + + ++----------------------------------------------------------------------------------------------------------------------------+ +; Flow Non-Default Global Settings ; ++-------------------------------------+---------------------------------------+---------------+-------------+----------------+ +; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; ++-------------------------------------+---------------------------------------+---------------+-------------+----------------+ +; COMPILER_SIGNATURE_ID ; 88491850560622.151199966411256 ; -- ; -- ; -- ; +; EDA_GENERATE_FUNCTIONAL_NETLIST ; On ; -- ; -- ; eda_simulation ; +; EDA_OUTPUT_DATA_FORMAT ; Verilog Hdl ; -- ; -- ; eda_simulation ; +; EDA_SIMULATION_TOOL ; ModelSim-Altera (Verilog) ; ; -- ; -- ; +; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; +; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; +; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ; +; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ; +; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; +; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ; +; POWER_PRESET_COOLING_SOLUTION ; 23 MM HEAT SINK WITH 200 LFPM AIRFLOW ; -- ; -- ; -- ; +; PROJECT_OUTPUT_DIRECTORY ; output_files ; -- ; -- ; -- ; ++-------------------------------------+---------------------------------------+---------------+-------------+----------------+ + + ++-------------------------------------------------------------------------------------------------------------------------------+ +; Flow Elapsed Time ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ +; Analysis & Synthesis ; 00:00:02 ; 1.0 ; 571 MB ; 00:00:02 ; +; Fitter ; 00:00:08 ; 1.1 ; 944 MB ; 00:00:09 ; +; Assembler ; 00:00:02 ; 1.0 ; 491 MB ; 00:00:03 ; +; TimeQuest Timing Analyzer ; 00:00:03 ; 1.0 ; 530 MB ; 00:00:02 ; +; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 451 MB ; 00:00:01 ; +; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 459 MB ; 00:00:01 ; +; EDA Netlist Writer ; 00:00:01 ; 1.0 ; 459 MB ; 00:00:01 ; +; Total ; 00:00:18 ; -- ; -- ; 00:00:19 ; ++---------------------------+--------------+-------------------------+---------------------+------------------------------------+ + + ++----------------------------------------------------------------------------------------+ +; Flow OS Summary ; ++---------------------------+------------------+-----------+------------+----------------+ +; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; ++---------------------------+------------------+-----------+------------+----------------+ +; Analysis & Synthesis ; Abbas-PC ; Windows 7 ; 6.2 ; x86_64 ; +; Fitter ; Abbas-PC ; Windows 7 ; 6.2 ; x86_64 ; +; Assembler ; Abbas-PC ; Windows 7 ; 6.2 ; x86_64 ; +; TimeQuest Timing Analyzer ; Abbas-PC ; Windows 7 ; 6.2 ; x86_64 ; +; EDA Netlist Writer ; Abbas-PC ; Windows 7 ; 6.2 ; x86_64 ; +; EDA Netlist Writer ; Abbas-PC ; Windows 7 ; 6.2 ; x86_64 ; +; EDA Netlist Writer ; Abbas-PC ; Windows 7 ; 6.2 ; x86_64 ; ++---------------------------+------------------+-----------+------------+----------------+ + + +------------ +; Flow Log ; +------------ +quartus_map --read_settings_files=on --write_settings_files=off gA6_lab5 -c gA6_lab5 +quartus_fit --read_settings_files=off --write_settings_files=off gA6_lab5 -c gA6_lab5 +quartus_asm --read_settings_files=off --write_settings_files=off gA6_lab5 -c gA6_lab5 +quartus_sta gA6_lab5 -c gA6_lab5 +quartus_eda --read_settings_files=off --write_settings_files=off gA6_lab5 -c gA6_lab5 +quartus_eda --gen_testbench --check_outputs=on --tool=modelsim_oem --format=verilog gA6_lab5 -c gA6_lab5 --vector_source=C:/home/abbas/dsd_A6/lab5/gA6_lab5_fsm.vwf --testbench_file=./simulation/qsim/gA6_lab5.vt +quartus_eda --functional=on --simulation=on --tool=modelsim_oem --format=verilog gA6_lab5 -c gA6_lab5 + + + diff --git a/lab5/output_files/gA6_lab5.jdi b/lab5/output_files/gA6_lab5.jdi new file mode 100644 index 0000000..553439f --- /dev/null +++ b/lab5/output_files/gA6_lab5.jdi @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/lab5/output_files/gA6_lab5.map.rpt b/lab5/output_files/gA6_lab5.map.rpt new file mode 100644 index 0000000..9a68015 --- /dev/null +++ b/lab5/output_files/gA6_lab5.map.rpt @@ -0,0 +1,325 @@ +Analysis & Synthesis report for gA6_lab5 +Wed Nov 29 18:54:27 2017 +Quartus II 64-Bit Version 13.0.0 Build 156 04/24/2013 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. Analysis & Synthesis Summary + 3. Analysis & Synthesis Settings + 4. Parallel Compilation + 5. Analysis & Synthesis Source Files Read + 6. Analysis & Synthesis Resource Usage Summary + 7. Analysis & Synthesis Resource Utilization by Entity + 8. Registers Removed During Synthesis + 9. General Register Statistics + 10. Multiplexer Restructuring Statistics (Restructuring Performed) + 11. Elapsed Time Per Partition + 12. Analysis & Synthesis Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++---------------------------------------------------------------------------------+ +; Analysis & Synthesis Summary ; ++------------------------------------+--------------------------------------------+ +; Analysis & Synthesis Status ; Successful - Wed Nov 29 18:54:27 2017 ; +; Quartus II 64-Bit Version ; 13.0.0 Build 156 04/24/2013 SJ Web Edition ; +; Revision Name ; gA6_lab5 ; +; Top-level Entity Name ; gA6_lab5 ; +; Family ; Cyclone II ; +; Total logic elements ; 45 ; +; Total combinational functions ; 36 ; +; Dedicated logic registers ; 17 ; +; Total registers ; 17 ; +; Total pins ; 55 ; +; Total virtual pins ; 0 ; +; Total memory bits ; 0 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Total PLLs ; 0 ; ++------------------------------------+--------------------------------------------+ + + ++----------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Settings ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Option ; Setting ; Default Value ; ++----------------------------------------------------------------------------+--------------------+--------------------+ +; Device ; EP2C20F484C7 ; ; +; Top-level entity name ; gA6_lab5 ; gA6_lab5 ; +; Family name ; Cyclone II ; Cyclone IV GX ; +; Use smart compilation ; Off ; Off ; +; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; +; Enable compact report table ; Off ; Off ; +; Restructure Multiplexers ; Auto ; Auto ; +; Create Debugging Nodes for IP Cores ; Off ; Off ; +; Preserve fewer node names ; On ; On ; +; Disable OpenCore Plus hardware evaluation ; Off ; Off ; +; Verilog Version ; Verilog_2001 ; Verilog_2001 ; +; VHDL Version ; VHDL_1993 ; VHDL_1993 ; +; State Machine Processing ; Auto ; Auto ; +; Safe State Machine ; Off ; Off ; +; Extract Verilog State Machines ; On ; On ; +; Extract VHDL State Machines ; On ; On ; +; Ignore Verilog initial constructs ; Off ; Off ; +; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; +; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; +; Add Pass-Through Logic to Inferred RAMs ; On ; On ; +; Infer RAMs from Raw Logic ; On ; On ; +; Parallel Synthesis ; On ; On ; +; DSP Block Balancing ; Auto ; Auto ; +; NOT Gate Push-Back ; On ; On ; +; Power-Up Don't Care ; On ; On ; +; Remove Redundant Logic Cells ; Off ; Off ; +; Remove Duplicate Registers ; On ; On ; +; Ignore CARRY Buffers ; Off ; Off ; +; Ignore CASCADE Buffers ; Off ; Off ; +; Ignore GLOBAL Buffers ; Off ; Off ; +; Ignore ROW GLOBAL Buffers ; Off ; Off ; +; Ignore LCELL Buffers ; Off ; Off ; +; Ignore SOFT Buffers ; On ; On ; +; Limit AHDL Integers to 32 Bits ; Off ; Off ; +; Optimization Technique ; Balanced ; Balanced ; +; Carry Chain Length ; 70 ; 70 ; +; Auto Carry Chains ; On ; On ; +; Auto Open-Drain Pins ; On ; On ; +; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ; +; Auto ROM Replacement ; On ; On ; +; Auto RAM Replacement ; On ; On ; +; Auto Shift Register Replacement ; Auto ; Auto ; +; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; +; Auto Clock Enable Replacement ; On ; On ; +; Strict RAM Replacement ; Off ; Off ; +; Allow Synchronous Control Signals ; On ; On ; +; Force Use of Synchronous Clear Signals ; Off ; Off ; +; Auto RAM to Logic Cell Conversion ; Off ; Off ; +; Auto Resource Sharing ; Off ; Off ; +; Allow Any RAM Size For Recognition ; Off ; Off ; +; Allow Any ROM Size For Recognition ; Off ; Off ; +; Allow Any Shift Register Size For Recognition ; Off ; Off ; +; Use LogicLock Constraints during Resource Balancing ; On ; On ; +; Ignore translate_off and synthesis_off directives ; Off ; Off ; +; Timing-Driven Synthesis ; Off ; Off ; +; Report Parameter Settings ; On ; On ; +; Report Source Assignments ; On ; On ; +; Report Connectivity Checks ; On ; On ; +; Ignore Maximum Fan-Out Assignments ; Off ; Off ; +; Synchronization Register Chain Length ; 2 ; 2 ; +; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; +; HDL message level ; Level2 ; Level2 ; +; Suppress Register Optimization Related Messages ; Off ; Off ; +; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; +; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; +; Clock MUX Protection ; On ; On ; +; Auto Gated Clock Conversion ; Off ; Off ; +; Block Design Naming ; Auto ; Auto ; +; SDC constraint protection ; Off ; Off ; +; Synthesis Effort ; Auto ; Auto ; +; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; +; Pre-Mapping Resynthesis Optimization ; Off ; Off ; +; Analysis & Synthesis Message Level ; Medium ; Medium ; +; Disable Register Merging Across Hierarchies ; Auto ; Auto ; +; Resource Aware Inference For Block RAM ; On ; On ; +; Synthesis Seed ; 1 ; 1 ; ++----------------------------------------------------------------------------+--------------------+--------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 2 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 1 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; 0.0% ; ++----------------------------+-------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Source Files Read ; ++----------------------------------+-----------------+------------------------------------+--------------------------------------------+---------+ +; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; ++----------------------------------+-----------------+------------------------------------+--------------------------------------------+---------+ +; gA6_winner.vhd ; yes ; User VHDL File ; C:/home/abbas/dsd_A6/lab5/gA6_winner.vhd ; ; +; gA6_computer.vhd ; yes ; User VHDL File ; C:/home/abbas/dsd_A6/lab5/gA6_computer.vhd ; ; +; gA6_lab5.bdf ; yes ; User Block Diagram/Schematic File ; C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf ; ; ++----------------------------------+-----------------+------------------------------------+--------------------------------------------+---------+ + + ++-----------------------------------------------------+ +; Analysis & Synthesis Resource Usage Summary ; ++---------------------------------------------+-------+ +; Resource ; Usage ; ++---------------------------------------------+-------+ +; Estimated Total logic elements ; 45 ; +; ; ; +; Total combinational functions ; 36 ; +; Logic element usage by number of LUT inputs ; ; +; -- 4 input functions ; 17 ; +; -- 3 input functions ; 14 ; +; -- <=2 input functions ; 5 ; +; ; ; +; Logic elements by mode ; ; +; -- normal mode ; 26 ; +; -- arithmetic mode ; 10 ; +; ; ; +; Total registers ; 17 ; +; -- Dedicated logic registers ; 17 ; +; -- I/O registers ; 0 ; +; ; ; +; I/O pins ; 55 ; +; Embedded Multiplier 9-bit elements ; 0 ; +; Maximum fan-out node ; clk ; +; Maximum fan-out ; 17 ; +; Total fan-out ; 196 ; +; Average fan-out ; 1.81 ; ++---------------------------------------------+-------+ + + ++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Analysis & Synthesis Resource Utilization by Entity ; ++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------+--------------+ +; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; ++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------+--------------+ +; |gA6_lab5 ; 36 (0) ; 17 (0) ; 0 ; 0 ; 0 ; 0 ; 55 ; 0 ; |gA6_lab5 ; ; +; |gA6_computer:inst| ; 6 (6) ; 10 (10) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |gA6_lab5|gA6_computer:inst ; ; +; |gA6_winner:inst1| ; 30 (30) ; 7 (7) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |gA6_lab5|gA6_winner:inst1 ; ; ++----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+-----------------------------+--------------+ +Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. + + ++---------------------------------------------------------------------------------------+ +; Registers Removed During Synthesis ; ++----------------------------------------+----------------------------------------------+ +; Register name ; Reason for Removal ; ++----------------------------------------+----------------------------------------------+ +; gA6_winner:inst1|led_display1[3] ; Merged with gA6_winner:inst1|led_display4[0] ; +; gA6_winner:inst1|led_display4[2] ; Merged with gA6_winner:inst1|led_display4[1] ; +; gA6_winner:inst1|led_display2[0] ; Merged with gA6_winner:inst1|led_display4[3] ; +; gA6_winner:inst1|led_display2[2,4] ; Merged with gA6_winner:inst1|led_display4[4] ; +; gA6_winner:inst1|led_display1[5] ; Merged with gA6_winner:inst1|led_display4[4] ; +; gA6_winner:inst1|led_display2[1,3] ; Merged with gA6_winner:inst1|led_display4[4] ; +; gA6_winner:inst1|led_display3[2] ; Merged with gA6_winner:inst1|led_display4[4] ; +; gA6_winner:inst1|led_display1[4] ; Merged with gA6_winner:inst1|led_display4[4] ; +; gA6_winner:inst1|led_display4[5] ; Merged with gA6_winner:inst1|led_display4[4] ; +; gA6_winner:inst1|led_display3[0,3,5,6] ; Merged with gA6_winner:inst1|led_display4[6] ; +; gA6_winner:inst1|led_display2[5] ; Merged with gA6_winner:inst1|led_display4[6] ; +; gA6_winner:inst1|led_display1[2] ; Merged with gA6_winner:inst1|led_display3[1] ; +; gA6_winner:inst1|led_display2[6] ; Merged with gA6_winner:inst1|led_display3[4] ; +; gA6_winner:inst1|led_display1[1,6] ; Merged with gA6_winner:inst1|led_display1[0] ; +; gA6_winner:inst1|led_display4[4] ; Stuck at GND due to stuck port data_in ; +; gA6_winner:inst1|led_display3[4] ; Stuck at VCC due to stuck port data_in ; +; gA6_winner:inst1|led_display4[1] ; Merged with gA6_winner:inst1|led_display4[3] ; +; gA6_winner:inst1|led_display4[6] ; Merged with gA6_winner:inst1|led_display3[1] ; +; gA6_winner:inst1|led_display4[0] ; Merged with gA6_winner:inst1|led_display1[0] ; +; Total Number of Removed Registers = 25 ; ; ++----------------------------------------+----------------------------------------------+ + + ++------------------------------------------------------+ +; General Register Statistics ; ++----------------------------------------------+-------+ +; Statistic ; Value ; ++----------------------------------------------+-------+ +; Total registers ; 17 ; +; Number of registers using Synchronous Clear ; 0 ; +; Number of registers using Synchronous Load ; 0 ; +; Number of registers using Asynchronous Clear ; 10 ; +; Number of registers using Asynchronous Load ; 0 ; +; Number of registers using Clock Enable ; 3 ; +; Number of registers using Preset ; 0 ; ++----------------------------------------------+-------+ + + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Multiplexer Restructuring Statistics (Restructuring Performed) ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------+ +; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------+ +; 4:1 ; 6 bits ; 12 LEs ; 12 LEs ; 0 LEs ; Yes ; |gA6_lab5|gA6_winner:inst1|led_display1[0] ; +; 6:1 ; 2 bits ; 8 LEs ; 4 LEs ; 4 LEs ; Yes ; |gA6_lab5|gA6_computer:inst|\computer:state[1] ; +; 6:1 ; 2 bits ; 8 LEs ; 8 LEs ; 0 LEs ; No ; |gA6_lab5|gA6_winner:inst1|p_win ; ++--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------+ + + ++-------------------------------+ +; Elapsed Time Per Partition ; ++----------------+--------------+ +; Partition Name ; Elapsed Time ; ++----------------+--------------+ +; Top ; 00:00:00 ; ++----------------+--------------+ + + ++-------------------------------+ +; Analysis & Synthesis Messages ; ++-------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit Analysis & Synthesis + Info: Version 13.0.0 Build 156 04/24/2013 SJ Web Edition + Info: Processing started: Wed Nov 29 18:54:24 2017 +Info: Command: quartus_map --read_settings_files=on --write_settings_files=off gA6_lab5 -c gA6_lab5 +Info (11104): Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead. +Info (12021): Found 2 design units, including 1 entities, in source file ga6_winner.vhd + Info (12022): Found design unit 1: gA6_winner-behavior + Info (12023): Found entity 1: gA6_winner +Info (12021): Found 2 design units, including 1 entities, in source file ga6_computer.vhd + Info (12022): Found design unit 1: gA6_computer-behavior + Info (12023): Found entity 1: gA6_computer +Info (12021): Found 1 design units, including 1 entities, in source file ga6_lab5.bdf + Info (12023): Found entity 1: gA6_lab5 +Info (12127): Elaborating entity "gA6_lab5" for the top level hierarchy +Info (12128): Elaborating entity "gA6_computer" for hierarchy "gA6_computer:inst" +Info (12128): Elaborating entity "gA6_winner" for hierarchy "gA6_winner:inst1" +Warning (13024): Output pins are stuck at VCC or GND + Warning (13410): Pin "led_display1[5]" is stuck at GND + Warning (13410): Pin "led_display1[4]" is stuck at GND + Warning (13410): Pin "led_display2[6]" is stuck at VCC + Warning (13410): Pin "led_display2[4]" is stuck at GND + Warning (13410): Pin "led_display2[3]" is stuck at GND + Warning (13410): Pin "led_display2[2]" is stuck at GND + Warning (13410): Pin "led_display2[1]" is stuck at GND + Warning (13410): Pin "led_display3[4]" is stuck at VCC + Warning (13410): Pin "led_display3[2]" is stuck at GND + Warning (13410): Pin "led_display4[5]" is stuck at GND + Warning (13410): Pin "led_display4[4]" is stuck at GND +Info (16010): Generating hard_block partition "hard_block:auto_generated_inst" + Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL +Info (21057): Implemented 102 device resources after synthesis - the final resource count might be different + Info (21058): Implemented 15 input pins + Info (21059): Implemented 40 output pins + Info (21061): Implemented 47 logic cells +Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 12 warnings + Info: Peak virtual memory: 582 megabytes + Info: Processing ended: Wed Nov 29 18:54:27 2017 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:03 + + diff --git a/lab5/output_files/gA6_lab5.map.summary b/lab5/output_files/gA6_lab5.map.summary new file mode 100644 index 0000000..861e552 --- /dev/null +++ b/lab5/output_files/gA6_lab5.map.summary @@ -0,0 +1,14 @@ +Analysis & Synthesis Status : Successful - Wed Nov 29 18:54:27 2017 +Quartus II 64-Bit Version : 13.0.0 Build 156 04/24/2013 SJ Web Edition +Revision Name : gA6_lab5 +Top-level Entity Name : gA6_lab5 +Family : Cyclone II +Total logic elements : 45 + Total combinational functions : 36 + Dedicated logic registers : 17 +Total registers : 17 +Total pins : 55 +Total virtual pins : 0 +Total memory bits : 0 +Embedded Multiplier 9-bit elements : 0 +Total PLLs : 0 diff --git a/lab5/output_files/gA6_lab5.pin b/lab5/output_files/gA6_lab5.pin new file mode 100644 index 0000000..1519d0a --- /dev/null +++ b/lab5/output_files/gA6_lab5.pin @@ -0,0 +1,554 @@ + -- Copyright (C) 1991-2013 Altera Corporation + -- Your use of Altera Corporation's design tools, logic functions + -- and other software and tools, and its AMPP partner logic + -- functions, and any output files from any of the foregoing + -- (including device programming or simulation files), and any + -- associated documentation or information are expressly subject + -- to the terms and conditions of the Altera Program License + -- Subscription Agreement, Altera MegaCore Function License + -- Agreement, or other applicable license agreement, including, + -- without limitation, that your use is for the sole purpose of + -- programming logic devices manufactured by Altera and sold by + -- Altera or its authorized distributors. Please refer to the + -- applicable agreement for further details. + -- + -- This is a Quartus II output file. It is for reporting purposes only, and is + -- not intended for use as a Quartus II input file. This file cannot be used + -- to make Quartus II pin assignments - for instructions on how to make pin + -- assignments, please see Quartus II help. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- NC : No Connect. This pin has no internal connection to the device. + -- DNU : Do Not Use. This pin MUST NOT be connected. + -- VCCINT : Dedicated power pin, which MUST be connected to VCC (1.2V). + -- VCCIO : Dedicated power pin, which MUST be connected to VCC + -- of its bank. + -- Bank 1: 3.3V + -- Bank 2: 3.3V + -- Bank 3: 3.3V + -- Bank 4: 3.3V + -- Bank 5: 3.3V + -- Bank 6: 3.3V + -- Bank 7: 3.3V + -- Bank 8: 3.3V + -- GND : Dedicated ground pin. Dedicated GND pins MUST be connected to GND. + -- It can also be used to report unused dedicated pins. The connection + -- on the board for unused dedicated pins depends on whether this will + -- be used in a future design. One example is device migration. When + -- using device migration, refer to the device pin-tables. If it is a + -- GND pin in the pin table or if it will not be used in a future design + -- for another purpose the it MUST be connected to GND. If it is an unused + -- dedicated pin, then it can be connected to a valid signal on the board + -- (low, high, or toggling) if that signal is required for a different + -- revision of the design. + -- GND+ : Unused input pin. It can also be used to report unused dual-purpose pins. + -- This pin should be connected to GND. It may also be connected to a + -- valid signal on the board (low, high, or toggling) if that signal + -- is required for a different revision of the design. + -- GND* : Unused I/O pin. Connect each pin marked GND* directly to GND + -- or leave it unconnected. + -- RESERVED : Unused I/O pin, which MUST be left unconnected. + -- RESERVED_INPUT : Pin is tri-stated and should be connected to the board. + -- RESERVED_INPUT_WITH_WEAK_PULLUP : Pin is tri-stated with internal weak pull-up resistor. + -- RESERVED_INPUT_WITH_BUS_HOLD : Pin is tri-stated with bus-hold circuitry. + -- RESERVED_OUTPUT_DRIVEN_HIGH : Pin is output driven high. + --------------------------------------------------------------------------------- + + + + --------------------------------------------------------------------------------- + -- Pin directions (input, output or bidir) are based on device operating in user mode. + --------------------------------------------------------------------------------- + +Quartus II 64-Bit Version 13.0.0 Build 156 04/24/2013 SJ Web Edition +CHIP "gA6_lab5" ASSIGNED TO AN: EP2C20F484C7 + +Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment +------------------------------------------------------------------------------------------------------------- +GND : A1 : gnd : : : : +VCCIO3 : A2 : power : : 3.3V : 3 : +GND* : A3 : : : : 3 : +GND* : A4 : : : : 3 : +GND* : A5 : : : : 3 : +GND* : A6 : : : : 3 : +GND* : A7 : : : : 3 : +GND* : A8 : : : : 3 : +GND* : A9 : : : : 3 : +GND* : A10 : : : : 3 : +GND* : A11 : : : : 3 : +GND+ : A12 : : : : 4 : +GND* : A13 : : : : 4 : +GND* : A14 : : : : 4 : +GND* : A15 : : : : 4 : +GND* : A16 : : : : 4 : +GND* : A17 : : : : 4 : +GND* : A18 : : : : 4 : +GND* : A19 : : : : 4 : +GND* : A20 : : : : 4 : +VCCIO4 : A21 : power : : 3.3V : 4 : +GND : A22 : gnd : : : : +VCCIO1 : AA1 : power : : 3.3V : 1 : +GND : AA2 : gnd : : : : +player_sum[2] : AA3 : input : 3.3-V LVTTL : : 8 : N +sum_out[3] : AA4 : output : 3.3-V LVTTL : : 8 : N +sum[0] : AA5 : input : 3.3-V LVTTL : : 8 : N +player_sum[1] : AA6 : input : 3.3-V LVTTL : : 8 : N +led_display4[1] : AA7 : output : 3.3-V LVTTL : : 8 : N +GND* : AA8 : : : : 8 : +GND* : AA9 : : : : 8 : +GND* : AA10 : : : : 8 : +GND* : AA11 : : : : 8 : +GND* : AA12 : : : : 7 : +GND* : AA13 : : : : 7 : +GND* : AA14 : : : : 7 : +GND* : AA15 : : : : 7 : +led_display2[1] : AA16 : output : 3.3-V LVTTL : : 7 : N +GND* : AA17 : : : : 7 : +GND* : AA18 : : : : 7 : +GND* : AA19 : : : : 7 : +GND* : AA20 : : : : 7 : +GND : AA21 : gnd : : : : +VCCIO6 : AA22 : power : : 3.3V : 6 : +GND : AB1 : gnd : : : : +VCCIO8 : AB2 : power : : 3.3V : 8 : +player_sum[5] : AB3 : input : 3.3-V LVTTL : : 8 : N +sum_out[0] : AB4 : output : 3.3-V LVTTL : : 8 : N +sum[2] : AB5 : input : 3.3-V LVTTL : : 8 : N +state_out[0] : AB6 : output : 3.3-V LVTTL : : 8 : N +led_display2[0] : AB7 : output : 3.3-V LVTTL : : 8 : N +GND* : AB8 : : : : 8 : +GND* : AB9 : : : : 8 : +GND* : AB10 : : : : 8 : +GND* : AB11 : : : : 8 : +GND* : AB12 : : : : 7 : +GND* : AB13 : : : : 7 : +GND* : AB14 : : : : 7 : +GND* : AB15 : : : : 7 : +GND* : AB16 : : : : 7 : +GND* : AB17 : : : : 7 : +GND* : AB18 : : : : 7 : +GND* : AB19 : : : : 7 : +GND* : AB20 : : : : 7 : +VCCIO7 : AB21 : power : : 3.3V : 7 : +GND : AB22 : gnd : : : : +VCCIO2 : B1 : power : : 3.3V : 2 : +GND : B2 : gnd : : : : +GND* : B3 : : : : 3 : +GND* : B4 : : : : 3 : +GND* : B5 : : : : 3 : +GND* : B6 : : : : 3 : +GND* : B7 : : : : 3 : +GND* : B8 : : : : 3 : +GND* : B9 : : : : 3 : +GND* : B10 : : : : 3 : +led_display2[2] : B11 : output : 3.3-V LVTTL : : 3 : N +GND+ : B12 : : : : 4 : +GND* : B13 : : : : 4 : +led_display2[6] : B14 : output : 3.3-V LVTTL : : 4 : N +GND* : B15 : : : : 4 : +GND* : B16 : : : : 4 : +led_display1[5] : B17 : output : 3.3-V LVTTL : : 4 : N +GND* : B18 : : : : 4 : +GND* : B19 : : : : 4 : +GND* : B20 : : : : 4 : +GND : B21 : gnd : : : : +VCCIO5 : B22 : power : : 3.3V : 5 : +GND* : C1 : : : : 2 : +GND* : C2 : : : : 2 : +~nCSO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C3 : input : 3.3-V LVTTL : : 2 : N +~ASDO~ / RESERVED_INPUT_WITH_WEAK_PULLUP : C4 : input : 3.3-V LVTTL : : 2 : N +GND : C5 : gnd : : : : +VCCIO3 : C6 : power : : 3.3V : 3 : +led_display3[4] : C7 : output : 3.3-V LVTTL : : 3 : N +GND : C8 : gnd : : : : +GND* : C9 : : : : 3 : +GND* : C10 : : : : 3 : +VCCIO3 : C11 : power : : 3.3V : 3 : +VCCIO4 : C12 : power : : 3.3V : 4 : +GND* : C13 : : : : 4 : +GND* : C14 : : : : 4 : +GND : C15 : gnd : : : : +GND* : C16 : : : : 4 : +GND* : C17 : : : : 4 : +GND* : C18 : : : : 4 : +GND* : C19 : : : : 5 : +GND* : C20 : : : : 5 : +led_display3[2] : C21 : output : 3.3-V LVTTL : : 5 : N +GND* : C22 : : : : 5 : +GND* : D1 : : : : 2 : +led_display4[4] : D2 : output : 3.3-V LVTTL : : 2 : N +GND* : D3 : : : : 2 : +GND* : D4 : : : : 2 : +GND* : D5 : : : : 2 : +GND* : D6 : : : : 2 : +GND* : D7 : : : : 3 : +GND* : D8 : : : : 3 : +GND* : D9 : : : : 3 : +GND : D10 : gnd : : : : +GND* : D11 : : : : 3 : +GND+ : D12 : : : : 3 : +GND : D13 : gnd : : : : +GND* : D14 : : : : 4 : +GND* : D15 : : : : 4 : +GND* : D16 : : : : 4 : +VCCIO4 : D17 : power : : 3.3V : 4 : +GND : D18 : gnd : : : : +GND* : D19 : : : : 5 : +GND* : D20 : : : : 5 : +GND* : D21 : : : : 5 : +GND* : D22 : : : : 5 : +GND* : E1 : : : : 2 : +GND* : E2 : : : : 2 : +GND* : E3 : : : : 2 : +GND* : E4 : : : : 2 : +VCCD_PLL3 : E5 : power : : 1.2V : : +VCCA_PLL3 : E6 : power : : 1.2V : : +GND* : E7 : : : : 3 : +GND* : E8 : : : : 3 : +GND* : E9 : : : : 3 : +VCCIO3 : E10 : power : : 3.3V : 3 : +GND* : E11 : : : : 3 : +GND+ : E12 : : : : 3 : +VCCIO4 : E13 : power : : 3.3V : 4 : +GND* : E14 : : : : 4 : +GND* : E15 : : : : 4 : +GNDA_PLL2 : E16 : gnd : : : : +GND_PLL2 : E17 : gnd : : : : +GND* : E18 : : : : 5 : +GND* : E19 : : : : 5 : +GND* : E20 : : : : 5 : +GND* : E21 : : : : 5 : +GND* : E22 : : : : 5 : +GND* : F1 : : : : 2 : +GND* : F2 : : : : 2 : +GND* : F3 : : : : 2 : +GND* : F4 : : : : 2 : +GND_PLL3 : F5 : gnd : : : : +GND_PLL3 : F6 : gnd : : : : +GNDA_PLL3 : F7 : gnd : : : : +GND* : F8 : : : : 3 : +GND* : F9 : : : : 3 : +GND* : F10 : : : : 3 : +GND* : F11 : : : : 3 : +GND* : F12 : : : : 4 : +GND* : F13 : : : : 4 : +GND* : F14 : : : : 4 : +GND* : F15 : : : : 4 : +VCCA_PLL2 : F16 : power : : 1.2V : : +VCCD_PLL2 : F17 : power : : 1.2V : : +GND_PLL2 : F18 : gnd : : : : +GND : F19 : gnd : : : : +GND* : F20 : : : : 5 : +GND* : F21 : : : : 5 : +GND* : F22 : : : : 5 : +NC : G1 : : : : : +NC : G2 : : : : : +GND* : G3 : : : : 2 : +GND : G4 : gnd : : : : +GND* : G5 : : : : 2 : +GND* : G6 : : : : 2 : +GND* : G7 : : : : 3 : +led_display4[5] : G8 : output : 3.3-V LVTTL : : 3 : N +VCCIO3 : G9 : power : : 3.3V : 3 : +GND : G10 : gnd : : : : +GND* : G11 : : : : 3 : +GND* : G12 : : : : 4 : +GND : G13 : gnd : : : : +VCCIO4 : G14 : power : : 3.3V : 4 : +GND* : G15 : : : : 4 : +GND* : G16 : : : : 4 : +GND* : G17 : : : : 5 : +GND* : G18 : : : : 5 : +VCCIO5 : G19 : power : : 3.3V : 5 : +GND* : G20 : : : : 5 : +GND* : G21 : : : : 5 : +GND* : G22 : : : : 5 : +GND* : H1 : : : : 2 : +GND* : H2 : : : : 2 : +GND* : H3 : : : : 2 : +GND* : H4 : : : : 2 : +GND* : H5 : : : : 2 : +GND* : H6 : : : : 2 : +GND* : H7 : : : : 3 : +GND* : H8 : : : : 3 : +GND* : H9 : : : : 3 : +GND* : H10 : : : : 3 : +GND* : H11 : : : : 3 : +GND* : H12 : : : : 4 : +GND* : H13 : : : : 4 : +GND* : H14 : : : : 4 : +led_display2[3] : H15 : output : 3.3-V LVTTL : : 4 : N +GND* : H16 : : : : 5 : +GND* : H17 : : : : 5 : +GND* : H18 : : : : 5 : +GND* : H19 : : : : 5 : +GND : H20 : gnd : : : : +NC : H21 : : : : : +NC : H22 : : : : : +GND* : J1 : : : : 2 : +GND* : J2 : : : : 2 : +NC : J3 : : : : : +GND* : J4 : : : : 2 : +NC : J5 : : : : : +NC : J6 : : : : : +VCCIO2 : J7 : power : : 3.3V : 2 : +NC : J8 : : : : : +NC : J9 : : : : : +VCCINT : J10 : power : : 1.2V : : +VCCINT : J11 : power : : 1.2V : : +VCCINT : J12 : power : : 1.2V : : +VCCINT : J13 : power : : 1.2V : : +GND* : J14 : : : : 4 : +GND* : J15 : : : : 5 : +VCCIO5 : J16 : power : : 3.3V : 5 : +GND* : J17 : : : : 5 : +GND* : J18 : : : : 5 : +GND* : J19 : : : : 5 : +GND* : J20 : : : : 5 : +GND* : J21 : : : : 5 : +GND* : J22 : : : : 5 : +nCE : K1 : : : : 2 : +TCK : K2 : input : : : 2 : +GND : K3 : gnd : : : : +DATA0 : K4 : input : : : 2 : +TDI : K5 : input : : : 2 : +TMS : K6 : input : : : 2 : +GND : K7 : gnd : : : : +NC : K8 : : : : : +VCCINT : K9 : power : : 1.2V : : +GND : K10 : gnd : : : : +GND : K11 : gnd : : : : +GND : K12 : gnd : : : : +GND : K13 : gnd : : : : +VCCINT : K14 : power : : 1.2V : : +NC : K15 : : : : : +GND : K16 : gnd : : : : +NC : K17 : : : : : +NC : K18 : : : : : +GND : K19 : gnd : : : : +GND* : K20 : : : : 5 : +GND* : K21 : : : : 5 : +GND* : K22 : : : : 5 : +GND+ : L1 : : : : 2 : +GND+ : L2 : : : : 2 : +VCCIO2 : L3 : power : : 3.3V : 2 : +nCONFIG : L4 : : : : 2 : +TDO : L5 : output : : : 2 : +DCLK : L6 : : : : 2 : +NC : L7 : : : : : +GND* : L8 : : : : 2 : +VCCINT : L9 : power : : 1.2V : : +GND : L10 : gnd : : : : +GND : L11 : gnd : : : : +GND : L12 : gnd : : : : +GND : L13 : gnd : : : : +VCCINT : L14 : power : : 1.2V : : +NC : L15 : : : : : +NC : L16 : : : : : +NC : L17 : : : : : +GND* : L18 : : : : 5 : +GND* : L19 : : : : 5 : +VCCIO5 : L20 : power : : 3.3V : 5 : +GND+ : L21 : : : : 5 : +GND+ : L22 : : : : 5 : +clk : M1 : input : 3.3-V LVTTL : : 1 : N +rst : M2 : input : 3.3-V LVTTL : : 1 : N +VCCIO1 : M3 : power : : 3.3V : 1 : +GND : M4 : gnd : : : : +GND* : M5 : : : : 1 : +GND* : M6 : : : : 1 : +NC : M7 : : : : : +NC : M8 : : : : : +VCCINT : M9 : power : : 1.2V : : +GND : M10 : gnd : : : : +GND : M11 : gnd : : : : +GND : M12 : gnd : : : : +GND : M13 : gnd : : : : +VCCINT : M14 : power : : 1.2V : : +NC : M15 : : : : : +NC : M16 : : : : : +MSEL0 : M17 : : : : 6 : +GND* : M18 : : : : 6 : +GND* : M19 : : : : 6 : +VCCIO6 : M20 : power : : 3.3V : 6 : +GND+ : M21 : : : : 6 : +GND+ : M22 : : : : 6 : +GND* : N1 : : : : 1 : +GND* : N2 : : : : 1 : +GND* : N3 : : : : 1 : +GND* : N4 : : : : 1 : +NC : N5 : : : : : +GND* : N6 : : : : 1 : +GND : N7 : gnd : : : : +NC : N8 : : : : : +VCCINT : N9 : power : : 1.2V : : +GND : N10 : gnd : : : : +GND : N11 : gnd : : : : +GND : N12 : gnd : : : : +GND : N13 : gnd : : : : +VCCINT : N14 : power : : 1.2V : : +GND* : N15 : : : : 6 : +GND : N16 : gnd : : : : +MSEL1 : N17 : : : : 6 : +CONF_DONE : N18 : : : : 6 : +GND : N19 : gnd : : : : +nSTATUS : N20 : : : : 6 : +GND* : N21 : : : : 6 : +GND* : N22 : : : : 6 : +GND* : P1 : : : : 1 : +GND* : P2 : : : : 1 : +GND* : P3 : : : : 1 : +NC : P4 : : : : : +GND* : P5 : : : : 1 : +GND* : P6 : : : : 1 : +VCCIO1 : P7 : power : : 3.3V : 1 : +led_display4[2] : P8 : output : 3.3-V LVTTL : : 8 : N +led_display4[3] : P9 : output : 3.3-V LVTTL : : 8 : N +VCCINT : P10 : power : : 1.2V : : +VCCINT : P11 : power : : 1.2V : : +VCCINT : P12 : power : : 1.2V : : +VCCINT : P13 : power : : 1.2V : : +NC : P14 : : : : : +GND* : P15 : : : : 6 : +VCCIO6 : P16 : power : : 3.3V : 6 : +GND* : P17 : : : : 6 : +GND* : P18 : : : : 6 : +NC : P19 : : : : : +NC : P20 : : : : : +NC : P21 : : : : : +NC : P22 : : : : : +GND* : R1 : : : : 1 : +GND* : R2 : : : : 1 : +GND : R3 : gnd : : : : +NC : R4 : : : : : +led_display1[0] : R5 : output : 3.3-V LVTTL : : 1 : N +led_display1[6] : R6 : output : 3.3-V LVTTL : : 1 : N +GND* : R7 : : : : 1 : +GND* : R8 : : : : 1 : +GND* : R9 : : : : 8 : +GND* : R10 : : : : 8 : +GND* : R11 : : : : 8 : +GND* : R12 : : : : 7 : +GND* : R13 : : : : 7 : +GND* : R14 : : : : 7 : +GND* : R15 : : : : 7 : +GND* : R16 : : : : 7 : +GND* : R17 : : : : 6 : +GND* : R18 : : : : 6 : +GND* : R19 : : : : 6 : +GND* : R20 : : : : 6 : +GND* : R21 : : : : 6 : +GND* : R22 : : : : 6 : +GND* : T1 : : : : 1 : +GND* : T2 : : : : 1 : +led_display1[3] : T3 : output : 3.3-V LVTTL : : 1 : N +VCCIO1 : T4 : power : : 3.3V : 1 : +led_display2[5] : T5 : output : 3.3-V LVTTL : : 1 : N +led_display3[6] : T6 : output : 3.3-V LVTTL : : 1 : N +sum_out[1] : T7 : output : 3.3-V LVTTL : : 8 : N +sum_out[2] : T8 : output : 3.3-V LVTTL : : 8 : N +VCCIO8 : T9 : power : : 3.3V : 8 : +GND : T10 : gnd : : : : +GND* : T11 : : : : 8 : +GND* : T12 : : : : 7 : +GND : T13 : gnd : : : : +VCCIO7 : T14 : power : : 3.3V : 7 : +led_display1[4] : T15 : output : 3.3-V LVTTL : : 7 : N +GND* : T16 : : : : 7 : +GND_PLL4 : T17 : gnd : : : : +GND* : T18 : : : : 6 : +VCCIO6 : T19 : power : : 3.3V : 6 : +GND : T20 : gnd : : : : +GND* : T21 : : : : 6 : +GND* : T22 : : : : 6 : +led_display4[0] : U1 : output : 3.3-V LVTTL : : 1 : N +led_display1[1] : U2 : output : 3.3-V LVTTL : : 1 : N +led_display3[5] : U3 : output : 3.3-V LVTTL : : 1 : N +sum_out[5] : U4 : output : 3.3-V LVTTL : : 1 : N +GND_PLL1 : U5 : gnd : : : : +VCCD_PLL1 : U6 : power : : 1.2V : : +VCCA_PLL1 : U7 : power : : 1.2V : : +sum[5] : U8 : input : 3.3-V LVTTL : : 8 : N +GND* : U9 : : : : 8 : +GND* : U10 : : : : 8 : +GND+ : U11 : : : : 8 : +GND+ : U12 : : : : 8 : +GND* : U13 : : : : 7 : +GND* : U14 : : : : 7 : +GND* : U15 : : : : 7 : +VCCA_PLL4 : U16 : power : : 1.2V : : +VCCD_PLL4 : U17 : power : : 1.2V : : +GND* : U18 : : : : 6 : +GND* : U19 : : : : 6 : +GND* : U20 : : : : 6 : +GND* : U21 : : : : 6 : +GND* : U22 : : : : 6 : +GND* : V1 : : : : 1 : +led_display3[0] : V2 : output : 3.3-V LVTTL : : 1 : N +GND : V3 : gnd : : : : +player_sum[4] : V4 : input : 3.3-V LVTTL : : 1 : N +GND_PLL1 : V5 : gnd : : : : +GND : V6 : gnd : : : : +GNDA_PLL1 : V7 : gnd : : : : +state_out[1] : V8 : output : 3.3-V LVTTL : : 8 : N +done : V9 : output : 3.3-V LVTTL : : 8 : N +VCCIO8 : V10 : power : : 3.3V : 8 : +GND* : V11 : : : : 8 : +GND+ : V12 : : : : 7 : +VCCIO7 : V13 : power : : 3.3V : 7 : +GND* : V14 : : : : 7 : +GND* : V15 : : : : 7 : +GNDA_PLL4 : V16 : gnd : : : : +GND : V17 : gnd : : : : +GND_PLL4 : V18 : gnd : : : : +GND* : V19 : : : : 6 : +GND* : V20 : : : : 6 : +GND* : V21 : : : : 6 : +GND* : V22 : : : : 6 : +led_display3[3] : W1 : output : 3.3-V LVTTL : : 1 : N +led_display4[6] : W2 : output : 3.3-V LVTTL : : 1 : N +dealer_wins : W3 : output : 3.3-V LVTTL : : 1 : N +player_wins : W4 : output : 3.3-V LVTTL : : 1 : N +sum_out[4] : W5 : output : 3.3-V LVTTL : : 1 : N +VCCIO8 : W6 : power : : 3.3V : 8 : +hit : W7 : output : 3.3-V LVTTL : : 8 : N +turn : W8 : input : 3.3-V LVTTL : : 8 : N +led_display2[4] : W9 : output : 3.3-V LVTTL : : 8 : N +GND : W10 : gnd : : : : +GND* : W11 : : : : 8 : +GND+ : W12 : : : : 7 : +GND : W13 : gnd : : : : +GND* : W14 : : : : 7 : +GND* : W15 : : : : 7 : +GND* : W16 : : : : 7 : +VCCIO7 : W17 : power : : 3.3V : 7 : +NC : W18 : : : : : +GND : W19 : gnd : : : : +~LVDS91p/nCEO~ : W20 : output : 3.3-V LVTTL : : 6 : N +GND* : W21 : : : : 6 : +GND* : W22 : : : : 6 : +led_display3[1] : Y1 : output : 3.3-V LVTTL : : 1 : N +led_display1[2] : Y2 : output : 3.3-V LVTTL : : 1 : N +sum[1] : Y3 : input : 3.3-V LVTTL : : 1 : N +player_sum[0] : Y4 : input : 3.3-V LVTTL : : 1 : N +sum[3] : Y5 : input : 3.3-V LVTTL : : 8 : N +sum[4] : Y6 : input : 3.3-V LVTTL : : 8 : N +player_sum[3] : Y7 : input : 3.3-V LVTTL : : 8 : N +GND : Y8 : gnd : : : : +GND* : Y9 : : : : 8 : +GND* : Y10 : : : : 8 : +VCCIO8 : Y11 : power : : 3.3V : 8 : +VCCIO7 : Y12 : power : : 3.3V : 7 : +GND* : Y13 : : : : 7 : +GND* : Y14 : : : : 7 : +GND : Y15 : gnd : : : : +GND* : Y16 : : : : 7 : +GND* : Y17 : : : : 7 : +GND* : Y18 : : : : 6 : +GND* : Y19 : : : : 6 : +GND* : Y20 : : : : 6 : +GND* : Y21 : : : : 6 : +GND* : Y22 : : : : 6 : diff --git a/lab5/output_files/gA6_lab5.pof b/lab5/output_files/gA6_lab5.pof new file mode 100644 index 0000000..86c799f Binary files /dev/null and b/lab5/output_files/gA6_lab5.pof differ diff --git a/lab5/output_files/gA6_lab5.sof b/lab5/output_files/gA6_lab5.sof new file mode 100644 index 0000000..7e71b09 Binary files /dev/null and b/lab5/output_files/gA6_lab5.sof differ diff --git a/lab5/output_files/gA6_lab5.sta.rpt b/lab5/output_files/gA6_lab5.sta.rpt new file mode 100644 index 0000000..6579e56 --- /dev/null +++ b/lab5/output_files/gA6_lab5.sta.rpt @@ -0,0 +1,1149 @@ +TimeQuest Timing Analyzer report for gA6_lab5 +Wed Nov 29 18:54:43 2017 +Quartus II 64-Bit Version 13.0.0 Build 156 04/24/2013 SJ Web Edition + + +--------------------- +; Table of Contents ; +--------------------- + 1. Legal Notice + 2. TimeQuest Timing Analyzer Summary + 3. Parallel Compilation + 4. Clocks + 5. Slow Model Fmax Summary + 6. Slow Model Setup Summary + 7. Slow Model Hold Summary + 8. Slow Model Recovery Summary + 9. Slow Model Removal Summary + 10. Slow Model Minimum Pulse Width Summary + 11. Slow Model Setup: 'clk' + 12. Slow Model Hold: 'clk' + 13. Slow Model Minimum Pulse Width: 'clk' + 14. Setup Times + 15. Hold Times + 16. Clock to Output Times + 17. Minimum Clock to Output Times + 18. Fast Model Setup Summary + 19. Fast Model Hold Summary + 20. Fast Model Recovery Summary + 21. Fast Model Removal Summary + 22. Fast Model Minimum Pulse Width Summary + 23. Fast Model Setup: 'clk' + 24. Fast Model Hold: 'clk' + 25. Fast Model Minimum Pulse Width: 'clk' + 26. Setup Times + 27. Hold Times + 28. Clock to Output Times + 29. Minimum Clock to Output Times + 30. Multicorner Timing Analysis Summary + 31. Setup Times + 32. Hold Times + 33. Clock to Output Times + 34. Minimum Clock to Output Times + 35. Setup Transfers + 36. Hold Transfers + 37. Report TCCS + 38. Report RSKM + 39. Unconstrained Paths + 40. TimeQuest Timing Analyzer Messages + + + +---------------- +; Legal Notice ; +---------------- +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. + + + ++-------------------------------------------------------------------------+ +; TimeQuest Timing Analyzer Summary ; ++--------------------+----------------------------------------------------+ +; Quartus II Version ; Version 13.0.0 Build 156 04/24/2013 SJ Web Edition ; +; Revision Name ; gA6_lab5 ; +; Device Family ; Cyclone II ; +; Device Name ; EP2C20F484C7 ; +; Timing Models ; Final ; +; Delay Model ; Combined ; +; Rise/Fall Delays ; Unavailable ; ++--------------------+----------------------------------------------------+ + + ++------------------------------------------+ +; Parallel Compilation ; ++----------------------------+-------------+ +; Processors ; Number ; ++----------------------------+-------------+ +; Number detected on machine ; 4 ; +; Maximum allowed ; 2 ; +; ; ; +; Average used ; 1.00 ; +; Maximum used ; 1 ; +; ; ; +; Usage by Processor ; % Time Used ; +; Processor 1 ; 100.0% ; +; Processors 2-4 ; 0.0% ; ++----------------------------+-------------+ + + ++---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Clocks ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+ +; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+ +; clk ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { clk } ; ++------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+---------+ + + ++--------------------------------------------------+ +; Slow Model Fmax Summary ; ++------------+-----------------+------------+------+ +; Fmax ; Restricted Fmax ; Clock Name ; Note ; ++------------+-----------------+------------+------+ +; 195.39 MHz ; 195.39 MHz ; clk ; ; ++------------+-----------------+------------+------+ +This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis. + + ++--------------------------------+ +; Slow Model Setup Summary ; ++-------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+--------+---------------+ +; clk ; -4.118 ; -25.738 ; ++-------+--------+---------------+ + + ++-------------------------------+ +; Slow Model Hold Summary ; ++-------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+-------+---------------+ +; clk ; 0.445 ; 0.000 ; ++-------+-------+---------------+ + + +------------------------------- +; Slow Model Recovery Summary ; +------------------------------- +No paths to report. + + +------------------------------ +; Slow Model Removal Summary ; +------------------------------ +No paths to report. + + ++----------------------------------------+ +; Slow Model Minimum Pulse Width Summary ; ++-------+--------+-----------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+--------+-----------------------+ +; clk ; -1.631 ; -22.405 ; ++-------+--------+-----------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow Model Setup: 'clk' ; ++--------+--------------------------------------+--------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+--------------------------------------+--------------------------------------+--------------+-------------+--------------+------------+------------+ +; -4.118 ; gA6_computer:inst|sum_out[0] ; gA6_winner:inst1|led_display1[0] ; clk ; clk ; 1.000 ; -0.001 ; 5.155 ; +; -4.118 ; gA6_computer:inst|sum_out[0] ; gA6_winner:inst1|led_display3[1] ; clk ; clk ; 1.000 ; -0.001 ; 5.155 ; +; -4.118 ; gA6_computer:inst|sum_out[0] ; gA6_winner:inst1|led_display4[3] ; clk ; clk ; 1.000 ; -0.001 ; 5.155 ; +; -4.042 ; gA6_computer:inst|sum_out[1] ; gA6_winner:inst1|led_display1[0] ; clk ; clk ; 1.000 ; -0.001 ; 5.079 ; +; -4.042 ; gA6_computer:inst|sum_out[1] ; gA6_winner:inst1|led_display3[1] ; clk ; clk ; 1.000 ; -0.001 ; 5.079 ; +; -4.042 ; gA6_computer:inst|sum_out[1] ; gA6_winner:inst1|led_display4[3] ; clk ; clk ; 1.000 ; -0.001 ; 5.079 ; +; -4.023 ; gA6_computer:inst|sum_out[2] ; gA6_winner:inst1|led_display1[0] ; clk ; clk ; 1.000 ; -0.001 ; 5.060 ; +; -4.023 ; gA6_computer:inst|sum_out[2] ; gA6_winner:inst1|led_display3[1] ; clk ; clk ; 1.000 ; -0.001 ; 5.060 ; +; -4.023 ; gA6_computer:inst|sum_out[2] ; gA6_winner:inst1|led_display4[3] ; clk ; clk ; 1.000 ; -0.001 ; 5.060 ; +; -3.948 ; gA6_computer:inst|sum_out[3] ; gA6_winner:inst1|led_display1[0] ; clk ; clk ; 1.000 ; -0.001 ; 4.985 ; +; -3.948 ; gA6_computer:inst|sum_out[3] ; gA6_winner:inst1|led_display3[1] ; clk ; clk ; 1.000 ; -0.001 ; 4.985 ; +; -3.948 ; gA6_computer:inst|sum_out[3] ; gA6_winner:inst1|led_display4[3] ; clk ; clk ; 1.000 ; -0.001 ; 4.985 ; +; -3.794 ; gA6_computer:inst|sum_out[4] ; gA6_winner:inst1|led_display1[0] ; clk ; clk ; 1.000 ; -0.001 ; 4.831 ; +; -3.794 ; gA6_computer:inst|sum_out[4] ; gA6_winner:inst1|led_display3[1] ; clk ; clk ; 1.000 ; -0.001 ; 4.831 ; +; -3.794 ; gA6_computer:inst|sum_out[4] ; gA6_winner:inst1|led_display4[3] ; clk ; clk ; 1.000 ; -0.001 ; 4.831 ; +; -3.555 ; gA6_computer:inst|sum_out[0] ; gA6_winner:inst1|player_wins ; clk ; clk ; 1.000 ; -0.001 ; 4.592 ; +; -3.489 ; gA6_computer:inst|sum_out[0] ; gA6_winner:inst1|\dealer:d_win ; clk ; clk ; 1.000 ; -0.001 ; 4.526 ; +; -3.477 ; gA6_computer:inst|sum_out[1] ; gA6_winner:inst1|player_wins ; clk ; clk ; 1.000 ; -0.001 ; 4.514 ; +; -3.456 ; gA6_computer:inst|sum_out[2] ; gA6_winner:inst1|player_wins ; clk ; clk ; 1.000 ; -0.001 ; 4.493 ; +; -3.413 ; gA6_computer:inst|sum_out[1] ; gA6_winner:inst1|\dealer:d_win ; clk ; clk ; 1.000 ; -0.001 ; 4.450 ; +; -3.394 ; gA6_computer:inst|sum_out[2] ; gA6_winner:inst1|\dealer:d_win ; clk ; clk ; 1.000 ; -0.001 ; 4.431 ; +; -3.375 ; gA6_computer:inst|sum_out[3] ; gA6_winner:inst1|player_wins ; clk ; clk ; 1.000 ; -0.001 ; 4.412 ; +; -3.319 ; gA6_computer:inst|sum_out[3] ; gA6_winner:inst1|\dealer:d_win ; clk ; clk ; 1.000 ; -0.001 ; 4.356 ; +; -3.226 ; gA6_computer:inst|sum_out[4] ; gA6_winner:inst1|player_wins ; clk ; clk ; 1.000 ; -0.001 ; 4.263 ; +; -3.165 ; gA6_computer:inst|sum_out[4] ; gA6_winner:inst1|\dealer:d_win ; clk ; clk ; 1.000 ; -0.001 ; 4.202 ; +; -3.077 ; gA6_computer:inst|sum_out[0] ; gA6_winner:inst1|\dealer:p_win ; clk ; clk ; 1.000 ; -0.001 ; 4.114 ; +; -3.040 ; gA6_computer:inst|sum_out[5] ; gA6_winner:inst1|led_display1[0] ; clk ; clk ; 1.000 ; -0.001 ; 4.077 ; +; -3.040 ; gA6_computer:inst|sum_out[5] ; gA6_winner:inst1|led_display3[1] ; clk ; clk ; 1.000 ; -0.001 ; 4.077 ; +; -3.040 ; gA6_computer:inst|sum_out[5] ; gA6_winner:inst1|led_display4[3] ; clk ; clk ; 1.000 ; -0.001 ; 4.077 ; +; -2.999 ; gA6_computer:inst|sum_out[1] ; gA6_winner:inst1|\dealer:p_win ; clk ; clk ; 1.000 ; -0.001 ; 4.036 ; +; -2.978 ; gA6_computer:inst|sum_out[2] ; gA6_winner:inst1|\dealer:p_win ; clk ; clk ; 1.000 ; -0.001 ; 4.015 ; +; -2.897 ; gA6_computer:inst|sum_out[3] ; gA6_winner:inst1|\dealer:p_win ; clk ; clk ; 1.000 ; -0.001 ; 3.934 ; +; -2.870 ; gA6_computer:inst|sum_out[0] ; gA6_winner:inst1|dealer_wins ; clk ; clk ; 1.000 ; -0.001 ; 3.907 ; +; -2.794 ; gA6_computer:inst|sum_out[1] ; gA6_winner:inst1|dealer_wins ; clk ; clk ; 1.000 ; -0.001 ; 3.831 ; +; -2.775 ; gA6_computer:inst|sum_out[2] ; gA6_winner:inst1|dealer_wins ; clk ; clk ; 1.000 ; -0.001 ; 3.812 ; +; -2.748 ; gA6_computer:inst|sum_out[4] ; gA6_winner:inst1|\dealer:p_win ; clk ; clk ; 1.000 ; -0.001 ; 3.785 ; +; -2.700 ; gA6_computer:inst|sum_out[3] ; gA6_winner:inst1|dealer_wins ; clk ; clk ; 1.000 ; -0.001 ; 3.737 ; +; -2.546 ; gA6_computer:inst|sum_out[4] ; gA6_winner:inst1|dealer_wins ; clk ; clk ; 1.000 ; -0.001 ; 3.583 ; +; -2.470 ; gA6_computer:inst|sum_out[5] ; gA6_winner:inst1|player_wins ; clk ; clk ; 1.000 ; -0.001 ; 3.507 ; +; -2.411 ; gA6_computer:inst|sum_out[5] ; gA6_winner:inst1|\dealer:d_win ; clk ; clk ; 1.000 ; -0.001 ; 3.448 ; +; -2.326 ; gA6_winner:inst1|\dealer:p_win ; gA6_winner:inst1|led_display1[0] ; clk ; clk ; 1.000 ; 0.000 ; 3.364 ; +; -2.326 ; gA6_winner:inst1|\dealer:p_win ; gA6_winner:inst1|led_display3[1] ; clk ; clk ; 1.000 ; 0.000 ; 3.364 ; +; -2.326 ; gA6_winner:inst1|\dealer:p_win ; gA6_winner:inst1|led_display4[3] ; clk ; clk ; 1.000 ; 0.000 ; 3.364 ; +; -1.992 ; gA6_computer:inst|sum_out[5] ; gA6_winner:inst1|\dealer:p_win ; clk ; clk ; 1.000 ; -0.001 ; 3.029 ; +; -1.792 ; gA6_computer:inst|sum_out[5] ; gA6_winner:inst1|dealer_wins ; clk ; clk ; 1.000 ; -0.001 ; 2.829 ; +; -1.153 ; gA6_winner:inst1|\dealer:d_win ; gA6_winner:inst1|\dealer:d_win ; clk ; clk ; 1.000 ; 0.000 ; 2.191 ; +; -0.626 ; gA6_winner:inst1|\dealer:d_win ; gA6_winner:inst1|led_display1[0] ; clk ; clk ; 1.000 ; 0.000 ; 1.664 ; +; -0.626 ; gA6_winner:inst1|\dealer:d_win ; gA6_winner:inst1|led_display3[1] ; clk ; clk ; 1.000 ; 0.000 ; 1.664 ; +; -0.626 ; gA6_winner:inst1|\dealer:d_win ; gA6_winner:inst1|led_display4[3] ; clk ; clk ; 1.000 ; 0.000 ; 1.664 ; +; -0.534 ; gA6_winner:inst1|\dealer:d_win ; gA6_winner:inst1|dealer_wins ; clk ; clk ; 1.000 ; 0.000 ; 1.572 ; +; -0.255 ; gA6_computer:inst|\computer:state[1] ; gA6_computer:inst|hit ; clk ; clk ; 1.000 ; 0.000 ; 1.293 ; +; -0.171 ; gA6_winner:inst1|\dealer:p_win ; gA6_winner:inst1|player_wins ; clk ; clk ; 1.000 ; 0.000 ; 1.209 ; +; -0.138 ; gA6_computer:inst|\computer:state[0] ; gA6_computer:inst|done ; clk ; clk ; 1.000 ; 0.000 ; 1.176 ; +; 0.115 ; gA6_computer:inst|\computer:state[0] ; gA6_computer:inst|\computer:state[1] ; clk ; clk ; 1.000 ; 0.000 ; 0.923 ; +; 0.115 ; gA6_computer:inst|\computer:state[0] ; gA6_computer:inst|hit ; clk ; clk ; 1.000 ; 0.000 ; 0.923 ; +; 0.123 ; gA6_computer:inst|\computer:state[1] ; gA6_computer:inst|done ; clk ; clk ; 1.000 ; 0.000 ; 0.915 ; +; 0.124 ; gA6_computer:inst|\computer:state[1] ; gA6_computer:inst|\computer:state[0] ; clk ; clk ; 1.000 ; 0.000 ; 0.914 ; +; 0.307 ; gA6_winner:inst1|\dealer:p_win ; gA6_winner:inst1|\dealer:p_win ; clk ; clk ; 1.000 ; 0.000 ; 0.731 ; +; 0.307 ; gA6_computer:inst|\computer:state[1] ; gA6_computer:inst|\computer:state[1] ; clk ; clk ; 1.000 ; 0.000 ; 0.731 ; +; 0.307 ; gA6_computer:inst|\computer:state[0] ; gA6_computer:inst|\computer:state[0] ; clk ; clk ; 1.000 ; 0.000 ; 0.731 ; ++--------+--------------------------------------+--------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Slow Model Hold: 'clk' ; ++-------+--------------------------------------+--------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+--------------------------------------+--------------------------------------+--------------+-------------+--------------+------------+------------+ +; 0.445 ; gA6_computer:inst|\computer:state[1] ; gA6_computer:inst|\computer:state[1] ; clk ; clk ; 0.000 ; 0.000 ; 0.731 ; +; 0.445 ; gA6_computer:inst|\computer:state[0] ; gA6_computer:inst|\computer:state[0] ; clk ; clk ; 0.000 ; 0.000 ; 0.731 ; +; 0.445 ; gA6_winner:inst1|\dealer:p_win ; gA6_winner:inst1|\dealer:p_win ; clk ; clk ; 0.000 ; 0.000 ; 0.731 ; +; 0.628 ; gA6_computer:inst|\computer:state[1] ; gA6_computer:inst|\computer:state[0] ; clk ; clk ; 0.000 ; 0.000 ; 0.914 ; +; 0.629 ; gA6_computer:inst|\computer:state[1] ; gA6_computer:inst|done ; clk ; clk ; 0.000 ; 0.000 ; 0.915 ; +; 0.637 ; gA6_computer:inst|\computer:state[0] ; gA6_computer:inst|hit ; clk ; clk ; 0.000 ; 0.000 ; 0.923 ; +; 0.637 ; gA6_computer:inst|\computer:state[0] ; gA6_computer:inst|\computer:state[1] ; clk ; clk ; 0.000 ; 0.000 ; 0.923 ; +; 0.890 ; gA6_computer:inst|\computer:state[0] ; gA6_computer:inst|done ; clk ; clk ; 0.000 ; 0.000 ; 1.176 ; +; 0.923 ; gA6_winner:inst1|\dealer:p_win ; gA6_winner:inst1|player_wins ; clk ; clk ; 0.000 ; 0.000 ; 1.209 ; +; 0.924 ; gA6_winner:inst1|\dealer:p_win ; gA6_winner:inst1|led_display4[3] ; clk ; clk ; 0.000 ; 0.000 ; 1.210 ; +; 1.007 ; gA6_computer:inst|\computer:state[1] ; gA6_computer:inst|hit ; clk ; clk ; 0.000 ; 0.000 ; 1.293 ; +; 1.008 ; gA6_winner:inst1|\dealer:p_win ; gA6_winner:inst1|led_display1[0] ; clk ; clk ; 0.000 ; 0.000 ; 1.294 ; +; 1.010 ; gA6_winner:inst1|\dealer:p_win ; gA6_winner:inst1|led_display3[1] ; clk ; clk ; 0.000 ; 0.000 ; 1.296 ; +; 1.281 ; gA6_winner:inst1|\dealer:d_win ; gA6_winner:inst1|led_display1[0] ; clk ; clk ; 0.000 ; 0.000 ; 1.567 ; +; 1.286 ; gA6_winner:inst1|\dealer:d_win ; gA6_winner:inst1|dealer_wins ; clk ; clk ; 0.000 ; 0.000 ; 1.572 ; +; 1.287 ; gA6_winner:inst1|\dealer:d_win ; gA6_winner:inst1|led_display3[1] ; clk ; clk ; 0.000 ; 0.000 ; 1.573 ; +; 1.378 ; gA6_winner:inst1|\dealer:d_win ; gA6_winner:inst1|led_display4[3] ; clk ; clk ; 0.000 ; 0.000 ; 1.664 ; +; 1.905 ; gA6_winner:inst1|\dealer:d_win ; gA6_winner:inst1|\dealer:d_win ; clk ; clk ; 0.000 ; 0.000 ; 2.191 ; +; 1.918 ; gA6_computer:inst|sum_out[1] ; gA6_winner:inst1|dealer_wins ; clk ; clk ; 0.000 ; -0.001 ; 2.203 ; +; 2.085 ; gA6_computer:inst|sum_out[1] ; gA6_winner:inst1|\dealer:p_win ; clk ; clk ; 0.000 ; -0.001 ; 2.370 ; +; 2.144 ; gA6_computer:inst|sum_out[3] ; gA6_winner:inst1|dealer_wins ; clk ; clk ; 0.000 ; -0.001 ; 2.429 ; +; 2.277 ; gA6_computer:inst|sum_out[5] ; gA6_winner:inst1|dealer_wins ; clk ; clk ; 0.000 ; -0.001 ; 2.562 ; +; 2.311 ; gA6_computer:inst|sum_out[3] ; gA6_winner:inst1|\dealer:p_win ; clk ; clk ; 0.000 ; -0.001 ; 2.596 ; +; 2.352 ; gA6_computer:inst|sum_out[1] ; gA6_winner:inst1|led_display3[1] ; clk ; clk ; 0.000 ; -0.001 ; 2.637 ; +; 2.397 ; gA6_computer:inst|sum_out[1] ; gA6_winner:inst1|led_display1[0] ; clk ; clk ; 0.000 ; -0.001 ; 2.682 ; +; 2.444 ; gA6_computer:inst|sum_out[5] ; gA6_winner:inst1|\dealer:p_win ; clk ; clk ; 0.000 ; -0.001 ; 2.729 ; +; 2.458 ; gA6_computer:inst|sum_out[4] ; gA6_winner:inst1|dealer_wins ; clk ; clk ; 0.000 ; -0.001 ; 2.743 ; +; 2.468 ; gA6_computer:inst|sum_out[0] ; gA6_winner:inst1|\dealer:p_win ; clk ; clk ; 0.000 ; -0.001 ; 2.753 ; +; 2.471 ; gA6_computer:inst|sum_out[0] ; gA6_winner:inst1|dealer_wins ; clk ; clk ; 0.000 ; -0.001 ; 2.756 ; +; 2.499 ; gA6_computer:inst|sum_out[4] ; gA6_winner:inst1|\dealer:p_win ; clk ; clk ; 0.000 ; -0.001 ; 2.784 ; +; 2.527 ; gA6_computer:inst|sum_out[2] ; gA6_winner:inst1|dealer_wins ; clk ; clk ; 0.000 ; -0.001 ; 2.812 ; +; 2.537 ; gA6_computer:inst|sum_out[1] ; gA6_winner:inst1|\dealer:d_win ; clk ; clk ; 0.000 ; -0.001 ; 2.822 ; +; 2.563 ; gA6_computer:inst|sum_out[1] ; gA6_winner:inst1|player_wins ; clk ; clk ; 0.000 ; -0.001 ; 2.848 ; +; 2.564 ; gA6_computer:inst|sum_out[1] ; gA6_winner:inst1|led_display4[3] ; clk ; clk ; 0.000 ; -0.001 ; 2.849 ; +; 2.578 ; gA6_computer:inst|sum_out[3] ; gA6_winner:inst1|led_display3[1] ; clk ; clk ; 0.000 ; -0.001 ; 2.863 ; +; 2.623 ; gA6_computer:inst|sum_out[3] ; gA6_winner:inst1|led_display1[0] ; clk ; clk ; 0.000 ; -0.001 ; 2.908 ; +; 2.643 ; gA6_computer:inst|sum_out[2] ; gA6_winner:inst1|\dealer:p_win ; clk ; clk ; 0.000 ; -0.001 ; 2.928 ; +; 2.711 ; gA6_computer:inst|sum_out[5] ; gA6_winner:inst1|led_display3[1] ; clk ; clk ; 0.000 ; -0.001 ; 2.996 ; +; 2.751 ; gA6_computer:inst|sum_out[5] ; gA6_winner:inst1|led_display1[0] ; clk ; clk ; 0.000 ; -0.001 ; 3.036 ; +; 2.763 ; gA6_computer:inst|sum_out[3] ; gA6_winner:inst1|\dealer:d_win ; clk ; clk ; 0.000 ; -0.001 ; 3.048 ; +; 2.788 ; gA6_computer:inst|sum_out[0] ; gA6_winner:inst1|led_display1[0] ; clk ; clk ; 0.000 ; -0.001 ; 3.073 ; +; 2.789 ; gA6_computer:inst|sum_out[3] ; gA6_winner:inst1|player_wins ; clk ; clk ; 0.000 ; -0.001 ; 3.074 ; +; 2.790 ; gA6_computer:inst|sum_out[3] ; gA6_winner:inst1|led_display4[3] ; clk ; clk ; 0.000 ; -0.001 ; 3.075 ; +; 2.791 ; gA6_computer:inst|sum_out[0] ; gA6_winner:inst1|led_display3[1] ; clk ; clk ; 0.000 ; -0.001 ; 3.076 ; +; 2.819 ; gA6_computer:inst|sum_out[4] ; gA6_winner:inst1|led_display1[0] ; clk ; clk ; 0.000 ; -0.001 ; 3.104 ; +; 2.822 ; gA6_computer:inst|sum_out[4] ; gA6_winner:inst1|led_display3[1] ; clk ; clk ; 0.000 ; -0.001 ; 3.107 ; +; 2.896 ; gA6_computer:inst|sum_out[5] ; gA6_winner:inst1|\dealer:d_win ; clk ; clk ; 0.000 ; -0.001 ; 3.181 ; +; 2.922 ; gA6_computer:inst|sum_out[5] ; gA6_winner:inst1|player_wins ; clk ; clk ; 0.000 ; -0.001 ; 3.207 ; +; 2.923 ; gA6_computer:inst|sum_out[5] ; gA6_winner:inst1|led_display4[3] ; clk ; clk ; 0.000 ; -0.001 ; 3.208 ; +; 2.946 ; gA6_computer:inst|sum_out[0] ; gA6_winner:inst1|player_wins ; clk ; clk ; 0.000 ; -0.001 ; 3.231 ; +; 2.947 ; gA6_computer:inst|sum_out[0] ; gA6_winner:inst1|led_display4[3] ; clk ; clk ; 0.000 ; -0.001 ; 3.232 ; +; 2.961 ; gA6_computer:inst|sum_out[2] ; gA6_winner:inst1|led_display3[1] ; clk ; clk ; 0.000 ; -0.001 ; 3.246 ; +; 2.963 ; gA6_computer:inst|sum_out[2] ; gA6_winner:inst1|led_display1[0] ; clk ; clk ; 0.000 ; -0.001 ; 3.248 ; +; 2.977 ; gA6_computer:inst|sum_out[4] ; gA6_winner:inst1|player_wins ; clk ; clk ; 0.000 ; -0.001 ; 3.262 ; +; 2.978 ; gA6_computer:inst|sum_out[4] ; gA6_winner:inst1|led_display4[3] ; clk ; clk ; 0.000 ; -0.001 ; 3.263 ; +; 3.077 ; gA6_computer:inst|sum_out[4] ; gA6_winner:inst1|\dealer:d_win ; clk ; clk ; 0.000 ; -0.001 ; 3.362 ; +; 3.090 ; gA6_computer:inst|sum_out[0] ; gA6_winner:inst1|\dealer:d_win ; clk ; clk ; 0.000 ; -0.001 ; 3.375 ; +; 3.121 ; gA6_computer:inst|sum_out[2] ; gA6_winner:inst1|player_wins ; clk ; clk ; 0.000 ; -0.001 ; 3.406 ; +; 3.122 ; gA6_computer:inst|sum_out[2] ; gA6_winner:inst1|led_display4[3] ; clk ; clk ; 0.000 ; -0.001 ; 3.407 ; +; 3.146 ; gA6_computer:inst|sum_out[2] ; gA6_winner:inst1|\dealer:d_win ; clk ; clk ; 0.000 ; -0.001 ; 3.431 ; ++-------+--------------------------------------+--------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++-----------------------------------------------------------------------------------------------------------------------+ +; Slow Model Minimum Pulse Width: 'clk' ; ++--------+--------------+----------------+------------------+-------+------------+--------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++--------+--------------+----------------+------------------+-------+------------+--------------------------------------+ +; -1.631 ; 1.000 ; 2.631 ; Port Rate ; clk ; Rise ; clk ; +; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; clk ; Rise ; gA6_computer:inst|\computer:state[0] ; +; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; clk ; Rise ; gA6_computer:inst|\computer:state[0] ; +; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; clk ; Rise ; gA6_computer:inst|\computer:state[1] ; +; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; clk ; Rise ; gA6_computer:inst|\computer:state[1] ; +; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; clk ; Rise ; gA6_computer:inst|done ; +; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; clk ; Rise ; gA6_computer:inst|done ; +; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; clk ; Rise ; gA6_computer:inst|hit ; +; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; clk ; Rise ; gA6_computer:inst|hit ; +; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; clk ; Rise ; gA6_computer:inst|sum_out[0] ; +; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; clk ; Rise ; gA6_computer:inst|sum_out[0] ; +; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; clk ; Rise ; gA6_computer:inst|sum_out[1] ; +; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; clk ; Rise ; gA6_computer:inst|sum_out[1] ; +; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; clk ; Rise ; gA6_computer:inst|sum_out[2] ; +; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; clk ; Rise ; gA6_computer:inst|sum_out[2] ; +; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; clk ; Rise ; gA6_computer:inst|sum_out[3] ; +; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; clk ; Rise ; gA6_computer:inst|sum_out[3] ; +; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; clk ; Rise ; gA6_computer:inst|sum_out[4] ; +; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; clk ; Rise ; gA6_computer:inst|sum_out[4] ; +; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; clk ; Rise ; gA6_computer:inst|sum_out[5] ; +; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; clk ; Rise ; gA6_computer:inst|sum_out[5] ; +; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; clk ; Rise ; gA6_winner:inst1|\dealer:d_win ; +; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; clk ; Rise ; gA6_winner:inst1|\dealer:d_win ; +; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; clk ; Rise ; gA6_winner:inst1|\dealer:p_win ; +; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; clk ; Rise ; gA6_winner:inst1|\dealer:p_win ; +; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; clk ; Rise ; gA6_winner:inst1|dealer_wins ; +; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; clk ; Rise ; gA6_winner:inst1|dealer_wins ; +; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; clk ; Rise ; gA6_winner:inst1|led_display1[0] ; +; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; clk ; Rise ; gA6_winner:inst1|led_display1[0] ; +; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; clk ; Rise ; gA6_winner:inst1|led_display3[1] ; +; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; clk ; Rise ; gA6_winner:inst1|led_display3[1] ; +; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; clk ; Rise ; gA6_winner:inst1|led_display4[3] ; +; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; clk ; Rise ; gA6_winner:inst1|led_display4[3] ; +; -0.611 ; 0.500 ; 1.111 ; High Pulse Width ; clk ; Rise ; gA6_winner:inst1|player_wins ; +; -0.611 ; 0.500 ; 1.111 ; Low Pulse Width ; clk ; Rise ; gA6_winner:inst1|player_wins ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; clk|combout ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; clk|combout ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; clk~clkctrl|inclk[0] ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; clk~clkctrl|inclk[0] ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; clk~clkctrl|outclk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; clk~clkctrl|outclk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst1|\dealer:d_win|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst1|\dealer:d_win|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst1|\dealer:p_win|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst1|\dealer:p_win|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst1|dealer_wins|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst1|dealer_wins|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst1|led_display1[0]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst1|led_display1[0]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst1|led_display3[1]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst1|led_display3[1]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst1|led_display4[3]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst1|led_display4[3]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst1|player_wins|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst1|player_wins|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst|\computer:state[0]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst|\computer:state[0]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst|\computer:state[1]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst|\computer:state[1]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst|done|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst|done|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst|hit|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst|hit|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst|sum_out[0]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst|sum_out[0]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst|sum_out[1]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst|sum_out[1]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst|sum_out[2]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst|sum_out[2]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst|sum_out[3]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst|sum_out[3]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst|sum_out[4]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst|sum_out[4]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst|sum_out[5]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst|sum_out[5]|clk ; ++--------+--------------+----------------+------------------+-------+------------+--------------------------------------+ + + ++----------------------------------------------------------------------------+ +; Setup Times ; ++----------------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++----------------+------------+-------+-------+------------+-----------------+ +; player_sum[*] ; clk ; 8.247 ; 8.247 ; Rise ; clk ; +; player_sum[0] ; clk ; 7.974 ; 7.974 ; Rise ; clk ; +; player_sum[1] ; clk ; 8.247 ; 8.247 ; Rise ; clk ; +; player_sum[2] ; clk ; 7.565 ; 7.565 ; Rise ; clk ; +; player_sum[3] ; clk ; 7.714 ; 7.714 ; Rise ; clk ; +; player_sum[4] ; clk ; 7.628 ; 7.628 ; Rise ; clk ; +; player_sum[5] ; clk ; 6.924 ; 6.924 ; Rise ; clk ; +; sum[*] ; clk ; 6.241 ; 6.241 ; Rise ; clk ; +; sum[0] ; clk ; 6.241 ; 6.241 ; Rise ; clk ; +; sum[1] ; clk ; 6.187 ; 6.187 ; Rise ; clk ; +; sum[2] ; clk ; 6.225 ; 6.225 ; Rise ; clk ; +; sum[3] ; clk ; 5.864 ; 5.864 ; Rise ; clk ; +; sum[4] ; clk ; 5.461 ; 5.461 ; Rise ; clk ; +; sum[5] ; clk ; 5.413 ; 5.413 ; Rise ; clk ; +; turn ; clk ; 3.772 ; 3.772 ; Rise ; clk ; ++----------------+------------+-------+-------+------------+-----------------+ + + ++------------------------------------------------------------------------------+ +; Hold Times ; ++----------------+------------+--------+--------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++----------------+------------+--------+--------+------------+-----------------+ +; player_sum[*] ; clk ; -4.050 ; -4.050 ; Rise ; clk ; +; player_sum[0] ; clk ; -5.783 ; -5.783 ; Rise ; clk ; +; player_sum[1] ; clk ; -5.592 ; -5.592 ; Rise ; clk ; +; player_sum[2] ; clk ; -5.383 ; -5.383 ; Rise ; clk ; +; player_sum[3] ; clk ; -5.409 ; -5.409 ; Rise ; clk ; +; player_sum[4] ; clk ; -4.797 ; -4.797 ; Rise ; clk ; +; player_sum[5] ; clk ; -4.050 ; -4.050 ; Rise ; clk ; +; sum[*] ; clk ; -3.325 ; -3.325 ; Rise ; clk ; +; sum[0] ; clk ; -3.394 ; -3.394 ; Rise ; clk ; +; sum[1] ; clk ; -3.579 ; -3.579 ; Rise ; clk ; +; sum[2] ; clk ; -3.325 ; -3.325 ; Rise ; clk ; +; sum[3] ; clk ; -3.358 ; -3.358 ; Rise ; clk ; +; sum[4] ; clk ; -3.380 ; -3.380 ; Rise ; clk ; +; sum[5] ; clk ; -3.603 ; -3.603 ; Rise ; clk ; +; turn ; clk ; -3.524 ; -3.524 ; Rise ; clk ; ++----------------+------------+--------+--------+------------+-----------------+ + + ++------------------------------------------------------------------------------+ +; Clock to Output Times ; ++------------------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++------------------+------------+-------+-------+------------+-----------------+ +; dealer_wins ; clk ; 6.926 ; 6.926 ; Rise ; clk ; +; done ; clk ; 6.863 ; 6.863 ; Rise ; clk ; +; hit ; clk ; 6.871 ; 6.871 ; Rise ; clk ; +; led_display1[*] ; clk ; 7.305 ; 7.305 ; Rise ; clk ; +; led_display1[0] ; clk ; 7.275 ; 7.275 ; Rise ; clk ; +; led_display1[1] ; clk ; 7.305 ; 7.305 ; Rise ; clk ; +; led_display1[2] ; clk ; 6.952 ; 6.952 ; Rise ; clk ; +; led_display1[3] ; clk ; 6.932 ; 6.932 ; Rise ; clk ; +; led_display1[6] ; clk ; 7.275 ; 7.275 ; Rise ; clk ; +; led_display2[*] ; clk ; 7.707 ; 7.707 ; Rise ; clk ; +; led_display2[0] ; clk ; 7.707 ; 7.707 ; Rise ; clk ; +; led_display2[5] ; clk ; 7.263 ; 7.263 ; Rise ; clk ; +; led_display3[*] ; clk ; 7.283 ; 7.283 ; Rise ; clk ; +; led_display3[0] ; clk ; 7.283 ; 7.283 ; Rise ; clk ; +; led_display3[1] ; clk ; 6.952 ; 6.952 ; Rise ; clk ; +; led_display3[3] ; clk ; 6.942 ; 6.942 ; Rise ; clk ; +; led_display3[5] ; clk ; 6.939 ; 6.939 ; Rise ; clk ; +; led_display3[6] ; clk ; 6.919 ; 6.919 ; Rise ; clk ; +; led_display4[*] ; clk ; 7.697 ; 7.697 ; Rise ; clk ; +; led_display4[0] ; clk ; 7.305 ; 7.305 ; Rise ; clk ; +; led_display4[1] ; clk ; 7.697 ; 7.697 ; Rise ; clk ; +; led_display4[2] ; clk ; 7.689 ; 7.689 ; Rise ; clk ; +; led_display4[3] ; clk ; 7.689 ; 7.689 ; Rise ; clk ; +; led_display4[6] ; clk ; 6.912 ; 6.912 ; Rise ; clk ; +; player_wins ; clk ; 6.911 ; 6.911 ; Rise ; clk ; +; state_out[*] ; clk ; 6.910 ; 6.910 ; Rise ; clk ; +; state_out[0] ; clk ; 6.910 ; 6.910 ; Rise ; clk ; +; state_out[1] ; clk ; 6.889 ; 6.889 ; Rise ; clk ; +; sum_out[*] ; clk ; 7.326 ; 7.326 ; Rise ; clk ; +; sum_out[0] ; clk ; 6.908 ; 6.908 ; Rise ; clk ; +; sum_out[1] ; clk ; 7.170 ; 7.170 ; Rise ; clk ; +; sum_out[2] ; clk ; 7.139 ; 7.139 ; Rise ; clk ; +; sum_out[3] ; clk ; 6.905 ; 6.905 ; Rise ; clk ; +; sum_out[4] ; clk ; 7.145 ; 7.145 ; Rise ; clk ; +; sum_out[5] ; clk ; 7.326 ; 7.326 ; Rise ; clk ; ++------------------+------------+-------+-------+------------+-----------------+ + + ++------------------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++------------------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++------------------+------------+-------+-------+------------+-----------------+ +; dealer_wins ; clk ; 6.926 ; 6.926 ; Rise ; clk ; +; done ; clk ; 6.863 ; 6.863 ; Rise ; clk ; +; hit ; clk ; 6.871 ; 6.871 ; Rise ; clk ; +; led_display1[*] ; clk ; 6.932 ; 6.932 ; Rise ; clk ; +; led_display1[0] ; clk ; 7.275 ; 7.275 ; Rise ; clk ; +; led_display1[1] ; clk ; 7.305 ; 7.305 ; Rise ; clk ; +; led_display1[2] ; clk ; 6.952 ; 6.952 ; Rise ; clk ; +; led_display1[3] ; clk ; 6.932 ; 6.932 ; Rise ; clk ; +; led_display1[6] ; clk ; 7.275 ; 7.275 ; Rise ; clk ; +; led_display2[*] ; clk ; 7.263 ; 7.263 ; Rise ; clk ; +; led_display2[0] ; clk ; 7.707 ; 7.707 ; Rise ; clk ; +; led_display2[5] ; clk ; 7.263 ; 7.263 ; Rise ; clk ; +; led_display3[*] ; clk ; 6.919 ; 6.919 ; Rise ; clk ; +; led_display3[0] ; clk ; 7.283 ; 7.283 ; Rise ; clk ; +; led_display3[1] ; clk ; 6.952 ; 6.952 ; Rise ; clk ; +; led_display3[3] ; clk ; 6.942 ; 6.942 ; Rise ; clk ; +; led_display3[5] ; clk ; 6.939 ; 6.939 ; Rise ; clk ; +; led_display3[6] ; clk ; 6.919 ; 6.919 ; Rise ; clk ; +; led_display4[*] ; clk ; 6.912 ; 6.912 ; Rise ; clk ; +; led_display4[0] ; clk ; 7.305 ; 7.305 ; Rise ; clk ; +; led_display4[1] ; clk ; 7.697 ; 7.697 ; Rise ; clk ; +; led_display4[2] ; clk ; 7.689 ; 7.689 ; Rise ; clk ; +; led_display4[3] ; clk ; 7.689 ; 7.689 ; Rise ; clk ; +; led_display4[6] ; clk ; 6.912 ; 6.912 ; Rise ; clk ; +; player_wins ; clk ; 6.911 ; 6.911 ; Rise ; clk ; +; state_out[*] ; clk ; 6.889 ; 6.889 ; Rise ; clk ; +; state_out[0] ; clk ; 6.910 ; 6.910 ; Rise ; clk ; +; state_out[1] ; clk ; 6.889 ; 6.889 ; Rise ; clk ; +; sum_out[*] ; clk ; 6.905 ; 6.905 ; Rise ; clk ; +; sum_out[0] ; clk ; 6.908 ; 6.908 ; Rise ; clk ; +; sum_out[1] ; clk ; 7.170 ; 7.170 ; Rise ; clk ; +; sum_out[2] ; clk ; 7.139 ; 7.139 ; Rise ; clk ; +; sum_out[3] ; clk ; 6.905 ; 6.905 ; Rise ; clk ; +; sum_out[4] ; clk ; 7.145 ; 7.145 ; Rise ; clk ; +; sum_out[5] ; clk ; 7.326 ; 7.326 ; Rise ; clk ; ++------------------+------------+-------+-------+------------+-----------------+ + + ++--------------------------------+ +; Fast Model Setup Summary ; ++-------+--------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+--------+---------------+ +; clk ; -1.010 ; -5.377 ; ++-------+--------+---------------+ + + ++-------------------------------+ +; Fast Model Hold Summary ; ++-------+-------+---------------+ +; Clock ; Slack ; End Point TNS ; ++-------+-------+---------------+ +; clk ; 0.215 ; 0.000 ; ++-------+-------+---------------+ + + +------------------------------- +; Fast Model Recovery Summary ; +------------------------------- +No paths to report. + + +------------------------------ +; Fast Model Removal Summary ; +------------------------------ +No paths to report. + + ++----------------------------------------+ +; Fast Model Minimum Pulse Width Summary ; ++-------+--------+-----------------------+ +; Clock ; Slack ; End Point TNS ; ++-------+--------+-----------------------+ +; clk ; -1.380 ; -18.380 ; ++-------+--------+-----------------------+ + + ++------------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast Model Setup: 'clk' ; ++--------+--------------------------------------+--------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++--------+--------------------------------------+--------------------------------------+--------------+-------------+--------------+------------+------------+ +; -1.010 ; gA6_computer:inst|sum_out[0] ; gA6_winner:inst1|led_display1[0] ; clk ; clk ; 1.000 ; 0.000 ; 2.042 ; +; -1.010 ; gA6_computer:inst|sum_out[0] ; gA6_winner:inst1|led_display3[1] ; clk ; clk ; 1.000 ; 0.000 ; 2.042 ; +; -1.010 ; gA6_computer:inst|sum_out[0] ; gA6_winner:inst1|led_display4[3] ; clk ; clk ; 1.000 ; 0.000 ; 2.042 ; +; -0.978 ; gA6_computer:inst|sum_out[1] ; gA6_winner:inst1|led_display1[0] ; clk ; clk ; 1.000 ; 0.000 ; 2.010 ; +; -0.978 ; gA6_computer:inst|sum_out[1] ; gA6_winner:inst1|led_display3[1] ; clk ; clk ; 1.000 ; 0.000 ; 2.010 ; +; -0.978 ; gA6_computer:inst|sum_out[1] ; gA6_winner:inst1|led_display4[3] ; clk ; clk ; 1.000 ; 0.000 ; 2.010 ; +; -0.966 ; gA6_computer:inst|sum_out[2] ; gA6_winner:inst1|led_display1[0] ; clk ; clk ; 1.000 ; 0.000 ; 1.998 ; +; -0.966 ; gA6_computer:inst|sum_out[2] ; gA6_winner:inst1|led_display3[1] ; clk ; clk ; 1.000 ; 0.000 ; 1.998 ; +; -0.966 ; gA6_computer:inst|sum_out[2] ; gA6_winner:inst1|led_display4[3] ; clk ; clk ; 1.000 ; 0.000 ; 1.998 ; +; -0.935 ; gA6_computer:inst|sum_out[3] ; gA6_winner:inst1|led_display1[0] ; clk ; clk ; 1.000 ; 0.000 ; 1.967 ; +; -0.935 ; gA6_computer:inst|sum_out[3] ; gA6_winner:inst1|led_display3[1] ; clk ; clk ; 1.000 ; 0.000 ; 1.967 ; +; -0.935 ; gA6_computer:inst|sum_out[3] ; gA6_winner:inst1|led_display4[3] ; clk ; clk ; 1.000 ; 0.000 ; 1.967 ; +; -0.869 ; gA6_computer:inst|sum_out[4] ; gA6_winner:inst1|led_display1[0] ; clk ; clk ; 1.000 ; 0.000 ; 1.901 ; +; -0.869 ; gA6_computer:inst|sum_out[4] ; gA6_winner:inst1|led_display3[1] ; clk ; clk ; 1.000 ; 0.000 ; 1.901 ; +; -0.869 ; gA6_computer:inst|sum_out[4] ; gA6_winner:inst1|led_display4[3] ; clk ; clk ; 1.000 ; 0.000 ; 1.901 ; +; -0.709 ; gA6_computer:inst|sum_out[0] ; gA6_winner:inst1|\dealer:d_win ; clk ; clk ; 1.000 ; 0.000 ; 1.741 ; +; -0.677 ; gA6_computer:inst|sum_out[1] ; gA6_winner:inst1|\dealer:d_win ; clk ; clk ; 1.000 ; 0.000 ; 1.709 ; +; -0.676 ; gA6_computer:inst|sum_out[0] ; gA6_winner:inst1|player_wins ; clk ; clk ; 1.000 ; 0.000 ; 1.708 ; +; -0.665 ; gA6_computer:inst|sum_out[2] ; gA6_winner:inst1|\dealer:d_win ; clk ; clk ; 1.000 ; 0.000 ; 1.697 ; +; -0.642 ; gA6_computer:inst|sum_out[1] ; gA6_winner:inst1|player_wins ; clk ; clk ; 1.000 ; 0.000 ; 1.674 ; +; -0.634 ; gA6_computer:inst|sum_out[3] ; gA6_winner:inst1|\dealer:d_win ; clk ; clk ; 1.000 ; 0.000 ; 1.666 ; +; -0.628 ; gA6_computer:inst|sum_out[2] ; gA6_winner:inst1|player_wins ; clk ; clk ; 1.000 ; 0.000 ; 1.660 ; +; -0.626 ; gA6_computer:inst|sum_out[5] ; gA6_winner:inst1|led_display1[0] ; clk ; clk ; 1.000 ; 0.000 ; 1.658 ; +; -0.626 ; gA6_computer:inst|sum_out[5] ; gA6_winner:inst1|led_display3[1] ; clk ; clk ; 1.000 ; 0.000 ; 1.658 ; +; -0.626 ; gA6_computer:inst|sum_out[5] ; gA6_winner:inst1|led_display4[3] ; clk ; clk ; 1.000 ; 0.000 ; 1.658 ; +; -0.592 ; gA6_computer:inst|sum_out[3] ; gA6_winner:inst1|player_wins ; clk ; clk ; 1.000 ; 0.000 ; 1.624 ; +; -0.568 ; gA6_computer:inst|sum_out[4] ; gA6_winner:inst1|\dealer:d_win ; clk ; clk ; 1.000 ; 0.000 ; 1.600 ; +; -0.530 ; gA6_computer:inst|sum_out[4] ; gA6_winner:inst1|player_wins ; clk ; clk ; 1.000 ; 0.000 ; 1.562 ; +; -0.505 ; gA6_computer:inst|sum_out[0] ; gA6_winner:inst1|\dealer:p_win ; clk ; clk ; 1.000 ; 0.000 ; 1.537 ; +; -0.471 ; gA6_computer:inst|sum_out[1] ; gA6_winner:inst1|\dealer:p_win ; clk ; clk ; 1.000 ; 0.000 ; 1.503 ; +; -0.457 ; gA6_computer:inst|sum_out[0] ; gA6_winner:inst1|dealer_wins ; clk ; clk ; 1.000 ; 0.000 ; 1.489 ; +; -0.457 ; gA6_computer:inst|sum_out[2] ; gA6_winner:inst1|\dealer:p_win ; clk ; clk ; 1.000 ; 0.000 ; 1.489 ; +; -0.425 ; gA6_computer:inst|sum_out[1] ; gA6_winner:inst1|dealer_wins ; clk ; clk ; 1.000 ; 0.000 ; 1.457 ; +; -0.421 ; gA6_computer:inst|sum_out[3] ; gA6_winner:inst1|\dealer:p_win ; clk ; clk ; 1.000 ; 0.000 ; 1.453 ; +; -0.413 ; gA6_computer:inst|sum_out[2] ; gA6_winner:inst1|dealer_wins ; clk ; clk ; 1.000 ; 0.000 ; 1.445 ; +; -0.382 ; gA6_computer:inst|sum_out[3] ; gA6_winner:inst1|dealer_wins ; clk ; clk ; 1.000 ; 0.000 ; 1.414 ; +; -0.359 ; gA6_computer:inst|sum_out[4] ; gA6_winner:inst1|\dealer:p_win ; clk ; clk ; 1.000 ; 0.000 ; 1.391 ; +; -0.342 ; gA6_winner:inst1|\dealer:p_win ; gA6_winner:inst1|led_display1[0] ; clk ; clk ; 1.000 ; 0.000 ; 1.374 ; +; -0.342 ; gA6_winner:inst1|\dealer:p_win ; gA6_winner:inst1|led_display3[1] ; clk ; clk ; 1.000 ; 0.000 ; 1.374 ; +; -0.342 ; gA6_winner:inst1|\dealer:p_win ; gA6_winner:inst1|led_display4[3] ; clk ; clk ; 1.000 ; 0.000 ; 1.374 ; +; -0.325 ; gA6_computer:inst|sum_out[5] ; gA6_winner:inst1|\dealer:d_win ; clk ; clk ; 1.000 ; 0.000 ; 1.357 ; +; -0.316 ; gA6_computer:inst|sum_out[4] ; gA6_winner:inst1|dealer_wins ; clk ; clk ; 1.000 ; 0.000 ; 1.348 ; +; -0.286 ; gA6_computer:inst|sum_out[5] ; gA6_winner:inst1|player_wins ; clk ; clk ; 1.000 ; 0.000 ; 1.318 ; +; -0.115 ; gA6_computer:inst|sum_out[5] ; gA6_winner:inst1|\dealer:p_win ; clk ; clk ; 1.000 ; 0.000 ; 1.147 ; +; -0.073 ; gA6_computer:inst|sum_out[5] ; gA6_winner:inst1|dealer_wins ; clk ; clk ; 1.000 ; 0.000 ; 1.105 ; +; 0.151 ; gA6_winner:inst1|\dealer:d_win ; gA6_winner:inst1|\dealer:d_win ; clk ; clk ; 1.000 ; 0.000 ; 0.881 ; +; 0.228 ; gA6_winner:inst1|\dealer:d_win ; gA6_winner:inst1|led_display1[0] ; clk ; clk ; 1.000 ; 0.000 ; 0.804 ; +; 0.228 ; gA6_winner:inst1|\dealer:d_win ; gA6_winner:inst1|led_display3[1] ; clk ; clk ; 1.000 ; 0.000 ; 0.804 ; +; 0.228 ; gA6_winner:inst1|\dealer:d_win ; gA6_winner:inst1|led_display4[3] ; clk ; clk ; 1.000 ; 0.000 ; 0.804 ; +; 0.403 ; gA6_winner:inst1|\dealer:d_win ; gA6_winner:inst1|dealer_wins ; clk ; clk ; 1.000 ; 0.000 ; 0.629 ; +; 0.494 ; gA6_winner:inst1|\dealer:p_win ; gA6_winner:inst1|player_wins ; clk ; clk ; 1.000 ; 0.000 ; 0.538 ; +; 0.506 ; gA6_computer:inst|\computer:state[1] ; gA6_computer:inst|hit ; clk ; clk ; 1.000 ; 0.000 ; 0.526 ; +; 0.515 ; gA6_computer:inst|\computer:state[0] ; gA6_computer:inst|done ; clk ; clk ; 1.000 ; 0.000 ; 0.517 ; +; 0.633 ; gA6_computer:inst|\computer:state[0] ; gA6_computer:inst|\computer:state[1] ; clk ; clk ; 1.000 ; 0.000 ; 0.399 ; +; 0.633 ; gA6_computer:inst|\computer:state[0] ; gA6_computer:inst|hit ; clk ; clk ; 1.000 ; 0.000 ; 0.399 ; +; 0.637 ; gA6_computer:inst|\computer:state[1] ; gA6_computer:inst|\computer:state[0] ; clk ; clk ; 1.000 ; 0.000 ; 0.395 ; +; 0.637 ; gA6_computer:inst|\computer:state[1] ; gA6_computer:inst|done ; clk ; clk ; 1.000 ; 0.000 ; 0.395 ; +; 0.665 ; gA6_winner:inst1|\dealer:p_win ; gA6_winner:inst1|\dealer:p_win ; clk ; clk ; 1.000 ; 0.000 ; 0.367 ; +; 0.665 ; gA6_computer:inst|\computer:state[1] ; gA6_computer:inst|\computer:state[1] ; clk ; clk ; 1.000 ; 0.000 ; 0.367 ; +; 0.665 ; gA6_computer:inst|\computer:state[0] ; gA6_computer:inst|\computer:state[0] ; clk ; clk ; 1.000 ; 0.000 ; 0.367 ; ++--------+--------------------------------------+--------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++-----------------------------------------------------------------------------------------------------------------------------------------------------------+ +; Fast Model Hold: 'clk' ; ++-------+--------------------------------------+--------------------------------------+--------------+-------------+--------------+------------+------------+ +; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ; ++-------+--------------------------------------+--------------------------------------+--------------+-------------+--------------+------------+------------+ +; 0.215 ; gA6_computer:inst|\computer:state[1] ; gA6_computer:inst|\computer:state[1] ; clk ; clk ; 0.000 ; 0.000 ; 0.367 ; +; 0.215 ; gA6_computer:inst|\computer:state[0] ; gA6_computer:inst|\computer:state[0] ; clk ; clk ; 0.000 ; 0.000 ; 0.367 ; +; 0.215 ; gA6_winner:inst1|\dealer:p_win ; gA6_winner:inst1|\dealer:p_win ; clk ; clk ; 0.000 ; 0.000 ; 0.367 ; +; 0.243 ; gA6_computer:inst|\computer:state[1] ; gA6_computer:inst|done ; clk ; clk ; 0.000 ; 0.000 ; 0.395 ; +; 0.243 ; gA6_computer:inst|\computer:state[1] ; gA6_computer:inst|\computer:state[0] ; clk ; clk ; 0.000 ; 0.000 ; 0.395 ; +; 0.247 ; gA6_computer:inst|\computer:state[0] ; gA6_computer:inst|hit ; clk ; clk ; 0.000 ; 0.000 ; 0.399 ; +; 0.247 ; gA6_computer:inst|\computer:state[0] ; gA6_computer:inst|\computer:state[1] ; clk ; clk ; 0.000 ; 0.000 ; 0.399 ; +; 0.365 ; gA6_computer:inst|\computer:state[0] ; gA6_computer:inst|done ; clk ; clk ; 0.000 ; 0.000 ; 0.517 ; +; 0.374 ; gA6_computer:inst|\computer:state[1] ; gA6_computer:inst|hit ; clk ; clk ; 0.000 ; 0.000 ; 0.526 ; +; 0.378 ; gA6_winner:inst1|\dealer:p_win ; gA6_winner:inst1|led_display1[0] ; clk ; clk ; 0.000 ; 0.000 ; 0.530 ; +; 0.380 ; gA6_winner:inst1|\dealer:p_win ; gA6_winner:inst1|led_display3[1] ; clk ; clk ; 0.000 ; 0.000 ; 0.532 ; +; 0.386 ; gA6_winner:inst1|\dealer:p_win ; gA6_winner:inst1|player_wins ; clk ; clk ; 0.000 ; 0.000 ; 0.538 ; +; 0.386 ; gA6_winner:inst1|\dealer:p_win ; gA6_winner:inst1|led_display4[3] ; clk ; clk ; 0.000 ; 0.000 ; 0.538 ; +; 0.477 ; gA6_winner:inst1|\dealer:d_win ; gA6_winner:inst1|dealer_wins ; clk ; clk ; 0.000 ; 0.000 ; 0.629 ; +; 0.477 ; gA6_winner:inst1|\dealer:d_win ; gA6_winner:inst1|led_display1[0] ; clk ; clk ; 0.000 ; 0.000 ; 0.629 ; +; 0.480 ; gA6_winner:inst1|\dealer:d_win ; gA6_winner:inst1|led_display3[1] ; clk ; clk ; 0.000 ; 0.000 ; 0.632 ; +; 0.652 ; gA6_winner:inst1|\dealer:d_win ; gA6_winner:inst1|led_display4[3] ; clk ; clk ; 0.000 ; 0.000 ; 0.804 ; +; 0.729 ; gA6_winner:inst1|\dealer:d_win ; gA6_winner:inst1|\dealer:d_win ; clk ; clk ; 0.000 ; 0.000 ; 0.881 ; +; 0.758 ; gA6_computer:inst|sum_out[1] ; gA6_winner:inst1|dealer_wins ; clk ; clk ; 0.000 ; 0.000 ; 0.910 ; +; 0.809 ; gA6_computer:inst|sum_out[3] ; gA6_winner:inst1|dealer_wins ; clk ; clk ; 0.000 ; 0.000 ; 0.961 ; +; 0.828 ; gA6_computer:inst|sum_out[1] ; gA6_winner:inst1|\dealer:p_win ; clk ; clk ; 0.000 ; 0.000 ; 0.980 ; +; 0.861 ; gA6_computer:inst|sum_out[5] ; gA6_winner:inst1|dealer_wins ; clk ; clk ; 0.000 ; 0.000 ; 1.013 ; +; 0.879 ; gA6_computer:inst|sum_out[3] ; gA6_winner:inst1|\dealer:p_win ; clk ; clk ; 0.000 ; 0.000 ; 1.031 ; +; 0.912 ; gA6_computer:inst|sum_out[4] ; gA6_winner:inst1|\dealer:p_win ; clk ; clk ; 0.000 ; 0.000 ; 1.064 ; +; 0.914 ; gA6_computer:inst|sum_out[4] ; gA6_winner:inst1|dealer_wins ; clk ; clk ; 0.000 ; 0.000 ; 1.066 ; +; 0.926 ; gA6_computer:inst|sum_out[1] ; gA6_winner:inst1|led_display1[0] ; clk ; clk ; 0.000 ; 0.000 ; 1.078 ; +; 0.926 ; gA6_computer:inst|sum_out[1] ; gA6_winner:inst1|led_display3[1] ; clk ; clk ; 0.000 ; 0.000 ; 1.078 ; +; 0.929 ; gA6_computer:inst|sum_out[0] ; gA6_winner:inst1|\dealer:p_win ; clk ; clk ; 0.000 ; 0.000 ; 1.081 ; +; 0.931 ; gA6_computer:inst|sum_out[5] ; gA6_winner:inst1|\dealer:p_win ; clk ; clk ; 0.000 ; 0.000 ; 1.083 ; +; 0.931 ; gA6_computer:inst|sum_out[0] ; gA6_winner:inst1|dealer_wins ; clk ; clk ; 0.000 ; 0.000 ; 1.083 ; +; 0.933 ; gA6_computer:inst|sum_out[2] ; gA6_winner:inst1|dealer_wins ; clk ; clk ; 0.000 ; 0.000 ; 1.085 ; +; 0.977 ; gA6_computer:inst|sum_out[3] ; gA6_winner:inst1|led_display1[0] ; clk ; clk ; 0.000 ; 0.000 ; 1.129 ; +; 0.977 ; gA6_computer:inst|sum_out[3] ; gA6_winner:inst1|led_display3[1] ; clk ; clk ; 0.000 ; 0.000 ; 1.129 ; +; 0.999 ; gA6_computer:inst|sum_out[1] ; gA6_winner:inst1|player_wins ; clk ; clk ; 0.000 ; 0.000 ; 1.151 ; +; 0.999 ; gA6_computer:inst|sum_out[1] ; gA6_winner:inst1|led_display4[3] ; clk ; clk ; 0.000 ; 0.000 ; 1.151 ; +; 1.003 ; gA6_computer:inst|sum_out[2] ; gA6_winner:inst1|\dealer:p_win ; clk ; clk ; 0.000 ; 0.000 ; 1.155 ; +; 1.010 ; gA6_computer:inst|sum_out[1] ; gA6_winner:inst1|\dealer:d_win ; clk ; clk ; 0.000 ; 0.000 ; 1.162 ; +; 1.023 ; gA6_computer:inst|sum_out[5] ; gA6_winner:inst1|led_display3[1] ; clk ; clk ; 0.000 ; 0.000 ; 1.175 ; +; 1.026 ; gA6_computer:inst|sum_out[5] ; gA6_winner:inst1|led_display1[0] ; clk ; clk ; 0.000 ; 0.000 ; 1.178 ; +; 1.032 ; gA6_computer:inst|sum_out[4] ; gA6_winner:inst1|led_display1[0] ; clk ; clk ; 0.000 ; 0.000 ; 1.184 ; +; 1.034 ; gA6_computer:inst|sum_out[4] ; gA6_winner:inst1|led_display3[1] ; clk ; clk ; 0.000 ; 0.000 ; 1.186 ; +; 1.049 ; gA6_computer:inst|sum_out[0] ; gA6_winner:inst1|led_display1[0] ; clk ; clk ; 0.000 ; 0.000 ; 1.201 ; +; 1.050 ; gA6_computer:inst|sum_out[3] ; gA6_winner:inst1|player_wins ; clk ; clk ; 0.000 ; 0.000 ; 1.202 ; +; 1.050 ; gA6_computer:inst|sum_out[3] ; gA6_winner:inst1|led_display4[3] ; clk ; clk ; 0.000 ; 0.000 ; 1.202 ; +; 1.051 ; gA6_computer:inst|sum_out[0] ; gA6_winner:inst1|led_display3[1] ; clk ; clk ; 0.000 ; 0.000 ; 1.203 ; +; 1.061 ; gA6_computer:inst|sum_out[3] ; gA6_winner:inst1|\dealer:d_win ; clk ; clk ; 0.000 ; 0.000 ; 1.213 ; +; 1.083 ; gA6_computer:inst|sum_out[4] ; gA6_winner:inst1|player_wins ; clk ; clk ; 0.000 ; 0.000 ; 1.235 ; +; 1.083 ; gA6_computer:inst|sum_out[4] ; gA6_winner:inst1|led_display4[3] ; clk ; clk ; 0.000 ; 0.000 ; 1.235 ; +; 1.100 ; gA6_computer:inst|sum_out[0] ; gA6_winner:inst1|player_wins ; clk ; clk ; 0.000 ; 0.000 ; 1.252 ; +; 1.100 ; gA6_computer:inst|sum_out[0] ; gA6_winner:inst1|led_display4[3] ; clk ; clk ; 0.000 ; 0.000 ; 1.252 ; +; 1.101 ; gA6_computer:inst|sum_out[2] ; gA6_winner:inst1|led_display1[0] ; clk ; clk ; 0.000 ; 0.000 ; 1.253 ; +; 1.101 ; gA6_computer:inst|sum_out[2] ; gA6_winner:inst1|led_display3[1] ; clk ; clk ; 0.000 ; 0.000 ; 1.253 ; +; 1.102 ; gA6_computer:inst|sum_out[5] ; gA6_winner:inst1|player_wins ; clk ; clk ; 0.000 ; 0.000 ; 1.254 ; +; 1.102 ; gA6_computer:inst|sum_out[5] ; gA6_winner:inst1|led_display4[3] ; clk ; clk ; 0.000 ; 0.000 ; 1.254 ; +; 1.113 ; gA6_computer:inst|sum_out[5] ; gA6_winner:inst1|\dealer:d_win ; clk ; clk ; 0.000 ; 0.000 ; 1.265 ; +; 1.166 ; gA6_computer:inst|sum_out[4] ; gA6_winner:inst1|\dealer:d_win ; clk ; clk ; 0.000 ; 0.000 ; 1.318 ; +; 1.174 ; gA6_computer:inst|sum_out[2] ; gA6_winner:inst1|player_wins ; clk ; clk ; 0.000 ; 0.000 ; 1.326 ; +; 1.174 ; gA6_computer:inst|sum_out[2] ; gA6_winner:inst1|led_display4[3] ; clk ; clk ; 0.000 ; 0.000 ; 1.326 ; +; 1.183 ; gA6_computer:inst|sum_out[0] ; gA6_winner:inst1|\dealer:d_win ; clk ; clk ; 0.000 ; 0.000 ; 1.335 ; +; 1.185 ; gA6_computer:inst|sum_out[2] ; gA6_winner:inst1|\dealer:d_win ; clk ; clk ; 0.000 ; 0.000 ; 1.337 ; ++-------+--------------------------------------+--------------------------------------+--------------+-------------+--------------+------------+------------+ + + ++-----------------------------------------------------------------------------------------------------------------------+ +; Fast Model Minimum Pulse Width: 'clk' ; ++--------+--------------+----------------+------------------+-------+------------+--------------------------------------+ +; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ; ++--------+--------------+----------------+------------------+-------+------------+--------------------------------------+ +; -1.380 ; 1.000 ; 2.380 ; Port Rate ; clk ; Rise ; clk ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; gA6_computer:inst|\computer:state[0] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; gA6_computer:inst|\computer:state[0] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; gA6_computer:inst|\computer:state[1] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; gA6_computer:inst|\computer:state[1] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; gA6_computer:inst|done ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; gA6_computer:inst|done ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; gA6_computer:inst|hit ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; gA6_computer:inst|hit ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; gA6_computer:inst|sum_out[0] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; gA6_computer:inst|sum_out[0] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; gA6_computer:inst|sum_out[1] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; gA6_computer:inst|sum_out[1] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; gA6_computer:inst|sum_out[2] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; gA6_computer:inst|sum_out[2] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; gA6_computer:inst|sum_out[3] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; gA6_computer:inst|sum_out[3] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; gA6_computer:inst|sum_out[4] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; gA6_computer:inst|sum_out[4] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; gA6_computer:inst|sum_out[5] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; gA6_computer:inst|sum_out[5] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; gA6_winner:inst1|\dealer:d_win ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; gA6_winner:inst1|\dealer:d_win ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; gA6_winner:inst1|\dealer:p_win ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; gA6_winner:inst1|\dealer:p_win ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; gA6_winner:inst1|dealer_wins ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; gA6_winner:inst1|dealer_wins ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; gA6_winner:inst1|led_display1[0] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; gA6_winner:inst1|led_display1[0] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; gA6_winner:inst1|led_display3[1] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; gA6_winner:inst1|led_display3[1] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; gA6_winner:inst1|led_display4[3] ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; gA6_winner:inst1|led_display4[3] ; +; -0.500 ; 0.500 ; 1.000 ; High Pulse Width ; clk ; Rise ; gA6_winner:inst1|player_wins ; +; -0.500 ; 0.500 ; 1.000 ; Low Pulse Width ; clk ; Rise ; gA6_winner:inst1|player_wins ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; clk|combout ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; clk|combout ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; clk~clkctrl|inclk[0] ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; clk~clkctrl|inclk[0] ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; clk~clkctrl|outclk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; clk~clkctrl|outclk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst1|\dealer:d_win|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst1|\dealer:d_win|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst1|\dealer:p_win|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst1|\dealer:p_win|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst1|dealer_wins|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst1|dealer_wins|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst1|led_display1[0]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst1|led_display1[0]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst1|led_display3[1]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst1|led_display3[1]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst1|led_display4[3]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst1|led_display4[3]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst1|player_wins|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst1|player_wins|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst|\computer:state[0]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst|\computer:state[0]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst|\computer:state[1]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst|\computer:state[1]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst|done|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst|done|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst|hit|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst|hit|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst|sum_out[0]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst|sum_out[0]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst|sum_out[1]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst|sum_out[1]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst|sum_out[2]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst|sum_out[2]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst|sum_out[3]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst|sum_out[3]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst|sum_out[4]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst|sum_out[4]|clk ; +; 0.500 ; 0.500 ; 0.000 ; High Pulse Width ; clk ; Rise ; inst|sum_out[5]|clk ; +; 0.500 ; 0.500 ; 0.000 ; Low Pulse Width ; clk ; Rise ; inst|sum_out[5]|clk ; ++--------+--------------+----------------+------------------+-------+------------+--------------------------------------+ + + ++----------------------------------------------------------------------------+ +; Setup Times ; ++----------------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++----------------+------------+-------+-------+------------+-----------------+ +; player_sum[*] ; clk ; 3.414 ; 3.414 ; Rise ; clk ; +; player_sum[0] ; clk ; 3.340 ; 3.340 ; Rise ; clk ; +; player_sum[1] ; clk ; 3.414 ; 3.414 ; Rise ; clk ; +; player_sum[2] ; clk ; 3.156 ; 3.156 ; Rise ; clk ; +; player_sum[3] ; clk ; 3.192 ; 3.192 ; Rise ; clk ; +; player_sum[4] ; clk ; 3.179 ; 3.179 ; Rise ; clk ; +; player_sum[5] ; clk ; 2.951 ; 2.951 ; Rise ; clk ; +; sum[*] ; clk ; 2.591 ; 2.591 ; Rise ; clk ; +; sum[0] ; clk ; 2.555 ; 2.555 ; Rise ; clk ; +; sum[1] ; clk ; 2.591 ; 2.591 ; Rise ; clk ; +; sum[2] ; clk ; 2.551 ; 2.551 ; Rise ; clk ; +; sum[3] ; clk ; 2.411 ; 2.411 ; Rise ; clk ; +; sum[4] ; clk ; 2.270 ; 2.270 ; Rise ; clk ; +; sum[5] ; clk ; 2.259 ; 2.259 ; Rise ; clk ; +; turn ; clk ; 1.666 ; 1.666 ; Rise ; clk ; ++----------------+------------+-------+-------+------------+-----------------+ + + ++------------------------------------------------------------------------------+ +; Hold Times ; ++----------------+------------+--------+--------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++----------------+------------+--------+--------+------------+-----------------+ +; player_sum[*] ; clk ; -1.764 ; -1.764 ; Rise ; clk ; +; player_sum[0] ; clk ; -2.401 ; -2.401 ; Rise ; clk ; +; player_sum[1] ; clk ; -2.318 ; -2.318 ; Rise ; clk ; +; player_sum[2] ; clk ; -2.237 ; -2.237 ; Rise ; clk ; +; player_sum[3] ; clk ; -2.235 ; -2.235 ; Rise ; clk ; +; player_sum[4] ; clk ; -2.018 ; -2.018 ; Rise ; clk ; +; player_sum[5] ; clk ; -1.764 ; -1.764 ; Rise ; clk ; +; sum[*] ; clk ; -1.531 ; -1.531 ; Rise ; clk ; +; sum[0] ; clk ; -1.559 ; -1.559 ; Rise ; clk ; +; sum[1] ; clk ; -1.660 ; -1.660 ; Rise ; clk ; +; sum[2] ; clk ; -1.538 ; -1.538 ; Rise ; clk ; +; sum[3] ; clk ; -1.531 ; -1.531 ; Rise ; clk ; +; sum[4] ; clk ; -1.544 ; -1.544 ; Rise ; clk ; +; sum[5] ; clk ; -1.607 ; -1.607 ; Rise ; clk ; +; turn ; clk ; -1.546 ; -1.546 ; Rise ; clk ; ++----------------+------------+--------+--------+------------+-----------------+ + + ++------------------------------------------------------------------------------+ +; Clock to Output Times ; ++------------------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++------------------+------------+-------+-------+------------+-----------------+ +; dealer_wins ; clk ; 3.752 ; 3.752 ; Rise ; clk ; +; done ; clk ; 3.748 ; 3.748 ; Rise ; clk ; +; hit ; clk ; 3.757 ; 3.757 ; Rise ; clk ; +; led_display1[*] ; clk ; 3.919 ; 3.919 ; Rise ; clk ; +; led_display1[0] ; clk ; 3.889 ; 3.889 ; Rise ; clk ; +; led_display1[1] ; clk ; 3.919 ; 3.919 ; Rise ; clk ; +; led_display1[2] ; clk ; 3.779 ; 3.779 ; Rise ; clk ; +; led_display1[3] ; clk ; 3.757 ; 3.757 ; Rise ; clk ; +; led_display1[6] ; clk ; 3.889 ; 3.889 ; Rise ; clk ; +; led_display2[*] ; clk ; 4.079 ; 4.079 ; Rise ; clk ; +; led_display2[0] ; clk ; 4.079 ; 4.079 ; Rise ; clk ; +; led_display2[5] ; clk ; 3.881 ; 3.881 ; Rise ; clk ; +; led_display3[*] ; clk ; 3.901 ; 3.901 ; Rise ; clk ; +; led_display3[0] ; clk ; 3.901 ; 3.901 ; Rise ; clk ; +; led_display3[1] ; clk ; 3.779 ; 3.779 ; Rise ; clk ; +; led_display3[3] ; clk ; 3.769 ; 3.769 ; Rise ; clk ; +; led_display3[5] ; clk ; 3.766 ; 3.766 ; Rise ; clk ; +; led_display3[6] ; clk ; 3.746 ; 3.746 ; Rise ; clk ; +; led_display4[*] ; clk ; 4.069 ; 4.069 ; Rise ; clk ; +; led_display4[0] ; clk ; 3.919 ; 3.919 ; Rise ; clk ; +; led_display4[1] ; clk ; 4.069 ; 4.069 ; Rise ; clk ; +; led_display4[2] ; clk ; 4.062 ; 4.062 ; Rise ; clk ; +; led_display4[3] ; clk ; 4.062 ; 4.062 ; Rise ; clk ; +; led_display4[6] ; clk ; 3.739 ; 3.739 ; Rise ; clk ; +; player_wins ; clk ; 3.742 ; 3.742 ; Rise ; clk ; +; state_out[*] ; clk ; 3.790 ; 3.790 ; Rise ; clk ; +; state_out[0] ; clk ; 3.790 ; 3.790 ; Rise ; clk ; +; state_out[1] ; clk ; 3.765 ; 3.765 ; Rise ; clk ; +; sum_out[*] ; clk ; 3.937 ; 3.937 ; Rise ; clk ; +; sum_out[0] ; clk ; 3.786 ; 3.786 ; Rise ; clk ; +; sum_out[1] ; clk ; 3.870 ; 3.870 ; Rise ; clk ; +; sum_out[2] ; clk ; 3.850 ; 3.850 ; Rise ; clk ; +; sum_out[3] ; clk ; 3.784 ; 3.784 ; Rise ; clk ; +; sum_out[4] ; clk ; 3.810 ; 3.810 ; Rise ; clk ; +; sum_out[5] ; clk ; 3.937 ; 3.937 ; Rise ; clk ; ++------------------+------------+-------+-------+------------+-----------------+ + + ++------------------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++------------------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++------------------+------------+-------+-------+------------+-----------------+ +; dealer_wins ; clk ; 3.752 ; 3.752 ; Rise ; clk ; +; done ; clk ; 3.748 ; 3.748 ; Rise ; clk ; +; hit ; clk ; 3.757 ; 3.757 ; Rise ; clk ; +; led_display1[*] ; clk ; 3.757 ; 3.757 ; Rise ; clk ; +; led_display1[0] ; clk ; 3.889 ; 3.889 ; Rise ; clk ; +; led_display1[1] ; clk ; 3.919 ; 3.919 ; Rise ; clk ; +; led_display1[2] ; clk ; 3.779 ; 3.779 ; Rise ; clk ; +; led_display1[3] ; clk ; 3.757 ; 3.757 ; Rise ; clk ; +; led_display1[6] ; clk ; 3.889 ; 3.889 ; Rise ; clk ; +; led_display2[*] ; clk ; 3.881 ; 3.881 ; Rise ; clk ; +; led_display2[0] ; clk ; 4.079 ; 4.079 ; Rise ; clk ; +; led_display2[5] ; clk ; 3.881 ; 3.881 ; Rise ; clk ; +; led_display3[*] ; clk ; 3.746 ; 3.746 ; Rise ; clk ; +; led_display3[0] ; clk ; 3.901 ; 3.901 ; Rise ; clk ; +; led_display3[1] ; clk ; 3.779 ; 3.779 ; Rise ; clk ; +; led_display3[3] ; clk ; 3.769 ; 3.769 ; Rise ; clk ; +; led_display3[5] ; clk ; 3.766 ; 3.766 ; Rise ; clk ; +; led_display3[6] ; clk ; 3.746 ; 3.746 ; Rise ; clk ; +; led_display4[*] ; clk ; 3.739 ; 3.739 ; Rise ; clk ; +; led_display4[0] ; clk ; 3.919 ; 3.919 ; Rise ; clk ; +; led_display4[1] ; clk ; 4.069 ; 4.069 ; Rise ; clk ; +; led_display4[2] ; clk ; 4.062 ; 4.062 ; Rise ; clk ; +; led_display4[3] ; clk ; 4.062 ; 4.062 ; Rise ; clk ; +; led_display4[6] ; clk ; 3.739 ; 3.739 ; Rise ; clk ; +; player_wins ; clk ; 3.742 ; 3.742 ; Rise ; clk ; +; state_out[*] ; clk ; 3.765 ; 3.765 ; Rise ; clk ; +; state_out[0] ; clk ; 3.790 ; 3.790 ; Rise ; clk ; +; state_out[1] ; clk ; 3.765 ; 3.765 ; Rise ; clk ; +; sum_out[*] ; clk ; 3.784 ; 3.784 ; Rise ; clk ; +; sum_out[0] ; clk ; 3.786 ; 3.786 ; Rise ; clk ; +; sum_out[1] ; clk ; 3.870 ; 3.870 ; Rise ; clk ; +; sum_out[2] ; clk ; 3.850 ; 3.850 ; Rise ; clk ; +; sum_out[3] ; clk ; 3.784 ; 3.784 ; Rise ; clk ; +; sum_out[4] ; clk ; 3.810 ; 3.810 ; Rise ; clk ; +; sum_out[5] ; clk ; 3.937 ; 3.937 ; Rise ; clk ; ++------------------+------------+-------+-------+------------+-----------------+ + + ++-------------------------------------------------------------------------------+ +; Multicorner Timing Analysis Summary ; ++------------------+---------+-------+----------+---------+---------------------+ +; Clock ; Setup ; Hold ; Recovery ; Removal ; Minimum Pulse Width ; ++------------------+---------+-------+----------+---------+---------------------+ +; Worst-case Slack ; -4.118 ; 0.215 ; N/A ; N/A ; -1.631 ; +; clk ; -4.118 ; 0.215 ; N/A ; N/A ; -1.631 ; +; Design-wide TNS ; -25.738 ; 0.0 ; 0.0 ; 0.0 ; -22.405 ; +; clk ; -25.738 ; 0.000 ; N/A ; N/A ; -22.405 ; ++------------------+---------+-------+----------+---------+---------------------+ + + ++----------------------------------------------------------------------------+ +; Setup Times ; ++----------------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++----------------+------------+-------+-------+------------+-----------------+ +; player_sum[*] ; clk ; 8.247 ; 8.247 ; Rise ; clk ; +; player_sum[0] ; clk ; 7.974 ; 7.974 ; Rise ; clk ; +; player_sum[1] ; clk ; 8.247 ; 8.247 ; Rise ; clk ; +; player_sum[2] ; clk ; 7.565 ; 7.565 ; Rise ; clk ; +; player_sum[3] ; clk ; 7.714 ; 7.714 ; Rise ; clk ; +; player_sum[4] ; clk ; 7.628 ; 7.628 ; Rise ; clk ; +; player_sum[5] ; clk ; 6.924 ; 6.924 ; Rise ; clk ; +; sum[*] ; clk ; 6.241 ; 6.241 ; Rise ; clk ; +; sum[0] ; clk ; 6.241 ; 6.241 ; Rise ; clk ; +; sum[1] ; clk ; 6.187 ; 6.187 ; Rise ; clk ; +; sum[2] ; clk ; 6.225 ; 6.225 ; Rise ; clk ; +; sum[3] ; clk ; 5.864 ; 5.864 ; Rise ; clk ; +; sum[4] ; clk ; 5.461 ; 5.461 ; Rise ; clk ; +; sum[5] ; clk ; 5.413 ; 5.413 ; Rise ; clk ; +; turn ; clk ; 3.772 ; 3.772 ; Rise ; clk ; ++----------------+------------+-------+-------+------------+-----------------+ + + ++------------------------------------------------------------------------------+ +; Hold Times ; ++----------------+------------+--------+--------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++----------------+------------+--------+--------+------------+-----------------+ +; player_sum[*] ; clk ; -1.764 ; -1.764 ; Rise ; clk ; +; player_sum[0] ; clk ; -2.401 ; -2.401 ; Rise ; clk ; +; player_sum[1] ; clk ; -2.318 ; -2.318 ; Rise ; clk ; +; player_sum[2] ; clk ; -2.237 ; -2.237 ; Rise ; clk ; +; player_sum[3] ; clk ; -2.235 ; -2.235 ; Rise ; clk ; +; player_sum[4] ; clk ; -2.018 ; -2.018 ; Rise ; clk ; +; player_sum[5] ; clk ; -1.764 ; -1.764 ; Rise ; clk ; +; sum[*] ; clk ; -1.531 ; -1.531 ; Rise ; clk ; +; sum[0] ; clk ; -1.559 ; -1.559 ; Rise ; clk ; +; sum[1] ; clk ; -1.660 ; -1.660 ; Rise ; clk ; +; sum[2] ; clk ; -1.538 ; -1.538 ; Rise ; clk ; +; sum[3] ; clk ; -1.531 ; -1.531 ; Rise ; clk ; +; sum[4] ; clk ; -1.544 ; -1.544 ; Rise ; clk ; +; sum[5] ; clk ; -1.607 ; -1.607 ; Rise ; clk ; +; turn ; clk ; -1.546 ; -1.546 ; Rise ; clk ; ++----------------+------------+--------+--------+------------+-----------------+ + + ++------------------------------------------------------------------------------+ +; Clock to Output Times ; ++------------------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++------------------+------------+-------+-------+------------+-----------------+ +; dealer_wins ; clk ; 6.926 ; 6.926 ; Rise ; clk ; +; done ; clk ; 6.863 ; 6.863 ; Rise ; clk ; +; hit ; clk ; 6.871 ; 6.871 ; Rise ; clk ; +; led_display1[*] ; clk ; 7.305 ; 7.305 ; Rise ; clk ; +; led_display1[0] ; clk ; 7.275 ; 7.275 ; Rise ; clk ; +; led_display1[1] ; clk ; 7.305 ; 7.305 ; Rise ; clk ; +; led_display1[2] ; clk ; 6.952 ; 6.952 ; Rise ; clk ; +; led_display1[3] ; clk ; 6.932 ; 6.932 ; Rise ; clk ; +; led_display1[6] ; clk ; 7.275 ; 7.275 ; Rise ; clk ; +; led_display2[*] ; clk ; 7.707 ; 7.707 ; Rise ; clk ; +; led_display2[0] ; clk ; 7.707 ; 7.707 ; Rise ; clk ; +; led_display2[5] ; clk ; 7.263 ; 7.263 ; Rise ; clk ; +; led_display3[*] ; clk ; 7.283 ; 7.283 ; Rise ; clk ; +; led_display3[0] ; clk ; 7.283 ; 7.283 ; Rise ; clk ; +; led_display3[1] ; clk ; 6.952 ; 6.952 ; Rise ; clk ; +; led_display3[3] ; clk ; 6.942 ; 6.942 ; Rise ; clk ; +; led_display3[5] ; clk ; 6.939 ; 6.939 ; Rise ; clk ; +; led_display3[6] ; clk ; 6.919 ; 6.919 ; Rise ; clk ; +; led_display4[*] ; clk ; 7.697 ; 7.697 ; Rise ; clk ; +; led_display4[0] ; clk ; 7.305 ; 7.305 ; Rise ; clk ; +; led_display4[1] ; clk ; 7.697 ; 7.697 ; Rise ; clk ; +; led_display4[2] ; clk ; 7.689 ; 7.689 ; Rise ; clk ; +; led_display4[3] ; clk ; 7.689 ; 7.689 ; Rise ; clk ; +; led_display4[6] ; clk ; 6.912 ; 6.912 ; Rise ; clk ; +; player_wins ; clk ; 6.911 ; 6.911 ; Rise ; clk ; +; state_out[*] ; clk ; 6.910 ; 6.910 ; Rise ; clk ; +; state_out[0] ; clk ; 6.910 ; 6.910 ; Rise ; clk ; +; state_out[1] ; clk ; 6.889 ; 6.889 ; Rise ; clk ; +; sum_out[*] ; clk ; 7.326 ; 7.326 ; Rise ; clk ; +; sum_out[0] ; clk ; 6.908 ; 6.908 ; Rise ; clk ; +; sum_out[1] ; clk ; 7.170 ; 7.170 ; Rise ; clk ; +; sum_out[2] ; clk ; 7.139 ; 7.139 ; Rise ; clk ; +; sum_out[3] ; clk ; 6.905 ; 6.905 ; Rise ; clk ; +; sum_out[4] ; clk ; 7.145 ; 7.145 ; Rise ; clk ; +; sum_out[5] ; clk ; 7.326 ; 7.326 ; Rise ; clk ; ++------------------+------------+-------+-------+------------+-----------------+ + + ++------------------------------------------------------------------------------+ +; Minimum Clock to Output Times ; ++------------------+------------+-------+-------+------------+-----------------+ +; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ; ++------------------+------------+-------+-------+------------+-----------------+ +; dealer_wins ; clk ; 3.752 ; 3.752 ; Rise ; clk ; +; done ; clk ; 3.748 ; 3.748 ; Rise ; clk ; +; hit ; clk ; 3.757 ; 3.757 ; Rise ; clk ; +; led_display1[*] ; clk ; 3.757 ; 3.757 ; Rise ; clk ; +; led_display1[0] ; clk ; 3.889 ; 3.889 ; Rise ; clk ; +; led_display1[1] ; clk ; 3.919 ; 3.919 ; Rise ; clk ; +; led_display1[2] ; clk ; 3.779 ; 3.779 ; Rise ; clk ; +; led_display1[3] ; clk ; 3.757 ; 3.757 ; Rise ; clk ; +; led_display1[6] ; clk ; 3.889 ; 3.889 ; Rise ; clk ; +; led_display2[*] ; clk ; 3.881 ; 3.881 ; Rise ; clk ; +; led_display2[0] ; clk ; 4.079 ; 4.079 ; Rise ; clk ; +; led_display2[5] ; clk ; 3.881 ; 3.881 ; Rise ; clk ; +; led_display3[*] ; clk ; 3.746 ; 3.746 ; Rise ; clk ; +; led_display3[0] ; clk ; 3.901 ; 3.901 ; Rise ; clk ; +; led_display3[1] ; clk ; 3.779 ; 3.779 ; Rise ; clk ; +; led_display3[3] ; clk ; 3.769 ; 3.769 ; Rise ; clk ; +; led_display3[5] ; clk ; 3.766 ; 3.766 ; Rise ; clk ; +; led_display3[6] ; clk ; 3.746 ; 3.746 ; Rise ; clk ; +; led_display4[*] ; clk ; 3.739 ; 3.739 ; Rise ; clk ; +; led_display4[0] ; clk ; 3.919 ; 3.919 ; Rise ; clk ; +; led_display4[1] ; clk ; 4.069 ; 4.069 ; Rise ; clk ; +; led_display4[2] ; clk ; 4.062 ; 4.062 ; Rise ; clk ; +; led_display4[3] ; clk ; 4.062 ; 4.062 ; Rise ; clk ; +; led_display4[6] ; clk ; 3.739 ; 3.739 ; Rise ; clk ; +; player_wins ; clk ; 3.742 ; 3.742 ; Rise ; clk ; +; state_out[*] ; clk ; 3.765 ; 3.765 ; Rise ; clk ; +; state_out[0] ; clk ; 3.790 ; 3.790 ; Rise ; clk ; +; state_out[1] ; clk ; 3.765 ; 3.765 ; Rise ; clk ; +; sum_out[*] ; clk ; 3.784 ; 3.784 ; Rise ; clk ; +; sum_out[0] ; clk ; 3.786 ; 3.786 ; Rise ; clk ; +; sum_out[1] ; clk ; 3.870 ; 3.870 ; Rise ; clk ; +; sum_out[2] ; clk ; 3.850 ; 3.850 ; Rise ; clk ; +; sum_out[3] ; clk ; 3.784 ; 3.784 ; Rise ; clk ; +; sum_out[4] ; clk ; 3.810 ; 3.810 ; Rise ; clk ; +; sum_out[5] ; clk ; 3.937 ; 3.937 ; Rise ; clk ; ++------------------+------------+-------+-------+------------+-----------------+ + + ++-------------------------------------------------------------------+ +; Setup Transfers ; ++------------+----------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+----------+----------+----------+----------+ +; clk ; clk ; 456 ; 0 ; 0 ; 0 ; ++------------+----------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + ++-------------------------------------------------------------------+ +; Hold Transfers ; ++------------+----------+----------+----------+----------+----------+ +; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ; ++------------+----------+----------+----------+----------+----------+ +; clk ; clk ; 456 ; 0 ; 0 ; 0 ; ++------------+----------+----------+----------+----------+----------+ +Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported. + + +--------------- +; Report TCCS ; +--------------- +No dedicated SERDES Transmitter circuitry present in device or used in design + + +--------------- +; Report RSKM ; +--------------- +No dedicated SERDES Receiver circuitry present in device or used in design + + ++------------------------------------------------+ +; Unconstrained Paths ; ++---------------------------------+-------+------+ +; Property ; Setup ; Hold ; ++---------------------------------+-------+------+ +; Illegal Clocks ; 0 ; 0 ; +; Unconstrained Clocks ; 0 ; 0 ; +; Unconstrained Input Ports ; 14 ; 14 ; +; Unconstrained Input Port Paths ; 77 ; 77 ; +; Unconstrained Output Ports ; 29 ; 29 ; +; Unconstrained Output Port Paths ; 29 ; 29 ; ++---------------------------------+-------+------+ + + ++------------------------------------+ +; TimeQuest Timing Analyzer Messages ; ++------------------------------------+ +Info: ******************************************************************* +Info: Running Quartus II 64-Bit TimeQuest Timing Analyzer + Info: Version 13.0.0 Build 156 04/24/2013 SJ Web Edition + Info: Processing started: Wed Nov 29 18:54:40 2017 +Info: Command: quartus_sta gA6_lab5 -c gA6_lab5 +Info: qsta_default_script.tcl version: #1 +Info (11104): Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead. +Info (21077): Low junction temperature is 0 degrees C +Info (21077): High junction temperature is 85 degrees C +Critical Warning (332012): Synopsys Design Constraints File file not found: 'gA6_lab5.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design. +Info (332142): No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0" +Info (332105): Deriving Clocks + Info (332105): create_clock -period 1.000 -name clk clk +Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON +Info: Analyzing Slow Model +Critical Warning (332148): Timing requirements not met +Info (332146): Worst-case setup slack is -4.118 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): -4.118 -25.738 clk +Info (332146): Worst-case hold slack is 0.445 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 0.445 0.000 clk +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is -1.631 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): -1.631 -22.405 clk +Info (332001): The selected device family is not supported by the report_metastability command. +Info: Analyzing Fast Model +Critical Warning (332148): Timing requirements not met +Info (332146): Worst-case setup slack is -1.010 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): -1.010 -5.377 clk +Info (332146): Worst-case hold slack is 0.215 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): 0.215 0.000 clk +Info (332140): No Recovery paths to report +Info (332140): No Removal paths to report +Info (332146): Worst-case minimum pulse width slack is -1.380 + Info (332119): Slack End Point TNS Clock + Info (332119): ========= ============= ===================== + Info (332119): -1.380 -18.380 clk +Info (332001): The selected device family is not supported by the report_metastability command. +Info (332102): Design is not fully constrained for setup requirements +Info (332102): Design is not fully constrained for hold requirements +Info: Quartus II 64-Bit TimeQuest Timing Analyzer was successful. 0 errors, 3 warnings + Info: Peak virtual memory: 530 megabytes + Info: Processing ended: Wed Nov 29 18:54:43 2017 + Info: Elapsed time: 00:00:03 + Info: Total CPU time (on all processors): 00:00:02 + + diff --git a/lab5/output_files/gA6_lab5.sta.summary b/lab5/output_files/gA6_lab5.sta.summary new file mode 100644 index 0000000..13d4143 --- /dev/null +++ b/lab5/output_files/gA6_lab5.sta.summary @@ -0,0 +1,29 @@ +------------------------------------------------------------ +TimeQuest Timing Analyzer Summary +------------------------------------------------------------ + +Type : Slow Model Setup 'clk' +Slack : -4.118 +TNS : -25.738 + +Type : Slow Model Hold 'clk' +Slack : 0.445 +TNS : 0.000 + +Type : Slow Model Minimum Pulse Width 'clk' +Slack : -1.631 +TNS : -22.405 + +Type : Fast Model Setup 'clk' +Slack : -1.010 +TNS : -5.377 + +Type : Fast Model Hold 'clk' +Slack : 0.215 +TNS : 0.000 + +Type : Fast Model Minimum Pulse Width 'clk' +Slack : -1.380 +TNS : -18.380 + +------------------------------------------------------------ diff --git a/lab5/simulation/modelsim/gA6_lab5.sft b/lab5/simulation/modelsim/gA6_lab5.sft new file mode 100644 index 0000000..f324fea --- /dev/null +++ b/lab5/simulation/modelsim/gA6_lab5.sft @@ -0,0 +1 @@ +set tool_name "ModelSim-Altera (Verilog)" diff --git a/lab5/simulation/modelsim/gA6_lab5.vho b/lab5/simulation/modelsim/gA6_lab5.vho new file mode 100644 index 0000000..f877b3e --- /dev/null +++ b/lab5/simulation/modelsim/gA6_lab5.vho @@ -0,0 +1,2415 @@ +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- VENDOR "Altera" +-- PROGRAM "Quartus II 64-Bit" +-- VERSION "Version 13.0.0 Build 156 04/24/2013 SJ Web Edition" + +-- DATE "11/29/2017 18:38:50" + +-- +-- Device: Altera EP2C20F484C7 Package FBGA484 +-- + +-- +-- This VHDL file should be used for ModelSim-Altera (VHDL) only +-- + +LIBRARY CYCLONEII; +LIBRARY IEEE; +USE CYCLONEII.CYCLONEII_COMPONENTS.ALL; +USE IEEE.STD_LOGIC_1164.ALL; + +ENTITY gA6_lab5 IS + PORT ( + hit : OUT std_logic; + clk : IN std_logic; + rst : IN std_logic; + turn : IN std_logic; + sum : IN std_logic_vector(5 DOWNTO 0); + done : OUT std_logic; + player_wins : OUT std_logic; + player_sum : IN std_logic_vector(5 DOWNTO 0); + dealer_wins : OUT std_logic; + led_display1 : OUT std_logic_vector(6 DOWNTO 0); + led_display2 : OUT std_logic_vector(6 DOWNTO 0); + led_display3 : OUT std_logic_vector(6 DOWNTO 0); + led_display4 : OUT std_logic_vector(6 DOWNTO 0); + sum_out : OUT std_logic_vector(5 DOWNTO 0) + ); +END gA6_lab5; + +-- Design Ports Information +-- hit => Location: PIN_T2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- done => Location: PIN_R1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- player_wins => Location: PIN_Y4, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- dealer_wins => Location: PIN_T6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display1[6] => Location: PIN_N2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display1[5] => Location: PIN_C14, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display1[4] => Location: PIN_B19, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display1[3] => Location: PIN_P1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display1[2] => Location: PIN_AA4, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display1[1] => Location: PIN_M5, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display1[0] => Location: PIN_N6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display2[6] => Location: PIN_AA13, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display2[5] => Location: PIN_AB4, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display2[4] => Location: PIN_A18, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display2[3] => Location: PIN_C7, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display2[2] => Location: PIN_AA6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display2[1] => Location: PIN_A5, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display2[0] => Location: PIN_P6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display3[6] => Location: PIN_W3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display3[5] => Location: PIN_Y3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display3[4] => Location: PIN_B6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display3[3] => Location: PIN_W4, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display3[2] => Location: PIN_F11, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display3[1] => Location: PIN_AA3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display3[0] => Location: PIN_AB3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display4[6] => Location: PIN_W5, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display4[5] => Location: PIN_V8, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display4[4] => Location: PIN_A19, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display4[3] => Location: PIN_N3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display4[2] => Location: PIN_P3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display4[1] => Location: PIN_N4, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display4[0] => Location: PIN_M6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- sum_out[5] => Location: PIN_R5, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- sum_out[4] => Location: PIN_U2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- sum_out[3] => Location: PIN_W2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- sum_out[2] => Location: PIN_P2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- sum_out[1] => Location: PIN_V1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- sum_out[0] => Location: PIN_T5, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- clk => Location: PIN_M1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- rst => Location: PIN_M2, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- player_sum[5] => Location: PIN_R6, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- player_sum[4] => Location: PIN_U1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- player_sum[3] => Location: PIN_W1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- player_sum[2] => Location: PIN_V2, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- player_sum[1] => Location: PIN_Y1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- player_sum[0] => Location: PIN_Y2, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- sum[5] => Location: PIN_R8, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- sum[4] => Location: PIN_T3, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- sum[3] => Location: PIN_U3, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- sum[2] => Location: PIN_R7, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- sum[1] => Location: PIN_T1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- sum[0] => Location: PIN_P5, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- turn => Location: PIN_R2, I/O Standard: 3.3-V LVTTL, Current Strength: Default + + +ARCHITECTURE structure OF gA6_lab5 IS +SIGNAL gnd : std_logic := '0'; +SIGNAL vcc : std_logic := '1'; +SIGNAL unknown : std_logic := 'X'; +SIGNAL devoe : std_logic := '1'; +SIGNAL devclrn : std_logic := '1'; +SIGNAL devpor : std_logic := '1'; +SIGNAL ww_devoe : std_logic; +SIGNAL ww_devclrn : std_logic; +SIGNAL ww_devpor : std_logic; +SIGNAL ww_hit : std_logic; +SIGNAL ww_clk : std_logic; +SIGNAL ww_rst : std_logic; +SIGNAL ww_turn : std_logic; +SIGNAL ww_sum : std_logic_vector(5 DOWNTO 0); +SIGNAL ww_done : std_logic; +SIGNAL ww_player_wins : std_logic; +SIGNAL ww_player_sum : std_logic_vector(5 DOWNTO 0); +SIGNAL ww_dealer_wins : std_logic; +SIGNAL ww_led_display1 : std_logic_vector(6 DOWNTO 0); +SIGNAL ww_led_display2 : std_logic_vector(6 DOWNTO 0); +SIGNAL ww_led_display3 : std_logic_vector(6 DOWNTO 0); +SIGNAL ww_led_display4 : std_logic_vector(6 DOWNTO 0); +SIGNAL ww_sum_out : std_logic_vector(5 DOWNTO 0); +SIGNAL \clk~clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0); +SIGNAL \rst~clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0); +SIGNAL \inst1|p_win~0_combout\ : std_logic; +SIGNAL \inst1|p_win~2_combout\ : std_logic; +SIGNAL \inst|computer:state[1]~0_combout\ : std_logic; +SIGNAL \turn~combout\ : std_logic; +SIGNAL \clk~combout\ : std_logic; +SIGNAL \clk~clkctrl_outclk\ : std_logic; +SIGNAL \inst|computer:state[0]~0_combout\ : std_logic; +SIGNAL \inst|computer:state[0]~1_combout\ : std_logic; +SIGNAL \inst|computer:state[0]~2_combout\ : std_logic; +SIGNAL \rst~combout\ : std_logic; +SIGNAL \rst~clkctrl_outclk\ : std_logic; +SIGNAL \inst|computer:state[0]~regout\ : std_logic; +SIGNAL \inst|computer:state[1]~1_combout\ : std_logic; +SIGNAL \inst|computer:state[1]~regout\ : std_logic; +SIGNAL \inst|Mux0~0_combout\ : std_logic; +SIGNAL \inst|hit~regout\ : std_logic; +SIGNAL \inst|Mux1~0_combout\ : std_logic; +SIGNAL \inst|done~regout\ : std_logic; +SIGNAL \inst1|p_win~6_combout\ : std_logic; +SIGNAL \inst1|LessThan2~1_cout\ : std_logic; +SIGNAL \inst1|LessThan2~3_cout\ : std_logic; +SIGNAL \inst1|LessThan2~5_cout\ : std_logic; +SIGNAL \inst1|LessThan2~7_cout\ : std_logic; +SIGNAL \inst1|LessThan2~9_cout\ : std_logic; +SIGNAL \inst1|LessThan2~10_combout\ : std_logic; +SIGNAL \inst1|LessThan3~1_cout\ : std_logic; +SIGNAL \inst1|LessThan3~3_cout\ : std_logic; +SIGNAL \inst1|LessThan3~5_cout\ : std_logic; +SIGNAL \inst1|LessThan3~7_cout\ : std_logic; +SIGNAL \inst1|LessThan3~9_cout\ : std_logic; +SIGNAL \inst1|LessThan3~10_combout\ : std_logic; +SIGNAL \inst1|p_win~1_combout\ : std_logic; +SIGNAL \inst1|Equal0~0_combout\ : std_logic; +SIGNAL \inst1|Equal0~1_combout\ : std_logic; +SIGNAL \inst1|Equal0~2_combout\ : std_logic; +SIGNAL \inst1|p_win~3_combout\ : std_logic; +SIGNAL \inst1|p_win~4_combout\ : std_logic; +SIGNAL \inst1|p_win~5_combout\ : std_logic; +SIGNAL \inst1|p_win~7_combout\ : std_logic; +SIGNAL \inst1|player_wins~regout\ : std_logic; +SIGNAL \inst1|dealer:d_win~regout\ : std_logic; +SIGNAL \inst1|d_win~0_combout\ : std_logic; +SIGNAL \inst1|dealer_wins~regout\ : std_logic; +SIGNAL \inst1|led_display1~6_combout\ : std_logic; +SIGNAL \inst1|led_display1~4_combout\ : std_logic; +SIGNAL \inst1|dealer:p_win~regout\ : std_logic; +SIGNAL \inst1|led_display1[0]~7_combout\ : std_logic; +SIGNAL \inst1|led_display1[0]~5_combout\ : std_logic; +SIGNAL \inst1|led_display3~3_combout\ : std_logic; +SIGNAL \inst1|led_display3~2_combout\ : std_logic; +SIGNAL \inst|sum_out\ : std_logic_vector(5 DOWNTO 0); +SIGNAL \inst1|led_display4\ : std_logic_vector(6 DOWNTO 0); +SIGNAL \inst1|led_display3\ : std_logic_vector(6 DOWNTO 0); +SIGNAL \inst1|led_display1\ : std_logic_vector(6 DOWNTO 0); +SIGNAL \sum~combout\ : std_logic_vector(5 DOWNTO 0); +SIGNAL \player_sum~combout\ : std_logic_vector(5 DOWNTO 0); +SIGNAL \inst1|ALT_INV_led_display4\ : std_logic_vector(3 DOWNTO 3); +SIGNAL \inst1|ALT_INV_led_display3\ : std_logic_vector(1 DOWNTO 1); +SIGNAL \inst1|ALT_INV_led_display1\ : std_logic_vector(0 DOWNTO 0); + +BEGIN + +hit <= ww_hit; +ww_clk <= clk; +ww_rst <= rst; +ww_turn <= turn; +ww_sum <= sum; +done <= ww_done; +player_wins <= ww_player_wins; +ww_player_sum <= player_sum; +dealer_wins <= ww_dealer_wins; +led_display1 <= ww_led_display1; +led_display2 <= ww_led_display2; +led_display3 <= ww_led_display3; +led_display4 <= ww_led_display4; +sum_out <= ww_sum_out; +ww_devoe <= devoe; +ww_devclrn <= devclrn; +ww_devpor <= devpor; + +\clk~clkctrl_INCLK_bus\ <= (gnd & gnd & gnd & \clk~combout\); + +\rst~clkctrl_INCLK_bus\ <= (gnd & gnd & gnd & \rst~combout\); +\inst1|ALT_INV_led_display4\(3) <= NOT \inst1|led_display4\(3); +\inst1|ALT_INV_led_display3\(1) <= NOT \inst1|led_display3\(1); +\inst1|ALT_INV_led_display1\(0) <= NOT \inst1|led_display1\(0); + +-- Location: LCCOMB_X1_Y7_N2 +\inst1|p_win~0\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|p_win~0_combout\ = (\inst|sum_out\(4) & ((\inst|sum_out\(3)) # ((\inst|sum_out\(1) & \inst|sum_out\(2))))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1010100010001000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|sum_out\(4), + datab => \inst|sum_out\(3), + datac => \inst|sum_out\(1), + datad => \inst|sum_out\(2), + combout => \inst1|p_win~0_combout\); + +-- Location: LCCOMB_X1_Y7_N30 +\inst1|p_win~2\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|p_win~2_combout\ = (\player_sum~combout\(4) & ((\player_sum~combout\(3)) # ((\player_sum~combout\(2) & \player_sum~combout\(1))))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111000010000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \player_sum~combout\(2), + datab => \player_sum~combout\(1), + datac => \player_sum~combout\(4), + datad => \player_sum~combout\(3), + combout => \inst1|p_win~2_combout\); + +-- Location: LCCOMB_X1_Y8_N30 +\inst|computer:state[1]~0\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst|computer:state[1]~0_combout\ = (\sum~combout\(2)) # ((\sum~combout\(1)) # ((\sum~combout\(0)) # (\sum~combout\(3)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111111111110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \sum~combout\(2), + datab => \sum~combout\(1), + datac => \sum~combout\(0), + datad => \sum~combout\(3), + combout => \inst|computer:state[1]~0_combout\); + +-- Location: PIN_V2, I/O Standard: 3.3-V LVTTL, Current Strength: Default +\player_sum[2]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "input", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => GND, + padio => ww_player_sum(2), + combout => \player_sum~combout\(2)); + +-- Location: PIN_Y2, I/O Standard: 3.3-V LVTTL, Current Strength: Default +\player_sum[0]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "input", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => GND, + padio => ww_player_sum(0), + combout => \player_sum~combout\(0)); + +-- Location: PIN_R2, I/O Standard: 3.3-V LVTTL, Current Strength: Default +\turn~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "input", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => GND, + padio => ww_turn, + combout => \turn~combout\); + +-- Location: PIN_M1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +\clk~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "input", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => GND, + padio => ww_clk, + combout => \clk~combout\); + +-- Location: CLKCTRL_G3 +\clk~clkctrl\ : cycloneii_clkctrl +-- pragma translate_off +GENERIC MAP ( + clock_type => "global clock", + ena_register_mode => "none") +-- pragma translate_on +PORT MAP ( + inclk => \clk~clkctrl_INCLK_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + outclk => \clk~clkctrl_outclk\); + +-- Location: PIN_T3, I/O Standard: 3.3-V LVTTL, Current Strength: Default +\sum[4]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "input", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => GND, + padio => ww_sum(4), + combout => \sum~combout\(4)); + +-- Location: PIN_R8, I/O Standard: 3.3-V LVTTL, Current Strength: Default +\sum[5]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "input", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => GND, + padio => ww_sum(5), + combout => \sum~combout\(5)); + +-- Location: LCCOMB_X1_Y8_N12 +\inst|computer:state[0]~0\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst|computer:state[0]~0_combout\ = (!\inst|computer:state[1]~regout\ & ((!\inst|computer:state[0]~regout\) # (!\sum~combout\(5)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000111111", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \sum~combout\(5), + datac => \inst|computer:state[0]~regout\, + datad => \inst|computer:state[1]~regout\, + combout => \inst|computer:state[0]~0_combout\); + +-- Location: LCCOMB_X1_Y8_N0 +\inst|computer:state[0]~1\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst|computer:state[0]~1_combout\ = (\inst|computer:state[0]~0_combout\ & (((!\inst|computer:state[0]~regout\) # (!\sum~combout\(4))) # (!\inst|computer:state[1]~0_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|computer:state[1]~0_combout\, + datab => \sum~combout\(4), + datac => \inst|computer:state[0]~regout\, + datad => \inst|computer:state[0]~0_combout\, + combout => \inst|computer:state[0]~1_combout\); + +-- Location: LCCOMB_X1_Y8_N20 +\inst|computer:state[0]~2\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst|computer:state[0]~2_combout\ = (\inst|computer:state[0]~1_combout\ & ((\turn~combout\) # (\inst|computer:state[0]~regout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111101000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \turn~combout\, + datac => \inst|computer:state[0]~regout\, + datad => \inst|computer:state[0]~1_combout\, + combout => \inst|computer:state[0]~2_combout\); + +-- Location: PIN_M2, I/O Standard: 3.3-V LVTTL, Current Strength: Default +\rst~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "input", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => GND, + padio => ww_rst, + combout => \rst~combout\); + +-- Location: CLKCTRL_G1 +\rst~clkctrl\ : cycloneii_clkctrl +-- pragma translate_off +GENERIC MAP ( + clock_type => "global clock", + ena_register_mode => "none") +-- pragma translate_on +PORT MAP ( + inclk => \rst~clkctrl_INCLK_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + outclk => \rst~clkctrl_outclk\); + +-- Location: LCFF_X1_Y8_N21 +\inst|computer:state[0]\ : cycloneii_lcell_ff +PORT MAP ( + clk => \clk~clkctrl_outclk\, + datain => \inst|computer:state[0]~2_combout\, + aclr => \rst~clkctrl_outclk\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \inst|computer:state[0]~regout\); + +-- Location: LCCOMB_X1_Y8_N2 +\inst|computer:state[1]~1\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst|computer:state[1]~1_combout\ = (\inst|computer:state[0]~regout\ & (!\inst|computer:state[1]~regout\ & !\inst|computer:state[0]~1_combout\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000001100", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \inst|computer:state[0]~regout\, + datac => \inst|computer:state[1]~regout\, + datad => \inst|computer:state[0]~1_combout\, + combout => \inst|computer:state[1]~1_combout\); + +-- Location: LCFF_X1_Y8_N3 +\inst|computer:state[1]\ : cycloneii_lcell_ff +PORT MAP ( + clk => \clk~clkctrl_outclk\, + datain => \inst|computer:state[1]~1_combout\, + aclr => \rst~clkctrl_outclk\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \inst|computer:state[1]~regout\); + +-- Location: LCCOMB_X1_Y8_N28 +\inst|Mux0~0\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst|Mux0~0_combout\ = (!\inst|computer:state[1]~regout\ & \inst|computer:state[0]~regout\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011001100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \inst|computer:state[1]~regout\, + datad => \inst|computer:state[0]~regout\, + combout => \inst|Mux0~0_combout\); + +-- Location: LCFF_X1_Y8_N29 +\inst|hit\ : cycloneii_lcell_ff +PORT MAP ( + clk => \clk~clkctrl_outclk\, + datain => \inst|Mux0~0_combout\, + aclr => \rst~clkctrl_outclk\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \inst|hit~regout\); + +-- Location: LCCOMB_X1_Y8_N26 +\inst|Mux1~0\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst|Mux1~0_combout\ = (\inst|computer:state[1]~regout\ & !\inst|computer:state[0]~regout\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000011001100", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \inst|computer:state[1]~regout\, + datad => \inst|computer:state[0]~regout\, + combout => \inst|Mux1~0_combout\); + +-- Location: LCFF_X1_Y8_N27 +\inst|done\ : cycloneii_lcell_ff +PORT MAP ( + clk => \clk~clkctrl_outclk\, + datain => \inst|Mux1~0_combout\, + aclr => \rst~clkctrl_outclk\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \inst|done~regout\); + +-- Location: PIN_R6, I/O Standard: 3.3-V LVTTL, Current Strength: Default +\player_sum[5]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "input", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => GND, + padio => ww_player_sum(5), + combout => \player_sum~combout\(5)); + +-- Location: LCCOMB_X2_Y7_N6 +\inst1|p_win~6\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|p_win~6_combout\ = (\inst1|p_win~2_combout\) # (\player_sum~combout\(5)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111101011111010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst1|p_win~2_combout\, + datac => \player_sum~combout\(5), + combout => \inst1|p_win~6_combout\); + +-- Location: LCFF_X1_Y7_N27 +\inst|sum_out[5]\ : cycloneii_lcell_ff +PORT MAP ( + clk => \clk~clkctrl_outclk\, + sdata => \sum~combout\(5), + aclr => \rst~clkctrl_outclk\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \inst|sum_out\(5)); + +-- Location: PIN_U1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +\player_sum[4]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "input", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => GND, + padio => ww_player_sum(4), + combout => \player_sum~combout\(4)); + +-- Location: PIN_U3, I/O Standard: 3.3-V LVTTL, Current Strength: Default +\sum[3]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "input", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => GND, + padio => ww_sum(3), + combout => \sum~combout\(3)); + +-- Location: LCFF_X1_Y7_N23 +\inst|sum_out[3]\ : cycloneii_lcell_ff +PORT MAP ( + clk => \clk~clkctrl_outclk\, + sdata => \sum~combout\(3), + aclr => \rst~clkctrl_outclk\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \inst|sum_out\(3)); + +-- Location: PIN_R7, I/O Standard: 3.3-V LVTTL, Current Strength: Default +\sum[2]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "input", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => GND, + padio => ww_sum(2), + combout => \sum~combout\(2)); + +-- Location: LCFF_X1_Y7_N29 +\inst|sum_out[2]\ : cycloneii_lcell_ff +PORT MAP ( + clk => \clk~clkctrl_outclk\, + sdata => \sum~combout\(2), + aclr => \rst~clkctrl_outclk\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \inst|sum_out\(2)); + +-- Location: PIN_T1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +\sum[1]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "input", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => GND, + padio => ww_sum(1), + combout => \sum~combout\(1)); + +-- Location: LCFF_X1_Y7_N3 +\inst|sum_out[1]\ : cycloneii_lcell_ff +PORT MAP ( + clk => \clk~clkctrl_outclk\, + sdata => \sum~combout\(1), + aclr => \rst~clkctrl_outclk\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \inst|sum_out\(1)); + +-- Location: PIN_P5, I/O Standard: 3.3-V LVTTL, Current Strength: Default +\sum[0]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "input", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => GND, + padio => ww_sum(0), + combout => \sum~combout\(0)); + +-- Location: LCFF_X1_Y7_N1 +\inst|sum_out[0]\ : cycloneii_lcell_ff +PORT MAP ( + clk => \clk~clkctrl_outclk\, + sdata => \sum~combout\(0), + aclr => \rst~clkctrl_outclk\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \inst|sum_out\(0)); + +-- Location: LCCOMB_X1_Y7_N16 +\inst1|LessThan2~1\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|LessThan2~1_cout\ = CARRY((\player_sum~combout\(0) & !\inst|sum_out\(0))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000100010", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \player_sum~combout\(0), + datab => \inst|sum_out\(0), + datad => VCC, + cout => \inst1|LessThan2~1_cout\); + +-- Location: LCCOMB_X1_Y7_N18 +\inst1|LessThan2~3\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|LessThan2~3_cout\ = CARRY((\player_sum~combout\(1) & (\inst|sum_out\(1) & !\inst1|LessThan2~1_cout\)) # (!\player_sum~combout\(1) & ((\inst|sum_out\(1)) # (!\inst1|LessThan2~1_cout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000001001101", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \player_sum~combout\(1), + datab => \inst|sum_out\(1), + datad => VCC, + cin => \inst1|LessThan2~1_cout\, + cout => \inst1|LessThan2~3_cout\); + +-- Location: LCCOMB_X1_Y7_N20 +\inst1|LessThan2~5\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|LessThan2~5_cout\ = CARRY((\player_sum~combout\(2) & ((!\inst1|LessThan2~3_cout\) # (!\inst|sum_out\(2)))) # (!\player_sum~combout\(2) & (!\inst|sum_out\(2) & !\inst1|LessThan2~3_cout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000101011", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \player_sum~combout\(2), + datab => \inst|sum_out\(2), + datad => VCC, + cin => \inst1|LessThan2~3_cout\, + cout => \inst1|LessThan2~5_cout\); + +-- Location: LCCOMB_X1_Y7_N22 +\inst1|LessThan2~7\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|LessThan2~7_cout\ = CARRY((\player_sum~combout\(3) & (\inst|sum_out\(3) & !\inst1|LessThan2~5_cout\)) # (!\player_sum~combout\(3) & ((\inst|sum_out\(3)) # (!\inst1|LessThan2~5_cout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000001001101", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \player_sum~combout\(3), + datab => \inst|sum_out\(3), + datad => VCC, + cin => \inst1|LessThan2~5_cout\, + cout => \inst1|LessThan2~7_cout\); + +-- Location: LCCOMB_X1_Y7_N24 +\inst1|LessThan2~9\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|LessThan2~9_cout\ = CARRY((\inst|sum_out\(4) & (\player_sum~combout\(4) & !\inst1|LessThan2~7_cout\)) # (!\inst|sum_out\(4) & ((\player_sum~combout\(4)) # (!\inst1|LessThan2~7_cout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000001001101", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \inst|sum_out\(4), + datab => \player_sum~combout\(4), + datad => VCC, + cin => \inst1|LessThan2~7_cout\, + cout => \inst1|LessThan2~9_cout\); + +-- Location: LCCOMB_X1_Y7_N26 +\inst1|LessThan2~10\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|LessThan2~10_combout\ = (\player_sum~combout\(5) & ((\inst1|LessThan2~9_cout\) # (!\inst|sum_out\(5)))) # (!\player_sum~combout\(5) & (\inst1|LessThan2~9_cout\ & !\inst|sum_out\(5))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1100000011111100", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + datab => \player_sum~combout\(5), + datad => \inst|sum_out\(5), + cin => \inst1|LessThan2~9_cout\, + combout => \inst1|LessThan2~10_combout\); + +-- Location: LCCOMB_X1_Y7_N4 +\inst1|LessThan3~1\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|LessThan3~1_cout\ = CARRY((!\player_sum~combout\(0) & \inst|sum_out\(0))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000001000100", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \player_sum~combout\(0), + datab => \inst|sum_out\(0), + datad => VCC, + cout => \inst1|LessThan3~1_cout\); + +-- Location: LCCOMB_X1_Y7_N6 +\inst1|LessThan3~3\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|LessThan3~3_cout\ = CARRY((\player_sum~combout\(1) & ((!\inst1|LessThan3~1_cout\) # (!\inst|sum_out\(1)))) # (!\player_sum~combout\(1) & (!\inst|sum_out\(1) & !\inst1|LessThan3~1_cout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000101011", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \player_sum~combout\(1), + datab => \inst|sum_out\(1), + datad => VCC, + cin => \inst1|LessThan3~1_cout\, + cout => \inst1|LessThan3~3_cout\); + +-- Location: LCCOMB_X1_Y7_N8 +\inst1|LessThan3~5\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|LessThan3~5_cout\ = CARRY((\player_sum~combout\(2) & (\inst|sum_out\(2) & !\inst1|LessThan3~3_cout\)) # (!\player_sum~combout\(2) & ((\inst|sum_out\(2)) # (!\inst1|LessThan3~3_cout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000001001101", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \player_sum~combout\(2), + datab => \inst|sum_out\(2), + datad => VCC, + cin => \inst1|LessThan3~3_cout\, + cout => \inst1|LessThan3~5_cout\); + +-- Location: LCCOMB_X1_Y7_N10 +\inst1|LessThan3~7\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|LessThan3~7_cout\ = CARRY((\player_sum~combout\(3) & ((!\inst1|LessThan3~5_cout\) # (!\inst|sum_out\(3)))) # (!\player_sum~combout\(3) & (!\inst|sum_out\(3) & !\inst1|LessThan3~5_cout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000101011", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \player_sum~combout\(3), + datab => \inst|sum_out\(3), + datad => VCC, + cin => \inst1|LessThan3~5_cout\, + cout => \inst1|LessThan3~7_cout\); + +-- Location: LCCOMB_X1_Y7_N12 +\inst1|LessThan3~9\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|LessThan3~9_cout\ = CARRY((\inst|sum_out\(4) & ((!\inst1|LessThan3~7_cout\) # (!\player_sum~combout\(4)))) # (!\inst|sum_out\(4) & (!\player_sum~combout\(4) & !\inst1|LessThan3~7_cout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000101011", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \inst|sum_out\(4), + datab => \player_sum~combout\(4), + datad => VCC, + cin => \inst1|LessThan3~7_cout\, + cout => \inst1|LessThan3~9_cout\); + +-- Location: LCCOMB_X1_Y7_N14 +\inst1|LessThan3~10\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|LessThan3~10_combout\ = (\player_sum~combout\(5) & (\inst1|LessThan3~9_cout\ & \inst|sum_out\(5))) # (!\player_sum~combout\(5) & ((\inst1|LessThan3~9_cout\) # (\inst|sum_out\(5)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111001100110000", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + datab => \player_sum~combout\(5), + datad => \inst|sum_out\(5), + cin => \inst1|LessThan3~9_cout\, + combout => \inst1|LessThan3~10_combout\); + +-- Location: LCCOMB_X2_Y7_N24 +\inst1|p_win~1\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|p_win~1_combout\ = (\inst1|p_win~0_combout\) # ((\inst1|LessThan2~10_combout\) # ((\inst|sum_out\(5)) # (!\inst1|LessThan3~10_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111011111111", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst1|p_win~0_combout\, + datab => \inst1|LessThan2~10_combout\, + datac => \inst|sum_out\(5), + datad => \inst1|LessThan3~10_combout\, + combout => \inst1|p_win~1_combout\); + +-- Location: LCFF_X1_Y7_N25 +\inst|sum_out[4]\ : cycloneii_lcell_ff +PORT MAP ( + clk => \clk~clkctrl_outclk\, + sdata => \sum~combout\(4), + aclr => \rst~clkctrl_outclk\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \inst|sum_out\(4)); + +-- Location: PIN_Y1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +\player_sum[1]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "input", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => GND, + padio => ww_player_sum(1), + combout => \player_sum~combout\(1)); + +-- Location: LCCOMB_X1_Y7_N0 +\inst1|Equal0~0\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|Equal0~0_combout\ = (\player_sum~combout\(0) & (\inst|sum_out\(0) & (\player_sum~combout\(1) $ (!\inst|sum_out\(1))))) # (!\player_sum~combout\(0) & (!\inst|sum_out\(0) & (\player_sum~combout\(1) $ (!\inst|sum_out\(1))))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1000010000100001", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \player_sum~combout\(0), + datab => \player_sum~combout\(1), + datac => \inst|sum_out\(0), + datad => \inst|sum_out\(1), + combout => \inst1|Equal0~0_combout\); + +-- Location: PIN_W1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +\player_sum[3]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "input", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => GND, + padio => ww_player_sum(3), + combout => \player_sum~combout\(3)); + +-- Location: LCCOMB_X1_Y7_N28 +\inst1|Equal0~1\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|Equal0~1_combout\ = (\player_sum~combout\(2) & (\inst|sum_out\(2) & (\player_sum~combout\(3) $ (!\inst|sum_out\(3))))) # (!\player_sum~combout\(2) & (!\inst|sum_out\(2) & (\player_sum~combout\(3) $ (!\inst|sum_out\(3))))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1000010000100001", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \player_sum~combout\(2), + datab => \player_sum~combout\(3), + datac => \inst|sum_out\(2), + datad => \inst|sum_out\(3), + combout => \inst1|Equal0~1_combout\); + +-- Location: LCCOMB_X2_Y7_N14 +\inst1|Equal0~2\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|Equal0~2_combout\ = (\inst1|Equal0~0_combout\ & (\inst1|Equal0~1_combout\ & (\player_sum~combout\(4) $ (!\inst|sum_out\(4))))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1001000000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \player_sum~combout\(4), + datab => \inst|sum_out\(4), + datac => \inst1|Equal0~0_combout\, + datad => \inst1|Equal0~1_combout\, + combout => \inst1|Equal0~2_combout\); + +-- Location: LCCOMB_X2_Y7_N8 +\inst1|p_win~3\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|p_win~3_combout\ = (\player_sum~combout\(5)) # (\inst1|LessThan3~10_combout\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111111110000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datac => \player_sum~combout\(5), + datad => \inst1|LessThan3~10_combout\, + combout => \inst1|p_win~3_combout\); + +-- Location: LCCOMB_X2_Y7_N10 +\inst1|p_win~4\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|p_win~4_combout\ = (!\inst1|p_win~0_combout\ & (!\inst|sum_out\(5) & !\inst1|LessThan2~10_combout\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000000101", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst1|p_win~0_combout\, + datac => \inst|sum_out\(5), + datad => \inst1|LessThan2~10_combout\, + combout => \inst1|p_win~4_combout\); + +-- Location: LCCOMB_X2_Y7_N0 +\inst1|p_win~5\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|p_win~5_combout\ = (\inst1|p_win~2_combout\) # ((\inst1|Equal0~2_combout\) # ((\inst1|p_win~3_combout\) # (!\inst1|p_win~4_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111011111111", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst1|p_win~2_combout\, + datab => \inst1|Equal0~2_combout\, + datac => \inst1|p_win~3_combout\, + datad => \inst1|p_win~4_combout\, + combout => \inst1|p_win~5_combout\); + +-- Location: LCCOMB_X2_Y7_N20 +\inst1|p_win~7\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|p_win~7_combout\ = (\inst1|p_win~5_combout\ & (((!\inst1|p_win~6_combout\ & \inst1|p_win~1_combout\)))) # (!\inst1|p_win~5_combout\ & (\inst1|dealer:p_win~regout\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011000010101010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst1|dealer:p_win~regout\, + datab => \inst1|p_win~6_combout\, + datac => \inst1|p_win~1_combout\, + datad => \inst1|p_win~5_combout\, + combout => \inst1|p_win~7_combout\); + +-- Location: LCFF_X2_Y7_N17 +\inst1|player_wins\ : cycloneii_lcell_ff +PORT MAP ( + clk => \clk~clkctrl_outclk\, + sdata => \inst1|p_win~7_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \inst1|player_wins~regout\); + +-- Location: LCFF_X2_Y7_N5 +\inst1|dealer:d_win\ : cycloneii_lcell_ff +PORT MAP ( + clk => \clk~clkctrl_outclk\, + datain => \inst1|d_win~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \inst1|dealer:d_win~regout\); + +-- Location: LCCOMB_X2_Y7_N4 +\inst1|d_win~0\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|d_win~0_combout\ = (\inst1|p_win~5_combout\ & ((\inst1|p_win~4_combout\) # ((\inst1|p_win~6_combout\)))) # (!\inst1|p_win~5_combout\ & (((\inst1|dealer:d_win~regout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1110111011110000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst1|p_win~4_combout\, + datab => \inst1|p_win~6_combout\, + datac => \inst1|dealer:d_win~regout\, + datad => \inst1|p_win~5_combout\, + combout => \inst1|d_win~0_combout\); + +-- Location: LCFF_X2_Y7_N31 +\inst1|dealer_wins\ : cycloneii_lcell_ff +PORT MAP ( + clk => \clk~clkctrl_outclk\, + sdata => \inst1|d_win~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \inst1|dealer_wins~regout\); + +-- Location: LCCOMB_X2_Y7_N2 +\inst1|led_display1~6\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|led_display1~6_combout\ = (\inst1|p_win~2_combout\) # ((\player_sum~combout\(5)) # ((!\inst1|p_win~1_combout\) # (!\inst1|p_win~4_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1110111111111111", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst1|p_win~2_combout\, + datab => \player_sum~combout\(5), + datac => \inst1|p_win~4_combout\, + datad => \inst1|p_win~1_combout\, + combout => \inst1|led_display1~6_combout\); + +-- Location: LCCOMB_X2_Y7_N12 +\inst1|led_display1~4\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|led_display1~4_combout\ = (\inst1|p_win~5_combout\ & (((\inst1|led_display1~6_combout\)))) # (!\inst1|p_win~5_combout\ & (((!\inst1|dealer:d_win~regout\)) # (!\inst1|dealer:p_win~regout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1101111100010011", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst1|dealer:p_win~regout\, + datab => \inst1|p_win~5_combout\, + datac => \inst1|dealer:d_win~regout\, + datad => \inst1|led_display1~6_combout\, + combout => \inst1|led_display1~4_combout\); + +-- Location: LCFF_X2_Y7_N27 +\inst1|dealer:p_win\ : cycloneii_lcell_ff +PORT MAP ( + clk => \clk~clkctrl_outclk\, + sdata => \inst1|p_win~7_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \inst1|dealer:p_win~regout\); + +-- Location: LCCOMB_X2_Y7_N28 +\inst1|led_display1[0]~7\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|led_display1[0]~7_combout\ = (\inst1|p_win~2_combout\) # ((\player_sum~combout\(5)) # ((\inst1|p_win~1_combout\) # (\inst1|p_win~4_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111111111110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst1|p_win~2_combout\, + datab => \player_sum~combout\(5), + datac => \inst1|p_win~1_combout\, + datad => \inst1|p_win~4_combout\, + combout => \inst1|led_display1[0]~7_combout\); + +-- Location: LCCOMB_X2_Y7_N26 +\inst1|led_display1[0]~5\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|led_display1[0]~5_combout\ = (\inst1|p_win~5_combout\ & (((\inst1|led_display1[0]~7_combout\)))) # (!\inst1|p_win~5_combout\ & ((\inst1|dealer:d_win~regout\) # ((\inst1|dealer:p_win~regout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111000110010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst1|dealer:d_win~regout\, + datab => \inst1|p_win~5_combout\, + datac => \inst1|dealer:p_win~regout\, + datad => \inst1|led_display1[0]~7_combout\, + combout => \inst1|led_display1[0]~5_combout\); + +-- Location: LCFF_X2_Y7_N13 +\inst1|led_display1[0]\ : cycloneii_lcell_ff +PORT MAP ( + clk => \clk~clkctrl_outclk\, + datain => \inst1|led_display1~4_combout\, + ena => \inst1|led_display1[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \inst1|led_display1\(0)); + +-- Location: LCCOMB_X2_Y7_N18 +\inst1|led_display3~3\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|led_display3~3_combout\ = (\inst1|p_win~2_combout\) # ((\player_sum~combout\(5)) # ((\inst1|p_win~4_combout\) # (!\inst1|p_win~1_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111011111111", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst1|p_win~2_combout\, + datab => \player_sum~combout\(5), + datac => \inst1|p_win~4_combout\, + datad => \inst1|p_win~1_combout\, + combout => \inst1|led_display3~3_combout\); + +-- Location: LCCOMB_X2_Y7_N22 +\inst1|led_display3~2\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|led_display3~2_combout\ = (\inst1|p_win~5_combout\ & (((\inst1|led_display3~3_combout\)))) # (!\inst1|p_win~5_combout\ & (((\inst1|dealer:d_win~regout\)) # (!\inst1|dealer:p_win~regout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111110100110001", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst1|dealer:p_win~regout\, + datab => \inst1|p_win~5_combout\, + datac => \inst1|dealer:d_win~regout\, + datad => \inst1|led_display3~3_combout\, + combout => \inst1|led_display3~2_combout\); + +-- Location: LCFF_X2_Y7_N23 +\inst1|led_display3[1]\ : cycloneii_lcell_ff +PORT MAP ( + clk => \clk~clkctrl_outclk\, + datain => \inst1|led_display3~2_combout\, + ena => \inst1|led_display1[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \inst1|led_display3\(1)); + +-- Location: LCFF_X2_Y7_N21 +\inst1|led_display4[3]\ : cycloneii_lcell_ff +PORT MAP ( + clk => \clk~clkctrl_outclk\, + datain => \inst1|p_win~7_combout\, + ena => \inst1|led_display1[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \inst1|led_display4\(3)); + +-- Location: PIN_T2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\hit~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst|hit~regout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_hit); + +-- Location: PIN_R1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\done~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst|done~regout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_done); + +-- Location: PIN_Y4, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\player_wins~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst1|player_wins~regout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_player_wins); + +-- Location: PIN_T6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\dealer_wins~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst1|dealer_wins~regout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_dealer_wins); + +-- Location: PIN_N2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display1[6]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst1|led_display1\(0), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display1(6)); + +-- Location: PIN_C14, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display1[5]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => GND, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display1(5)); + +-- Location: PIN_B19, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display1[4]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => GND, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display1(4)); + +-- Location: PIN_P1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display1[3]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst1|ALT_INV_led_display1\(0), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display1(3)); + +-- Location: PIN_AA4, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display1[2]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst1|led_display3\(1), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display1(2)); + +-- Location: PIN_M5, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display1[1]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst1|led_display1\(0), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display1(1)); + +-- Location: PIN_N6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display1[0]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst1|led_display1\(0), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display1(0)); + +-- Location: PIN_AA13, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display2[6]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display2(6)); + +-- Location: PIN_AB4, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display2[5]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst1|ALT_INV_led_display3\(1), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display2(5)); + +-- Location: PIN_A18, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display2[4]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => GND, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display2(4)); + +-- Location: PIN_C7, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display2[3]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => GND, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display2(3)); + +-- Location: PIN_AA6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display2[2]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => GND, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display2(2)); + +-- Location: PIN_A5, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display2[1]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => GND, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display2(1)); + +-- Location: PIN_P6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display2[0]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst1|led_display4\(3), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display2(0)); + +-- Location: PIN_W3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display3[6]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst1|ALT_INV_led_display3\(1), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display3(6)); + +-- Location: PIN_Y3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display3[5]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst1|ALT_INV_led_display3\(1), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display3(5)); + +-- Location: PIN_B6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display3[4]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display3(4)); + +-- Location: PIN_W4, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display3[3]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst1|ALT_INV_led_display3\(1), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display3(3)); + +-- Location: PIN_F11, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display3[2]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => GND, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display3(2)); + +-- Location: PIN_AA3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display3[1]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst1|led_display3\(1), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display3(1)); + +-- Location: PIN_AB3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display3[0]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst1|ALT_INV_led_display3\(1), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display3(0)); + +-- Location: PIN_W5, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display4[6]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst1|ALT_INV_led_display3\(1), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display4(6)); + +-- Location: PIN_V8, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display4[5]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => GND, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display4(5)); + +-- Location: PIN_A19, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display4[4]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => GND, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display4(4)); + +-- Location: PIN_N3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display4[3]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst1|led_display4\(3), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display4(3)); + +-- Location: PIN_P3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display4[2]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst1|ALT_INV_led_display4\(3), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display4(2)); + +-- Location: PIN_N4, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display4[1]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst1|ALT_INV_led_display4\(3), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display4(1)); + +-- Location: PIN_M6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display4[0]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst1|ALT_INV_led_display1\(0), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display4(0)); + +-- Location: PIN_R5, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\sum_out[5]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst|sum_out\(5), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_sum_out(5)); + +-- Location: PIN_U2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\sum_out[4]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst|sum_out\(4), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_sum_out(4)); + +-- Location: PIN_W2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\sum_out[3]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst|sum_out\(3), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_sum_out(3)); + +-- Location: PIN_P2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\sum_out[2]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst|sum_out\(2), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_sum_out(2)); + +-- Location: PIN_V1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\sum_out[1]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst|sum_out\(1), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_sum_out(1)); + +-- Location: PIN_T5, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\sum_out[0]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst|sum_out\(0), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_sum_out(0)); +END structure; + + diff --git a/lab5/simulation/modelsim/gA6_lab5.vo b/lab5/simulation/modelsim/gA6_lab5.vo new file mode 100644 index 0000000..078ddf0 --- /dev/null +++ b/lab5/simulation/modelsim/gA6_lab5.vo @@ -0,0 +1,3064 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus II 64-Bit" +// VERSION "Version 13.0.0 Build 156 04/24/2013 SJ Web Edition" + +// DATE "11/29/2017 18:55:05" + +// +// Device: Altera EP2C20F484C7 Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim-Altera (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module gA6_lab5 ( + hit, + clk, + rst, + turn, + sum, + done, + player_wins, + player_sum, + dealer_wins, + led_display1, + led_display2, + led_display3, + led_display4, + state_out, + sum_out); +output hit; +input clk; +input rst; +input turn; +input [5:0] sum; +output done; +output player_wins; +input [5:0] player_sum; +output dealer_wins; +output [6:0] led_display1; +output [6:0] led_display2; +output [6:0] led_display3; +output [6:0] led_display4; +output [1:0] state_out; +output [5:0] sum_out; + +// Design Ports Information +// hit => Location: PIN_W7, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// done => Location: PIN_V9, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// player_wins => Location: PIN_W4, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// dealer_wins => Location: PIN_W3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display1[6] => Location: PIN_R6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display1[5] => Location: PIN_B17, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display1[4] => Location: PIN_T15, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display1[3] => Location: PIN_T3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display1[2] => Location: PIN_Y2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display1[1] => Location: PIN_U2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display1[0] => Location: PIN_R5, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display2[6] => Location: PIN_B14, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display2[5] => Location: PIN_T5, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display2[4] => Location: PIN_W9, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display2[3] => Location: PIN_H15, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display2[2] => Location: PIN_B11, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display2[1] => Location: PIN_AA16, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display2[0] => Location: PIN_AB7, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display3[6] => Location: PIN_T6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display3[5] => Location: PIN_U3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display3[4] => Location: PIN_C7, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display3[3] => Location: PIN_W1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display3[2] => Location: PIN_C21, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display3[1] => Location: PIN_Y1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display3[0] => Location: PIN_V2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display4[6] => Location: PIN_W2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display4[5] => Location: PIN_G8, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display4[4] => Location: PIN_D2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display4[3] => Location: PIN_P9, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display4[2] => Location: PIN_P8, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display4[1] => Location: PIN_AA7, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display4[0] => Location: PIN_U1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// state_out[1] => Location: PIN_V8, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// state_out[0] => Location: PIN_AB6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// sum_out[5] => Location: PIN_U4, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// sum_out[4] => Location: PIN_W5, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// sum_out[3] => Location: PIN_AA4, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// sum_out[2] => Location: PIN_T8, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// sum_out[1] => Location: PIN_T7, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// sum_out[0] => Location: PIN_AB4, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// sum[5] => Location: PIN_U8, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// sum[4] => Location: PIN_Y6, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// sum[3] => Location: PIN_Y5, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// sum[2] => Location: PIN_AB5, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// sum[1] => Location: PIN_Y3, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// sum[0] => Location: PIN_AA5, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// clk => Location: PIN_M1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// rst => Location: PIN_M2, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// player_sum[5] => Location: PIN_AB3, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// player_sum[4] => Location: PIN_V4, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// player_sum[3] => Location: PIN_Y7, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// player_sum[2] => Location: PIN_AA3, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// player_sum[1] => Location: PIN_AA6, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// player_sum[0] => Location: PIN_Y4, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// turn => Location: PIN_W8, I/O Standard: 3.3-V LVTTL, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +wire \turn~combout ; +wire \clk~combout ; +wire \clk~clkctrl_outclk ; +wire \inst|LessThan0~0_combout ; +wire \inst|LessThan0~1_combout ; +wire \inst|computer:state[0]~0_combout ; +wire \rst~combout ; +wire \rst~clkctrl_outclk ; +wire \inst|computer:state[0]~regout ; +wire \inst|computer:state[1]~0_combout ; +wire \inst|computer:state[1]~regout ; +wire \inst|Mux0~0_combout ; +wire \inst|hit~regout ; +wire \inst|Mux1~0_combout ; +wire \inst|done~regout ; +wire \inst1|p_win~2_combout ; +wire \inst1|p_win~6_combout ; +wire \inst1|dealer:p_win~regout ; +wire \inst1|Equal0~1_combout ; +wire \inst1|Equal0~0_combout ; +wire \inst1|Equal0~2_combout ; +wire \inst1|LessThan3~1_cout ; +wire \inst1|LessThan3~3_cout ; +wire \inst1|LessThan3~5_cout ; +wire \inst1|LessThan3~7_cout ; +wire \inst1|LessThan3~9_cout ; +wire \inst1|LessThan3~10_combout ; +wire \inst1|p_win~3_combout ; +wire \inst1|LessThan2~1_cout ; +wire \inst1|LessThan2~3_cout ; +wire \inst1|LessThan2~5_cout ; +wire \inst1|LessThan2~7_cout ; +wire \inst1|LessThan2~9_cout ; +wire \inst1|LessThan2~10_combout ; +wire \inst1|p_win~0_combout ; +wire \inst1|p_win~4_combout ; +wire \inst1|p_win~5_combout ; +wire \inst1|p_win~7_combout ; +wire \inst1|player_wins~feeder_combout ; +wire \inst1|player_wins~regout ; +wire \inst1|d_win~0_combout ; +wire \inst1|dealer_wins~regout ; +wire \inst1|p_win~1_combout ; +wire \inst1|led_display1~6_combout ; +wire \inst1|led_display1~4_combout ; +wire \inst1|dealer:d_win~regout ; +wire \inst1|led_display1[0]~7_combout ; +wire \inst1|led_display1[0]~5_combout ; +wire \inst1|led_display3~3_combout ; +wire \inst1|led_display3~2_combout ; +wire \inst1|led_display4[3]~feeder_combout ; +wire [5:0] \sum~combout ; +wire [5:0] \inst|sum_out ; +wire [6:0] \inst1|led_display3 ; +wire [6:0] \inst1|led_display4 ; +wire [5:0] \player_sum~combout ; +wire [6:0] \inst1|led_display1 ; + + +// Location: PIN_V4, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \player_sum[4]~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\player_sum~combout [4]), + .regout(), + .differentialout(), + .linkout(), + .padio(player_sum[4])); +// synopsys translate_off +defparam \player_sum[4]~I .input_async_reset = "none"; +defparam \player_sum[4]~I .input_power_up = "low"; +defparam \player_sum[4]~I .input_register_mode = "none"; +defparam \player_sum[4]~I .input_sync_reset = "none"; +defparam \player_sum[4]~I .oe_async_reset = "none"; +defparam \player_sum[4]~I .oe_power_up = "low"; +defparam \player_sum[4]~I .oe_register_mode = "none"; +defparam \player_sum[4]~I .oe_sync_reset = "none"; +defparam \player_sum[4]~I .operation_mode = "input"; +defparam \player_sum[4]~I .output_async_reset = "none"; +defparam \player_sum[4]~I .output_power_up = "low"; +defparam \player_sum[4]~I .output_register_mode = "none"; +defparam \player_sum[4]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_W8, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \turn~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\turn~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(turn)); +// synopsys translate_off +defparam \turn~I .input_async_reset = "none"; +defparam \turn~I .input_power_up = "low"; +defparam \turn~I .input_register_mode = "none"; +defparam \turn~I .input_sync_reset = "none"; +defparam \turn~I .oe_async_reset = "none"; +defparam \turn~I .oe_power_up = "low"; +defparam \turn~I .oe_register_mode = "none"; +defparam \turn~I .oe_sync_reset = "none"; +defparam \turn~I .operation_mode = "input"; +defparam \turn~I .output_async_reset = "none"; +defparam \turn~I .output_power_up = "low"; +defparam \turn~I .output_register_mode = "none"; +defparam \turn~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_M1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \clk~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\clk~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(clk)); +// synopsys translate_off +defparam \clk~I .input_async_reset = "none"; +defparam \clk~I .input_power_up = "low"; +defparam \clk~I .input_register_mode = "none"; +defparam \clk~I .input_sync_reset = "none"; +defparam \clk~I .oe_async_reset = "none"; +defparam \clk~I .oe_power_up = "low"; +defparam \clk~I .oe_register_mode = "none"; +defparam \clk~I .oe_sync_reset = "none"; +defparam \clk~I .operation_mode = "input"; +defparam \clk~I .output_async_reset = "none"; +defparam \clk~I .output_power_up = "low"; +defparam \clk~I .output_register_mode = "none"; +defparam \clk~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: CLKCTRL_G3 +cycloneii_clkctrl \clk~clkctrl ( + .ena(vcc), + .inclk({gnd,gnd,gnd,\clk~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk~clkctrl_outclk )); +// synopsys translate_off +defparam \clk~clkctrl .clock_type = "global clock"; +defparam \clk~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: PIN_AA5, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \sum[0]~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\sum~combout [0]), + .regout(), + .differentialout(), + .linkout(), + .padio(sum[0])); +// synopsys translate_off +defparam \sum[0]~I .input_async_reset = "none"; +defparam \sum[0]~I .input_power_up = "low"; +defparam \sum[0]~I .input_register_mode = "none"; +defparam \sum[0]~I .input_sync_reset = "none"; +defparam \sum[0]~I .oe_async_reset = "none"; +defparam \sum[0]~I .oe_power_up = "low"; +defparam \sum[0]~I .oe_register_mode = "none"; +defparam \sum[0]~I .oe_sync_reset = "none"; +defparam \sum[0]~I .operation_mode = "input"; +defparam \sum[0]~I .output_async_reset = "none"; +defparam \sum[0]~I .output_power_up = "low"; +defparam \sum[0]~I .output_register_mode = "none"; +defparam \sum[0]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_Y3, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \sum[1]~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\sum~combout [1]), + .regout(), + .differentialout(), + .linkout(), + .padio(sum[1])); +// synopsys translate_off +defparam \sum[1]~I .input_async_reset = "none"; +defparam \sum[1]~I .input_power_up = "low"; +defparam \sum[1]~I .input_register_mode = "none"; +defparam \sum[1]~I .input_sync_reset = "none"; +defparam \sum[1]~I .oe_async_reset = "none"; +defparam \sum[1]~I .oe_power_up = "low"; +defparam \sum[1]~I .oe_register_mode = "none"; +defparam \sum[1]~I .oe_sync_reset = "none"; +defparam \sum[1]~I .operation_mode = "input"; +defparam \sum[1]~I .output_async_reset = "none"; +defparam \sum[1]~I .output_power_up = "low"; +defparam \sum[1]~I .output_register_mode = "none"; +defparam \sum[1]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_Y5, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \sum[3]~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\sum~combout [3]), + .regout(), + .differentialout(), + .linkout(), + .padio(sum[3])); +// synopsys translate_off +defparam \sum[3]~I .input_async_reset = "none"; +defparam \sum[3]~I .input_power_up = "low"; +defparam \sum[3]~I .input_register_mode = "none"; +defparam \sum[3]~I .input_sync_reset = "none"; +defparam \sum[3]~I .oe_async_reset = "none"; +defparam \sum[3]~I .oe_power_up = "low"; +defparam \sum[3]~I .oe_register_mode = "none"; +defparam \sum[3]~I .oe_sync_reset = "none"; +defparam \sum[3]~I .operation_mode = "input"; +defparam \sum[3]~I .output_async_reset = "none"; +defparam \sum[3]~I .output_power_up = "low"; +defparam \sum[3]~I .output_register_mode = "none"; +defparam \sum[3]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y1_N0 +cycloneii_lcell_comb \inst|LessThan0~0 ( +// Equation(s): +// \inst|LessThan0~0_combout = (\sum~combout [2]) # ((\sum~combout [0]) # ((\sum~combout [1]) # (\sum~combout [3]))) + + .dataa(\sum~combout [2]), + .datab(\sum~combout [0]), + .datac(\sum~combout [1]), + .datad(\sum~combout [3]), + .cin(gnd), + .combout(\inst|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst|LessThan0~0 .lut_mask = 16'hFFFE; +defparam \inst|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: PIN_U8, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \sum[5]~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\sum~combout [5]), + .regout(), + .differentialout(), + .linkout(), + .padio(sum[5])); +// synopsys translate_off +defparam \sum[5]~I .input_async_reset = "none"; +defparam \sum[5]~I .input_power_up = "low"; +defparam \sum[5]~I .input_register_mode = "none"; +defparam \sum[5]~I .input_sync_reset = "none"; +defparam \sum[5]~I .oe_async_reset = "none"; +defparam \sum[5]~I .oe_power_up = "low"; +defparam \sum[5]~I .oe_register_mode = "none"; +defparam \sum[5]~I .oe_sync_reset = "none"; +defparam \sum[5]~I .operation_mode = "input"; +defparam \sum[5]~I .output_async_reset = "none"; +defparam \sum[5]~I .output_power_up = "low"; +defparam \sum[5]~I .output_register_mode = "none"; +defparam \sum[5]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y1_N18 +cycloneii_lcell_comb \inst|LessThan0~1 ( +// Equation(s): +// \inst|LessThan0~1_combout = (\sum~combout [5]) # ((\sum~combout [4] & \inst|LessThan0~0_combout )) + + .dataa(\sum~combout [4]), + .datab(\inst|LessThan0~0_combout ), + .datac(\sum~combout [5]), + .datad(vcc), + .cin(gnd), + .combout(\inst|LessThan0~1_combout ), + .cout()); +// synopsys translate_off +defparam \inst|LessThan0~1 .lut_mask = 16'hF8F8; +defparam \inst|LessThan0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X9_Y1_N22 +cycloneii_lcell_comb \inst|computer:state[0]~0 ( +// Equation(s): +// \inst|computer:state[0]~0_combout = (!\inst|computer:state[1]~regout & ((\inst|computer:state[0]~regout & ((!\inst|LessThan0~1_combout ))) # (!\inst|computer:state[0]~regout & (\turn~combout )))) + + .dataa(\turn~combout ), + .datab(\inst|LessThan0~1_combout ), + .datac(\inst|computer:state[0]~regout ), + .datad(\inst|computer:state[1]~regout ), + .cin(gnd), + .combout(\inst|computer:state[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst|computer:state[0]~0 .lut_mask = 16'h003A; +defparam \inst|computer:state[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: PIN_M2, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \rst~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\rst~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(rst)); +// synopsys translate_off +defparam \rst~I .input_async_reset = "none"; +defparam \rst~I .input_power_up = "low"; +defparam \rst~I .input_register_mode = "none"; +defparam \rst~I .input_sync_reset = "none"; +defparam \rst~I .oe_async_reset = "none"; +defparam \rst~I .oe_power_up = "low"; +defparam \rst~I .oe_register_mode = "none"; +defparam \rst~I .oe_sync_reset = "none"; +defparam \rst~I .operation_mode = "input"; +defparam \rst~I .output_async_reset = "none"; +defparam \rst~I .output_power_up = "low"; +defparam \rst~I .output_register_mode = "none"; +defparam \rst~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: CLKCTRL_G1 +cycloneii_clkctrl \rst~clkctrl ( + .ena(vcc), + .inclk({gnd,gnd,gnd,\rst~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst~clkctrl_outclk )); +// synopsys translate_off +defparam \rst~clkctrl .clock_type = "global clock"; +defparam \rst~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCFF_X9_Y1_N23 +cycloneii_lcell_ff \inst|computer:state[0] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst|computer:state[0]~0_combout ), + .sdata(gnd), + .aclr(\rst~clkctrl_outclk ), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst|computer:state[0]~regout )); + +// Location: LCCOMB_X9_Y1_N28 +cycloneii_lcell_comb \inst|computer:state[1]~0 ( +// Equation(s): +// \inst|computer:state[1]~0_combout = (\inst|LessThan0~1_combout & (!\inst|computer:state[1]~regout & \inst|computer:state[0]~regout )) + + .dataa(vcc), + .datab(\inst|LessThan0~1_combout ), + .datac(\inst|computer:state[1]~regout ), + .datad(\inst|computer:state[0]~regout ), + .cin(gnd), + .combout(\inst|computer:state[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst|computer:state[1]~0 .lut_mask = 16'h0C00; +defparam \inst|computer:state[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X9_Y1_N29 +cycloneii_lcell_ff \inst|computer:state[1] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst|computer:state[1]~0_combout ), + .sdata(gnd), + .aclr(\rst~clkctrl_outclk ), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst|computer:state[1]~regout )); + +// Location: LCCOMB_X9_Y1_N16 +cycloneii_lcell_comb \inst|Mux0~0 ( +// Equation(s): +// \inst|Mux0~0_combout = (!\inst|LessThan0~1_combout & (!\inst|computer:state[1]~regout & \inst|computer:state[0]~regout )) + + .dataa(vcc), + .datab(\inst|LessThan0~1_combout ), + .datac(\inst|computer:state[1]~regout ), + .datad(\inst|computer:state[0]~regout ), + .cin(gnd), + .combout(\inst|Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst|Mux0~0 .lut_mask = 16'h0300; +defparam \inst|Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X9_Y1_N17 +cycloneii_lcell_ff \inst|hit ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst|Mux0~0_combout ), + .sdata(gnd), + .aclr(\rst~clkctrl_outclk ), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst|hit~regout )); + +// Location: LCCOMB_X9_Y1_N18 +cycloneii_lcell_comb \inst|Mux1~0 ( +// Equation(s): +// \inst|Mux1~0_combout = (!\inst|computer:state[0]~regout & \inst|computer:state[1]~regout ) + + .dataa(vcc), + .datab(\inst|computer:state[0]~regout ), + .datac(vcc), + .datad(\inst|computer:state[1]~regout ), + .cin(gnd), + .combout(\inst|Mux1~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst|Mux1~0 .lut_mask = 16'h3300; +defparam \inst|Mux1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X9_Y1_N19 +cycloneii_lcell_ff \inst|done ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst|Mux1~0_combout ), + .sdata(gnd), + .aclr(\rst~clkctrl_outclk ), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst|done~regout )); + +// Location: PIN_AB3, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \player_sum[5]~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\player_sum~combout [5]), + .regout(), + .differentialout(), + .linkout(), + .padio(player_sum[5])); +// synopsys translate_off +defparam \player_sum[5]~I .input_async_reset = "none"; +defparam \player_sum[5]~I .input_power_up = "low"; +defparam \player_sum[5]~I .input_register_mode = "none"; +defparam \player_sum[5]~I .input_sync_reset = "none"; +defparam \player_sum[5]~I .oe_async_reset = "none"; +defparam \player_sum[5]~I .oe_power_up = "low"; +defparam \player_sum[5]~I .oe_register_mode = "none"; +defparam \player_sum[5]~I .oe_sync_reset = "none"; +defparam \player_sum[5]~I .operation_mode = "input"; +defparam \player_sum[5]~I .output_async_reset = "none"; +defparam \player_sum[5]~I .output_power_up = "low"; +defparam \player_sum[5]~I .output_register_mode = "none"; +defparam \player_sum[5]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_AA3, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \player_sum[2]~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\player_sum~combout [2]), + .regout(), + .differentialout(), + .linkout(), + .padio(player_sum[2])); +// synopsys translate_off +defparam \player_sum[2]~I .input_async_reset = "none"; +defparam \player_sum[2]~I .input_power_up = "low"; +defparam \player_sum[2]~I .input_register_mode = "none"; +defparam \player_sum[2]~I .input_sync_reset = "none"; +defparam \player_sum[2]~I .oe_async_reset = "none"; +defparam \player_sum[2]~I .oe_power_up = "low"; +defparam \player_sum[2]~I .oe_register_mode = "none"; +defparam \player_sum[2]~I .oe_sync_reset = "none"; +defparam \player_sum[2]~I .operation_mode = "input"; +defparam \player_sum[2]~I .output_async_reset = "none"; +defparam \player_sum[2]~I .output_power_up = "low"; +defparam \player_sum[2]~I .output_register_mode = "none"; +defparam \player_sum[2]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_Y7, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \player_sum[3]~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\player_sum~combout [3]), + .regout(), + .differentialout(), + .linkout(), + .padio(player_sum[3])); +// synopsys translate_off +defparam \player_sum[3]~I .input_async_reset = "none"; +defparam \player_sum[3]~I .input_power_up = "low"; +defparam \player_sum[3]~I .input_register_mode = "none"; +defparam \player_sum[3]~I .input_sync_reset = "none"; +defparam \player_sum[3]~I .oe_async_reset = "none"; +defparam \player_sum[3]~I .oe_power_up = "low"; +defparam \player_sum[3]~I .oe_register_mode = "none"; +defparam \player_sum[3]~I .oe_sync_reset = "none"; +defparam \player_sum[3]~I .operation_mode = "input"; +defparam \player_sum[3]~I .output_async_reset = "none"; +defparam \player_sum[3]~I .output_power_up = "low"; +defparam \player_sum[3]~I .output_register_mode = "none"; +defparam \player_sum[3]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_AA6, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \player_sum[1]~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\player_sum~combout [1]), + .regout(), + .differentialout(), + .linkout(), + .padio(player_sum[1])); +// synopsys translate_off +defparam \player_sum[1]~I .input_async_reset = "none"; +defparam \player_sum[1]~I .input_power_up = "low"; +defparam \player_sum[1]~I .input_register_mode = "none"; +defparam \player_sum[1]~I .input_sync_reset = "none"; +defparam \player_sum[1]~I .oe_async_reset = "none"; +defparam \player_sum[1]~I .oe_power_up = "low"; +defparam \player_sum[1]~I .oe_register_mode = "none"; +defparam \player_sum[1]~I .oe_sync_reset = "none"; +defparam \player_sum[1]~I .operation_mode = "input"; +defparam \player_sum[1]~I .output_async_reset = "none"; +defparam \player_sum[1]~I .output_power_up = "low"; +defparam \player_sum[1]~I .output_register_mode = "none"; +defparam \player_sum[1]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y1_N14 +cycloneii_lcell_comb \inst1|p_win~2 ( +// Equation(s): +// \inst1|p_win~2_combout = (\player_sum~combout [4] & ((\player_sum~combout [3]) # ((\player_sum~combout [2] & \player_sum~combout [1])))) + + .dataa(\player_sum~combout [4]), + .datab(\player_sum~combout [2]), + .datac(\player_sum~combout [3]), + .datad(\player_sum~combout [1]), + .cin(gnd), + .combout(\inst1|p_win~2_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|p_win~2 .lut_mask = 16'hA8A0; +defparam \inst1|p_win~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y1_N2 +cycloneii_lcell_comb \inst1|p_win~6 ( +// Equation(s): +// \inst1|p_win~6_combout = (\player_sum~combout [5]) # (\inst1|p_win~2_combout ) + + .dataa(vcc), + .datab(vcc), + .datac(\player_sum~combout [5]), + .datad(\inst1|p_win~2_combout ), + .cin(gnd), + .combout(\inst1|p_win~6_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|p_win~6 .lut_mask = 16'hFFF0; +defparam \inst1|p_win~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X1_Y1_N7 +cycloneii_lcell_ff \inst1|dealer:p_win ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst1|p_win~7_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst1|dealer:p_win~regout )); + +// Location: PIN_Y6, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \sum[4]~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\sum~combout [4]), + .regout(), + .differentialout(), + .linkout(), + .padio(sum[4])); +// synopsys translate_off +defparam \sum[4]~I .input_async_reset = "none"; +defparam \sum[4]~I .input_power_up = "low"; +defparam \sum[4]~I .input_register_mode = "none"; +defparam \sum[4]~I .input_sync_reset = "none"; +defparam \sum[4]~I .oe_async_reset = "none"; +defparam \sum[4]~I .oe_power_up = "low"; +defparam \sum[4]~I .oe_register_mode = "none"; +defparam \sum[4]~I .oe_sync_reset = "none"; +defparam \sum[4]~I .operation_mode = "input"; +defparam \sum[4]~I .output_async_reset = "none"; +defparam \sum[4]~I .output_power_up = "low"; +defparam \sum[4]~I .output_register_mode = "none"; +defparam \sum[4]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: LCFF_X2_Y1_N9 +cycloneii_lcell_ff \inst|sum_out[4] ( + .clk(\clk~clkctrl_outclk ), + .datain(gnd), + .sdata(\sum~combout [4]), + .aclr(\rst~clkctrl_outclk ), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst|sum_out [4])); + +// Location: PIN_AB5, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \sum[2]~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\sum~combout [2]), + .regout(), + .differentialout(), + .linkout(), + .padio(sum[2])); +// synopsys translate_off +defparam \sum[2]~I .input_async_reset = "none"; +defparam \sum[2]~I .input_power_up = "low"; +defparam \sum[2]~I .input_register_mode = "none"; +defparam \sum[2]~I .input_sync_reset = "none"; +defparam \sum[2]~I .oe_async_reset = "none"; +defparam \sum[2]~I .oe_power_up = "low"; +defparam \sum[2]~I .oe_register_mode = "none"; +defparam \sum[2]~I .oe_sync_reset = "none"; +defparam \sum[2]~I .operation_mode = "input"; +defparam \sum[2]~I .output_async_reset = "none"; +defparam \sum[2]~I .output_power_up = "low"; +defparam \sum[2]~I .output_register_mode = "none"; +defparam \sum[2]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: LCFF_X2_Y1_N13 +cycloneii_lcell_ff \inst|sum_out[2] ( + .clk(\clk~clkctrl_outclk ), + .datain(gnd), + .sdata(\sum~combout [2]), + .aclr(\rst~clkctrl_outclk ), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst|sum_out [2])); + +// Location: LCFF_X2_Y1_N7 +cycloneii_lcell_ff \inst|sum_out[3] ( + .clk(\clk~clkctrl_outclk ), + .datain(gnd), + .sdata(\sum~combout [3]), + .aclr(\rst~clkctrl_outclk ), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst|sum_out [3])); + +// Location: LCCOMB_X2_Y1_N12 +cycloneii_lcell_comb \inst1|Equal0~1 ( +// Equation(s): +// \inst1|Equal0~1_combout = (\player_sum~combout [3] & (\inst|sum_out [3] & (\player_sum~combout [2] $ (!\inst|sum_out [2])))) # (!\player_sum~combout [3] & (!\inst|sum_out [3] & (\player_sum~combout [2] $ (!\inst|sum_out [2])))) + + .dataa(\player_sum~combout [3]), + .datab(\player_sum~combout [2]), + .datac(\inst|sum_out [2]), + .datad(\inst|sum_out [3]), + .cin(gnd), + .combout(\inst1|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|Equal0~1 .lut_mask = 16'h8241; +defparam \inst1|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: PIN_Y4, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \player_sum[0]~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\player_sum~combout [0]), + .regout(), + .differentialout(), + .linkout(), + .padio(player_sum[0])); +// synopsys translate_off +defparam \player_sum[0]~I .input_async_reset = "none"; +defparam \player_sum[0]~I .input_power_up = "low"; +defparam \player_sum[0]~I .input_register_mode = "none"; +defparam \player_sum[0]~I .input_sync_reset = "none"; +defparam \player_sum[0]~I .oe_async_reset = "none"; +defparam \player_sum[0]~I .oe_power_up = "low"; +defparam \player_sum[0]~I .oe_register_mode = "none"; +defparam \player_sum[0]~I .oe_sync_reset = "none"; +defparam \player_sum[0]~I .operation_mode = "input"; +defparam \player_sum[0]~I .output_async_reset = "none"; +defparam \player_sum[0]~I .output_power_up = "low"; +defparam \player_sum[0]~I .output_register_mode = "none"; +defparam \player_sum[0]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: LCFF_X2_Y1_N29 +cycloneii_lcell_ff \inst|sum_out[0] ( + .clk(\clk~clkctrl_outclk ), + .datain(gnd), + .sdata(\sum~combout [0]), + .aclr(\rst~clkctrl_outclk ), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst|sum_out [0])); + +// Location: LCFF_X2_Y1_N31 +cycloneii_lcell_ff \inst|sum_out[1] ( + .clk(\clk~clkctrl_outclk ), + .datain(gnd), + .sdata(\sum~combout [1]), + .aclr(\rst~clkctrl_outclk ), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst|sum_out [1])); + +// Location: LCCOMB_X2_Y1_N28 +cycloneii_lcell_comb \inst1|Equal0~0 ( +// Equation(s): +// \inst1|Equal0~0_combout = (\player_sum~combout [1] & (\inst|sum_out [1] & (\player_sum~combout [0] $ (!\inst|sum_out [0])))) # (!\player_sum~combout [1] & (!\inst|sum_out [1] & (\player_sum~combout [0] $ (!\inst|sum_out [0])))) + + .dataa(\player_sum~combout [1]), + .datab(\player_sum~combout [0]), + .datac(\inst|sum_out [0]), + .datad(\inst|sum_out [1]), + .cin(gnd), + .combout(\inst1|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|Equal0~0 .lut_mask = 16'h8241; +defparam \inst1|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y1_N18 +cycloneii_lcell_comb \inst1|Equal0~2 ( +// Equation(s): +// \inst1|Equal0~2_combout = (\inst1|Equal0~1_combout & (\inst1|Equal0~0_combout & (\player_sum~combout [4] $ (!\inst|sum_out [4])))) + + .dataa(\player_sum~combout [4]), + .datab(\inst|sum_out [4]), + .datac(\inst1|Equal0~1_combout ), + .datad(\inst1|Equal0~0_combout ), + .cin(gnd), + .combout(\inst1|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|Equal0~2 .lut_mask = 16'h9000; +defparam \inst1|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X2_Y1_N11 +cycloneii_lcell_ff \inst|sum_out[5] ( + .clk(\clk~clkctrl_outclk ), + .datain(gnd), + .sdata(\sum~combout [5]), + .aclr(\rst~clkctrl_outclk ), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst|sum_out [5])); + +// Location: LCCOMB_X2_Y1_N16 +cycloneii_lcell_comb \inst1|LessThan3~1 ( +// Equation(s): +// \inst1|LessThan3~1_cout = CARRY((!\player_sum~combout [0] & \inst|sum_out [0])) + + .dataa(\player_sum~combout [0]), + .datab(\inst|sum_out [0]), + .datac(vcc), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\inst1|LessThan3~1_cout )); +// synopsys translate_off +defparam \inst1|LessThan3~1 .lut_mask = 16'h0044; +defparam \inst1|LessThan3~1 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y1_N18 +cycloneii_lcell_comb \inst1|LessThan3~3 ( +// Equation(s): +// \inst1|LessThan3~3_cout = CARRY((\player_sum~combout [1] & ((!\inst1|LessThan3~1_cout ) # (!\inst|sum_out [1]))) # (!\player_sum~combout [1] & (!\inst|sum_out [1] & !\inst1|LessThan3~1_cout ))) + + .dataa(\player_sum~combout [1]), + .datab(\inst|sum_out [1]), + .datac(vcc), + .datad(vcc), + .cin(\inst1|LessThan3~1_cout ), + .combout(), + .cout(\inst1|LessThan3~3_cout )); +// synopsys translate_off +defparam \inst1|LessThan3~3 .lut_mask = 16'h002B; +defparam \inst1|LessThan3~3 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y1_N20 +cycloneii_lcell_comb \inst1|LessThan3~5 ( +// Equation(s): +// \inst1|LessThan3~5_cout = CARRY((\inst|sum_out [2] & ((!\inst1|LessThan3~3_cout ) # (!\player_sum~combout [2]))) # (!\inst|sum_out [2] & (!\player_sum~combout [2] & !\inst1|LessThan3~3_cout ))) + + .dataa(\inst|sum_out [2]), + .datab(\player_sum~combout [2]), + .datac(vcc), + .datad(vcc), + .cin(\inst1|LessThan3~3_cout ), + .combout(), + .cout(\inst1|LessThan3~5_cout )); +// synopsys translate_off +defparam \inst1|LessThan3~5 .lut_mask = 16'h002B; +defparam \inst1|LessThan3~5 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y1_N22 +cycloneii_lcell_comb \inst1|LessThan3~7 ( +// Equation(s): +// \inst1|LessThan3~7_cout = CARRY((\inst|sum_out [3] & (\player_sum~combout [3] & !\inst1|LessThan3~5_cout )) # (!\inst|sum_out [3] & ((\player_sum~combout [3]) # (!\inst1|LessThan3~5_cout )))) + + .dataa(\inst|sum_out [3]), + .datab(\player_sum~combout [3]), + .datac(vcc), + .datad(vcc), + .cin(\inst1|LessThan3~5_cout ), + .combout(), + .cout(\inst1|LessThan3~7_cout )); +// synopsys translate_off +defparam \inst1|LessThan3~7 .lut_mask = 16'h004D; +defparam \inst1|LessThan3~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y1_N24 +cycloneii_lcell_comb \inst1|LessThan3~9 ( +// Equation(s): +// \inst1|LessThan3~9_cout = CARRY((\player_sum~combout [4] & (\inst|sum_out [4] & !\inst1|LessThan3~7_cout )) # (!\player_sum~combout [4] & ((\inst|sum_out [4]) # (!\inst1|LessThan3~7_cout )))) + + .dataa(\player_sum~combout [4]), + .datab(\inst|sum_out [4]), + .datac(vcc), + .datad(vcc), + .cin(\inst1|LessThan3~7_cout ), + .combout(), + .cout(\inst1|LessThan3~9_cout )); +// synopsys translate_off +defparam \inst1|LessThan3~9 .lut_mask = 16'h004D; +defparam \inst1|LessThan3~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y1_N26 +cycloneii_lcell_comb \inst1|LessThan3~10 ( +// Equation(s): +// \inst1|LessThan3~10_combout = (\player_sum~combout [5] & (\inst1|LessThan3~9_cout & \inst|sum_out [5])) # (!\player_sum~combout [5] & ((\inst1|LessThan3~9_cout ) # (\inst|sum_out [5]))) + + .dataa(\player_sum~combout [5]), + .datab(vcc), + .datac(vcc), + .datad(\inst|sum_out [5]), + .cin(\inst1|LessThan3~9_cout ), + .combout(\inst1|LessThan3~10_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|LessThan3~10 .lut_mask = 16'hF550; +defparam \inst1|LessThan3~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y1_N20 +cycloneii_lcell_comb \inst1|p_win~3 ( +// Equation(s): +// \inst1|p_win~3_combout = (\player_sum~combout [5]) # (\inst1|LessThan3~10_combout ) + + .dataa(vcc), + .datab(\player_sum~combout [5]), + .datac(\inst1|LessThan3~10_combout ), + .datad(vcc), + .cin(gnd), + .combout(\inst1|p_win~3_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|p_win~3 .lut_mask = 16'hFCFC; +defparam \inst1|p_win~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y1_N0 +cycloneii_lcell_comb \inst1|LessThan2~1 ( +// Equation(s): +// \inst1|LessThan2~1_cout = CARRY((\player_sum~combout [0] & !\inst|sum_out [0])) + + .dataa(\player_sum~combout [0]), + .datab(\inst|sum_out [0]), + .datac(vcc), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\inst1|LessThan2~1_cout )); +// synopsys translate_off +defparam \inst1|LessThan2~1 .lut_mask = 16'h0022; +defparam \inst1|LessThan2~1 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y1_N2 +cycloneii_lcell_comb \inst1|LessThan2~3 ( +// Equation(s): +// \inst1|LessThan2~3_cout = CARRY((\player_sum~combout [1] & (\inst|sum_out [1] & !\inst1|LessThan2~1_cout )) # (!\player_sum~combout [1] & ((\inst|sum_out [1]) # (!\inst1|LessThan2~1_cout )))) + + .dataa(\player_sum~combout [1]), + .datab(\inst|sum_out [1]), + .datac(vcc), + .datad(vcc), + .cin(\inst1|LessThan2~1_cout ), + .combout(), + .cout(\inst1|LessThan2~3_cout )); +// synopsys translate_off +defparam \inst1|LessThan2~3 .lut_mask = 16'h004D; +defparam \inst1|LessThan2~3 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y1_N4 +cycloneii_lcell_comb \inst1|LessThan2~5 ( +// Equation(s): +// \inst1|LessThan2~5_cout = CARRY((\inst|sum_out [2] & (\player_sum~combout [2] & !\inst1|LessThan2~3_cout )) # (!\inst|sum_out [2] & ((\player_sum~combout [2]) # (!\inst1|LessThan2~3_cout )))) + + .dataa(\inst|sum_out [2]), + .datab(\player_sum~combout [2]), + .datac(vcc), + .datad(vcc), + .cin(\inst1|LessThan2~3_cout ), + .combout(), + .cout(\inst1|LessThan2~5_cout )); +// synopsys translate_off +defparam \inst1|LessThan2~5 .lut_mask = 16'h004D; +defparam \inst1|LessThan2~5 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y1_N6 +cycloneii_lcell_comb \inst1|LessThan2~7 ( +// Equation(s): +// \inst1|LessThan2~7_cout = CARRY((\inst|sum_out [3] & ((!\inst1|LessThan2~5_cout ) # (!\player_sum~combout [3]))) # (!\inst|sum_out [3] & (!\player_sum~combout [3] & !\inst1|LessThan2~5_cout ))) + + .dataa(\inst|sum_out [3]), + .datab(\player_sum~combout [3]), + .datac(vcc), + .datad(vcc), + .cin(\inst1|LessThan2~5_cout ), + .combout(), + .cout(\inst1|LessThan2~7_cout )); +// synopsys translate_off +defparam \inst1|LessThan2~7 .lut_mask = 16'h002B; +defparam \inst1|LessThan2~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y1_N8 +cycloneii_lcell_comb \inst1|LessThan2~9 ( +// Equation(s): +// \inst1|LessThan2~9_cout = CARRY((\player_sum~combout [4] & ((!\inst1|LessThan2~7_cout ) # (!\inst|sum_out [4]))) # (!\player_sum~combout [4] & (!\inst|sum_out [4] & !\inst1|LessThan2~7_cout ))) + + .dataa(\player_sum~combout [4]), + .datab(\inst|sum_out [4]), + .datac(vcc), + .datad(vcc), + .cin(\inst1|LessThan2~7_cout ), + .combout(), + .cout(\inst1|LessThan2~9_cout )); +// synopsys translate_off +defparam \inst1|LessThan2~9 .lut_mask = 16'h002B; +defparam \inst1|LessThan2~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y1_N10 +cycloneii_lcell_comb \inst1|LessThan2~10 ( +// Equation(s): +// \inst1|LessThan2~10_combout = (\player_sum~combout [5] & ((\inst1|LessThan2~9_cout ) # (!\inst|sum_out [5]))) # (!\player_sum~combout [5] & (\inst1|LessThan2~9_cout & !\inst|sum_out [5])) + + .dataa(\player_sum~combout [5]), + .datab(vcc), + .datac(vcc), + .datad(\inst|sum_out [5]), + .cin(\inst1|LessThan2~9_cout ), + .combout(\inst1|LessThan2~10_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|LessThan2~10 .lut_mask = 16'hA0FA; +defparam \inst1|LessThan2~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y1_N30 +cycloneii_lcell_comb \inst1|p_win~0 ( +// Equation(s): +// \inst1|p_win~0_combout = (\inst|sum_out [4] & ((\inst|sum_out [3]) # ((\inst|sum_out [2] & \inst|sum_out [1])))) + + .dataa(\inst|sum_out [2]), + .datab(\inst|sum_out [4]), + .datac(\inst|sum_out [1]), + .datad(\inst|sum_out [3]), + .cin(gnd), + .combout(\inst1|p_win~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|p_win~0 .lut_mask = 16'hCC80; +defparam \inst1|p_win~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y1_N30 +cycloneii_lcell_comb \inst1|p_win~4 ( +// Equation(s): +// \inst1|p_win~4_combout = (!\inst|sum_out [5] & (!\inst1|LessThan2~10_combout & !\inst1|p_win~0_combout )) + + .dataa(\inst|sum_out [5]), + .datab(vcc), + .datac(\inst1|LessThan2~10_combout ), + .datad(\inst1|p_win~0_combout ), + .cin(gnd), + .combout(\inst1|p_win~4_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|p_win~4 .lut_mask = 16'h0005; +defparam \inst1|p_win~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y1_N0 +cycloneii_lcell_comb \inst1|p_win~5 ( +// Equation(s): +// \inst1|p_win~5_combout = (\inst1|p_win~2_combout ) # ((\inst1|Equal0~2_combout ) # ((\inst1|p_win~3_combout ) # (!\inst1|p_win~4_combout ))) + + .dataa(\inst1|p_win~2_combout ), + .datab(\inst1|Equal0~2_combout ), + .datac(\inst1|p_win~3_combout ), + .datad(\inst1|p_win~4_combout ), + .cin(gnd), + .combout(\inst1|p_win~5_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|p_win~5 .lut_mask = 16'hFEFF; +defparam \inst1|p_win~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y1_N6 +cycloneii_lcell_comb \inst1|p_win~7 ( +// Equation(s): +// \inst1|p_win~7_combout = (\inst1|p_win~5_combout & (\inst1|p_win~1_combout & (!\inst1|p_win~6_combout ))) # (!\inst1|p_win~5_combout & (((\inst1|dealer:p_win~regout )))) + + .dataa(\inst1|p_win~1_combout ), + .datab(\inst1|p_win~6_combout ), + .datac(\inst1|dealer:p_win~regout ), + .datad(\inst1|p_win~5_combout ), + .cin(gnd), + .combout(\inst1|p_win~7_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|p_win~7 .lut_mask = 16'h22F0; +defparam \inst1|p_win~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y1_N24 +cycloneii_lcell_comb \inst1|player_wins~feeder ( +// Equation(s): +// \inst1|player_wins~feeder_combout = \inst1|p_win~7_combout + + .dataa(vcc), + .datab(vcc), + .datac(vcc), + .datad(\inst1|p_win~7_combout ), + .cin(gnd), + .combout(\inst1|player_wins~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|player_wins~feeder .lut_mask = 16'hFF00; +defparam \inst1|player_wins~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X1_Y1_N25 +cycloneii_lcell_ff \inst1|player_wins ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst1|player_wins~feeder_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst1|player_wins~regout )); + +// Location: LCCOMB_X1_Y1_N14 +cycloneii_lcell_comb \inst1|d_win~0 ( +// Equation(s): +// \inst1|d_win~0_combout = (\inst1|p_win~5_combout & (((\inst1|p_win~6_combout ) # (\inst1|p_win~4_combout )))) # (!\inst1|p_win~5_combout & (\inst1|dealer:d_win~regout )) + + .dataa(\inst1|dealer:d_win~regout ), + .datab(\inst1|p_win~6_combout ), + .datac(\inst1|p_win~4_combout ), + .datad(\inst1|p_win~5_combout ), + .cin(gnd), + .combout(\inst1|d_win~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|d_win~0 .lut_mask = 16'hFCAA; +defparam \inst1|d_win~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X1_Y1_N15 +cycloneii_lcell_ff \inst1|dealer_wins ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst1|d_win~0_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst1|dealer_wins~regout )); + +// Location: LCCOMB_X1_Y1_N8 +cycloneii_lcell_comb \inst1|p_win~1 ( +// Equation(s): +// \inst1|p_win~1_combout = (\inst|sum_out [5]) # ((\inst1|p_win~0_combout ) # ((\inst1|LessThan2~10_combout ) # (!\inst1|LessThan3~10_combout ))) + + .dataa(\inst|sum_out [5]), + .datab(\inst1|p_win~0_combout ), + .datac(\inst1|LessThan3~10_combout ), + .datad(\inst1|LessThan2~10_combout ), + .cin(gnd), + .combout(\inst1|p_win~1_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|p_win~1 .lut_mask = 16'hFFEF; +defparam \inst1|p_win~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y1_N26 +cycloneii_lcell_comb \inst1|led_display1~6 ( +// Equation(s): +// \inst1|led_display1~6_combout = (\inst1|p_win~2_combout ) # ((\player_sum~combout [5]) # ((!\inst1|p_win~1_combout ) # (!\inst1|p_win~4_combout ))) + + .dataa(\inst1|p_win~2_combout ), + .datab(\player_sum~combout [5]), + .datac(\inst1|p_win~4_combout ), + .datad(\inst1|p_win~1_combout ), + .cin(gnd), + .combout(\inst1|led_display1~6_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|led_display1~6 .lut_mask = 16'hEFFF; +defparam \inst1|led_display1~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y1_N12 +cycloneii_lcell_comb \inst1|led_display1~4 ( +// Equation(s): +// \inst1|led_display1~4_combout = (\inst1|p_win~5_combout & (((\inst1|led_display1~6_combout )))) # (!\inst1|p_win~5_combout & (((!\inst1|dealer:p_win~regout )) # (!\inst1|dealer:d_win~regout ))) + + .dataa(\inst1|dealer:d_win~regout ), + .datab(\inst1|p_win~5_combout ), + .datac(\inst1|dealer:p_win~regout ), + .datad(\inst1|led_display1~6_combout ), + .cin(gnd), + .combout(\inst1|led_display1~4_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|led_display1~4 .lut_mask = 16'hDF13; +defparam \inst1|led_display1~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X1_Y1_N5 +cycloneii_lcell_ff \inst1|dealer:d_win ( + .clk(\clk~clkctrl_outclk ), + .datain(gnd), + .sdata(\inst1|d_win~0_combout ), + .aclr(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst1|dealer:d_win~regout )); + +// Location: LCCOMB_X1_Y1_N28 +cycloneii_lcell_comb \inst1|led_display1[0]~7 ( +// Equation(s): +// \inst1|led_display1[0]~7_combout = (\inst1|p_win~2_combout ) # ((\player_sum~combout [5]) # ((\inst1|p_win~1_combout ) # (\inst1|p_win~4_combout ))) + + .dataa(\inst1|p_win~2_combout ), + .datab(\player_sum~combout [5]), + .datac(\inst1|p_win~1_combout ), + .datad(\inst1|p_win~4_combout ), + .cin(gnd), + .combout(\inst1|led_display1[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|led_display1[0]~7 .lut_mask = 16'hFFFE; +defparam \inst1|led_display1[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y1_N4 +cycloneii_lcell_comb \inst1|led_display1[0]~5 ( +// Equation(s): +// \inst1|led_display1[0]~5_combout = (\inst1|p_win~5_combout & (((\inst1|led_display1[0]~7_combout )))) # (!\inst1|p_win~5_combout & ((\inst1|dealer:p_win~regout ) # ((\inst1|dealer:d_win~regout )))) + + .dataa(\inst1|dealer:p_win~regout ), + .datab(\inst1|p_win~5_combout ), + .datac(\inst1|dealer:d_win~regout ), + .datad(\inst1|led_display1[0]~7_combout ), + .cin(gnd), + .combout(\inst1|led_display1[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|led_display1[0]~5 .lut_mask = 16'hFE32; +defparam \inst1|led_display1[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X1_Y1_N13 +cycloneii_lcell_ff \inst1|led_display1[0] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst1|led_display1~4_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\inst1|led_display1[0]~5_combout ), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst1|led_display1 [0])); + +// Location: LCCOMB_X1_Y1_N10 +cycloneii_lcell_comb \inst1|led_display3~3 ( +// Equation(s): +// \inst1|led_display3~3_combout = (\inst1|p_win~2_combout ) # ((\player_sum~combout [5]) # ((\inst1|p_win~4_combout ) # (!\inst1|p_win~1_combout ))) + + .dataa(\inst1|p_win~2_combout ), + .datab(\player_sum~combout [5]), + .datac(\inst1|p_win~4_combout ), + .datad(\inst1|p_win~1_combout ), + .cin(gnd), + .combout(\inst1|led_display3~3_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|led_display3~3 .lut_mask = 16'hFEFF; +defparam \inst1|led_display3~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y1_N22 +cycloneii_lcell_comb \inst1|led_display3~2 ( +// Equation(s): +// \inst1|led_display3~2_combout = (\inst1|p_win~5_combout & (((\inst1|led_display3~3_combout )))) # (!\inst1|p_win~5_combout & ((\inst1|dealer:d_win~regout ) # ((!\inst1|dealer:p_win~regout )))) + + .dataa(\inst1|dealer:d_win~regout ), + .datab(\inst1|p_win~5_combout ), + .datac(\inst1|dealer:p_win~regout ), + .datad(\inst1|led_display3~3_combout ), + .cin(gnd), + .combout(\inst1|led_display3~2_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|led_display3~2 .lut_mask = 16'hEF23; +defparam \inst1|led_display3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X1_Y1_N23 +cycloneii_lcell_ff \inst1|led_display3[1] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst1|led_display3~2_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\inst1|led_display1[0]~5_combout ), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst1|led_display3 [1])); + +// Location: LCCOMB_X1_Y1_N16 +cycloneii_lcell_comb \inst1|led_display4[3]~feeder ( +// Equation(s): +// \inst1|led_display4[3]~feeder_combout = \inst1|p_win~7_combout + + .dataa(vcc), + .datab(vcc), + .datac(vcc), + .datad(\inst1|p_win~7_combout ), + .cin(gnd), + .combout(\inst1|led_display4[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|led_display4[3]~feeder .lut_mask = 16'hFF00; +defparam \inst1|led_display4[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X1_Y1_N17 +cycloneii_lcell_ff \inst1|led_display4[3] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst1|led_display4[3]~feeder_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\inst1|led_display1[0]~5_combout ), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst1|led_display4 [3])); + +// Location: PIN_W7, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \hit~I ( + .datain(\inst|hit~regout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(hit)); +// synopsys translate_off +defparam \hit~I .input_async_reset = "none"; +defparam \hit~I .input_power_up = "low"; +defparam \hit~I .input_register_mode = "none"; +defparam \hit~I .input_sync_reset = "none"; +defparam \hit~I .oe_async_reset = "none"; +defparam \hit~I .oe_power_up = "low"; +defparam \hit~I .oe_register_mode = "none"; +defparam \hit~I .oe_sync_reset = "none"; +defparam \hit~I .operation_mode = "output"; +defparam \hit~I .output_async_reset = "none"; +defparam \hit~I .output_power_up = "low"; +defparam \hit~I .output_register_mode = "none"; +defparam \hit~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_V9, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \done~I ( + .datain(\inst|done~regout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(done)); +// synopsys translate_off +defparam \done~I .input_async_reset = "none"; +defparam \done~I .input_power_up = "low"; +defparam \done~I .input_register_mode = "none"; +defparam \done~I .input_sync_reset = "none"; +defparam \done~I .oe_async_reset = "none"; +defparam \done~I .oe_power_up = "low"; +defparam \done~I .oe_register_mode = "none"; +defparam \done~I .oe_sync_reset = "none"; +defparam \done~I .operation_mode = "output"; +defparam \done~I .output_async_reset = "none"; +defparam \done~I .output_power_up = "low"; +defparam \done~I .output_register_mode = "none"; +defparam \done~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_W4, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \player_wins~I ( + .datain(\inst1|player_wins~regout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(player_wins)); +// synopsys translate_off +defparam \player_wins~I .input_async_reset = "none"; +defparam \player_wins~I .input_power_up = "low"; +defparam \player_wins~I .input_register_mode = "none"; +defparam \player_wins~I .input_sync_reset = "none"; +defparam \player_wins~I .oe_async_reset = "none"; +defparam \player_wins~I .oe_power_up = "low"; +defparam \player_wins~I .oe_register_mode = "none"; +defparam \player_wins~I .oe_sync_reset = "none"; +defparam \player_wins~I .operation_mode = "output"; +defparam \player_wins~I .output_async_reset = "none"; +defparam \player_wins~I .output_power_up = "low"; +defparam \player_wins~I .output_register_mode = "none"; +defparam \player_wins~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_W3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \dealer_wins~I ( + .datain(\inst1|dealer_wins~regout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(dealer_wins)); +// synopsys translate_off +defparam \dealer_wins~I .input_async_reset = "none"; +defparam \dealer_wins~I .input_power_up = "low"; +defparam \dealer_wins~I .input_register_mode = "none"; +defparam \dealer_wins~I .input_sync_reset = "none"; +defparam \dealer_wins~I .oe_async_reset = "none"; +defparam \dealer_wins~I .oe_power_up = "low"; +defparam \dealer_wins~I .oe_register_mode = "none"; +defparam \dealer_wins~I .oe_sync_reset = "none"; +defparam \dealer_wins~I .operation_mode = "output"; +defparam \dealer_wins~I .output_async_reset = "none"; +defparam \dealer_wins~I .output_power_up = "low"; +defparam \dealer_wins~I .output_register_mode = "none"; +defparam \dealer_wins~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_R6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display1[6]~I ( + .datain(\inst1|led_display1 [0]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display1[6])); +// synopsys translate_off +defparam \led_display1[6]~I .input_async_reset = "none"; +defparam \led_display1[6]~I .input_power_up = "low"; +defparam \led_display1[6]~I .input_register_mode = "none"; +defparam \led_display1[6]~I .input_sync_reset = "none"; +defparam \led_display1[6]~I .oe_async_reset = "none"; +defparam \led_display1[6]~I .oe_power_up = "low"; +defparam \led_display1[6]~I .oe_register_mode = "none"; +defparam \led_display1[6]~I .oe_sync_reset = "none"; +defparam \led_display1[6]~I .operation_mode = "output"; +defparam \led_display1[6]~I .output_async_reset = "none"; +defparam \led_display1[6]~I .output_power_up = "low"; +defparam \led_display1[6]~I .output_register_mode = "none"; +defparam \led_display1[6]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_B17, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display1[5]~I ( + .datain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display1[5])); +// synopsys translate_off +defparam \led_display1[5]~I .input_async_reset = "none"; +defparam \led_display1[5]~I .input_power_up = "low"; +defparam \led_display1[5]~I .input_register_mode = "none"; +defparam \led_display1[5]~I .input_sync_reset = "none"; +defparam \led_display1[5]~I .oe_async_reset = "none"; +defparam \led_display1[5]~I .oe_power_up = "low"; +defparam \led_display1[5]~I .oe_register_mode = "none"; +defparam \led_display1[5]~I .oe_sync_reset = "none"; +defparam \led_display1[5]~I .operation_mode = "output"; +defparam \led_display1[5]~I .output_async_reset = "none"; +defparam \led_display1[5]~I .output_power_up = "low"; +defparam \led_display1[5]~I .output_register_mode = "none"; +defparam \led_display1[5]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_T15, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display1[4]~I ( + .datain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display1[4])); +// synopsys translate_off +defparam \led_display1[4]~I .input_async_reset = "none"; +defparam \led_display1[4]~I .input_power_up = "low"; +defparam \led_display1[4]~I .input_register_mode = "none"; +defparam \led_display1[4]~I .input_sync_reset = "none"; +defparam \led_display1[4]~I .oe_async_reset = "none"; +defparam \led_display1[4]~I .oe_power_up = "low"; +defparam \led_display1[4]~I .oe_register_mode = "none"; +defparam \led_display1[4]~I .oe_sync_reset = "none"; +defparam \led_display1[4]~I .operation_mode = "output"; +defparam \led_display1[4]~I .output_async_reset = "none"; +defparam \led_display1[4]~I .output_power_up = "low"; +defparam \led_display1[4]~I .output_register_mode = "none"; +defparam \led_display1[4]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_T3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display1[3]~I ( + .datain(!\inst1|led_display1 [0]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display1[3])); +// synopsys translate_off +defparam \led_display1[3]~I .input_async_reset = "none"; +defparam \led_display1[3]~I .input_power_up = "low"; +defparam \led_display1[3]~I .input_register_mode = "none"; +defparam \led_display1[3]~I .input_sync_reset = "none"; +defparam \led_display1[3]~I .oe_async_reset = "none"; +defparam \led_display1[3]~I .oe_power_up = "low"; +defparam \led_display1[3]~I .oe_register_mode = "none"; +defparam \led_display1[3]~I .oe_sync_reset = "none"; +defparam \led_display1[3]~I .operation_mode = "output"; +defparam \led_display1[3]~I .output_async_reset = "none"; +defparam \led_display1[3]~I .output_power_up = "low"; +defparam \led_display1[3]~I .output_register_mode = "none"; +defparam \led_display1[3]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_Y2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display1[2]~I ( + .datain(\inst1|led_display3 [1]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display1[2])); +// synopsys translate_off +defparam \led_display1[2]~I .input_async_reset = "none"; +defparam \led_display1[2]~I .input_power_up = "low"; +defparam \led_display1[2]~I .input_register_mode = "none"; +defparam \led_display1[2]~I .input_sync_reset = "none"; +defparam \led_display1[2]~I .oe_async_reset = "none"; +defparam \led_display1[2]~I .oe_power_up = "low"; +defparam \led_display1[2]~I .oe_register_mode = "none"; +defparam \led_display1[2]~I .oe_sync_reset = "none"; +defparam \led_display1[2]~I .operation_mode = "output"; +defparam \led_display1[2]~I .output_async_reset = "none"; +defparam \led_display1[2]~I .output_power_up = "low"; +defparam \led_display1[2]~I .output_register_mode = "none"; +defparam \led_display1[2]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_U2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display1[1]~I ( + .datain(\inst1|led_display1 [0]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display1[1])); +// synopsys translate_off +defparam \led_display1[1]~I .input_async_reset = "none"; +defparam \led_display1[1]~I .input_power_up = "low"; +defparam \led_display1[1]~I .input_register_mode = "none"; +defparam \led_display1[1]~I .input_sync_reset = "none"; +defparam \led_display1[1]~I .oe_async_reset = "none"; +defparam \led_display1[1]~I .oe_power_up = "low"; +defparam \led_display1[1]~I .oe_register_mode = "none"; +defparam \led_display1[1]~I .oe_sync_reset = "none"; +defparam \led_display1[1]~I .operation_mode = "output"; +defparam \led_display1[1]~I .output_async_reset = "none"; +defparam \led_display1[1]~I .output_power_up = "low"; +defparam \led_display1[1]~I .output_register_mode = "none"; +defparam \led_display1[1]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_R5, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display1[0]~I ( + .datain(\inst1|led_display1 [0]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display1[0])); +// synopsys translate_off +defparam \led_display1[0]~I .input_async_reset = "none"; +defparam \led_display1[0]~I .input_power_up = "low"; +defparam \led_display1[0]~I .input_register_mode = "none"; +defparam \led_display1[0]~I .input_sync_reset = "none"; +defparam \led_display1[0]~I .oe_async_reset = "none"; +defparam \led_display1[0]~I .oe_power_up = "low"; +defparam \led_display1[0]~I .oe_register_mode = "none"; +defparam \led_display1[0]~I .oe_sync_reset = "none"; +defparam \led_display1[0]~I .operation_mode = "output"; +defparam \led_display1[0]~I .output_async_reset = "none"; +defparam \led_display1[0]~I .output_power_up = "low"; +defparam \led_display1[0]~I .output_register_mode = "none"; +defparam \led_display1[0]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_B14, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display2[6]~I ( + .datain(vcc), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display2[6])); +// synopsys translate_off +defparam \led_display2[6]~I .input_async_reset = "none"; +defparam \led_display2[6]~I .input_power_up = "low"; +defparam \led_display2[6]~I .input_register_mode = "none"; +defparam \led_display2[6]~I .input_sync_reset = "none"; +defparam \led_display2[6]~I .oe_async_reset = "none"; +defparam \led_display2[6]~I .oe_power_up = "low"; +defparam \led_display2[6]~I .oe_register_mode = "none"; +defparam \led_display2[6]~I .oe_sync_reset = "none"; +defparam \led_display2[6]~I .operation_mode = "output"; +defparam \led_display2[6]~I .output_async_reset = "none"; +defparam \led_display2[6]~I .output_power_up = "low"; +defparam \led_display2[6]~I .output_register_mode = "none"; +defparam \led_display2[6]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_T5, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display2[5]~I ( + .datain(!\inst1|led_display3 [1]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display2[5])); +// synopsys translate_off +defparam \led_display2[5]~I .input_async_reset = "none"; +defparam \led_display2[5]~I .input_power_up = "low"; +defparam \led_display2[5]~I .input_register_mode = "none"; +defparam \led_display2[5]~I .input_sync_reset = "none"; +defparam \led_display2[5]~I .oe_async_reset = "none"; +defparam \led_display2[5]~I .oe_power_up = "low"; +defparam \led_display2[5]~I .oe_register_mode = "none"; +defparam \led_display2[5]~I .oe_sync_reset = "none"; +defparam \led_display2[5]~I .operation_mode = "output"; +defparam \led_display2[5]~I .output_async_reset = "none"; +defparam \led_display2[5]~I .output_power_up = "low"; +defparam \led_display2[5]~I .output_register_mode = "none"; +defparam \led_display2[5]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_W9, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display2[4]~I ( + .datain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display2[4])); +// synopsys translate_off +defparam \led_display2[4]~I .input_async_reset = "none"; +defparam \led_display2[4]~I .input_power_up = "low"; +defparam \led_display2[4]~I .input_register_mode = "none"; +defparam \led_display2[4]~I .input_sync_reset = "none"; +defparam \led_display2[4]~I .oe_async_reset = "none"; +defparam \led_display2[4]~I .oe_power_up = "low"; +defparam \led_display2[4]~I .oe_register_mode = "none"; +defparam \led_display2[4]~I .oe_sync_reset = "none"; +defparam \led_display2[4]~I .operation_mode = "output"; +defparam \led_display2[4]~I .output_async_reset = "none"; +defparam \led_display2[4]~I .output_power_up = "low"; +defparam \led_display2[4]~I .output_register_mode = "none"; +defparam \led_display2[4]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_H15, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display2[3]~I ( + .datain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display2[3])); +// synopsys translate_off +defparam \led_display2[3]~I .input_async_reset = "none"; +defparam \led_display2[3]~I .input_power_up = "low"; +defparam \led_display2[3]~I .input_register_mode = "none"; +defparam \led_display2[3]~I .input_sync_reset = "none"; +defparam \led_display2[3]~I .oe_async_reset = "none"; +defparam \led_display2[3]~I .oe_power_up = "low"; +defparam \led_display2[3]~I .oe_register_mode = "none"; +defparam \led_display2[3]~I .oe_sync_reset = "none"; +defparam \led_display2[3]~I .operation_mode = "output"; +defparam \led_display2[3]~I .output_async_reset = "none"; +defparam \led_display2[3]~I .output_power_up = "low"; +defparam \led_display2[3]~I .output_register_mode = "none"; +defparam \led_display2[3]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_B11, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display2[2]~I ( + .datain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display2[2])); +// synopsys translate_off +defparam \led_display2[2]~I .input_async_reset = "none"; +defparam \led_display2[2]~I .input_power_up = "low"; +defparam \led_display2[2]~I .input_register_mode = "none"; +defparam \led_display2[2]~I .input_sync_reset = "none"; +defparam \led_display2[2]~I .oe_async_reset = "none"; +defparam \led_display2[2]~I .oe_power_up = "low"; +defparam \led_display2[2]~I .oe_register_mode = "none"; +defparam \led_display2[2]~I .oe_sync_reset = "none"; +defparam \led_display2[2]~I .operation_mode = "output"; +defparam \led_display2[2]~I .output_async_reset = "none"; +defparam \led_display2[2]~I .output_power_up = "low"; +defparam \led_display2[2]~I .output_register_mode = "none"; +defparam \led_display2[2]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_AA16, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display2[1]~I ( + .datain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display2[1])); +// synopsys translate_off +defparam \led_display2[1]~I .input_async_reset = "none"; +defparam \led_display2[1]~I .input_power_up = "low"; +defparam \led_display2[1]~I .input_register_mode = "none"; +defparam \led_display2[1]~I .input_sync_reset = "none"; +defparam \led_display2[1]~I .oe_async_reset = "none"; +defparam \led_display2[1]~I .oe_power_up = "low"; +defparam \led_display2[1]~I .oe_register_mode = "none"; +defparam \led_display2[1]~I .oe_sync_reset = "none"; +defparam \led_display2[1]~I .operation_mode = "output"; +defparam \led_display2[1]~I .output_async_reset = "none"; +defparam \led_display2[1]~I .output_power_up = "low"; +defparam \led_display2[1]~I .output_register_mode = "none"; +defparam \led_display2[1]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_AB7, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display2[0]~I ( + .datain(\inst1|led_display4 [3]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display2[0])); +// synopsys translate_off +defparam \led_display2[0]~I .input_async_reset = "none"; +defparam \led_display2[0]~I .input_power_up = "low"; +defparam \led_display2[0]~I .input_register_mode = "none"; +defparam \led_display2[0]~I .input_sync_reset = "none"; +defparam \led_display2[0]~I .oe_async_reset = "none"; +defparam \led_display2[0]~I .oe_power_up = "low"; +defparam \led_display2[0]~I .oe_register_mode = "none"; +defparam \led_display2[0]~I .oe_sync_reset = "none"; +defparam \led_display2[0]~I .operation_mode = "output"; +defparam \led_display2[0]~I .output_async_reset = "none"; +defparam \led_display2[0]~I .output_power_up = "low"; +defparam \led_display2[0]~I .output_register_mode = "none"; +defparam \led_display2[0]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_T6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display3[6]~I ( + .datain(!\inst1|led_display3 [1]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display3[6])); +// synopsys translate_off +defparam \led_display3[6]~I .input_async_reset = "none"; +defparam \led_display3[6]~I .input_power_up = "low"; +defparam \led_display3[6]~I .input_register_mode = "none"; +defparam \led_display3[6]~I .input_sync_reset = "none"; +defparam \led_display3[6]~I .oe_async_reset = "none"; +defparam \led_display3[6]~I .oe_power_up = "low"; +defparam \led_display3[6]~I .oe_register_mode = "none"; +defparam \led_display3[6]~I .oe_sync_reset = "none"; +defparam \led_display3[6]~I .operation_mode = "output"; +defparam \led_display3[6]~I .output_async_reset = "none"; +defparam \led_display3[6]~I .output_power_up = "low"; +defparam \led_display3[6]~I .output_register_mode = "none"; +defparam \led_display3[6]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_U3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display3[5]~I ( + .datain(!\inst1|led_display3 [1]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display3[5])); +// synopsys translate_off +defparam \led_display3[5]~I .input_async_reset = "none"; +defparam \led_display3[5]~I .input_power_up = "low"; +defparam \led_display3[5]~I .input_register_mode = "none"; +defparam \led_display3[5]~I .input_sync_reset = "none"; +defparam \led_display3[5]~I .oe_async_reset = "none"; +defparam \led_display3[5]~I .oe_power_up = "low"; +defparam \led_display3[5]~I .oe_register_mode = "none"; +defparam \led_display3[5]~I .oe_sync_reset = "none"; +defparam \led_display3[5]~I .operation_mode = "output"; +defparam \led_display3[5]~I .output_async_reset = "none"; +defparam \led_display3[5]~I .output_power_up = "low"; +defparam \led_display3[5]~I .output_register_mode = "none"; +defparam \led_display3[5]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_C7, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display3[4]~I ( + .datain(vcc), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display3[4])); +// synopsys translate_off +defparam \led_display3[4]~I .input_async_reset = "none"; +defparam \led_display3[4]~I .input_power_up = "low"; +defparam \led_display3[4]~I .input_register_mode = "none"; +defparam \led_display3[4]~I .input_sync_reset = "none"; +defparam \led_display3[4]~I .oe_async_reset = "none"; +defparam \led_display3[4]~I .oe_power_up = "low"; +defparam \led_display3[4]~I .oe_register_mode = "none"; +defparam \led_display3[4]~I .oe_sync_reset = "none"; +defparam \led_display3[4]~I .operation_mode = "output"; +defparam \led_display3[4]~I .output_async_reset = "none"; +defparam \led_display3[4]~I .output_power_up = "low"; +defparam \led_display3[4]~I .output_register_mode = "none"; +defparam \led_display3[4]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_W1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display3[3]~I ( + .datain(!\inst1|led_display3 [1]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display3[3])); +// synopsys translate_off +defparam \led_display3[3]~I .input_async_reset = "none"; +defparam \led_display3[3]~I .input_power_up = "low"; +defparam \led_display3[3]~I .input_register_mode = "none"; +defparam \led_display3[3]~I .input_sync_reset = "none"; +defparam \led_display3[3]~I .oe_async_reset = "none"; +defparam \led_display3[3]~I .oe_power_up = "low"; +defparam \led_display3[3]~I .oe_register_mode = "none"; +defparam \led_display3[3]~I .oe_sync_reset = "none"; +defparam \led_display3[3]~I .operation_mode = "output"; +defparam \led_display3[3]~I .output_async_reset = "none"; +defparam \led_display3[3]~I .output_power_up = "low"; +defparam \led_display3[3]~I .output_register_mode = "none"; +defparam \led_display3[3]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_C21, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display3[2]~I ( + .datain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display3[2])); +// synopsys translate_off +defparam \led_display3[2]~I .input_async_reset = "none"; +defparam \led_display3[2]~I .input_power_up = "low"; +defparam \led_display3[2]~I .input_register_mode = "none"; +defparam \led_display3[2]~I .input_sync_reset = "none"; +defparam \led_display3[2]~I .oe_async_reset = "none"; +defparam \led_display3[2]~I .oe_power_up = "low"; +defparam \led_display3[2]~I .oe_register_mode = "none"; +defparam \led_display3[2]~I .oe_sync_reset = "none"; +defparam \led_display3[2]~I .operation_mode = "output"; +defparam \led_display3[2]~I .output_async_reset = "none"; +defparam \led_display3[2]~I .output_power_up = "low"; +defparam \led_display3[2]~I .output_register_mode = "none"; +defparam \led_display3[2]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_Y1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display3[1]~I ( + .datain(\inst1|led_display3 [1]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display3[1])); +// synopsys translate_off +defparam \led_display3[1]~I .input_async_reset = "none"; +defparam \led_display3[1]~I .input_power_up = "low"; +defparam \led_display3[1]~I .input_register_mode = "none"; +defparam \led_display3[1]~I .input_sync_reset = "none"; +defparam \led_display3[1]~I .oe_async_reset = "none"; +defparam \led_display3[1]~I .oe_power_up = "low"; +defparam \led_display3[1]~I .oe_register_mode = "none"; +defparam \led_display3[1]~I .oe_sync_reset = "none"; +defparam \led_display3[1]~I .operation_mode = "output"; +defparam \led_display3[1]~I .output_async_reset = "none"; +defparam \led_display3[1]~I .output_power_up = "low"; +defparam \led_display3[1]~I .output_register_mode = "none"; +defparam \led_display3[1]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_V2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display3[0]~I ( + .datain(!\inst1|led_display3 [1]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display3[0])); +// synopsys translate_off +defparam \led_display3[0]~I .input_async_reset = "none"; +defparam \led_display3[0]~I .input_power_up = "low"; +defparam \led_display3[0]~I .input_register_mode = "none"; +defparam \led_display3[0]~I .input_sync_reset = "none"; +defparam \led_display3[0]~I .oe_async_reset = "none"; +defparam \led_display3[0]~I .oe_power_up = "low"; +defparam \led_display3[0]~I .oe_register_mode = "none"; +defparam \led_display3[0]~I .oe_sync_reset = "none"; +defparam \led_display3[0]~I .operation_mode = "output"; +defparam \led_display3[0]~I .output_async_reset = "none"; +defparam \led_display3[0]~I .output_power_up = "low"; +defparam \led_display3[0]~I .output_register_mode = "none"; +defparam \led_display3[0]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_W2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display4[6]~I ( + .datain(!\inst1|led_display3 [1]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display4[6])); +// synopsys translate_off +defparam \led_display4[6]~I .input_async_reset = "none"; +defparam \led_display4[6]~I .input_power_up = "low"; +defparam \led_display4[6]~I .input_register_mode = "none"; +defparam \led_display4[6]~I .input_sync_reset = "none"; +defparam \led_display4[6]~I .oe_async_reset = "none"; +defparam \led_display4[6]~I .oe_power_up = "low"; +defparam \led_display4[6]~I .oe_register_mode = "none"; +defparam \led_display4[6]~I .oe_sync_reset = "none"; +defparam \led_display4[6]~I .operation_mode = "output"; +defparam \led_display4[6]~I .output_async_reset = "none"; +defparam \led_display4[6]~I .output_power_up = "low"; +defparam \led_display4[6]~I .output_register_mode = "none"; +defparam \led_display4[6]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_G8, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display4[5]~I ( + .datain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display4[5])); +// synopsys translate_off +defparam \led_display4[5]~I .input_async_reset = "none"; +defparam \led_display4[5]~I .input_power_up = "low"; +defparam \led_display4[5]~I .input_register_mode = "none"; +defparam \led_display4[5]~I .input_sync_reset = "none"; +defparam \led_display4[5]~I .oe_async_reset = "none"; +defparam \led_display4[5]~I .oe_power_up = "low"; +defparam \led_display4[5]~I .oe_register_mode = "none"; +defparam \led_display4[5]~I .oe_sync_reset = "none"; +defparam \led_display4[5]~I .operation_mode = "output"; +defparam \led_display4[5]~I .output_async_reset = "none"; +defparam \led_display4[5]~I .output_power_up = "low"; +defparam \led_display4[5]~I .output_register_mode = "none"; +defparam \led_display4[5]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_D2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display4[4]~I ( + .datain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display4[4])); +// synopsys translate_off +defparam \led_display4[4]~I .input_async_reset = "none"; +defparam \led_display4[4]~I .input_power_up = "low"; +defparam \led_display4[4]~I .input_register_mode = "none"; +defparam \led_display4[4]~I .input_sync_reset = "none"; +defparam \led_display4[4]~I .oe_async_reset = "none"; +defparam \led_display4[4]~I .oe_power_up = "low"; +defparam \led_display4[4]~I .oe_register_mode = "none"; +defparam \led_display4[4]~I .oe_sync_reset = "none"; +defparam \led_display4[4]~I .operation_mode = "output"; +defparam \led_display4[4]~I .output_async_reset = "none"; +defparam \led_display4[4]~I .output_power_up = "low"; +defparam \led_display4[4]~I .output_register_mode = "none"; +defparam \led_display4[4]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_P9, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display4[3]~I ( + .datain(\inst1|led_display4 [3]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display4[3])); +// synopsys translate_off +defparam \led_display4[3]~I .input_async_reset = "none"; +defparam \led_display4[3]~I .input_power_up = "low"; +defparam \led_display4[3]~I .input_register_mode = "none"; +defparam \led_display4[3]~I .input_sync_reset = "none"; +defparam \led_display4[3]~I .oe_async_reset = "none"; +defparam \led_display4[3]~I .oe_power_up = "low"; +defparam \led_display4[3]~I .oe_register_mode = "none"; +defparam \led_display4[3]~I .oe_sync_reset = "none"; +defparam \led_display4[3]~I .operation_mode = "output"; +defparam \led_display4[3]~I .output_async_reset = "none"; +defparam \led_display4[3]~I .output_power_up = "low"; +defparam \led_display4[3]~I .output_register_mode = "none"; +defparam \led_display4[3]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_P8, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display4[2]~I ( + .datain(!\inst1|led_display4 [3]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display4[2])); +// synopsys translate_off +defparam \led_display4[2]~I .input_async_reset = "none"; +defparam \led_display4[2]~I .input_power_up = "low"; +defparam \led_display4[2]~I .input_register_mode = "none"; +defparam \led_display4[2]~I .input_sync_reset = "none"; +defparam \led_display4[2]~I .oe_async_reset = "none"; +defparam \led_display4[2]~I .oe_power_up = "low"; +defparam \led_display4[2]~I .oe_register_mode = "none"; +defparam \led_display4[2]~I .oe_sync_reset = "none"; +defparam \led_display4[2]~I .operation_mode = "output"; +defparam \led_display4[2]~I .output_async_reset = "none"; +defparam \led_display4[2]~I .output_power_up = "low"; +defparam \led_display4[2]~I .output_register_mode = "none"; +defparam \led_display4[2]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_AA7, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display4[1]~I ( + .datain(!\inst1|led_display4 [3]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display4[1])); +// synopsys translate_off +defparam \led_display4[1]~I .input_async_reset = "none"; +defparam \led_display4[1]~I .input_power_up = "low"; +defparam \led_display4[1]~I .input_register_mode = "none"; +defparam \led_display4[1]~I .input_sync_reset = "none"; +defparam \led_display4[1]~I .oe_async_reset = "none"; +defparam \led_display4[1]~I .oe_power_up = "low"; +defparam \led_display4[1]~I .oe_register_mode = "none"; +defparam \led_display4[1]~I .oe_sync_reset = "none"; +defparam \led_display4[1]~I .operation_mode = "output"; +defparam \led_display4[1]~I .output_async_reset = "none"; +defparam \led_display4[1]~I .output_power_up = "low"; +defparam \led_display4[1]~I .output_register_mode = "none"; +defparam \led_display4[1]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_U1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display4[0]~I ( + .datain(!\inst1|led_display1 [0]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display4[0])); +// synopsys translate_off +defparam \led_display4[0]~I .input_async_reset = "none"; +defparam \led_display4[0]~I .input_power_up = "low"; +defparam \led_display4[0]~I .input_register_mode = "none"; +defparam \led_display4[0]~I .input_sync_reset = "none"; +defparam \led_display4[0]~I .oe_async_reset = "none"; +defparam \led_display4[0]~I .oe_power_up = "low"; +defparam \led_display4[0]~I .oe_register_mode = "none"; +defparam \led_display4[0]~I .oe_sync_reset = "none"; +defparam \led_display4[0]~I .operation_mode = "output"; +defparam \led_display4[0]~I .output_async_reset = "none"; +defparam \led_display4[0]~I .output_power_up = "low"; +defparam \led_display4[0]~I .output_register_mode = "none"; +defparam \led_display4[0]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_V8, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \state_out[1]~I ( + .datain(\inst|computer:state[1]~regout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(state_out[1])); +// synopsys translate_off +defparam \state_out[1]~I .input_async_reset = "none"; +defparam \state_out[1]~I .input_power_up = "low"; +defparam \state_out[1]~I .input_register_mode = "none"; +defparam \state_out[1]~I .input_sync_reset = "none"; +defparam \state_out[1]~I .oe_async_reset = "none"; +defparam \state_out[1]~I .oe_power_up = "low"; +defparam \state_out[1]~I .oe_register_mode = "none"; +defparam \state_out[1]~I .oe_sync_reset = "none"; +defparam \state_out[1]~I .operation_mode = "output"; +defparam \state_out[1]~I .output_async_reset = "none"; +defparam \state_out[1]~I .output_power_up = "low"; +defparam \state_out[1]~I .output_register_mode = "none"; +defparam \state_out[1]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_AB6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \state_out[0]~I ( + .datain(\inst|computer:state[0]~regout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(state_out[0])); +// synopsys translate_off +defparam \state_out[0]~I .input_async_reset = "none"; +defparam \state_out[0]~I .input_power_up = "low"; +defparam \state_out[0]~I .input_register_mode = "none"; +defparam \state_out[0]~I .input_sync_reset = "none"; +defparam \state_out[0]~I .oe_async_reset = "none"; +defparam \state_out[0]~I .oe_power_up = "low"; +defparam \state_out[0]~I .oe_register_mode = "none"; +defparam \state_out[0]~I .oe_sync_reset = "none"; +defparam \state_out[0]~I .operation_mode = "output"; +defparam \state_out[0]~I .output_async_reset = "none"; +defparam \state_out[0]~I .output_power_up = "low"; +defparam \state_out[0]~I .output_register_mode = "none"; +defparam \state_out[0]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_U4, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \sum_out[5]~I ( + .datain(\inst|sum_out [5]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(sum_out[5])); +// synopsys translate_off +defparam \sum_out[5]~I .input_async_reset = "none"; +defparam \sum_out[5]~I .input_power_up = "low"; +defparam \sum_out[5]~I .input_register_mode = "none"; +defparam \sum_out[5]~I .input_sync_reset = "none"; +defparam \sum_out[5]~I .oe_async_reset = "none"; +defparam \sum_out[5]~I .oe_power_up = "low"; +defparam \sum_out[5]~I .oe_register_mode = "none"; +defparam \sum_out[5]~I .oe_sync_reset = "none"; +defparam \sum_out[5]~I .operation_mode = "output"; +defparam \sum_out[5]~I .output_async_reset = "none"; +defparam \sum_out[5]~I .output_power_up = "low"; +defparam \sum_out[5]~I .output_register_mode = "none"; +defparam \sum_out[5]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_W5, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \sum_out[4]~I ( + .datain(\inst|sum_out [4]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(sum_out[4])); +// synopsys translate_off +defparam \sum_out[4]~I .input_async_reset = "none"; +defparam \sum_out[4]~I .input_power_up = "low"; +defparam \sum_out[4]~I .input_register_mode = "none"; +defparam \sum_out[4]~I .input_sync_reset = "none"; +defparam \sum_out[4]~I .oe_async_reset = "none"; +defparam \sum_out[4]~I .oe_power_up = "low"; +defparam \sum_out[4]~I .oe_register_mode = "none"; +defparam \sum_out[4]~I .oe_sync_reset = "none"; +defparam \sum_out[4]~I .operation_mode = "output"; +defparam \sum_out[4]~I .output_async_reset = "none"; +defparam \sum_out[4]~I .output_power_up = "low"; +defparam \sum_out[4]~I .output_register_mode = "none"; +defparam \sum_out[4]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_AA4, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \sum_out[3]~I ( + .datain(\inst|sum_out [3]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(sum_out[3])); +// synopsys translate_off +defparam \sum_out[3]~I .input_async_reset = "none"; +defparam \sum_out[3]~I .input_power_up = "low"; +defparam \sum_out[3]~I .input_register_mode = "none"; +defparam \sum_out[3]~I .input_sync_reset = "none"; +defparam \sum_out[3]~I .oe_async_reset = "none"; +defparam \sum_out[3]~I .oe_power_up = "low"; +defparam \sum_out[3]~I .oe_register_mode = "none"; +defparam \sum_out[3]~I .oe_sync_reset = "none"; +defparam \sum_out[3]~I .operation_mode = "output"; +defparam \sum_out[3]~I .output_async_reset = "none"; +defparam \sum_out[3]~I .output_power_up = "low"; +defparam \sum_out[3]~I .output_register_mode = "none"; +defparam \sum_out[3]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_T8, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \sum_out[2]~I ( + .datain(\inst|sum_out [2]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(sum_out[2])); +// synopsys translate_off +defparam \sum_out[2]~I .input_async_reset = "none"; +defparam \sum_out[2]~I .input_power_up = "low"; +defparam \sum_out[2]~I .input_register_mode = "none"; +defparam \sum_out[2]~I .input_sync_reset = "none"; +defparam \sum_out[2]~I .oe_async_reset = "none"; +defparam \sum_out[2]~I .oe_power_up = "low"; +defparam \sum_out[2]~I .oe_register_mode = "none"; +defparam \sum_out[2]~I .oe_sync_reset = "none"; +defparam \sum_out[2]~I .operation_mode = "output"; +defparam \sum_out[2]~I .output_async_reset = "none"; +defparam \sum_out[2]~I .output_power_up = "low"; +defparam \sum_out[2]~I .output_register_mode = "none"; +defparam \sum_out[2]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_T7, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \sum_out[1]~I ( + .datain(\inst|sum_out [1]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(sum_out[1])); +// synopsys translate_off +defparam \sum_out[1]~I .input_async_reset = "none"; +defparam \sum_out[1]~I .input_power_up = "low"; +defparam \sum_out[1]~I .input_register_mode = "none"; +defparam \sum_out[1]~I .input_sync_reset = "none"; +defparam \sum_out[1]~I .oe_async_reset = "none"; +defparam \sum_out[1]~I .oe_power_up = "low"; +defparam \sum_out[1]~I .oe_register_mode = "none"; +defparam \sum_out[1]~I .oe_sync_reset = "none"; +defparam \sum_out[1]~I .operation_mode = "output"; +defparam \sum_out[1]~I .output_async_reset = "none"; +defparam \sum_out[1]~I .output_power_up = "low"; +defparam \sum_out[1]~I .output_register_mode = "none"; +defparam \sum_out[1]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_AB4, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \sum_out[0]~I ( + .datain(\inst|sum_out [0]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(sum_out[0])); +// synopsys translate_off +defparam \sum_out[0]~I .input_async_reset = "none"; +defparam \sum_out[0]~I .input_power_up = "low"; +defparam \sum_out[0]~I .input_register_mode = "none"; +defparam \sum_out[0]~I .input_sync_reset = "none"; +defparam \sum_out[0]~I .oe_async_reset = "none"; +defparam \sum_out[0]~I .oe_power_up = "low"; +defparam \sum_out[0]~I .oe_register_mode = "none"; +defparam \sum_out[0]~I .oe_sync_reset = "none"; +defparam \sum_out[0]~I .operation_mode = "output"; +defparam \sum_out[0]~I .output_async_reset = "none"; +defparam \sum_out[0]~I .output_power_up = "low"; +defparam \sum_out[0]~I .output_register_mode = "none"; +defparam \sum_out[0]~I .output_sync_reset = "none"; +// synopsys translate_on + +endmodule diff --git a/lab5/simulation/modelsim/gA6_lab5_fast.vho b/lab5/simulation/modelsim/gA6_lab5_fast.vho new file mode 100644 index 0000000..f877b3e --- /dev/null +++ b/lab5/simulation/modelsim/gA6_lab5_fast.vho @@ -0,0 +1,2415 @@ +-- Copyright (C) 1991-2013 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + +-- VENDOR "Altera" +-- PROGRAM "Quartus II 64-Bit" +-- VERSION "Version 13.0.0 Build 156 04/24/2013 SJ Web Edition" + +-- DATE "11/29/2017 18:38:50" + +-- +-- Device: Altera EP2C20F484C7 Package FBGA484 +-- + +-- +-- This VHDL file should be used for ModelSim-Altera (VHDL) only +-- + +LIBRARY CYCLONEII; +LIBRARY IEEE; +USE CYCLONEII.CYCLONEII_COMPONENTS.ALL; +USE IEEE.STD_LOGIC_1164.ALL; + +ENTITY gA6_lab5 IS + PORT ( + hit : OUT std_logic; + clk : IN std_logic; + rst : IN std_logic; + turn : IN std_logic; + sum : IN std_logic_vector(5 DOWNTO 0); + done : OUT std_logic; + player_wins : OUT std_logic; + player_sum : IN std_logic_vector(5 DOWNTO 0); + dealer_wins : OUT std_logic; + led_display1 : OUT std_logic_vector(6 DOWNTO 0); + led_display2 : OUT std_logic_vector(6 DOWNTO 0); + led_display3 : OUT std_logic_vector(6 DOWNTO 0); + led_display4 : OUT std_logic_vector(6 DOWNTO 0); + sum_out : OUT std_logic_vector(5 DOWNTO 0) + ); +END gA6_lab5; + +-- Design Ports Information +-- hit => Location: PIN_T2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- done => Location: PIN_R1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- player_wins => Location: PIN_Y4, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- dealer_wins => Location: PIN_T6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display1[6] => Location: PIN_N2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display1[5] => Location: PIN_C14, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display1[4] => Location: PIN_B19, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display1[3] => Location: PIN_P1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display1[2] => Location: PIN_AA4, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display1[1] => Location: PIN_M5, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display1[0] => Location: PIN_N6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display2[6] => Location: PIN_AA13, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display2[5] => Location: PIN_AB4, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display2[4] => Location: PIN_A18, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display2[3] => Location: PIN_C7, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display2[2] => Location: PIN_AA6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display2[1] => Location: PIN_A5, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display2[0] => Location: PIN_P6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display3[6] => Location: PIN_W3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display3[5] => Location: PIN_Y3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display3[4] => Location: PIN_B6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display3[3] => Location: PIN_W4, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display3[2] => Location: PIN_F11, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display3[1] => Location: PIN_AA3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display3[0] => Location: PIN_AB3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display4[6] => Location: PIN_W5, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display4[5] => Location: PIN_V8, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display4[4] => Location: PIN_A19, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display4[3] => Location: PIN_N3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display4[2] => Location: PIN_P3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display4[1] => Location: PIN_N4, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- led_display4[0] => Location: PIN_M6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- sum_out[5] => Location: PIN_R5, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- sum_out[4] => Location: PIN_U2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- sum_out[3] => Location: PIN_W2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- sum_out[2] => Location: PIN_P2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- sum_out[1] => Location: PIN_V1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- sum_out[0] => Location: PIN_T5, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +-- clk => Location: PIN_M1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- rst => Location: PIN_M2, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- player_sum[5] => Location: PIN_R6, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- player_sum[4] => Location: PIN_U1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- player_sum[3] => Location: PIN_W1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- player_sum[2] => Location: PIN_V2, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- player_sum[1] => Location: PIN_Y1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- player_sum[0] => Location: PIN_Y2, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- sum[5] => Location: PIN_R8, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- sum[4] => Location: PIN_T3, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- sum[3] => Location: PIN_U3, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- sum[2] => Location: PIN_R7, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- sum[1] => Location: PIN_T1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- sum[0] => Location: PIN_P5, I/O Standard: 3.3-V LVTTL, Current Strength: Default +-- turn => Location: PIN_R2, I/O Standard: 3.3-V LVTTL, Current Strength: Default + + +ARCHITECTURE structure OF gA6_lab5 IS +SIGNAL gnd : std_logic := '0'; +SIGNAL vcc : std_logic := '1'; +SIGNAL unknown : std_logic := 'X'; +SIGNAL devoe : std_logic := '1'; +SIGNAL devclrn : std_logic := '1'; +SIGNAL devpor : std_logic := '1'; +SIGNAL ww_devoe : std_logic; +SIGNAL ww_devclrn : std_logic; +SIGNAL ww_devpor : std_logic; +SIGNAL ww_hit : std_logic; +SIGNAL ww_clk : std_logic; +SIGNAL ww_rst : std_logic; +SIGNAL ww_turn : std_logic; +SIGNAL ww_sum : std_logic_vector(5 DOWNTO 0); +SIGNAL ww_done : std_logic; +SIGNAL ww_player_wins : std_logic; +SIGNAL ww_player_sum : std_logic_vector(5 DOWNTO 0); +SIGNAL ww_dealer_wins : std_logic; +SIGNAL ww_led_display1 : std_logic_vector(6 DOWNTO 0); +SIGNAL ww_led_display2 : std_logic_vector(6 DOWNTO 0); +SIGNAL ww_led_display3 : std_logic_vector(6 DOWNTO 0); +SIGNAL ww_led_display4 : std_logic_vector(6 DOWNTO 0); +SIGNAL ww_sum_out : std_logic_vector(5 DOWNTO 0); +SIGNAL \clk~clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0); +SIGNAL \rst~clkctrl_INCLK_bus\ : std_logic_vector(3 DOWNTO 0); +SIGNAL \inst1|p_win~0_combout\ : std_logic; +SIGNAL \inst1|p_win~2_combout\ : std_logic; +SIGNAL \inst|computer:state[1]~0_combout\ : std_logic; +SIGNAL \turn~combout\ : std_logic; +SIGNAL \clk~combout\ : std_logic; +SIGNAL \clk~clkctrl_outclk\ : std_logic; +SIGNAL \inst|computer:state[0]~0_combout\ : std_logic; +SIGNAL \inst|computer:state[0]~1_combout\ : std_logic; +SIGNAL \inst|computer:state[0]~2_combout\ : std_logic; +SIGNAL \rst~combout\ : std_logic; +SIGNAL \rst~clkctrl_outclk\ : std_logic; +SIGNAL \inst|computer:state[0]~regout\ : std_logic; +SIGNAL \inst|computer:state[1]~1_combout\ : std_logic; +SIGNAL \inst|computer:state[1]~regout\ : std_logic; +SIGNAL \inst|Mux0~0_combout\ : std_logic; +SIGNAL \inst|hit~regout\ : std_logic; +SIGNAL \inst|Mux1~0_combout\ : std_logic; +SIGNAL \inst|done~regout\ : std_logic; +SIGNAL \inst1|p_win~6_combout\ : std_logic; +SIGNAL \inst1|LessThan2~1_cout\ : std_logic; +SIGNAL \inst1|LessThan2~3_cout\ : std_logic; +SIGNAL \inst1|LessThan2~5_cout\ : std_logic; +SIGNAL \inst1|LessThan2~7_cout\ : std_logic; +SIGNAL \inst1|LessThan2~9_cout\ : std_logic; +SIGNAL \inst1|LessThan2~10_combout\ : std_logic; +SIGNAL \inst1|LessThan3~1_cout\ : std_logic; +SIGNAL \inst1|LessThan3~3_cout\ : std_logic; +SIGNAL \inst1|LessThan3~5_cout\ : std_logic; +SIGNAL \inst1|LessThan3~7_cout\ : std_logic; +SIGNAL \inst1|LessThan3~9_cout\ : std_logic; +SIGNAL \inst1|LessThan3~10_combout\ : std_logic; +SIGNAL \inst1|p_win~1_combout\ : std_logic; +SIGNAL \inst1|Equal0~0_combout\ : std_logic; +SIGNAL \inst1|Equal0~1_combout\ : std_logic; +SIGNAL \inst1|Equal0~2_combout\ : std_logic; +SIGNAL \inst1|p_win~3_combout\ : std_logic; +SIGNAL \inst1|p_win~4_combout\ : std_logic; +SIGNAL \inst1|p_win~5_combout\ : std_logic; +SIGNAL \inst1|p_win~7_combout\ : std_logic; +SIGNAL \inst1|player_wins~regout\ : std_logic; +SIGNAL \inst1|dealer:d_win~regout\ : std_logic; +SIGNAL \inst1|d_win~0_combout\ : std_logic; +SIGNAL \inst1|dealer_wins~regout\ : std_logic; +SIGNAL \inst1|led_display1~6_combout\ : std_logic; +SIGNAL \inst1|led_display1~4_combout\ : std_logic; +SIGNAL \inst1|dealer:p_win~regout\ : std_logic; +SIGNAL \inst1|led_display1[0]~7_combout\ : std_logic; +SIGNAL \inst1|led_display1[0]~5_combout\ : std_logic; +SIGNAL \inst1|led_display3~3_combout\ : std_logic; +SIGNAL \inst1|led_display3~2_combout\ : std_logic; +SIGNAL \inst|sum_out\ : std_logic_vector(5 DOWNTO 0); +SIGNAL \inst1|led_display4\ : std_logic_vector(6 DOWNTO 0); +SIGNAL \inst1|led_display3\ : std_logic_vector(6 DOWNTO 0); +SIGNAL \inst1|led_display1\ : std_logic_vector(6 DOWNTO 0); +SIGNAL \sum~combout\ : std_logic_vector(5 DOWNTO 0); +SIGNAL \player_sum~combout\ : std_logic_vector(5 DOWNTO 0); +SIGNAL \inst1|ALT_INV_led_display4\ : std_logic_vector(3 DOWNTO 3); +SIGNAL \inst1|ALT_INV_led_display3\ : std_logic_vector(1 DOWNTO 1); +SIGNAL \inst1|ALT_INV_led_display1\ : std_logic_vector(0 DOWNTO 0); + +BEGIN + +hit <= ww_hit; +ww_clk <= clk; +ww_rst <= rst; +ww_turn <= turn; +ww_sum <= sum; +done <= ww_done; +player_wins <= ww_player_wins; +ww_player_sum <= player_sum; +dealer_wins <= ww_dealer_wins; +led_display1 <= ww_led_display1; +led_display2 <= ww_led_display2; +led_display3 <= ww_led_display3; +led_display4 <= ww_led_display4; +sum_out <= ww_sum_out; +ww_devoe <= devoe; +ww_devclrn <= devclrn; +ww_devpor <= devpor; + +\clk~clkctrl_INCLK_bus\ <= (gnd & gnd & gnd & \clk~combout\); + +\rst~clkctrl_INCLK_bus\ <= (gnd & gnd & gnd & \rst~combout\); +\inst1|ALT_INV_led_display4\(3) <= NOT \inst1|led_display4\(3); +\inst1|ALT_INV_led_display3\(1) <= NOT \inst1|led_display3\(1); +\inst1|ALT_INV_led_display1\(0) <= NOT \inst1|led_display1\(0); + +-- Location: LCCOMB_X1_Y7_N2 +\inst1|p_win~0\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|p_win~0_combout\ = (\inst|sum_out\(4) & ((\inst|sum_out\(3)) # ((\inst|sum_out\(1) & \inst|sum_out\(2))))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1010100010001000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|sum_out\(4), + datab => \inst|sum_out\(3), + datac => \inst|sum_out\(1), + datad => \inst|sum_out\(2), + combout => \inst1|p_win~0_combout\); + +-- Location: LCCOMB_X1_Y7_N30 +\inst1|p_win~2\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|p_win~2_combout\ = (\player_sum~combout\(4) & ((\player_sum~combout\(3)) # ((\player_sum~combout\(2) & \player_sum~combout\(1))))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111000010000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \player_sum~combout\(2), + datab => \player_sum~combout\(1), + datac => \player_sum~combout\(4), + datad => \player_sum~combout\(3), + combout => \inst1|p_win~2_combout\); + +-- Location: LCCOMB_X1_Y8_N30 +\inst|computer:state[1]~0\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst|computer:state[1]~0_combout\ = (\sum~combout\(2)) # ((\sum~combout\(1)) # ((\sum~combout\(0)) # (\sum~combout\(3)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111111111110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \sum~combout\(2), + datab => \sum~combout\(1), + datac => \sum~combout\(0), + datad => \sum~combout\(3), + combout => \inst|computer:state[1]~0_combout\); + +-- Location: PIN_V2, I/O Standard: 3.3-V LVTTL, Current Strength: Default +\player_sum[2]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "input", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => GND, + padio => ww_player_sum(2), + combout => \player_sum~combout\(2)); + +-- Location: PIN_Y2, I/O Standard: 3.3-V LVTTL, Current Strength: Default +\player_sum[0]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "input", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => GND, + padio => ww_player_sum(0), + combout => \player_sum~combout\(0)); + +-- Location: PIN_R2, I/O Standard: 3.3-V LVTTL, Current Strength: Default +\turn~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "input", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => GND, + padio => ww_turn, + combout => \turn~combout\); + +-- Location: PIN_M1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +\clk~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "input", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => GND, + padio => ww_clk, + combout => \clk~combout\); + +-- Location: CLKCTRL_G3 +\clk~clkctrl\ : cycloneii_clkctrl +-- pragma translate_off +GENERIC MAP ( + clock_type => "global clock", + ena_register_mode => "none") +-- pragma translate_on +PORT MAP ( + inclk => \clk~clkctrl_INCLK_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + outclk => \clk~clkctrl_outclk\); + +-- Location: PIN_T3, I/O Standard: 3.3-V LVTTL, Current Strength: Default +\sum[4]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "input", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => GND, + padio => ww_sum(4), + combout => \sum~combout\(4)); + +-- Location: PIN_R8, I/O Standard: 3.3-V LVTTL, Current Strength: Default +\sum[5]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "input", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => GND, + padio => ww_sum(5), + combout => \sum~combout\(5)); + +-- Location: LCCOMB_X1_Y8_N12 +\inst|computer:state[0]~0\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst|computer:state[0]~0_combout\ = (!\inst|computer:state[1]~regout\ & ((!\inst|computer:state[0]~regout\) # (!\sum~combout\(5)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000111111", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \sum~combout\(5), + datac => \inst|computer:state[0]~regout\, + datad => \inst|computer:state[1]~regout\, + combout => \inst|computer:state[0]~0_combout\); + +-- Location: LCCOMB_X1_Y8_N0 +\inst|computer:state[0]~1\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst|computer:state[0]~1_combout\ = (\inst|computer:state[0]~0_combout\ & (((!\inst|computer:state[0]~regout\) # (!\sum~combout\(4))) # (!\inst|computer:state[1]~0_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0111111100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst|computer:state[1]~0_combout\, + datab => \sum~combout\(4), + datac => \inst|computer:state[0]~regout\, + datad => \inst|computer:state[0]~0_combout\, + combout => \inst|computer:state[0]~1_combout\); + +-- Location: LCCOMB_X1_Y8_N20 +\inst|computer:state[0]~2\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst|computer:state[0]~2_combout\ = (\inst|computer:state[0]~1_combout\ & ((\turn~combout\) # (\inst|computer:state[0]~regout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111101000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \turn~combout\, + datac => \inst|computer:state[0]~regout\, + datad => \inst|computer:state[0]~1_combout\, + combout => \inst|computer:state[0]~2_combout\); + +-- Location: PIN_M2, I/O Standard: 3.3-V LVTTL, Current Strength: Default +\rst~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "input", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => GND, + padio => ww_rst, + combout => \rst~combout\); + +-- Location: CLKCTRL_G1 +\rst~clkctrl\ : cycloneii_clkctrl +-- pragma translate_off +GENERIC MAP ( + clock_type => "global clock", + ena_register_mode => "none") +-- pragma translate_on +PORT MAP ( + inclk => \rst~clkctrl_INCLK_bus\, + devclrn => ww_devclrn, + devpor => ww_devpor, + outclk => \rst~clkctrl_outclk\); + +-- Location: LCFF_X1_Y8_N21 +\inst|computer:state[0]\ : cycloneii_lcell_ff +PORT MAP ( + clk => \clk~clkctrl_outclk\, + datain => \inst|computer:state[0]~2_combout\, + aclr => \rst~clkctrl_outclk\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \inst|computer:state[0]~regout\); + +-- Location: LCCOMB_X1_Y8_N2 +\inst|computer:state[1]~1\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst|computer:state[1]~1_combout\ = (\inst|computer:state[0]~regout\ & (!\inst|computer:state[1]~regout\ & !\inst|computer:state[0]~1_combout\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000001100", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \inst|computer:state[0]~regout\, + datac => \inst|computer:state[1]~regout\, + datad => \inst|computer:state[0]~1_combout\, + combout => \inst|computer:state[1]~1_combout\); + +-- Location: LCFF_X1_Y8_N3 +\inst|computer:state[1]\ : cycloneii_lcell_ff +PORT MAP ( + clk => \clk~clkctrl_outclk\, + datain => \inst|computer:state[1]~1_combout\, + aclr => \rst~clkctrl_outclk\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \inst|computer:state[1]~regout\); + +-- Location: LCCOMB_X1_Y8_N28 +\inst|Mux0~0\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst|Mux0~0_combout\ = (!\inst|computer:state[1]~regout\ & \inst|computer:state[0]~regout\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011001100000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \inst|computer:state[1]~regout\, + datad => \inst|computer:state[0]~regout\, + combout => \inst|Mux0~0_combout\); + +-- Location: LCFF_X1_Y8_N29 +\inst|hit\ : cycloneii_lcell_ff +PORT MAP ( + clk => \clk~clkctrl_outclk\, + datain => \inst|Mux0~0_combout\, + aclr => \rst~clkctrl_outclk\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \inst|hit~regout\); + +-- Location: LCCOMB_X1_Y8_N26 +\inst|Mux1~0\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst|Mux1~0_combout\ = (\inst|computer:state[1]~regout\ & !\inst|computer:state[0]~regout\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000011001100", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datab => \inst|computer:state[1]~regout\, + datad => \inst|computer:state[0]~regout\, + combout => \inst|Mux1~0_combout\); + +-- Location: LCFF_X1_Y8_N27 +\inst|done\ : cycloneii_lcell_ff +PORT MAP ( + clk => \clk~clkctrl_outclk\, + datain => \inst|Mux1~0_combout\, + aclr => \rst~clkctrl_outclk\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \inst|done~regout\); + +-- Location: PIN_R6, I/O Standard: 3.3-V LVTTL, Current Strength: Default +\player_sum[5]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "input", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => GND, + padio => ww_player_sum(5), + combout => \player_sum~combout\(5)); + +-- Location: LCCOMB_X2_Y7_N6 +\inst1|p_win~6\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|p_win~6_combout\ = (\inst1|p_win~2_combout\) # (\player_sum~combout\(5)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111101011111010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst1|p_win~2_combout\, + datac => \player_sum~combout\(5), + combout => \inst1|p_win~6_combout\); + +-- Location: LCFF_X1_Y7_N27 +\inst|sum_out[5]\ : cycloneii_lcell_ff +PORT MAP ( + clk => \clk~clkctrl_outclk\, + sdata => \sum~combout\(5), + aclr => \rst~clkctrl_outclk\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \inst|sum_out\(5)); + +-- Location: PIN_U1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +\player_sum[4]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "input", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => GND, + padio => ww_player_sum(4), + combout => \player_sum~combout\(4)); + +-- Location: PIN_U3, I/O Standard: 3.3-V LVTTL, Current Strength: Default +\sum[3]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "input", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => GND, + padio => ww_sum(3), + combout => \sum~combout\(3)); + +-- Location: LCFF_X1_Y7_N23 +\inst|sum_out[3]\ : cycloneii_lcell_ff +PORT MAP ( + clk => \clk~clkctrl_outclk\, + sdata => \sum~combout\(3), + aclr => \rst~clkctrl_outclk\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \inst|sum_out\(3)); + +-- Location: PIN_R7, I/O Standard: 3.3-V LVTTL, Current Strength: Default +\sum[2]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "input", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => GND, + padio => ww_sum(2), + combout => \sum~combout\(2)); + +-- Location: LCFF_X1_Y7_N29 +\inst|sum_out[2]\ : cycloneii_lcell_ff +PORT MAP ( + clk => \clk~clkctrl_outclk\, + sdata => \sum~combout\(2), + aclr => \rst~clkctrl_outclk\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \inst|sum_out\(2)); + +-- Location: PIN_T1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +\sum[1]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "input", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => GND, + padio => ww_sum(1), + combout => \sum~combout\(1)); + +-- Location: LCFF_X1_Y7_N3 +\inst|sum_out[1]\ : cycloneii_lcell_ff +PORT MAP ( + clk => \clk~clkctrl_outclk\, + sdata => \sum~combout\(1), + aclr => \rst~clkctrl_outclk\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \inst|sum_out\(1)); + +-- Location: PIN_P5, I/O Standard: 3.3-V LVTTL, Current Strength: Default +\sum[0]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "input", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => GND, + padio => ww_sum(0), + combout => \sum~combout\(0)); + +-- Location: LCFF_X1_Y7_N1 +\inst|sum_out[0]\ : cycloneii_lcell_ff +PORT MAP ( + clk => \clk~clkctrl_outclk\, + sdata => \sum~combout\(0), + aclr => \rst~clkctrl_outclk\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \inst|sum_out\(0)); + +-- Location: LCCOMB_X1_Y7_N16 +\inst1|LessThan2~1\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|LessThan2~1_cout\ = CARRY((\player_sum~combout\(0) & !\inst|sum_out\(0))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000100010", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \player_sum~combout\(0), + datab => \inst|sum_out\(0), + datad => VCC, + cout => \inst1|LessThan2~1_cout\); + +-- Location: LCCOMB_X1_Y7_N18 +\inst1|LessThan2~3\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|LessThan2~3_cout\ = CARRY((\player_sum~combout\(1) & (\inst|sum_out\(1) & !\inst1|LessThan2~1_cout\)) # (!\player_sum~combout\(1) & ((\inst|sum_out\(1)) # (!\inst1|LessThan2~1_cout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000001001101", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \player_sum~combout\(1), + datab => \inst|sum_out\(1), + datad => VCC, + cin => \inst1|LessThan2~1_cout\, + cout => \inst1|LessThan2~3_cout\); + +-- Location: LCCOMB_X1_Y7_N20 +\inst1|LessThan2~5\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|LessThan2~5_cout\ = CARRY((\player_sum~combout\(2) & ((!\inst1|LessThan2~3_cout\) # (!\inst|sum_out\(2)))) # (!\player_sum~combout\(2) & (!\inst|sum_out\(2) & !\inst1|LessThan2~3_cout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000101011", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \player_sum~combout\(2), + datab => \inst|sum_out\(2), + datad => VCC, + cin => \inst1|LessThan2~3_cout\, + cout => \inst1|LessThan2~5_cout\); + +-- Location: LCCOMB_X1_Y7_N22 +\inst1|LessThan2~7\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|LessThan2~7_cout\ = CARRY((\player_sum~combout\(3) & (\inst|sum_out\(3) & !\inst1|LessThan2~5_cout\)) # (!\player_sum~combout\(3) & ((\inst|sum_out\(3)) # (!\inst1|LessThan2~5_cout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000001001101", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \player_sum~combout\(3), + datab => \inst|sum_out\(3), + datad => VCC, + cin => \inst1|LessThan2~5_cout\, + cout => \inst1|LessThan2~7_cout\); + +-- Location: LCCOMB_X1_Y7_N24 +\inst1|LessThan2~9\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|LessThan2~9_cout\ = CARRY((\inst|sum_out\(4) & (\player_sum~combout\(4) & !\inst1|LessThan2~7_cout\)) # (!\inst|sum_out\(4) & ((\player_sum~combout\(4)) # (!\inst1|LessThan2~7_cout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000001001101", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \inst|sum_out\(4), + datab => \player_sum~combout\(4), + datad => VCC, + cin => \inst1|LessThan2~7_cout\, + cout => \inst1|LessThan2~9_cout\); + +-- Location: LCCOMB_X1_Y7_N26 +\inst1|LessThan2~10\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|LessThan2~10_combout\ = (\player_sum~combout\(5) & ((\inst1|LessThan2~9_cout\) # (!\inst|sum_out\(5)))) # (!\player_sum~combout\(5) & (\inst1|LessThan2~9_cout\ & !\inst|sum_out\(5))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1100000011111100", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + datab => \player_sum~combout\(5), + datad => \inst|sum_out\(5), + cin => \inst1|LessThan2~9_cout\, + combout => \inst1|LessThan2~10_combout\); + +-- Location: LCCOMB_X1_Y7_N4 +\inst1|LessThan3~1\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|LessThan3~1_cout\ = CARRY((!\player_sum~combout\(0) & \inst|sum_out\(0))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000001000100", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \player_sum~combout\(0), + datab => \inst|sum_out\(0), + datad => VCC, + cout => \inst1|LessThan3~1_cout\); + +-- Location: LCCOMB_X1_Y7_N6 +\inst1|LessThan3~3\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|LessThan3~3_cout\ = CARRY((\player_sum~combout\(1) & ((!\inst1|LessThan3~1_cout\) # (!\inst|sum_out\(1)))) # (!\player_sum~combout\(1) & (!\inst|sum_out\(1) & !\inst1|LessThan3~1_cout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000101011", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \player_sum~combout\(1), + datab => \inst|sum_out\(1), + datad => VCC, + cin => \inst1|LessThan3~1_cout\, + cout => \inst1|LessThan3~3_cout\); + +-- Location: LCCOMB_X1_Y7_N8 +\inst1|LessThan3~5\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|LessThan3~5_cout\ = CARRY((\player_sum~combout\(2) & (\inst|sum_out\(2) & !\inst1|LessThan3~3_cout\)) # (!\player_sum~combout\(2) & ((\inst|sum_out\(2)) # (!\inst1|LessThan3~3_cout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000001001101", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \player_sum~combout\(2), + datab => \inst|sum_out\(2), + datad => VCC, + cin => \inst1|LessThan3~3_cout\, + cout => \inst1|LessThan3~5_cout\); + +-- Location: LCCOMB_X1_Y7_N10 +\inst1|LessThan3~7\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|LessThan3~7_cout\ = CARRY((\player_sum~combout\(3) & ((!\inst1|LessThan3~5_cout\) # (!\inst|sum_out\(3)))) # (!\player_sum~combout\(3) & (!\inst|sum_out\(3) & !\inst1|LessThan3~5_cout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000101011", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \player_sum~combout\(3), + datab => \inst|sum_out\(3), + datad => VCC, + cin => \inst1|LessThan3~5_cout\, + cout => \inst1|LessThan3~7_cout\); + +-- Location: LCCOMB_X1_Y7_N12 +\inst1|LessThan3~9\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|LessThan3~9_cout\ = CARRY((\inst|sum_out\(4) & ((!\inst1|LessThan3~7_cout\) # (!\player_sum~combout\(4)))) # (!\inst|sum_out\(4) & (!\player_sum~combout\(4) & !\inst1|LessThan3~7_cout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000101011", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + dataa => \inst|sum_out\(4), + datab => \player_sum~combout\(4), + datad => VCC, + cin => \inst1|LessThan3~7_cout\, + cout => \inst1|LessThan3~9_cout\); + +-- Location: LCCOMB_X1_Y7_N14 +\inst1|LessThan3~10\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|LessThan3~10_combout\ = (\player_sum~combout\(5) & (\inst1|LessThan3~9_cout\ & \inst|sum_out\(5))) # (!\player_sum~combout\(5) & ((\inst1|LessThan3~9_cout\) # (\inst|sum_out\(5)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111001100110000", + sum_lutc_input => "cin") +-- pragma translate_on +PORT MAP ( + datab => \player_sum~combout\(5), + datad => \inst|sum_out\(5), + cin => \inst1|LessThan3~9_cout\, + combout => \inst1|LessThan3~10_combout\); + +-- Location: LCCOMB_X2_Y7_N24 +\inst1|p_win~1\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|p_win~1_combout\ = (\inst1|p_win~0_combout\) # ((\inst1|LessThan2~10_combout\) # ((\inst|sum_out\(5)) # (!\inst1|LessThan3~10_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111011111111", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst1|p_win~0_combout\, + datab => \inst1|LessThan2~10_combout\, + datac => \inst|sum_out\(5), + datad => \inst1|LessThan3~10_combout\, + combout => \inst1|p_win~1_combout\); + +-- Location: LCFF_X1_Y7_N25 +\inst|sum_out[4]\ : cycloneii_lcell_ff +PORT MAP ( + clk => \clk~clkctrl_outclk\, + sdata => \sum~combout\(4), + aclr => \rst~clkctrl_outclk\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \inst|sum_out\(4)); + +-- Location: PIN_Y1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +\player_sum[1]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "input", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => GND, + padio => ww_player_sum(1), + combout => \player_sum~combout\(1)); + +-- Location: LCCOMB_X1_Y7_N0 +\inst1|Equal0~0\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|Equal0~0_combout\ = (\player_sum~combout\(0) & (\inst|sum_out\(0) & (\player_sum~combout\(1) $ (!\inst|sum_out\(1))))) # (!\player_sum~combout\(0) & (!\inst|sum_out\(0) & (\player_sum~combout\(1) $ (!\inst|sum_out\(1))))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1000010000100001", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \player_sum~combout\(0), + datab => \player_sum~combout\(1), + datac => \inst|sum_out\(0), + datad => \inst|sum_out\(1), + combout => \inst1|Equal0~0_combout\); + +-- Location: PIN_W1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +\player_sum[3]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "input", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => GND, + padio => ww_player_sum(3), + combout => \player_sum~combout\(3)); + +-- Location: LCCOMB_X1_Y7_N28 +\inst1|Equal0~1\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|Equal0~1_combout\ = (\player_sum~combout\(2) & (\inst|sum_out\(2) & (\player_sum~combout\(3) $ (!\inst|sum_out\(3))))) # (!\player_sum~combout\(2) & (!\inst|sum_out\(2) & (\player_sum~combout\(3) $ (!\inst|sum_out\(3))))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1000010000100001", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \player_sum~combout\(2), + datab => \player_sum~combout\(3), + datac => \inst|sum_out\(2), + datad => \inst|sum_out\(3), + combout => \inst1|Equal0~1_combout\); + +-- Location: LCCOMB_X2_Y7_N14 +\inst1|Equal0~2\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|Equal0~2_combout\ = (\inst1|Equal0~0_combout\ & (\inst1|Equal0~1_combout\ & (\player_sum~combout\(4) $ (!\inst|sum_out\(4))))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1001000000000000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \player_sum~combout\(4), + datab => \inst|sum_out\(4), + datac => \inst1|Equal0~0_combout\, + datad => \inst1|Equal0~1_combout\, + combout => \inst1|Equal0~2_combout\); + +-- Location: LCCOMB_X2_Y7_N8 +\inst1|p_win~3\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|p_win~3_combout\ = (\player_sum~combout\(5)) # (\inst1|LessThan3~10_combout\) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111111110000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + datac => \player_sum~combout\(5), + datad => \inst1|LessThan3~10_combout\, + combout => \inst1|p_win~3_combout\); + +-- Location: LCCOMB_X2_Y7_N10 +\inst1|p_win~4\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|p_win~4_combout\ = (!\inst1|p_win~0_combout\ & (!\inst|sum_out\(5) & !\inst1|LessThan2~10_combout\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0000000000000101", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst1|p_win~0_combout\, + datac => \inst|sum_out\(5), + datad => \inst1|LessThan2~10_combout\, + combout => \inst1|p_win~4_combout\); + +-- Location: LCCOMB_X2_Y7_N0 +\inst1|p_win~5\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|p_win~5_combout\ = (\inst1|p_win~2_combout\) # ((\inst1|Equal0~2_combout\) # ((\inst1|p_win~3_combout\) # (!\inst1|p_win~4_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111011111111", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst1|p_win~2_combout\, + datab => \inst1|Equal0~2_combout\, + datac => \inst1|p_win~3_combout\, + datad => \inst1|p_win~4_combout\, + combout => \inst1|p_win~5_combout\); + +-- Location: LCCOMB_X2_Y7_N20 +\inst1|p_win~7\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|p_win~7_combout\ = (\inst1|p_win~5_combout\ & (((!\inst1|p_win~6_combout\ & \inst1|p_win~1_combout\)))) # (!\inst1|p_win~5_combout\ & (\inst1|dealer:p_win~regout\)) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "0011000010101010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst1|dealer:p_win~regout\, + datab => \inst1|p_win~6_combout\, + datac => \inst1|p_win~1_combout\, + datad => \inst1|p_win~5_combout\, + combout => \inst1|p_win~7_combout\); + +-- Location: LCFF_X2_Y7_N17 +\inst1|player_wins\ : cycloneii_lcell_ff +PORT MAP ( + clk => \clk~clkctrl_outclk\, + sdata => \inst1|p_win~7_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \inst1|player_wins~regout\); + +-- Location: LCFF_X2_Y7_N5 +\inst1|dealer:d_win\ : cycloneii_lcell_ff +PORT MAP ( + clk => \clk~clkctrl_outclk\, + datain => \inst1|d_win~0_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \inst1|dealer:d_win~regout\); + +-- Location: LCCOMB_X2_Y7_N4 +\inst1|d_win~0\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|d_win~0_combout\ = (\inst1|p_win~5_combout\ & ((\inst1|p_win~4_combout\) # ((\inst1|p_win~6_combout\)))) # (!\inst1|p_win~5_combout\ & (((\inst1|dealer:d_win~regout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1110111011110000", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst1|p_win~4_combout\, + datab => \inst1|p_win~6_combout\, + datac => \inst1|dealer:d_win~regout\, + datad => \inst1|p_win~5_combout\, + combout => \inst1|d_win~0_combout\); + +-- Location: LCFF_X2_Y7_N31 +\inst1|dealer_wins\ : cycloneii_lcell_ff +PORT MAP ( + clk => \clk~clkctrl_outclk\, + sdata => \inst1|d_win~0_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \inst1|dealer_wins~regout\); + +-- Location: LCCOMB_X2_Y7_N2 +\inst1|led_display1~6\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|led_display1~6_combout\ = (\inst1|p_win~2_combout\) # ((\player_sum~combout\(5)) # ((!\inst1|p_win~1_combout\) # (!\inst1|p_win~4_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1110111111111111", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst1|p_win~2_combout\, + datab => \player_sum~combout\(5), + datac => \inst1|p_win~4_combout\, + datad => \inst1|p_win~1_combout\, + combout => \inst1|led_display1~6_combout\); + +-- Location: LCCOMB_X2_Y7_N12 +\inst1|led_display1~4\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|led_display1~4_combout\ = (\inst1|p_win~5_combout\ & (((\inst1|led_display1~6_combout\)))) # (!\inst1|p_win~5_combout\ & (((!\inst1|dealer:d_win~regout\)) # (!\inst1|dealer:p_win~regout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1101111100010011", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst1|dealer:p_win~regout\, + datab => \inst1|p_win~5_combout\, + datac => \inst1|dealer:d_win~regout\, + datad => \inst1|led_display1~6_combout\, + combout => \inst1|led_display1~4_combout\); + +-- Location: LCFF_X2_Y7_N27 +\inst1|dealer:p_win\ : cycloneii_lcell_ff +PORT MAP ( + clk => \clk~clkctrl_outclk\, + sdata => \inst1|p_win~7_combout\, + sload => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \inst1|dealer:p_win~regout\); + +-- Location: LCCOMB_X2_Y7_N28 +\inst1|led_display1[0]~7\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|led_display1[0]~7_combout\ = (\inst1|p_win~2_combout\) # ((\player_sum~combout\(5)) # ((\inst1|p_win~1_combout\) # (\inst1|p_win~4_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111111111110", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst1|p_win~2_combout\, + datab => \player_sum~combout\(5), + datac => \inst1|p_win~1_combout\, + datad => \inst1|p_win~4_combout\, + combout => \inst1|led_display1[0]~7_combout\); + +-- Location: LCCOMB_X2_Y7_N26 +\inst1|led_display1[0]~5\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|led_display1[0]~5_combout\ = (\inst1|p_win~5_combout\ & (((\inst1|led_display1[0]~7_combout\)))) # (!\inst1|p_win~5_combout\ & ((\inst1|dealer:d_win~regout\) # ((\inst1|dealer:p_win~regout\)))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111000110010", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst1|dealer:d_win~regout\, + datab => \inst1|p_win~5_combout\, + datac => \inst1|dealer:p_win~regout\, + datad => \inst1|led_display1[0]~7_combout\, + combout => \inst1|led_display1[0]~5_combout\); + +-- Location: LCFF_X2_Y7_N13 +\inst1|led_display1[0]\ : cycloneii_lcell_ff +PORT MAP ( + clk => \clk~clkctrl_outclk\, + datain => \inst1|led_display1~4_combout\, + ena => \inst1|led_display1[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \inst1|led_display1\(0)); + +-- Location: LCCOMB_X2_Y7_N18 +\inst1|led_display3~3\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|led_display3~3_combout\ = (\inst1|p_win~2_combout\) # ((\player_sum~combout\(5)) # ((\inst1|p_win~4_combout\) # (!\inst1|p_win~1_combout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111111011111111", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst1|p_win~2_combout\, + datab => \player_sum~combout\(5), + datac => \inst1|p_win~4_combout\, + datad => \inst1|p_win~1_combout\, + combout => \inst1|led_display3~3_combout\); + +-- Location: LCCOMB_X2_Y7_N22 +\inst1|led_display3~2\ : cycloneii_lcell_comb +-- Equation(s): +-- \inst1|led_display3~2_combout\ = (\inst1|p_win~5_combout\ & (((\inst1|led_display3~3_combout\)))) # (!\inst1|p_win~5_combout\ & (((\inst1|dealer:d_win~regout\)) # (!\inst1|dealer:p_win~regout\))) + +-- pragma translate_off +GENERIC MAP ( + lut_mask => "1111110100110001", + sum_lutc_input => "datac") +-- pragma translate_on +PORT MAP ( + dataa => \inst1|dealer:p_win~regout\, + datab => \inst1|p_win~5_combout\, + datac => \inst1|dealer:d_win~regout\, + datad => \inst1|led_display3~3_combout\, + combout => \inst1|led_display3~2_combout\); + +-- Location: LCFF_X2_Y7_N23 +\inst1|led_display3[1]\ : cycloneii_lcell_ff +PORT MAP ( + clk => \clk~clkctrl_outclk\, + datain => \inst1|led_display3~2_combout\, + ena => \inst1|led_display1[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \inst1|led_display3\(1)); + +-- Location: LCFF_X2_Y7_N21 +\inst1|led_display4[3]\ : cycloneii_lcell_ff +PORT MAP ( + clk => \clk~clkctrl_outclk\, + datain => \inst1|p_win~7_combout\, + ena => \inst1|led_display1[0]~5_combout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + regout => \inst1|led_display4\(3)); + +-- Location: PIN_T2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\hit~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst|hit~regout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_hit); + +-- Location: PIN_R1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\done~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst|done~regout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_done); + +-- Location: PIN_Y4, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\player_wins~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst1|player_wins~regout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_player_wins); + +-- Location: PIN_T6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\dealer_wins~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst1|dealer_wins~regout\, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_dealer_wins); + +-- Location: PIN_N2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display1[6]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst1|led_display1\(0), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display1(6)); + +-- Location: PIN_C14, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display1[5]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => GND, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display1(5)); + +-- Location: PIN_B19, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display1[4]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => GND, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display1(4)); + +-- Location: PIN_P1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display1[3]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst1|ALT_INV_led_display1\(0), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display1(3)); + +-- Location: PIN_AA4, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display1[2]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst1|led_display3\(1), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display1(2)); + +-- Location: PIN_M5, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display1[1]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst1|led_display1\(0), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display1(1)); + +-- Location: PIN_N6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display1[0]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst1|led_display1\(0), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display1(0)); + +-- Location: PIN_AA13, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display2[6]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display2(6)); + +-- Location: PIN_AB4, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display2[5]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst1|ALT_INV_led_display3\(1), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display2(5)); + +-- Location: PIN_A18, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display2[4]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => GND, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display2(4)); + +-- Location: PIN_C7, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display2[3]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => GND, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display2(3)); + +-- Location: PIN_AA6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display2[2]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => GND, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display2(2)); + +-- Location: PIN_A5, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display2[1]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => GND, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display2(1)); + +-- Location: PIN_P6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display2[0]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst1|led_display4\(3), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display2(0)); + +-- Location: PIN_W3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display3[6]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst1|ALT_INV_led_display3\(1), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display3(6)); + +-- Location: PIN_Y3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display3[5]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst1|ALT_INV_led_display3\(1), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display3(5)); + +-- Location: PIN_B6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display3[4]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => VCC, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display3(4)); + +-- Location: PIN_W4, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display3[3]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst1|ALT_INV_led_display3\(1), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display3(3)); + +-- Location: PIN_F11, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display3[2]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => GND, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display3(2)); + +-- Location: PIN_AA3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display3[1]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst1|led_display3\(1), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display3(1)); + +-- Location: PIN_AB3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display3[0]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst1|ALT_INV_led_display3\(1), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display3(0)); + +-- Location: PIN_W5, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display4[6]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst1|ALT_INV_led_display3\(1), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display4(6)); + +-- Location: PIN_V8, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display4[5]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => GND, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display4(5)); + +-- Location: PIN_A19, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display4[4]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => GND, + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display4(4)); + +-- Location: PIN_N3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display4[3]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst1|led_display4\(3), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display4(3)); + +-- Location: PIN_P3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display4[2]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst1|ALT_INV_led_display4\(3), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display4(2)); + +-- Location: PIN_N4, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display4[1]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst1|ALT_INV_led_display4\(3), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display4(1)); + +-- Location: PIN_M6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\led_display4[0]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst1|ALT_INV_led_display1\(0), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_led_display4(0)); + +-- Location: PIN_R5, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\sum_out[5]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst|sum_out\(5), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_sum_out(5)); + +-- Location: PIN_U2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\sum_out[4]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst|sum_out\(4), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_sum_out(4)); + +-- Location: PIN_W2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\sum_out[3]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst|sum_out\(3), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_sum_out(3)); + +-- Location: PIN_P2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\sum_out[2]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst|sum_out\(2), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_sum_out(2)); + +-- Location: PIN_V1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\sum_out[1]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst|sum_out\(1), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_sum_out(1)); + +-- Location: PIN_T5, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +\sum_out[0]~I\ : cycloneii_io +-- pragma translate_off +GENERIC MAP ( + input_async_reset => "none", + input_power_up => "low", + input_register_mode => "none", + input_sync_reset => "none", + oe_async_reset => "none", + oe_power_up => "low", + oe_register_mode => "none", + oe_sync_reset => "none", + operation_mode => "output", + output_async_reset => "none", + output_power_up => "low", + output_register_mode => "none", + output_sync_reset => "none") +-- pragma translate_on +PORT MAP ( + datain => \inst|sum_out\(0), + devclrn => ww_devclrn, + devpor => ww_devpor, + devoe => ww_devoe, + oe => VCC, + padio => ww_sum_out(0)); +END structure; + + diff --git a/lab5/simulation/modelsim/gA6_lab5_modelsim.xrf b/lab5/simulation/modelsim/gA6_lab5_modelsim.xrf new file mode 100644 index 0000000..a820b7c --- /dev/null +++ b/lab5/simulation/modelsim/gA6_lab5_modelsim.xrf @@ -0,0 +1,123 @@ +vendor_name = ModelSim +source_file = 1, C:/home/abbas/dsd_A6/lab5/gA6_winner.vhd +source_file = 1, C:/home/abbas/dsd_A6/lab5/gA6_computer.vhd +source_file = 1, C:/home/abbas/dsd_A6/lab5/gA6_lab5.bdf +source_file = 1, C:/home/abbas/dsd_A6/lab5/gA6_lab5_fsm.vwf +source_file = 1, C:/home/abbas/dsd_A6/lab5/db/gA6_lab5.cbx.xml +source_file = 1, c:/altera/13.0/quartus/libraries/vhdl/ieee/prmtvs_b.vhd +source_file = 1, c:/altera/13.0/quartus/libraries/vhdl/ieee/prmtvs_p.vhd +source_file = 1, c:/altera/13.0/quartus/libraries/vhdl/ieee/timing_b.vhd +source_file = 1, c:/altera/13.0/quartus/libraries/vhdl/ieee/timing_p.vhd +design_name = gA6_lab5 +instance = comp, \player_sum[4]~I , player_sum[4], gA6_lab5, 1 +instance = comp, \turn~I , turn, gA6_lab5, 1 +instance = comp, \clk~I , clk, gA6_lab5, 1 +instance = comp, \clk~clkctrl , clk~clkctrl, gA6_lab5, 1 +instance = comp, \sum[0]~I , sum[0], gA6_lab5, 1 +instance = comp, \sum[1]~I , sum[1], gA6_lab5, 1 +instance = comp, \sum[3]~I , sum[3], gA6_lab5, 1 +instance = comp, \inst|LessThan0~0 , inst|LessThan0~0, gA6_lab5, 1 +instance = comp, \sum[5]~I , sum[5], gA6_lab5, 1 +instance = comp, \inst|LessThan0~1 , inst|LessThan0~1, gA6_lab5, 1 +instance = comp, \inst|computer:state[0]~0 , inst|\computer:state[0]~0, gA6_lab5, 1 +instance = comp, \rst~I , rst, gA6_lab5, 1 +instance = comp, \rst~clkctrl , rst~clkctrl, gA6_lab5, 1 +instance = comp, \inst|computer:state[0] , inst|\computer:state[0], gA6_lab5, 1 +instance = comp, \inst|computer:state[1]~0 , inst|\computer:state[1]~0, gA6_lab5, 1 +instance = comp, \inst|computer:state[1] , inst|\computer:state[1], gA6_lab5, 1 +instance = comp, \inst|Mux0~0 , inst|Mux0~0, gA6_lab5, 1 +instance = comp, \inst|hit , inst|hit, gA6_lab5, 1 +instance = comp, \inst|Mux1~0 , inst|Mux1~0, gA6_lab5, 1 +instance = comp, \inst|done , inst|done, gA6_lab5, 1 +instance = comp, \player_sum[5]~I , player_sum[5], gA6_lab5, 1 +instance = comp, \player_sum[2]~I , player_sum[2], gA6_lab5, 1 +instance = comp, \player_sum[3]~I , player_sum[3], gA6_lab5, 1 +instance = comp, \player_sum[1]~I , player_sum[1], gA6_lab5, 1 +instance = comp, \inst1|p_win~2 , inst1|p_win~2, gA6_lab5, 1 +instance = comp, \inst1|p_win~6 , inst1|p_win~6, gA6_lab5, 1 +instance = comp, \inst1|dealer:p_win , inst1|\dealer:p_win, gA6_lab5, 1 +instance = comp, \sum[4]~I , sum[4], gA6_lab5, 1 +instance = comp, \inst|sum_out[4] , inst|sum_out[4], gA6_lab5, 1 +instance = comp, \sum[2]~I , sum[2], gA6_lab5, 1 +instance = comp, \inst|sum_out[2] , inst|sum_out[2], gA6_lab5, 1 +instance = comp, \inst|sum_out[3] , inst|sum_out[3], gA6_lab5, 1 +instance = comp, \inst1|Equal0~1 , inst1|Equal0~1, gA6_lab5, 1 +instance = comp, \player_sum[0]~I , player_sum[0], gA6_lab5, 1 +instance = comp, \inst|sum_out[0] , inst|sum_out[0], gA6_lab5, 1 +instance = comp, \inst|sum_out[1] , inst|sum_out[1], gA6_lab5, 1 +instance = comp, \inst1|Equal0~0 , inst1|Equal0~0, gA6_lab5, 1 +instance = comp, \inst1|Equal0~2 , inst1|Equal0~2, gA6_lab5, 1 +instance = comp, \inst|sum_out[5] , inst|sum_out[5], gA6_lab5, 1 +instance = comp, \inst1|LessThan3~1 , inst1|LessThan3~1, gA6_lab5, 1 +instance = comp, \inst1|LessThan3~3 , inst1|LessThan3~3, gA6_lab5, 1 +instance = comp, \inst1|LessThan3~5 , inst1|LessThan3~5, gA6_lab5, 1 +instance = comp, \inst1|LessThan3~7 , inst1|LessThan3~7, gA6_lab5, 1 +instance = comp, \inst1|LessThan3~9 , inst1|LessThan3~9, gA6_lab5, 1 +instance = comp, \inst1|LessThan3~10 , inst1|LessThan3~10, gA6_lab5, 1 +instance = comp, \inst1|p_win~3 , inst1|p_win~3, gA6_lab5, 1 +instance = comp, \inst1|LessThan2~1 , inst1|LessThan2~1, gA6_lab5, 1 +instance = comp, \inst1|LessThan2~3 , inst1|LessThan2~3, gA6_lab5, 1 +instance = comp, \inst1|LessThan2~5 , inst1|LessThan2~5, gA6_lab5, 1 +instance = comp, \inst1|LessThan2~7 , inst1|LessThan2~7, gA6_lab5, 1 +instance = comp, \inst1|LessThan2~9 , inst1|LessThan2~9, gA6_lab5, 1 +instance = comp, \inst1|LessThan2~10 , inst1|LessThan2~10, gA6_lab5, 1 +instance = comp, \inst1|p_win~0 , inst1|p_win~0, gA6_lab5, 1 +instance = comp, \inst1|p_win~4 , inst1|p_win~4, gA6_lab5, 1 +instance = comp, \inst1|p_win~5 , inst1|p_win~5, gA6_lab5, 1 +instance = comp, \inst1|p_win~7 , inst1|p_win~7, gA6_lab5, 1 +instance = comp, \inst1|player_wins~feeder , inst1|player_wins~feeder, gA6_lab5, 1 +instance = comp, \inst1|player_wins , inst1|player_wins, gA6_lab5, 1 +instance = comp, \inst1|d_win~0 , inst1|d_win~0, gA6_lab5, 1 +instance = comp, \inst1|dealer_wins , inst1|dealer_wins, gA6_lab5, 1 +instance = comp, \inst1|p_win~1 , inst1|p_win~1, gA6_lab5, 1 +instance = comp, \inst1|led_display1~6 , inst1|led_display1~6, gA6_lab5, 1 +instance = comp, \inst1|led_display1~4 , inst1|led_display1~4, gA6_lab5, 1 +instance = comp, \inst1|dealer:d_win , inst1|\dealer:d_win, gA6_lab5, 1 +instance = comp, \inst1|led_display1[0]~7 , inst1|led_display1[0]~7, gA6_lab5, 1 +instance = comp, \inst1|led_display1[0]~5 , inst1|led_display1[0]~5, gA6_lab5, 1 +instance = comp, \inst1|led_display1[0] , inst1|led_display1[0], gA6_lab5, 1 +instance = comp, \inst1|led_display3~3 , inst1|led_display3~3, gA6_lab5, 1 +instance = comp, \inst1|led_display3~2 , inst1|led_display3~2, gA6_lab5, 1 +instance = comp, \inst1|led_display3[1] , inst1|led_display3[1], gA6_lab5, 1 +instance = comp, \inst1|led_display4[3]~feeder , inst1|led_display4[3]~feeder, gA6_lab5, 1 +instance = comp, \inst1|led_display4[3] , inst1|led_display4[3], gA6_lab5, 1 +instance = comp, \hit~I , hit, gA6_lab5, 1 +instance = comp, \done~I , done, gA6_lab5, 1 +instance = comp, \player_wins~I , player_wins, gA6_lab5, 1 +instance = comp, \dealer_wins~I , dealer_wins, gA6_lab5, 1 +instance = comp, \led_display1[6]~I , led_display1[6], gA6_lab5, 1 +instance = comp, \led_display1[5]~I , led_display1[5], gA6_lab5, 1 +instance = comp, \led_display1[4]~I , led_display1[4], gA6_lab5, 1 +instance = comp, \led_display1[3]~I , led_display1[3], gA6_lab5, 1 +instance = comp, \led_display1[2]~I , led_display1[2], gA6_lab5, 1 +instance = comp, \led_display1[1]~I , led_display1[1], gA6_lab5, 1 +instance = comp, \led_display1[0]~I , led_display1[0], gA6_lab5, 1 +instance = comp, \led_display2[6]~I , led_display2[6], gA6_lab5, 1 +instance = comp, \led_display2[5]~I , led_display2[5], gA6_lab5, 1 +instance = comp, \led_display2[4]~I , led_display2[4], gA6_lab5, 1 +instance = comp, \led_display2[3]~I , led_display2[3], gA6_lab5, 1 +instance = comp, \led_display2[2]~I , led_display2[2], gA6_lab5, 1 +instance = comp, \led_display2[1]~I , led_display2[1], gA6_lab5, 1 +instance = comp, \led_display2[0]~I , led_display2[0], gA6_lab5, 1 +instance = comp, \led_display3[6]~I , led_display3[6], gA6_lab5, 1 +instance = comp, \led_display3[5]~I , led_display3[5], gA6_lab5, 1 +instance = comp, \led_display3[4]~I , led_display3[4], gA6_lab5, 1 +instance = comp, \led_display3[3]~I , led_display3[3], gA6_lab5, 1 +instance = comp, \led_display3[2]~I , led_display3[2], gA6_lab5, 1 +instance = comp, \led_display3[1]~I , led_display3[1], gA6_lab5, 1 +instance = comp, \led_display3[0]~I , led_display3[0], gA6_lab5, 1 +instance = comp, \led_display4[6]~I , led_display4[6], gA6_lab5, 1 +instance = comp, \led_display4[5]~I , led_display4[5], gA6_lab5, 1 +instance = comp, \led_display4[4]~I , led_display4[4], gA6_lab5, 1 +instance = comp, \led_display4[3]~I , led_display4[3], gA6_lab5, 1 +instance = comp, \led_display4[2]~I , led_display4[2], gA6_lab5, 1 +instance = comp, \led_display4[1]~I , led_display4[1], gA6_lab5, 1 +instance = comp, \led_display4[0]~I , led_display4[0], gA6_lab5, 1 +instance = comp, \state_out[1]~I , state_out[1], gA6_lab5, 1 +instance = comp, \state_out[0]~I , state_out[0], gA6_lab5, 1 +instance = comp, \sum_out[5]~I , sum_out[5], gA6_lab5, 1 +instance = comp, \sum_out[4]~I , sum_out[4], gA6_lab5, 1 +instance = comp, \sum_out[3]~I , sum_out[3], gA6_lab5, 1 +instance = comp, \sum_out[2]~I , sum_out[2], gA6_lab5, 1 +instance = comp, \sum_out[1]~I , sum_out[1], gA6_lab5, 1 +instance = comp, \sum_out[0]~I , sum_out[0], gA6_lab5, 1 diff --git a/lab5/simulation/modelsim/gA6_lab5_vhd.sdo b/lab5/simulation/modelsim/gA6_lab5_vhd.sdo new file mode 100644 index 0000000..05a94c1 --- /dev/null +++ b/lab5/simulation/modelsim/gA6_lab5_vhd.sdo @@ -0,0 +1,1373 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP2C20F484C7 Package FBGA484 +// + +// +// This SDF file should be used for ModelSim-Altera (VHDL) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "gA6_lab5") + (DATE "11/29/2017 18:38:50") + (VENDOR "Altera") + (PROGRAM "Quartus II 64-Bit") + (VERSION "Version 13.0.0 Build 156 04/24/2013 SJ Web Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|p_win\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (406:406:406) (406:406:406)) + (PORT datab (402:402:402) (402:402:402)) + (PORT datad (383:383:383) (383:383:383)) + (IOPATH dataa combout (544:544:544) (544:544:544)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (358:358:358) (358:358:358)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|p_win\~2\\) + (DELAY + (ABSOLUTE + (PORT dataa (5239:5239:5239) (5239:5239:5239)) + (PORT datab (5239:5239:5239) (5239:5239:5239)) + (PORT datac (4890:4890:4890) (4890:4890:4890)) + (PORT datad (5248:5248:5248) (5248:5248:5248)) + (IOPATH dataa combout (544:544:544) (544:544:544)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (319:319:319) (319:319:319)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst\|computer\:state\[1\]\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (5215:5215:5215) (5215:5215:5215)) + (PORT datab (4868:4868:4868) (4868:4868:4868)) + (PORT datac (5200:5200:5200) (5200:5200:5200)) + (PORT datad (5228:5228:5228) (5228:5228:5228)) + (IOPATH dataa combout (545:545:545) (545:545:545)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (278:278:278) (278:278:278)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\player_sum\[2\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (874:874:874) (874:874:874)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\player_sum\[0\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (884:884:884) (884:884:884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\turn\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (864:864:864) (864:864:864)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\clk\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (1026:1026:1026) (1026:1026:1026)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_clkctrl") + (INSTANCE \\clk\~clkctrl\\) + (DELAY + (ABSOLUTE + (PORT inclk[0] (238:238:238) (238:238:238)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_ena_reg") + (INSTANCE \\clk\~clkctrl\\.extena0_reg) + (DELAY + (ABSOLUTE + (PORT d (279:279:279) (279:279:279)) + (PORT clk (0:0:0) (0:0:0)) + (IOPATH (posedge clk) q (239:239:239) (239:239:239)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (55:55:55)) + (HOLD d (posedge clk) (110:110:110)) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\sum\[4\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (854:854:854) (854:854:854)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\sum\[5\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (864:864:864) (864:864:864)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst\|computer\:state\[0\]\~0\\) + (DELAY + (ABSOLUTE + (PORT datab (5185:5185:5185) (5185:5185:5185)) + (PORT datac (374:374:374) (374:374:374)) + (PORT datad (357:357:357) (357:357:357)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (177:177:177) (177:177:177)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst\|computer\:state\[0\]\~1\\) + (DELAY + (ABSOLUTE + (PORT dataa (483:483:483) (483:483:483)) + (PORT datab (5222:5222:5222) (5222:5222:5222)) + (PORT datac (375:375:375) (375:375:375)) + (PORT datad (285:285:285) (285:285:285)) + (IOPATH dataa combout (513:513:513) (513:513:513)) + (IOPATH datab combout (485:485:485) (485:485:485)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst\|computer\:state\[0\]\~2\\) + (DELAY + (ABSOLUTE + (PORT dataa (4856:4856:4856) (4856:4856:4856)) + (PORT datad (306:306:306) (306:306:306)) + (IOPATH dataa combout (513:513:513) (513:513:513)) + (IOPATH datac combout (358:358:358) (358:358:358)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\rst\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (1026:1026:1026) (1026:1026:1026)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_clkctrl") + (INSTANCE \\rst\~clkctrl\\) + (DELAY + (ABSOLUTE + (PORT inclk[0] (232:232:232) (232:232:232)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_ena_reg") + (INSTANCE \\rst\~clkctrl\\.extena0_reg) + (DELAY + (ABSOLUTE + (PORT d (279:279:279) (279:279:279)) + (PORT clk (0:0:0) (0:0:0)) + (IOPATH (posedge clk) q (239:239:239) (239:239:239)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (55:55:55)) + (HOLD d (posedge clk) (110:110:110)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE \\inst\|computer\:state\[0\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1581:1581:1581) (1581:1581:1581)) + (PORT datain (96:96:96) (96:96:96)) + (PORT aclr (1585:1585:1585) (1585:1585:1585)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + (IOPATH (posedge aclr) regout (243:243:243) (243:243:243)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst\|computer\:state\[1\]\~1\\) + (DELAY + (ABSOLUTE + (PORT datab (613:613:613) (613:613:613)) + (PORT datad (299:299:299) (299:299:299)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (358:358:358) (358:358:358)) + (IOPATH datad combout (177:177:177) (177:177:177)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE \\inst\|computer\:state\[1\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1581:1581:1581) (1581:1581:1581)) + (PORT datain (96:96:96) (96:96:96)) + (PORT aclr (1585:1585:1585) (1585:1585:1585)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + (IOPATH (posedge aclr) regout (243:243:243) (243:243:243)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst\|Mux0\~0\\) + (DELAY + (ABSOLUTE + (PORT datab (610:610:610) (610:610:610)) + (PORT datad (610:610:610) (610:610:610)) + (IOPATH datab combout (427:427:427) (427:427:427)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE \\inst\|hit\\) + (DELAY + (ABSOLUTE + (PORT clk (1581:1581:1581) (1581:1581:1581)) + (PORT datain (96:96:96) (96:96:96)) + (PORT aclr (1585:1585:1585) (1585:1585:1585)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + (IOPATH (posedge aclr) regout (243:243:243) (243:243:243)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst\|Mux1\~0\\) + (DELAY + (ABSOLUTE + (PORT datab (610:610:610) (610:610:610)) + (PORT datad (610:610:610) (610:610:610)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datad combout (177:177:177) (177:177:177)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE \\inst\|done\\) + (DELAY + (ABSOLUTE + (PORT clk (1581:1581:1581) (1581:1581:1581)) + (PORT datain (96:96:96) (96:96:96)) + (PORT aclr (1585:1585:1585) (1585:1585:1585)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + (IOPATH (posedge aclr) regout (243:243:243) (243:243:243)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\player_sum\[5\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (844:844:844) (844:844:844)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|p_win\~6\\) + (DELAY + (ABSOLUTE + (PORT dataa (554:554:554) (554:554:554)) + (PORT datac (5163:5163:5163) (5163:5163:5163)) + (IOPATH dataa combout (545:545:545) (545:545:545)) + (IOPATH datac combout (278:278:278) (278:278:278)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE \\inst\|sum_out\[5\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1572:1572:1572) (1572:1572:1572)) + (PORT sdata (5567:5567:5567) (5567:5567:5567)) + (PORT aclr (1576:1576:1576) (1576:1576:1576)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + (IOPATH (posedge aclr) regout (243:243:243) (243:243:243)) + ) + ) + (TIMINGCHECK + (HOLD sdata (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\player_sum\[4\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (874:874:874) (874:874:874)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\sum\[3\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (864:864:864) (864:864:864)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE \\inst\|sum_out\[3\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1572:1572:1572) (1572:1572:1572)) + (PORT sdata (5625:5625:5625) (5625:5625:5625)) + (PORT aclr (1576:1576:1576) (1576:1576:1576)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + (IOPATH (posedge aclr) regout (243:243:243) (243:243:243)) + ) + ) + (TIMINGCHECK + (HOLD sdata (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\sum\[2\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (864:864:864) (864:864:864)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE \\inst\|sum_out\[2\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1572:1572:1572) (1572:1572:1572)) + (PORT sdata (5627:5627:5627) (5627:5627:5627)) + (PORT aclr (1576:1576:1576) (1576:1576:1576)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + (IOPATH (posedge aclr) regout (243:243:243) (243:243:243)) + ) + ) + (TIMINGCHECK + (HOLD sdata (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\sum\[1\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (864:864:864) (864:864:864)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE \\inst\|sum_out\[1\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1572:1572:1572) (1572:1572:1572)) + (PORT sdata (5597:5597:5597) (5597:5597:5597)) + (PORT aclr (1576:1576:1576) (1576:1576:1576)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + (IOPATH (posedge aclr) regout (243:243:243) (243:243:243)) + ) + ) + (TIMINGCHECK + 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(80:80:80)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|LessThan2\~9\\) + (DELAY + (ABSOLUTE + (PORT dataa (402:402:402) (402:402:402)) + (PORT datab (4887:4887:4887) (4887:4887:4887)) + (IOPATH dataa cout (517:517:517) (517:517:517)) + (IOPATH datab cout (495:495:495) (495:495:495)) + (IOPATH cin cout (80:80:80) (80:80:80)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|LessThan2\~10\\) + (DELAY + (ABSOLUTE + (PORT datab (4851:4851:4851) (4851:4851:4851)) + (PORT datad (376:376:376) (376:376:376)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datad combout (178:178:178) (178:178:178)) + (IOPATH cin combout (458:458:458) (458:458:458)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|LessThan3\~1\\) + (DELAY + (ABSOLUTE + (PORT dataa (5246:5246:5246) (5246:5246:5246)) + (PORT datab (377:377:377) (377:377:377)) + (IOPATH dataa cout (517:517:517) (517:517:517)) + (IOPATH datab cout (495:495:495) (495:495:495)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|LessThan3\~3\\) + (DELAY + (ABSOLUTE + (PORT dataa (5784:5784:5784) (5784:5784:5784)) + (PORT datab (393:393:393) (393:393:393)) + (IOPATH dataa cout (517:517:517) (517:517:517)) + (IOPATH datab cout (495:495:495) (495:495:495)) + (IOPATH cin cout (80:80:80) (80:80:80)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|LessThan3\~5\\) + (DELAY + (ABSOLUTE + (PORT dataa (5237:5237:5237) (5237:5237:5237)) + (PORT datab (386:386:386) (386:386:386)) + (IOPATH dataa cout (517:517:517) (517:517:517)) + (IOPATH datab cout (495:495:495) (495:495:495)) + (IOPATH cin cout (80:80:80) (80:80:80)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|LessThan3\~7\\) + (DELAY + (ABSOLUTE + (PORT dataa (5265:5265:5265) (5265:5265:5265)) + (PORT datab (400:400:400) (400:400:400)) + (IOPATH dataa cout (517:517:517) (517:517:517)) + (IOPATH datab cout (495:495:495) (495:495:495)) + (IOPATH cin cout (80:80:80) (80:80:80)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|LessThan3\~9\\) + (DELAY + (ABSOLUTE + (PORT dataa (405:405:405) (405:405:405)) + (PORT datab (4886:4886:4886) (4886:4886:4886)) + (IOPATH dataa cout (517:517:517) (517:517:517)) + (IOPATH datab cout (495:495:495) (495:495:495)) + (IOPATH cin cout (80:80:80) (80:80:80)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|LessThan3\~10\\) + (DELAY + (ABSOLUTE + (PORT datab (4852:4852:4852) (4852:4852:4852)) + (PORT datad (378:378:378) (378:378:378)) + (IOPATH datab combout (491:491:491) (491:491:491)) + (IOPATH datad combout (178:178:178) (178:178:178)) + (IOPATH cin combout (458:458:458) (458:458:458)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|p_win\~1\\) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (550:550:550)) + (PORT datab (557:557:557) (557:557:557)) + (PORT datac (890:890:890) (890:890:890)) + (PORT datad (477:477:477) (477:477:477)) + (IOPATH dataa combout (545:545:545) (545:545:545)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (278:278:278) (278:278:278)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE \\inst\|sum_out\[4\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1572:1572:1572) (1572:1572:1572)) + (PORT sdata (5883:5883:5883) (5883:5883:5883)) + (PORT aclr (1576:1576:1576) (1576:1576:1576)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + (IOPATH (posedge aclr) regout (243:243:243) (243:243:243)) + ) + ) + (TIMINGCHECK + (HOLD sdata (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\player_sum\[1\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (884:884:884) (884:884:884)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|Equal0\~0\\) + (DELAY + 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(178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|Equal0\~2\\) + (DELAY + (ABSOLUTE + (PORT dataa (5538:5538:5538) (5538:5538:5538)) + (PORT datab (632:632:632) (632:632:632)) + (PORT datac (533:533:533) (533:533:533)) + (PORT datad (563:563:563) (563:563:563)) + (IOPATH dataa combout (512:512:512) (512:512:512)) + (IOPATH datab combout (491:491:491) (491:491:491)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|p_win\~3\\) + (DELAY + (ABSOLUTE + (PORT datac (5162:5162:5162) (5162:5162:5162)) + (PORT datad (475:475:475) (475:475:475)) + (IOPATH datac combout (278:278:278) (278:278:278)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|p_win\~4\\) + (DELAY + (ABSOLUTE + (PORT dataa (547:547:547) (547:547:547)) + (PORT datac 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(IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|led_display1\~4\\) + (DELAY + (ABSOLUTE + (PORT dataa (651:651:651) (651:651:651)) + (PORT datab (336:336:336) (336:336:336)) + (PORT datac (602:602:602) (602:602:602)) + (PORT datad (290:290:290) (290:290:290)) + (IOPATH dataa combout (542:542:542) (542:542:542)) + (IOPATH datab combout (491:491:491) (491:491:491)) + (IOPATH datac combout (322:322:322) (322:322:322)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE \\inst1\|dealer\:p_win\\) + (DELAY + (ABSOLUTE + (PORT clk (1573:1573:1573) (1573:1573:1573)) + (PORT sdata (723:723:723) (723:723:723)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + ) + ) + (TIMINGCHECK + (HOLD sdata (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|led_display1\[0\]\~7\\) + (DELAY + (ABSOLUTE + (PORT dataa (550:550:550) (550:550:550)) + (PORT datab (5166:5166:5166) (5166:5166:5166)) + (PORT datac (317:317:317) (317:317:317)) + (PORT datad (310:310:310) (310:310:310)) + (IOPATH dataa combout (545:545:545) (545:545:545)) + (IOPATH datab combout (521:521:521) (521:521:521)) + (IOPATH datac combout (278:278:278) (278:278:278)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|led_display1\[0\]\~5\\) + (DELAY + (ABSOLUTE + (PORT dataa (607:607:607) (607:607:607)) + (PORT datab (339:339:339) (339:339:339)) + (PORT datad (289:289:289) (289:289:289)) + (IOPATH dataa combout (545:545:545) (545:545:545)) + (IOPATH datab combout (491:491:491) (491:491:491)) + (IOPATH datac combout (358:358:358) (358:358:358)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE 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(ABSOLUTE + (PORT dataa (648:648:648) (648:648:648)) + (PORT datab (340:340:340) (340:340:340)) + (PORT datac (604:604:604) (604:604:604)) + (PORT datad (289:289:289) (289:289:289)) + (IOPATH dataa combout (545:545:545) (545:545:545)) + (IOPATH datab combout (491:491:491) (491:491:491)) + (IOPATH datac combout (319:319:319) (319:319:319)) + (IOPATH datad combout (178:178:178) (178:178:178)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE \\inst1\|led_display3\[1\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1573:1573:1573) (1573:1573:1573)) + (PORT datain (96:96:96) (96:96:96)) + (PORT ena (1023:1023:1023) (1023:1023:1023)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + (HOLD ena (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE \\inst1\|led_display4\[3\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1573:1573:1573) (1573:1573:1573)) + (PORT datain (96:96:96) (96:96:96)) + (PORT ena (1023:1023:1023) (1023:1023:1023)) + (IOPATH (posedge clk) regout (277:277:277) (277:277:277)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (286:286:286)) + (HOLD ena (posedge clk) (286:286:286)) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\hit\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (582:582:582) (582:582:582)) + (IOPATH datain padio (2840:2840:2840) (2840:2840:2840)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\done\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (582:582:582) (582:582:582)) + (IOPATH datain padio (2840:2840:2840) (2840:2840:2840)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\player_wins\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (1181:1181:1181) (1181:1181:1181)) + (IOPATH datain padio (2850:2850:2850) (2850:2850:2850)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\dealer_wins\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (1190:1190:1190) (1190:1190:1190)) + (IOPATH datain padio (2820:2820:2820) (2820:2820:2820)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display1\[6\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (1516:1516:1516) (1516:1516:1516)) + (IOPATH datain padio (2840:2840:2840) (2840:2840:2840)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display1\[5\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH datain padio (2986:2986:2986) (2986:2986:2986)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display1\[4\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH datain padio (3016:3016:3016) (3016:3016:3016)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display1\[3\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (1192:1192:1192) (1192:1192:1192)) + (IOPATH datain padio (2840:2840:2840) (2840:2840:2840)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display1\[2\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (1165:1165:1165) (1165:1165:1165)) + (IOPATH datain padio (3016:3016:3016) (3016:3016:3016)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display1\[1\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (1516:1516:1516) (1516:1516:1516)) + (IOPATH datain padio (2810:2810:2810) (2810:2810:2810)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display1\[0\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (1192:1192:1192) (1192:1192:1192)) + (IOPATH datain padio (2810:2810:2810) (2810:2810:2810)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display2\[6\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH datain padio (3006:3006:3006) (3006:3006:3006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display2\[5\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (1165:1165:1165) (1165:1165:1165)) + (IOPATH datain padio (3016:3016:3016) (3016:3016:3016)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display2\[4\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH datain padio (3016:3016:3016) (3016:3016:3016)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display2\[3\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH datain padio (2996:2996:2996) (2996:2996:2996)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display2\[2\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH datain padio (3006:3006:3006) (3006:3006:3006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display2\[1\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH datain padio (3016:3016:3016) (3016:3016:3016)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display2\[0\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (1191:1191:1191) (1191:1191:1191)) + (IOPATH datain padio (2820:2820:2820) (2820:2820:2820)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display3\[6\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (1845:1845:1845) (1845:1845:1845)) + (IOPATH datain padio (2840:2840:2840) (2840:2840:2840)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display3\[5\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (1845:1845:1845) (1845:1845:1845)) + (IOPATH datain padio (2850:2850:2850) (2850:2850:2850)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display3\[4\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH datain padio (3006:3006:3006) (3006:3006:3006)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display3\[3\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (1845:1845:1845) (1845:1845:1845)) + (IOPATH datain padio (2840:2840:2840) (2840:2840:2840)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display3\[2\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH datain padio (2976:2976:2976) (2976:2976:2976)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display3\[1\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (1165:1165:1165) (1165:1165:1165)) + (IOPATH datain padio (3016:3016:3016) (3016:3016:3016)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display3\[0\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (1165:1165:1165) (1165:1165:1165)) + (IOPATH datain padio (3016:3016:3016) (3016:3016:3016)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display4\[6\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (1509:1509:1509) (1509:1509:1509)) + (IOPATH datain padio (2830:2830:2830) (2830:2830:2830)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display4\[5\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH datain padio (2986:2986:2986) (2986:2986:2986)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display4\[4\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH datain padio (3016:3016:3016) (3016:3016:3016)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display4\[3\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (1201:1201:1201) (1201:1201:1201)) + (IOPATH datain padio (2820:2820:2820) (2820:2820:2820)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display4\[2\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (1201:1201:1201) (1201:1201:1201)) + (IOPATH datain padio (2830:2830:2830) (2830:2830:2830)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display4\[1\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (1201:1201:1201) (1201:1201:1201)) + (IOPATH datain padio (2820:2820:2820) (2820:2820:2820)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display4\[0\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (1516:1516:1516) (1516:1516:1516)) + (IOPATH datain padio (2810:2810:2810) (2810:2810:2810)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\sum_out\[5\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (598:598:598) (598:598:598)) + (IOPATH datain padio (2820:2820:2820) (2820:2820:2820)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\sum_out\[4\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (603:603:603) (603:603:603)) + (IOPATH datain padio (2850:2850:2850) (2850:2850:2850)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\sum_out\[3\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (949:949:949) (949:949:949)) + (IOPATH datain padio (2820:2820:2820) (2820:2820:2820)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\sum_out\[2\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (957:957:957) (957:957:957)) + (IOPATH datain padio (2840:2840:2840) (2840:2840:2840)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\sum_out\[1\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (932:932:932) (932:932:932)) + (IOPATH datain padio (2850:2850:2850) (2850:2850:2850)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\sum_out\[0\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (935:935:935) (935:935:935)) + (IOPATH datain padio (2830:2830:2830) (2830:2830:2830)) + ) + ) + ) +) diff --git a/lab5/simulation/modelsim/gA6_lab5_vhd_fast.sdo b/lab5/simulation/modelsim/gA6_lab5_vhd_fast.sdo new file mode 100644 index 0000000..22240eb --- /dev/null +++ b/lab5/simulation/modelsim/gA6_lab5_vhd_fast.sdo @@ -0,0 +1,1373 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + + +// +// Device: Altera EP2C20F484C7 Package FBGA484 +// + +// +// This SDF file should be used for ModelSim-Altera (VHDL) only +// + +(DELAYFILE + (SDFVERSION "2.1") + (DESIGN "gA6_lab5") + (DATE "11/29/2017 18:38:50") + (VENDOR "Altera") + (PROGRAM "Quartus II 64-Bit") + (VERSION "Version 13.0.0 Build 156 04/24/2013 SJ Web Edition") + (DIVIDER .) + (TIMESCALE 1 ps) + + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|p_win\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (171:171:171) (171:171:171)) + (PORT datab (174:174:174) (174:174:174)) + (PORT datad (164:164:164) (164:164:164)) + (IOPATH dataa combout (187:187:187) (187:187:187)) + (IOPATH datab combout (178:178:178) (178:178:178)) + (IOPATH datac combout (184:184:184) (184:184:184)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|p_win\~2\\) + (DELAY + (ABSOLUTE + (PORT dataa (2865:2865:2865) (2865:2865:2865)) + (PORT datab (2878:2878:2878) (2878:2878:2878)) + (PORT datac (2736:2736:2736) (2736:2736:2736)) + (PORT datad (2882:2882:2882) (2882:2882:2882)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (133:133:133) (133:133:133)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst\|computer\:state\[1\]\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2853:2853:2853) (2853:2853:2853)) + (PORT datab (2721:2721:2721) (2721:2721:2721)) + (PORT datac (2847:2847:2847) (2847:2847:2847)) + (PORT datad (2869:2869:2869) (2869:2869:2869)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\player_sum\[2\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (474:474:474) (474:474:474)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\player_sum\[0\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (484:484:484) (484:484:484)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\turn\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (464:464:464) (464:464:464)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\clk\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (571:571:571) (571:571:571)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_clkctrl") + (INSTANCE \\clk\~clkctrl\\) + (DELAY + (ABSOLUTE + (PORT inclk[0] (186:186:186) (186:186:186)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_ena_reg") + (INSTANCE \\clk\~clkctrl\\.extena0_reg) + (DELAY + (ABSOLUTE + (PORT d (260:260:260) (260:260:260)) + (PORT clk (0:0:0) (0:0:0)) + (IOPATH (posedge clk) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (33:33:33)) + (HOLD d (posedge clk) (56:56:56)) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\sum\[4\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (454:454:454) (454:454:454)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\sum\[5\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (464:464:464) (464:464:464)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst\|computer\:state\[0\]\~0\\) + (DELAY + (ABSOLUTE + (PORT datab (2838:2838:2838) (2838:2838:2838)) + (PORT datac (157:157:157) (157:157:157)) + (PORT datad (149:149:149) (149:149:149)) + (IOPATH datab combout (180:180:180) (180:180:180)) + (IOPATH datac combout (110:110:110) (110:110:110)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst\|computer\:state\[0\]\~1\\) + (DELAY + (ABSOLUTE + (PORT dataa (183:183:183) (183:183:183)) + (PORT datab (2868:2868:2868) (2868:2868:2868)) + (PORT datac (160:160:160) (160:160:160)) + (PORT datad (102:102:102) (102:102:102)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst\|computer\:state\[0\]\~2\\) + (DELAY + (ABSOLUTE + (PORT dataa (2711:2711:2711) (2711:2711:2711)) + (PORT datad (115:115:115) (115:115:115)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datac combout (184:184:184) (184:184:184)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\rst\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (571:571:571) (571:571:571)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_clkctrl") + (INSTANCE \\rst\~clkctrl\\) + (DELAY + (ABSOLUTE + (PORT inclk[0] (181:181:181) (181:181:181)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_ena_reg") + (INSTANCE \\rst\~clkctrl\\.extena0_reg) + (DELAY + (ABSOLUTE + (PORT d (260:260:260) (260:260:260)) + (PORT clk (0:0:0) (0:0:0)) + (IOPATH (posedge clk) q (173:173:173) (173:173:173)) + ) + ) + (TIMINGCHECK + (SETUP d (posedge clk) (33:33:33)) + (HOLD d (posedge clk) (56:56:56)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE \\inst\|computer\:state\[0\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1023:1023:1023) (1023:1023:1023)) + (PORT datain (42:42:42) (42:42:42)) + (PORT aclr (1013:1013:1013) (1013:1013:1013)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + (IOPATH (posedge aclr) regout (133:133:133) (133:133:133)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst\|computer\:state\[1\]\~1\\) + (DELAY + (ABSOLUTE + (PORT datab (247:247:247) (247:247:247)) + (PORT datad (108:108:108) (108:108:108)) + (IOPATH datab combout (180:180:180) (180:180:180)) + (IOPATH datac combout (184:184:184) (184:184:184)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE \\inst\|computer\:state\[1\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1023:1023:1023) (1023:1023:1023)) + (PORT datain (42:42:42) (42:42:42)) + (PORT aclr (1013:1013:1013) (1013:1013:1013)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + (IOPATH (posedge aclr) regout (133:133:133) (133:133:133)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst\|Mux0\~0\\) + (DELAY + (ABSOLUTE + (PORT datab (246:246:246) (246:246:246)) + (PORT datad (243:243:243) (243:243:243)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE \\inst\|hit\\) + (DELAY + (ABSOLUTE + (PORT clk (1023:1023:1023) (1023:1023:1023)) + (PORT datain (42:42:42) (42:42:42)) + (PORT aclr (1013:1013:1013) (1013:1013:1013)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + (IOPATH (posedge aclr) regout (133:133:133) (133:133:133)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst\|Mux1\~0\\) + (DELAY + (ABSOLUTE + (PORT datab (246:246:246) (246:246:246)) + (PORT datad (242:242:242) (242:242:242)) + (IOPATH datab combout (180:180:180) (180:180:180)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE \\inst\|done\\) + (DELAY + (ABSOLUTE + (PORT clk (1023:1023:1023) (1023:1023:1023)) + (PORT datain (42:42:42) (42:42:42)) + (PORT aclr (1013:1013:1013) (1013:1013:1013)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + (IOPATH (posedge aclr) regout (133:133:133) (133:133:133)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\player_sum\[5\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (444:444:444) (444:444:444)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|p_win\~6\\) + (DELAY + (ABSOLUTE + (PORT dataa (224:224:224) (224:224:224)) + (PORT datac (2836:2836:2836) (2836:2836:2836)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datac combout (107:107:107) (107:107:107)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE \\inst\|sum_out\[5\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1017:1017:1017)) + (PORT sdata (3028:3028:3028) (3028:3028:3028)) + (PORT aclr (1007:1007:1007) (1007:1007:1007)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + (IOPATH (posedge aclr) regout (133:133:133) (133:133:133)) + ) + ) + (TIMINGCHECK + (HOLD sdata (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\player_sum\[4\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (474:474:474) (474:474:474)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\sum\[3\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (464:464:464) (464:464:464)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE \\inst\|sum_out\[3\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1017:1017:1017)) + (PORT sdata (3043:3043:3043) (3043:3043:3043)) + (PORT aclr (1007:1007:1007) (1007:1007:1007)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + (IOPATH (posedge aclr) regout (133:133:133) (133:133:133)) + ) + ) + (TIMINGCHECK + (HOLD sdata (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\sum\[2\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (464:464:464) (464:464:464)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE \\inst\|sum_out\[2\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1017:1017:1017)) + (PORT sdata (3047:3047:3047) (3047:3047:3047)) + (PORT aclr (1007:1007:1007) (1007:1007:1007)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + (IOPATH (posedge aclr) regout (133:133:133) (133:133:133)) + ) + ) + (TIMINGCHECK + (HOLD sdata (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\sum\[1\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (464:464:464) (464:464:464)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE \\inst\|sum_out\[1\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1017:1017:1017)) + (PORT sdata (3021:3021:3021) (3021:3021:3021)) + (PORT aclr (1007:1007:1007) (1007:1007:1007)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + (IOPATH (posedge aclr) regout (133:133:133) (133:133:133)) + ) + ) + (TIMINGCHECK + (HOLD sdata (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\sum\[0\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (444:444:444) (444:444:444)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE \\inst\|sum_out\[0\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1017:1017:1017)) + (PORT sdata (3040:3040:3040) (3040:3040:3040)) + (PORT aclr (1007:1007:1007) (1007:1007:1007)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + (IOPATH (posedge aclr) regout (133:133:133) (133:133:133)) + ) + ) + (TIMINGCHECK + (HOLD sdata (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|LessThan2\~1\\) + (DELAY + (ABSOLUTE + (PORT dataa (2873:2873:2873) (2873:2873:2873)) + (PORT datab (164:164:164) (164:164:164)) + (IOPATH dataa cout (150:150:150) (150:150:150)) + (IOPATH datab cout (143:143:143) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|LessThan2\~3\\) + (DELAY + (ABSOLUTE + (PORT dataa (3078:3078:3078) (3078:3078:3078)) + (PORT datab (173:173:173) (173:173:173)) + (IOPATH dataa cout (150:150:150) (150:150:150)) + (IOPATH datab cout (143:143:143) (143:143:143)) + (IOPATH cin cout (35:35:35) (35:35:35)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|LessThan2\~5\\) + (DELAY + (ABSOLUTE + (PORT dataa (2866:2866:2866) (2866:2866:2866)) + (PORT datab (163:163:163) (163:163:163)) + (IOPATH dataa cout (150:150:150) (150:150:150)) + (IOPATH datab cout (143:143:143) (143:143:143)) + (IOPATH cin cout (35:35:35) (35:35:35)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|LessThan2\~7\\) + (DELAY + (ABSOLUTE + (PORT dataa (2891:2891:2891) (2891:2891:2891)) + (PORT datab (168:168:168) (168:168:168)) + (IOPATH dataa cout (150:150:150) (150:150:150)) + (IOPATH datab cout (143:143:143) (143:143:143)) + (IOPATH cin cout (35:35:35) (35:35:35)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|LessThan2\~9\\) + (DELAY + (ABSOLUTE + (PORT dataa (166:166:166) (166:166:166)) + (PORT datab (2738:2738:2738) (2738:2738:2738)) + (IOPATH dataa cout (150:150:150) (150:150:150)) + (IOPATH datab cout (143:143:143) (143:143:143)) + (IOPATH cin cout (35:35:35) (35:35:35)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|LessThan2\~10\\) + (DELAY + (ABSOLUTE + (PORT datab (2713:2713:2713) (2713:2713:2713)) + (PORT datad (159:159:159) (159:159:159)) + (IOPATH datab combout (180:180:180) (180:180:180)) + (IOPATH datad combout (59:59:59) (59:59:59)) + (IOPATH cin combout (170:170:170) (170:170:170)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|LessThan3\~1\\) + (DELAY + (ABSOLUTE + (PORT dataa (2879:2879:2879) (2879:2879:2879)) + (PORT datab (159:159:159) (159:159:159)) + (IOPATH dataa cout (150:150:150) (150:150:150)) + (IOPATH datab cout (143:143:143) (143:143:143)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|LessThan3\~3\\) + (DELAY + (ABSOLUTE + (PORT dataa (3076:3076:3076) (3076:3076:3076)) + (PORT datab (168:168:168) (168:168:168)) + (IOPATH dataa cout (150:150:150) (150:150:150)) + (IOPATH datab cout (143:143:143) (143:143:143)) + (IOPATH cin cout (35:35:35) (35:35:35)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|LessThan3\~5\\) + (DELAY + (ABSOLUTE + (PORT dataa (2862:2862:2862) (2862:2862:2862)) + (PORT datab (165:165:165) (165:165:165)) + (IOPATH dataa cout (150:150:150) (150:150:150)) + (IOPATH datab cout (143:143:143) (143:143:143)) + (IOPATH cin cout (35:35:35) (35:35:35)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|LessThan3\~7\\) + (DELAY + (ABSOLUTE + (PORT dataa (2886:2886:2886) (2886:2886:2886)) + (PORT datab (173:173:173) (173:173:173)) + (IOPATH dataa cout (150:150:150) (150:150:150)) + (IOPATH datab cout (143:143:143) (143:143:143)) + (IOPATH cin cout (35:35:35) (35:35:35)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|LessThan3\~9\\) + (DELAY + (ABSOLUTE + (PORT dataa (169:169:169) (169:169:169)) + (PORT datab (2736:2736:2736) (2736:2736:2736)) + (IOPATH dataa cout (150:150:150) (150:150:150)) + (IOPATH datab cout (143:143:143) (143:143:143)) + (IOPATH cin cout (35:35:35) (35:35:35)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|LessThan3\~10\\) + (DELAY + (ABSOLUTE + (PORT datab (2713:2713:2713) (2713:2713:2713)) + (PORT datad (161:161:161) (161:161:161)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datad combout (59:59:59) (59:59:59)) + (IOPATH cin combout (170:170:170) (170:170:170)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|p_win\~1\\) + (DELAY + (ABSOLUTE + (PORT dataa (198:198:198) (198:198:198)) + (PORT datab (203:203:203) (203:203:203)) + (PORT datac (345:345:345) (345:345:345)) + (PORT datad (182:182:182) (182:182:182)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (79:79:79) (79:79:79)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE \\inst\|sum_out\[4\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1017:1017:1017) (1017:1017:1017)) + (PORT sdata (3132:3132:3132) (3132:3132:3132)) + (PORT aclr (1007:1007:1007) (1007:1007:1007)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + (IOPATH (posedge aclr) regout (133:133:133) (133:133:133)) + ) + ) + (TIMINGCHECK + (HOLD sdata (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\player_sum\[1\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (484:484:484) (484:484:484)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|Equal0\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (2879:2879:2879) (2879:2879:2879)) + (PORT datab (2880:2880:2880) (2880:2880:2880)) + (PORT datad (164:164:164) (164:164:164)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (180:180:180) (180:180:180)) + (IOPATH datac combout (184:184:184) (184:184:184)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\player_sum\[3\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH padio combout (474:474:474) (474:474:474)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|Equal0\~1\\) + (DELAY + (ABSOLUTE + (PORT dataa (2865:2865:2865) (2865:2865:2865)) + (PORT datab (2957:2957:2957) (2957:2957:2957)) + (PORT datad (167:167:167) (167:167:167)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (180:180:180) (180:180:180)) + (IOPATH datac combout (184:184:184) (184:184:184)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|Equal0\~2\\) + (DELAY + (ABSOLUTE + (PORT dataa (2976:2976:2976) (2976:2976:2976)) + (PORT datab (252:252:252) (252:252:252)) + (PORT datac (191:191:191) (191:191:191)) + (PORT datad (207:207:207) (207:207:207)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (133:133:133) (133:133:133)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|p_win\~3\\) + (DELAY + (ABSOLUTE + (PORT datac (2835:2835:2835) (2835:2835:2835)) + (PORT datad (181:181:181) (181:181:181)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|p_win\~4\\) + (DELAY + (ABSOLUTE + (PORT dataa (196:196:196) (196:196:196)) + (PORT datac (347:347:347) (347:347:347)) + (PORT datad (205:205:205) (205:205:205)) + (IOPATH dataa combout (187:187:187) (187:187:187)) + (IOPATH datac combout (110:110:110) (110:110:110)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|p_win\~5\\) + (DELAY + (ABSOLUTE + (PORT dataa (225:225:225) (225:225:225)) + (PORT datab (109:109:109) (109:109:109)) + (PORT datac (109:109:109) (109:109:109)) + (PORT datad (112:112:112) (112:112:112)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (79:79:79) (79:79:79)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|p_win\~7\\) + (DELAY + (ABSOLUTE + (PORT dataa (264:264:264) (264:264:264)) + (PORT datab (199:199:199) (199:199:199)) + (PORT datac (115:115:115) (115:115:115)) + (PORT datad (131:131:131) (131:131:131)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (110:110:110) (110:110:110)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE \\inst1\|player_wins\\) + (DELAY + (ABSOLUTE + (PORT clk (1018:1018:1018) (1018:1018:1018)) + (PORT sdata (297:297:297) (297:297:297)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + ) + ) + (TIMINGCHECK + (HOLD sdata (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE \\inst1\|dealer\:d_win\\) + (DELAY + (ABSOLUTE + (PORT clk (1018:1018:1018) (1018:1018:1018)) + (PORT datain (42:42:42) (42:42:42)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|d_win\~0\\) + (DELAY + (ABSOLUTE + (PORT dataa (120:120:120) (120:120:120)) + (PORT datab (195:195:195) (195:195:195)) + (PORT datad (123:123:123) (123:123:123)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (178:178:178) (178:178:178)) + (IOPATH datac combout (184:184:184) (184:184:184)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE \\inst1\|dealer_wins\\) + (DELAY + (ABSOLUTE + (PORT clk (1018:1018:1018) (1018:1018:1018)) + (PORT sdata (295:295:295) (295:295:295)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + ) + ) + (TIMINGCHECK + (HOLD sdata (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|led_display1\~6\\) + (DELAY + (ABSOLUTE + (PORT dataa (225:225:225) (225:225:225)) + (PORT datab (2838:2838:2838) (2838:2838:2838)) + (PORT datac (200:200:200) (200:200:200)) + (PORT datad (301:301:301) (301:301:301)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (79:79:79) (79:79:79)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|led_display1\~4\\) + (DELAY + (ABSOLUTE + (PORT dataa (268:268:268) (268:268:268)) + (PORT datab (129:129:129) (129:129:129)) + (PORT datac (239:239:239) (239:239:239)) + (PORT datad (105:105:105) (105:105:105)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE \\inst1\|dealer\:p_win\\) + (DELAY + (ABSOLUTE + (PORT clk (1018:1018:1018) (1018:1018:1018)) + (PORT sdata (299:299:299) (299:299:299)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + ) + ) + (TIMINGCHECK + (HOLD sdata (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|led_display1\[0\]\~7\\) + (DELAY + (ABSOLUTE + (PORT dataa (221:221:221) (221:221:221)) + (PORT datab (2834:2834:2834) (2834:2834:2834)) + (PORT datac (115:115:115) (115:115:115)) + (PORT datad (113:113:113) (113:113:113)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|led_display1\[0\]\~5\\) + (DELAY + (ABSOLUTE + (PORT dataa (239:239:239) (239:239:239)) + (PORT datab (132:132:132) (132:132:132)) + (PORT datad (104:104:104) (104:104:104)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (184:184:184) (184:184:184)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE \\inst1\|led_display1\[0\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1018:1018:1018) (1018:1018:1018)) + (PORT datain (42:42:42) (42:42:42)) + (PORT ena (475:475:475) (475:475:475)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + (HOLD ena (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|led_display3\~3\\) + (DELAY + (ABSOLUTE + (PORT dataa (222:222:222) (222:222:222)) + (PORT datab (2830:2830:2830) (2830:2830:2830)) + (PORT datac (203:203:203) (203:203:203)) + (PORT datad (294:294:294) (294:294:294)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (79:79:79) (79:79:79)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_comb") + (INSTANCE \\inst1\|led_display3\~2\\) + (DELAY + (ABSOLUTE + (PORT dataa (264:264:264) (264:264:264)) + (PORT datab (133:133:133) (133:133:133)) + (PORT datac (241:241:241) (241:241:241)) + (PORT datad (103:103:103) (103:103:103)) + (IOPATH dataa combout (180:180:180) (180:180:180)) + (IOPATH datab combout (175:175:175) (175:175:175)) + (IOPATH datac combout (107:107:107) (107:107:107)) + (IOPATH datad combout (59:59:59) (59:59:59)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE \\inst1\|led_display3\[1\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1018:1018:1018) (1018:1018:1018)) + (PORT datain (42:42:42) (42:42:42)) + (PORT ena (475:475:475) (475:475:475)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + (HOLD ena (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_lcell_ff") + (INSTANCE \\inst1\|led_display4\[3\]\\) + (DELAY + (ABSOLUTE + (PORT clk (1018:1018:1018) (1018:1018:1018)) + (PORT datain (42:42:42) (42:42:42)) + (PORT ena (475:475:475) (475:475:475)) + (IOPATH (posedge clk) regout (141:141:141) (141:141:141)) + ) + ) + (TIMINGCHECK + (HOLD datain (posedge clk) (152:152:152)) + (HOLD ena (posedge clk) (152:152:152)) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\hit\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (260:260:260) (260:260:260)) + (IOPATH datain padio (1408:1408:1408) (1408:1408:1408)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\done\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (260:260:260) (260:260:260)) + (IOPATH datain padio (1408:1408:1408) (1408:1408:1408)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\player_wins\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (489:489:489) (489:489:489)) + (IOPATH datain padio (1418:1418:1418) (1418:1418:1418)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\dealer_wins\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (489:489:489) (489:489:489)) + (IOPATH datain padio (1388:1388:1388) (1388:1388:1388)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display1\[6\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (618:618:618) (618:618:618)) + (IOPATH datain padio (1408:1408:1408) (1408:1408:1408)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display1\[5\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH datain padio (1513:1513:1513) (1513:1513:1513)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display1\[4\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH datain padio (1543:1543:1543) (1543:1543:1543)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display1\[3\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (498:498:498) (498:498:498)) + (IOPATH datain padio (1408:1408:1408) (1408:1408:1408)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display1\[2\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (491:491:491) (491:491:491)) + (IOPATH datain padio (1543:1543:1543) (1543:1543:1543)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display1\[1\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (618:618:618) (618:618:618)) + (IOPATH datain padio (1378:1378:1378) (1378:1378:1378)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display1\[0\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (498:498:498) (498:498:498)) + (IOPATH datain padio (1378:1378:1378) (1378:1378:1378)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display2\[6\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH datain padio (1533:1533:1533) (1533:1533:1533)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display2\[5\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (491:491:491) (491:491:491)) + (IOPATH datain padio (1543:1543:1543) (1543:1543:1543)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display2\[4\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH datain padio (1543:1543:1543) (1543:1543:1543)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display2\[3\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH datain padio (1523:1523:1523) (1523:1523:1523)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display2\[2\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH datain padio (1533:1533:1533) (1533:1533:1533)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display2\[1\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH datain padio (1543:1543:1543) (1543:1543:1543)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display2\[0\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (492:492:492) (492:492:492)) + (IOPATH datain padio (1388:1388:1388) (1388:1388:1388)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display3\[6\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (737:737:737) (737:737:737)) + (IOPATH datain padio (1408:1408:1408) (1408:1408:1408)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display3\[5\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (737:737:737) (737:737:737)) + (IOPATH datain padio (1418:1418:1418) (1418:1418:1418)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display3\[4\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH datain padio (1533:1533:1533) (1533:1533:1533)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display3\[3\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (737:737:737) (737:737:737)) + (IOPATH datain padio (1408:1408:1408) (1408:1408:1408)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display3\[2\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH datain padio (1503:1503:1503) (1503:1503:1503)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display3\[1\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (491:491:491) (491:491:491)) + (IOPATH datain padio (1543:1543:1543) (1543:1543:1543)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display3\[0\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (491:491:491) (491:491:491)) + (IOPATH datain padio (1543:1543:1543) (1543:1543:1543)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display4\[6\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (613:613:613) (613:613:613)) + (IOPATH datain padio (1398:1398:1398) (1398:1398:1398)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display4\[5\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH datain padio (1513:1513:1513) (1513:1513:1513)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display4\[4\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (IOPATH datain padio (1543:1543:1543) (1543:1543:1543)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display4\[3\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (500:500:500) (500:500:500)) + (IOPATH datain padio (1388:1388:1388) (1388:1388:1388)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display4\[2\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (500:500:500) (500:500:500)) + (IOPATH datain padio (1398:1398:1398) (1398:1398:1398)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display4\[1\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (500:500:500) (500:500:500)) + (IOPATH datain padio (1388:1388:1388) (1388:1388:1388)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\led_display4\[0\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (618:618:618) (618:618:618)) + (IOPATH datain padio (1378:1378:1378) (1378:1378:1378)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\sum_out\[5\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (265:265:265) (265:265:265)) + (IOPATH datain padio (1388:1388:1388) (1388:1388:1388)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\sum_out\[4\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (267:267:267) (267:267:267)) + (IOPATH datain padio (1418:1418:1418) (1418:1418:1418)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\sum_out\[3\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (407:407:407) (407:407:407)) + (IOPATH datain padio (1388:1388:1388) (1388:1388:1388)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\sum_out\[2\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (414:414:414) (414:414:414)) + (IOPATH datain padio (1408:1408:1408) (1408:1408:1408)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\sum_out\[1\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (390:390:390) (390:390:390)) + (IOPATH datain padio (1418:1418:1418) (1418:1418:1418)) + ) + ) + ) + (CELL + (CELLTYPE "cycloneii_asynch_io") + (INSTANCE \\sum_out\[0\]\~I\\.asynch_inst) + (DELAY + (ABSOLUTE + (PORT datain (392:392:392) (392:392:392)) + (IOPATH datain padio (1398:1398:1398) (1398:1398:1398)) + ) + ) + ) +) diff --git a/lab5/simulation/qsim/gA6_lab5.do b/lab5/simulation/qsim/gA6_lab5.do new file mode 100644 index 0000000..01e2df6 --- /dev/null +++ b/lab5/simulation/qsim/gA6_lab5.do @@ -0,0 +1,10 @@ +onerror {quit -f} +vlib work +vlog -work work gA6_lab5.vo +vlog -work work gA6_lab5.vt +vsim -novopt -c -t 1ps -L cycloneii_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate work.gA6_lab5_vlg_vec_tst +vcd file -direction gA6_lab5.msim.vcd +vcd add -internal gA6_lab5_vlg_vec_tst/* +vcd add -internal gA6_lab5_vlg_vec_tst/i1/* +add wave /* +run -all diff --git a/lab5/simulation/qsim/gA6_lab5.msim.vcd b/lab5/simulation/qsim/gA6_lab5.msim.vcd new file mode 100644 index 0000000..8733e4e --- /dev/null +++ b/lab5/simulation/qsim/gA6_lab5.msim.vcd @@ -0,0 +1,1320 @@ +$comment + File created using the following command: + vcd file gA6_lab5.msim.vcd -direction +$end +$date + Wed Nov 29 18:55:08 2017 +$end +$version + ModelSim Version 10.1d +$end +$timescale + 1ps +$end +$scope module gA6_lab5_vlg_vec_tst $end +$var reg 1 ! clk $end +$var reg 6 " player_sum [5:0] $end +$var reg 1 # rst $end +$var reg 6 $ sum [5:0] $end +$var reg 1 % turn $end +$var wire 1 & dealer_wins $end +$var wire 1 ' done $end +$var wire 1 ( hit $end +$var wire 1 ) led_display1 [6] $end +$var wire 1 * led_display1 [5] $end +$var wire 1 + led_display1 [4] $end +$var wire 1 , led_display1 [3] $end +$var wire 1 - led_display1 [2] $end +$var wire 1 . led_display1 [1] $end +$var wire 1 / led_display1 [0] $end +$var wire 1 0 led_display2 [6] $end +$var wire 1 1 led_display2 [5] $end +$var wire 1 2 led_display2 [4] $end +$var wire 1 3 led_display2 [3] $end +$var wire 1 4 led_display2 [2] $end +$var wire 1 5 led_display2 [1] $end +$var wire 1 6 led_display2 [0] $end +$var wire 1 7 led_display3 [6] $end +$var wire 1 8 led_display3 [5] $end +$var wire 1 9 led_display3 [4] $end +$var wire 1 : led_display3 [3] $end +$var wire 1 ; led_display3 [2] $end +$var wire 1 < led_display3 [1] $end +$var wire 1 = led_display3 [0] $end +$var wire 1 > led_display4 [6] $end +$var wire 1 ? led_display4 [5] $end +$var wire 1 @ led_display4 [4] $end +$var wire 1 A led_display4 [3] $end +$var wire 1 B led_display4 [2] $end +$var wire 1 C led_display4 [1] $end +$var wire 1 D led_display4 [0] $end +$var wire 1 E player_wins $end +$var wire 1 F state_out [1] $end +$var wire 1 G state_out [0] $end +$var wire 1 H sum_out [5] $end +$var wire 1 I sum_out [4] $end +$var wire 1 J sum_out [3] $end +$var wire 1 K sum_out [2] $end +$var wire 1 L sum_out [1] $end +$var wire 1 M sum_out [0] $end +$var wire 1 N sampler $end +$scope module i1 $end +$var wire 1 O gnd $end +$var wire 1 P vcc $end +$var wire 1 Q unknown $end +$var tri1 1 R devclrn $end +$var tri1 1 S devpor $end +$var tri1 1 T devoe $end +$var wire 1 U turn~combout $end +$var wire 1 V clk~combout $end +$var wire 1 W clk~clkctrl_outclk $end +$var wire 1 X inst|LessThan0~0_combout $end +$var wire 1 Y inst|LessThan0~1_combout $end +$var wire 1 Z inst|computer:state[0]~0_combout $end +$var wire 1 [ rst~combout $end +$var wire 1 \ rst~clkctrl_outclk $end +$var wire 1 ] inst|computer:state[0]~regout $end +$var wire 1 ^ inst|computer:state[1]~0_combout $end +$var wire 1 _ inst|computer:state[1]~regout $end +$var wire 1 ` inst|Mux0~0_combout $end +$var wire 1 a inst|hit~regout $end +$var wire 1 b inst|Mux1~0_combout $end +$var wire 1 c inst|done~regout $end +$var wire 1 d inst1|p_win~2_combout $end +$var wire 1 e inst1|p_win~6_combout $end +$var wire 1 f inst1|dealer:p_win~regout $end +$var wire 1 g inst1|Equal0~1_combout $end +$var wire 1 h inst1|Equal0~0_combout $end +$var wire 1 i inst1|Equal0~2_combout $end +$var wire 1 j inst1|LessThan3~1_cout $end +$var wire 1 k inst1|LessThan3~3_cout $end +$var wire 1 l inst1|LessThan3~5_cout $end +$var wire 1 m inst1|LessThan3~7_cout $end +$var wire 1 n inst1|LessThan3~9_cout $end +$var wire 1 o inst1|LessThan3~10_combout $end +$var wire 1 p inst1|p_win~3_combout $end +$var wire 1 q inst1|LessThan2~1_cout $end +$var wire 1 r inst1|LessThan2~3_cout $end +$var wire 1 s inst1|LessThan2~5_cout $end +$var wire 1 t inst1|LessThan2~7_cout $end +$var wire 1 u inst1|LessThan2~9_cout $end +$var wire 1 v inst1|LessThan2~10_combout $end +$var wire 1 w inst1|p_win~0_combout $end +$var wire 1 x inst1|p_win~4_combout $end +$var wire 1 y inst1|p_win~5_combout $end +$var wire 1 z inst1|p_win~7_combout $end +$var wire 1 { inst1|player_wins~feeder_combout $end +$var wire 1 | inst1|player_wins~regout $end +$var wire 1 } inst1|d_win~0_combout $end +$var wire 1 ~ inst1|dealer_wins~regout $end +$var wire 1 !! inst1|p_win~1_combout $end +$var wire 1 "! inst1|led_display1~6_combout $end +$var wire 1 #! inst1|led_display1~4_combout $end +$var wire 1 $! inst1|dealer:d_win~regout $end +$var wire 1 %! inst1|led_display1[0]~7_combout $end +$var wire 1 &! inst1|led_display1[0]~5_combout $end +$var wire 1 '! inst1|led_display3~3_combout $end +$var wire 1 (! inst1|led_display3~2_combout $end +$var wire 1 )! inst1|led_display4[3]~feeder_combout $end +$var wire 1 *! sum~combout [5] $end +$var wire 1 +! sum~combout [4] $end +$var wire 1 ,! sum~combout [3] $end +$var wire 1 -! sum~combout [2] $end +$var wire 1 .! sum~combout [1] $end +$var wire 1 /! sum~combout [0] $end +$var wire 1 0! inst|sum_out [5] $end +$var wire 1 1! inst|sum_out [4] $end +$var wire 1 2! inst|sum_out [3] $end +$var wire 1 3! inst|sum_out [2] $end +$var wire 1 4! inst|sum_out [1] $end +$var wire 1 5! inst|sum_out [0] $end +$var wire 1 6! inst1|led_display3 [6] $end +$var wire 1 7! inst1|led_display3 [5] $end +$var wire 1 8! inst1|led_display3 [4] $end +$var wire 1 9! inst1|led_display3 [3] $end +$var wire 1 :! inst1|led_display3 [2] $end +$var wire 1 ;! inst1|led_display3 [1] $end +$var wire 1 ! inst1|led_display4 [5] $end +$var wire 1 ?! inst1|led_display4 [4] $end +$var wire 1 @! inst1|led_display4 [3] $end +$var wire 1 A! inst1|led_display4 [2] $end +$var wire 1 B! inst1|led_display4 [1] $end +$var wire 1 C! inst1|led_display4 [0] $end +$var wire 1 D! player_sum~combout [5] $end +$var wire 1 E! player_sum~combout [4] $end +$var wire 1 F! player_sum~combout [3] $end +$var wire 1 G! player_sum~combout [2] $end +$var wire 1 H! player_sum~combout [1] $end +$var wire 1 I! player_sum~combout [0] $end +$var wire 1 J! inst1|led_display1 [6] $end +$var wire 1 K! inst1|led_display1 [5] $end +$var wire 1 L! inst1|led_display1 [4] $end +$var wire 1 M! inst1|led_display1 [3] $end +$var wire 1 N! inst1|led_display1 [2] $end +$var wire 1 O! inst1|led_display1 [1] $end +$var wire 1 P! inst1|led_display1 [0] $end +$upscope $end +$upscope $end +$enddefinitions $end +#0 +$dumpvars +0! +b10101 " +0# +b0 $ +0% +0& +0' +0( +0/ +0. +0- +1, +0+ +0* +0) +06 +05 +04 +03 +02 +11 +10 +1= +0< +0; +1: +19 +18 +17 +1D +1C +1B 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+b1000 $ +b1001 $ +b1011 $ +0! +1/! +1.! +0+! +0V +0W +1N +0Y +#940000 +1! +1V +1W +0N +14! +15! +01! +1] +0w +0k +0h +1j +1u +0n +1` +1L +1M +0I +1G +0!! +1x +1v +0o +1'! +0z +1} +1!! +0x +0p +1(! +0)! +0{ +0'! +1z +0} +0(! +1)! +1{ +#950000 +b1001 $ +0.! +1N +#960000 +0! +0V +0W +0N +#980000 +1! +1V +1W +1N +04! +1a +0L +1( +#1000000 diff --git a/lab5/simulation/qsim/gA6_lab5.msim.vwf b/lab5/simulation/qsim/gA6_lab5.msim.vwf new file mode 100644 index 0000000..e00708d --- /dev/null +++ b/lab5/simulation/qsim/gA6_lab5.msim.vwf @@ -0,0 +1,5208 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 0.0; + GRID_DUTY_CYCLE = 50; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|clk") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|player_sum") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 6; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|player_sum[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "gA6_lab5_vlg_vec_tst|player_sum"; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|player_sum[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "gA6_lab5_vlg_vec_tst|player_sum"; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|player_sum[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "gA6_lab5_vlg_vec_tst|player_sum"; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|player_sum[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "gA6_lab5_vlg_vec_tst|player_sum"; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|player_sum[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "gA6_lab5_vlg_vec_tst|player_sum"; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|player_sum[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "gA6_lab5_vlg_vec_tst|player_sum"; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|rst") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|sum") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 6; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|sum[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "gA6_lab5_vlg_vec_tst|sum"; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|sum[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "gA6_lab5_vlg_vec_tst|sum"; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|sum[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "gA6_lab5_vlg_vec_tst|sum"; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|sum[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "gA6_lab5_vlg_vec_tst|sum"; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|sum[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "gA6_lab5_vlg_vec_tst|sum"; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|sum[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "gA6_lab5_vlg_vec_tst|sum"; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|turn") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|dealer_wins") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|done") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|hit") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|led_display1[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|led_display1[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|led_display1[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|led_display1[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|led_display1[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|led_display1[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|led_display1[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|led_display2[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|led_display2[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|led_display2[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|led_display2[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|led_display2[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|led_display2[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|led_display2[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|led_display3[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|led_display3[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|led_display3[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|led_display3[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|led_display3[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|led_display3[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|led_display3[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|led_display4[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|led_display4[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|led_display4[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|led_display4[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|led_display4[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|led_display4[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|led_display4[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|player_wins") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|state_out[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|state_out[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|sum_out[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|sum_out[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|sum_out[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|sum_out[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|sum_out[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|sum_out[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|sampler") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|gnd") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|vcc") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|unknown") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|devclrn") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|devpor") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|devoe") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|turn~combout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|clk~combout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|clk~clkctrl_outclk") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst|LessThan0~0_combout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst|LessThan0~1_combout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst|computer:state[0]~0_combout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|rst~combout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|rst~clkctrl_outclk") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst|computer:state[0]~regout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst|computer:state[1]~0_combout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst|computer:state[1]~regout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst|Mux0~0_combout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst|hit~regout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst|Mux1~0_combout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst|done~regout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|p_win~2_combout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|p_win~6_combout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|dealer:p_win~regout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|Equal0~1_combout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|Equal0~0_combout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|Equal0~2_combout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|LessThan3~1_cout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|LessThan3~3_cout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|LessThan3~5_cout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|LessThan3~7_cout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|LessThan3~9_cout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|LessThan3~10_combout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|p_win~3_combout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|LessThan2~1_cout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|LessThan2~3_cout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|LessThan2~5_cout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|LessThan2~7_cout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|LessThan2~9_cout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|LessThan2~10_combout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|p_win~0_combout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|p_win~4_combout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|p_win~5_combout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|p_win~7_combout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|player_wins~feeder_combout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|player_wins~regout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|d_win~0_combout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|dealer_wins~regout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|p_win~1_combout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|led_display1~6_combout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|led_display1~4_combout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|dealer:d_win~regout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|led_display1[0]~7_combout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|led_display1[0]~5_combout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|led_display3~3_combout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|led_display3~2_combout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|led_display4[3]~feeder_combout") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|sum~combout[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|sum~combout[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|sum~combout[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|sum~combout[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|sum~combout[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|sum~combout[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst|sum_out[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst|sum_out[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst|sum_out[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst|sum_out[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst|sum_out[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst|sum_out[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|led_display3[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|led_display3[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|led_display3[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|led_display3[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|led_display3[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|led_display3[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|led_display3[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|led_display4[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|led_display4[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|led_display4[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|led_display4[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|led_display4[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|led_display4[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|led_display4[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|player_sum~combout[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|player_sum~combout[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|player_sum~combout[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|player_sum~combout[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|player_sum~combout[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|player_sum~combout[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|led_display1[6]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|led_display1[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|led_display1[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|led_display1[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|led_display1[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|led_display1[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("gA6_lab5_vlg_vec_tst|i1|inst1|led_display1[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|clk") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|player_sum[5]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|player_sum[4]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 150.0; + LEVEL 0 FOR 70.0; + LEVEL 1 FOR 460.0; + LEVEL 0 FOR 210.0; + LEVEL 1 FOR 110.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|player_sum[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 420.0; + LEVEL 1 FOR 170.0; + LEVEL 0 FOR 90.0; + LEVEL 1 FOR 210.0; + LEVEL 0 FOR 110.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|player_sum[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 150.0; + LEVEL 0 FOR 180.0; + LEVEL 1 FOR 90.0; + LEVEL 0 FOR 170.0; + LEVEL 1 FOR 90.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 260.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|player_sum[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 590.0; + LEVEL 1 FOR 90.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 150.0; + LEVEL 0 FOR 110.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|player_sum[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 150.0; + LEVEL 0 FOR 530.0; + LEVEL 1 FOR 210.0; + LEVEL 0 FOR 110.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|rst") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 640.0; + LEVEL 1 FOR 130.0; + LEVEL 0 FOR 230.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|sum[5]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|sum[4]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 210.0; + LEVEL 0 FOR 180.0; + LEVEL 1 FOR 90.0; + LEVEL 0 FOR 150.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 80.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|sum[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 70.0; + LEVEL 0 FOR 210.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 270.0; + LEVEL 1 FOR 230.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|sum[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 230.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 180.0; + LEVEL 1 FOR 240.0; + LEVEL 0 FOR 140.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|sum[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 70.0; + LEVEL 1 FOR 90.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 90.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 90.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 50.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|sum[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 210.0; + LEVEL 1 FOR 180.0; + LEVEL 0 FOR 90.0; + LEVEL 1 FOR 150.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 80.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|turn") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 90.0; + LEVEL 1 FOR 340.0; + LEVEL 0 FOR 210.0; + LEVEL 1 FOR 90.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|dealer_wins") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 180.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 240.0; + LEVEL 0 FOR 300.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|done") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 140.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 500.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|hit") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 280.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 340.0; + LEVEL 1 FOR 20.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|led_display1[6]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 160.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 580.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|led_display1[5]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|led_display1[4]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|led_display1[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 160.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 580.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|led_display1[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 180.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 240.0; + LEVEL 0 FOR 300.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|led_display1[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 160.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 580.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|led_display1[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 160.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 580.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|led_display2[6]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|led_display2[5]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 180.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 240.0; + LEVEL 1 FOR 300.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|led_display2[4]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|led_display2[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|led_display2[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|led_display2[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|led_display2[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 200.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 200.0; + LEVEL 0 FOR 240.0; + LEVEL 1 FOR 300.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|led_display3[6]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 180.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 240.0; + LEVEL 1 FOR 300.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|led_display3[5]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 180.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 240.0; + LEVEL 1 FOR 300.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|led_display3[4]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|led_display3[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 180.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 240.0; + LEVEL 1 FOR 300.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|led_display3[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|led_display3[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 180.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 240.0; + LEVEL 0 FOR 300.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|led_display3[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 180.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 240.0; + LEVEL 1 FOR 300.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|led_display4[6]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 180.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 240.0; + LEVEL 1 FOR 300.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|led_display4[5]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|led_display4[4]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|led_display4[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 200.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 200.0; + LEVEL 0 FOR 240.0; + LEVEL 1 FOR 300.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|led_display4[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 240.0; + LEVEL 0 FOR 300.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|led_display4[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 240.0; + LEVEL 0 FOR 300.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|led_display4[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 160.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 580.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|player_wins") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 200.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 200.0; + LEVEL 0 FOR 240.0; + LEVEL 1 FOR 300.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|state_out[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 540.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|state_out[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 140.0; + LEVEL 0 FOR 300.0; + LEVEL 1 FOR 60.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|sum_out[5]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|sum_out[4]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 200.0; + LEVEL 0 FOR 160.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 220.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 60.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|sum_out[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 280.0; + LEVEL 1 FOR 220.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|sum_out[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 260.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 160.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 140.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 140.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|sum_out[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 220.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 20.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|sum_out[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 220.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 160.0; + LEVEL 0 FOR 160.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 60.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|sampler") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|gnd") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|vcc") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|unknown") +{ + NODE + { + REPEAT = 1; + LEVEL X FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|devclrn") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|devpor") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|devoe") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|turn~combout") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 90.0; + LEVEL 1 FOR 340.0; + LEVEL 0 FOR 210.0; + LEVEL 1 FOR 90.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|clk~combout") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|clk~clkctrl_outclk") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst|LessThan0~0_combout") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 190.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 590.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst|LessThan0~1_combout") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 180.0; + LEVEL 1 FOR 90.0; + LEVEL 0 FOR 150.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 80.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst|computer:state[0]~0_combout") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 70.0; + LEVEL 0 FOR 90.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 130.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 160.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 210.0; + LEVEL 1 FOR 90.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|rst~combout") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 640.0; + LEVEL 1 FOR 130.0; + LEVEL 0 FOR 230.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|rst~clkctrl_outclk") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 640.0; + LEVEL 1 FOR 130.0; + LEVEL 0 FOR 230.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst|computer:state[0]~regout") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 140.0; + LEVEL 0 FOR 300.0; + LEVEL 1 FOR 60.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst|computer:state[1]~0_combout") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 130.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 150.0; + LEVEL 1 FOR 10.0; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 360.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst|computer:state[1]~regout") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 540.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst|Mux0~0_combout") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 150.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 90.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 320.0; + LEVEL 1 FOR 60.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst|hit~regout") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 280.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 340.0; + LEVEL 1 FOR 20.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst|Mux1~0_combout") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 540.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst|done~regout") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 140.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 500.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|p_win~2_combout") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 420.0; + LEVEL 1 FOR 260.0; + LEVEL 0 FOR 320.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|p_win~6_combout") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 420.0; + LEVEL 1 FOR 260.0; + LEVEL 0 FOR 320.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|dealer:p_win~regout") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 200.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 200.0; + LEVEL 0 FOR 240.0; + LEVEL 1 FOR 300.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|Equal0~1_combout") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 150.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 150.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 140.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 140.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|Equal0~0_combout") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 150.0; + LEVEL 1 FOR 70.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 260.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 60.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|Equal0~2_combout") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 150.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 150.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 240.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 360.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|LessThan3~1_cout") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 220.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 160.0; + LEVEL 0 FOR 320.0; + LEVEL 1 FOR 60.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|LessThan3~3_cout") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 170.0; + LEVEL 1 FOR 300.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 60.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|LessThan3~5_cout") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 220.0; + LEVEL 1 FOR 110.0; + LEVEL 0 FOR 90.0; + LEVEL 1 FOR 170.0; + LEVEL 0 FOR 410.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|LessThan3~7_cout") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 150.0; + LEVEL 1 FOR 130.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 390.0; + LEVEL 0 FOR 110.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|LessThan3~9_cout") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 180.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 70.0; + LEVEL 0 FOR 530.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 60.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|LessThan3~10_combout") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 180.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 70.0; + LEVEL 0 FOR 530.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 60.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|p_win~3_combout") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 180.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 70.0; + LEVEL 0 FOR 530.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 60.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|LessThan2~1_cout") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 150.0; + LEVEL 0 FOR 530.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 110.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|LessThan2~3_cout") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 440.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 250.0; + LEVEL 1 FOR 110.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|LessThan2~5_cout") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 150.0; + LEVEL 0 FOR 230.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 170.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 360.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|LessThan2~7_cout") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 230.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 250.0; + LEVEL 1 FOR 110.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|LessThan2~9_cout") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 150.0; + LEVEL 0 FOR 70.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 240.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 220.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 60.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|LessThan2~10_combout") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 150.0; + LEVEL 0 FOR 70.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 240.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 220.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 60.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|p_win~0_combout") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 260.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 160.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 220.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 60.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|p_win~4_combout") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 150.0; + LEVEL 1 FOR 70.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 620.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|p_win~5_combout") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|p_win~7_combout") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 180.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 90.0; + LEVEL 0 FOR 260.0; + LEVEL 1 FOR 320.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|player_wins~feeder_combout") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 180.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 90.0; + LEVEL 0 FOR 260.0; + LEVEL 1 FOR 320.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|player_wins~regout") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 200.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 200.0; + LEVEL 0 FOR 240.0; + LEVEL 1 FOR 300.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|d_win~0_combout") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 150.0; + LEVEL 1 FOR 70.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 260.0; + LEVEL 0 FOR 320.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|dealer_wins~regout") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 180.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 240.0; + LEVEL 0 FOR 300.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|p_win~1_combout") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 180.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 670.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|led_display1~6_combout") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 150.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 150.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 620.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|led_display1~4_combout") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 150.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 150.0; + LEVEL 0 FOR 50.0; + LEVEL 1 FOR 620.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|dealer:d_win~regout") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 180.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 240.0; + LEVEL 0 FOR 300.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|led_display1[0]~7_combout") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|led_display1[0]~5_combout") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|led_display3~3_combout") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 150.0; + LEVEL 1 FOR 70.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 260.0; + LEVEL 0 FOR 320.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|led_display3~2_combout") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 150.0; + LEVEL 1 FOR 70.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 260.0; + LEVEL 0 FOR 320.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|led_display4[3]~feeder_combout") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 180.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 90.0; + LEVEL 0 FOR 260.0; + LEVEL 1 FOR 320.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|sum~combout[5]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|sum~combout[4]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 210.0; + LEVEL 0 FOR 180.0; + LEVEL 1 FOR 90.0; + LEVEL 0 FOR 150.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 80.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|sum~combout[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 70.0; + LEVEL 0 FOR 210.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 270.0; + LEVEL 1 FOR 230.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|sum~combout[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 230.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 180.0; + LEVEL 1 FOR 240.0; + LEVEL 0 FOR 140.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|sum~combout[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 70.0; + LEVEL 1 FOR 90.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 90.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 90.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 50.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|sum~combout[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 210.0; + LEVEL 1 FOR 180.0; + LEVEL 0 FOR 90.0; + LEVEL 1 FOR 150.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 80.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst|sum_out[5]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst|sum_out[4]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 200.0; + LEVEL 0 FOR 160.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 220.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 60.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst|sum_out[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 280.0; + LEVEL 1 FOR 220.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst|sum_out[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 260.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 160.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 140.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 140.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst|sum_out[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 220.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 20.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst|sum_out[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 220.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 160.0; + LEVEL 0 FOR 160.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 60.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|led_display3[6]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|led_display3[5]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|led_display3[4]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|led_display3[3]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|led_display3[2]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|led_display3[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 180.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 240.0; + LEVEL 0 FOR 300.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|led_display3[0]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|led_display4[6]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|led_display4[5]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|led_display4[4]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|led_display4[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 200.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 200.0; + LEVEL 0 FOR 240.0; + LEVEL 1 FOR 300.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|led_display4[2]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|led_display4[1]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|led_display4[0]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|player_sum~combout[5]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|player_sum~combout[4]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 150.0; + LEVEL 0 FOR 70.0; + LEVEL 1 FOR 460.0; + LEVEL 0 FOR 210.0; + LEVEL 1 FOR 110.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|player_sum~combout[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 420.0; + LEVEL 1 FOR 170.0; + LEVEL 0 FOR 90.0; + LEVEL 1 FOR 210.0; + LEVEL 0 FOR 110.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|player_sum~combout[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 150.0; + LEVEL 0 FOR 180.0; + LEVEL 1 FOR 90.0; + LEVEL 0 FOR 170.0; + LEVEL 1 FOR 90.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 260.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|player_sum~combout[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 590.0; + LEVEL 1 FOR 90.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 150.0; + LEVEL 0 FOR 110.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|player_sum~combout[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 150.0; + LEVEL 0 FOR 530.0; + LEVEL 1 FOR 210.0; + LEVEL 0 FOR 110.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|led_display1[6]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|led_display1[5]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|led_display1[4]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|led_display1[3]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|led_display1[2]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|led_display1[1]") +{ + NODE + { + REPEAT = 1; + LEVEL Z FOR 1000.0; + } +} + +TRANSITION_LIST("gA6_lab5_vlg_vec_tst|i1|inst1|led_display1[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 160.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 580.0; + } +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|clk"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|player_sum"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 1; + TREE_LEVEL = 0; + CHILDREN = 2, 3, 4, 5, 6, 7; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|player_sum[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 2; + TREE_LEVEL = 1; + PARENT = 1; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|player_sum[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 3; + TREE_LEVEL = 1; + PARENT = 1; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|player_sum[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 1; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|player_sum[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 1; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|player_sum[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 6; + TREE_LEVEL = 1; + PARENT = 1; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|player_sum[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 1; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|rst"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 8; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|sum"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 9; + TREE_LEVEL = 0; + CHILDREN = 10, 11, 12, 13, 14, 15; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|sum[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 10; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|sum[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 11; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|sum[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 12; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|sum[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 13; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|sum[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 14; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|sum[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 15; + TREE_LEVEL = 1; + PARENT = 9; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|turn"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 16; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|dealer_wins"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 17; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|done"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 18; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|hit"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 19; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|led_display1[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 20; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|led_display1[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 21; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|led_display1[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 22; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|led_display1[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 23; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|led_display1[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 24; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|led_display1[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 25; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|led_display1[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 26; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|led_display2[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 27; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|led_display2[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 28; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|led_display2[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 29; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|led_display2[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 30; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|led_display2[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 31; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|led_display2[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 32; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|led_display2[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 33; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|led_display3[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 34; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|led_display3[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 35; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|led_display3[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 36; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|led_display3[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 37; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|led_display3[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 38; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|led_display3[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 39; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|led_display3[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 40; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|led_display4[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 41; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|led_display4[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 42; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|led_display4[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 43; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|led_display4[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 44; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|led_display4[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 45; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|led_display4[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 46; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|led_display4[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 47; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|player_wins"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 48; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|state_out[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 49; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|state_out[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 50; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|sum_out[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 51; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|sum_out[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 52; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|sum_out[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 53; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|sum_out[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 54; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|sum_out[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 55; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|sum_out[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 56; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|sampler"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 57; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|gnd"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 58; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|vcc"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 59; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|unknown"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 60; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|devclrn"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 61; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|devpor"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 62; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|devoe"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 63; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|turn~combout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 64; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|clk~combout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 65; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|clk~clkctrl_outclk"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 66; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst|LessThan0~0_combout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 67; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst|LessThan0~1_combout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 68; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst|computer:state[0]~0_combout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 69; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|rst~combout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 70; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|rst~clkctrl_outclk"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 71; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst|computer:state[0]~regout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 72; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst|computer:state[1]~0_combout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 73; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst|computer:state[1]~regout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 74; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst|Mux0~0_combout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 75; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst|hit~regout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 76; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst|Mux1~0_combout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 77; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst|done~regout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 78; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|p_win~2_combout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 79; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|p_win~6_combout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 80; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|dealer:p_win~regout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 81; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|Equal0~1_combout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 82; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|Equal0~0_combout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 83; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|Equal0~2_combout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 84; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|LessThan3~1_cout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 85; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|LessThan3~3_cout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 86; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|LessThan3~5_cout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 87; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|LessThan3~7_cout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 88; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|LessThan3~9_cout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 89; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|LessThan3~10_combout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 90; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|p_win~3_combout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 91; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|LessThan2~1_cout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 92; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|LessThan2~3_cout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 93; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|LessThan2~5_cout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 94; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|LessThan2~7_cout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 95; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|LessThan2~9_cout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 96; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|LessThan2~10_combout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 97; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|p_win~0_combout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 98; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|p_win~4_combout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 99; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|p_win~5_combout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 100; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|p_win~7_combout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 101; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|player_wins~feeder_combout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 102; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|player_wins~regout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 103; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|d_win~0_combout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 104; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|dealer_wins~regout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 105; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|p_win~1_combout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 106; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|led_display1~6_combout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 107; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|led_display1~4_combout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 108; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|dealer:d_win~regout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 109; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|led_display1[0]~7_combout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 110; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|led_display1[0]~5_combout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 111; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|led_display3~3_combout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 112; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|led_display3~2_combout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 113; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|led_display4[3]~feeder_combout"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 114; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|sum~combout[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 115; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|sum~combout[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 116; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|sum~combout[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 117; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|sum~combout[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 118; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|sum~combout[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 119; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|sum~combout[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 120; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst|sum_out[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 121; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst|sum_out[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 122; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst|sum_out[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 123; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst|sum_out[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 124; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst|sum_out[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 125; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst|sum_out[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 126; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|led_display3[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 127; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|led_display3[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 128; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|led_display3[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 129; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|led_display3[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 130; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|led_display3[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 131; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|led_display3[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 132; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|led_display3[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 133; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|led_display4[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 134; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|led_display4[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 135; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|led_display4[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 136; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|led_display4[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 137; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|led_display4[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 138; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|led_display4[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 139; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|led_display4[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 140; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|player_sum~combout[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 141; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|player_sum~combout[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 142; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|player_sum~combout[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 143; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|player_sum~combout[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 144; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|player_sum~combout[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 145; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|player_sum~combout[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 146; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|led_display1[6]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 147; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|led_display1[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 148; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|led_display1[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 149; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|led_display1[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 150; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|led_display1[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 151; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|led_display1[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 152; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "gA6_lab5_vlg_vec_tst|i1|inst1|led_display1[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 153; + TREE_LEVEL = 0; +} +; diff --git a/lab5/simulation/qsim/gA6_lab5.sim.vwf b/lab5/simulation/qsim/gA6_lab5.sim.vwf new file mode 100644 index 0000000..60b72ab --- /dev/null +++ b/lab5/simulation/qsim/gA6_lab5.sim.vwf @@ -0,0 +1,1075 @@ +/* +WARNING: Do NOT edit the input and output ports in this file in a text +editor if you plan to continue editing the block that represents it in +the Block Editor! File corruption is VERY likely to occur. +*/ + +/* +Copyright (C) 1991-2013 Altera Corporation +Your use of Altera Corporation's design tools, logic functions +and other software and tools, and its AMPP partner logic +functions, and any output files from any of the foregoing +(including device programming or simulation files), and any +associated documentation or information are expressly subject +to the terms and conditions of the Altera Program License +Subscription Agreement, Altera MegaCore Function License +Agreement, or other applicable license agreement, including, +without limitation, that your use is for the sole purpose of +programming logic devices manufactured by Altera and sold by +Altera or its authorized distributors. Please refer to the +applicable agreement for further details. +*/ + +HEADER +{ + VERSION = 1; + TIME_UNIT = ns; + DATA_OFFSET = 0.0; + DATA_DURATION = 1000.0; + SIMULATION_TIME = 0.0; + GRID_PHASE = 0.0; + GRID_PERIOD = 0.0; + GRID_DUTY_CYCLE = 50; +} + + + + +SIGNAL("clk") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("dealer_wins") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("done") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("hit") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("player_sum") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 6; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("player_sum[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "player_sum"; +} + +SIGNAL("player_sum[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "player_sum"; +} + +SIGNAL("player_sum[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "player_sum"; +} + +SIGNAL("player_sum[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "player_sum"; +} + +SIGNAL("player_sum[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "player_sum"; +} + +SIGNAL("player_sum[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "player_sum"; +} + +SIGNAL("player_wins") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("rst") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("sum") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 6; + LSB_INDEX = 0; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("sum[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "sum"; +} + +SIGNAL("sum[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "sum"; +} + +SIGNAL("sum[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "sum"; +} + +SIGNAL("sum[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "sum"; +} + +SIGNAL("sum[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "sum"; +} + +SIGNAL("sum[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = "sum"; +} + +SIGNAL("sum_out") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 6; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("sum_out[5]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "sum_out"; +} + +SIGNAL("sum_out[4]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "sum_out"; +} + +SIGNAL("sum_out[3]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "sum_out"; +} + +SIGNAL("sum_out[2]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "sum_out"; +} + +SIGNAL("sum_out[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "sum_out"; +} + +SIGNAL("sum_out[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "sum_out"; +} + +SIGNAL("turn") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = INPUT; + PARENT = ""; +} + +SIGNAL("state_out") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = BUS; + WIDTH = 2; + LSB_INDEX = 0; + DIRECTION = OUTPUT; + PARENT = ""; +} + +SIGNAL("state_out[1]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "state_out"; +} + +SIGNAL("state_out[0]") +{ + VALUE_TYPE = NINE_LEVEL_BIT; + SIGNAL_TYPE = SINGLE_BIT; + WIDTH = 1; + LSB_INDEX = -1; + DIRECTION = OUTPUT; + PARENT = "state_out"; +} + +TRANSITION_LIST("clk") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 20.0; + } +} +TRANSITION_LIST("dealer_wins") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 180.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 240.0; + LEVEL 0 FOR 300.0; + } +} +TRANSITION_LIST("done") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 140.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 500.0; + } +} +TRANSITION_LIST("hit") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 280.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 340.0; + LEVEL 1 FOR 20.0; + } +} +TRANSITION_LIST("player_sum[5]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} +TRANSITION_LIST("player_sum[4]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 150.0; + LEVEL 0 FOR 70.0; + LEVEL 1 FOR 460.0; + LEVEL 0 FOR 210.0; + LEVEL 1 FOR 110.0; + } +} +TRANSITION_LIST("player_sum[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 420.0; + LEVEL 1 FOR 170.0; + LEVEL 0 FOR 90.0; + LEVEL 1 FOR 210.0; + LEVEL 0 FOR 110.0; + } +} +TRANSITION_LIST("player_sum[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 150.0; + LEVEL 0 FOR 180.0; + LEVEL 1 FOR 90.0; + LEVEL 0 FOR 170.0; + LEVEL 1 FOR 90.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 260.0; + } +} +TRANSITION_LIST("player_sum[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 590.0; + LEVEL 1 FOR 90.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 150.0; + LEVEL 0 FOR 110.0; + } +} +TRANSITION_LIST("player_sum[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 1 FOR 150.0; + LEVEL 0 FOR 530.0; + LEVEL 1 FOR 210.0; + LEVEL 0 FOR 110.0; + } +} +TRANSITION_LIST("player_wins") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 200.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 200.0; + LEVEL 0 FOR 240.0; + LEVEL 1 FOR 300.0; + } +} +TRANSITION_LIST("rst") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 640.0; + LEVEL 1 FOR 130.0; + LEVEL 0 FOR 230.0; + } +} +TRANSITION_LIST("sum[5]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} +TRANSITION_LIST("sum[4]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 210.0; + LEVEL 0 FOR 180.0; + LEVEL 1 FOR 90.0; + LEVEL 0 FOR 150.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 80.0; + } +} +TRANSITION_LIST("sum[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 50.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 70.0; + LEVEL 0 FOR 210.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 270.0; + LEVEL 1 FOR 230.0; + } +} +TRANSITION_LIST("sum[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 230.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 180.0; + LEVEL 1 FOR 240.0; + LEVEL 0 FOR 140.0; + } +} +TRANSITION_LIST("sum[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 70.0; + LEVEL 1 FOR 90.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 90.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 60.0; + LEVEL 0 FOR 90.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 30.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 50.0; + } +} +TRANSITION_LIST("sum[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 30.0; + LEVEL 0 FOR 210.0; + LEVEL 1 FOR 180.0; + LEVEL 0 FOR 90.0; + LEVEL 1 FOR 150.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 80.0; + } +} +TRANSITION_LIST("sum_out[5]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 1000.0; + } +} +TRANSITION_LIST("sum_out[4]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 200.0; + LEVEL 0 FOR 160.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 220.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 60.0; + } +} +TRANSITION_LIST("sum_out[3]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 280.0; + LEVEL 1 FOR 220.0; + } +} +TRANSITION_LIST("sum_out[2]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 260.0; + LEVEL 1 FOR 120.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 160.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 140.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 140.0; + } +} +TRANSITION_LIST("sum_out[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 20.0; + LEVEL 0 FOR 220.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 40.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 20.0; + } +} +TRANSITION_LIST("sum_out[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 220.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 200.0; + LEVEL 1 FOR 160.0; + LEVEL 0 FOR 160.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 60.0; + } +} +TRANSITION_LIST("turn") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 10.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 60.0; + LEVEL 1 FOR 100.0; + LEVEL 0 FOR 90.0; + LEVEL 1 FOR 340.0; + LEVEL 0 FOR 210.0; + LEVEL 1 FOR 90.0; + } +} +TRANSITION_LIST("state_out[1]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 100.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 540.0; + } +} +TRANSITION_LIST("state_out[0]") +{ + NODE + { + REPEAT = 1; + LEVEL 0 FOR 20.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 80.0; + LEVEL 0 FOR 120.0; + LEVEL 1 FOR 40.0; + LEVEL 0 FOR 80.0; + LEVEL 1 FOR 140.0; + LEVEL 0 FOR 300.0; + LEVEL 1 FOR 60.0; + } +} + + +DISPLAY_LINE +{ + CHANNEL = "clk"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 0; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "rst"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 1; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "turn"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 2; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "sum"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 3; + TREE_LEVEL = 0; + CHILDREN = 4, 5, 6, 7, 8, 9; +} + +DISPLAY_LINE +{ + CHANNEL = "sum[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 4; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "sum[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 5; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "sum[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 6; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "sum[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 7; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "sum[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 8; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "sum[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 9; + TREE_LEVEL = 1; + PARENT = 3; +} + +DISPLAY_LINE +{ + CHANNEL = "sum_out"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 10; + TREE_LEVEL = 0; + CHILDREN = 11, 12, 13, 14, 15, 16; +} + +DISPLAY_LINE +{ + CHANNEL = "sum_out[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 11; + TREE_LEVEL = 1; + PARENT = 10; +} + +DISPLAY_LINE +{ + CHANNEL = "sum_out[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 12; + TREE_LEVEL = 1; + PARENT = 10; +} + +DISPLAY_LINE +{ + CHANNEL = "sum_out[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 13; + TREE_LEVEL = 1; + PARENT = 10; +} + +DISPLAY_LINE +{ + CHANNEL = "sum_out[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 14; + TREE_LEVEL = 1; + PARENT = 10; +} + +DISPLAY_LINE +{ + CHANNEL = "sum_out[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 15; + TREE_LEVEL = 1; + PARENT = 10; +} + +DISPLAY_LINE +{ + CHANNEL = "sum_out[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 16; + TREE_LEVEL = 1; + PARENT = 10; +} + +DISPLAY_LINE +{ + CHANNEL = "state_out"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 17; + TREE_LEVEL = 0; + CHILDREN = 18, 19; +} + +DISPLAY_LINE +{ + CHANNEL = "state_out[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 18; + TREE_LEVEL = 1; + PARENT = 17; +} + +DISPLAY_LINE +{ + CHANNEL = "state_out[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Binary; + TREE_INDEX = 19; + TREE_LEVEL = 1; + PARENT = 17; +} + +DISPLAY_LINE +{ + CHANNEL = "hit"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 20; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "done"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 21; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "player_sum"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 22; + TREE_LEVEL = 0; + CHILDREN = 23, 24, 25, 26, 27, 28; +} + +DISPLAY_LINE +{ + CHANNEL = "player_sum[5]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 23; + TREE_LEVEL = 1; + PARENT = 22; +} + +DISPLAY_LINE +{ + CHANNEL = "player_sum[4]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 24; + TREE_LEVEL = 1; + PARENT = 22; +} + +DISPLAY_LINE +{ + CHANNEL = "player_sum[3]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 25; + TREE_LEVEL = 1; + PARENT = 22; +} + +DISPLAY_LINE +{ + CHANNEL = "player_sum[2]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 26; + TREE_LEVEL = 1; + PARENT = 22; +} + +DISPLAY_LINE +{ + CHANNEL = "player_sum[1]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 27; + TREE_LEVEL = 1; + PARENT = 22; +} + +DISPLAY_LINE +{ + CHANNEL = "player_sum[0]"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 28; + TREE_LEVEL = 1; + PARENT = 22; +} + +DISPLAY_LINE +{ + CHANNEL = "player_wins"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 29; + TREE_LEVEL = 0; +} + +DISPLAY_LINE +{ + CHANNEL = "dealer_wins"; + EXPAND_STATUS = COLLAPSED; + RADIX = Unsigned; + TREE_INDEX = 30; + TREE_LEVEL = 0; +} +TIME_BAR +{ + TIME = 0; + MASTER = TRUE; +} +; diff --git a/lab5/simulation/qsim/gA6_lab5.vo b/lab5/simulation/qsim/gA6_lab5.vo new file mode 100644 index 0000000..078ddf0 --- /dev/null +++ b/lab5/simulation/qsim/gA6_lab5.vo @@ -0,0 +1,3064 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// VENDOR "Altera" +// PROGRAM "Quartus II 64-Bit" +// VERSION "Version 13.0.0 Build 156 04/24/2013 SJ Web Edition" + +// DATE "11/29/2017 18:55:05" + +// +// Device: Altera EP2C20F484C7 Package FBGA484 +// + +// +// This Verilog file should be used for ModelSim-Altera (Verilog) only +// + +`timescale 1 ps/ 1 ps + +module gA6_lab5 ( + hit, + clk, + rst, + turn, + sum, + done, + player_wins, + player_sum, + dealer_wins, + led_display1, + led_display2, + led_display3, + led_display4, + state_out, + sum_out); +output hit; +input clk; +input rst; +input turn; +input [5:0] sum; +output done; +output player_wins; +input [5:0] player_sum; +output dealer_wins; +output [6:0] led_display1; +output [6:0] led_display2; +output [6:0] led_display3; +output [6:0] led_display4; +output [1:0] state_out; +output [5:0] sum_out; + +// Design Ports Information +// hit => Location: PIN_W7, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// done => Location: PIN_V9, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// player_wins => Location: PIN_W4, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// dealer_wins => Location: PIN_W3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display1[6] => Location: PIN_R6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display1[5] => Location: PIN_B17, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display1[4] => Location: PIN_T15, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display1[3] => Location: PIN_T3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display1[2] => Location: PIN_Y2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display1[1] => Location: PIN_U2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display1[0] => Location: PIN_R5, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display2[6] => Location: PIN_B14, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display2[5] => Location: PIN_T5, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display2[4] => Location: PIN_W9, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display2[3] => Location: PIN_H15, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display2[2] => Location: PIN_B11, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display2[1] => Location: PIN_AA16, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display2[0] => Location: PIN_AB7, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display3[6] => Location: PIN_T6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display3[5] => Location: PIN_U3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display3[4] => Location: PIN_C7, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display3[3] => Location: PIN_W1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display3[2] => Location: PIN_C21, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display3[1] => Location: PIN_Y1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display3[0] => Location: PIN_V2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display4[6] => Location: PIN_W2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display4[5] => Location: PIN_G8, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display4[4] => Location: PIN_D2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display4[3] => Location: PIN_P9, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display4[2] => Location: PIN_P8, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display4[1] => Location: PIN_AA7, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// led_display4[0] => Location: PIN_U1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// state_out[1] => Location: PIN_V8, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// state_out[0] => Location: PIN_AB6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// sum_out[5] => Location: PIN_U4, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// sum_out[4] => Location: PIN_W5, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// sum_out[3] => Location: PIN_AA4, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// sum_out[2] => Location: PIN_T8, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// sum_out[1] => Location: PIN_T7, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// sum_out[0] => Location: PIN_AB4, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +// sum[5] => Location: PIN_U8, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// sum[4] => Location: PIN_Y6, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// sum[3] => Location: PIN_Y5, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// sum[2] => Location: PIN_AB5, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// sum[1] => Location: PIN_Y3, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// sum[0] => Location: PIN_AA5, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// clk => Location: PIN_M1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// rst => Location: PIN_M2, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// player_sum[5] => Location: PIN_AB3, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// player_sum[4] => Location: PIN_V4, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// player_sum[3] => Location: PIN_Y7, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// player_sum[2] => Location: PIN_AA3, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// player_sum[1] => Location: PIN_AA6, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// player_sum[0] => Location: PIN_Y4, I/O Standard: 3.3-V LVTTL, Current Strength: Default +// turn => Location: PIN_W8, I/O Standard: 3.3-V LVTTL, Current Strength: Default + + +wire gnd; +wire vcc; +wire unknown; + +assign gnd = 1'b0; +assign vcc = 1'b1; +assign unknown = 1'bx; + +tri1 devclrn; +tri1 devpor; +tri1 devoe; +wire \turn~combout ; +wire \clk~combout ; +wire \clk~clkctrl_outclk ; +wire \inst|LessThan0~0_combout ; +wire \inst|LessThan0~1_combout ; +wire \inst|computer:state[0]~0_combout ; +wire \rst~combout ; +wire \rst~clkctrl_outclk ; +wire \inst|computer:state[0]~regout ; +wire \inst|computer:state[1]~0_combout ; +wire \inst|computer:state[1]~regout ; +wire \inst|Mux0~0_combout ; +wire \inst|hit~regout ; +wire \inst|Mux1~0_combout ; +wire \inst|done~regout ; +wire \inst1|p_win~2_combout ; +wire \inst1|p_win~6_combout ; +wire \inst1|dealer:p_win~regout ; +wire \inst1|Equal0~1_combout ; +wire \inst1|Equal0~0_combout ; +wire \inst1|Equal0~2_combout ; +wire \inst1|LessThan3~1_cout ; +wire \inst1|LessThan3~3_cout ; +wire \inst1|LessThan3~5_cout ; +wire \inst1|LessThan3~7_cout ; +wire \inst1|LessThan3~9_cout ; +wire \inst1|LessThan3~10_combout ; +wire \inst1|p_win~3_combout ; +wire \inst1|LessThan2~1_cout ; +wire \inst1|LessThan2~3_cout ; +wire \inst1|LessThan2~5_cout ; +wire \inst1|LessThan2~7_cout ; +wire \inst1|LessThan2~9_cout ; +wire \inst1|LessThan2~10_combout ; +wire \inst1|p_win~0_combout ; +wire \inst1|p_win~4_combout ; +wire \inst1|p_win~5_combout ; +wire \inst1|p_win~7_combout ; +wire \inst1|player_wins~feeder_combout ; +wire \inst1|player_wins~regout ; +wire \inst1|d_win~0_combout ; +wire \inst1|dealer_wins~regout ; +wire \inst1|p_win~1_combout ; +wire \inst1|led_display1~6_combout ; +wire \inst1|led_display1~4_combout ; +wire \inst1|dealer:d_win~regout ; +wire \inst1|led_display1[0]~7_combout ; +wire \inst1|led_display1[0]~5_combout ; +wire \inst1|led_display3~3_combout ; +wire \inst1|led_display3~2_combout ; +wire \inst1|led_display4[3]~feeder_combout ; +wire [5:0] \sum~combout ; +wire [5:0] \inst|sum_out ; +wire [6:0] \inst1|led_display3 ; +wire [6:0] \inst1|led_display4 ; +wire [5:0] \player_sum~combout ; +wire [6:0] \inst1|led_display1 ; + + +// Location: PIN_V4, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \player_sum[4]~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\player_sum~combout [4]), + .regout(), + .differentialout(), + .linkout(), + .padio(player_sum[4])); +// synopsys translate_off +defparam \player_sum[4]~I .input_async_reset = "none"; +defparam \player_sum[4]~I .input_power_up = "low"; +defparam \player_sum[4]~I .input_register_mode = "none"; +defparam \player_sum[4]~I .input_sync_reset = "none"; +defparam \player_sum[4]~I .oe_async_reset = "none"; +defparam \player_sum[4]~I .oe_power_up = "low"; +defparam \player_sum[4]~I .oe_register_mode = "none"; +defparam \player_sum[4]~I .oe_sync_reset = "none"; +defparam \player_sum[4]~I .operation_mode = "input"; +defparam \player_sum[4]~I .output_async_reset = "none"; +defparam \player_sum[4]~I .output_power_up = "low"; +defparam \player_sum[4]~I .output_register_mode = "none"; +defparam \player_sum[4]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_W8, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \turn~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\turn~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(turn)); +// synopsys translate_off +defparam \turn~I .input_async_reset = "none"; +defparam \turn~I .input_power_up = "low"; +defparam \turn~I .input_register_mode = "none"; +defparam \turn~I .input_sync_reset = "none"; +defparam \turn~I .oe_async_reset = "none"; +defparam \turn~I .oe_power_up = "low"; +defparam \turn~I .oe_register_mode = "none"; +defparam \turn~I .oe_sync_reset = "none"; +defparam \turn~I .operation_mode = "input"; +defparam \turn~I .output_async_reset = "none"; +defparam \turn~I .output_power_up = "low"; +defparam \turn~I .output_register_mode = "none"; +defparam \turn~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_M1, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \clk~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\clk~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(clk)); +// synopsys translate_off +defparam \clk~I .input_async_reset = "none"; +defparam \clk~I .input_power_up = "low"; +defparam \clk~I .input_register_mode = "none"; +defparam \clk~I .input_sync_reset = "none"; +defparam \clk~I .oe_async_reset = "none"; +defparam \clk~I .oe_power_up = "low"; +defparam \clk~I .oe_register_mode = "none"; +defparam \clk~I .oe_sync_reset = "none"; +defparam \clk~I .operation_mode = "input"; +defparam \clk~I .output_async_reset = "none"; +defparam \clk~I .output_power_up = "low"; +defparam \clk~I .output_register_mode = "none"; +defparam \clk~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: CLKCTRL_G3 +cycloneii_clkctrl \clk~clkctrl ( + .ena(vcc), + .inclk({gnd,gnd,gnd,\clk~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\clk~clkctrl_outclk )); +// synopsys translate_off +defparam \clk~clkctrl .clock_type = "global clock"; +defparam \clk~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: PIN_AA5, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \sum[0]~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\sum~combout [0]), + .regout(), + .differentialout(), + .linkout(), + .padio(sum[0])); +// synopsys translate_off +defparam \sum[0]~I .input_async_reset = "none"; +defparam \sum[0]~I .input_power_up = "low"; +defparam \sum[0]~I .input_register_mode = "none"; +defparam \sum[0]~I .input_sync_reset = "none"; +defparam \sum[0]~I .oe_async_reset = "none"; +defparam \sum[0]~I .oe_power_up = "low"; +defparam \sum[0]~I .oe_register_mode = "none"; +defparam \sum[0]~I .oe_sync_reset = "none"; +defparam \sum[0]~I .operation_mode = "input"; +defparam \sum[0]~I .output_async_reset = "none"; +defparam \sum[0]~I .output_power_up = "low"; +defparam \sum[0]~I .output_register_mode = "none"; +defparam \sum[0]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_Y3, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \sum[1]~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\sum~combout [1]), + .regout(), + .differentialout(), + .linkout(), + .padio(sum[1])); +// synopsys translate_off +defparam \sum[1]~I .input_async_reset = "none"; +defparam \sum[1]~I .input_power_up = "low"; +defparam \sum[1]~I .input_register_mode = "none"; +defparam \sum[1]~I .input_sync_reset = "none"; +defparam \sum[1]~I .oe_async_reset = "none"; +defparam \sum[1]~I .oe_power_up = "low"; +defparam \sum[1]~I .oe_register_mode = "none"; +defparam \sum[1]~I .oe_sync_reset = "none"; +defparam \sum[1]~I .operation_mode = "input"; +defparam \sum[1]~I .output_async_reset = "none"; +defparam \sum[1]~I .output_power_up = "low"; +defparam \sum[1]~I .output_register_mode = "none"; +defparam \sum[1]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_Y5, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \sum[3]~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\sum~combout [3]), + .regout(), + .differentialout(), + .linkout(), + .padio(sum[3])); +// synopsys translate_off +defparam \sum[3]~I .input_async_reset = "none"; +defparam \sum[3]~I .input_power_up = "low"; +defparam \sum[3]~I .input_register_mode = "none"; +defparam \sum[3]~I .input_sync_reset = "none"; +defparam \sum[3]~I .oe_async_reset = "none"; +defparam \sum[3]~I .oe_power_up = "low"; +defparam \sum[3]~I .oe_register_mode = "none"; +defparam \sum[3]~I .oe_sync_reset = "none"; +defparam \sum[3]~I .operation_mode = "input"; +defparam \sum[3]~I .output_async_reset = "none"; +defparam \sum[3]~I .output_power_up = "low"; +defparam \sum[3]~I .output_register_mode = "none"; +defparam \sum[3]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y1_N0 +cycloneii_lcell_comb \inst|LessThan0~0 ( +// Equation(s): +// \inst|LessThan0~0_combout = (\sum~combout [2]) # ((\sum~combout [0]) # ((\sum~combout [1]) # (\sum~combout [3]))) + + .dataa(\sum~combout [2]), + .datab(\sum~combout [0]), + .datac(\sum~combout [1]), + .datad(\sum~combout [3]), + .cin(gnd), + .combout(\inst|LessThan0~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst|LessThan0~0 .lut_mask = 16'hFFFE; +defparam \inst|LessThan0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: PIN_U8, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \sum[5]~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\sum~combout [5]), + .regout(), + .differentialout(), + .linkout(), + .padio(sum[5])); +// synopsys translate_off +defparam \sum[5]~I .input_async_reset = "none"; +defparam \sum[5]~I .input_power_up = "low"; +defparam \sum[5]~I .input_register_mode = "none"; +defparam \sum[5]~I .input_sync_reset = "none"; +defparam \sum[5]~I .oe_async_reset = "none"; +defparam \sum[5]~I .oe_power_up = "low"; +defparam \sum[5]~I .oe_register_mode = "none"; +defparam \sum[5]~I .oe_sync_reset = "none"; +defparam \sum[5]~I .operation_mode = "input"; +defparam \sum[5]~I .output_async_reset = "none"; +defparam \sum[5]~I .output_power_up = "low"; +defparam \sum[5]~I .output_register_mode = "none"; +defparam \sum[5]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: LCCOMB_X3_Y1_N18 +cycloneii_lcell_comb \inst|LessThan0~1 ( +// Equation(s): +// \inst|LessThan0~1_combout = (\sum~combout [5]) # ((\sum~combout [4] & \inst|LessThan0~0_combout )) + + .dataa(\sum~combout [4]), + .datab(\inst|LessThan0~0_combout ), + .datac(\sum~combout [5]), + .datad(vcc), + .cin(gnd), + .combout(\inst|LessThan0~1_combout ), + .cout()); +// synopsys translate_off +defparam \inst|LessThan0~1 .lut_mask = 16'hF8F8; +defparam \inst|LessThan0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X9_Y1_N22 +cycloneii_lcell_comb \inst|computer:state[0]~0 ( +// Equation(s): +// \inst|computer:state[0]~0_combout = (!\inst|computer:state[1]~regout & ((\inst|computer:state[0]~regout & ((!\inst|LessThan0~1_combout ))) # (!\inst|computer:state[0]~regout & (\turn~combout )))) + + .dataa(\turn~combout ), + .datab(\inst|LessThan0~1_combout ), + .datac(\inst|computer:state[0]~regout ), + .datad(\inst|computer:state[1]~regout ), + .cin(gnd), + .combout(\inst|computer:state[0]~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst|computer:state[0]~0 .lut_mask = 16'h003A; +defparam \inst|computer:state[0]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: PIN_M2, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \rst~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\rst~combout ), + .regout(), + .differentialout(), + .linkout(), + .padio(rst)); +// synopsys translate_off +defparam \rst~I .input_async_reset = "none"; +defparam \rst~I .input_power_up = "low"; +defparam \rst~I .input_register_mode = "none"; +defparam \rst~I .input_sync_reset = "none"; +defparam \rst~I .oe_async_reset = "none"; +defparam \rst~I .oe_power_up = "low"; +defparam \rst~I .oe_register_mode = "none"; +defparam \rst~I .oe_sync_reset = "none"; +defparam \rst~I .operation_mode = "input"; +defparam \rst~I .output_async_reset = "none"; +defparam \rst~I .output_power_up = "low"; +defparam \rst~I .output_register_mode = "none"; +defparam \rst~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: CLKCTRL_G1 +cycloneii_clkctrl \rst~clkctrl ( + .ena(vcc), + .inclk({gnd,gnd,gnd,\rst~combout }), + .clkselect(2'b00), + .devclrn(devclrn), + .devpor(devpor), + .outclk(\rst~clkctrl_outclk )); +// synopsys translate_off +defparam \rst~clkctrl .clock_type = "global clock"; +defparam \rst~clkctrl .ena_register_mode = "none"; +// synopsys translate_on + +// Location: LCFF_X9_Y1_N23 +cycloneii_lcell_ff \inst|computer:state[0] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst|computer:state[0]~0_combout ), + .sdata(gnd), + .aclr(\rst~clkctrl_outclk ), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst|computer:state[0]~regout )); + +// Location: LCCOMB_X9_Y1_N28 +cycloneii_lcell_comb \inst|computer:state[1]~0 ( +// Equation(s): +// \inst|computer:state[1]~0_combout = (\inst|LessThan0~1_combout & (!\inst|computer:state[1]~regout & \inst|computer:state[0]~regout )) + + .dataa(vcc), + .datab(\inst|LessThan0~1_combout ), + .datac(\inst|computer:state[1]~regout ), + .datad(\inst|computer:state[0]~regout ), + .cin(gnd), + .combout(\inst|computer:state[1]~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst|computer:state[1]~0 .lut_mask = 16'h0C00; +defparam \inst|computer:state[1]~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X9_Y1_N29 +cycloneii_lcell_ff \inst|computer:state[1] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst|computer:state[1]~0_combout ), + .sdata(gnd), + .aclr(\rst~clkctrl_outclk ), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst|computer:state[1]~regout )); + +// Location: LCCOMB_X9_Y1_N16 +cycloneii_lcell_comb \inst|Mux0~0 ( +// Equation(s): +// \inst|Mux0~0_combout = (!\inst|LessThan0~1_combout & (!\inst|computer:state[1]~regout & \inst|computer:state[0]~regout )) + + .dataa(vcc), + .datab(\inst|LessThan0~1_combout ), + .datac(\inst|computer:state[1]~regout ), + .datad(\inst|computer:state[0]~regout ), + .cin(gnd), + .combout(\inst|Mux0~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst|Mux0~0 .lut_mask = 16'h0300; +defparam \inst|Mux0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X9_Y1_N17 +cycloneii_lcell_ff \inst|hit ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst|Mux0~0_combout ), + .sdata(gnd), + .aclr(\rst~clkctrl_outclk ), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst|hit~regout )); + +// Location: LCCOMB_X9_Y1_N18 +cycloneii_lcell_comb \inst|Mux1~0 ( +// Equation(s): +// \inst|Mux1~0_combout = (!\inst|computer:state[0]~regout & \inst|computer:state[1]~regout ) + + .dataa(vcc), + .datab(\inst|computer:state[0]~regout ), + .datac(vcc), + .datad(\inst|computer:state[1]~regout ), + .cin(gnd), + .combout(\inst|Mux1~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst|Mux1~0 .lut_mask = 16'h3300; +defparam \inst|Mux1~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X9_Y1_N19 +cycloneii_lcell_ff \inst|done ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst|Mux1~0_combout ), + .sdata(gnd), + .aclr(\rst~clkctrl_outclk ), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst|done~regout )); + +// Location: PIN_AB3, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \player_sum[5]~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\player_sum~combout [5]), + .regout(), + .differentialout(), + .linkout(), + .padio(player_sum[5])); +// synopsys translate_off +defparam \player_sum[5]~I .input_async_reset = "none"; +defparam \player_sum[5]~I .input_power_up = "low"; +defparam \player_sum[5]~I .input_register_mode = "none"; +defparam \player_sum[5]~I .input_sync_reset = "none"; +defparam \player_sum[5]~I .oe_async_reset = "none"; +defparam \player_sum[5]~I .oe_power_up = "low"; +defparam \player_sum[5]~I .oe_register_mode = "none"; +defparam \player_sum[5]~I .oe_sync_reset = "none"; +defparam \player_sum[5]~I .operation_mode = "input"; +defparam \player_sum[5]~I .output_async_reset = "none"; +defparam \player_sum[5]~I .output_power_up = "low"; +defparam \player_sum[5]~I .output_register_mode = "none"; +defparam \player_sum[5]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_AA3, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \player_sum[2]~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\player_sum~combout [2]), + .regout(), + .differentialout(), + .linkout(), + .padio(player_sum[2])); +// synopsys translate_off +defparam \player_sum[2]~I .input_async_reset = "none"; +defparam \player_sum[2]~I .input_power_up = "low"; +defparam \player_sum[2]~I .input_register_mode = "none"; +defparam \player_sum[2]~I .input_sync_reset = "none"; +defparam \player_sum[2]~I .oe_async_reset = "none"; +defparam \player_sum[2]~I .oe_power_up = "low"; +defparam \player_sum[2]~I .oe_register_mode = "none"; +defparam \player_sum[2]~I .oe_sync_reset = "none"; +defparam \player_sum[2]~I .operation_mode = "input"; +defparam \player_sum[2]~I .output_async_reset = "none"; +defparam \player_sum[2]~I .output_power_up = "low"; +defparam \player_sum[2]~I .output_register_mode = "none"; +defparam \player_sum[2]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_Y7, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \player_sum[3]~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\player_sum~combout [3]), + .regout(), + .differentialout(), + .linkout(), + .padio(player_sum[3])); +// synopsys translate_off +defparam \player_sum[3]~I .input_async_reset = "none"; +defparam \player_sum[3]~I .input_power_up = "low"; +defparam \player_sum[3]~I .input_register_mode = "none"; +defparam \player_sum[3]~I .input_sync_reset = "none"; +defparam \player_sum[3]~I .oe_async_reset = "none"; +defparam \player_sum[3]~I .oe_power_up = "low"; +defparam \player_sum[3]~I .oe_register_mode = "none"; +defparam \player_sum[3]~I .oe_sync_reset = "none"; +defparam \player_sum[3]~I .operation_mode = "input"; +defparam \player_sum[3]~I .output_async_reset = "none"; +defparam \player_sum[3]~I .output_power_up = "low"; +defparam \player_sum[3]~I .output_register_mode = "none"; +defparam \player_sum[3]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_AA6, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \player_sum[1]~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\player_sum~combout [1]), + .regout(), + .differentialout(), + .linkout(), + .padio(player_sum[1])); +// synopsys translate_off +defparam \player_sum[1]~I .input_async_reset = "none"; +defparam \player_sum[1]~I .input_power_up = "low"; +defparam \player_sum[1]~I .input_register_mode = "none"; +defparam \player_sum[1]~I .input_sync_reset = "none"; +defparam \player_sum[1]~I .oe_async_reset = "none"; +defparam \player_sum[1]~I .oe_power_up = "low"; +defparam \player_sum[1]~I .oe_register_mode = "none"; +defparam \player_sum[1]~I .oe_sync_reset = "none"; +defparam \player_sum[1]~I .operation_mode = "input"; +defparam \player_sum[1]~I .output_async_reset = "none"; +defparam \player_sum[1]~I .output_power_up = "low"; +defparam \player_sum[1]~I .output_register_mode = "none"; +defparam \player_sum[1]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y1_N14 +cycloneii_lcell_comb \inst1|p_win~2 ( +// Equation(s): +// \inst1|p_win~2_combout = (\player_sum~combout [4] & ((\player_sum~combout [3]) # ((\player_sum~combout [2] & \player_sum~combout [1])))) + + .dataa(\player_sum~combout [4]), + .datab(\player_sum~combout [2]), + .datac(\player_sum~combout [3]), + .datad(\player_sum~combout [1]), + .cin(gnd), + .combout(\inst1|p_win~2_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|p_win~2 .lut_mask = 16'hA8A0; +defparam \inst1|p_win~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y1_N2 +cycloneii_lcell_comb \inst1|p_win~6 ( +// Equation(s): +// \inst1|p_win~6_combout = (\player_sum~combout [5]) # (\inst1|p_win~2_combout ) + + .dataa(vcc), + .datab(vcc), + .datac(\player_sum~combout [5]), + .datad(\inst1|p_win~2_combout ), + .cin(gnd), + .combout(\inst1|p_win~6_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|p_win~6 .lut_mask = 16'hFFF0; +defparam \inst1|p_win~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X1_Y1_N7 +cycloneii_lcell_ff \inst1|dealer:p_win ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst1|p_win~7_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst1|dealer:p_win~regout )); + +// Location: PIN_Y6, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \sum[4]~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\sum~combout [4]), + .regout(), + .differentialout(), + .linkout(), + .padio(sum[4])); +// synopsys translate_off +defparam \sum[4]~I .input_async_reset = "none"; +defparam \sum[4]~I .input_power_up = "low"; +defparam \sum[4]~I .input_register_mode = "none"; +defparam \sum[4]~I .input_sync_reset = "none"; +defparam \sum[4]~I .oe_async_reset = "none"; +defparam \sum[4]~I .oe_power_up = "low"; +defparam \sum[4]~I .oe_register_mode = "none"; +defparam \sum[4]~I .oe_sync_reset = "none"; +defparam \sum[4]~I .operation_mode = "input"; +defparam \sum[4]~I .output_async_reset = "none"; +defparam \sum[4]~I .output_power_up = "low"; +defparam \sum[4]~I .output_register_mode = "none"; +defparam \sum[4]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: LCFF_X2_Y1_N9 +cycloneii_lcell_ff \inst|sum_out[4] ( + .clk(\clk~clkctrl_outclk ), + .datain(gnd), + .sdata(\sum~combout [4]), + .aclr(\rst~clkctrl_outclk ), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst|sum_out [4])); + +// Location: PIN_AB5, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \sum[2]~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\sum~combout [2]), + .regout(), + .differentialout(), + .linkout(), + .padio(sum[2])); +// synopsys translate_off +defparam \sum[2]~I .input_async_reset = "none"; +defparam \sum[2]~I .input_power_up = "low"; +defparam \sum[2]~I .input_register_mode = "none"; +defparam \sum[2]~I .input_sync_reset = "none"; +defparam \sum[2]~I .oe_async_reset = "none"; +defparam \sum[2]~I .oe_power_up = "low"; +defparam \sum[2]~I .oe_register_mode = "none"; +defparam \sum[2]~I .oe_sync_reset = "none"; +defparam \sum[2]~I .operation_mode = "input"; +defparam \sum[2]~I .output_async_reset = "none"; +defparam \sum[2]~I .output_power_up = "low"; +defparam \sum[2]~I .output_register_mode = "none"; +defparam \sum[2]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: LCFF_X2_Y1_N13 +cycloneii_lcell_ff \inst|sum_out[2] ( + .clk(\clk~clkctrl_outclk ), + .datain(gnd), + .sdata(\sum~combout [2]), + .aclr(\rst~clkctrl_outclk ), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst|sum_out [2])); + +// Location: LCFF_X2_Y1_N7 +cycloneii_lcell_ff \inst|sum_out[3] ( + .clk(\clk~clkctrl_outclk ), + .datain(gnd), + .sdata(\sum~combout [3]), + .aclr(\rst~clkctrl_outclk ), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst|sum_out [3])); + +// Location: LCCOMB_X2_Y1_N12 +cycloneii_lcell_comb \inst1|Equal0~1 ( +// Equation(s): +// \inst1|Equal0~1_combout = (\player_sum~combout [3] & (\inst|sum_out [3] & (\player_sum~combout [2] $ (!\inst|sum_out [2])))) # (!\player_sum~combout [3] & (!\inst|sum_out [3] & (\player_sum~combout [2] $ (!\inst|sum_out [2])))) + + .dataa(\player_sum~combout [3]), + .datab(\player_sum~combout [2]), + .datac(\inst|sum_out [2]), + .datad(\inst|sum_out [3]), + .cin(gnd), + .combout(\inst1|Equal0~1_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|Equal0~1 .lut_mask = 16'h8241; +defparam \inst1|Equal0~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: PIN_Y4, I/O Standard: 3.3-V LVTTL, Current Strength: Default +cycloneii_io \player_sum[0]~I ( + .datain(gnd), + .oe(gnd), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(\player_sum~combout [0]), + .regout(), + .differentialout(), + .linkout(), + .padio(player_sum[0])); +// synopsys translate_off +defparam \player_sum[0]~I .input_async_reset = "none"; +defparam \player_sum[0]~I .input_power_up = "low"; +defparam \player_sum[0]~I .input_register_mode = "none"; +defparam \player_sum[0]~I .input_sync_reset = "none"; +defparam \player_sum[0]~I .oe_async_reset = "none"; +defparam \player_sum[0]~I .oe_power_up = "low"; +defparam \player_sum[0]~I .oe_register_mode = "none"; +defparam \player_sum[0]~I .oe_sync_reset = "none"; +defparam \player_sum[0]~I .operation_mode = "input"; +defparam \player_sum[0]~I .output_async_reset = "none"; +defparam \player_sum[0]~I .output_power_up = "low"; +defparam \player_sum[0]~I .output_register_mode = "none"; +defparam \player_sum[0]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: LCFF_X2_Y1_N29 +cycloneii_lcell_ff \inst|sum_out[0] ( + .clk(\clk~clkctrl_outclk ), + .datain(gnd), + .sdata(\sum~combout [0]), + .aclr(\rst~clkctrl_outclk ), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst|sum_out [0])); + +// Location: LCFF_X2_Y1_N31 +cycloneii_lcell_ff \inst|sum_out[1] ( + .clk(\clk~clkctrl_outclk ), + .datain(gnd), + .sdata(\sum~combout [1]), + .aclr(\rst~clkctrl_outclk ), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst|sum_out [1])); + +// Location: LCCOMB_X2_Y1_N28 +cycloneii_lcell_comb \inst1|Equal0~0 ( +// Equation(s): +// \inst1|Equal0~0_combout = (\player_sum~combout [1] & (\inst|sum_out [1] & (\player_sum~combout [0] $ (!\inst|sum_out [0])))) # (!\player_sum~combout [1] & (!\inst|sum_out [1] & (\player_sum~combout [0] $ (!\inst|sum_out [0])))) + + .dataa(\player_sum~combout [1]), + .datab(\player_sum~combout [0]), + .datac(\inst|sum_out [0]), + .datad(\inst|sum_out [1]), + .cin(gnd), + .combout(\inst1|Equal0~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|Equal0~0 .lut_mask = 16'h8241; +defparam \inst1|Equal0~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y1_N18 +cycloneii_lcell_comb \inst1|Equal0~2 ( +// Equation(s): +// \inst1|Equal0~2_combout = (\inst1|Equal0~1_combout & (\inst1|Equal0~0_combout & (\player_sum~combout [4] $ (!\inst|sum_out [4])))) + + .dataa(\player_sum~combout [4]), + .datab(\inst|sum_out [4]), + .datac(\inst1|Equal0~1_combout ), + .datad(\inst1|Equal0~0_combout ), + .cin(gnd), + .combout(\inst1|Equal0~2_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|Equal0~2 .lut_mask = 16'h9000; +defparam \inst1|Equal0~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X2_Y1_N11 +cycloneii_lcell_ff \inst|sum_out[5] ( + .clk(\clk~clkctrl_outclk ), + .datain(gnd), + .sdata(\sum~combout [5]), + .aclr(\rst~clkctrl_outclk ), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst|sum_out [5])); + +// Location: LCCOMB_X2_Y1_N16 +cycloneii_lcell_comb \inst1|LessThan3~1 ( +// Equation(s): +// \inst1|LessThan3~1_cout = CARRY((!\player_sum~combout [0] & \inst|sum_out [0])) + + .dataa(\player_sum~combout [0]), + .datab(\inst|sum_out [0]), + .datac(vcc), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\inst1|LessThan3~1_cout )); +// synopsys translate_off +defparam \inst1|LessThan3~1 .lut_mask = 16'h0044; +defparam \inst1|LessThan3~1 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y1_N18 +cycloneii_lcell_comb \inst1|LessThan3~3 ( +// Equation(s): +// \inst1|LessThan3~3_cout = CARRY((\player_sum~combout [1] & ((!\inst1|LessThan3~1_cout ) # (!\inst|sum_out [1]))) # (!\player_sum~combout [1] & (!\inst|sum_out [1] & !\inst1|LessThan3~1_cout ))) + + .dataa(\player_sum~combout [1]), + .datab(\inst|sum_out [1]), + .datac(vcc), + .datad(vcc), + .cin(\inst1|LessThan3~1_cout ), + .combout(), + .cout(\inst1|LessThan3~3_cout )); +// synopsys translate_off +defparam \inst1|LessThan3~3 .lut_mask = 16'h002B; +defparam \inst1|LessThan3~3 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y1_N20 +cycloneii_lcell_comb \inst1|LessThan3~5 ( +// Equation(s): +// \inst1|LessThan3~5_cout = CARRY((\inst|sum_out [2] & ((!\inst1|LessThan3~3_cout ) # (!\player_sum~combout [2]))) # (!\inst|sum_out [2] & (!\player_sum~combout [2] & !\inst1|LessThan3~3_cout ))) + + .dataa(\inst|sum_out [2]), + .datab(\player_sum~combout [2]), + .datac(vcc), + .datad(vcc), + .cin(\inst1|LessThan3~3_cout ), + .combout(), + .cout(\inst1|LessThan3~5_cout )); +// synopsys translate_off +defparam \inst1|LessThan3~5 .lut_mask = 16'h002B; +defparam \inst1|LessThan3~5 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y1_N22 +cycloneii_lcell_comb \inst1|LessThan3~7 ( +// Equation(s): +// \inst1|LessThan3~7_cout = CARRY((\inst|sum_out [3] & (\player_sum~combout [3] & !\inst1|LessThan3~5_cout )) # (!\inst|sum_out [3] & ((\player_sum~combout [3]) # (!\inst1|LessThan3~5_cout )))) + + .dataa(\inst|sum_out [3]), + .datab(\player_sum~combout [3]), + .datac(vcc), + .datad(vcc), + .cin(\inst1|LessThan3~5_cout ), + .combout(), + .cout(\inst1|LessThan3~7_cout )); +// synopsys translate_off +defparam \inst1|LessThan3~7 .lut_mask = 16'h004D; +defparam \inst1|LessThan3~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y1_N24 +cycloneii_lcell_comb \inst1|LessThan3~9 ( +// Equation(s): +// \inst1|LessThan3~9_cout = CARRY((\player_sum~combout [4] & (\inst|sum_out [4] & !\inst1|LessThan3~7_cout )) # (!\player_sum~combout [4] & ((\inst|sum_out [4]) # (!\inst1|LessThan3~7_cout )))) + + .dataa(\player_sum~combout [4]), + .datab(\inst|sum_out [4]), + .datac(vcc), + .datad(vcc), + .cin(\inst1|LessThan3~7_cout ), + .combout(), + .cout(\inst1|LessThan3~9_cout )); +// synopsys translate_off +defparam \inst1|LessThan3~9 .lut_mask = 16'h004D; +defparam \inst1|LessThan3~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y1_N26 +cycloneii_lcell_comb \inst1|LessThan3~10 ( +// Equation(s): +// \inst1|LessThan3~10_combout = (\player_sum~combout [5] & (\inst1|LessThan3~9_cout & \inst|sum_out [5])) # (!\player_sum~combout [5] & ((\inst1|LessThan3~9_cout ) # (\inst|sum_out [5]))) + + .dataa(\player_sum~combout [5]), + .datab(vcc), + .datac(vcc), + .datad(\inst|sum_out [5]), + .cin(\inst1|LessThan3~9_cout ), + .combout(\inst1|LessThan3~10_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|LessThan3~10 .lut_mask = 16'hF550; +defparam \inst1|LessThan3~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y1_N20 +cycloneii_lcell_comb \inst1|p_win~3 ( +// Equation(s): +// \inst1|p_win~3_combout = (\player_sum~combout [5]) # (\inst1|LessThan3~10_combout ) + + .dataa(vcc), + .datab(\player_sum~combout [5]), + .datac(\inst1|LessThan3~10_combout ), + .datad(vcc), + .cin(gnd), + .combout(\inst1|p_win~3_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|p_win~3 .lut_mask = 16'hFCFC; +defparam \inst1|p_win~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y1_N0 +cycloneii_lcell_comb \inst1|LessThan2~1 ( +// Equation(s): +// \inst1|LessThan2~1_cout = CARRY((\player_sum~combout [0] & !\inst|sum_out [0])) + + .dataa(\player_sum~combout [0]), + .datab(\inst|sum_out [0]), + .datac(vcc), + .datad(vcc), + .cin(gnd), + .combout(), + .cout(\inst1|LessThan2~1_cout )); +// synopsys translate_off +defparam \inst1|LessThan2~1 .lut_mask = 16'h0022; +defparam \inst1|LessThan2~1 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y1_N2 +cycloneii_lcell_comb \inst1|LessThan2~3 ( +// Equation(s): +// \inst1|LessThan2~3_cout = CARRY((\player_sum~combout [1] & (\inst|sum_out [1] & !\inst1|LessThan2~1_cout )) # (!\player_sum~combout [1] & ((\inst|sum_out [1]) # (!\inst1|LessThan2~1_cout )))) + + .dataa(\player_sum~combout [1]), + .datab(\inst|sum_out [1]), + .datac(vcc), + .datad(vcc), + .cin(\inst1|LessThan2~1_cout ), + .combout(), + .cout(\inst1|LessThan2~3_cout )); +// synopsys translate_off +defparam \inst1|LessThan2~3 .lut_mask = 16'h004D; +defparam \inst1|LessThan2~3 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y1_N4 +cycloneii_lcell_comb \inst1|LessThan2~5 ( +// Equation(s): +// \inst1|LessThan2~5_cout = CARRY((\inst|sum_out [2] & (\player_sum~combout [2] & !\inst1|LessThan2~3_cout )) # (!\inst|sum_out [2] & ((\player_sum~combout [2]) # (!\inst1|LessThan2~3_cout )))) + + .dataa(\inst|sum_out [2]), + .datab(\player_sum~combout [2]), + .datac(vcc), + .datad(vcc), + .cin(\inst1|LessThan2~3_cout ), + .combout(), + .cout(\inst1|LessThan2~5_cout )); +// synopsys translate_off +defparam \inst1|LessThan2~5 .lut_mask = 16'h004D; +defparam \inst1|LessThan2~5 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y1_N6 +cycloneii_lcell_comb \inst1|LessThan2~7 ( +// Equation(s): +// \inst1|LessThan2~7_cout = CARRY((\inst|sum_out [3] & ((!\inst1|LessThan2~5_cout ) # (!\player_sum~combout [3]))) # (!\inst|sum_out [3] & (!\player_sum~combout [3] & !\inst1|LessThan2~5_cout ))) + + .dataa(\inst|sum_out [3]), + .datab(\player_sum~combout [3]), + .datac(vcc), + .datad(vcc), + .cin(\inst1|LessThan2~5_cout ), + .combout(), + .cout(\inst1|LessThan2~7_cout )); +// synopsys translate_off +defparam \inst1|LessThan2~7 .lut_mask = 16'h002B; +defparam \inst1|LessThan2~7 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y1_N8 +cycloneii_lcell_comb \inst1|LessThan2~9 ( +// Equation(s): +// \inst1|LessThan2~9_cout = CARRY((\player_sum~combout [4] & ((!\inst1|LessThan2~7_cout ) # (!\inst|sum_out [4]))) # (!\player_sum~combout [4] & (!\inst|sum_out [4] & !\inst1|LessThan2~7_cout ))) + + .dataa(\player_sum~combout [4]), + .datab(\inst|sum_out [4]), + .datac(vcc), + .datad(vcc), + .cin(\inst1|LessThan2~7_cout ), + .combout(), + .cout(\inst1|LessThan2~9_cout )); +// synopsys translate_off +defparam \inst1|LessThan2~9 .lut_mask = 16'h002B; +defparam \inst1|LessThan2~9 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y1_N10 +cycloneii_lcell_comb \inst1|LessThan2~10 ( +// Equation(s): +// \inst1|LessThan2~10_combout = (\player_sum~combout [5] & ((\inst1|LessThan2~9_cout ) # (!\inst|sum_out [5]))) # (!\player_sum~combout [5] & (\inst1|LessThan2~9_cout & !\inst|sum_out [5])) + + .dataa(\player_sum~combout [5]), + .datab(vcc), + .datac(vcc), + .datad(\inst|sum_out [5]), + .cin(\inst1|LessThan2~9_cout ), + .combout(\inst1|LessThan2~10_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|LessThan2~10 .lut_mask = 16'hA0FA; +defparam \inst1|LessThan2~10 .sum_lutc_input = "cin"; +// synopsys translate_on + +// Location: LCCOMB_X2_Y1_N30 +cycloneii_lcell_comb \inst1|p_win~0 ( +// Equation(s): +// \inst1|p_win~0_combout = (\inst|sum_out [4] & ((\inst|sum_out [3]) # ((\inst|sum_out [2] & \inst|sum_out [1])))) + + .dataa(\inst|sum_out [2]), + .datab(\inst|sum_out [4]), + .datac(\inst|sum_out [1]), + .datad(\inst|sum_out [3]), + .cin(gnd), + .combout(\inst1|p_win~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|p_win~0 .lut_mask = 16'hCC80; +defparam \inst1|p_win~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y1_N30 +cycloneii_lcell_comb \inst1|p_win~4 ( +// Equation(s): +// \inst1|p_win~4_combout = (!\inst|sum_out [5] & (!\inst1|LessThan2~10_combout & !\inst1|p_win~0_combout )) + + .dataa(\inst|sum_out [5]), + .datab(vcc), + .datac(\inst1|LessThan2~10_combout ), + .datad(\inst1|p_win~0_combout ), + .cin(gnd), + .combout(\inst1|p_win~4_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|p_win~4 .lut_mask = 16'h0005; +defparam \inst1|p_win~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y1_N0 +cycloneii_lcell_comb \inst1|p_win~5 ( +// Equation(s): +// \inst1|p_win~5_combout = (\inst1|p_win~2_combout ) # ((\inst1|Equal0~2_combout ) # ((\inst1|p_win~3_combout ) # (!\inst1|p_win~4_combout ))) + + .dataa(\inst1|p_win~2_combout ), + .datab(\inst1|Equal0~2_combout ), + .datac(\inst1|p_win~3_combout ), + .datad(\inst1|p_win~4_combout ), + .cin(gnd), + .combout(\inst1|p_win~5_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|p_win~5 .lut_mask = 16'hFEFF; +defparam \inst1|p_win~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y1_N6 +cycloneii_lcell_comb \inst1|p_win~7 ( +// Equation(s): +// \inst1|p_win~7_combout = (\inst1|p_win~5_combout & (\inst1|p_win~1_combout & (!\inst1|p_win~6_combout ))) # (!\inst1|p_win~5_combout & (((\inst1|dealer:p_win~regout )))) + + .dataa(\inst1|p_win~1_combout ), + .datab(\inst1|p_win~6_combout ), + .datac(\inst1|dealer:p_win~regout ), + .datad(\inst1|p_win~5_combout ), + .cin(gnd), + .combout(\inst1|p_win~7_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|p_win~7 .lut_mask = 16'h22F0; +defparam \inst1|p_win~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y1_N24 +cycloneii_lcell_comb \inst1|player_wins~feeder ( +// Equation(s): +// \inst1|player_wins~feeder_combout = \inst1|p_win~7_combout + + .dataa(vcc), + .datab(vcc), + .datac(vcc), + .datad(\inst1|p_win~7_combout ), + .cin(gnd), + .combout(\inst1|player_wins~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|player_wins~feeder .lut_mask = 16'hFF00; +defparam \inst1|player_wins~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X1_Y1_N25 +cycloneii_lcell_ff \inst1|player_wins ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst1|player_wins~feeder_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst1|player_wins~regout )); + +// Location: LCCOMB_X1_Y1_N14 +cycloneii_lcell_comb \inst1|d_win~0 ( +// Equation(s): +// \inst1|d_win~0_combout = (\inst1|p_win~5_combout & (((\inst1|p_win~6_combout ) # (\inst1|p_win~4_combout )))) # (!\inst1|p_win~5_combout & (\inst1|dealer:d_win~regout )) + + .dataa(\inst1|dealer:d_win~regout ), + .datab(\inst1|p_win~6_combout ), + .datac(\inst1|p_win~4_combout ), + .datad(\inst1|p_win~5_combout ), + .cin(gnd), + .combout(\inst1|d_win~0_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|d_win~0 .lut_mask = 16'hFCAA; +defparam \inst1|d_win~0 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X1_Y1_N15 +cycloneii_lcell_ff \inst1|dealer_wins ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst1|d_win~0_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(gnd), + .sload(gnd), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst1|dealer_wins~regout )); + +// Location: LCCOMB_X1_Y1_N8 +cycloneii_lcell_comb \inst1|p_win~1 ( +// Equation(s): +// \inst1|p_win~1_combout = (\inst|sum_out [5]) # ((\inst1|p_win~0_combout ) # ((\inst1|LessThan2~10_combout ) # (!\inst1|LessThan3~10_combout ))) + + .dataa(\inst|sum_out [5]), + .datab(\inst1|p_win~0_combout ), + .datac(\inst1|LessThan3~10_combout ), + .datad(\inst1|LessThan2~10_combout ), + .cin(gnd), + .combout(\inst1|p_win~1_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|p_win~1 .lut_mask = 16'hFFEF; +defparam \inst1|p_win~1 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y1_N26 +cycloneii_lcell_comb \inst1|led_display1~6 ( +// Equation(s): +// \inst1|led_display1~6_combout = (\inst1|p_win~2_combout ) # ((\player_sum~combout [5]) # ((!\inst1|p_win~1_combout ) # (!\inst1|p_win~4_combout ))) + + .dataa(\inst1|p_win~2_combout ), + .datab(\player_sum~combout [5]), + .datac(\inst1|p_win~4_combout ), + .datad(\inst1|p_win~1_combout ), + .cin(gnd), + .combout(\inst1|led_display1~6_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|led_display1~6 .lut_mask = 16'hEFFF; +defparam \inst1|led_display1~6 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y1_N12 +cycloneii_lcell_comb \inst1|led_display1~4 ( +// Equation(s): +// \inst1|led_display1~4_combout = (\inst1|p_win~5_combout & (((\inst1|led_display1~6_combout )))) # (!\inst1|p_win~5_combout & (((!\inst1|dealer:p_win~regout )) # (!\inst1|dealer:d_win~regout ))) + + .dataa(\inst1|dealer:d_win~regout ), + .datab(\inst1|p_win~5_combout ), + .datac(\inst1|dealer:p_win~regout ), + .datad(\inst1|led_display1~6_combout ), + .cin(gnd), + .combout(\inst1|led_display1~4_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|led_display1~4 .lut_mask = 16'hDF13; +defparam \inst1|led_display1~4 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X1_Y1_N5 +cycloneii_lcell_ff \inst1|dealer:d_win ( + .clk(\clk~clkctrl_outclk ), + .datain(gnd), + .sdata(\inst1|d_win~0_combout ), + .aclr(gnd), + .sclr(gnd), + .sload(vcc), + .ena(vcc), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst1|dealer:d_win~regout )); + +// Location: LCCOMB_X1_Y1_N28 +cycloneii_lcell_comb \inst1|led_display1[0]~7 ( +// Equation(s): +// \inst1|led_display1[0]~7_combout = (\inst1|p_win~2_combout ) # ((\player_sum~combout [5]) # ((\inst1|p_win~1_combout ) # (\inst1|p_win~4_combout ))) + + .dataa(\inst1|p_win~2_combout ), + .datab(\player_sum~combout [5]), + .datac(\inst1|p_win~1_combout ), + .datad(\inst1|p_win~4_combout ), + .cin(gnd), + .combout(\inst1|led_display1[0]~7_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|led_display1[0]~7 .lut_mask = 16'hFFFE; +defparam \inst1|led_display1[0]~7 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y1_N4 +cycloneii_lcell_comb \inst1|led_display1[0]~5 ( +// Equation(s): +// \inst1|led_display1[0]~5_combout = (\inst1|p_win~5_combout & (((\inst1|led_display1[0]~7_combout )))) # (!\inst1|p_win~5_combout & ((\inst1|dealer:p_win~regout ) # ((\inst1|dealer:d_win~regout )))) + + .dataa(\inst1|dealer:p_win~regout ), + .datab(\inst1|p_win~5_combout ), + .datac(\inst1|dealer:d_win~regout ), + .datad(\inst1|led_display1[0]~7_combout ), + .cin(gnd), + .combout(\inst1|led_display1[0]~5_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|led_display1[0]~5 .lut_mask = 16'hFE32; +defparam \inst1|led_display1[0]~5 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X1_Y1_N13 +cycloneii_lcell_ff \inst1|led_display1[0] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst1|led_display1~4_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\inst1|led_display1[0]~5_combout ), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst1|led_display1 [0])); + +// Location: LCCOMB_X1_Y1_N10 +cycloneii_lcell_comb \inst1|led_display3~3 ( +// Equation(s): +// \inst1|led_display3~3_combout = (\inst1|p_win~2_combout ) # ((\player_sum~combout [5]) # ((\inst1|p_win~4_combout ) # (!\inst1|p_win~1_combout ))) + + .dataa(\inst1|p_win~2_combout ), + .datab(\player_sum~combout [5]), + .datac(\inst1|p_win~4_combout ), + .datad(\inst1|p_win~1_combout ), + .cin(gnd), + .combout(\inst1|led_display3~3_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|led_display3~3 .lut_mask = 16'hFEFF; +defparam \inst1|led_display3~3 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCCOMB_X1_Y1_N22 +cycloneii_lcell_comb \inst1|led_display3~2 ( +// Equation(s): +// \inst1|led_display3~2_combout = (\inst1|p_win~5_combout & (((\inst1|led_display3~3_combout )))) # (!\inst1|p_win~5_combout & ((\inst1|dealer:d_win~regout ) # ((!\inst1|dealer:p_win~regout )))) + + .dataa(\inst1|dealer:d_win~regout ), + .datab(\inst1|p_win~5_combout ), + .datac(\inst1|dealer:p_win~regout ), + .datad(\inst1|led_display3~3_combout ), + .cin(gnd), + .combout(\inst1|led_display3~2_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|led_display3~2 .lut_mask = 16'hEF23; +defparam \inst1|led_display3~2 .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X1_Y1_N23 +cycloneii_lcell_ff \inst1|led_display3[1] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst1|led_display3~2_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\inst1|led_display1[0]~5_combout ), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst1|led_display3 [1])); + +// Location: LCCOMB_X1_Y1_N16 +cycloneii_lcell_comb \inst1|led_display4[3]~feeder ( +// Equation(s): +// \inst1|led_display4[3]~feeder_combout = \inst1|p_win~7_combout + + .dataa(vcc), + .datab(vcc), + .datac(vcc), + .datad(\inst1|p_win~7_combout ), + .cin(gnd), + .combout(\inst1|led_display4[3]~feeder_combout ), + .cout()); +// synopsys translate_off +defparam \inst1|led_display4[3]~feeder .lut_mask = 16'hFF00; +defparam \inst1|led_display4[3]~feeder .sum_lutc_input = "datac"; +// synopsys translate_on + +// Location: LCFF_X1_Y1_N17 +cycloneii_lcell_ff \inst1|led_display4[3] ( + .clk(\clk~clkctrl_outclk ), + .datain(\inst1|led_display4[3]~feeder_combout ), + .sdata(gnd), + .aclr(gnd), + .sclr(gnd), + .sload(gnd), + .ena(\inst1|led_display1[0]~5_combout ), + .devclrn(devclrn), + .devpor(devpor), + .regout(\inst1|led_display4 [3])); + +// Location: PIN_W7, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \hit~I ( + .datain(\inst|hit~regout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(hit)); +// synopsys translate_off +defparam \hit~I .input_async_reset = "none"; +defparam \hit~I .input_power_up = "low"; +defparam \hit~I .input_register_mode = "none"; +defparam \hit~I .input_sync_reset = "none"; +defparam \hit~I .oe_async_reset = "none"; +defparam \hit~I .oe_power_up = "low"; +defparam \hit~I .oe_register_mode = "none"; +defparam \hit~I .oe_sync_reset = "none"; +defparam \hit~I .operation_mode = "output"; +defparam \hit~I .output_async_reset = "none"; +defparam \hit~I .output_power_up = "low"; +defparam \hit~I .output_register_mode = "none"; +defparam \hit~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_V9, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \done~I ( + .datain(\inst|done~regout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(done)); +// synopsys translate_off +defparam \done~I .input_async_reset = "none"; +defparam \done~I .input_power_up = "low"; +defparam \done~I .input_register_mode = "none"; +defparam \done~I .input_sync_reset = "none"; +defparam \done~I .oe_async_reset = "none"; +defparam \done~I .oe_power_up = "low"; +defparam \done~I .oe_register_mode = "none"; +defparam \done~I .oe_sync_reset = "none"; +defparam \done~I .operation_mode = "output"; +defparam \done~I .output_async_reset = "none"; +defparam \done~I .output_power_up = "low"; +defparam \done~I .output_register_mode = "none"; +defparam \done~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_W4, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \player_wins~I ( + .datain(\inst1|player_wins~regout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(player_wins)); +// synopsys translate_off +defparam \player_wins~I .input_async_reset = "none"; +defparam \player_wins~I .input_power_up = "low"; +defparam \player_wins~I .input_register_mode = "none"; +defparam \player_wins~I .input_sync_reset = "none"; +defparam \player_wins~I .oe_async_reset = "none"; +defparam \player_wins~I .oe_power_up = "low"; +defparam \player_wins~I .oe_register_mode = "none"; +defparam \player_wins~I .oe_sync_reset = "none"; +defparam \player_wins~I .operation_mode = "output"; +defparam \player_wins~I .output_async_reset = "none"; +defparam \player_wins~I .output_power_up = "low"; +defparam \player_wins~I .output_register_mode = "none"; +defparam \player_wins~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_W3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \dealer_wins~I ( + .datain(\inst1|dealer_wins~regout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(dealer_wins)); +// synopsys translate_off +defparam \dealer_wins~I .input_async_reset = "none"; +defparam \dealer_wins~I .input_power_up = "low"; +defparam \dealer_wins~I .input_register_mode = "none"; +defparam \dealer_wins~I .input_sync_reset = "none"; +defparam \dealer_wins~I .oe_async_reset = "none"; +defparam \dealer_wins~I .oe_power_up = "low"; +defparam \dealer_wins~I .oe_register_mode = "none"; +defparam \dealer_wins~I .oe_sync_reset = "none"; +defparam \dealer_wins~I .operation_mode = "output"; +defparam \dealer_wins~I .output_async_reset = "none"; +defparam \dealer_wins~I .output_power_up = "low"; +defparam \dealer_wins~I .output_register_mode = "none"; +defparam \dealer_wins~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_R6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display1[6]~I ( + .datain(\inst1|led_display1 [0]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display1[6])); +// synopsys translate_off +defparam \led_display1[6]~I .input_async_reset = "none"; +defparam \led_display1[6]~I .input_power_up = "low"; +defparam \led_display1[6]~I .input_register_mode = "none"; +defparam \led_display1[6]~I .input_sync_reset = "none"; +defparam \led_display1[6]~I .oe_async_reset = "none"; +defparam \led_display1[6]~I .oe_power_up = "low"; +defparam \led_display1[6]~I .oe_register_mode = "none"; +defparam \led_display1[6]~I .oe_sync_reset = "none"; +defparam \led_display1[6]~I .operation_mode = "output"; +defparam \led_display1[6]~I .output_async_reset = "none"; +defparam \led_display1[6]~I .output_power_up = "low"; +defparam \led_display1[6]~I .output_register_mode = "none"; +defparam \led_display1[6]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_B17, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display1[5]~I ( + .datain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display1[5])); +// synopsys translate_off +defparam \led_display1[5]~I .input_async_reset = "none"; +defparam \led_display1[5]~I .input_power_up = "low"; +defparam \led_display1[5]~I .input_register_mode = "none"; +defparam \led_display1[5]~I .input_sync_reset = "none"; +defparam \led_display1[5]~I .oe_async_reset = "none"; +defparam \led_display1[5]~I .oe_power_up = "low"; +defparam \led_display1[5]~I .oe_register_mode = "none"; +defparam \led_display1[5]~I .oe_sync_reset = "none"; +defparam \led_display1[5]~I .operation_mode = "output"; +defparam \led_display1[5]~I .output_async_reset = "none"; +defparam \led_display1[5]~I .output_power_up = "low"; +defparam \led_display1[5]~I .output_register_mode = "none"; +defparam \led_display1[5]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_T15, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display1[4]~I ( + .datain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display1[4])); +// synopsys translate_off +defparam \led_display1[4]~I .input_async_reset = "none"; +defparam \led_display1[4]~I .input_power_up = "low"; +defparam \led_display1[4]~I .input_register_mode = "none"; +defparam \led_display1[4]~I .input_sync_reset = "none"; +defparam \led_display1[4]~I .oe_async_reset = "none"; +defparam \led_display1[4]~I .oe_power_up = "low"; +defparam \led_display1[4]~I .oe_register_mode = "none"; +defparam \led_display1[4]~I .oe_sync_reset = "none"; +defparam \led_display1[4]~I .operation_mode = "output"; +defparam \led_display1[4]~I .output_async_reset = "none"; +defparam \led_display1[4]~I .output_power_up = "low"; +defparam \led_display1[4]~I .output_register_mode = "none"; +defparam \led_display1[4]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_T3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display1[3]~I ( + .datain(!\inst1|led_display1 [0]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display1[3])); +// synopsys translate_off +defparam \led_display1[3]~I .input_async_reset = "none"; +defparam \led_display1[3]~I .input_power_up = "low"; +defparam \led_display1[3]~I .input_register_mode = "none"; +defparam \led_display1[3]~I .input_sync_reset = "none"; +defparam \led_display1[3]~I .oe_async_reset = "none"; +defparam \led_display1[3]~I .oe_power_up = "low"; +defparam \led_display1[3]~I .oe_register_mode = "none"; +defparam \led_display1[3]~I .oe_sync_reset = "none"; +defparam \led_display1[3]~I .operation_mode = "output"; +defparam \led_display1[3]~I .output_async_reset = "none"; +defparam \led_display1[3]~I .output_power_up = "low"; +defparam \led_display1[3]~I .output_register_mode = "none"; +defparam \led_display1[3]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_Y2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display1[2]~I ( + .datain(\inst1|led_display3 [1]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display1[2])); +// synopsys translate_off +defparam \led_display1[2]~I .input_async_reset = "none"; +defparam \led_display1[2]~I .input_power_up = "low"; +defparam \led_display1[2]~I .input_register_mode = "none"; +defparam \led_display1[2]~I .input_sync_reset = "none"; +defparam \led_display1[2]~I .oe_async_reset = "none"; +defparam \led_display1[2]~I .oe_power_up = "low"; +defparam \led_display1[2]~I .oe_register_mode = "none"; +defparam \led_display1[2]~I .oe_sync_reset = "none"; +defparam \led_display1[2]~I .operation_mode = "output"; +defparam \led_display1[2]~I .output_async_reset = "none"; +defparam \led_display1[2]~I .output_power_up = "low"; +defparam \led_display1[2]~I .output_register_mode = "none"; +defparam \led_display1[2]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_U2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display1[1]~I ( + .datain(\inst1|led_display1 [0]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display1[1])); +// synopsys translate_off +defparam \led_display1[1]~I .input_async_reset = "none"; +defparam \led_display1[1]~I .input_power_up = "low"; +defparam \led_display1[1]~I .input_register_mode = "none"; +defparam \led_display1[1]~I .input_sync_reset = "none"; +defparam \led_display1[1]~I .oe_async_reset = "none"; +defparam \led_display1[1]~I .oe_power_up = "low"; +defparam \led_display1[1]~I .oe_register_mode = "none"; +defparam \led_display1[1]~I .oe_sync_reset = "none"; +defparam \led_display1[1]~I .operation_mode = "output"; +defparam \led_display1[1]~I .output_async_reset = "none"; +defparam \led_display1[1]~I .output_power_up = "low"; +defparam \led_display1[1]~I .output_register_mode = "none"; +defparam \led_display1[1]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_R5, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display1[0]~I ( + .datain(\inst1|led_display1 [0]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display1[0])); +// synopsys translate_off +defparam \led_display1[0]~I .input_async_reset = "none"; +defparam \led_display1[0]~I .input_power_up = "low"; +defparam \led_display1[0]~I .input_register_mode = "none"; +defparam \led_display1[0]~I .input_sync_reset = "none"; +defparam \led_display1[0]~I .oe_async_reset = "none"; +defparam \led_display1[0]~I .oe_power_up = "low"; +defparam \led_display1[0]~I .oe_register_mode = "none"; +defparam \led_display1[0]~I .oe_sync_reset = "none"; +defparam \led_display1[0]~I .operation_mode = "output"; +defparam \led_display1[0]~I .output_async_reset = "none"; +defparam \led_display1[0]~I .output_power_up = "low"; +defparam \led_display1[0]~I .output_register_mode = "none"; +defparam \led_display1[0]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_B14, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display2[6]~I ( + .datain(vcc), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display2[6])); +// synopsys translate_off +defparam \led_display2[6]~I .input_async_reset = "none"; +defparam \led_display2[6]~I .input_power_up = "low"; +defparam \led_display2[6]~I .input_register_mode = "none"; +defparam \led_display2[6]~I .input_sync_reset = "none"; +defparam \led_display2[6]~I .oe_async_reset = "none"; +defparam \led_display2[6]~I .oe_power_up = "low"; +defparam \led_display2[6]~I .oe_register_mode = "none"; +defparam \led_display2[6]~I .oe_sync_reset = "none"; +defparam \led_display2[6]~I .operation_mode = "output"; +defparam \led_display2[6]~I .output_async_reset = "none"; +defparam \led_display2[6]~I .output_power_up = "low"; +defparam \led_display2[6]~I .output_register_mode = "none"; +defparam \led_display2[6]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_T5, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display2[5]~I ( + .datain(!\inst1|led_display3 [1]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display2[5])); +// synopsys translate_off +defparam \led_display2[5]~I .input_async_reset = "none"; +defparam \led_display2[5]~I .input_power_up = "low"; +defparam \led_display2[5]~I .input_register_mode = "none"; +defparam \led_display2[5]~I .input_sync_reset = "none"; +defparam \led_display2[5]~I .oe_async_reset = "none"; +defparam \led_display2[5]~I .oe_power_up = "low"; +defparam \led_display2[5]~I .oe_register_mode = "none"; +defparam \led_display2[5]~I .oe_sync_reset = "none"; +defparam \led_display2[5]~I .operation_mode = "output"; +defparam \led_display2[5]~I .output_async_reset = "none"; +defparam \led_display2[5]~I .output_power_up = "low"; +defparam \led_display2[5]~I .output_register_mode = "none"; +defparam \led_display2[5]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_W9, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display2[4]~I ( + .datain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display2[4])); +// synopsys translate_off +defparam \led_display2[4]~I .input_async_reset = "none"; +defparam \led_display2[4]~I .input_power_up = "low"; +defparam \led_display2[4]~I .input_register_mode = "none"; +defparam \led_display2[4]~I .input_sync_reset = "none"; +defparam \led_display2[4]~I .oe_async_reset = "none"; +defparam \led_display2[4]~I .oe_power_up = "low"; +defparam \led_display2[4]~I .oe_register_mode = "none"; +defparam \led_display2[4]~I .oe_sync_reset = "none"; +defparam \led_display2[4]~I .operation_mode = "output"; +defparam \led_display2[4]~I .output_async_reset = "none"; +defparam \led_display2[4]~I .output_power_up = "low"; +defparam \led_display2[4]~I .output_register_mode = "none"; +defparam \led_display2[4]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_H15, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display2[3]~I ( + .datain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display2[3])); +// synopsys translate_off +defparam \led_display2[3]~I .input_async_reset = "none"; +defparam \led_display2[3]~I .input_power_up = "low"; +defparam \led_display2[3]~I .input_register_mode = "none"; +defparam \led_display2[3]~I .input_sync_reset = "none"; +defparam \led_display2[3]~I .oe_async_reset = "none"; +defparam \led_display2[3]~I .oe_power_up = "low"; +defparam \led_display2[3]~I .oe_register_mode = "none"; +defparam \led_display2[3]~I .oe_sync_reset = "none"; +defparam \led_display2[3]~I .operation_mode = "output"; +defparam \led_display2[3]~I .output_async_reset = "none"; +defparam \led_display2[3]~I .output_power_up = "low"; +defparam \led_display2[3]~I .output_register_mode = "none"; +defparam \led_display2[3]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_B11, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display2[2]~I ( + .datain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display2[2])); +// synopsys translate_off +defparam \led_display2[2]~I .input_async_reset = "none"; +defparam \led_display2[2]~I .input_power_up = "low"; +defparam \led_display2[2]~I .input_register_mode = "none"; +defparam \led_display2[2]~I .input_sync_reset = "none"; +defparam \led_display2[2]~I .oe_async_reset = "none"; +defparam \led_display2[2]~I .oe_power_up = "low"; +defparam \led_display2[2]~I .oe_register_mode = "none"; +defparam \led_display2[2]~I .oe_sync_reset = "none"; +defparam \led_display2[2]~I .operation_mode = "output"; +defparam \led_display2[2]~I .output_async_reset = "none"; +defparam \led_display2[2]~I .output_power_up = "low"; +defparam \led_display2[2]~I .output_register_mode = "none"; +defparam \led_display2[2]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_AA16, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display2[1]~I ( + .datain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display2[1])); +// synopsys translate_off +defparam \led_display2[1]~I .input_async_reset = "none"; +defparam \led_display2[1]~I .input_power_up = "low"; +defparam \led_display2[1]~I .input_register_mode = "none"; +defparam \led_display2[1]~I .input_sync_reset = "none"; +defparam \led_display2[1]~I .oe_async_reset = "none"; +defparam \led_display2[1]~I .oe_power_up = "low"; +defparam \led_display2[1]~I .oe_register_mode = "none"; +defparam \led_display2[1]~I .oe_sync_reset = "none"; +defparam \led_display2[1]~I .operation_mode = "output"; +defparam \led_display2[1]~I .output_async_reset = "none"; +defparam \led_display2[1]~I .output_power_up = "low"; +defparam \led_display2[1]~I .output_register_mode = "none"; +defparam \led_display2[1]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_AB7, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display2[0]~I ( + .datain(\inst1|led_display4 [3]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display2[0])); +// synopsys translate_off +defparam \led_display2[0]~I .input_async_reset = "none"; +defparam \led_display2[0]~I .input_power_up = "low"; +defparam \led_display2[0]~I .input_register_mode = "none"; +defparam \led_display2[0]~I .input_sync_reset = "none"; +defparam \led_display2[0]~I .oe_async_reset = "none"; +defparam \led_display2[0]~I .oe_power_up = "low"; +defparam \led_display2[0]~I .oe_register_mode = "none"; +defparam \led_display2[0]~I .oe_sync_reset = "none"; +defparam \led_display2[0]~I .operation_mode = "output"; +defparam \led_display2[0]~I .output_async_reset = "none"; +defparam \led_display2[0]~I .output_power_up = "low"; +defparam \led_display2[0]~I .output_register_mode = "none"; +defparam \led_display2[0]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_T6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display3[6]~I ( + .datain(!\inst1|led_display3 [1]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display3[6])); +// synopsys translate_off +defparam \led_display3[6]~I .input_async_reset = "none"; +defparam \led_display3[6]~I .input_power_up = "low"; +defparam \led_display3[6]~I .input_register_mode = "none"; +defparam \led_display3[6]~I .input_sync_reset = "none"; +defparam \led_display3[6]~I .oe_async_reset = "none"; +defparam \led_display3[6]~I .oe_power_up = "low"; +defparam \led_display3[6]~I .oe_register_mode = "none"; +defparam \led_display3[6]~I .oe_sync_reset = "none"; +defparam \led_display3[6]~I .operation_mode = "output"; +defparam \led_display3[6]~I .output_async_reset = "none"; +defparam \led_display3[6]~I .output_power_up = "low"; +defparam \led_display3[6]~I .output_register_mode = "none"; +defparam \led_display3[6]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_U3, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display3[5]~I ( + .datain(!\inst1|led_display3 [1]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display3[5])); +// synopsys translate_off +defparam \led_display3[5]~I .input_async_reset = "none"; +defparam \led_display3[5]~I .input_power_up = "low"; +defparam \led_display3[5]~I .input_register_mode = "none"; +defparam \led_display3[5]~I .input_sync_reset = "none"; +defparam \led_display3[5]~I .oe_async_reset = "none"; +defparam \led_display3[5]~I .oe_power_up = "low"; +defparam \led_display3[5]~I .oe_register_mode = "none"; +defparam \led_display3[5]~I .oe_sync_reset = "none"; +defparam \led_display3[5]~I .operation_mode = "output"; +defparam \led_display3[5]~I .output_async_reset = "none"; +defparam \led_display3[5]~I .output_power_up = "low"; +defparam \led_display3[5]~I .output_register_mode = "none"; +defparam \led_display3[5]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_C7, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display3[4]~I ( + .datain(vcc), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display3[4])); +// synopsys translate_off +defparam \led_display3[4]~I .input_async_reset = "none"; +defparam \led_display3[4]~I .input_power_up = "low"; +defparam \led_display3[4]~I .input_register_mode = "none"; +defparam \led_display3[4]~I .input_sync_reset = "none"; +defparam \led_display3[4]~I .oe_async_reset = "none"; +defparam \led_display3[4]~I .oe_power_up = "low"; +defparam \led_display3[4]~I .oe_register_mode = "none"; +defparam \led_display3[4]~I .oe_sync_reset = "none"; +defparam \led_display3[4]~I .operation_mode = "output"; +defparam \led_display3[4]~I .output_async_reset = "none"; +defparam \led_display3[4]~I .output_power_up = "low"; +defparam \led_display3[4]~I .output_register_mode = "none"; +defparam \led_display3[4]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_W1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display3[3]~I ( + .datain(!\inst1|led_display3 [1]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display3[3])); +// synopsys translate_off +defparam \led_display3[3]~I .input_async_reset = "none"; +defparam \led_display3[3]~I .input_power_up = "low"; +defparam \led_display3[3]~I .input_register_mode = "none"; +defparam \led_display3[3]~I .input_sync_reset = "none"; +defparam \led_display3[3]~I .oe_async_reset = "none"; +defparam \led_display3[3]~I .oe_power_up = "low"; +defparam \led_display3[3]~I .oe_register_mode = "none"; +defparam \led_display3[3]~I .oe_sync_reset = "none"; +defparam \led_display3[3]~I .operation_mode = "output"; +defparam \led_display3[3]~I .output_async_reset = "none"; +defparam \led_display3[3]~I .output_power_up = "low"; +defparam \led_display3[3]~I .output_register_mode = "none"; +defparam \led_display3[3]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_C21, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display3[2]~I ( + .datain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display3[2])); +// synopsys translate_off +defparam \led_display3[2]~I .input_async_reset = "none"; +defparam \led_display3[2]~I .input_power_up = "low"; +defparam \led_display3[2]~I .input_register_mode = "none"; +defparam \led_display3[2]~I .input_sync_reset = "none"; +defparam \led_display3[2]~I .oe_async_reset = "none"; +defparam \led_display3[2]~I .oe_power_up = "low"; +defparam \led_display3[2]~I .oe_register_mode = "none"; +defparam \led_display3[2]~I .oe_sync_reset = "none"; +defparam \led_display3[2]~I .operation_mode = "output"; +defparam \led_display3[2]~I .output_async_reset = "none"; +defparam \led_display3[2]~I .output_power_up = "low"; +defparam \led_display3[2]~I .output_register_mode = "none"; +defparam \led_display3[2]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_Y1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display3[1]~I ( + .datain(\inst1|led_display3 [1]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display3[1])); +// synopsys translate_off +defparam \led_display3[1]~I .input_async_reset = "none"; +defparam \led_display3[1]~I .input_power_up = "low"; +defparam \led_display3[1]~I .input_register_mode = "none"; +defparam \led_display3[1]~I .input_sync_reset = "none"; +defparam \led_display3[1]~I .oe_async_reset = "none"; +defparam \led_display3[1]~I .oe_power_up = "low"; +defparam \led_display3[1]~I .oe_register_mode = "none"; +defparam \led_display3[1]~I .oe_sync_reset = "none"; +defparam \led_display3[1]~I .operation_mode = "output"; +defparam \led_display3[1]~I .output_async_reset = "none"; +defparam \led_display3[1]~I .output_power_up = "low"; +defparam \led_display3[1]~I .output_register_mode = "none"; +defparam \led_display3[1]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_V2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display3[0]~I ( + .datain(!\inst1|led_display3 [1]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display3[0])); +// synopsys translate_off +defparam \led_display3[0]~I .input_async_reset = "none"; +defparam \led_display3[0]~I .input_power_up = "low"; +defparam \led_display3[0]~I .input_register_mode = "none"; +defparam \led_display3[0]~I .input_sync_reset = "none"; +defparam \led_display3[0]~I .oe_async_reset = "none"; +defparam \led_display3[0]~I .oe_power_up = "low"; +defparam \led_display3[0]~I .oe_register_mode = "none"; +defparam \led_display3[0]~I .oe_sync_reset = "none"; +defparam \led_display3[0]~I .operation_mode = "output"; +defparam \led_display3[0]~I .output_async_reset = "none"; +defparam \led_display3[0]~I .output_power_up = "low"; +defparam \led_display3[0]~I .output_register_mode = "none"; +defparam \led_display3[0]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_W2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display4[6]~I ( + .datain(!\inst1|led_display3 [1]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display4[6])); +// synopsys translate_off +defparam \led_display4[6]~I .input_async_reset = "none"; +defparam \led_display4[6]~I .input_power_up = "low"; +defparam \led_display4[6]~I .input_register_mode = "none"; +defparam \led_display4[6]~I .input_sync_reset = "none"; +defparam \led_display4[6]~I .oe_async_reset = "none"; +defparam \led_display4[6]~I .oe_power_up = "low"; +defparam \led_display4[6]~I .oe_register_mode = "none"; +defparam \led_display4[6]~I .oe_sync_reset = "none"; +defparam \led_display4[6]~I .operation_mode = "output"; +defparam \led_display4[6]~I .output_async_reset = "none"; +defparam \led_display4[6]~I .output_power_up = "low"; +defparam \led_display4[6]~I .output_register_mode = "none"; +defparam \led_display4[6]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_G8, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display4[5]~I ( + .datain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display4[5])); +// synopsys translate_off +defparam \led_display4[5]~I .input_async_reset = "none"; +defparam \led_display4[5]~I .input_power_up = "low"; +defparam \led_display4[5]~I .input_register_mode = "none"; +defparam \led_display4[5]~I .input_sync_reset = "none"; +defparam \led_display4[5]~I .oe_async_reset = "none"; +defparam \led_display4[5]~I .oe_power_up = "low"; +defparam \led_display4[5]~I .oe_register_mode = "none"; +defparam \led_display4[5]~I .oe_sync_reset = "none"; +defparam \led_display4[5]~I .operation_mode = "output"; +defparam \led_display4[5]~I .output_async_reset = "none"; +defparam \led_display4[5]~I .output_power_up = "low"; +defparam \led_display4[5]~I .output_register_mode = "none"; +defparam \led_display4[5]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_D2, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display4[4]~I ( + .datain(gnd), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display4[4])); +// synopsys translate_off +defparam \led_display4[4]~I .input_async_reset = "none"; +defparam \led_display4[4]~I .input_power_up = "low"; +defparam \led_display4[4]~I .input_register_mode = "none"; +defparam \led_display4[4]~I .input_sync_reset = "none"; +defparam \led_display4[4]~I .oe_async_reset = "none"; +defparam \led_display4[4]~I .oe_power_up = "low"; +defparam \led_display4[4]~I .oe_register_mode = "none"; +defparam \led_display4[4]~I .oe_sync_reset = "none"; +defparam \led_display4[4]~I .operation_mode = "output"; +defparam \led_display4[4]~I .output_async_reset = "none"; +defparam \led_display4[4]~I .output_power_up = "low"; +defparam \led_display4[4]~I .output_register_mode = "none"; +defparam \led_display4[4]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_P9, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display4[3]~I ( + .datain(\inst1|led_display4 [3]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display4[3])); +// synopsys translate_off +defparam \led_display4[3]~I .input_async_reset = "none"; +defparam \led_display4[3]~I .input_power_up = "low"; +defparam \led_display4[3]~I .input_register_mode = "none"; +defparam \led_display4[3]~I .input_sync_reset = "none"; +defparam \led_display4[3]~I .oe_async_reset = "none"; +defparam \led_display4[3]~I .oe_power_up = "low"; +defparam \led_display4[3]~I .oe_register_mode = "none"; +defparam \led_display4[3]~I .oe_sync_reset = "none"; +defparam \led_display4[3]~I .operation_mode = "output"; +defparam \led_display4[3]~I .output_async_reset = "none"; +defparam \led_display4[3]~I .output_power_up = "low"; +defparam \led_display4[3]~I .output_register_mode = "none"; +defparam \led_display4[3]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_P8, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display4[2]~I ( + .datain(!\inst1|led_display4 [3]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display4[2])); +// synopsys translate_off +defparam \led_display4[2]~I .input_async_reset = "none"; +defparam \led_display4[2]~I .input_power_up = "low"; +defparam \led_display4[2]~I .input_register_mode = "none"; +defparam \led_display4[2]~I .input_sync_reset = "none"; +defparam \led_display4[2]~I .oe_async_reset = "none"; +defparam \led_display4[2]~I .oe_power_up = "low"; +defparam \led_display4[2]~I .oe_register_mode = "none"; +defparam \led_display4[2]~I .oe_sync_reset = "none"; +defparam \led_display4[2]~I .operation_mode = "output"; +defparam \led_display4[2]~I .output_async_reset = "none"; +defparam \led_display4[2]~I .output_power_up = "low"; +defparam \led_display4[2]~I .output_register_mode = "none"; +defparam \led_display4[2]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_AA7, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display4[1]~I ( + .datain(!\inst1|led_display4 [3]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display4[1])); +// synopsys translate_off +defparam \led_display4[1]~I .input_async_reset = "none"; +defparam \led_display4[1]~I .input_power_up = "low"; +defparam \led_display4[1]~I .input_register_mode = "none"; +defparam \led_display4[1]~I .input_sync_reset = "none"; +defparam \led_display4[1]~I .oe_async_reset = "none"; +defparam \led_display4[1]~I .oe_power_up = "low"; +defparam \led_display4[1]~I .oe_register_mode = "none"; +defparam \led_display4[1]~I .oe_sync_reset = "none"; +defparam \led_display4[1]~I .operation_mode = "output"; +defparam \led_display4[1]~I .output_async_reset = "none"; +defparam \led_display4[1]~I .output_power_up = "low"; +defparam \led_display4[1]~I .output_register_mode = "none"; +defparam \led_display4[1]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_U1, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \led_display4[0]~I ( + .datain(!\inst1|led_display1 [0]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(led_display4[0])); +// synopsys translate_off +defparam \led_display4[0]~I .input_async_reset = "none"; +defparam \led_display4[0]~I .input_power_up = "low"; +defparam \led_display4[0]~I .input_register_mode = "none"; +defparam \led_display4[0]~I .input_sync_reset = "none"; +defparam \led_display4[0]~I .oe_async_reset = "none"; +defparam \led_display4[0]~I .oe_power_up = "low"; +defparam \led_display4[0]~I .oe_register_mode = "none"; +defparam \led_display4[0]~I .oe_sync_reset = "none"; +defparam \led_display4[0]~I .operation_mode = "output"; +defparam \led_display4[0]~I .output_async_reset = "none"; +defparam \led_display4[0]~I .output_power_up = "low"; +defparam \led_display4[0]~I .output_register_mode = "none"; +defparam \led_display4[0]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_V8, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \state_out[1]~I ( + .datain(\inst|computer:state[1]~regout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(state_out[1])); +// synopsys translate_off +defparam \state_out[1]~I .input_async_reset = "none"; +defparam \state_out[1]~I .input_power_up = "low"; +defparam \state_out[1]~I .input_register_mode = "none"; +defparam \state_out[1]~I .input_sync_reset = "none"; +defparam \state_out[1]~I .oe_async_reset = "none"; +defparam \state_out[1]~I .oe_power_up = "low"; +defparam \state_out[1]~I .oe_register_mode = "none"; +defparam \state_out[1]~I .oe_sync_reset = "none"; +defparam \state_out[1]~I .operation_mode = "output"; +defparam \state_out[1]~I .output_async_reset = "none"; +defparam \state_out[1]~I .output_power_up = "low"; +defparam \state_out[1]~I .output_register_mode = "none"; +defparam \state_out[1]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_AB6, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \state_out[0]~I ( + .datain(\inst|computer:state[0]~regout ), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(state_out[0])); +// synopsys translate_off +defparam \state_out[0]~I .input_async_reset = "none"; +defparam \state_out[0]~I .input_power_up = "low"; +defparam \state_out[0]~I .input_register_mode = "none"; +defparam \state_out[0]~I .input_sync_reset = "none"; +defparam \state_out[0]~I .oe_async_reset = "none"; +defparam \state_out[0]~I .oe_power_up = "low"; +defparam \state_out[0]~I .oe_register_mode = "none"; +defparam \state_out[0]~I .oe_sync_reset = "none"; +defparam \state_out[0]~I .operation_mode = "output"; +defparam \state_out[0]~I .output_async_reset = "none"; +defparam \state_out[0]~I .output_power_up = "low"; +defparam \state_out[0]~I .output_register_mode = "none"; +defparam \state_out[0]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_U4, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \sum_out[5]~I ( + .datain(\inst|sum_out [5]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(sum_out[5])); +// synopsys translate_off +defparam \sum_out[5]~I .input_async_reset = "none"; +defparam \sum_out[5]~I .input_power_up = "low"; +defparam \sum_out[5]~I .input_register_mode = "none"; +defparam \sum_out[5]~I .input_sync_reset = "none"; +defparam \sum_out[5]~I .oe_async_reset = "none"; +defparam \sum_out[5]~I .oe_power_up = "low"; +defparam \sum_out[5]~I .oe_register_mode = "none"; +defparam \sum_out[5]~I .oe_sync_reset = "none"; +defparam \sum_out[5]~I .operation_mode = "output"; +defparam \sum_out[5]~I .output_async_reset = "none"; +defparam \sum_out[5]~I .output_power_up = "low"; +defparam \sum_out[5]~I .output_register_mode = "none"; +defparam \sum_out[5]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_W5, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \sum_out[4]~I ( + .datain(\inst|sum_out [4]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(sum_out[4])); +// synopsys translate_off +defparam \sum_out[4]~I .input_async_reset = "none"; +defparam \sum_out[4]~I .input_power_up = "low"; +defparam \sum_out[4]~I .input_register_mode = "none"; +defparam \sum_out[4]~I .input_sync_reset = "none"; +defparam \sum_out[4]~I .oe_async_reset = "none"; +defparam \sum_out[4]~I .oe_power_up = "low"; +defparam \sum_out[4]~I .oe_register_mode = "none"; +defparam \sum_out[4]~I .oe_sync_reset = "none"; +defparam \sum_out[4]~I .operation_mode = "output"; +defparam \sum_out[4]~I .output_async_reset = "none"; +defparam \sum_out[4]~I .output_power_up = "low"; +defparam \sum_out[4]~I .output_register_mode = "none"; +defparam \sum_out[4]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_AA4, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \sum_out[3]~I ( + .datain(\inst|sum_out [3]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(sum_out[3])); +// synopsys translate_off +defparam \sum_out[3]~I .input_async_reset = "none"; +defparam \sum_out[3]~I .input_power_up = "low"; +defparam \sum_out[3]~I .input_register_mode = "none"; +defparam \sum_out[3]~I .input_sync_reset = "none"; +defparam \sum_out[3]~I .oe_async_reset = "none"; +defparam \sum_out[3]~I .oe_power_up = "low"; +defparam \sum_out[3]~I .oe_register_mode = "none"; +defparam \sum_out[3]~I .oe_sync_reset = "none"; +defparam \sum_out[3]~I .operation_mode = "output"; +defparam \sum_out[3]~I .output_async_reset = "none"; +defparam \sum_out[3]~I .output_power_up = "low"; +defparam \sum_out[3]~I .output_register_mode = "none"; +defparam \sum_out[3]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_T8, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \sum_out[2]~I ( + .datain(\inst|sum_out [2]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(sum_out[2])); +// synopsys translate_off +defparam \sum_out[2]~I .input_async_reset = "none"; +defparam \sum_out[2]~I .input_power_up = "low"; +defparam \sum_out[2]~I .input_register_mode = "none"; +defparam \sum_out[2]~I .input_sync_reset = "none"; +defparam \sum_out[2]~I .oe_async_reset = "none"; +defparam \sum_out[2]~I .oe_power_up = "low"; +defparam \sum_out[2]~I .oe_register_mode = "none"; +defparam \sum_out[2]~I .oe_sync_reset = "none"; +defparam \sum_out[2]~I .operation_mode = "output"; +defparam \sum_out[2]~I .output_async_reset = "none"; +defparam \sum_out[2]~I .output_power_up = "low"; +defparam \sum_out[2]~I .output_register_mode = "none"; +defparam \sum_out[2]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_T7, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \sum_out[1]~I ( + .datain(\inst|sum_out [1]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(sum_out[1])); +// synopsys translate_off +defparam \sum_out[1]~I .input_async_reset = "none"; +defparam \sum_out[1]~I .input_power_up = "low"; +defparam \sum_out[1]~I .input_register_mode = "none"; +defparam \sum_out[1]~I .input_sync_reset = "none"; +defparam \sum_out[1]~I .oe_async_reset = "none"; +defparam \sum_out[1]~I .oe_power_up = "low"; +defparam \sum_out[1]~I .oe_register_mode = "none"; +defparam \sum_out[1]~I .oe_sync_reset = "none"; +defparam \sum_out[1]~I .operation_mode = "output"; +defparam \sum_out[1]~I .output_async_reset = "none"; +defparam \sum_out[1]~I .output_power_up = "low"; +defparam \sum_out[1]~I .output_register_mode = "none"; +defparam \sum_out[1]~I .output_sync_reset = "none"; +// synopsys translate_on + +// Location: PIN_AB4, I/O Standard: 3.3-V LVTTL, Current Strength: 24mA +cycloneii_io \sum_out[0]~I ( + .datain(\inst|sum_out [0]), + .oe(vcc), + .outclk(gnd), + .outclkena(vcc), + .inclk(gnd), + .inclkena(vcc), + .areset(gnd), + .sreset(gnd), + .differentialin(gnd), + .linkin(gnd), + .devclrn(devclrn), + .devpor(devpor), + .devoe(devoe), + .combout(), + .regout(), + .differentialout(), + .linkout(), + .padio(sum_out[0])); +// synopsys translate_off +defparam \sum_out[0]~I .input_async_reset = "none"; +defparam \sum_out[0]~I .input_power_up = "low"; +defparam \sum_out[0]~I .input_register_mode = "none"; +defparam \sum_out[0]~I .input_sync_reset = "none"; +defparam \sum_out[0]~I .oe_async_reset = "none"; +defparam \sum_out[0]~I .oe_power_up = "low"; +defparam \sum_out[0]~I .oe_register_mode = "none"; +defparam \sum_out[0]~I .oe_sync_reset = "none"; +defparam \sum_out[0]~I .operation_mode = "output"; +defparam \sum_out[0]~I .output_async_reset = "none"; +defparam \sum_out[0]~I .output_power_up = "low"; +defparam \sum_out[0]~I .output_register_mode = "none"; +defparam \sum_out[0]~I .output_sync_reset = "none"; +// synopsys translate_on + +endmodule diff --git a/lab5/simulation/qsim/gA6_lab5.vt b/lab5/simulation/qsim/gA6_lab5.vt new file mode 100644 index 0000000..f035c29 --- /dev/null +++ b/lab5/simulation/qsim/gA6_lab5.vt @@ -0,0 +1,638 @@ +// Copyright (C) 1991-2013 Altera Corporation +// Your use of Altera Corporation's design tools, logic functions +// and other software and tools, and its AMPP partner logic +// functions, and any output files from any of the foregoing +// (including device programming or simulation files), and any +// associated documentation or information are expressly subject +// to the terms and conditions of the Altera Program License +// Subscription Agreement, Altera MegaCore Function License +// Agreement, or other applicable license agreement, including, +// without limitation, that your use is for the sole purpose of +// programming logic devices manufactured by Altera and sold by +// Altera or its authorized distributors. Please refer to the +// applicable agreement for further details. + +// ***************************************************************************** +// This file contains a Verilog test bench with test vectors .The test vectors +// are exported from a vector file in the Quartus Waveform Editor and apply to +// the top level entity of the current Quartus project .The user can use this +// testbench to simulate his design using a third-party simulation tool . +// ***************************************************************************** +// Generated on "11/29/2017 18:55:04" + +// Verilog Self-Checking Test Bench (with test vectors) for design : gA6_lab5 +// +// Simulation tool : 3rd Party +// + +`timescale 1 ps/ 1 ps +module gA6_lab5_vlg_sample_tst( + clk, + player_sum, + rst, + sum, + turn, + sampler_tx +); +input clk; +input [5:0] player_sum; +input rst; +input [5:0] sum; +input turn; +output sampler_tx; + +reg sample; +time current_time; +always @(clk or player_sum or rst or sum or turn) + +begin + if ($realtime > 0) + begin + if ($realtime == 0 || $realtime != current_time) + begin + if (sample === 1'bx) + sample = 0; + else + sample = ~sample; + end + current_time = $realtime; + end +end + +assign sampler_tx = sample; +endmodule + +module gA6_lab5_vlg_check_tst ( + dealer_wins, + done, + hit, + led_display1, + led_display2, + led_display3, + led_display4, + player_wins, + state_out, + sum_out, + sampler_rx +); +input dealer_wins; +input done; +input hit; +input [6:0] led_display1; +input [6:0] led_display2; +input [6:0] led_display3; +input [6:0] led_display4; +input player_wins; +input [1:0] state_out; +input [5:0] sum_out; +input sampler_rx; + +reg dealer_wins_expected; +reg done_expected; +reg hit_expected; +reg [6:0] led_display1_expected; +reg [6:0] led_display2_expected; +reg [6:0] led_display3_expected; +reg [6:0] led_display4_expected; +reg player_wins_expected; +reg [1:0] state_out_expected; +reg [5:0] sum_out_expected; + +reg dealer_wins_prev; +reg done_prev; +reg hit_prev; +reg [6:0] led_display1_prev; +reg [6:0] led_display2_prev; +reg [6:0] led_display3_prev; +reg [6:0] led_display4_prev; +reg player_wins_prev; +reg [1:0] state_out_prev; +reg [5:0] sum_out_prev; + +reg dealer_wins_expected_prev; +reg done_expected_prev; +reg hit_expected_prev; +reg player_wins_expected_prev; +reg [1:0] state_out_expected_prev; +reg [5:0] sum_out_expected_prev; + +reg last_dealer_wins_exp; +reg last_done_exp; +reg last_hit_exp; +reg last_player_wins_exp; +reg [1:0] last_state_out_exp; +reg [5:0] last_sum_out_exp; + +reg trigger; + +integer i; +integer nummismatches; + +reg [1:10] on_first_change ; + + +initial +begin +trigger = 0; +i = 0; +nummismatches = 0; +on_first_change = 10'b1; +end + +// update real /o prevs + +always @(trigger) +begin + dealer_wins_prev = dealer_wins; + done_prev = done; + hit_prev = hit; + led_display1_prev = led_display1; + led_display2_prev = led_display2; + led_display3_prev = led_display3; + led_display4_prev = led_display4; + player_wins_prev = player_wins; + state_out_prev = state_out; + sum_out_prev = sum_out; +end + +// update expected /o prevs + +always @(trigger) +begin + dealer_wins_expected_prev = dealer_wins_expected; + done_expected_prev = done_expected; + hit_expected_prev = hit_expected; + player_wins_expected_prev = player_wins_expected; + state_out_expected_prev = state_out_expected; + sum_out_expected_prev = sum_out_expected; +end + + +// expected sum_out[ 5 ] +initial +begin + sum_out_expected[5] = 1'bX; +end +// expected sum_out[ 4 ] +initial +begin + sum_out_expected[4] = 1'bX; +end +// expected sum_out[ 3 ] +initial +begin + sum_out_expected[3] = 1'bX; +end +// expected sum_out[ 2 ] +initial +begin + sum_out_expected[2] = 1'bX; +end +// expected sum_out[ 1 ] +initial +begin + sum_out_expected[1] = 1'bX; +end +// expected sum_out[ 0 ] +initial +begin + sum_out_expected[0] = 1'bX; +end +// expected state_out[ 1 ] +initial +begin + state_out_expected[1] = 1'bX; +end +// expected state_out[ 0 ] +initial +begin + state_out_expected[0] = 1'bX; +end + +// expected hit +initial +begin + hit_expected = 1'bX; +end + +// expected done +initial +begin + done_expected = 1'bX; +end + +// expected player_wins +initial +begin + player_wins_expected = 1'bX; +end + +// expected dealer_wins +initial +begin + dealer_wins_expected = 1'bX; +end +// generate trigger +always @(dealer_wins_expected or dealer_wins or done_expected or done or hit_expected or hit or led_display1_expected or led_display1 or led_display2_expected or led_display2 or led_display3_expected or led_display3 or led_display4_expected or led_display4 or player_wins_expected or player_wins or state_out_expected or state_out or sum_out_expected or sum_out) +begin + trigger <= ~trigger; +end + +always @(posedge sampler_rx or negedge sampler_rx) +begin +`ifdef debug_tbench + $display("Scanning pattern %d @time = %t",i,$realtime ); + i = i + 1; + $display("| expected dealer_wins = %b | expected done = %b | expected hit = %b | expected led_display1 = %b | expected led_display2 = %b | expected led_display3 = %b | expected led_display4 = %b | expected player_wins = %b | expected state_out = %b | expected sum_out = %b | ",dealer_wins_expected_prev,done_expected_prev,hit_expected_prev,led_display1_expected_prev,led_display2_expected_prev,led_display3_expected_prev,led_display4_expected_prev,player_wins_expected_prev,state_out_expected_prev,sum_out_expected_prev); + $display("| real dealer_wins = %b | real done = %b | real hit = %b | real led_display1 = %b | real led_display2 = %b | real led_display3 = %b | real led_display4 = %b | real player_wins = %b | real state_out = %b | real sum_out = %b | ",dealer_wins_prev,done_prev,hit_prev,led_display1_prev,led_display2_prev,led_display3_prev,led_display4_prev,player_wins_prev,state_out_prev,sum_out_prev); +`endif + if ( + ( dealer_wins_expected_prev !== 1'bx ) && ( dealer_wins_prev !== dealer_wins_expected_prev ) + && ((dealer_wins_expected_prev !== last_dealer_wins_exp) || + on_first_change[1]) + ) + begin + $display ("ERROR! Vector Mismatch for output port dealer_wins :: @time = %t", $realtime); + $display (" Expected value = %b", dealer_wins_expected_prev); + $display (" Real value = %b", dealer_wins_prev); + nummismatches = nummismatches + 1; + on_first_change[1] = 1'b0; + last_dealer_wins_exp = dealer_wins_expected_prev; + end + if ( + ( done_expected_prev !== 1'bx ) && ( done_prev !== done_expected_prev ) + && ((done_expected_prev !== last_done_exp) || + on_first_change[2]) + ) + begin + $display ("ERROR! Vector Mismatch for output port done :: @time = %t", $realtime); + $display (" Expected value = %b", done_expected_prev); + $display (" Real value = %b", done_prev); + nummismatches = nummismatches + 1; + on_first_change[2] = 1'b0; + last_done_exp = done_expected_prev; + end + if ( + ( hit_expected_prev !== 1'bx ) && ( hit_prev !== hit_expected_prev ) + && ((hit_expected_prev !== last_hit_exp) || + on_first_change[3]) + ) + begin + $display ("ERROR! Vector Mismatch for output port hit :: @time = %t", $realtime); + $display (" Expected value = %b", hit_expected_prev); + $display (" Real value = %b", hit_prev); + nummismatches = nummismatches + 1; + on_first_change[3] = 1'b0; + last_hit_exp = hit_expected_prev; + end + if ( + ( player_wins_expected_prev !== 1'bx ) && ( player_wins_prev !== player_wins_expected_prev ) + && ((player_wins_expected_prev !== last_player_wins_exp) || + on_first_change[8]) + ) + begin + $display ("ERROR! Vector Mismatch for output port player_wins :: @time = %t", $realtime); + $display (" Expected value = %b", player_wins_expected_prev); + $display (" Real value = %b", player_wins_prev); + nummismatches = nummismatches + 1; + on_first_change[8] = 1'b0; + last_player_wins_exp = player_wins_expected_prev; + end + if ( + ( state_out_expected_prev[0] !== 1'bx ) && ( state_out_prev[0] !== state_out_expected_prev[0] ) + && ((state_out_expected_prev[0] !== last_state_out_exp[0]) || + on_first_change[9]) + ) + begin + $display ("ERROR! Vector Mismatch for output port state_out[0] :: @time = %t", $realtime); + $display (" Expected value = %b", state_out_expected_prev); + $display (" Real value = %b", state_out_prev); + nummismatches = nummismatches + 1; + on_first_change[9] = 1'b0; + last_state_out_exp[0] = state_out_expected_prev[0]; + end + if ( + ( state_out_expected_prev[1] !== 1'bx ) && ( state_out_prev[1] !== state_out_expected_prev[1] ) + && ((state_out_expected_prev[1] !== last_state_out_exp[1]) || + on_first_change[9]) + ) + begin + $display ("ERROR! Vector Mismatch for output port state_out[1] :: @time = %t", $realtime); + $display (" Expected value = %b", state_out_expected_prev); + $display (" Real value = %b", state_out_prev); + nummismatches = nummismatches + 1; + on_first_change[9] = 1'b0; + last_state_out_exp[1] = state_out_expected_prev[1]; + end + if ( + ( sum_out_expected_prev[0] !== 1'bx ) && ( sum_out_prev[0] !== sum_out_expected_prev[0] ) + && ((sum_out_expected_prev[0] !== last_sum_out_exp[0]) || + on_first_change[10]) + ) + begin + $display ("ERROR! Vector Mismatch for output port sum_out[0] :: @time = %t", $realtime); + $display (" Expected value = %b", sum_out_expected_prev); + $display (" Real value = %b", sum_out_prev); + nummismatches = nummismatches + 1; + on_first_change[10] = 1'b0; + last_sum_out_exp[0] = sum_out_expected_prev[0]; + end + if ( + ( sum_out_expected_prev[1] !== 1'bx ) && ( sum_out_prev[1] !== sum_out_expected_prev[1] ) + && ((sum_out_expected_prev[1] !== last_sum_out_exp[1]) || + on_first_change[10]) + ) + begin + $display ("ERROR! Vector Mismatch for output port sum_out[1] :: @time = %t", $realtime); + $display (" Expected value = %b", sum_out_expected_prev); + $display (" Real value = %b", sum_out_prev); + nummismatches = nummismatches + 1; + on_first_change[10] = 1'b0; + last_sum_out_exp[1] = sum_out_expected_prev[1]; + end + if ( + ( sum_out_expected_prev[2] !== 1'bx ) && ( sum_out_prev[2] !== sum_out_expected_prev[2] ) + && ((sum_out_expected_prev[2] !== last_sum_out_exp[2]) || + on_first_change[10]) + ) + begin + $display ("ERROR! Vector Mismatch for output port sum_out[2] :: @time = %t", $realtime); + $display (" Expected value = %b", sum_out_expected_prev); + $display (" Real value = %b", sum_out_prev); + nummismatches = nummismatches + 1; + on_first_change[10] = 1'b0; + last_sum_out_exp[2] = sum_out_expected_prev[2]; + end + if ( + ( sum_out_expected_prev[3] !== 1'bx ) && ( sum_out_prev[3] !== sum_out_expected_prev[3] ) + && ((sum_out_expected_prev[3] !== last_sum_out_exp[3]) || + on_first_change[10]) + ) + begin + $display ("ERROR! Vector Mismatch for output port sum_out[3] :: @time = %t", $realtime); + $display (" Expected value = %b", sum_out_expected_prev); + $display (" Real value = %b", sum_out_prev); + nummismatches = nummismatches + 1; + on_first_change[10] = 1'b0; + last_sum_out_exp[3] = sum_out_expected_prev[3]; + end + if ( + ( sum_out_expected_prev[4] !== 1'bx ) && ( sum_out_prev[4] !== sum_out_expected_prev[4] ) + && ((sum_out_expected_prev[4] !== last_sum_out_exp[4]) || + on_first_change[10]) + ) + begin + $display ("ERROR! Vector Mismatch for output port sum_out[4] :: @time = %t", $realtime); + $display (" Expected value = %b", sum_out_expected_prev); + $display (" Real value = %b", sum_out_prev); + nummismatches = nummismatches + 1; + on_first_change[10] = 1'b0; + last_sum_out_exp[4] = sum_out_expected_prev[4]; + end + if ( + ( sum_out_expected_prev[5] !== 1'bx ) && ( sum_out_prev[5] !== sum_out_expected_prev[5] ) + && ((sum_out_expected_prev[5] !== last_sum_out_exp[5]) || + on_first_change[10]) + ) + begin + $display ("ERROR! Vector Mismatch for output port sum_out[5] :: @time = %t", $realtime); + $display (" Expected value = %b", sum_out_expected_prev); + $display (" Real value = %b", sum_out_prev); + nummismatches = nummismatches + 1; + on_first_change[10] = 1'b0; + last_sum_out_exp[5] = sum_out_expected_prev[5]; + end + + trigger <= ~trigger; +end +initial + +begin +$timeformat(-12,3," ps",6); +#1000000; +if (nummismatches > 0) + $display ("%d mismatched vectors : Simulation failed !",nummismatches); +else + $display ("Simulation passed !"); +$finish; +end +endmodule + +module gA6_lab5_vlg_vec_tst(); +// constants +// general purpose registers +reg clk; +reg [5:0] player_sum; +reg rst; +reg [5:0] sum; +reg turn; +// wires +wire dealer_wins; +wire done; +wire hit; +wire [6:0] led_display1; +wire [6:0] led_display2; +wire [6:0] led_display3; +wire [6:0] led_display4; +wire player_wins; +wire [1:0] state_out; +wire [5:0] sum_out; + +wire sampler; + +// assign statements (if any) +gA6_lab5 i1 ( +// port map - connection between master ports and signals/registers + .clk(clk), + .dealer_wins(dealer_wins), + .done(done), + .hit(hit), + .led_display1(led_display1), + .led_display2(led_display2), + .led_display3(led_display3), + .led_display4(led_display4), + .player_sum(player_sum), + .player_wins(player_wins), + .rst(rst), + .state_out(state_out), + .sum(sum), + .sum_out(sum_out), + .turn(turn) +); + +// clk +always +begin + clk = 1'b0; + clk = #20000 1'b1; + #20000; +end + +// rst +initial +begin + rst = 1'b0; + rst = #640000 1'b1; + rst = #130000 1'b0; +end + +// turn +initial +begin + turn = 1'b0; + turn = #10000 1'b1; + turn = #100000 1'b0; + turn = #60000 1'b1; + turn = #100000 1'b0; + turn = #90000 1'b1; + turn = #340000 1'b0; + turn = #210000 1'b1; +end +// sum[ 5 ] +initial +begin + sum[5] = 1'b0; +end +// sum[ 4 ] +initial +begin + sum[4] = 1'b0; + sum[4] = #80000 1'b1; + sum[4] = #50000 1'b0; + sum[4] = #100000 1'b1; + sum[4] = #210000 1'b0; + sum[4] = #180000 1'b1; + sum[4] = #90000 1'b0; + sum[4] = #150000 1'b1; + sum[4] = #60000 1'b0; +end +// sum[ 3 ] +initial +begin + sum[3] = 1'b0; + sum[3] = #30000 1'b1; + sum[3] = #50000 1'b0; + sum[3] = #80000 1'b1; + sum[3] = #70000 1'b0; + sum[3] = #210000 1'b1; + sum[3] = #60000 1'b0; + sum[3] = #270000 1'b1; +end +// sum[ 2 ] +initial +begin + sum[2] = 1'b0; + sum[2] = #230000 1'b1; + sum[2] = #120000 1'b0; + sum[2] = #60000 1'b1; + sum[2] = #30000 1'b0; + sum[2] = #180000 1'b1; + sum[2] = #240000 1'b0; +end +// sum[ 1 ] +initial +begin + sum[1] = 1'b0; + sum[1] = #30000 1'b1; + sum[1] = #100000 1'b0; + sum[1] = #70000 1'b1; + sum[1] = #90000 1'b0; + sum[1] = #120000 1'b1; + sum[1] = #90000 1'b0; + sum[1] = #120000 1'b1; + sum[1] = #30000 1'b0; + sum[1] = #60000 1'b1; + sum[1] = #60000 1'b0; + sum[1] = #90000 1'b1; + sum[1] = #30000 1'b0; + sum[1] = #30000 1'b1; + sum[1] = #30000 1'b0; +end +// sum[ 0 ] +initial +begin + sum[0] = 1'b0; + sum[0] = #200000 1'b1; + sum[0] = #30000 1'b0; + sum[0] = #210000 1'b1; + sum[0] = #180000 1'b0; + sum[0] = #90000 1'b1; + sum[0] = #150000 1'b0; + sum[0] = #60000 1'b1; +end +// player_sum[ 5 ] +initial +begin + player_sum[5] = 1'b0; +end +// player_sum[ 4 ] +initial +begin + player_sum[4] = 1'b1; + player_sum[4] = #150000 1'b0; + player_sum[4] = #70000 1'b1; + player_sum[4] = #460000 1'b0; + player_sum[4] = #210000 1'b1; +end +// player_sum[ 3 ] +initial +begin + player_sum[3] = 1'b0; + player_sum[3] = #420000 1'b1; + player_sum[3] = #170000 1'b0; + player_sum[3] = #90000 1'b1; + player_sum[3] = #210000 1'b0; +end +// player_sum[ 2 ] +initial +begin + player_sum[2] = 1'b1; + player_sum[2] = #150000 1'b0; + player_sum[2] = #180000 1'b1; + player_sum[2] = #90000 1'b0; + player_sum[2] = #170000 1'b1; + player_sum[2] = #90000 1'b0; + player_sum[2] = #60000 1'b1; +end +// player_sum[ 1 ] +initial +begin + player_sum[1] = 1'b0; + player_sum[1] = #590000 1'b1; + player_sum[1] = #90000 1'b0; + player_sum[1] = #60000 1'b1; + player_sum[1] = #150000 1'b0; +end +// player_sum[ 0 ] +initial +begin + player_sum[0] = 1'b1; + player_sum[0] = #150000 1'b0; + player_sum[0] = #530000 1'b1; + player_sum[0] = #210000 1'b0; +end + +gA6_lab5_vlg_sample_tst tb_sample ( + .clk(clk), + .player_sum(player_sum), + .rst(rst), + .sum(sum), + .turn(turn), + .sampler_tx(sampler) +); + +gA6_lab5_vlg_check_tst tb_out( + .dealer_wins(dealer_wins), + .done(done), + .hit(hit), + .led_display1(led_display1), + .led_display2(led_display2), + .led_display3(led_display3), + .led_display4(led_display4), + .player_wins(player_wins), + .state_out(state_out), + .sum_out(sum_out), + .sampler_rx(sampler) +); +endmodule + diff --git a/lab5/simulation/qsim/transcript b/lab5/simulation/qsim/transcript new file mode 100644 index 0000000..3ae6e3c --- /dev/null +++ b/lab5/simulation/qsim/transcript @@ -0,0 +1,33 @@ +# do gA6_lab5.do +# ** Warning: (vlib-34) Library already exists at "work". +# +# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012 +# -- Compiling module gA6_lab5 +# +# Top level modules: +# gA6_lab5 +# Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012 +# -- Compiling module gA6_lab5_vlg_sample_tst +# -- Compiling module gA6_lab5_vlg_check_tst +# -- Compiling module gA6_lab5_vlg_vec_tst +# +# Top level modules: +# gA6_lab5_vlg_vec_tst +# vsim -L cycloneii_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate -c -t 1ps -novopt work.gA6_lab5_vlg_vec_tst +# Loading work.gA6_lab5_vlg_vec_tst +# Loading work.gA6_lab5 +# Loading cycloneii_ver.cycloneii_io +# Loading cycloneii_ver.cycloneii_mux21 +# Loading cycloneii_ver.cycloneii_dffe +# Loading cycloneii_ver.cycloneii_asynch_io +# Loading cycloneii_ver.cycloneii_clkctrl +# Loading cycloneii_ver.cycloneii_mux41 +# Loading cycloneii_ver.cycloneii_ena_reg +# Loading cycloneii_ver.cycloneii_lcell_comb +# Loading cycloneii_ver.cycloneii_lcell_ff +# Loading work.gA6_lab5_vlg_sample_tst +# Loading work.gA6_lab5_vlg_check_tst +# Loading cycloneii_ver.CYCLONEII_PRIM_DFFE +# Simulation passed ! +# ** Note: $finish : gA6_lab5.vt(417) +# Time: 1 us Iteration: 0 Instance: /gA6_lab5_vlg_vec_tst/tb_out diff --git a/lab5/simulation/qsim/vsim.wlf b/lab5/simulation/qsim/vsim.wlf new file mode 100644 index 0000000..7016a38 Binary files /dev/null and b/lab5/simulation/qsim/vsim.wlf differ diff --git a/lab5/simulation/qsim/work/_info b/lab5/simulation/qsim/work/_info new file mode 100644 index 0000000..10a6d6a --- /dev/null +++ b/lab5/simulation/qsim/work/_info @@ -0,0 +1,85 @@ +m255 +K3 +13 +cModel Technology +Z0 dC:\home\abbas\dsd_A6\lab5\simulation\qsim +vgA6_lab5 +Z1 Ia6Z7GEjKEe1MzkO`A7cjQ0 +Z2 V1D[]1z=ImBf2ZbGU5mR;U0 +Z3 dC:\home\abbas\dsd_A6\lab5\simulation\qsim +Z4 w1511999705 +Z5 8gA6_lab5.vo +Z6 FgA6_lab5.vo +L0 31 +Z7 OV;L;10.1d;51 +r1 +31 +Z8 !s90 -work|work|gA6_lab5.vo| +Z9 o-work work -O0 +Z10 ng@a6_lab5 +!i10b 1 +Z11 !s100 @[_memWilhLSX7>Q838`^1 +!s85 0 +Z12 !s108 1511999707.044000 +Z13 !s107 gA6_lab5.vo| +!s101 -O0 +vgA6_lab5_vlg_check_tst +!i10b 1 +Z14 !s100 =1Fl23A9?lbTB:JHUThon3 +Z15 I?dTeUOl2A5PUMb?n3`UPUFN0 +Z26 V[JI0fiWMfY>2BCS?gi2 +R3 +R17 +R18 +R19 +L0 29 +R7 +r1 +!s85 0 +31 +R20 +R21 +R22 +!s101 -O0 +R9 +Z27 ng@a6_lab5_vlg_sample_tst +vgA6_lab5_vlg_vec_tst +!i10b 1 +Z28 !s100 SJYZOfg_Pz60RDcA;966H3 +Z29 ISCha7;;H6YcOn3iH[7mAg2 +Z30 VYlc4BZkZ5zXMDTS]KZJUS1 +R3 +R17 +R18 +R19 +Z31 L0 421 +R7 +r1 +!s85 0 +31 +R20 +R21 +R22 +!s101 -O0 +R9 +Z32 ng@a6_lab5_vlg_vec_tst diff --git a/lab5/simulation/qsim/work/_vmake b/lab5/simulation/qsim/work/_vmake new file mode 100644 index 0000000..2f7e729 --- /dev/null +++ b/lab5/simulation/qsim/work/_vmake @@ -0,0 +1,3 @@ +m255 +K3 +cModel Technology diff --git a/lab5/simulation/qsim/work/g@a6_lab5/_primary.dat b/lab5/simulation/qsim/work/g@a6_lab5/_primary.dat new file mode 100644 index 0000000..fb27543 Binary files /dev/null and b/lab5/simulation/qsim/work/g@a6_lab5/_primary.dat differ diff --git a/lab5/simulation/qsim/work/g@a6_lab5/_primary.dbs b/lab5/simulation/qsim/work/g@a6_lab5/_primary.dbs new file mode 100644 index 0000000..28e3eea Binary files /dev/null and b/lab5/simulation/qsim/work/g@a6_lab5/_primary.dbs differ diff --git a/lab5/simulation/qsim/work/g@a6_lab5/_primary.vhd b/lab5/simulation/qsim/work/g@a6_lab5/_primary.vhd new file mode 100644 index 0000000..f13ca2e --- /dev/null +++ b/lab5/simulation/qsim/work/g@a6_lab5/_primary.vhd @@ -0,0 +1,21 @@ +library verilog; +use verilog.vl_types.all; +entity gA6_lab5 is + port( + hit : out vl_logic; + clk : in vl_logic; + rst : in vl_logic; + turn : in vl_logic; + sum : in vl_logic_vector(5 downto 0); + done : out vl_logic; + player_wins : out vl_logic; + player_sum : in vl_logic_vector(5 downto 0); + dealer_wins : out vl_logic; + led_display1 : out vl_logic_vector(6 downto 0); + led_display2 : out vl_logic_vector(6 downto 0); + led_display3 : out vl_logic_vector(6 downto 0); + led_display4 : out vl_logic_vector(6 downto 0); + state_out : out vl_logic_vector(1 downto 0); + sum_out : out vl_logic_vector(5 downto 0) + ); +end gA6_lab5; diff --git a/lab5/simulation/qsim/work/g@a6_lab5/verilog.prw b/lab5/simulation/qsim/work/g@a6_lab5/verilog.prw new file mode 100644 index 0000000..68b760e Binary files /dev/null and b/lab5/simulation/qsim/work/g@a6_lab5/verilog.prw differ diff --git a/lab5/simulation/qsim/work/g@a6_lab5/verilog.psm b/lab5/simulation/qsim/work/g@a6_lab5/verilog.psm new file mode 100644 index 0000000..f0bc76e Binary files /dev/null and b/lab5/simulation/qsim/work/g@a6_lab5/verilog.psm differ diff --git a/lab5/simulation/qsim/work/g@a6_lab5_vlg_check_tst/_primary.dat b/lab5/simulation/qsim/work/g@a6_lab5_vlg_check_tst/_primary.dat new file mode 100644 index 0000000..369bcd3 Binary files /dev/null and b/lab5/simulation/qsim/work/g@a6_lab5_vlg_check_tst/_primary.dat differ diff --git a/lab5/simulation/qsim/work/g@a6_lab5_vlg_check_tst/_primary.dbs b/lab5/simulation/qsim/work/g@a6_lab5_vlg_check_tst/_primary.dbs new file mode 100644 index 0000000..382b412 Binary files /dev/null and b/lab5/simulation/qsim/work/g@a6_lab5_vlg_check_tst/_primary.dbs differ diff --git a/lab5/simulation/qsim/work/g@a6_lab5_vlg_check_tst/_primary.vhd b/lab5/simulation/qsim/work/g@a6_lab5_vlg_check_tst/_primary.vhd new file mode 100644 index 0000000..4b4a74a --- /dev/null +++ b/lab5/simulation/qsim/work/g@a6_lab5_vlg_check_tst/_primary.vhd @@ -0,0 +1,17 @@ +library verilog; +use verilog.vl_types.all; +entity gA6_lab5_vlg_check_tst is + port( + dealer_wins : in vl_logic; + done : in vl_logic; + hit : in vl_logic; + led_display1 : in vl_logic_vector(6 downto 0); + led_display2 : in vl_logic_vector(6 downto 0); + led_display3 : in vl_logic_vector(6 downto 0); + led_display4 : in vl_logic_vector(6 downto 0); + player_wins : in vl_logic; + state_out : in vl_logic_vector(1 downto 0); + sum_out : in vl_logic_vector(5 downto 0); + sampler_rx : in vl_logic + ); +end gA6_lab5_vlg_check_tst; diff --git a/lab5/simulation/qsim/work/g@a6_lab5_vlg_check_tst/verilog.prw b/lab5/simulation/qsim/work/g@a6_lab5_vlg_check_tst/verilog.prw new file mode 100644 index 0000000..ede571d Binary files /dev/null and b/lab5/simulation/qsim/work/g@a6_lab5_vlg_check_tst/verilog.prw differ diff --git a/lab5/simulation/qsim/work/g@a6_lab5_vlg_check_tst/verilog.psm b/lab5/simulation/qsim/work/g@a6_lab5_vlg_check_tst/verilog.psm new file mode 100644 index 0000000..ec2a51c Binary files /dev/null and b/lab5/simulation/qsim/work/g@a6_lab5_vlg_check_tst/verilog.psm differ diff --git a/lab5/simulation/qsim/work/g@a6_lab5_vlg_sample_tst/_primary.dat b/lab5/simulation/qsim/work/g@a6_lab5_vlg_sample_tst/_primary.dat new file mode 100644 index 0000000..eb53a86 Binary files /dev/null and b/lab5/simulation/qsim/work/g@a6_lab5_vlg_sample_tst/_primary.dat differ diff --git a/lab5/simulation/qsim/work/g@a6_lab5_vlg_sample_tst/_primary.dbs b/lab5/simulation/qsim/work/g@a6_lab5_vlg_sample_tst/_primary.dbs new file mode 100644 index 0000000..d5c59f4 Binary files /dev/null and b/lab5/simulation/qsim/work/g@a6_lab5_vlg_sample_tst/_primary.dbs differ diff --git a/lab5/simulation/qsim/work/g@a6_lab5_vlg_sample_tst/_primary.vhd b/lab5/simulation/qsim/work/g@a6_lab5_vlg_sample_tst/_primary.vhd new file mode 100644 index 0000000..9aca1fe --- /dev/null +++ b/lab5/simulation/qsim/work/g@a6_lab5_vlg_sample_tst/_primary.vhd @@ -0,0 +1,12 @@ +library verilog; +use verilog.vl_types.all; +entity gA6_lab5_vlg_sample_tst is + port( + clk : in vl_logic; + player_sum : in vl_logic_vector(5 downto 0); + rst : in vl_logic; + sum : in vl_logic_vector(5 downto 0); + turn : in vl_logic; + sampler_tx : out vl_logic + ); +end gA6_lab5_vlg_sample_tst; diff --git a/lab5/simulation/qsim/work/g@a6_lab5_vlg_sample_tst/verilog.prw b/lab5/simulation/qsim/work/g@a6_lab5_vlg_sample_tst/verilog.prw new file mode 100644 index 0000000..107b550 Binary files /dev/null and b/lab5/simulation/qsim/work/g@a6_lab5_vlg_sample_tst/verilog.prw differ diff --git a/lab5/simulation/qsim/work/g@a6_lab5_vlg_sample_tst/verilog.psm b/lab5/simulation/qsim/work/g@a6_lab5_vlg_sample_tst/verilog.psm new file mode 100644 index 0000000..702941e Binary files /dev/null and b/lab5/simulation/qsim/work/g@a6_lab5_vlg_sample_tst/verilog.psm differ diff --git a/lab5/simulation/qsim/work/g@a6_lab5_vlg_vec_tst/_primary.dat b/lab5/simulation/qsim/work/g@a6_lab5_vlg_vec_tst/_primary.dat new file mode 100644 index 0000000..266f8e8 Binary files /dev/null and b/lab5/simulation/qsim/work/g@a6_lab5_vlg_vec_tst/_primary.dat differ diff --git a/lab5/simulation/qsim/work/g@a6_lab5_vlg_vec_tst/_primary.dbs b/lab5/simulation/qsim/work/g@a6_lab5_vlg_vec_tst/_primary.dbs new file mode 100644 index 0000000..33074c1 Binary files /dev/null and b/lab5/simulation/qsim/work/g@a6_lab5_vlg_vec_tst/_primary.dbs differ diff --git a/lab5/simulation/qsim/work/g@a6_lab5_vlg_vec_tst/_primary.vhd b/lab5/simulation/qsim/work/g@a6_lab5_vlg_vec_tst/_primary.vhd new file mode 100644 index 0000000..307f20c --- /dev/null +++ b/lab5/simulation/qsim/work/g@a6_lab5_vlg_vec_tst/_primary.vhd @@ -0,0 +1,4 @@ +library verilog; +use verilog.vl_types.all; +entity gA6_lab5_vlg_vec_tst is +end gA6_lab5_vlg_vec_tst; diff --git a/lab5/simulation/qsim/work/g@a6_lab5_vlg_vec_tst/verilog.prw b/lab5/simulation/qsim/work/g@a6_lab5_vlg_vec_tst/verilog.prw new file mode 100644 index 0000000..f0e26dc Binary files /dev/null and b/lab5/simulation/qsim/work/g@a6_lab5_vlg_vec_tst/verilog.prw differ diff --git a/lab5/simulation/qsim/work/g@a6_lab5_vlg_vec_tst/verilog.psm b/lab5/simulation/qsim/work/g@a6_lab5_vlg_vec_tst/verilog.psm new file mode 100644 index 0000000..066f49a Binary files /dev/null and b/lab5/simulation/qsim/work/g@a6_lab5_vlg_vec_tst/verilog.psm differ