From c4f34ed05f45a9732b73bc16103dc66ebfef4f20 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Tue, 12 Nov 2024 16:44:38 +1300 Subject: [PATCH 1/8] Start removing guidelines folder Disable the export to docs and remove any references to the guidelines folder. --- Makefile | 9 +++------ README.md | 3 --- docs/source/getting_started/installation.rst | 4 ---- .../yosys_internals/extending_yosys/extensions.rst | 6 +----- kernel/yosys.h | 2 -- 5 files changed, 4 insertions(+), 20 deletions(-) diff --git a/Makefile b/Makefile index 2dda052f90e..ef4af66f9cd 100644 --- a/Makefile +++ b/Makefile @@ -997,15 +997,12 @@ docs/source/cell/word_add.rst: $(TARGETS) $(EXTRA_TARGETS) docs/source/generated/cells.json: docs/source/generated $(TARGETS) $(EXTRA_TARGETS) $(Q) ./$(PROGRAM_PREFIX)yosys -p 'help -dump-cells-json $@' -PHONY: docs/gen docs/guidelines docs/usage docs/reqs +PHONY: docs/gen docs/usage docs/reqs docs/gen: $(TARGETS) $(Q) $(MAKE) -C docs gen -DOCS_GUIDELINE_FILES := GettingStarted CodingStyle -DOCS_GUIDELINE_SOURCE := $(addprefix guidelines/,$(DOCS_GUIDELINE_FILES)) -docs/guidelines docs/source/generated: $(DOCS_GUIDELINE_SOURCE) +docs/source/generated: $(Q) mkdir -p docs/source/generated - $(Q) cp -f $(DOCS_GUIDELINE_SOURCE) docs/source/generated # some commands return an error and print the usage text to stderr define DOC_USAGE_STDERR @@ -1035,7 +1032,7 @@ docs/reqs: $(Q) $(MAKE) -C docs reqs .PHONY: docs/prep -docs/prep: docs/source/cmd/abc.rst docs/source/generated/cells.json docs/gen docs/guidelines docs/usage +docs/prep: docs/source/cmd/abc.rst docs/source/generated/cells.json docs/gen docs/usage DOC_TARGET ?= html docs: docs/prep diff --git a/README.md b/README.md index 02495c71af4..fe9c72f7b5c 100644 --- a/README.md +++ b/README.md @@ -47,9 +47,6 @@ The "Documentation" page on the web site contains links to more resources, including a manual that even describes some of the Yosys internals: - https://yosyshq.net/yosys/documentation.html -The directory `guidelines` contains additional information -for people interested in using the Yosys C++ APIs. - Users interested in formal verification might want to use the formal verification front-end for Yosys, SymbiYosys: - https://symbiyosys.readthedocs.io/en/latest/ diff --git a/docs/source/getting_started/installation.rst b/docs/source/getting_started/installation.rst index 57ae5303639..a53d47e9853 100644 --- a/docs/source/getting_started/installation.rst +++ b/docs/source/getting_started/installation.rst @@ -161,10 +161,6 @@ directories: ``frontends/`` This directory contains a subdirectory for each of the frontend modules. -``guidelines/`` - Contains developer guidelines, including the code of conduct and coding style - guide. - ``kernel/`` This directory contains all the core functionality of Yosys. This includes the functions and definitions for working with the RTLIL data structures diff --git a/docs/source/yosys_internals/extending_yosys/extensions.rst b/docs/source/yosys_internals/extending_yosys/extensions.rst index 4063641d479..b02c4cd992f 100644 --- a/docs/source/yosys_internals/extending_yosys/extensions.rst +++ b/docs/source/yosys_internals/extending_yosys/extensions.rst @@ -11,11 +11,7 @@ Writing extensions This chapter contains some bits and pieces of information about programming yosys extensions. Don't be afraid to ask questions on the YosysHQ Slack. -The :file:`guidelines/` directory of the Yosys source code contains notes on -various aspects of Yosys development. In particular, the files GettingStarted -and CodingStyle may be of interest. - -.. todo:: what's in guidelines/GettingStarted that's missing from the manual? +.. todo:: mention coding guide Quick guide ----------- diff --git a/kernel/yosys.h b/kernel/yosys.h index 5922d9ab752..903540a9e4d 100644 --- a/kernel/yosys.h +++ b/kernel/yosys.h @@ -32,8 +32,6 @@ // // This header is very boring. It just defines some general things that // belong nowhere else and includes the interesting headers. -// -// Find more information in the "guidelines/GettingStarted" file. #ifndef YOSYS_H From 66eec4352775d1f268639b3051971eecba2dd015 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Tue, 12 Nov 2024 17:17:17 +1300 Subject: [PATCH 2/8] Goodbye guidelines (except GettingStarted) Drop the parts that are being dropped. Move the things that are being moved. Also move the verilog stuff out of README and into the docs. GettingStarted is less cut and dry, so hold off on that one. --- README.md | 426 +++--------------- .../extending_yosys/contributing.rst | 12 +- .../yosys_internals/extending_yosys/index.rst | 1 + .../extending_yosys/test_suites.rst | 75 ++- docs/source/yosys_internals/index.rst | 1 + docs/source/yosys_internals/verilog.rst | 364 +++++++++++++++ guidelines/Checklists | 116 ----- guidelines/CodeOfConduct | 72 --- guidelines/UnitTests | 69 --- guidelines/Windows | 83 ---- kernel/rtlil.cc | 15 + 11 files changed, 527 insertions(+), 707 deletions(-) rename guidelines/CodingStyle => docs/source/yosys_internals/extending_yosys/contributing.rst (86%) create mode 100644 docs/source/yosys_internals/verilog.rst delete mode 100644 guidelines/Checklists delete mode 100644 guidelines/CodeOfConduct delete mode 100644 guidelines/UnitTests delete mode 100644 guidelines/Windows diff --git a/README.md b/README.md index fe9c72f7b5c..1defe7c9642 100644 --- a/README.md +++ b/README.md @@ -263,367 +263,6 @@ The command ``prep`` provides a good default word-level synthesis script, as used in SMT-based formal verification. -Unsupported Verilog-2005 Features -================================= - -The following Verilog-2005 features are not supported by -Yosys and there are currently no plans to add support -for them: - -- Non-synthesizable language features as defined in - IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002 - -- The ``tri``, ``triand`` and ``trior`` net types - -- The ``config`` and ``disable`` keywords and library map files - - -Verilog Attributes and non-standard features -============================================ - -- The ``full_case`` attribute on case statements is supported - (also the non-standard ``// synopsys full_case`` directive) - -- The ``parallel_case`` attribute on case statements is supported - (also the non-standard ``// synopsys parallel_case`` directive) - -- The ``// synopsys translate_off`` and ``// synopsys translate_on`` - directives are also supported (but the use of ``` `ifdef .. `endif ``` - is strongly recommended instead). - -- The ``nomem2reg`` attribute on modules or arrays prohibits the - automatic early conversion of arrays to separate registers. This - is potentially dangerous. Usually the front-end has good reasons - for converting an array to a list of registers. Prohibiting this - step will likely result in incorrect synthesis results. - -- The ``mem2reg`` attribute on modules or arrays forces the early - conversion of arrays to separate registers. - -- The ``nomeminit`` attribute on modules or arrays prohibits the - creation of initialized memories. This effectively puts ``mem2reg`` - on all memories that are written to in an ``initial`` block and - are not ROMs. - -- The ``nolatches`` attribute on modules or always-blocks - prohibits the generation of logic-loops for latches. Instead - all not explicitly assigned values default to x-bits. This does - not affect clocked storage elements such as flip-flops. - -- The ``nosync`` attribute on registers prohibits the generation of a - storage element. The register itself will always have all bits set - to 'x' (undefined). The variable may only be used as blocking assigned - temporary variable within an always block. This is mostly used internally - by Yosys to synthesize Verilog functions and access arrays. - -- The ``nowrshmsk`` attribute on a register prohibits the generation of - shift-and-mask type circuits for writing to bit slices of that register. - -- The ``onehot`` attribute on wires mark them as one-hot state register. This - is used for example for memory port sharing and set by the fsm_map pass. - -- The ``blackbox`` attribute on modules is used to mark empty stub modules - that have the same ports as the real thing but do not contain information - on the internal configuration. This modules are only used by the synthesis - passes to identify input and output ports of cells. The Verilog backend - also does not output blackbox modules on default. ``read_verilog``, unless - called with ``-noblackbox`` will automatically set the blackbox attribute - on any empty module it reads. - -- The ``noblackbox`` attribute set on an empty module prevents ``read_verilog`` - from automatically setting the blackbox attribute on the module. - -- The ``whitebox`` attribute on modules triggers the same behavior as - ``blackbox``, but is for whitebox modules, i.e. library modules that - contain a behavioral model of the cell type. - -- The ``lib_whitebox`` attribute overwrites ``whitebox`` when ``read_verilog`` - is run in `-lib` mode. Otherwise it's automatically removed. - -- The ``dynports`` attribute is used by the Verilog front-end to mark modules - that have ports with a width that depends on a parameter. - -- The ``hdlname`` attribute is used by some passes to document the original - (HDL) name of a module when renaming a module. It should contain a single - name, or, when describing a hierarchical name in a flattened design, multiple - names separated by a single space character. - -- The ``keep`` attribute on cells and wires is used to mark objects that should - never be removed by the optimizer. This is used for example for cells that - have hidden connections that are not part of the netlist, such as IO pads. - Setting the ``keep`` attribute on a module has the same effect as setting it - on all instances of the module. - -- The ``keep_hierarchy`` attribute on cells and modules keeps the ``flatten`` - command from flattening the indicated cells and modules. - -- The ``init`` attribute on wires is set by the frontend when a register is - initialized "FPGA-style" with ``reg foo = val``. It can be used during - synthesis to add the necessary reset logic. - -- The ``top`` attribute on a module marks this module as the top of the - design hierarchy. The ``hierarchy`` command sets this attribute when called - with ``-top``. Other commands, such as ``flatten`` and various backends - use this attribute to determine the top module. - -- The ``src`` attribute is set on cells and wires created by to the string - ``:`` by the HDL front-end and is then carried - through the synthesis. When entities are combined, a new |-separated - string is created that contains all the string from the original entities. - -- The ``defaultvalue`` attribute is used to store default values for - module inputs. The attribute is attached to the input wire by the HDL - front-end when the input is declared with a default value. - -- The ``parameter`` and ``localparam`` attributes are used to mark wires - that represent module parameters or localparams (when the HDL front-end - is run in ``-pwires`` mode). - -- Wires marked with the ``hierconn`` attribute are connected to wires with the - same name (format ``cell_name.identifier``) when they are imported from - sub-modules by ``flatten``. - -- The ``clkbuf_driver`` attribute can be set on an output port of a blackbox - module to mark it as a clock buffer output, and thus prevent ``clkbufmap`` - from inserting another clock buffer on a net driven by such output. - -- The ``clkbuf_sink`` attribute can be set on an input port of a module to - request clock buffer insertion by the ``clkbufmap`` pass. - -- The ``clkbuf_inv`` attribute can be set on an output port of a module - with the value set to the name of an input port of that module. When - the ``clkbufmap`` would otherwise insert a clock buffer on this output, - it will instead try inserting the clock buffer on the input port (this - is used to implement clock inverter cells that clock buffer insertion - will "see through"). - -- The ``clkbuf_inhibit`` is the default attribute to set on a wire to prevent - automatic clock buffer insertion by ``clkbufmap``. This behaviour can be - overridden by providing a custom selection to ``clkbufmap``. - -- The ``invertible_pin`` attribute can be set on a port to mark it as - invertible via a cell parameter. The name of the inversion parameter - is specified as the value of this attribute. The value of the inversion - parameter must be of the same width as the port, with 1 indicating - an inverted bit and 0 indicating a non-inverted bit. - -- The ``iopad_external_pin`` attribute on a blackbox module's port marks - it as the external-facing pin of an I/O pad, and prevents ``iopadmap`` - from inserting another pad cell on it. - -- The module attribute ``abc9_lut`` is an integer attribute indicating to - `abc9` that this module describes a LUT with an area cost of this value, and - propagation delays described using `specify` statements. - -- The module attribute ``abc9_box`` is a boolean specifying a black/white-box - definition, with propagation delays described using `specify` statements, for - use by `abc9`. - -- The port attribute ``abc9_carry`` marks the carry-in (if an input port) and - carry-out (if output port) ports of a box. This information is necessary for - `abc9` to preserve the integrity of carry-chains. Specifying this attribute - onto a bus port will affect only its most significant bit. - -- The module attribute ``abc9_flop`` is a boolean marking the module as a - flip-flop. This allows `abc9` to analyse its contents in order to perform - sequential synthesis. - -- The frontend sets attributes ``always_comb``, ``always_latch`` and - ``always_ff`` on processes derived from SystemVerilog style always blocks - according to the type of the always. These are checked for correctness in - ``proc_dlatch``. - -- The cell attribute ``wildcard_port_conns`` represents wildcard port - connections (SystemVerilog ``.*``). These are resolved to concrete - connections to matching wires in ``hierarchy``. - -- In addition to the ``(* ... *)`` attribute syntax, Yosys supports - the non-standard ``{* ... *}`` attribute syntax to set default attributes - for everything that comes after the ``{* ... *}`` statement. (Reset - by adding an empty ``{* *}`` statement.) - -- In module parameter and port declarations, and cell port and parameter - lists, a trailing comma is ignored. This simplifies writing Verilog code - generators a bit in some cases. - -- Modules can be declared with ``module mod_name(...);`` (with three dots - instead of a list of module ports). With this syntax it is sufficient - to simply declare a module port as 'input' or 'output' in the module - body. - -- When defining a macro with `define, all text between triple double quotes - is interpreted as macro body, even if it contains unescaped newlines. The - triple double quotes are removed from the macro body. For example: - - `define MY_MACRO(a, b) """ - assign a = 23; - assign b = 42; - """ - -- The attribute ``via_celltype`` can be used to implement a Verilog task or - function by instantiating the specified cell type. The value is the name - of the cell type to use. For functions the name of the output port can - be specified by appending it to the cell type separated by a whitespace. - The body of the task or function is unused in this case and can be used - to specify a behavioral model of the cell type for simulation. For example: - - module my_add3(A, B, C, Y); - parameter WIDTH = 8; - input [WIDTH-1:0] A, B, C; - output [WIDTH-1:0] Y; - ... - endmodule - - module top; - ... - (* via_celltype = "my_add3 Y" *) - (* via_celltype_defparam_WIDTH = 32 *) - function [31:0] add3; - input [31:0] A, B, C; - begin - add3 = A + B + C; - end - endfunction - ... - endmodule - -- The ``wiretype`` attribute is added by the verilog parser for wires of a - typedef'd type to indicate the type identifier. - -- Various ``enum_value_{value}`` attributes are added to wires of an enumerated type - to give a map of possible enum items to their values. - -- The ``enum_base_type`` attribute is added to enum items to indicate which - enum they belong to (enums -- anonymous and otherwise -- are - automatically named with an auto-incrementing counter). Note that enums - are currently not strongly typed. - -- A limited subset of DPI-C functions is supported. The plugin mechanism - (see ``help plugin``) can be used to load .so files with implementations - of DPI-C routines. As a non-standard extension it is possible to specify - a plugin alias using the ``:`` syntax. For example: - - module dpitest; - import "DPI-C" function foo:round = real my_round (real); - parameter real r = my_round(12.345); - endmodule - - $ yosys -p 'plugin -a foo -i /lib/libm.so; read_verilog dpitest.v' - -- Sized constants (the syntax ``'s?[bodh]``) support constant - expressions as ````. If the expression is not a simple identifier, it - must be put in parentheses. Examples: ``WIDTH'd42``, ``(4+2)'b101010`` - -- The system tasks ``$finish``, ``$stop`` and ``$display`` are supported in - initial blocks in an unconditional context (only if/case statements on - expressions over parameters and constant values are allowed). The intended - use for this is synthesis-time DRC. - -- There is limited support for converting ``specify`` .. ``endspecify`` - statements to special ``$specify2``, ``$specify3``, and ``$specrule`` cells, - for use in blackboxes and whiteboxes. Use ``read_verilog -specify`` to - enable this functionality. (By default these blocks are ignored.) - -- The ``reprocess_after`` internal attribute is used by the Verilog frontend to - mark cells with bindings which might depend on the specified instantiated - module. Modules with such cells will be reprocessed during the ``hierarchy`` - pass once the referenced module definition(s) become available. - -- The ``smtlib2_module`` attribute can be set on a blackbox module to specify a - formal model directly using SMT-LIB 2. For such a module, the - ``smtlib2_comb_expr`` attribute can be used on output ports to define their - value using an SMT-LIB 2 expression. For example: - - (* blackbox *) - (* smtlib2_module *) - module submod(a, b); - input [7:0] a; - (* smtlib2_comb_expr = "(bvnot a)" *) - output [7:0] b; - endmodule - -Non-standard or SystemVerilog features for formal verification -============================================================== - -- Support for ``assert``, ``assume``, ``restrict``, and ``cover`` is enabled - when ``read_verilog`` is called with ``-formal``. - -- The system task ``$initstate`` evaluates to 1 in the initial state and - to 0 otherwise. - -- The system function ``$anyconst`` evaluates to any constant value. This is - equivalent to declaring a reg as ``rand const``, but also works outside - of checkers. (Yosys also supports ``rand const`` outside checkers.) - -- The system function ``$anyseq`` evaluates to any value, possibly a different - value in each cycle. This is equivalent to declaring a reg as ``rand``, - but also works outside of checkers. (Yosys also supports ``rand`` - variables outside checkers.) - -- The system functions ``$allconst`` and ``$allseq`` can be used to construct - formal exist-forall problems. Assumptions only hold if the trace satisfies - the assumption for all ``$allconst/$allseq`` values. For assertions and cover - statements it is sufficient if just one ``$allconst/$allseq`` value triggers - the property (similar to ``$anyconst/$anyseq``). - -- Wires/registers declared using the ``anyconst/anyseq/allconst/allseq`` attribute - (for example ``(* anyconst *) reg [7:0] foobar;``) will behave as if driven - by a ``$anyconst/$anyseq/$allconst/$allseq`` function. - -- The SystemVerilog tasks ``$past``, ``$stable``, ``$rose`` and ``$fell`` are - supported in any clocked block. - -- The syntax ``@($global_clock)`` can be used to create FFs that have no - explicit clock input (``$ff`` cells). The same can be achieved by using - ``@(posedge )`` or ``@(negedge )`` when ```` - is marked with the ``(* gclk *)`` Verilog attribute. - - -Supported features from SystemVerilog -===================================== - -When ``read_verilog`` is called with ``-sv``, it accepts some language features -from SystemVerilog: - -- The ``assert`` statement from SystemVerilog is supported in its most basic - form. In module context: ``assert property ();`` and within an - always block: ``assert();``. It is transformed to an ``$assert`` cell. - -- The ``assume``, ``restrict``, and ``cover`` statements from SystemVerilog are - also supported. The same limitations as with the ``assert`` statement apply. - -- The keywords ``always_comb``, ``always_ff`` and ``always_latch``, ``logic`` - and ``bit`` are supported. - -- Declaring free variables with ``rand`` and ``rand const`` is supported. - -- Checkers without a port list that do not need to be instantiated (but instead - behave like a named block) are supported. - -- SystemVerilog packages are supported. Once a SystemVerilog file is read - into a design with ``read_verilog``, all its packages are available to - SystemVerilog files being read into the same design afterwards. - -- typedefs are supported (including inside packages) - - type casts are currently not supported - -- enums are supported (including inside packages) - - but are currently not strongly typed - -- packed structs and unions are supported - - arrays of packed structs/unions are currently not supported - - structure literals are currently not supported - -- multidimensional arrays are supported - - array assignment of unpacked arrays is currently not supported - - array literals are currently not supported - -- SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether - ports are inputs or outputs are supported. - -- Assignments within expressions are supported. - - Building the documentation ========================== @@ -659,3 +298,68 @@ From the root of the repository, run `make docs`. This will build/rebuild yosys as necessary before generating the website documentation from the yosys help commands. To build for pdf instead of html, call `make docs DOC_TARGET=latexpdf`. + +Building for Windows +==================== + +Creating the Visual Studio Template Project +------------------------------------------- + +1. Create an empty Visual C++ Win32 Console App project + + Microsoft Visual Studio Express 2013 for Windows Desktop + Open New Project Wizard (File -> New Project..) + + Project Name: YosysVS + Solution Name: YosysVS + [X] Create directory for solution + [ ] Add to source control + + [X] Console applications + [X] Empty Project + [ ] SDL checks + +2. Open YosysVS Project Properties + + Select Configuration: All Configurations + + C/C++ -> General -> Additional Include Directories + Add: ..\yosys + + C/C++ -> Preprocessor -> Preprocessor Definitions + Add: _YOSYS_;_CRT_SECURE_NO_WARNINGS + +3. Resulting file system tree: + + YosysVS/ + YosysVS/YosysVS + YosysVS/YosysVS/YosysVS.vcxproj + YosysVS/YosysVS/YosysVS.vcxproj.filters + YosysVS/YosysVS.sdf + YosysVS/YosysVS.sln + YosysVS/YosysVS.v12.suo + +4. Zip YosysVS as YosysVS-Tpl-v1.zip + +Compiling with Visual Studio +---------------------------- + +Visual Studio builds are not directly supported by build scripts, but they are still possible. + +1. Easy way + + - Go to https://github.com/YosysHQ/yosys/actions/workflows/vs.yml?query=branch%3Amain + - Click on the most recent completed run + - In Artifacts region find vcxsrc and click on it to download + - Unpack downloaded ZIP file + - Open YosysVS.sln with Visual Studio + +2. Using WSL or MSYS2 + + - Make sure to have make, python3 and git available + - Git clone yosys repository + - Execute ```make vcxsrc YOSYS_VER=latest``` + - File yosys-win32-vcxsrc-latest.zip will be created + - Transfer that file to location visible by Windows application + - Unpack ZIP + - Open YosysVS.sln with Visual Studio diff --git a/guidelines/CodingStyle b/docs/source/yosys_internals/extending_yosys/contributing.rst similarity index 86% rename from guidelines/CodingStyle rename to docs/source/yosys_internals/extending_yosys/contributing.rst index 491507cdd48..364067f8efc 100644 --- a/guidelines/CodingStyle +++ b/docs/source/yosys_internals/extending_yosys/contributing.rst @@ -1,9 +1,11 @@ -Coding Style -============ +Contributing to Yosys +===================== +Coding Style +------------ Formatting of code ------------------- +~~~~~~~~~~~~~~~~~~ - Yosys code is using tabs for indentation. Tabs are 8 characters. @@ -23,7 +25,7 @@ Formatting of code C++ Language -------------- +~~~~~~~~~~~~ Yosys is written in C++17. @@ -31,4 +33,4 @@ In general Yosys uses "int" instead of "size_t". To avoid compiler warnings for implicit type casts, always use "GetSize(foobar)" instead of "foobar.size()". (GetSize() is defined in kernel/yosys.h) -Use range-based for loops whenever applicable. \ No newline at end of file +Use range-based for loops whenever applicable. diff --git a/docs/source/yosys_internals/extending_yosys/index.rst b/docs/source/yosys_internals/extending_yosys/index.rst index 88f36d5264e..4ee21517bba 100644 --- a/docs/source/yosys_internals/extending_yosys/index.rst +++ b/docs/source/yosys_internals/extending_yosys/index.rst @@ -11,5 +11,6 @@ of interest for developers looking to customise Yosys builds. extensions build_verific functional_ir + contributing test_suites diff --git a/docs/source/yosys_internals/extending_yosys/test_suites.rst b/docs/source/yosys_internals/extending_yosys/test_suites.rst index 7a6b7497774..8a9c4711ef8 100644 --- a/docs/source/yosys_internals/extending_yosys/test_suites.rst +++ b/docs/source/yosys_internals/extending_yosys/test_suites.rst @@ -1,7 +1,7 @@ Testing Yosys ============= -.. todo:: more about the included test suite +.. TODO:: more about the included test suite and how to add tests Automatic testing ----------------- @@ -23,3 +23,76 @@ For up to date information, including OS versions, refer to `the git actions page`_. .. _the git actions page: https://github.com/YosysHQ/yosys/actions + +.. todo:: are unit tests currently working + +.. + How to add a unit test + ---------------------- + + Unit test brings some advantages, briefly, we can list some of them (reference + [1](https://en.wikipedia.org/wiki/Unit_testing)): + + * Tests reduce bugs in new features; + * Tests reduce bugs in existing features; + * Tests are good documentation; + * Tests reduce the cost of change; + * Tests allow refactoring; + + With those advantages in mind, it was required to choose a framework which fits + well with C/C++ code. Hence, it was chosen (google test) + [https://github.com/google/googletest], because it is largely used and it is + relatively easy learn. + + Install and configure google test (manually) + ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + + In this section, you will see a brief description of how to install google + test. However, it is strongly recommended that you take a look to the official + repository (https://github.com/google/googletest) and refers to that if you + have any problem to install it. Follow the steps below: + + * Install: cmake and pthread + * Clone google test project from: https://github.com/google/googletest and + enter in the project directory + * Inside project directory, type: + + ``` + cmake -DBUILD_SHARED_LIBS=ON . + make + ``` + + * After compilation, copy all "*.so" inside directory "googlemock" and + "googlemock/gtest" to "/usr/lib/" + * Done! Now you can compile your tests. + + If you have any problem, go to the official repository to find help. + + Ps.: Some distros already have googletest packed. If your distro supports it, + you can use it instead of compile. + + Create a new unit test + ~~~~~~~~~~~~~~~~~~~~~~ + + If you want to add new unit tests for Yosys, just follow the steps below: + + * Go to directory "yosys/test/unit/" + * In this directory you can find something similar Yosys's directory structure. + To create your unit test file you have to follow this pattern: + fileNameToImplementUnitTest + Test.cc. E.g.: if you want to implement the + unit test for kernel/celledges.cc, you will need to create a file like this: + tests/unit/kernel/celledgesTest.cc; + * Implement your unit test + + Run unit tests + ~~~~~~~~~~~~~~ + + To compile and run all unit tests, just go to yosys root directory and type: + ``` + make unit-test + ``` + + If you want to remove all unit test files, type: + ``` + make clean-unit-test + ``` diff --git a/docs/source/yosys_internals/index.rst b/docs/source/yosys_internals/index.rst index efd865623b0..9631e865331 100644 --- a/docs/source/yosys_internals/index.rst +++ b/docs/source/yosys_internals/index.rst @@ -38,3 +38,4 @@ as reference to implement a similar system in any language. formats/index extending_yosys/index techmap + verilog diff --git a/docs/source/yosys_internals/verilog.rst b/docs/source/yosys_internals/verilog.rst new file mode 100644 index 00000000000..1c9031a4fa9 --- /dev/null +++ b/docs/source/yosys_internals/verilog.rst @@ -0,0 +1,364 @@ +Notes on Verilog support in Yosys +================================= + +.. TODO:: how much of this is specific to the read_verilog and should be in :doc:`/yosys_internals/flow/verilog_frontend`? + +Unsupported Verilog-2005 Features +--------------------------------- + +The following Verilog-2005 features are not supported by +Yosys and there are currently no plans to add support +for them: + +- Non-synthesizable language features as defined in + IEC 62142(E):2005 / IEEE Std. 1364.1(E):2002 + +- The ``tri``, ``triand`` and ``trior`` net types + +- The ``config`` and ``disable`` keywords and library map files + + +Verilog Attributes and non-standard features +-------------------------------------------- + +- The ``full_case`` attribute on case statements is supported + (also the non-standard ``// synopsys full_case`` directive) + +- The ``parallel_case`` attribute on case statements is supported + (also the non-standard ``// synopsys parallel_case`` directive) + +- The ``// synopsys translate_off`` and ``// synopsys translate_on`` + directives are also supported (but the use of ``` `ifdef .. `endif ``` + is strongly recommended instead). + +- The ``nomem2reg`` attribute on modules or arrays prohibits the + automatic early conversion of arrays to separate registers. This + is potentially dangerous. Usually the front-end has good reasons + for converting an array to a list of registers. Prohibiting this + step will likely result in incorrect synthesis results. + +- The ``mem2reg`` attribute on modules or arrays forces the early + conversion of arrays to separate registers. + +- The ``nomeminit`` attribute on modules or arrays prohibits the + creation of initialized memories. This effectively puts ``mem2reg`` + on all memories that are written to in an ``initial`` block and + are not ROMs. + +- The ``nolatches`` attribute on modules or always-blocks + prohibits the generation of logic-loops for latches. Instead + all not explicitly assigned values default to x-bits. This does + not affect clocked storage elements such as flip-flops. + +- The ``nosync`` attribute on registers prohibits the generation of a + storage element. The register itself will always have all bits set + to 'x' (undefined). The variable may only be used as blocking assigned + temporary variable within an always block. This is mostly used internally + by Yosys to synthesize Verilog functions and access arrays. + +- The ``nowrshmsk`` attribute on a register prohibits the generation of + shift-and-mask type circuits for writing to bit slices of that register. + +- The ``onehot`` attribute on wires mark them as one-hot state register. This + is used for example for memory port sharing and set by the fsm_map pass. + +- The ``blackbox`` attribute on modules is used to mark empty stub modules + that have the same ports as the real thing but do not contain information + on the internal configuration. This modules are only used by the synthesis + passes to identify input and output ports of cells. The Verilog backend + also does not output blackbox modules on default. ``read_verilog``, unless + called with ``-noblackbox`` will automatically set the blackbox attribute + on any empty module it reads. + +- The ``noblackbox`` attribute set on an empty module prevents ``read_verilog`` + from automatically setting the blackbox attribute on the module. + +- The ``whitebox`` attribute on modules triggers the same behavior as + ``blackbox``, but is for whitebox modules, i.e. library modules that + contain a behavioral model of the cell type. + +- The ``lib_whitebox`` attribute overwrites ``whitebox`` when ``read_verilog`` + is run in `-lib` mode. Otherwise it's automatically removed. + +- The ``dynports`` attribute is used by the Verilog front-end to mark modules + that have ports with a width that depends on a parameter. + +- The ``hdlname`` attribute is used by some passes to document the original + (HDL) name of a module when renaming a module. It should contain a single + name, or, when describing a hierarchical name in a flattened design, multiple + names separated by a single space character. + +- The ``keep`` attribute on cells and wires is used to mark objects that should + never be removed by the optimizer. This is used for example for cells that + have hidden connections that are not part of the netlist, such as IO pads. + Setting the ``keep`` attribute on a module has the same effect as setting it + on all instances of the module. + +- The ``keep_hierarchy`` attribute on cells and modules keeps the ``flatten`` + command from flattening the indicated cells and modules. + +- The ``init`` attribute on wires is set by the frontend when a register is + initialized "FPGA-style" with ``reg foo = val``. It can be used during + synthesis to add the necessary reset logic. + +- The ``top`` attribute on a module marks this module as the top of the + design hierarchy. The ``hierarchy`` command sets this attribute when called + with ``-top``. Other commands, such as ``flatten`` and various backends + use this attribute to determine the top module. + +- The ``src`` attribute is set on cells and wires created by to the string + ``:`` by the HDL front-end and is then carried + through the synthesis. When entities are combined, a new |-separated + string is created that contains all the string from the original entities. + +- The ``defaultvalue`` attribute is used to store default values for + module inputs. The attribute is attached to the input wire by the HDL + front-end when the input is declared with a default value. + +- The ``parameter`` and ``localparam`` attributes are used to mark wires + that represent module parameters or localparams (when the HDL front-end + is run in ``-pwires`` mode). + +- Wires marked with the ``hierconn`` attribute are connected to wires with the + same name (format ``cell_name.identifier``) when they are imported from + sub-modules by ``flatten``. + +- The ``clkbuf_driver`` attribute can be set on an output port of a blackbox + module to mark it as a clock buffer output, and thus prevent ``clkbufmap`` + from inserting another clock buffer on a net driven by such output. + +- The ``clkbuf_sink`` attribute can be set on an input port of a module to + request clock buffer insertion by the ``clkbufmap`` pass. + +- The ``clkbuf_inv`` attribute can be set on an output port of a module + with the value set to the name of an input port of that module. When + the ``clkbufmap`` would otherwise insert a clock buffer on this output, + it will instead try inserting the clock buffer on the input port (this + is used to implement clock inverter cells that clock buffer insertion + will "see through"). + +- The ``clkbuf_inhibit`` is the default attribute to set on a wire to prevent + automatic clock buffer insertion by ``clkbufmap``. This behaviour can be + overridden by providing a custom selection to ``clkbufmap``. + +- The ``invertible_pin`` attribute can be set on a port to mark it as + invertible via a cell parameter. The name of the inversion parameter + is specified as the value of this attribute. The value of the inversion + parameter must be of the same width as the port, with 1 indicating + an inverted bit and 0 indicating a non-inverted bit. + +- The ``iopad_external_pin`` attribute on a blackbox module's port marks + it as the external-facing pin of an I/O pad, and prevents ``iopadmap`` + from inserting another pad cell on it. + +- The module attribute ``abc9_lut`` is an integer attribute indicating to + `abc9` that this module describes a LUT with an area cost of this value, and + propagation delays described using `specify` statements. + +- The module attribute ``abc9_box`` is a boolean specifying a black/white-box + definition, with propagation delays described using `specify` statements, for + use by `abc9`. + +- The port attribute ``abc9_carry`` marks the carry-in (if an input port) and + carry-out (if output port) ports of a box. This information is necessary for + `abc9` to preserve the integrity of carry-chains. Specifying this attribute + onto a bus port will affect only its most significant bit. + +- The module attribute ``abc9_flop`` is a boolean marking the module as a + flip-flop. This allows `abc9` to analyse its contents in order to perform + sequential synthesis. + +- The frontend sets attributes ``always_comb``, ``always_latch`` and + ``always_ff`` on processes derived from SystemVerilog style always blocks + according to the type of the always. These are checked for correctness in + ``proc_dlatch``. + +- The cell attribute ``wildcard_port_conns`` represents wildcard port + connections (SystemVerilog ``.*``). These are resolved to concrete + connections to matching wires in ``hierarchy``. + +- In addition to the ``(* ... *)`` attribute syntax, Yosys supports + the non-standard ``{* ... *}`` attribute syntax to set default attributes + for everything that comes after the ``{* ... *}`` statement. (Reset + by adding an empty ``{* *}`` statement.) + +- In module parameter and port declarations, and cell port and parameter + lists, a trailing comma is ignored. This simplifies writing Verilog code + generators a bit in some cases. + +- Modules can be declared with ``module mod_name(...);`` (with three dots + instead of a list of module ports). With this syntax it is sufficient + to simply declare a module port as 'input' or 'output' in the module + body. + +- When defining a macro with `define, all text between triple double quotes + is interpreted as macro body, even if it contains unescaped newlines. The + triple double quotes are removed from the macro body. For example: + + `define MY_MACRO(a, b) """ + assign a = 23; + assign b = 42; + """ + +- The attribute ``via_celltype`` can be used to implement a Verilog task or + function by instantiating the specified cell type. The value is the name + of the cell type to use. For functions the name of the output port can + be specified by appending it to the cell type separated by a whitespace. + The body of the task or function is unused in this case and can be used + to specify a behavioral model of the cell type for simulation. For example: + + module my_add3(A, B, C, Y); + parameter WIDTH = 8; + input [WIDTH-1:0] A, B, C; + output [WIDTH-1:0] Y; + ... + endmodule + + module top; + ... + (* via_celltype = "my_add3 Y" *) + (* via_celltype_defparam_WIDTH = 32 *) + function [31:0] add3; + input [31:0] A, B, C; + begin + add3 = A + B + C; + end + endfunction + ... + endmodule + +- The ``wiretype`` attribute is added by the verilog parser for wires of a + typedef'd type to indicate the type identifier. + +- Various ``enum_value_{value}`` attributes are added to wires of an enumerated type + to give a map of possible enum items to their values. + +- The ``enum_base_type`` attribute is added to enum items to indicate which + enum they belong to (enums -- anonymous and otherwise -- are + automatically named with an auto-incrementing counter). Note that enums + are currently not strongly typed. + +- A limited subset of DPI-C functions is supported. The plugin mechanism + (see ``help plugin``) can be used to load .so files with implementations + of DPI-C routines. As a non-standard extension it is possible to specify + a plugin alias using the ``:`` syntax. For example: + + module dpitest; + import "DPI-C" function foo:round = real my_round (real); + parameter real r = my_round(12.345); + endmodule + + $ yosys -p 'plugin -a foo -i /lib/libm.so; read_verilog dpitest.v' + +- Sized constants (the syntax ``'s?[bodh]``) support constant + expressions as ````. If the expression is not a simple identifier, it + must be put in parentheses. Examples: ``WIDTH'd42``, ``(4+2)'b101010`` + +- The system tasks ``$finish``, ``$stop`` and ``$display`` are supported in + initial blocks in an unconditional context (only if/case statements on + expressions over parameters and constant values are allowed). The intended + use for this is synthesis-time DRC. + +- There is limited support for converting ``specify`` .. ``endspecify`` + statements to special ``$specify2``, ``$specify3``, and ``$specrule`` cells, + for use in blackboxes and whiteboxes. Use ``read_verilog -specify`` to + enable this functionality. (By default these blocks are ignored.) + +- The ``reprocess_after`` internal attribute is used by the Verilog frontend to + mark cells with bindings which might depend on the specified instantiated + module. Modules with such cells will be reprocessed during the ``hierarchy`` + pass once the referenced module definition(s) become available. + +- The ``smtlib2_module`` attribute can be set on a blackbox module to specify a + formal model directly using SMT-LIB 2. For such a module, the + ``smtlib2_comb_expr`` attribute can be used on output ports to define their + value using an SMT-LIB 2 expression. For example: + + (* blackbox *) + (* smtlib2_module *) + module submod(a, b); + input [7:0] a; + (* smtlib2_comb_expr = "(bvnot a)" *) + output [7:0] b; + endmodule + +Non-standard or SystemVerilog features for formal verification +-------------------------------------------------------------- + +- Support for ``assert``, ``assume``, ``restrict``, and ``cover`` is enabled + when ``read_verilog`` is called with ``-formal``. + +- The system task ``$initstate`` evaluates to 1 in the initial state and + to 0 otherwise. + +- The system function ``$anyconst`` evaluates to any constant value. This is + equivalent to declaring a reg as ``rand const``, but also works outside + of checkers. (Yosys also supports ``rand const`` outside checkers.) + +- The system function ``$anyseq`` evaluates to any value, possibly a different + value in each cycle. This is equivalent to declaring a reg as ``rand``, + but also works outside of checkers. (Yosys also supports ``rand`` + variables outside checkers.) + +- The system functions ``$allconst`` and ``$allseq`` can be used to construct + formal exist-forall problems. Assumptions only hold if the trace satisfies + the assumption for all ``$allconst/$allseq`` values. For assertions and cover + statements it is sufficient if just one ``$allconst/$allseq`` value triggers + the property (similar to ``$anyconst/$anyseq``). + +- Wires/registers declared using the ``anyconst/anyseq/allconst/allseq`` attribute + (for example ``(* anyconst *) reg [7:0] foobar;``) will behave as if driven + by a ``$anyconst/$anyseq/$allconst/$allseq`` function. + +- The SystemVerilog tasks ``$past``, ``$stable``, ``$rose`` and ``$fell`` are + supported in any clocked block. + +- The syntax ``@($global_clock)`` can be used to create FFs that have no + explicit clock input (``$ff`` cells). The same can be achieved by using + ``@(posedge )`` or ``@(negedge )`` when ```` + is marked with the ``(* gclk *)`` Verilog attribute. + + +Supported features from SystemVerilog +------------------------------------- + +When ``read_verilog`` is called with ``-sv``, it accepts some language features +from SystemVerilog: + +- The ``assert`` statement from SystemVerilog is supported in its most basic + form. In module context: ``assert property ();`` and within an + always block: ``assert();``. It is transformed to an ``$assert`` cell. + +- The ``assume``, ``restrict``, and ``cover`` statements from SystemVerilog are + also supported. The same limitations as with the ``assert`` statement apply. + +- The keywords ``always_comb``, ``always_ff`` and ``always_latch``, ``logic`` + and ``bit`` are supported. + +- Declaring free variables with ``rand`` and ``rand const`` is supported. + +- Checkers without a port list that do not need to be instantiated (but instead + behave like a named block) are supported. + +- SystemVerilog packages are supported. Once a SystemVerilog file is read + into a design with ``read_verilog``, all its packages are available to + SystemVerilog files being read into the same design afterwards. + +- typedefs are supported (including inside packages) + - type casts are currently not supported + +- enums are supported (including inside packages) + - but are currently not strongly typed + +- packed structs and unions are supported + - arrays of packed structs/unions are currently not supported + - structure literals are currently not supported + +- multidimensional arrays are supported + - array assignment of unpacked arrays is currently not supported + - array literals are currently not supported + +- SystemVerilog interfaces (SVIs) are supported. Modports for specifying whether + ports are inputs or outputs are supported. + +- Assignments within expressions are supported. diff --git a/guidelines/Checklists b/guidelines/Checklists deleted file mode 100644 index 75af12fa9e4..00000000000 --- a/guidelines/Checklists +++ /dev/null @@ -1,116 +0,0 @@ -Checklist for adding internal cell types -======================================== - -Things to do right away: - - - Add to kernel/celltypes.h (incl. eval() handling for non-mem cells) - - Add to InternalCellChecker::check() in kernel/rtlil.cc - - Add to techlibs/common/simlib.v - - Add to techlibs/common/techmap.v - -Things to do after finalizing the cell interface: - - - Add support to kernel/satgen.h for the new cell type - - Add to docs/source/CHAPTER_CellLib.rst (or just add a fixme to the bottom) - - Maybe add support to the Verilog backend for dumping such cells as expression - - - -Checklist for creating Yosys releases -===================================== - -Update the CHANGELOG file: - - cd ~yosys - gitk & - vi CHANGELOG - - -Update and check documentation: - - cd ~yosys - make docs - - sanity check the figures in docs/images - - if there are any odd things -> investigate - - cd ~yosys - vi README guidelines/* - - is the information provided in those file still up to date - - -Then with default config setting: - - cd ~yosys - make vgtest - - cd ~yosys - ./yosys -p 'proc; show' tests/simple/fiedler-cooley.v - ./yosys -p 'proc; opt; show' tests/simple/fiedler-cooley.v - ./yosys -p 'synth; show' tests/simple/fiedler-cooley.v - ./yosys -p 'synth_xilinx -top up3down5; show' tests/simple/fiedler-cooley.v - - cd ~yosys/examples/cmos - bash testbench.sh - - cd ~yosys/examples/basys3 - bash run.sh - - -Test building plugins with various of the standard passes: - - yosys-config --build test.so equiv_simple.cc - - also check the code examples in guidelines/GettingStarted - - -And if a version of the verific library is currently available: - - cd ~yosys - cat frontends/verific/build_amd64.txt - - follow instructions - - cd frontends/verific - ../../yosys test_navre.ys - - -Finally run all tests with "make config-{clang,gcc}": - - cd ~yosys - make clean - make test - make ystests - make vloghtb - make install - - cd ~yosys-bigsim - make clean - make full - - cd ~vloghammer - make purge gen_issues gen_samples - make SYN_LIST="yosys" SIM_LIST="icarus yosim verilator" REPORT_FULL=1 world - chromium-browser report.html - - -Release: - - - set YOSYS_VER to x.y.z in Makefile - - remove "bumpversion" target from Makefile - - update version string in CHANGELOG - git commit -am "Yosys x.y.z" - - - push tag to github - - post changelog on github - - post short release note on reddit - - -Updating the website: - - cd ~yosys - make install - - cd ~yosys-web - make update_show - git commit -am update - make push - - - Read the Docs updates handled by Jenkins on source change diff --git a/guidelines/CodeOfConduct b/guidelines/CodeOfConduct deleted file mode 100644 index 92decd3b6a5..00000000000 --- a/guidelines/CodeOfConduct +++ /dev/null @@ -1,72 +0,0 @@ -Contributor Covenant Code of Conduct - -Our Pledge - -In the interest of fostering an open and welcoming environment, we as -contributors and maintainers pledge to making participation in our project and -our community a harassment-free experience for everyone, regardless of age, body -size, disability, ethnicity, gender identity and expression, level of experience, -nationality, personal appearance, race, religion, or sexual identity and -orientation. - -Our Standards - -Examples of behavior that contributes to creating a positive environment -include: - -* Using welcoming and inclusive language -* Being respectful of differing viewpoints and experiences -* Gracefully accepting constructive criticism -* Focusing on what is best for the community -* Showing empathy towards other community members - -Examples of unacceptable behavior by participants include: - -* The use of sexualized language or imagery and unwelcome sexual attention or - advances -* Trolling, insulting/derogatory comments, and personal or political attacks -* Public or private harassment -* Publishing others' private information, such as a physical or electronic - address, without explicit permission -* Other conduct which could reasonably be considered inappropriate in a - professional setting - -Our Responsibilities - -Project maintainers are responsible for clarifying the standards of acceptable -behavior and are expected to take appropriate and fair corrective action in -response to any instances of unacceptable behavior. - -Project maintainers have the right and responsibility to remove, edit, or -reject comments, commits, code, wiki edits, issues, and other contributions -that are not aligned to this Code of Conduct, or to ban temporarily or -permanently any contributor for other behaviors that they deem inappropriate, -threatening, offensive, or harmful. - -Scope - -This Code of Conduct applies both within project spaces and in public spaces -when an individual is representing the project or its community. Examples of -representing a project or community include using an official project e-mail -address, posting via an official social media account, or acting as an appointed -representative at an online or offline event. Representation of a project may be -further defined and clarified by project maintainers. - -Enforcement - -Instances of abusive, harassing, or otherwise unacceptable behavior may be -reported by contacting the project team at contact@yosyshq.com and/or -claire@clairexen.net. All complaints will be reviewed and investigated and -will result in a response that is deemed necessary and appropriate to the -circumstances. The project team is obligated to maintain confidentiality with -regard to the reporter of an incident. Further details of specific enforcement -policies may be posted separately. - -Project maintainers who do not follow or enforce the Code of Conduct in good -faith may face temporary or permanent repercussions as determined by other -members of the project's leadership. - -Attribution - -This Code of Conduct is adapted from the Contributor Covenant, version 1.4, -available at http://contributor-covenant.org/version/1/4/ diff --git a/guidelines/UnitTests b/guidelines/UnitTests deleted file mode 100644 index d42a63ce587..00000000000 --- a/guidelines/UnitTests +++ /dev/null @@ -1,69 +0,0 @@ -How to add unit test -==================== - -Unit test brings some advantages, briefly, we can list some of them (reference -[1](https://en.wikipedia.org/wiki/Unit_testing)): - -* Tests reduce bugs in new features; -* Tests reduce bugs in existing features; -* Tests are good documentation; -* Tests reduce the cost of change; -* Tests allow refactoring; - -With those advantages in mind, it was required to choose a framework which fits -well with C/C++ code. Hence, it was chosen (google test) -[https://github.com/google/googletest], because it is largely used and it is -relatively easy learn. - -Install and configure google test (manually) --------------------------------------------- - -In this section, you will see a brief description of how to install google -test. However, it is strongly recommended that you take a look to the official -repository (https://github.com/google/googletest) and refers to that if you -have any problem to install it. Follow the steps below: - -* Install: cmake and pthread -* Clone google test project from: https://github.com/google/googletest and - enter in the project directory -* Inside project directory, type: - -``` -cmake -DBUILD_SHARED_LIBS=ON . -make -``` - -* After compilation, copy all "*.so" inside directory "googlemock" and - "googlemock/gtest" to "/usr/lib/" -* Done! Now you can compile your tests. - -If you have any problem, go to the official repository to find help. - -Ps.: Some distros already have googletest packed. If your distro supports it, -you can use it instead of compile. - -Create new unit test --------------------- - -If you want to add new unit tests for Yosys, just follow the steps below: - -* Go to directory "yosys/test/unit/" -* In this directory you can find something similar Yosys's directory structure. - To create your unit test file you have to follow this pattern: - fileNameToImplementUnitTest + Test.cc. E.g.: if you want to implement the - unit test for kernel/celledges.cc, you will need to create a file like this: - tests/unit/kernel/celledgesTest.cc; -* Implement your unit test - -Run unit test -------------- - -To compile and run all unit tests, just go to yosys root directory and type: -``` -make unit-test -``` - -If you want to remove all unit test files, type: -``` -make clean-unit-test -``` diff --git a/guidelines/Windows b/guidelines/Windows deleted file mode 100644 index c4548c37cc7..00000000000 --- a/guidelines/Windows +++ /dev/null @@ -1,83 +0,0 @@ -Creating the Visual Studio Template Project -=========================================== - -1. Create an empty Visual C++ Win32 Console App project - - Microsoft Visual Studio Express 2013 for Windows Desktop - Open New Project Wizard (File -> New Project..) - - Project Name: YosysVS - Solution Name: YosysVS - [X] Create directory for solution - [ ] Add to source control - - [X] Console applications - [X] Empty Project - [ ] SDL checks - -2. Open YosysVS Project Properties - - Select Configuration: All Configurations - - C/C++ -> General -> Additional Include Directories - Add: ..\yosys - - C/C++ -> Preprocessor -> Preprocessor Definitions - Add: _YOSYS_;_CRT_SECURE_NO_WARNINGS - -3. Resulting file system tree: - - YosysVS/ - YosysVS/YosysVS - YosysVS/YosysVS/YosysVS.vcxproj - YosysVS/YosysVS/YosysVS.vcxproj.filters - YosysVS/YosysVS.sdf - YosysVS/YosysVS.sln - YosysVS/YosysVS.v12.suo - -4. Zip YosysVS as YosysVS-Tpl-v1.zip - -Compiling with Visual Studio -============================ - -Visual Studio builds are not directly supported by build scripts, but they are still possible. - -1. Easy way - - - Go to https://github.com/YosysHQ/yosys/actions/workflows/vs.yml?query=branch%3Amain - - Click on the most recent completed run - - In Artifacts region find vcxsrc and click on it to download - - Unpack downloaded ZIP file - - Open YosysVS.sln with Visual Studio - -2. Using WSL or MSYS2 - - - Make sure to have make, python3 and git available - - Git clone yosys repository - - Execute ```make vcxsrc YOSYS_VER=latest``` - - File yosys-win32-vcxsrc-latest.zip will be created - - Transfer that file to location visible by Windows application - - Unpack ZIP - - Open YosysVS.sln with Visual Studio - -Cross-Building for Windows with MXE -=================================== - -Check http://mxe.cc/#requirements and install all missing requirements. - -As root (or other user with write access to /usr/local/src): - - cd /usr/local/src - git clone https://github.com/mxe/mxe.git - cd mxe - - make -j$(nproc) MXE_PLUGIN_DIRS="plugins/tcl.tk" \ - MXE_TARGETS="i686-w64-mingw32.static" \ - gcc tcl readline - -Then as regular user in some directory where you build stuff: - - git clone https://github.com/YosysHQ/yosys.git yosys-win32 - cd yosys-win32 - make config-mxe - make -j$(nproc) mxebin diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 180982a7cba..604bdb27f53 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -2147,6 +2147,21 @@ namespace { check_expected(); return; } + /* + * Checklist for adding internal cell types + * ======================================== + * Things to do right away: + * - Add to kernel/celltypes.h (incl. eval() handling for non-mem cells) + * - Add to InternalCellChecker::check() in kernel/rtlil.cc + * - Add to techlibs/common/simlib.v + * - Add to techlibs/common/techmap.v + * + * Things to do after finalizing the cell interface: + * - Add support to kernel/satgen.h for the new cell type + * - Add to docs/source/CHAPTER_CellLib.rst (or just add a fixme to the bottom) + * - Maybe add support to the Verilog backend for dumping such cells as expression + * + */ error(__LINE__); } }; From 55da97c9bab2d5239bf655f3635fec7a67064b2c Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Tue, 12 Nov 2024 17:41:17 +1300 Subject: [PATCH 3/8] Docs: Formatting recent md -> rst converts --- .../extending_yosys/contributing.rst | 26 +- .../extending_yosys/test_suites.rst | 53 ++-- docs/source/yosys_internals/verilog.rst | 272 +++++++++--------- 3 files changed, 181 insertions(+), 170 deletions(-) diff --git a/docs/source/yosys_internals/extending_yosys/contributing.rst b/docs/source/yosys_internals/extending_yosys/contributing.rst index 364067f8efc..e06de61b165 100644 --- a/docs/source/yosys_internals/extending_yosys/contributing.rst +++ b/docs/source/yosys_internals/extending_yosys/contributing.rst @@ -9,19 +9,19 @@ Formatting of code - Yosys code is using tabs for indentation. Tabs are 8 characters. -- A continuation of a statement in the following line is indented by - two additional tabs. +- A continuation of a statement in the following line is indented by two + additional tabs. -- Lines are as long as you want them to be. A good rule of thumb is - to break lines at about column 150. +- Lines are as long as you want them to be. A good rule of thumb is to break + lines at about column 150. -- Opening braces can be put on the same or next line as the statement - opening the block (if, switch, for, while, do). Put the opening brace - on its own line for larger blocks, especially blocks that contains - blank lines. +- Opening braces can be put on the same or next line as the statement opening + the block (if, switch, for, while, do). Put the opening brace on its own line + for larger blocks, especially blocks that contains blank lines. -- Otherwise stick to the Linux Kernel Coding Style: - https://www.kernel.org/doc/Documentation/process/coding-style.rst +- Otherwise stick to the `Linux Kernel Coding Style`_. + +.. _Linux Kernel Coding Style: https://www.kernel.org/doc/Documentation/process/coding-style.rst C++ Language @@ -29,8 +29,8 @@ C++ Language Yosys is written in C++17. -In general Yosys uses "int" instead of "size_t". To avoid compiler -warnings for implicit type casts, always use "GetSize(foobar)" instead -of "foobar.size()". (GetSize() is defined in kernel/yosys.h) +In general Yosys uses ``int`` instead of ``size_t``. To avoid compiler warnings +for implicit type casts, always use ``GetSize(foobar)`` instead of +``foobar.size()``. (``GetSize()`` is defined in :file:`kernel/yosys.h`) Use range-based for loops whenever applicable. diff --git a/docs/source/yosys_internals/extending_yosys/test_suites.rst b/docs/source/yosys_internals/extending_yosys/test_suites.rst index 8a9c4711ef8..264b97ce1db 100644 --- a/docs/source/yosys_internals/extending_yosys/test_suites.rst +++ b/docs/source/yosys_internals/extending_yosys/test_suites.rst @@ -40,30 +40,31 @@ page`_. * Tests allow refactoring; With those advantages in mind, it was required to choose a framework which fits - well with C/C++ code. Hence, it was chosen (google test) - [https://github.com/google/googletest], because it is largely used and it is - relatively easy learn. + well with C/C++ code. Hence, `google test`_ was chosen, because it is widely + used and it is relatively easy learn. + + .. _google test: https://github.com/google/googletest Install and configure google test (manually) ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - In this section, you will see a brief description of how to install google - test. However, it is strongly recommended that you take a look to the official - repository (https://github.com/google/googletest) and refers to that if you - have any problem to install it. Follow the steps below: + In this section, you will see a brief description of how to install google test. + However, it is strongly recommended that you take a look to the official + repository (https://github.com/google/googletest) and refers to that if you have + any problem to install it. Follow the steps below: * Install: cmake and pthread - * Clone google test project from: https://github.com/google/googletest and - enter in the project directory + * Clone google test project from: https://github.com/google/googletest and enter + in the project directory * Inside project directory, type: - ``` - cmake -DBUILD_SHARED_LIBS=ON . - make - ``` + .. code-block:: console + + cmake -DBUILD_SHARED_LIBS=ON . + make - * After compilation, copy all "*.so" inside directory "googlemock" and - "googlemock/gtest" to "/usr/lib/" + * After compilation, copy all ``*.so`` inside directory ``googlemock`` and + ``googlemock/gtest`` to ``/usr/lib/`` * Done! Now you can compile your tests. If you have any problem, go to the official repository to find help. @@ -76,23 +77,25 @@ page`_. If you want to add new unit tests for Yosys, just follow the steps below: - * Go to directory "yosys/test/unit/" + * Go to directory :file:`test/unit/` * In this directory you can find something similar Yosys's directory structure. To create your unit test file you have to follow this pattern: - fileNameToImplementUnitTest + Test.cc. E.g.: if you want to implement the - unit test for kernel/celledges.cc, you will need to create a file like this: - tests/unit/kernel/celledgesTest.cc; + fileNameToImplementUnitTest + Test.cc. E.g.: if you want to implement the unit + test for ``kernel/celledges.cc``, you will need to create a file like this: + ``tests/unit/kernel/celledgesTest.cc``; * Implement your unit test Run unit tests ~~~~~~~~~~~~~~ To compile and run all unit tests, just go to yosys root directory and type: - ``` - make unit-test - ``` + + .. code-block:: console + + make unit-test If you want to remove all unit test files, type: - ``` - make clean-unit-test - ``` + + .. code-block:: console + + make clean-unit-test diff --git a/docs/source/yosys_internals/verilog.rst b/docs/source/yosys_internals/verilog.rst index 1c9031a4fa9..20fd0ac9f4b 100644 --- a/docs/source/yosys_internals/verilog.rst +++ b/docs/source/yosys_internals/verilog.rst @@ -21,64 +21,63 @@ for them: Verilog Attributes and non-standard features -------------------------------------------- -- The ``full_case`` attribute on case statements is supported - (also the non-standard ``// synopsys full_case`` directive) +- The ``full_case`` attribute on case statements is supported (also the + non-standard ``// synopsys full_case`` directive) -- The ``parallel_case`` attribute on case statements is supported - (also the non-standard ``// synopsys parallel_case`` directive) +- The ``parallel_case`` attribute on case statements is supported (also the + non-standard ``// synopsys parallel_case`` directive) -- The ``// synopsys translate_off`` and ``// synopsys translate_on`` - directives are also supported (but the use of ``` `ifdef .. `endif ``` - is strongly recommended instead). +- The ``// synopsys translate_off`` and ``// synopsys translate_on`` directives + are also supported (but the use of ``` `ifdef .. `endif ``` is strongly + recommended instead). -- The ``nomem2reg`` attribute on modules or arrays prohibits the - automatic early conversion of arrays to separate registers. This - is potentially dangerous. Usually the front-end has good reasons - for converting an array to a list of registers. Prohibiting this - step will likely result in incorrect synthesis results. +- The ``nomem2reg`` attribute on modules or arrays prohibits the automatic early + conversion of arrays to separate registers. This is potentially dangerous. + Usually the front-end has good reasons for converting an array to a list of + registers. Prohibiting this step will likely result in incorrect synthesis + results. -- The ``mem2reg`` attribute on modules or arrays forces the early - conversion of arrays to separate registers. +- The ``mem2reg`` attribute on modules or arrays forces the early conversion of + arrays to separate registers. -- The ``nomeminit`` attribute on modules or arrays prohibits the - creation of initialized memories. This effectively puts ``mem2reg`` - on all memories that are written to in an ``initial`` block and - are not ROMs. +- The ``nomeminit`` attribute on modules or arrays prohibits the creation of + initialized memories. This effectively puts ``mem2reg`` on all memories that + are written to in an ``initial`` block and are not ROMs. -- The ``nolatches`` attribute on modules or always-blocks - prohibits the generation of logic-loops for latches. Instead - all not explicitly assigned values default to x-bits. This does - not affect clocked storage elements such as flip-flops. +- The ``nolatches`` attribute on modules or always-blocks prohibits the + generation of logic-loops for latches. Instead all not explicitly assigned + values default to x-bits. This does not affect clocked storage elements such + as flip-flops. -- The ``nosync`` attribute on registers prohibits the generation of a - storage element. The register itself will always have all bits set - to 'x' (undefined). The variable may only be used as blocking assigned - temporary variable within an always block. This is mostly used internally - by Yosys to synthesize Verilog functions and access arrays. +- The ``nosync`` attribute on registers prohibits the generation of a storage + element. The register itself will always have all bits set to 'x' (undefined). + The variable may only be used as blocking assigned temporary variable within + an always block. This is mostly used internally by Yosys to synthesize Verilog + functions and access arrays. - The ``nowrshmsk`` attribute on a register prohibits the generation of shift-and-mask type circuits for writing to bit slices of that register. -- The ``onehot`` attribute on wires mark them as one-hot state register. This - is used for example for memory port sharing and set by the fsm_map pass. +- The ``onehot`` attribute on wires mark them as one-hot state register. This is + used for example for memory port sharing and set by the fsm_map pass. -- The ``blackbox`` attribute on modules is used to mark empty stub modules - that have the same ports as the real thing but do not contain information - on the internal configuration. This modules are only used by the synthesis - passes to identify input and output ports of cells. The Verilog backend - also does not output blackbox modules on default. ``read_verilog``, unless - called with ``-noblackbox`` will automatically set the blackbox attribute - on any empty module it reads. +- The ``blackbox`` attribute on modules is used to mark empty stub modules that + have the same ports as the real thing but do not contain information on the + internal configuration. This modules are only used by the synthesis passes to + identify input and output ports of cells. The Verilog backend also does not + output blackbox modules on default. `read_verilog`, unless called with + ``-noblackbox`` will automatically set the blackbox attribute on any empty + module it reads. -- The ``noblackbox`` attribute set on an empty module prevents ``read_verilog`` +- The ``noblackbox`` attribute set on an empty module prevents `read_verilog` from automatically setting the blackbox attribute on the module. - The ``whitebox`` attribute on modules triggers the same behavior as - ``blackbox``, but is for whitebox modules, i.e. library modules that - contain a behavioral model of the cell type. + ``blackbox``, but is for whitebox modules, i.e. library modules that contain a + behavioral model of the cell type. -- The ``lib_whitebox`` attribute overwrites ``whitebox`` when ``read_verilog`` - is run in `-lib` mode. Otherwise it's automatically removed. +- The ``lib_whitebox`` attribute overwrites ``whitebox`` when `read_verilog` is + run in ``-lib`` mode. Otherwise it's automatically removed. - The ``dynports`` attribute is used by the Verilog front-end to mark modules that have ports with a width that depends on a parameter. @@ -94,70 +93,69 @@ Verilog Attributes and non-standard features Setting the ``keep`` attribute on a module has the same effect as setting it on all instances of the module. -- The ``keep_hierarchy`` attribute on cells and modules keeps the ``flatten`` +- The ``keep_hierarchy`` attribute on cells and modules keeps the `flatten` command from flattening the indicated cells and modules. - The ``init`` attribute on wires is set by the frontend when a register is initialized "FPGA-style" with ``reg foo = val``. It can be used during synthesis to add the necessary reset logic. -- The ``top`` attribute on a module marks this module as the top of the - design hierarchy. The ``hierarchy`` command sets this attribute when called - with ``-top``. Other commands, such as ``flatten`` and various backends - use this attribute to determine the top module. +- The ``top`` attribute on a module marks this module as the top of the design + hierarchy. The `hierarchy` command sets this attribute when called with + ``-top``. Other commands, such as `flatten` and various backends use this + attribute to determine the top module. - The ``src`` attribute is set on cells and wires created by to the string ``:`` by the HDL front-end and is then carried - through the synthesis. When entities are combined, a new |-separated - string is created that contains all the string from the original entities. + through the synthesis. When entities are combined, a new \|-separated string + is created that contains all the strings from the original entities. -- The ``defaultvalue`` attribute is used to store default values for - module inputs. The attribute is attached to the input wire by the HDL - front-end when the input is declared with a default value. +- The ``defaultvalue`` attribute is used to store default values for module + inputs. The attribute is attached to the input wire by the HDL front-end when + the input is declared with a default value. -- The ``parameter`` and ``localparam`` attributes are used to mark wires - that represent module parameters or localparams (when the HDL front-end - is run in ``-pwires`` mode). +- The ``parameter`` and ``localparam`` attributes are used to mark wires that + represent module parameters or localparams (when the HDL front-end is run in + ``-pwires`` mode). - Wires marked with the ``hierconn`` attribute are connected to wires with the same name (format ``cell_name.identifier``) when they are imported from - sub-modules by ``flatten``. + sub-modules by `flatten`. - The ``clkbuf_driver`` attribute can be set on an output port of a blackbox - module to mark it as a clock buffer output, and thus prevent ``clkbufmap`` - from inserting another clock buffer on a net driven by such output. + module to mark it as a clock buffer output, and thus prevent `clkbufmap` from + inserting another clock buffer on a net driven by such output. - The ``clkbuf_sink`` attribute can be set on an input port of a module to - request clock buffer insertion by the ``clkbufmap`` pass. + request clock buffer insertion by the `clkbufmap` pass. -- The ``clkbuf_inv`` attribute can be set on an output port of a module - with the value set to the name of an input port of that module. When - the ``clkbufmap`` would otherwise insert a clock buffer on this output, - it will instead try inserting the clock buffer on the input port (this - is used to implement clock inverter cells that clock buffer insertion - will "see through"). +- The ``clkbuf_inv`` attribute can be set on an output port of a module with the + value set to the name of an input port of that module. When the `clkbufmap` + would otherwise insert a clock buffer on this output, it will instead try + inserting the clock buffer on the input port (this is used to implement clock + inverter cells that clock buffer insertion will "see through"). - The ``clkbuf_inhibit`` is the default attribute to set on a wire to prevent - automatic clock buffer insertion by ``clkbufmap``. This behaviour can be - overridden by providing a custom selection to ``clkbufmap``. + automatic clock buffer insertion by `clkbufmap`. This behaviour can be + overridden by providing a custom selection to `clkbufmap`. -- The ``invertible_pin`` attribute can be set on a port to mark it as - invertible via a cell parameter. The name of the inversion parameter - is specified as the value of this attribute. The value of the inversion - parameter must be of the same width as the port, with 1 indicating - an inverted bit and 0 indicating a non-inverted bit. +- The ``invertible_pin`` attribute can be set on a port to mark it as invertible + via a cell parameter. The name of the inversion parameter is specified as the + value of this attribute. The value of the inversion parameter must be of the + same width as the port, with 1 indicating an inverted bit and 0 indicating a + non-inverted bit. -- The ``iopad_external_pin`` attribute on a blackbox module's port marks - it as the external-facing pin of an I/O pad, and prevents ``iopadmap`` - from inserting another pad cell on it. +- The ``iopad_external_pin`` attribute on a blackbox module's port marks it as + the external-facing pin of an I/O pad, and prevents `iopadmap` from inserting + another pad cell on it. -- The module attribute ``abc9_lut`` is an integer attribute indicating to - `abc9` that this module describes a LUT with an area cost of this value, and - propagation delays described using `specify` statements. +- The module attribute ``abc9_lut`` is an integer attribute indicating to `abc9` + that this module describes a LUT with an area cost of this value, and + propagation delays described using ``specify`` statements. - The module attribute ``abc9_box`` is a boolean specifying a black/white-box - definition, with propagation delays described using `specify` statements, for - use by `abc9`. + definition, with propagation delays described using ``specify`` statements, + for use by `abc9`. - The port attribute ``abc9_carry`` marks the carry-in (if an input port) and carry-out (if output port) ports of a box. This information is necessary for @@ -174,38 +172,41 @@ Verilog Attributes and non-standard features ``proc_dlatch``. - The cell attribute ``wildcard_port_conns`` represents wildcard port - connections (SystemVerilog ``.*``). These are resolved to concrete - connections to matching wires in ``hierarchy``. + connections (SystemVerilog ``.*``). These are resolved to concrete connections + to matching wires in `hierarchy`. -- In addition to the ``(* ... *)`` attribute syntax, Yosys supports - the non-standard ``{* ... *}`` attribute syntax to set default attributes - for everything that comes after the ``{* ... *}`` statement. (Reset - by adding an empty ``{* *}`` statement.) +- In addition to the ``(* ... *)`` attribute syntax, Yosys supports the + non-standard ``{* ... *}`` attribute syntax to set default attributes for + everything that comes after the ``{* ... *}`` statement. (Reset by adding an + empty ``{* *}`` statement.) -- In module parameter and port declarations, and cell port and parameter - lists, a trailing comma is ignored. This simplifies writing Verilog code - generators a bit in some cases. +- In module parameter and port declarations, and cell port and parameter lists, + a trailing comma is ignored. This simplifies writing Verilog code generators a + bit in some cases. - Modules can be declared with ``module mod_name(...);`` (with three dots - instead of a list of module ports). With this syntax it is sufficient - to simply declare a module port as 'input' or 'output' in the module - body. + instead of a list of module ports). With this syntax it is sufficient to + simply declare a module port as 'input' or 'output' in the module body. -- When defining a macro with `define, all text between triple double quotes +- When defining a macro with ``\`define``, all text between triple double quotes is interpreted as macro body, even if it contains unescaped newlines. The triple double quotes are removed from the macro body. For example: +.. code-block:: verilog + `define MY_MACRO(a, b) """ assign a = 23; assign b = 42; """ - The attribute ``via_celltype`` can be used to implement a Verilog task or - function by instantiating the specified cell type. The value is the name - of the cell type to use. For functions the name of the output port can - be specified by appending it to the cell type separated by a whitespace. - The body of the task or function is unused in this case and can be used - to specify a behavioral model of the cell type for simulation. For example: + function by instantiating the specified cell type. The value is the name of + the cell type to use. For functions the name of the output port can be + specified by appending it to the cell type separated by a whitespace. The body + of the task or function is unused in this case and can be used to specify a + behavioral model of the cell type for simulation. For example: + +.. code-block:: verilog module my_add3(A, B, C, Y); parameter WIDTH = 8; @@ -230,24 +231,28 @@ Verilog Attributes and non-standard features - The ``wiretype`` attribute is added by the verilog parser for wires of a typedef'd type to indicate the type identifier. -- Various ``enum_value_{value}`` attributes are added to wires of an enumerated type - to give a map of possible enum items to their values. +- Various ``enum_value_{value}`` attributes are added to wires of an enumerated + type to give a map of possible enum items to their values. + +- The ``enum_base_type`` attribute is added to enum items to indicate which enum + they belong to (enums -- anonymous and otherwise -- are automatically named + with an auto-incrementing counter). Note that enums are currently not strongly + typed. -- The ``enum_base_type`` attribute is added to enum items to indicate which - enum they belong to (enums -- anonymous and otherwise -- are - automatically named with an auto-incrementing counter). Note that enums - are currently not strongly typed. +- A limited subset of DPI-C functions is supported. The plugin mechanism (see + ``help plugin``) can be used to load .so files with implementations of DPI-C + routines. As a non-standard extension it is possible to specify a plugin alias + using the ``:`` syntax. For example: -- A limited subset of DPI-C functions is supported. The plugin mechanism - (see ``help plugin``) can be used to load .so files with implementations - of DPI-C routines. As a non-standard extension it is possible to specify - a plugin alias using the ``:`` syntax. For example: +.. code-block:: verilog module dpitest; import "DPI-C" function foo:round = real my_round (real); parameter real r = my_round(12.345); endmodule +.. code-block:: + $ yosys -p 'plugin -a foo -i /lib/libm.so; read_verilog dpitest.v' - Sized constants (the syntax ``'s?[bodh]``) support constant @@ -256,17 +261,17 @@ Verilog Attributes and non-standard features - The system tasks ``$finish``, ``$stop`` and ``$display`` are supported in initial blocks in an unconditional context (only if/case statements on - expressions over parameters and constant values are allowed). The intended - use for this is synthesis-time DRC. + expressions over parameters and constant values are allowed). The intended use + for this is synthesis-time DRC. - There is limited support for converting ``specify`` .. ``endspecify`` statements to special ``$specify2``, ``$specify3``, and ``$specrule`` cells, - for use in blackboxes and whiteboxes. Use ``read_verilog -specify`` to - enable this functionality. (By default these blocks are ignored.) + for use in blackboxes and whiteboxes. Use ``read_verilog -specify`` to enable + this functionality. (By default these blocks are ignored.) - The ``reprocess_after`` internal attribute is used by the Verilog frontend to mark cells with bindings which might depend on the specified instantiated - module. Modules with such cells will be reprocessed during the ``hierarchy`` + module. Modules with such cells will be reprocessed during the `hierarchy` pass once the referenced module definition(s) become available. - The ``smtlib2_module`` attribute can be set on a blackbox module to specify a @@ -274,6 +279,8 @@ Verilog Attributes and non-standard features ``smtlib2_comb_expr`` attribute can be used on output ports to define their value using an SMT-LIB 2 expression. For example: +.. code-block:: verilog + (* blackbox *) (* smtlib2_module *) module submod(a, b); @@ -286,48 +293,49 @@ Non-standard or SystemVerilog features for formal verification -------------------------------------------------------------- - Support for ``assert``, ``assume``, ``restrict``, and ``cover`` is enabled - when ``read_verilog`` is called with ``-formal``. + when `read_verilog` is called with ``-formal``. -- The system task ``$initstate`` evaluates to 1 in the initial state and - to 0 otherwise. +- The system task ``$initstate`` evaluates to 1 in the initial state and to 0 + otherwise. - The system function ``$anyconst`` evaluates to any constant value. This is - equivalent to declaring a reg as ``rand const``, but also works outside - of checkers. (Yosys also supports ``rand const`` outside checkers.) + equivalent to declaring a reg as ``rand const``, but also works outside of + checkers. (Yosys also supports ``rand const`` outside checkers.) - The system function ``$anyseq`` evaluates to any value, possibly a different - value in each cycle. This is equivalent to declaring a reg as ``rand``, - but also works outside of checkers. (Yosys also supports ``rand`` - variables outside checkers.) + value in each cycle. This is equivalent to declaring a reg as ``rand``, but + also works outside of checkers. (Yosys also supports ``rand`` variables + outside checkers.) - The system functions ``$allconst`` and ``$allseq`` can be used to construct - formal exist-forall problems. Assumptions only hold if the trace satisfies - the assumption for all ``$allconst/$allseq`` values. For assertions and cover + formal exist-forall problems. Assumptions only hold if the trace satisfies the + assumption for all ``$allconst/$allseq`` values. For assertions and cover statements it is sufficient if just one ``$allconst/$allseq`` value triggers the property (similar to ``$anyconst/$anyseq``). -- Wires/registers declared using the ``anyconst/anyseq/allconst/allseq`` attribute - (for example ``(* anyconst *) reg [7:0] foobar;``) will behave as if driven - by a ``$anyconst/$anyseq/$allconst/$allseq`` function. +- Wires/registers declared using the ``anyconst/anyseq/allconst/allseq`` + attribute (for example ``(* anyconst *) reg [7:0] foobar;``) will behave as if + driven by a ``$anyconst/$anyseq/$allconst/$allseq`` function. - The SystemVerilog tasks ``$past``, ``$stable``, ``$rose`` and ``$fell`` are supported in any clocked block. - The syntax ``@($global_clock)`` can be used to create FFs that have no explicit clock input (``$ff`` cells). The same can be achieved by using - ``@(posedge )`` or ``@(negedge )`` when ```` - is marked with the ``(* gclk *)`` Verilog attribute. + ``@(posedge )`` or ``@(negedge )`` when ```` is + marked with the ``(* gclk *)`` Verilog attribute. Supported features from SystemVerilog ------------------------------------- -When ``read_verilog`` is called with ``-sv``, it accepts some language features +When `read_verilog` is called with ``-sv``, it accepts some language features from SystemVerilog: - The ``assert`` statement from SystemVerilog is supported in its most basic form. In module context: ``assert property ();`` and within an - always block: ``assert();``. It is transformed to an ``$assert`` cell. + always block: ``assert();``. It is transformed to an ``$assert`` + cell. - The ``assume``, ``restrict``, and ``cover`` statements from SystemVerilog are also supported. The same limitations as with the ``assert`` statement apply. @@ -340,9 +348,9 @@ from SystemVerilog: - Checkers without a port list that do not need to be instantiated (but instead behave like a named block) are supported. -- SystemVerilog packages are supported. Once a SystemVerilog file is read - into a design with ``read_verilog``, all its packages are available to - SystemVerilog files being read into the same design afterwards. +- SystemVerilog packages are supported. Once a SystemVerilog file is read into a + design with `read_verilog`, all its packages are available to SystemVerilog + files being read into the same design afterwards. - typedefs are supported (including inside packages) - type casts are currently not supported From 436b703f844e0db5c80233f1c853339f7a4f04ce Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Tue, 12 Nov 2024 17:49:30 +1300 Subject: [PATCH 4/8] Add updated CODE_OF_CONDUCT Based on version 2.0 of the Contributor Covenant. --- CODE_OF_CONDUCT | 128 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 128 insertions(+) create mode 100644 CODE_OF_CONDUCT diff --git a/CODE_OF_CONDUCT b/CODE_OF_CONDUCT new file mode 100644 index 00000000000..ad29106307f --- /dev/null +++ b/CODE_OF_CONDUCT @@ -0,0 +1,128 @@ +# Contributor Covenant Code of Conduct + +## Our Pledge + +We as members, contributors, and leaders pledge to make participation in our +community a harassment-free experience for everyone, regardless of age, body +size, visible or invisible disability, ethnicity, sex characteristics, gender +identity and expression, level of experience, education, socio-economic status, +nationality, personal appearance, race, religion, or sexual identity +and orientation. + +We pledge to act and interact in ways that contribute to an open, welcoming, +diverse, inclusive, and healthy community. + +## Our Standards + +Examples of behavior that contributes to a positive environment for our +community include: + +* Demonstrating empathy and kindness toward other people +* Being respectful of differing opinions, viewpoints, and experiences +* Giving and gracefully accepting constructive feedback +* Accepting responsibility and apologizing to those affected by our mistakes, + and learning from the experience +* Focusing on what is best not just for us as individuals, but for the + overall community + +Examples of unacceptable behavior include: + +* The use of sexualized language or imagery, and sexual attention or + advances of any kind +* Trolling, insulting or derogatory comments, and personal or political attacks +* Public or private harassment +* Publishing others' private information, such as a physical or email + address, without their explicit permission +* Other conduct which could reasonably be considered inappropriate in a + professional setting + +## Enforcement Responsibilities + +Community leaders are responsible for clarifying and enforcing our standards of +acceptable behavior and will take appropriate and fair corrective action in +response to any behavior that they deem inappropriate, threatening, offensive, +or harmful. + +Community leaders have the right and responsibility to remove, edit, or reject +comments, commits, code, wiki edits, issues, and other contributions that are +not aligned to this Code of Conduct, and will communicate reasons for moderation +decisions when appropriate. + +## Scope + +This Code of Conduct applies within all community spaces, and also applies when +an individual is officially representing the community in public spaces. +Examples of representing our community include using an official e-mail address, +posting via an official social media account, or acting as an appointed +representative at an online or offline event. + +## Enforcement + +Instances of abusive, harassing, or otherwise unacceptable behavior may be +reported by contacting the project team at contact@yosyshq.com and/or +claire@clairexen.net. +All complaints will be reviewed and investigated promptly and fairly. + +All community leaders are obligated to respect the privacy and security of the +reporter of any incident. + +## Enforcement Guidelines + +Community leaders will follow these Community Impact Guidelines in determining +the consequences for any action they deem in violation of this Code of Conduct: + +### 1. Correction + +**Community Impact**: Use of inappropriate language or other behavior deemed +unprofessional or unwelcome in the community. + +**Consequence**: A private, written warning from community leaders, providing +clarity around the nature of the violation and an explanation of why the +behavior was inappropriate. A public apology may be requested. + +### 2. Warning + +**Community Impact**: A violation through a single incident or series +of actions. + +**Consequence**: A warning with consequences for continued behavior. No +interaction with the people involved, including unsolicited interaction with +those enforcing the Code of Conduct, for a specified period of time. This +includes avoiding interactions in community spaces as well as external channels +like social media. Violating these terms may lead to a temporary or +permanent ban. + +### 3. Temporary Ban + +**Community Impact**: A serious violation of community standards, including +sustained inappropriate behavior. + +**Consequence**: A temporary ban from any sort of interaction or public +communication with the community for a specified period of time. No public or +private interaction with the people involved, including unsolicited interaction +with those enforcing the Code of Conduct, is allowed during this period. +Violating these terms may lead to a permanent ban. + +### 4. Permanent Ban + +**Community Impact**: Demonstrating a pattern of violation of community +standards, including sustained inappropriate behavior, harassment of an +individual, or aggression toward or disparagement of classes of individuals. + +**Consequence**: A permanent ban from any sort of public interaction within +the community. + +## Attribution + +This Code of Conduct is adapted from the [Contributor Covenant][homepage], +version 2.0, available at +https://www.contributor-covenant.org/version/2/0/code_of_conduct.html. + +Community Impact Guidelines were inspired by [Mozilla's code of conduct +enforcement ladder](https://github.com/mozilla/diversity). + +[homepage]: https://www.contributor-covenant.org + +For answers to common questions about this code of conduct, see the FAQ at +https://www.contributor-covenant.org/faq. Translations are available at +https://www.contributor-covenant.org/translations. From e95f5d9d5a66be3acf53802bcd653eec2fe310c3 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Fri, 22 Nov 2024 05:54:21 +1300 Subject: [PATCH 5/8] README: Drop the license from the top Github shows the license file automatically, and the first section mentions it is ISC. --- README.md | 19 ------------------- 1 file changed, 19 deletions(-) diff --git a/README.md b/README.md index 1defe7c9642..93b776c8908 100644 --- a/README.md +++ b/README.md @@ -1,22 +1,3 @@ -``` -yosys -- Yosys Open SYnthesis Suite - -Copyright (C) 2012 - 2024 Claire Xenia Wolf - -Permission to use, copy, modify, and/or distribute this software for any -purpose with or without fee is hereby granted, provided that the above -copyright notice and this permission notice appear in all copies. - -THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES -WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF -MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR -ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES -WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN -ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF -OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. -``` - - yosys – Yosys Open SYnthesis Suite =================================== From d55692aff8b9c588f95d2612efaddf9b99f63c99 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Fri, 22 Nov 2024 05:55:16 +1300 Subject: [PATCH 6/8] CODE_OF_CONDUCT now explicitly .md --- CODE_OF_CONDUCT => CODE_OF_CONDUCT.md | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename CODE_OF_CONDUCT => CODE_OF_CONDUCT.md (100%) diff --git a/CODE_OF_CONDUCT b/CODE_OF_CONDUCT.md similarity index 100% rename from CODE_OF_CONDUCT rename to CODE_OF_CONDUCT.md From 2a9cfdfe0f2c92dcfcc20e73eeb020aca4914cbd Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Fri, 22 Nov 2024 05:56:07 +1300 Subject: [PATCH 7/8] README: Some updating of web site section --- README.md | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/README.md b/README.md index 93b776c8908..dd0f265b837 100644 --- a/README.md +++ b/README.md @@ -24,14 +24,14 @@ Web Site and Other Resources More information and documentation can be found on the Yosys web site: - https://yosyshq.net/yosys/ -The "Documentation" page on the web site contains links to more resources, -including a manual that even describes some of the Yosys internals: -- https://yosyshq.net/yosys/documentation.html - -Users interested in formal verification might want to use the formal verification -front-end for Yosys, SymbiYosys: -- https://symbiyosys.readthedocs.io/en/latest/ -- https://github.com/YosysHQ/SymbiYosys +Documentation from this repository is automatically built and available on Read +the Docs: +- https://yosyshq.readthedocs.io/projects/yosys + +Users interested in formal verification might want to use the formal +verification front-end for Yosys, SBY: +- https://yosyshq.readthedocs.io/projects/sby/ +- https://github.com/YosysHQ/sby Installation From adb665e157e41a911a1e8c83ca0cf35f1ec6b6eb Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Thu, 28 Nov 2024 12:24:33 +1300 Subject: [PATCH 8/8] Moving primary build instructions to docs Also drop visual studio instructions. --- README.md | 142 ++++--------------- docs/source/getting_started/installation.rst | 126 ++++++++++++---- 2 files changed, 130 insertions(+), 138 deletions(-) diff --git a/README.md b/README.md index dd0f265b837..5869f086ed8 100644 --- a/README.md +++ b/README.md @@ -18,6 +18,7 @@ Third-party software distributed alongside this software is licensed under compatible licenses. Please refer to `abc` and `libs` subdirectories for their license terms. + Web Site and Other Resources ============================ @@ -49,9 +50,25 @@ For more information about the difference between Tabby CAD Suite and the OSS CA Many Linux distributions also provide Yosys binaries, some more up to date than others. Check with your package manager! + Building from Source ==================== +For more details, and instructions for other platforms, check [building from +source](https://yosyshq.readthedocs.io/projects/yosys/en/latest/getting_started/installation.html#building-from-source) +on Read the Docs. + +When cloning Yosys, some required libraries are included as git submodules. Make +sure to call e.g. + + $ git clone --recurse-submodules https://github.com/YosysHQ/yosys.git + +or + + $ git clone https://github.com/YosysHQ/yosys.git + $ cd yosys + $ git submodule update --init --recursive + You need a C++ compiler with C++17 support (up-to-date CLANG or GCC is recommended) and some standard tools such as GNU Flex, GNU Bison, and GNU Make. TCL, readline and libffi are optional (see ``ENABLE_*`` settings in Makefile). @@ -65,58 +82,22 @@ prerequisites for building yosys: graphviz xdot pkg-config python3 libboost-system-dev \ libboost-python-dev libboost-filesystem-dev zlib1g-dev -Similarily, on Mac OS X Homebrew can be used to install dependencies (from within cloned yosys repository): - - $ brew tap Homebrew/bundle && brew bundle - -or MacPorts: - - $ sudo port install bison flex readline gawk libffi \ - git graphviz pkgconfig python36 boost zlib tcl - -On FreeBSD use the following command to install all prerequisites: - - # pkg install bison flex readline gawk libffi\ - git graphviz pkgconf python3 python36 tcl-wrapper boost-libs - -On FreeBSD system use gmake instead of make. To run tests use: - % MAKE=gmake CC=cc gmake test - -For Cygwin use the following command to install all prerequisites, or select these additional packages: - - setup-x86_64.exe -q --packages=bison,flex,gcc-core,gcc-g++,git,libffi-devel,libreadline-devel,make,pkg-config,python3,tcl-devel,boost-build,zlib-devel - The environment variable `CXX` can be used to control the C++ compiler used, or -run one of the following: +run one of the following to override it: $ make config-clang $ make config-gcc -Note that these will result in `make` ignoring the `CXX` environment variable, -unless `CXX` is assigned in the call to make, e.g. - - $ make CXX=$CXX - The Makefile has many variables influencing the build process. These can be -adjusted by modifying the Makefile.conf file which is created at the -`make config-...` step (see above), or they can be set by passing an option -to the make command directly. - -For example, if you have clang, and (a compatible version of) `ld.lld` -available in PATH, it's recommended to speed up incremental builds with -lld by enabling LTO: - - $ make ENABLE_LTO=1 - -On macOS, LTO requires using clang from homebrew which isn't in PATH -rather than xcode clang. +adjusted by modifying the Makefile.conf file which is created at the `make +config-...` step (see above), or they can be set by passing an option to the +make command directly: -$ make ENABLE_LTO=1 CXX=$(brew --prefix)/opt/llvm/bin/clang++ + $ make CXX=$CXX -For other compilers and build configurations it might be -necessary to make some changes to the config section of the -Makefile. It's also an alternative way to set the make variables -mentioned above. +For other compilers and build configurations it might be necessary to make some +changes to the config section of the Makefile. It's also an alternative way to +set the make variables mentioned above. $ vi Makefile # ..or.. $ vi Makefile.conf @@ -126,10 +107,9 @@ To build Yosys simply type 'make' in this directory. $ make $ sudo make install -Note that this also downloads, builds and installs ABC (using yosys-abc -as executable name). - -Tests are located in the tests subdirectory and can be executed using the test target. Note that you need gawk as well as a recent version of iverilog (i.e. build from git). Then, execute tests via: +Tests are located in the tests subdirectory and can be executed using the test +target. Note that you need gawk as well as a recent version of iverilog (i.e. +build from git). Then, execute tests via: $ make test @@ -140,6 +120,7 @@ To use a separate (out-of-tree) build directory, provide a path to the Makefile. Out-of-tree builds require a clean source tree. + Getting Started =============== @@ -279,68 +260,3 @@ From the root of the repository, run `make docs`. This will build/rebuild yosys as necessary before generating the website documentation from the yosys help commands. To build for pdf instead of html, call `make docs DOC_TARGET=latexpdf`. - -Building for Windows -==================== - -Creating the Visual Studio Template Project -------------------------------------------- - -1. Create an empty Visual C++ Win32 Console App project - - Microsoft Visual Studio Express 2013 for Windows Desktop - Open New Project Wizard (File -> New Project..) - - Project Name: YosysVS - Solution Name: YosysVS - [X] Create directory for solution - [ ] Add to source control - - [X] Console applications - [X] Empty Project - [ ] SDL checks - -2. Open YosysVS Project Properties - - Select Configuration: All Configurations - - C/C++ -> General -> Additional Include Directories - Add: ..\yosys - - C/C++ -> Preprocessor -> Preprocessor Definitions - Add: _YOSYS_;_CRT_SECURE_NO_WARNINGS - -3. Resulting file system tree: - - YosysVS/ - YosysVS/YosysVS - YosysVS/YosysVS/YosysVS.vcxproj - YosysVS/YosysVS/YosysVS.vcxproj.filters - YosysVS/YosysVS.sdf - YosysVS/YosysVS.sln - YosysVS/YosysVS.v12.suo - -4. Zip YosysVS as YosysVS-Tpl-v1.zip - -Compiling with Visual Studio ----------------------------- - -Visual Studio builds are not directly supported by build scripts, but they are still possible. - -1. Easy way - - - Go to https://github.com/YosysHQ/yosys/actions/workflows/vs.yml?query=branch%3Amain - - Click on the most recent completed run - - In Artifacts region find vcxsrc and click on it to download - - Unpack downloaded ZIP file - - Open YosysVS.sln with Visual Studio - -2. Using WSL or MSYS2 - - - Make sure to have make, python3 and git available - - Git clone yosys repository - - Execute ```make vcxsrc YOSYS_VER=latest``` - - File yosys-win32-vcxsrc-latest.zip will be created - - Transfer that file to location visible by Windows application - - Unpack ZIP - - Open YosysVS.sln with Visual Studio diff --git a/docs/source/getting_started/installation.rst b/docs/source/getting_started/installation.rst index a53d47e9853..5c20955c532 100644 --- a/docs/source/getting_started/installation.rst +++ b/docs/source/getting_started/installation.rst @@ -62,9 +62,21 @@ The `OSS CAD Suite`_ releases `nightly builds`_ for the following architectures: Building from source ~~~~~~~~~~~~~~~~~~~~ -Refer to the `readme`_ for the most up-to-date install instructions. +.. TODO:: discuss release packages (and figure out what is/isn't included) -.. _readme: https://github.com/YosysHQ/yosys#building-from-source +The Yosys source files can be obtained from the `YosysHQ/Yosys git repository`_. +`ABC`_ and some of the other libraries used are included as git submodules. To +clone these submodules at the same time, use e.g.: + +.. code:: console + + git clone --recurse-submodules https://github.com/YosysHQ/yosys.git # ..or.. + git clone https://github.com/YosysHQ/yosys.git + cd yosys + git submodule update --init --recursive + +.. _YosysHQ/Yosys git repository: https://github.com/yosyshq/yosys/ +.. _ABC: https://github.com/berkeley-abc/abc Supported platforms ^^^^^^^^^^^^^^^^^^^ @@ -90,52 +102,119 @@ libffi, Tcl and zlib; are optional but enabled by default (see :makevar:`ENABLE_*` settings in Makefile). Graphviz and Xdot are used by the `show` command to display schematics. +.. TODO:: check there aren't any extra prereqs that are already installed on git images + Installing all prerequisites for Ubuntu 20.04: .. code:: console - sudo sudo apt-get install build-essential clang lld bison flex \ - libreadline-dev gawk tcl-dev libffi-dev git make \ - graphviz xdot pkg-config python3 libboost-system-dev \ + sudo apt-get install gperf build-essential bison flex \ + libreadline-dev gawk tcl-dev libffi-dev git graphviz \ + xdot pkg-config python3 libboost-system-dev \ libboost-python-dev libboost-filesystem-dev zlib1g-dev -Installing all prerequisites for macOS 11 (with Homebrew): +Installing all prerequisites for macOS 13 (with Homebrew): .. code:: console - brew install bison flex gawk libffi git graphviz \ - pkg-config python3 tcl-tk xdot bash boost-python3 + brew tap Homebrew/bundle && brew bundle -Running the build system -^^^^^^^^^^^^^^^^^^^^^^^^ +.. TODO:: check these are still up to date -From the root ``yosys`` directory, call the following commands: +or MacPorts: .. code:: console - - make - sudo make install -This will build and then install Yosys, making it available on the command line -as ``yosys``. Note that this also downloads, builds, and installs `ABC`_ (using -:program:`yosys-abc` as the executable name). + sudo port install bison flex readline gawk libffi graphviz \ + pkgconfig python36 boost zlib tcl -.. _ABC: https://github.com/berkeley-abc/abc +.. todo:: Is there a console alternative that has the # prefix instead of $? -The default compiler is ``clang``, to change between ``clang`` and ``gcc``, use -one of the following: +On FreeBSD use the following command to install all prerequisites: .. code:: console - make config-clang + pkg install bison flex readline gawk libffi graphviz \ + pkgconf python3 python36 tcl-wrapper boost-libs + +.. note:: On FreeBSD system use gmake instead of make. To run tests use: + ``MAKE=gmake CC=cc gmake test`` + +For Cygwin use the following command to install all prerequisites, or select these additional packages: + +.. code:: + + setup-x86_64.exe -q --packages=bison,flex,gcc-core,gcc-g++,git,libffi-devel,libreadline-devel,make,pkg-config,python3,tcl-devel,boost-build,zlib-devel + +Build configuration +^^^^^^^^^^^^^^^^^^^ + +The Yosys build is based solely on Makefiles, and uses a number of variables +which influence the build process. The recommended method for configuring +builds is with a ``Makefile.conf`` file in the root ``yosys`` directory. The +following commands will clean the directory and provide an initial configuration +file: + +.. code:: console + + make config-clang # ..or.. make config-gcc -To use a compiler different than the default, use: +Check the root Makefile to see what other configuration targets are available. +Other variables can then be added to the ``Makefile.conf`` as needed, for +example: + +.. code:: console + + echo "ENABLE_ZLIB := 0" >> Makefile.conf + +Using one of these targets will set the ``CONFIG`` variable to something other +than ``none``, and will override the environment variable for ``CXX``. To use a +different compiler than the default when building, use: .. code:: console + make CXX=$CXX # ..or.. make CXX="g++-11" +.. note:: + + Setting the compiler in this way will prevent some other options such as + ``ENABLE_CCACHE`` from working as expected. + +If you have clang, and (a compatible version of) ``ld.lld`` available in PATH, +it's recommended to speed up incremental builds with lld by enabling LTO with +``ENABLE_LTO=1``. On macOS, LTO requires using clang from homebrew rather than +clang from xcode. For example: + +.. code:: console + + make ENABLE_LTO=1 CXX=$(brew --prefix)/opt/llvm/bin/clang++ + +By default, building (and installing) yosys will build (and install) `ABC`_, +using :program:`yosys-abc` as the executable name. To use an existing ABC +executable instead, set the ``ABCEXTERNAL`` make variable to point to the +desired executable. + +Running the build system +^^^^^^^^^^^^^^^^^^^^^^^^ + +From the root ``yosys`` directory, call the following commands: + +.. code:: console + + make + sudo make install + +To use a separate (out-of-tree) build directory, provide a path to the Makefile. + +.. code:: console + + mkdir build; cd build + make -f ../Makefile + +Out-of-tree builds require a clean source tree. + .. seealso:: Refer to :doc:`/yosys_internals/extending_yosys/test_suites` for details on @@ -202,9 +281,6 @@ commands. Good starting points for reading example source code to learn how to write passes are :file:`passes/opt/opt_dff.cc` and :file:`passes/opt/opt_merge.cc`. -See the top-level README file for a quick Getting Started guide and build -instructions. The Yosys build is based solely on Makefiles. - Users of the Qt Creator IDE can generate a QT Creator project file using make qtcreator. Users of the Eclipse IDE can use the "Makefile Project with Existing Code" project type in the Eclipse "New Project" dialog (only available after the