diff --git a/src/finn/custom_op/fpgadataflow/hls/channelwise_op_hls.py b/src/finn/custom_op/fpgadataflow/hls/channelwise_op_hls.py index 14efa113d..adb71c0cc 100644 --- a/src/finn/custom_op/fpgadataflow/hls/channelwise_op_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/channelwise_op_hls.py @@ -285,7 +285,12 @@ def execute_node(self, context, graph): inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits) super().reset_rtlsim(sim) super().toggle_clk(sim) - output = self.rtlsim(sim, inp) + io_dict = { + "inputs": {"in0": inp}, + "outputs": {"out": []}, + } + self.rtlsim_multi_io(sim, io_dict) + output = io_dict["outputs"]["out"] odt = self.get_output_datatype() target_bits = odt.bitwidth() packed_bits = self.get_outstream_width() diff --git a/src/finn/custom_op/fpgadataflow/hls/convolutioninputgenerator_hls.py b/src/finn/custom_op/fpgadataflow/hls/convolutioninputgenerator_hls.py index 4a5c02ee0..eeb7dd880 100644 --- a/src/finn/custom_op/fpgadataflow/hls/convolutioninputgenerator_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/convolutioninputgenerator_hls.py @@ -388,7 +388,12 @@ def execute_node(self, context, graph): ) super().reset_rtlsim(sim) super().toggle_clk(sim) - rtlsim_output = self.rtlsim(sim, rtlsim_inp) + io_dict = { + "inputs": {"in0": rtlsim_inp}, + "outputs": {"out": []}, + } + self.rtlsim_multi_io(sim, io_dict) + rtlsim_output = io_dict["outputs"]["out"] odt = export_idt target_bits = odt.bitwidth() packed_bits = self.get_outstream_width() diff --git a/src/finn/custom_op/fpgadataflow/hls/downsampler_hls.py b/src/finn/custom_op/fpgadataflow/hls/downsampler_hls.py index 56f472b9c..76364befd 100644 --- a/src/finn/custom_op/fpgadataflow/hls/downsampler_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/downsampler_hls.py @@ -139,7 +139,12 @@ def execute_node(self, context, graph): ) super().reset_rtlsim(sim) super().toggle_clk(sim) - rtlsim_output = self.rtlsim(sim, rtlsim_inp) + io_dict = { + "inputs": {"in0": rtlsim_inp}, + "outputs": {"out": []}, + } + self.rtlsim_multi_io(sim, io_dict) + rtlsim_output = io_dict["outputs"]["out"] odt = export_idt target_bits = odt.bitwidth() packed_bits = self.get_outstream_width() diff --git a/src/finn/custom_op/fpgadataflow/hls/fmpadding_hls.py b/src/finn/custom_op/fpgadataflow/hls/fmpadding_hls.py index d57699af0..a6eb9cab0 100644 --- a/src/finn/custom_op/fpgadataflow/hls/fmpadding_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/fmpadding_hls.py @@ -186,7 +186,12 @@ def execute_node(self, context, graph): ) super().reset_rtlsim(sim) super().toggle_clk(sim) - rtlsim_output = self.rtlsim(sim, rtlsim_inp) + io_dict = { + "inputs": {"in0": rtlsim_inp}, + "outputs": {"out": []}, + } + self.rtlsim_multi_io(sim, io_dict) + rtlsim_output = io_dict["outputs"]["out"] odt = export_idt target_bits = odt.bitwidth() packed_bits = self.get_outstream_width() diff --git a/src/finn/custom_op/fpgadataflow/hls/fmpadding_pixel_hls.py b/src/finn/custom_op/fpgadataflow/hls/fmpadding_pixel_hls.py index b7ba301fb..7e6bb80e3 100644 --- a/src/finn/custom_op/fpgadataflow/hls/fmpadding_pixel_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/fmpadding_pixel_hls.py @@ -141,7 +141,12 @@ def execute_node(self, context, graph): ) super().reset_rtlsim(sim) super().toggle_clk(sim) - rtlsim_output = self.rtlsim(sim, rtlsim_inp) + io_dict = { + "inputs": {"in0": rtlsim_inp}, + "outputs": {"out": []}, + } + self.rtlsim_multi_io(sim, io_dict) + rtlsim_output = io_dict["outputs"]["out"] odt = export_idt target_bits = odt.bitwidth() packed_bits = self.get_outstream_width() diff --git a/src/finn/custom_op/fpgadataflow/hls/globalaccpool_hls.py b/src/finn/custom_op/fpgadataflow/hls/globalaccpool_hls.py index 9b2a7b25b..e19585066 100644 --- a/src/finn/custom_op/fpgadataflow/hls/globalaccpool_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/globalaccpool_hls.py @@ -119,7 +119,12 @@ def execute_node(self, context, graph): ) super().reset_rtlsim(sim) super().toggle_clk(sim) - rtlsim_output = self.rtlsim(sim, rtlsim_inp) + io_dict = { + "inputs": {"in0": rtlsim_inp}, + "outputs": {"out": []}, + } + self.rtlsim_multi_io(sim, io_dict) + rtlsim_output = io_dict["outputs"]["out"] odt = self.get_output_datatype() target_bits = odt.bitwidth() packed_bits = self.get_outstream_width() diff --git a/src/finn/custom_op/fpgadataflow/hls/labelselect_hls.py b/src/finn/custom_op/fpgadataflow/hls/labelselect_hls.py index 1e2c0d034..a79856f7e 100644 --- a/src/finn/custom_op/fpgadataflow/hls/labelselect_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/labelselect_hls.py @@ -121,7 +121,12 @@ def execute_node(self, context, graph): ) super().reset_rtlsim(sim) super().toggle_clk(sim) - rtlsim_output = self.rtlsim(sim, rtlsim_inp) + io_dict = { + "inputs": {"in0": rtlsim_inp}, + "outputs": {"out": []}, + } + self.rtlsim_multi_io(sim, io_dict) + rtlsim_output = io_dict["outputs"]["out"] odt = self.get_output_datatype() target_bits = odt.bitwidth() packed_bits = self.get_outstream_width() diff --git a/src/finn/custom_op/fpgadataflow/hls/lookup_hls.py b/src/finn/custom_op/fpgadataflow/hls/lookup_hls.py index ba44deb89..fbe12e51e 100644 --- a/src/finn/custom_op/fpgadataflow/hls/lookup_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/lookup_hls.py @@ -298,7 +298,12 @@ def execute_node(self, context, graph): ) super().reset_rtlsim(sim) super().toggle_clk(sim) - rtlsim_output = self.rtlsim(sim, rtlsim_inp) + io_dict = { + "inputs": {"in0": rtlsim_inp}, + "outputs": {"out": []}, + } + self.rtlsim_multi_io(sim, io_dict) + rtlsim_output = io_dict["outputs"]["out"] target_bits = odt.bitwidth() packed_bits = self.get_outstream_width() out_npy_path = "{}/output.npy".format(code_gen_dir) diff --git a/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py b/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py index cae1c30eb..772057b7d 100644 --- a/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/matrixvectoractivation_hls.py @@ -556,10 +556,13 @@ def execute_node(self, context, graph): "inputs": {"in0": inp, "weights": wei * num_w_reps}, "outputs": {"out": []}, } - self.rtlsim_multi_io(sim, io_dict) - output = io_dict["outputs"]["out"] else: - output = self.rtlsim(sim, inp) + io_dict = { + "inputs": {"in0": inp}, + "outputs": {"out": []}, + } + self.rtlsim_multi_io(sim, io_dict) + output = io_dict["outputs"]["out"] odt = self.get_output_datatype() target_bits = odt.bitwidth() packed_bits = self.get_outstream_width() diff --git a/src/finn/custom_op/fpgadataflow/hls/pool_hls.py b/src/finn/custom_op/fpgadataflow/hls/pool_hls.py index 64c6ec33f..609c53fd6 100644 --- a/src/finn/custom_op/fpgadataflow/hls/pool_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/pool_hls.py @@ -236,7 +236,12 @@ def execute_node(self, context, graph): ) super().reset_rtlsim(sim) super().toggle_clk(sim) - rtlsim_output = self.rtlsim(sim, rtlsim_inp) + io_dict = { + "inputs": {"in0": rtlsim_inp}, + "outputs": {"out": []}, + } + self.rtlsim_multi_io(sim, io_dict) + rtlsim_output = io_dict["outputs"]["out"] odt = self.get_output_datatype() target_bits = odt.bitwidth() packed_bits = self.get_outstream_width() diff --git a/src/finn/custom_op/fpgadataflow/hls/streamingdatawidthconverter_hls.py b/src/finn/custom_op/fpgadataflow/hls/streamingdatawidthconverter_hls.py index 4619a1756..c58aabbdb 100644 --- a/src/finn/custom_op/fpgadataflow/hls/streamingdatawidthconverter_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/streamingdatawidthconverter_hls.py @@ -178,7 +178,12 @@ def execute_node(self, context, graph): ) super().reset_rtlsim(sim) super().toggle_clk(sim) - rtlsim_output = self.rtlsim(sim, rtlsim_inp) + io_dict = { + "inputs": {"in0": rtlsim_inp}, + "outputs": {"out": []}, + } + self.rtlsim_multi_io(sim, io_dict) + rtlsim_output = io_dict["outputs"]["out"] odt = export_idt target_bits = odt.bitwidth() packed_bits = self.get_outstream_width() diff --git a/src/finn/custom_op/fpgadataflow/hls/streamingeltwise_hls.py b/src/finn/custom_op/fpgadataflow/hls/streamingeltwise_hls.py index 0d618d832..41ee72fe8 100644 --- a/src/finn/custom_op/fpgadataflow/hls/streamingeltwise_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/streamingeltwise_hls.py @@ -130,7 +130,12 @@ def execute_node(self, context, graph): ) super().reset_rtlsim(sim) super().toggle_clk(sim) - rtlsim_output = self.rtlsim(sim, rtlsim_inp0, rtlsim_inp1) + io_dict = { + "inputs": {"in0": rtlsim_inp0, "in1": rtlsim_inp1}, + "outputs": {"out": []}, + } + self.rtlsim_multi_io(sim, io_dict) + rtlsim_output = io_dict["outputs"]["out"] odt = self.get_output_datatype() target_bits = odt.bitwidth() packed_bits = self.get_outstream_width() diff --git a/src/finn/custom_op/fpgadataflow/hls/streamingmaxpool_hls.py b/src/finn/custom_op/fpgadataflow/hls/streamingmaxpool_hls.py index 69db7b460..f7546d7e1 100755 --- a/src/finn/custom_op/fpgadataflow/hls/streamingmaxpool_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/streamingmaxpool_hls.py @@ -191,7 +191,12 @@ def execute_node(self, context, graph): ) super().reset_rtlsim(sim) super().toggle_clk(sim) - rtlsim_output = self.rtlsim(sim, rtlsim_inp) + io_dict = { + "inputs": {"in0": rtlsim_inp}, + "outputs": {"out": []}, + } + self.rtlsim_multi_io(sim, io_dict) + rtlsim_output = io_dict["outputs"]["out"] odt = export_idt target_bits = odt.bitwidth() packed_bits = self.get_outstream_width() diff --git a/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py b/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py index b753bc7a0..4c0da73ec 100644 --- a/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/thresholding_hls.py @@ -348,12 +348,15 @@ def execute_node(self, context, graph): "inputs": {"in0": inp, "weights": wei * num_w_reps}, "outputs": {"out": []}, } - self.rtlsim_multi_io(sim, io_dict) - output = io_dict["outputs"]["out"] elif self.get_nodeattr("mem_mode") == "internal_embedded": - output = self.rtlsim(sim, inp) + io_dict = { + "inputs": {"in0": inp}, + "outputs": {"out": []}, + } else: raise Exception("Unrecognized mem_mode") + self.rtlsim_multi_io(sim, io_dict) + output = io_dict["outputs"]["out"] odt = self.get_output_datatype() target_bits = odt.bitwidth() packed_bits = self.get_outstream_width() diff --git a/src/finn/custom_op/fpgadataflow/hls/upsampler_hls.py b/src/finn/custom_op/fpgadataflow/hls/upsampler_hls.py index 05d26eddb..c6a062a77 100644 --- a/src/finn/custom_op/fpgadataflow/hls/upsampler_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/upsampler_hls.py @@ -149,7 +149,12 @@ def execute_node(self, context, graph): ) super().reset_rtlsim(sim) super().toggle_clk(sim) - rtlsim_output = self.rtlsim(sim, rtlsim_inp) + io_dict = { + "inputs": {"in0": rtlsim_inp}, + "outputs": {"out": []}, + } + self.rtlsim_multi_io(sim, io_dict) + rtlsim_output = io_dict["outputs"]["out"] odt = export_idt target_bits = odt.bitwidth() packed_bits = self.get_outstream_width() diff --git a/src/finn/custom_op/fpgadataflow/hls/vectorvectoractivation_hls.py b/src/finn/custom_op/fpgadataflow/hls/vectorvectoractivation_hls.py index f9ba68e6b..8f2419b69 100644 --- a/src/finn/custom_op/fpgadataflow/hls/vectorvectoractivation_hls.py +++ b/src/finn/custom_op/fpgadataflow/hls/vectorvectoractivation_hls.py @@ -208,10 +208,13 @@ def execute_node(self, context, graph): "inputs": {"in0": inp, "weights": wei * num_w_reps}, "outputs": {"out": []}, } - self.rtlsim_multi_io(sim, io_dict) - output = io_dict["outputs"]["out"] else: - output = self.rtlsim(sim, inp) + io_dict = { + "inputs": {"in0": inp}, + "outputs": {"out": []}, + } + self.rtlsim_multi_io(sim, io_dict) + output = io_dict["outputs"]["out"] odt = self.get_output_datatype() target_bits = odt.bitwidth() packed_bits = self.get_outstream_width() diff --git a/src/finn/custom_op/fpgadataflow/hwcustomop.py b/src/finn/custom_op/fpgadataflow/hwcustomop.py index 4d90664f7..dafe46910 100644 --- a/src/finn/custom_op/fpgadataflow/hwcustomop.py +++ b/src/finn/custom_op/fpgadataflow/hwcustomop.py @@ -69,6 +69,7 @@ def get_nodeattr_types(self): "res_estimate": ("s", False, ""), "res_synth": ("s", False, ""), "rtlsim_so": ("s", False, ""), + "rtlsim_backend": ("s", False, "pyverilator", {"pyverilator", "pyxsi"}), # partitioning info # ID of SLR to which the Op is attached in Vitis builds # Set to -1 as 'don't care' @@ -98,8 +99,6 @@ def get_nodeattr_types(self): # amount of zero padding inserted during chrc. "io_chrc_pads_in": ("ints", False, []), "io_chrc_pads_out": ("ints", False, []), - # experimental: rtlsim backend - "rtlsim_backend": ("s", False, "pyverilator", {"pyverilator", "pyxsi"}), } def get_verilog_top_module_name(self): diff --git a/src/finn/custom_op/fpgadataflow/rtl/convolutioninputgenerator_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/convolutioninputgenerator_rtl.py index 616591916..e6cfa204c 100755 --- a/src/finn/custom_op/fpgadataflow/rtl/convolutioninputgenerator_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/convolutioninputgenerator_rtl.py @@ -331,7 +331,12 @@ def execute_node(self, context, graph): ) super().reset_rtlsim(sim) super().toggle_clk(sim) - rtlsim_output = self.rtlsim(sim, rtlsim_inp) + io_dict = { + "inputs": {"in0": rtlsim_inp}, + "outputs": {"out": []}, + } + self.rtlsim_multi_io(sim, io_dict) + rtlsim_output = io_dict["outputs"]["out"] odt = export_idt target_bits = odt.bitwidth() packed_bits = self.get_outstream_width() diff --git a/src/finn/custom_op/fpgadataflow/rtl/fmpadding_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/fmpadding_rtl.py index 4b37577ca..2fd589dd9 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/fmpadding_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/fmpadding_rtl.py @@ -91,7 +91,12 @@ def execute_node(self, context, graph): ) super().reset_rtlsim(sim) super().toggle_clk(sim) - rtlsim_output = self.rtlsim(sim, rtlsim_inp) + io_dict = { + "inputs": {"in0": rtlsim_inp}, + "outputs": {"out": []}, + } + self.rtlsim_multi_io(sim, io_dict) + rtlsim_output = io_dict["outputs"]["out"] odt = export_idt target_bits = odt.bitwidth() packed_bits = self.get_outstream_width() diff --git a/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py index b950d5a83..4dc883f64 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py @@ -108,10 +108,13 @@ def execute_node(self, context, graph): "inputs": {"in0": inp, "weights": wei * num_w_reps}, "outputs": {"out": []}, } - self.rtlsim_multi_io(sim, io_dict) - output = io_dict["outputs"]["out"] else: - output = self.rtlsim(sim, inp) + io_dict = { + "inputs": {"in0": inp}, + "outputs": {"out": []}, + } + self.rtlsim_multi_io(sim, io_dict) + output = io_dict["outputs"]["out"] odt = self.get_output_datatype() target_bits = odt.bitwidth() packed_bits = self.get_outstream_width() diff --git a/src/finn/custom_op/fpgadataflow/rtl/streamingdatawidthconverter_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/streamingdatawidthconverter_rtl.py index fdb763c81..ad9c8d4f0 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/streamingdatawidthconverter_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/streamingdatawidthconverter_rtl.py @@ -95,7 +95,12 @@ def execute_node(self, context, graph): ) super().reset_rtlsim(sim) super().toggle_clk(sim) - rtlsim_output = self.rtlsim(sim, rtlsim_inp) + io_dict = { + "inputs": {"in0": rtlsim_inp}, + "outputs": {"out": []}, + } + self.rtlsim_multi_io(sim, io_dict) + rtlsim_output = io_dict["outputs"]["out"] odt = export_idt target_bits = odt.bitwidth() packed_bits = self.get_outstream_width() diff --git a/src/finn/custom_op/fpgadataflow/rtl/streamingfifo_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/streamingfifo_rtl.py index 6c38dd405..1b1d632bd 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/streamingfifo_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/streamingfifo_rtl.py @@ -147,7 +147,12 @@ def execute_node(self, context, graph): inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits) super().reset_rtlsim(sim) super().toggle_clk(sim) - output = self.rtlsim(sim, inp) + io_dict = { + "inputs": {"in0": inp}, + "outputs": {"out": []}, + } + self.rtlsim_multi_io(sim, io_dict) + output = io_dict["outputs"]["out"] odt = DataType[self.get_nodeattr("dataType")] target_bits = odt.bitwidth() packed_bits = self.get_outstream_width() diff --git a/src/finn/custom_op/fpgadataflow/rtl/vectorvectoractivation_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/vectorvectoractivation_rtl.py index 8273978c6..901ff99b0 100644 --- a/src/finn/custom_op/fpgadataflow/rtl/vectorvectoractivation_rtl.py +++ b/src/finn/custom_op/fpgadataflow/rtl/vectorvectoractivation_rtl.py @@ -115,10 +115,13 @@ def execute_node(self, context, graph): "inputs": {"in0": inp, "weights": wei * num_w_reps}, "outputs": {"out": []}, } - self.rtlsim_multi_io(sim, io_dict) - output = io_dict["outputs"]["out"] else: - output = self.rtlsim(sim, inp) + io_dict = { + "inputs": {"in0": inp}, + "outputs": {"out": []}, + } + self.rtlsim_multi_io(sim, io_dict) + output = io_dict["outputs"]["out"] odt = self.get_output_datatype() target_bits = odt.bitwidth() packed_bits = self.get_outstream_width()