From 7d5a8b6b2103b6ebd931a0b9d0479808007d5c4d Mon Sep 17 00:00:00 2001 From: icolbert Date: Thu, 3 Aug 2023 07:53:34 -0700 Subject: [PATCH] Pre-commit fixes --- tests/fpgadataflow/test_minimize_bit_width.py | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/tests/fpgadataflow/test_minimize_bit_width.py b/tests/fpgadataflow/test_minimize_bit_width.py index 0427bbd4d8..4be0a260b7 100644 --- a/tests/fpgadataflow/test_minimize_bit_width.py +++ b/tests/fpgadataflow/test_minimize_bit_width.py @@ -294,9 +294,7 @@ def test_minimize_accumulator_width(wdt: DataType, idt: DataType, tdt: DataType, # bit width minimization logic in the MVAU and VVAU is exact and should be # less than or equal to this calculation exp_adt = calculate_accumulator_bit_width(inst, model) - assert ( - cur_adt.bitwidth() <= exp_adt.bitwidth() - ), "Mismatched accumulation data types" + assert cur_adt.bitwidth() <= exp_adt.bitwidth(), "Mismatched accumulation data types" # if there is no activation, outputDataType = accDataType if inst.get_nodeattr("noActivation"):