[pyxsi] Remove references to rpc setup in cherry-picked commits

Xilinx · Nov 19, 2024 · 6a16fdf · 6a16fdf
1 parent 28e482b
commit 6a16fdf
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Showing 2 changed files with 11 additions and 5 deletions.
diff --git a/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py b/src/finn/custom_op/fpgadataflow/rtl/matrixvectoractivation_rtl.py
@@ -94,8 +94,9 @@ def execute_node(self, context, graph):
                 sim = self.get_rtlsim()
                 nbits = self.get_instream_width()
                 inp = npy_to_rtlsim_input("{}/input_0.npy".format(code_gen_dir), export_idt, nbits)
-                self.reset_rtlsim(sim)
-                self.toggle_clk(sim)
+                super().reset_rtlsim(sim)
+                if self.get_nodeattr("rtlsim_backend") == "pyverilator":
+                    super().toggle_clk(sim)
                 if mem_mode in ["external", "internal_decoupled"]:
                     wnbits = self.get_weightstream_width()
                     export_wdt = self.get_weight_datatype()
@@ -113,6 +114,7 @@ def execute_node(self, context, graph):
                         "outputs": {"out": []},
                     }
                 self.rtlsim_multi_io(sim, io_dict)
+                super().close_rtlsim(sim)
                 output = io_dict["outputs"]["out"]
                 odt = self.get_output_datatype()
                 target_bits = odt.bitwidth()
@@ -292,7 +294,7 @@ def get_rtl_file_list(self, abspath=False):
             code_gen_dir = ""
             rtllib_dir = ""
         verilog_files = [
-            code_gen_dir + self.get_nodeattr("gen_top_module") + "_wrapper.v",
+            code_gen_dir + self.get_nodeattr("gen_top_module") + "_wrapper_sim.v",
             rtllib_dir + "mvu_vvu_axi.sv",
             rtllib_dir + "replay_buffer.sv",
             rtllib_dir + "mvu_4sx4u.sv",

diff --git a/src/finn/custom_op/fpgadataflow/rtlbackend.py b/src/finn/custom_op/fpgadataflow/rtlbackend.py
@@ -28,14 +28,18 @@
 
 from abc import ABC, abstractmethod
 
-from finn.util import pyxsi_rpcclient
 from finn.util.basic import get_rtlsim_trace_depth, make_build_dir
 
 try:
     from pyverilator import PyVerilator
 except ModuleNotFoundError:
     PyVerilator = None
 
+try:
+    import pyxsi_utils
+except ModuleNotFoundError:
+    pyxsi_utils = None
+
 
 class RTLBackend(ABC):
     """RTLBackend class all custom ops that correspond to a module in finn-rtllib
@@ -81,7 +85,7 @@ def prepare_rtlsim(self):
         elif rtlsim_backend == "pyxsi":
             verilog_files = self.get_rtl_file_list(abspath=True)
             single_src_dir = make_build_dir("rtlsim_" + self.onnx_node.name + "_")
-            ret = pyxsi_rpcclient.compile_sim_obj(
+            ret = pyxsi_utils.compile_sim_obj(
                 self.get_verilog_top_module_name(), verilog_files, single_src_dir
             )
             # save generated lib filename in attribute