write_template for VHDL testbench not implemented...

[maxroc]

In the Xilinx TclStore designutils rev. 1.8 , the write_template doesn't seem to implement the -testbench for VHDL feature.
For ex. the following command in Vivado 2014.4 for an opened implemented design returns a message reading "not yet implemented" and an empty file:

TCL Console> ::tclapp::xilinx::designutils::write_template -testbench -vhdl -file C:/M/Temp/footb.vhd

Any chance this will be implemented in the near future?