versal: integrate lpd int csr #20
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kay-ge
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Copy the SERBS interface implementation from Xilinx QEMU fork as a dependency for LPD INT control and status register block. Includes meson changes to build SERBS IF. Signed-off-by: Nelson Ho <[email protected]>
Copy the xlnx-versal-intlpd-config implementation from the Xilinx QEMU fork. This is just a barebones device implementation intended to satisfy the reg writes in versal bsp sysBoardInit. Signed-off-by: Nelson Ho <[email protected]>
Split the LPD INT CSR state structure into a header file for inclusion in Versal SoC. There is a large gap in the register space from R_IR_DISABLE_MISSION2 to R_LPD_AFIFM_ADMA_APB, which results in a large unused space allocated as part of the reg array in the state structure. Since HVP does not attempt to configure the registers at 0x10000 offset and above, I have commented out these registers and associated handlers. Contains meson changes to build the LPD interrupt config device when Xilinx Versal is configured to be built. Signed-off-by: Nelson Ho <[email protected]>
Integrate the low power domain interconnect isolation control and status registers into the Versal SoC. Signed-off-by: Nelson Ho <[email protected]>
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This change adds the low power domain interconnect isolation control and status register to the versal SoC. This changeset pulls in the SERBS interface implementation from the Xilinx QEMU fork as a dependency, and maps the LPD interconnect control and status register block into the Versal SoC PS address space.