From d55e77f704cb0e0e3e3dded874b342775862d2af Mon Sep 17 00:00:00 2001 From: Nelson Ho Date: Mon, 9 Dec 2024 22:18:45 +0000 Subject: [PATCH] versal: integrate PMC interconnect CSR Integrate the Platform Management Controller interconnect configuration and status register block model into the Versal SoC. This is to satisfy the PMC INT DMA0 and DMA1 route configuration that HVP performs during system initialization. Signed-off-by: Nelson Ho --- hw/arm/xlnx-versal.c | 16 ++++++++++++++++ include/hw/arm/xlnx-versal.h | 4 ++++ 2 files changed, 20 insertions(+) diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 6bcf42dad9..015b472bde 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -805,6 +805,21 @@ static void versal_create_crl(Versal *s, qemu_irq *pic) sysbus_connect_irq(sbd, 0, pic[VERSAL_CRL_IRQ]); } +static void versal_create_pmcint(Versal *s) +{ + SysBusDevice *sbd; + MemoryRegion *mr; + + object_initialize_child(OBJECT(s), "pmc-int", &s->pmc.pmcint, + TYPE_XILINX_PMC_INT_REGS); + sbd = SYS_BUS_DEVICE(&s->pmc.pmcint); + sysbus_realize(sbd, &error_fatal); + + mr = sysbus_mmio_get_region(sbd, 0); + + memory_region_add_subregion(&s->mr_ps, MM_PMC_INT_CSR, mr); +} + static void versal_create_smmu(Versal *s, qemu_irq *pic) { SysBusDevice *sbd; @@ -998,6 +1013,7 @@ static void versal_realize(DeviceState *dev, Error **errp) versal_create_lpd_slcr(s); versal_create_crl(s, pic); versal_create_cfu(s, pic); + versal_create_pmcint(s); versal_map_ddr(s); versal_unimp(s); diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index e5d21c0011..4cda04100c 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -35,6 +35,7 @@ #include "hw/misc/xlnx-versal-pmc-iou-slcr.h" #include "hw/misc/xlnx-versal-trng.h" #include "hw/misc/xlnx-versal-lpd-iou-slcr.h" +#include "hw/misc/xlnx-versal-pmc-int.h" #include "hw/net/xlnx-versal-canfd.h" #include "hw/misc/xlnx-versal-cfu.h" #include "hw/misc/xlnx-versal-cframe-reg.h" @@ -136,6 +137,7 @@ struct Versal { XlnxVersalCFUSFR cfu_sfr; XlnxVersalCFrameReg cframe[XLNX_VERSAL_NR_CFRAME]; XlnxVersalCFrameBcastReg cframe_bcast; + PMC_INT_REGS pmcint; OrIRQState apb_irq_orgate; } pmc; @@ -353,4 +355,6 @@ struct Versal { #define MM_PMC_RTC_SIZE 0x10000 #define MM_PMC_TRNG 0xf1230000 #define MM_PMC_TRNG_SIZE 0x10000 + +#define MM_PMC_INT_CSR 0xf1330000 #endif