versal: integrate LPD INT CSR

Integrate the low power domain interconnect isolation control and status registers into the Versal SoC. Signed-off-by: Nelson Ho <[email protected]>
Wind-River · Dec 10, 2024 · bc261a9 · bc261a9
1 parent b29e8d0
commit bc261a9
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diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c
@@ -390,6 +390,21 @@ static void versal_create_trng(Versal *s, qemu_irq *pic)
     sysbus_connect_irq(sbd, 0, pic[VERSAL_TRNG_IRQ]);
 }
 
+static void versal_create_intlpd_csr(Versal *s)
+{
+    SysBusDevice *sbd;
+    MemoryRegion *mr;
+
+    object_initialize_child(OBJECT(s), "lpd_int_csr", &s->lpd.int_csr,
+                            TYPE_XILINX_INTLPD_CONFIG);
+    sbd = SYS_BUS_DEVICE(&s->lpd.int_csr);
+    sysbus_realize(sbd, &error_fatal);
+
+    mr = sysbus_mmio_get_region(sbd, 0);
+
+    memory_region_add_subregion(&s->mr_ps, MM_LPD_INT_CSR, mr);
+}
+
 static void versal_create_xrams(Versal *s, qemu_irq *pic)
 {
     int nr_xrams = ARRAY_SIZE(s->lpd.xram.ctrl);
@@ -974,6 +989,7 @@ static void versal_realize(DeviceState *dev, Error **errp)
     versal_create_pmc_apb_irq_orgate(s, pic);
     versal_create_rtc(s, pic);
     versal_create_trng(s, pic);
+    versal_create_intlpd_csr(s);
     versal_create_xrams(s, pic);
     versal_create_bbram(s, pic);
     versal_create_efuse(s, pic);

diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h
@@ -24,6 +24,7 @@
 #include "hw/rtc/xlnx-zynqmp-rtc.h"
 #include "qom/object.h"
 #include "hw/usb/xlnx-usb-subsystem.h"
+#include "hw/misc/xlnx-versal-intlpd-config.h"
 #include "hw/misc/xlnx-versal-xramc.h"
 #include "hw/nvram/xlnx-bbram.h"
 #include "hw/nvram/xlnx-versal-efuse.h"
@@ -106,6 +107,7 @@ struct Versal {
 
         XlnxVersalCRL crl;
         LPD_SLCR slcr;
+        INTLPD_CONFIG int_csr;
     } lpd;
 
     /* The Platform Management Controller subsystem.  */
@@ -210,6 +212,8 @@ struct Versal {
 #define MM_OCM                      0xfffc0000U
 #define MM_OCM_SIZE                 0x40000
 
+#define MM_LPD_INT_CSR              0xfe600000
+
 #define MM_XRAM                     0xfe800000
 #define MM_XRAMC                    0xff8e0000
 #define MM_XRAMC_SIZE               0x10000