From fc8606f107d9b6d20b9476df5dabd945a5630e45 Mon Sep 17 00:00:00 2001 From: Marat Dukhan Date: Tue, 24 Sep 2019 04:53:21 -0700 Subject: [PATCH] Sign Select instructions --- proposals/simd/BinarySIMD.md | 4 ++++ proposals/simd/ImplementationStatus.md | 4 ++++ proposals/simd/SIMD.md | 11 +++++++++++ 3 files changed, 19 insertions(+) diff --git a/proposals/simd/BinarySIMD.md b/proposals/simd/BinarySIMD.md index 57971f165..08c109309 100644 --- a/proposals/simd/BinarySIMD.md +++ b/proposals/simd/BinarySIMD.md @@ -249,3 +249,7 @@ For example, `ImmLaneIdx16` is a byte with values in the range 0-15 (inclusive). | `v128.store16_lane` | `TBD`| m:memarg, i:ImmLaneIdx8 | | `v128.store32_lane` | `TBD`| m:memarg, i:ImmLaneIdx4 | | `v128.store64_lane` | `TBD`| m:memarg, i:ImmLaneIdx2 | +| `v8x16.signselect` | `TBD`| - | +| `v16x8.signselect` | `TBD`| - | +| `v32x4.signselect` | `TBD`| - | +| `v64x2.signselect` | `TBD`| - | diff --git a/proposals/simd/ImplementationStatus.md b/proposals/simd/ImplementationStatus.md index a2b18c992..581fa9972 100644 --- a/proposals/simd/ImplementationStatus.md +++ b/proposals/simd/ImplementationStatus.md @@ -217,6 +217,10 @@ | `v128.store16_lane` | | | | | | | `v128.store32_lane` | | | | | | | `v128.store64_lane` | | | | | | +| `v8x16.signselect` | | | | | | +| `v16x8.signselect` | | | | | | +| `v32x4.signselect` | | | | | | +| `v64x2.signselect` | | | | | | [1] Tip of tree LLVM as of May 20, 2020 diff --git a/proposals/simd/SIMD.md b/proposals/simd/SIMD.md index 24db53eb1..701ad42ac 100644 --- a/proposals/simd/SIMD.md +++ b/proposals/simd/SIMD.md @@ -662,6 +662,17 @@ Note that the normal WebAssembly `select` instruction also works with vector types. It selects between two whole vectors controlled by a single scalar value, rather than selecting bits controlled by a control mask vector. +### Sign select +* `v8x16.signselect(v1: v128, v2: v128, c: v128) -> v128` +* `v16x8.signselect(v1: v128, v2: v128, c: v128) -> v128` +* `v32x4.signselect(v1: v128, v2: v128, c: v128) -> v128` +* `v64x2.signselect(v1: v128, v2: v128, c: v128) -> v128` + +Use the sign bits in the control mask `c` to select the corresponding element +from `v1` when 1 (negative sign) and `v2` when 0 (positive sign). + +Note that these instructions work for both signed integer and floating-point +control masks. ## Boolean horizontal reductions