constraint_ft600.sdc

## Constraints required for design.
## Please modify it according to your actual situation.
##
## Note:
##    The clock of FT600/FT601   chip (ftdi_clk) is 100MHz
##    The clock of FT232H/FT232H chip (ftdi_clk) is 60MHz
##    It is also necessary to declare that the FPGA's main clock and ftdi_clk clock are asynchronous. Because they only transmit data through asynchronous FIFO
##

## 50MHz FPGA main clock (usually generated by oscillator)
create_clock -name clk      -period  20.000  [get_ports clk]            

## 100MHz FT600 chip clock (generated by FT600)
create_clock -name ftdi_clk -period  10.000  [get_ports ftdi_clk]        

## Declare that these two clocks are asynchronous
set_clock_groups -asynchronous -group {clk} -group {ftdi_clk}