A memory mapped bus functional model library

Overview

The purpose of the library is to provide a convenient way to interact with a device under test using any memory mapped bus protocol. The library will consist of several parts:

1. A general API to read and write data to an address space.
2. A memory model where data can be allocated, read and written.
3. Bus transactors for translation between general read/write commands on the API to actual bus signaling such as AXI or XILINX BRAM interface.

Read/Write API

-- Raw API, migth have higher level convenience procedures for 32-bit, 16-bit etc
procedure write(signal net : inout net_t; address : integer; data : integer_vector; num_bytes : integer; timeout : time);
procedure read(signal net : inout net_t; address : integer; variable data : inout integer_vector; num_bytes : integer; timeout : time);

Memory Model

The memory model supports:

1. Reading and writing data to it
2. Setting access flags on addresses such as write_only, read_only, read_write, write_reference_data
3. Allocating address space in the memory for data buffers with meta-data information to provide good error messages such as the name of the buffer and the internal offset as well as the number of bytes per word and potentially also line pitch for images.
4. Method to check that an address space has been written with the expected reference data.

Bus Transactors

The following bus transactors are initially planned to be implemented.

1. AXI master talking either directly to the memory model.
2. AXI lite slave
3. XILINX BRAM slave

The bus transactors should also support several bus specific configuration that can be changed at run time such as the data rate and fifo depths for different AXI channels.