From ad8dbf20426be819d1edbc212e7dd4d4f4f2a13f Mon Sep 17 00:00:00 2001 From: Lars Asplund Date: Sat, 1 Jan 2022 23:06:29 +0100 Subject: [PATCH] Added VHDL configuration examples. --- examples/vhdl/vhdl_configuration/dff.vhd | 62 ++++++++++++ .../handling_generics_limitation/tb_reset.vhd | 59 ++++++++++++ ..._selecting_dut_with_generate_statement.vhd | 95 +++++++++++++++++++ .../tb_state_change.vhd | 65 +++++++++++++ .../test_fixture.vhd | 38 ++++++++ examples/vhdl/vhdl_configuration/run.py | 60 ++++++++++++ ..._selecting_dut_with_vhdl_configuration.vhd | 92 ++++++++++++++++++ ...ng_test_runner_with_vhdl_configuration.vhd | 78 +++++++++++++++ .../vhdl/vhdl_configuration/test_reset.vhd | 37 ++++++++ .../vhdl/vhdl_configuration/test_runner.vhd | 22 +++++ .../vhdl_configuration/test_state_change.vhd | 43 +++++++++ tests/acceptance/test_external_run_scripts.py | 26 +++++ 12 files changed, 677 insertions(+) create mode 100644 examples/vhdl/vhdl_configuration/dff.vhd create mode 100644 examples/vhdl/vhdl_configuration/handling_generics_limitation/tb_reset.vhd create mode 100644 examples/vhdl/vhdl_configuration/handling_generics_limitation/tb_selecting_dut_with_generate_statement.vhd create mode 100644 examples/vhdl/vhdl_configuration/handling_generics_limitation/tb_state_change.vhd create mode 100644 examples/vhdl/vhdl_configuration/handling_generics_limitation/test_fixture.vhd create mode 100644 examples/vhdl/vhdl_configuration/run.py create mode 100644 examples/vhdl/vhdl_configuration/tb_selecting_dut_with_vhdl_configuration.vhd create mode 100644 examples/vhdl/vhdl_configuration/tb_selecting_test_runner_with_vhdl_configuration.vhd create mode 100644 examples/vhdl/vhdl_configuration/test_reset.vhd create mode 100644 examples/vhdl/vhdl_configuration/test_runner.vhd create mode 100644 examples/vhdl/vhdl_configuration/test_state_change.vhd diff --git a/examples/vhdl/vhdl_configuration/dff.vhd b/examples/vhdl/vhdl_configuration/dff.vhd new file mode 100644 index 000000000..958541c37 --- /dev/null +++ b/examples/vhdl/vhdl_configuration/dff.vhd @@ -0,0 +1,62 @@ +-- This Source Code Form is subject to the terms of the Mozilla Public +-- License, v. 2.0. If a copy of the MPL was not distributed with this file, +-- You can obtain one at http://mozilla.org/MPL/2.0/. +-- +-- Copyright (c) 2014-2021, Lars Asplund lars.anders.asplund@gmail.com +library ieee; +use ieee.std_logic_1164.all; + +entity dff is + generic( + width : positive := 8 + ); + port( + clk : in std_logic; + reset : in std_logic; + d : in std_logic_vector(width - 1 downto 0); + q : out std_logic_vector(width - 1 downto 0) + ); +end; + +architecture rtl of dff is +begin + process(clk) is + begin + if rising_edge(clk) then + if reset = '1' then + q <= (others => '0'); + else + q <= d; + end if; + end if; + end process; +end; + +configuration dff_rtl of tb_selecting_dut_with_vhdl_configuration is + for tb + for test_fixture + for dut : dff + use entity work.dff(rtl); + end for; + end for; + end for; +end; + +architecture behavioral of dff is +begin + process + begin + wait until rising_edge(clk); + q <= (others => '0') when reset else d; + end process; +end; + +configuration dff_behavioral of tb_selecting_dut_with_vhdl_configuration is + for tb + for test_fixture + for dut : dff + use entity work.dff(behavioral); + end for; + end for; + end for; +end; diff --git a/examples/vhdl/vhdl_configuration/handling_generics_limitation/tb_reset.vhd b/examples/vhdl/vhdl_configuration/handling_generics_limitation/tb_reset.vhd new file mode 100644 index 000000000..465452bb1 --- /dev/null +++ b/examples/vhdl/vhdl_configuration/handling_generics_limitation/tb_reset.vhd @@ -0,0 +1,59 @@ +-- This Source Code Form is subject to the terms of the Mozilla Public +-- License, v. 2.0. If a copy of the MPL was not distributed with this file, +-- You can obtain one at http://mozilla.org/MPL/2.0/. +-- +-- Copyright (c) 2014-2021, Lars Asplund lars.anders.asplund@gmail.com +-- +-- Description: Instead of having a testbench containing a shared test fixture +-- and then use VHDL configurations to select different test runners implementing +-- different tests one can flip things upside down. Each test become a separate +-- top-level testbench and the shared test fixture is placed in a separate entity +-- imported by each tetbench. + +library vunit_lib; +context vunit_lib.vunit_context; + +library ieee; +use ieee.std_logic_1164.all; + +entity tb_reset is + generic( + runner_cfg : string; + width : positive + ); +end entity; + +architecture tb of tb_reset is + constant clk_period : time := 10 ns; + + signal reset : std_logic; + signal clk : std_logic; + signal d : std_logic_vector(width - 1 downto 0); + signal q : std_logic_vector(width - 1 downto 0); +begin + text_fixture_inst : entity work.test_fixture + generic map( + width => width, + clk_period => clk_period + ) + port map( + clk => clk, + reset => reset, + d => d, + q => q + ); + + test_runner : process + begin + test_runner_setup(runner, runner_cfg); + + d <= (others => '1'); + reset <= '1'; + wait until rising_edge(clk); + wait for 0 ns; + check_equal(q, 0); + + test_runner_cleanup(runner); + end process; + +end architecture; diff --git a/examples/vhdl/vhdl_configuration/handling_generics_limitation/tb_selecting_dut_with_generate_statement.vhd b/examples/vhdl/vhdl_configuration/handling_generics_limitation/tb_selecting_dut_with_generate_statement.vhd new file mode 100644 index 000000000..423f8ac0a --- /dev/null +++ b/examples/vhdl/vhdl_configuration/handling_generics_limitation/tb_selecting_dut_with_generate_statement.vhd @@ -0,0 +1,95 @@ +-- This Source Code Form is subject to the terms of the Mozilla Public +-- License, v. 2.0. If a copy of the MPL was not distributed with this file, +-- You can obtain one at http://mozilla.org/MPL/2.0/. +-- +-- Copyright (c) 2014-2021, Lars Asplund lars.anders.asplund@gmail.com +-- +-- Description: This is an example of a testbench using a generic instead +-- of VHDL configurations to select the DUT to run. Without VHDL configurations +-- the width generic to the dff entity can be exposed and modified at the top-level + +library vunit_lib; +context vunit_lib.vunit_context; + +library ieee; +use ieee.std_logic_1164.all; + +entity tb_selecting_dut_with_generate_statement is + generic( + runner_cfg : string; + width : positive; + dff_arch : string + ); +end entity; + +architecture tb of tb_selecting_dut_with_generate_statement is + constant clk_period : time := 10 ns; + + signal reset : std_logic; + signal clk : std_logic := '0'; + signal d : std_logic_vector(width - 1 downto 0); + signal q : std_logic_vector(width - 1 downto 0); +begin + test_runner : process + begin + test_runner_setup(runner, runner_cfg); + + while test_suite loop + if run("Test reset") then + d <= (others => '1'); + reset <= '1'; + wait until rising_edge(clk); + wait for 0 ns; + check_equal(q, 0); + + elsif run("Test state change") then + reset <= '0'; + + d <= (others => '1'); + wait until rising_edge(clk); + wait for 0 ns; + check_equal(q, std_logic_vector'(q'range => '1')); + + d <= (others => '0'); + wait until rising_edge(clk); + wait for 0 ns; + check_equal(q, 0); + end if; + end loop; + + test_runner_cleanup(runner); + end process; + + test_fixture : block is + begin + clk <= not clk after clk_period / 2; + + dut_selection : if dff_arch = "rtl" generate + dut : entity work.dff(rtl) + generic map( + width => width + ) + port map( + clk => clk, + reset => reset, + d => d, + q => q + ); + + elsif dff_arch = "behavioral" generate + dut : entity work.dff(behavioral) + generic map( + width => width + ) + port map( + clk => clk, + reset => reset, + d => d, + q => q + ); + + else generate + error("Unknown DFF architecture"); + end generate; + end block; +end architecture; diff --git a/examples/vhdl/vhdl_configuration/handling_generics_limitation/tb_state_change.vhd b/examples/vhdl/vhdl_configuration/handling_generics_limitation/tb_state_change.vhd new file mode 100644 index 000000000..38dc37720 --- /dev/null +++ b/examples/vhdl/vhdl_configuration/handling_generics_limitation/tb_state_change.vhd @@ -0,0 +1,65 @@ +-- This Source Code Form is subject to the terms of the Mozilla Public +-- License, v. 2.0. If a copy of the MPL was not distributed with this file, +-- You can obtain one at http://mozilla.org/MPL/2.0/. +-- +-- Copyright (c) 2014-2021, Lars Asplund lars.anders.asplund@gmail.com +-- +-- Description: Instead of having a testbench containing a shared test fixture +-- and then use VHDL configurations to select different test runners implementing +-- different tests one can flip things upside down. Each test become a separate +-- top-level testbench and the shared test fixture is placed in a separate entity +-- imported by each tetbench. + +library vunit_lib; +context vunit_lib.vunit_context; + +library ieee; +use ieee.std_logic_1164.all; + +entity tb_state_change is + generic( + runner_cfg : string; + width : positive + ); +end entity; + +architecture tb of tb_state_change is + constant clk_period : time := 10 ns; + + signal reset : std_logic; + signal clk : std_logic; + signal d : std_logic_vector(width - 1 downto 0); + signal q : std_logic_vector(width - 1 downto 0); +begin + text_fixture_inst : entity work.test_fixture + generic map( + width => width, + clk_period => clk_period + ) + port map( + clk => clk, + reset => reset, + d => d, + q => q + ); + + test_runner : process + begin + test_runner_setup(runner, runner_cfg); + + reset <= '0'; + + d <= (others => '1'); + wait until rising_edge(clk); + wait for 0 ns; + check_equal(q, std_logic_vector'(q'range => '1')); + + d <= (others => '0'); + wait until rising_edge(clk); + wait for 0 ns; + check_equal(q, 0); + + test_runner_cleanup(runner); + end process; + +end architecture; diff --git a/examples/vhdl/vhdl_configuration/handling_generics_limitation/test_fixture.vhd b/examples/vhdl/vhdl_configuration/handling_generics_limitation/test_fixture.vhd new file mode 100644 index 000000000..0eada4994 --- /dev/null +++ b/examples/vhdl/vhdl_configuration/handling_generics_limitation/test_fixture.vhd @@ -0,0 +1,38 @@ +-- This Source Code Form is subject to the terms of the Mozilla Public +-- License, v. 2.0. If a copy of the MPL was not distributed with this file, +-- You can obtain one at http://mozilla.org/MPL/2.0/. +-- +-- Copyright (c) 2014-2021, Lars Asplund lars.anders.asplund@gmail.com + +library ieee; +use ieee.std_logic_1164.all; + +entity test_fixture is + generic( + width : positive := 8; + clk_period : time + ); + port( + clk : out std_logic := '0'; + reset : in std_logic; + d : in std_logic_vector(width - 1 downto 0); + q : out std_logic_vector(width - 1 downto 0) + ); +end entity; + +architecture tb of test_fixture is +begin + clk <= not clk after clk_period / 2; + + dut : entity work.dff(rtl) + generic map( + width => width + ) + port map( + clk => clk, + reset => reset, + d => d, + q => q + ); + +end architecture; diff --git a/examples/vhdl/vhdl_configuration/run.py b/examples/vhdl/vhdl_configuration/run.py new file mode 100644 index 000000000..194201db9 --- /dev/null +++ b/examples/vhdl/vhdl_configuration/run.py @@ -0,0 +1,60 @@ +#!/usr/bin/env python3 + +# This Source Code Form is subject to the terms of the Mozilla Public +# License, v. 2.0. If a copy of the MPL was not distributed with this file, +# You can obtain one at http://mozilla.org/MPL/2.0/. +# +# Copyright (c) 2014-2021, Lars Asplund lars.anders.asplund@gmail.com + +from pathlib import Path +from vunit import VUnit +from vunit.json4vhdl import encode_json, b16encode + +vu = VUnit.from_argv(compile_builtins=False) +vu.add_vhdl_builtins() +lib = vu.add_library("lib") +lib.add_source_files(Path(__file__).parent / "*.vhd") +lib.add_source_files(Path(__file__).parent / "handling_generics_limitation" / "*.vhd") + +# VHDL configurations are detected automatically and are treated as a special +# case of the broader VUnit configuration concept. As such the configuration +# can be extended beyond the capabilities of a pure VHDL configuration. For example, +# by adding a post_check function. The exception is generics since VHDL doesn't allow +# generics to be combined with configurations. Workarounds for this limitation can be +# found in the handling_generics_limitation directory + +# Get the VHDL-defined configurations from test or testbench objects using a pattern matching +# configurations of interest. +tb = lib.test_bench("tb_selecting_dut_with_vhdl_configuration") +configurations = tb.get_configs("dff_*") + +# Remember to run the run script with the -v flag to see the message from the dummy post_check +def post_check(output_path): + print("Running post-check") + + return True + + +configurations.set_post_check(post_check) + +# The testbenches in the handling_generics_limitation directory are examples of how the generics +# limitation of VHDL configurations can be worked around. This allow us to create configurations +# with different settings for the DUT width generic + +# This testbench replaces VHDL configurations with generate statements +tb = lib.test_bench("tb_selecting_dut_with_generate_statement") +for width in [8, 32]: + for arch in ["rtl", "behavioral"]: + tb.add_config(name=f"dff_{arch}_width={width}", generics=dict(dff_arch=arch, width=width)) + +# Instead of having a testbench containing a shared test fixture +# and then use VHDL configurations to select different test runners implementing +# different tests one can flip things upside down. Each test become a separate +# top-level testbench and the shared test fixture is placed in a separate entity +# imported by each tetbench. +for tb_name in ["tb_reset", "tb_state_change"]: + tb = lib.test_bench(tb_name) + for width in [8, 32]: + tb.add_config(name=f"width={width}", generics=dict(width=width)) + +vu.main() diff --git a/examples/vhdl/vhdl_configuration/tb_selecting_dut_with_vhdl_configuration.vhd b/examples/vhdl/vhdl_configuration/tb_selecting_dut_with_vhdl_configuration.vhd new file mode 100644 index 000000000..6cdb8ccfc --- /dev/null +++ b/examples/vhdl/vhdl_configuration/tb_selecting_dut_with_vhdl_configuration.vhd @@ -0,0 +1,92 @@ +-- This Source Code Form is subject to the terms of the Mozilla Public +-- License, v. 2.0. If a copy of the MPL was not distributed with this file, +-- You can obtain one at http://mozilla.org/MPL/2.0/. +-- +-- Copyright (c) 2014-2021, Lars Asplund lars.anders.asplund@gmail.com +-- +-- Description: This is an example of a testbench using VHDL configurations +-- to select DUT architecture + +library vunit_lib; +context vunit_lib.vunit_context; + +library ieee; +use ieee.std_logic_1164.all; + +entity tb_selecting_dut_with_vhdl_configuration is + -- VHDL doesn't support generics with VHDL configurations. + -- Assigning null_runner_cfg to runner_cfg will instruct + -- test_runner_setup to look for a runner.cfg file containing the + -- same information. Note that runner_cfg must remain present to + -- indicate that this is a testbench entity. + generic(runner_cfg : string := null_runner_cfg); +end entity; + +architecture tb of tb_selecting_dut_with_vhdl_configuration is + constant clk_period : time := 10 ns; + constant width : positive := 8; + + signal reset : std_logic; + signal clk : std_logic := '0'; + signal d : std_logic_vector(width - 1 downto 0); + signal q : std_logic_vector(width - 1 downto 0); + + component dff is + generic( + width : positive := width + ); + port( + clk : in std_logic; + reset : in std_logic; + d : in std_logic_vector(width - 1 downto 0); + q : out std_logic_vector(width - 1 downto 0) + ); + end component; + +begin + test_runner : process + begin + test_runner_setup(runner, runner_cfg); + + while test_suite loop + if run("Test reset") then + d <= (others => '1'); + reset <= '1'; + wait until rising_edge(clk); + wait for 0 ns; + check_equal(q, 0); + + elsif run("Test state change") then + reset <= '0'; + + d <= (others => '1'); + wait until rising_edge(clk); + wait for 0 ns; + check_equal(q, std_logic_vector'(q'range => '1')); + + d <= (others => '0'); + wait until rising_edge(clk); + wait for 0 ns; + check_equal(q, 0); + end if; + end loop; + + test_runner_cleanup(runner); + end process; + + test_fixture : block is + begin + clk <= not clk after clk_period / 2; + + dut : dff + generic map( + width => width + ) + port map( + clk => clk, + reset => reset, + d => d, + q => q + ); + end block; +end architecture; diff --git a/examples/vhdl/vhdl_configuration/tb_selecting_test_runner_with_vhdl_configuration.vhd b/examples/vhdl/vhdl_configuration/tb_selecting_test_runner_with_vhdl_configuration.vhd new file mode 100644 index 000000000..6338e4fa6 --- /dev/null +++ b/examples/vhdl/vhdl_configuration/tb_selecting_test_runner_with_vhdl_configuration.vhd @@ -0,0 +1,78 @@ +-- This Source Code Form is subject to the terms of the Mozilla Public +-- License, v. 2.0. If a copy of the MPL was not distributed with this file, +-- You can obtain one at http://mozilla.org/MPL/2.0/. +-- +-- Copyright (c) 2014-2021, Lars Asplund lars.anders.asplund@gmail.com +-- +-- Description: This is an example of a testbench using separate architectures +-- of a test runner entity to define different tests. This is a structure +-- found in OSVVM-native testbenches + +library vunit_lib; +context vunit_lib.vunit_context; + +library ieee; +use ieee.std_logic_1164.all; + +entity tb_selecting_test_runner_with_vhdl_configuration is + -- VHDL doesn't support generics with VHDL configurations. + -- Assigning null_runner_cfg to runner_cfg will instruct + -- test_runner_setup to look for a runner.cfg file containing the + -- same information. Note that runner_cfg must remain present to + -- indicate that this is a testbench entity. + generic(runner_cfg : string := null_runner_cfg); +end entity; + +architecture tb of tb_selecting_test_runner_with_vhdl_configuration is + constant clk_period : time := 10 ns; + constant width : positive := 8; + + signal reset : std_logic; + signal clk : std_logic := '0'; + signal d : std_logic_vector(width - 1 downto 0); + signal q : std_logic_vector(width - 1 downto 0); + + component test_runner is + generic( + clk_period : time; + width : positive; + nested_runner_cfg : string + ); + port( + reset : out std_logic; + clk : in std_logic; + d : out std_logic_vector(width - 1 downto 0); + q : in std_logic_vector(width - 1 downto 0) + ); + end component; + +begin + test_runner_inst : test_runner + generic map( + clk_period => clk_period, + width => width, + nested_runner_cfg => runner_cfg + ) + port map( + reset => reset, + clk => clk, + d => d, + q => q + ); + + test_fixture : block is + begin + clk <= not clk after clk_period / 2; + + dut : entity work.dff(rtl) + generic map( + width => width + ) + port map( + clk => clk, + reset => reset, + d => d, + q => q + ); + end block; +end architecture; diff --git a/examples/vhdl/vhdl_configuration/test_reset.vhd b/examples/vhdl/vhdl_configuration/test_reset.vhd new file mode 100644 index 000000000..e6d355191 --- /dev/null +++ b/examples/vhdl/vhdl_configuration/test_reset.vhd @@ -0,0 +1,37 @@ +-- This Source Code Form is subject to the terms of the Mozilla Public +-- License, v. 2.0. If a copy of the MPL was not distributed with this file, +-- You can obtain one at http://mozilla.org/MPL/2.0/. +-- +-- Copyright (c) 2014-2021, Lars Asplund lars.anders.asplund@gmail.com + +library vunit_lib; +context vunit_lib.vunit_context; + +library ieee; +use ieee.std_logic_1164.all; + +architecture test_reset_a of test_runner is +begin + main : process + begin + test_runner_setup(runner, nested_runner_cfg); + + d <= (others => '1'); + reset <= '1'; + wait until rising_edge(clk); + wait for 0 ns; + check_equal(q, 0); + + test_runner_cleanup(runner); + end process; + + test_runner_watchdog(runner, 10 * clk_period); +end; + +configuration test_reset of tb_selecting_test_runner_with_vhdl_configuration is + for tb + for test_runner_inst : test_runner + use entity work.test_runner(test_reset_a); + end for; + end for; +end; diff --git a/examples/vhdl/vhdl_configuration/test_runner.vhd b/examples/vhdl/vhdl_configuration/test_runner.vhd new file mode 100644 index 000000000..95a0dfe41 --- /dev/null +++ b/examples/vhdl/vhdl_configuration/test_runner.vhd @@ -0,0 +1,22 @@ +-- This Source Code Form is subject to the terms of the Mozilla Public +-- License, v. 2.0. If a copy of the MPL was not distributed with this file, +-- You can obtain one at http://mozilla.org/MPL/2.0/. +-- +-- Copyright (c) 2014-2021, Lars Asplund lars.anders.asplund@gmail.com + +library ieee; +use ieee.std_logic_1164.all; + +entity test_runner is + generic( + clk_period : time; + width : positive; + nested_runner_cfg : string + ); + port( + reset : out std_logic; + clk : in std_logic; + d : out std_logic_vector(width - 1 downto 0); + q : in std_logic_vector(width - 1 downto 0) + ); +end entity; diff --git a/examples/vhdl/vhdl_configuration/test_state_change.vhd b/examples/vhdl/vhdl_configuration/test_state_change.vhd new file mode 100644 index 000000000..1c82b7455 --- /dev/null +++ b/examples/vhdl/vhdl_configuration/test_state_change.vhd @@ -0,0 +1,43 @@ +-- This Source Code Form is subject to the terms of the Mozilla Public +-- License, v. 2.0. If a copy of the MPL was not distributed with this file, +-- You can obtain one at http://mozilla.org/MPL/2.0/. +-- +-- Copyright (c) 2014-2021, Lars Asplund lars.anders.asplund@gmail.com + +library vunit_lib; +context vunit_lib.vunit_context; + +library ieee; +use ieee.std_logic_1164.all; + +architecture test_state_change_a of test_runner is +begin + main : process + begin + test_runner_setup(runner, nested_runner_cfg); + + reset <= '0'; + + d <= (others => '1'); + wait until rising_edge(clk); + wait for 0 ns; + check_equal(q, std_logic_vector'(q'range => '1')); + + d <= (others => '0'); + wait until rising_edge(clk); + wait for 0 ns; + check_equal(q, 0); + + test_runner_cleanup(runner); + end process; + + test_runner_watchdog(runner, 10 * clk_period); +end; + +configuration test_state_change of tb_selecting_test_runner_with_vhdl_configuration is + for tb + for test_runner_inst : test_runner + use entity work.test_runner(test_state_change_a); + end for; + end for; +end; diff --git a/tests/acceptance/test_external_run_scripts.py b/tests/acceptance/test_external_run_scripts.py index 8c5bbeacf..e38f9d704 100644 --- a/tests/acceptance/test_external_run_scripts.py +++ b/tests/acceptance/test_external_run_scripts.py @@ -176,6 +176,32 @@ def test_vhdl_composite_generics_example_project(self): ], ) + def test_vhdl_configuration_example_project(self): + self.check(ROOT / "examples/vhdl/vhdl_configuration/run.py") + check_report( + self.report_file, + [ + ("passed", "lib.tb_selecting_dut_with_vhdl_configuration.dff_rtl.Test reset"), + ("passed", "lib.tb_selecting_dut_with_vhdl_configuration.dff_behavioral.Test reset"), + ("passed", "lib.tb_selecting_dut_with_vhdl_configuration.dff_rtl.Test state change"), + ("passed", "lib.tb_selecting_dut_with_vhdl_configuration.dff_behavioral.Test state change"), + ("passed", "lib.tb_selecting_test_runner_with_vhdl_configuration.test_reset"), + ("passed", "lib.tb_selecting_test_runner_with_vhdl_configuration.test_state_change"), + ("passed", "lib.tb_reset.width=8"), + ("passed", "lib.tb_reset.width=32"), + ("passed", "lib.tb_selecting_dut_with_generate_statement.dff_rtl_width=8.Test reset"), + ("passed", "lib.tb_selecting_dut_with_generate_statement.dff_behavioral_width=8.Test reset"), + ("passed", "lib.tb_selecting_dut_with_generate_statement.dff_rtl_width=32.Test reset"), + ("passed", "lib.tb_selecting_dut_with_generate_statement.dff_behavioral_width=32.Test reset"), + ("passed", "lib.tb_selecting_dut_with_generate_statement.dff_rtl_width=8.Test state change"), + ("passed", "lib.tb_selecting_dut_with_generate_statement.dff_behavioral_width=8.Test state change"), + ("passed", "lib.tb_selecting_dut_with_generate_statement.dff_rtl_width=32.Test state change"), + ("passed", "lib.tb_selecting_dut_with_generate_statement.dff_behavioral_width=32.Test state change"), + ("passed", "lib.tb_state_change.width=8"), + ("passed", "lib.tb_state_change.width=32"), + ], + ) + @mark.skipif(not simulator_is("ghdl"), reason="Support complex JSON strings as generic") def test_vhdl_json4vhdl_example_project(self): self.check(ROOT / "examples/vhdl/json4vhdl/run.py")