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i-chip.html
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<!doctype html>
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<title>I-chip</title>
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<h2>Introduction</h2>
<p style=" text-align: left">Sponsored by: <img src="http://upload.wikimedia.org/wikipedia/commons/thumb/d/d4/Mentor_Graphics_Logo.svg/1280px-Mentor_Graphics_Logo.svg.png" height="150" width="400"/><br>
An HDL event: Now there is no need to manually place gates and transistors to build electronic circuits. Describe complex circuits at an abstract level in terms of functionality and data flow by designing those circuits in HDLs. This FPGA Design Contest requires one to write the code for the given problem statement in either VHDL or Verilog and optimize it, then dump the code on the FPGA Kit to physically realize the design that was coded.
</p>
<h2>
Problem Statement:
</h2>
<p style=" text-align: left">
<b>Edge and corner detection in a greyscale image.</b><br>
<b>Simulation (Use of MODELSIM is compulsory):-</b><br>
Participants have to detect edges and coordinates of the corners in any given greyscale image.<br>
An image will be provided in the form of a text file with the 2
bit hexadecimal value of each pixel (row wise) and the
participants have to output a text file(with binary values
representing the black and white image) which represents an
image with only the edges left from the original image.<br>
Also output the coordinates of the corners.<br>
<b>Synthesis :-</b> Particpants have to output the coordinates of
the corners on a 7 segment display. An image will be provided
in the form of a .coe file with the hexadecimal value of each
pixel (row wise) and the participants have to output the
coordinates of the corners on a 7 segment display at the
press of a button.<br>
Any HDL(VHDL/Verilog) can be used.
RTL design must be synthesizable and should be targeted for
FPGA technology Spartan3 (XC3S400).<br>
Pipelined designs are recommended.<br>
</p>
<h2>
Event Structure:
</h2>
<p style=" text-align: left">
Edge and corner detection in a greyscale image.<br>
There are 2 parts<br>
1) Simulation<br>
2) Synthesis<br>
</p>
<h2>
Judging Criteria:
</h2>
<p style=" text-align: left">
Accuracy.<br>
Run time (frequency of operation and latency).<br>
Resources used in the FPGA.<br>
The design must cover all aspects of problem statement and shows correct simulation for all test cases.<br>
</p>
<h2>
Contact Details:
</h2>
<div class="row" style="color: #302E39">
<div class="row">
<div class="col m3">Shubham Mantri</div>
<div class="col m6">[email protected]</div>
<div class="col m3">9455927695</div>
</div>
<div class="row">
<div class="col m3">Arnab Mondal</div>
<div class="col m6">[email protected]</div>
<div class="col m3">9628248855</div>
</div>
</div>
</div>
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