This repository contains the source code to read and edit the LUT contents of CLBs on the Virtex 5 and Zynq. Other architectures can probably be supported with minimal changes.
This serves as a replacement for the XHwIcap_GetClbBits and XHwIcap_SetClbBits functions provided by Xilinx.
To cite this work please use the following paper:
A. Kulkarni, T. Davidson, K. Heyse, and D.Stroobandt, "Improving reconfiguration speed for dynamic circuit specialization using placement constraints," in ReConFigurable Computing and FPGAs (ReConFig), 2014 International Conference on, 2014, pp. 1-6