From 82b076aa8570c217d67f583744948f3a5258e92c Mon Sep 17 00:00:00 2001
From: qarlosalberto <carlosruiznaranjo@gmail.com>
Date: Mon, 17 Jul 2023 19:32:25 +0200
Subject: [PATCH] chore: update version

---
 packages/teroshdl/auto_package/templates/info.nj             | 2 +-
 packages/teroshdl/package.json                               | 2 +-
 packages/teroshdl/resources/release_notes/release-notes.html | 3 ++-
 3 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/packages/teroshdl/auto_package/templates/info.nj b/packages/teroshdl/auto_package/templates/info.nj
index 3c8f13af..ab4e72ac 100644
--- a/packages/teroshdl/auto_package/templates/info.nj
+++ b/packages/teroshdl/auto_package/templates/info.nj
@@ -2,7 +2,7 @@
 "displayName": "TerosHDL",
 "publisher": "teros-technology",
 "description": "Powerful IDE for ASIC/FPGA: state machine viewer, linter, documentation, snippets... and more! ",
-"version": "5.0.4",
+"version": "5.0.5",
 "engines": {
     "vscode": "^1.74.0"
 },
diff --git a/packages/teroshdl/package.json b/packages/teroshdl/package.json
index aedfab78..a46d3b81 100644
--- a/packages/teroshdl/package.json
+++ b/packages/teroshdl/package.json
@@ -3,7 +3,7 @@
     "displayName": "TerosHDL",
     "publisher": "teros-technology",
     "description": "Powerful IDE for ASIC/FPGA: state machine viewer, linter, documentation, snippets... and more! ",
-    "version": "5.0.4",
+    "version": "5.0.5",
     "engines": {
         "vscode": "^1.74.0"
     },
diff --git a/packages/teroshdl/resources/release_notes/release-notes.html b/packages/teroshdl/resources/release_notes/release-notes.html
index 22d10772..7d4b67e8 100644
--- a/packages/teroshdl/resources/release_notes/release-notes.html
+++ b/packages/teroshdl/resources/release_notes/release-notes.html
@@ -33,13 +33,14 @@
     <br>
     <br>
 
-    <h4 id="release-notes"> Minor changes v5.0.4</h4>
+    <h4 id="release-notes"> Minor changes v5.0.4 and v5.0.5</h4>
     <p>
         <ul>
             <li> Support for GUI in VUnit</li>
             <li> Support for "copy as VHDL component" in Verilog/SV templates</li>
             <li> Fix bug parsing Verilog/SV arrays</li>
             <li> Fix bug updating VHDL libraries</li>
+            <li> Fix bug in linter when path has white space</li>
         </ul>
     </p>